[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / pci.c

/*
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/nl80211.h>
#include <linux/pci.h>
#include "ath9k.h"

static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
	{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E  AR9300 */
	{ 0 }
};

/* return bus cachesize in 4B word units */
static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	u8 u8tmp;

	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
	*csz = (int)u8tmp;

	/*
	 * This check was put in to avoid "unplesant" consequences if
	 * the bootrom has not fully initialized all PCI devices.
	 * Sometimes the cache line size register is not set
	 */

	if (*csz == 0)
		*csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
}

static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
{
	struct ath_hw *ah = (struct ath_hw *) common->ah;

	common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));

	if (!ath9k_hw_wait(ah,
			   AR_EEPROM_STATUS_DATA,
			   AR_EEPROM_STATUS_DATA_BUSY |
			   AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
			   AH_WAIT_TIMEOUT)) {
		return false;
	}

	*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
		   AR_EEPROM_STATUS_DATA_VAL);

	return true;
}

/*
 * Bluetooth coexistance requires disabling ASPM.
 */
static void ath_pci_bt_coex_prep(struct ath_common *common)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	struct pci_dev *pdev = to_pci_dev(sc->dev);
	u8 aspm;

	if (!pdev->is_pcie)
		return;

	pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
	aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
	pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
}

static const struct ath_bus_ops ath_pci_bus_ops = {
	.ath_bus_type = ATH_PCI,
	.read_cachesize = ath_pci_read_cachesize,
	.eeprom_read = ath_pci_eeprom_read,
	.bt_coex_prep = ath_pci_bt_coex_prep,
};

static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	void __iomem *mem;
	struct ath_wiphy *aphy;
	struct ath_softc *sc;
	struct ieee80211_hw *hw;
	u8 csz;
	u16 subsysid;
	u32 val;
	int ret = 0;
	char hw_name[64];

	if (pci_enable_device(pdev))
		return -EIO;

	ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
		printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
		goto err_dma;
	}

	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
		printk(KERN_ERR "ath9k: 32-bit DMA consistent "
			"DMA enable failed\n");
		goto err_dma;
	}

	/*
	 * Cache line size is used to size and align various
	 * structures used to communicate with the hardware.
	 */
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	if (csz == 0) {
		/*
		 * Linux 2.4.18 (at least) writes the cache line size
		 * register as a 16-bit wide register which is wrong.
		 * We must have this setup properly for rx buffer
		 * DMA to work so force a reasonable value here if it
		 * comes up zero.
		 */
		csz = L1_CACHE_BYTES / sizeof(u32);
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	}
	/*
	 * The default setting of latency timer yields poor results,
	 * set it to the value used by other systems. It may be worth
	 * tweaking this setting more.
	 */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);

	pci_set_master(pdev);

	/*
	 * Disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state.
	 */
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	ret = pci_request_region(pdev, 0, "ath9k");
	if (ret) {
		dev_err(&pdev->dev, "PCI memory region reserve error\n");
		ret = -ENODEV;
		goto err_region;
	}

	mem = pci_iomap(pdev, 0, 0);
	if (!mem) {
		printk(KERN_ERR "PCI memory map error\n") ;
		ret = -EIO;
		goto err_iomap;
	}

	hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
				sizeof(struct ath_softc), &ath9k_ops);
	if (!hw) {
		dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
		ret = -ENOMEM;
		goto err_alloc_hw;
	}

	SET_IEEE80211_DEV(hw, &pdev->dev);
	pci_set_drvdata(pdev, hw);

	aphy = hw->priv;
	sc = (struct ath_softc *) (aphy + 1);
	aphy->sc = sc;
	aphy->hw = hw;
	sc->pri_wiphy = aphy;
	sc->hw = hw;
	sc->dev = &pdev->dev;
	sc->mem = mem;

	/* Will be cleared in ath9k_start() */
	sc->sc_flags |= SC_OP_INVALID;

	ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
	if (ret) {
		dev_err(&pdev->dev, "request_irq failed\n");
		goto err_irq;
	}

	sc->irq = pdev->irq;

	pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
	ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
	if (ret) {
		dev_err(&pdev->dev, "Failed to initialize device\n");
		goto err_init;
	}

	ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
	printk(KERN_INFO
	       "%s: %s mem=0x%lx, irq=%d\n",
	       wiphy_name(hw->wiphy),
	       hw_name,
	       (unsigned long)mem, pdev->irq);

	return 0;

err_init:
	free_irq(sc->irq, sc);
err_irq:
	ieee80211_free_hw(hw);
err_alloc_hw:
	pci_iounmap(pdev, mem);
err_iomap:
	pci_release_region(pdev, 0);
err_region:
	/* Nothing */
err_dma:
	pci_disable_device(pdev);
	return ret;
}

static void ath_pci_remove(struct pci_dev *pdev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
	void __iomem *mem = sc->mem;

	ath9k_deinit_device(sc);
	free_irq(sc->irq, sc);
	ieee80211_free_hw(sc->hw);

	pci_iounmap(pdev, mem);
	pci_disable_device(pdev);
	pci_release_region(pdev, 0);
}

#ifdef CONFIG_PM

static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;

	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);

	pci_save_state(pdev);
	pci_disable_device(pdev);
	pci_set_power_state(pdev, PCI_D3hot);

	return 0;
}

static int ath_pci_resume(struct pci_dev *pdev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
	u32 val;
	int err;

	pci_restore_state(pdev);

	err = pci_enable_device(pdev);
	if (err)
		return err;

	/*
	 * Suspend/Resume resets the PCI configuration space, so we have to
	 * re-disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state
	 */
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	/* Enable LED */
	ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
			    AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);

	return 0;
}

#endif /* CONFIG_PM */

MODULE_DEVICE_TABLE(pci, ath_pci_id_table);

static struct pci_driver ath_pci_driver = {
	.name       = "ath9k",
	.id_table   = ath_pci_id_table,
	.probe      = ath_pci_probe,
	.remove     = ath_pci_remove,
#ifdef CONFIG_PM
	.suspend    = ath_pci_suspend,
	.resume     = ath_pci_resume,
#endif /* CONFIG_PM */
};

int ath_pci_init(void)
{
	return pci_register_driver(&ath_pci_driver);
}

void ath_pci_exit(void)
{
	pci_unregister_driver(&ath_pci_driver);
}
Commit	Line	Data
6baff7f9	1	/*
cee075a2	2	* Copyright (c) 2008-2009 Atheros Communications Inc.
6baff7f9 GJ	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#include <linux/nl80211.h>
	18	#include <linux/pci.h>
394cf0a1	19	#include "ath9k.h"
6baff7f9	20
a3aa1884	21	static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
6baff7f9 GJ	22	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
	23	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
	24	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
	25	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
	26	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
	27	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
5ffaf8a3	28	{ PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
ac88b6ec VN	29	{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
ac88b6ec VN	30	{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
733f0ea4	31	{ PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
6baff7f9 GJ	32	{ 0 }
	33	};
	34
	35	/* return bus cachesize in 4B word units */
5bb12791	36	static void ath_pci_read_cachesize(struct ath_common common, int csz)
6baff7f9	37	{
bc974f4a	38	struct ath_softc sc = (struct ath_softc ) common->priv;
6baff7f9 GJ	39	u8 u8tmp;
6baff7f9 GJ	40
f020979d	41	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
6baff7f9 GJ	42	*csz = (int)u8tmp;
	43
	44	/*
	45	* This check was put in to avoid "unplesant" consequences if
	46	* the bootrom has not fully initialized all PCI devices.
	47	* Sometimes the cache line size register is not set
	48	*/
	49
	50	if (*csz == 0)
	51	csz = DEFAULT_CACHELINE >> 2; / Use the default size */
	52	}
	53
5bb12791	54	static bool ath_pci_eeprom_read(struct ath_common common, u32 off, u16 data)
9dbeb91a	55	{
5bb12791 LR	56	struct ath_hw ah = (struct ath_hw ) common->ah;
5bb12791 LR	57
475a6e4d	58	common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
9dbeb91a GJ	59
	60	if (!ath9k_hw_wait(ah,
	61	AR_EEPROM_STATUS_DATA,
	62	AR_EEPROM_STATUS_DATA_BUSY \|
0caa7b14 S	63	AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
0caa7b14 S	64	AH_WAIT_TIMEOUT)) {
9dbeb91a GJ	65	return false;
	66	}
	67
475a6e4d	68	*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
9dbeb91a GJ	69	AR_EEPROM_STATUS_DATA_VAL);
	70
	71	return true;
	72	}
	73
867633f0 LR	74	/*
	75	* Bluetooth coexistance requires disabling ASPM.
	76	*/
5bb12791	77	static void ath_pci_bt_coex_prep(struct ath_common *common)
867633f0	78	{
bc974f4a	79	struct ath_softc sc = (struct ath_softc ) common->priv;
867633f0 LR	80	struct pci_dev *pdev = to_pci_dev(sc->dev);
	81	u8 aspm;
	82
	83	if (!pdev->is_pcie)
	84	return;
	85
	86	pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
	87	aspm &= ~(ATH_PCIE_CAP_LINK_L0S \| ATH_PCIE_CAP_LINK_L1);
	88	pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
	89	}
	90
83bd11a0	91	static const struct ath_bus_ops ath_pci_bus_ops = {
497ad9ad	92	.ath_bus_type = ATH_PCI,
6baff7f9	93	.read_cachesize = ath_pci_read_cachesize,
9dbeb91a	94	.eeprom_read = ath_pci_eeprom_read,
867633f0	95	.bt_coex_prep = ath_pci_bt_coex_prep,
6baff7f9 GJ	96	};
	97
	98	static int ath_pci_probe(struct pci_dev pdev, const struct pci_device_id id)
	99	{
	100	void __iomem *mem;
bce048d7	101	struct ath_wiphy *aphy;
6baff7f9 GJ	102	struct ath_softc *sc;
	103	struct ieee80211_hw *hw;
	104	u8 csz;
aeac355d	105	u16 subsysid;
f0214843	106	u32 val;
6baff7f9	107	int ret = 0;
f934c4d9	108	char hw_name[64];
6baff7f9 GJ	109
	110	if (pci_enable_device(pdev))
	111	return -EIO;
	112
e930438c	113	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6baff7f9 GJ	114	if (ret) {
6baff7f9 GJ	115	printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
285f2dda	116	goto err_dma;
6baff7f9 GJ	117	}
6baff7f9 GJ	118
e930438c	119	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6baff7f9 GJ	120	if (ret) {
	121	printk(KERN_ERR "ath9k: 32-bit DMA consistent "
	122	"DMA enable failed\n");
285f2dda	123	goto err_dma;
6baff7f9 GJ	124	}
	125
	126	/*
	127	* Cache line size is used to size and align various
	128	* structures used to communicate with the hardware.
	129	*/
	130	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	131	if (csz == 0) {
	132	/*
	133	* Linux 2.4.18 (at least) writes the cache line size
	134	* register as a 16-bit wide register which is wrong.
	135	* We must have this setup properly for rx buffer
	136	* DMA to work so force a reasonable value here if it
	137	* comes up zero.
	138	*/
	139	csz = L1_CACHE_BYTES / sizeof(u32);
	140	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	141	}
	142	/*
	143	* The default setting of latency timer yields poor results,
	144	* set it to the value used by other systems. It may be worth
	145	* tweaking this setting more.
	146	*/
	147	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
	148
	149	pci_set_master(pdev);
	150
f0214843 JM	151	/*
	152	* Disable the RETRY_TIMEOUT register (0x41) to keep
	153	* PCI Tx retries from interfering with C3 CPU state.
	154	*/
	155	pci_read_config_dword(pdev, 0x40, &val);
	156	if ((val & 0x0000ff00) != 0)
	157	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
	158
6baff7f9 GJ	159	ret = pci_request_region(pdev, 0, "ath9k");
	160	if (ret) {
	161	dev_err(&pdev->dev, "PCI memory region reserve error\n");
	162	ret = -ENODEV;
285f2dda	163	goto err_region;
6baff7f9 GJ	164	}
	165
	166	mem = pci_iomap(pdev, 0, 0);
	167	if (!mem) {
	168	printk(KERN_ERR "PCI memory map error\n") ;
	169	ret = -EIO;
285f2dda	170	goto err_iomap;
6baff7f9 GJ	171	}
6baff7f9 GJ	172
bce048d7 JM	173	hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
bce048d7 JM	174	sizeof(struct ath_softc), &ath9k_ops);
db6be53c	175	if (!hw) {
285f2dda	176	dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
db6be53c	177	ret = -ENOMEM;
285f2dda	178	goto err_alloc_hw;
6baff7f9 GJ	179	}
	180
	181	SET_IEEE80211_DEV(hw, &pdev->dev);
	182	pci_set_drvdata(pdev, hw);
	183
bce048d7 JM	184	aphy = hw->priv;
	185	sc = (struct ath_softc *) (aphy + 1);
	186	aphy->sc = sc;
	187	aphy->hw = hw;
	188	sc->pri_wiphy = aphy;
6baff7f9 GJ	189	sc->hw = hw;
	190	sc->dev = &pdev->dev;
	191	sc->mem = mem;
6baff7f9	192
5e4ea1f0 S	193	/* Will be cleared in ath9k_start() */
5e4ea1f0 S	194	sc->sc_flags \|= SC_OP_INVALID;
6baff7f9	195
fc548af8	196	ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
580171f7 LR	197	if (ret) {
580171f7 LR	198	dev_err(&pdev->dev, "request_irq failed\n");
285f2dda	199	goto err_irq;
6baff7f9 GJ	200	}
	201
	202	sc->irq = pdev->irq;
	203
285f2dda S	204	pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
	205	ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
	206	if (ret) {
	207	dev_err(&pdev->dev, "Failed to initialize device\n");
	208	goto err_init;
	209	}
	210
	211	ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
6baff7f9	212	printk(KERN_INFO
f934c4d9	213	"%s: %s mem=0x%lx, irq=%d\n",
6baff7f9	214	wiphy_name(hw->wiphy),
f934c4d9	215	hw_name,
6baff7f9 GJ	216	(unsigned long)mem, pdev->irq);
	217
	218	return 0;
285f2dda S	219
	220	err_init:
	221	free_irq(sc->irq, sc);
	222	err_irq:
6baff7f9	223	ieee80211_free_hw(hw);
285f2dda	224	err_alloc_hw:
6baff7f9	225	pci_iounmap(pdev, mem);
285f2dda	226	err_iomap:
6baff7f9	227	pci_release_region(pdev, 0);
285f2dda S	228	err_region:
	229	/* Nothing */
	230	err_dma:
6baff7f9 GJ	231	pci_disable_device(pdev);
	232	return ret;
	233	}
	234
	235	static void ath_pci_remove(struct pci_dev *pdev)
	236	{
	237	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
bce048d7 JM	238	struct ath_wiphy *aphy = hw->priv;
bce048d7 JM	239	struct ath_softc *sc = aphy->sc;
ab5132a2	240	void __iomem *mem = sc->mem;
6baff7f9	241
285f2dda S	242	ath9k_deinit_device(sc);
	243	free_irq(sc->irq, sc);
	244	ieee80211_free_hw(sc->hw);
ab5132a2 PR	245
	246	pci_iounmap(pdev, mem);
	247	pci_disable_device(pdev);
	248	pci_release_region(pdev, 0);
6baff7f9 GJ	249	}
	250
	251	#ifdef CONFIG_PM
	252
	253	static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
	254	{
	255	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
bce048d7 JM	256	struct ath_wiphy *aphy = hw->priv;
bce048d7 JM	257	struct ath_softc *sc = aphy->sc;
6baff7f9	258
08fc5c1b	259	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
6baff7f9	260
6baff7f9 GJ	261	pci_save_state(pdev);
	262	pci_disable_device(pdev);
	263	pci_set_power_state(pdev, PCI_D3hot);
	264
	265	return 0;
	266	}
	267
	268	static int ath_pci_resume(struct pci_dev *pdev)
	269	{
	270	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
bce048d7 JM	271	struct ath_wiphy *aphy = hw->priv;
bce048d7 JM	272	struct ath_softc *sc = aphy->sc;
f0214843	273	u32 val;
6baff7f9 GJ	274	int err;
6baff7f9 GJ	275
523c36fc S	276	pci_restore_state(pdev);
523c36fc S	277
6baff7f9 GJ	278	err = pci_enable_device(pdev);
	279	if (err)
	280	return err;
523c36fc	281
f0214843 JM	282	/*
	283	* Suspend/Resume resets the PCI configuration space, so we have to
	284	* re-disable the RETRY_TIMEOUT register (0x41) to keep
	285	* PCI Tx retries from interfering with C3 CPU state
	286	*/
	287	pci_read_config_dword(pdev, 0x40, &val);
	288	if ((val & 0x0000ff00) != 0)
	289	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
6baff7f9 GJ	290
6baff7f9 GJ	291	/* Enable LED */
08fc5c1b	292	ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
6baff7f9	293	AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b	294	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
6baff7f9	295
6baff7f9 GJ	296	return 0;
	297	}
	298
	299	#endif /* CONFIG_PM */
	300
	301	MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
	302
	303	static struct pci_driver ath_pci_driver = {
	304	.name = "ath9k",
	305	.id_table = ath_pci_id_table,
	306	.probe = ath_pci_probe,
	307	.remove = ath_pci_remove,
	308	#ifdef CONFIG_PM
	309	.suspend = ath_pci_suspend,
	310	.resume = ath_pci_resume,
	311	#endif /* CONFIG_PM */
	312	};
	313
db0f41f5	314	int ath_pci_init(void)
6baff7f9 GJ	315	{
	316	return pci_register_driver(&ath_pci_driver);
	317	}
	318
	319	void ath_pci_exit(void)
	320	{
	321	pci_unregister_driver(&ath_pci_driver);
	322	}