[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / pci.c

/*
 * Copyright (c) 2008-2011 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/nl80211.h>
#include <linux/pci.h>
#include <linux/pci-aspm.h>
#include <linux/ath9k_platform.h>
#include <linux/module.h>
#include "ath9k.h"

static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
	{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E  AR9300 */

	/* PCI-E CUS198 */
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0032,
			 PCI_VENDOR_ID_AZWAVE,
			 0x2086),
	  .driver_data = ATH9K_PCI_CUS198 },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0032,
			 PCI_VENDOR_ID_AZWAVE,
			 0x1237),
	  .driver_data = ATH9K_PCI_CUS198 },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0032,
			 PCI_VENDOR_ID_AZWAVE,
			 0x2126),
	  .driver_data = ATH9K_PCI_CUS198 },

	/* PCI-E CUS230 */
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0032,
			 PCI_VENDOR_ID_AZWAVE,
			 0x2152),
	  .driver_data = ATH9K_PCI_CUS230 },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0032,
			 PCI_VENDOR_ID_FOXCONN,
			 0xE075),
	  .driver_data = ATH9K_PCI_CUS230 },

	{ PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E  AR9485 */
	{ PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E  AR9580 */

	/* PCI-E CUS217 */
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0034,
			 PCI_VENDOR_ID_AZWAVE,
			 0x2116),
	  .driver_data = ATH9K_PCI_CUS217 },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0034,
			 0x11AD, /* LITEON */
			 0x6661),
	  .driver_data = ATH9K_PCI_CUS217 },

	/* AR9462 with WoW support */
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0034,
			 PCI_VENDOR_ID_ATHEROS,
			 0x3117),
	  .driver_data = ATH9K_PCI_WOW },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0034,
			 PCI_VENDOR_ID_LENOVO,
			 0x3214),
	  .driver_data = ATH9K_PCI_WOW },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0034,
			 PCI_VENDOR_ID_ATTANSIC,
			 0x0091),
	  .driver_data = ATH9K_PCI_WOW },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0034,
			 PCI_VENDOR_ID_AZWAVE,
			 0x2110),
	  .driver_data = ATH9K_PCI_WOW },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0034,
			 PCI_VENDOR_ID_ASUSTEK,
			 0x850E),
	  .driver_data = ATH9K_PCI_WOW },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0034,
			 0x11AD, /* LITEON */
			 0x6631),
	  .driver_data = ATH9K_PCI_WOW },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0034,
			 0x11AD, /* LITEON */
			 0x6641),
	  .driver_data = ATH9K_PCI_WOW },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0034,
			 PCI_VENDOR_ID_HP,
			 0x1864),
	  .driver_data = ATH9K_PCI_WOW },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0034,
			 0x14CD, /* USI */
			 0x0063),
	  .driver_data = ATH9K_PCI_WOW },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0034,
			 0x14CD, /* USI */
			 0x0064),
	  .driver_data = ATH9K_PCI_WOW },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
			 0x0034,
			 0x10CF, /* Fujitsu */
			 0x1783),
	  .driver_data = ATH9K_PCI_WOW },

	{ PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E  AR9462 */
	{ PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E  AR1111/AR9485 */
	{ PCI_VDEVICE(ATHEROS, 0x0036) }, /* PCI-E  AR9565 */
	{ 0 }
};


/* return bus cachesize in 4B word units */
static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	u8 u8tmp;

	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
	*csz = (int)u8tmp;

	/*
	 * This check was put in to avoid "unpleasant" consequences if
	 * the bootrom has not fully initialized all PCI devices.
	 * Sometimes the cache line size register is not set
	 */

	if (*csz == 0)
		*csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
}

static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	struct ath9k_platform_data *pdata = sc->dev->platform_data;

	if (pdata) {
		if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
			ath_err(common,
				"%s: eeprom read failed, offset %08x is out of range\n",
				__func__, off);
		}

		*data = pdata->eeprom_data[off];
	} else {
		struct ath_hw *ah = (struct ath_hw *) common->ah;

		common->ops->read(ah, AR5416_EEPROM_OFFSET +
				      (off << AR5416_EEPROM_S));

		if (!ath9k_hw_wait(ah,
				   AR_EEPROM_STATUS_DATA,
				   AR_EEPROM_STATUS_DATA_BUSY |
				   AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
				   AH_WAIT_TIMEOUT)) {
			return false;
		}

		*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
			   AR_EEPROM_STATUS_DATA_VAL);
	}

	return true;
}

/* Need to be called after we discover btcoex capabilities */
static void ath_pci_aspm_init(struct ath_common *common)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	struct ath_hw *ah = sc->sc_ah;
	struct pci_dev *pdev = to_pci_dev(sc->dev);
	struct pci_dev *parent;
	u16 aspm;

	if (!ah->is_pciexpress)
		return;

	parent = pdev->bus->self;
	if (!parent)
		return;

	if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) &&
	    (AR_SREV_9285(ah))) {
		/* Bluetooth coexistence requires disabling ASPM. */
		pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
			PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);

		/*
		 * Both upstream and downstream PCIe components should
		 * have the same ASPM settings.
		 */
		pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
			PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);

		ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
		return;
	}

	pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
	if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) {
		ah->aspm_enabled = true;
		/* Initialize PCIe PM and SERDES registers. */
		ath9k_hw_configpcipowersave(ah, false);
		ath_info(common, "ASPM enabled: 0x%x\n", aspm);
	}
}

static const struct ath_bus_ops ath_pci_bus_ops = {
	.ath_bus_type = ATH_PCI,
	.read_cachesize = ath_pci_read_cachesize,
	.eeprom_read = ath_pci_eeprom_read,
	.aspm_init = ath_pci_aspm_init,
};

static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	struct ath_softc *sc;
	struct ieee80211_hw *hw;
	u8 csz;
	u32 val;
	int ret = 0;
	char hw_name[64];

	if (pcim_enable_device(pdev))
		return -EIO;

	ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
		pr_err("32-bit DMA not available\n");
		return ret;
	}

	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
		pr_err("32-bit DMA consistent DMA enable failed\n");
		return ret;
	}

	/*
	 * Cache line size is used to size and align various
	 * structures used to communicate with the hardware.
	 */
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	if (csz == 0) {
		/*
		 * Linux 2.4.18 (at least) writes the cache line size
		 * register as a 16-bit wide register which is wrong.
		 * We must have this setup properly for rx buffer
		 * DMA to work so force a reasonable value here if it
		 * comes up zero.
		 */
		csz = L1_CACHE_BYTES / sizeof(u32);
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	}
	/*
	 * The default setting of latency timer yields poor results,
	 * set it to the value used by other systems. It may be worth
	 * tweaking this setting more.
	 */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);

	pci_set_master(pdev);

	/*
	 * Disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state.
	 */
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	ret = pcim_iomap_regions(pdev, BIT(0), "ath9k");
	if (ret) {
		dev_err(&pdev->dev, "PCI memory region reserve error\n");
		return -ENODEV;
	}

	hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
	if (!hw) {
		dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
		return -ENOMEM;
	}

	SET_IEEE80211_DEV(hw, &pdev->dev);
	pci_set_drvdata(pdev, hw);

	sc = hw->priv;
	sc->hw = hw;
	sc->dev = &pdev->dev;
	sc->mem = pcim_iomap_table(pdev)[0];
	sc->driver_data = id->driver_data;

	/* Will be cleared in ath9k_start() */
	set_bit(SC_OP_INVALID, &sc->sc_flags);

	ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
	if (ret) {
		dev_err(&pdev->dev, "request_irq failed\n");
		goto err_irq;
	}

	sc->irq = pdev->irq;

	ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops);
	if (ret) {
		dev_err(&pdev->dev, "Failed to initialize device\n");
		goto err_init;
	}

	ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
	wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
		   hw_name, (unsigned long)sc->mem, pdev->irq);

	return 0;

err_init:
	free_irq(sc->irq, sc);
err_irq:
	ieee80211_free_hw(hw);
	return ret;
}

static void ath_pci_remove(struct pci_dev *pdev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_softc *sc = hw->priv;

	if (!is_ath9k_unloaded)
		sc->sc_ah->ah_flags |= AH_UNPLUGGED;
	ath9k_deinit_device(sc);
	free_irq(sc->irq, sc);
	ieee80211_free_hw(sc->hw);
}

#ifdef CONFIG_PM_SLEEP

static int ath_pci_suspend(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_softc *sc = hw->priv;

	if (sc->wow_enabled)
		return 0;

	/* The device has to be moved to FULLSLEEP forcibly.
	 * Otherwise the chip never moved to full sleep,
	 * when no interface is up.
	 */
	ath9k_stop_btcoex(sc);
	ath9k_hw_disable(sc->sc_ah);
	ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);

	return 0;
}

static int ath_pci_resume(struct device *device)
{
	struct pci_dev *pdev = to_pci_dev(device);
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_softc *sc = hw->priv;
	struct ath_hw *ah = sc->sc_ah;
	struct ath_common *common = ath9k_hw_common(ah);
	u32 val;

	/*
	 * Suspend/Resume resets the PCI configuration space, so we have to
	 * re-disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state
	 */
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	ath_pci_aspm_init(common);
	ah->reset_power_on = false;

	return 0;
}

static SIMPLE_DEV_PM_OPS(ath9k_pm_ops, ath_pci_suspend, ath_pci_resume);

#define ATH9K_PM_OPS	(&ath9k_pm_ops)

#else /* !CONFIG_PM_SLEEP */

#define ATH9K_PM_OPS	NULL

#endif /* !CONFIG_PM_SLEEP */


MODULE_DEVICE_TABLE(pci, ath_pci_id_table);

static struct pci_driver ath_pci_driver = {
	.name       = "ath9k",
	.id_table   = ath_pci_id_table,
	.probe      = ath_pci_probe,
	.remove     = ath_pci_remove,
	.driver.pm  = ATH9K_PM_OPS,
};

int ath_pci_init(void)
{
	return pci_register_driver(&ath_pci_driver);
}

void ath_pci_exit(void)
{
	pci_unregister_driver(&ath_pci_driver);
}
Commit	Line	Data
6baff7f9	1	/*
5b68138e	2	* Copyright (c) 2008-2011 Atheros Communications Inc.
6baff7f9 GJ	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
516304b0 JP	17	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
516304b0 JP	18
6baff7f9 GJ	19	#include <linux/nl80211.h>
6baff7f9 GJ	20	#include <linux/pci.h>
d4930086	21	#include <linux/pci-aspm.h>
a05b5d45	22	#include <linux/ath9k_platform.h>
9d9779e7	23	#include <linux/module.h>
394cf0a1	24	#include "ath9k.h"
6baff7f9	25
a3aa1884	26	static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
6baff7f9 GJ	27	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
	28	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
	29	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
	30	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
	31	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
	32	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
5ffaf8a3	33	{ PCI_VDEVICE(ATHEROS, 0x002C) }, /* PCI-E 802.11n bonded out */
ac88b6ec VN	34	{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
ac88b6ec VN	35	{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
0efabd51	36	{ PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E AR9300 */
9b60b64b SM	37
	38	/* PCI-E CUS198 */
	39	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	40	0x0032,
	41	PCI_VENDOR_ID_AZWAVE,
	42	0x2086),
	43	.driver_data = ATH9K_PCI_CUS198 },
	44	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	45	0x0032,
	46	PCI_VENDOR_ID_AZWAVE,
	47	0x1237),
	48	.driver_data = ATH9K_PCI_CUS198 },
	49	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	50	0x0032,
	51	PCI_VENDOR_ID_AZWAVE,
	52	0x2126),
	53	.driver_data = ATH9K_PCI_CUS198 },
e861ef52 SM	54
e861ef52 SM	55	/* PCI-E CUS230 */
9b60b64b SM	56	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	57	0x0032,
	58	PCI_VENDOR_ID_AZWAVE,
	59	0x2152),
e861ef52	60	.driver_data = ATH9K_PCI_CUS230 },
9b60b64b SM	61	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	62	0x0032,
	63	PCI_VENDOR_ID_FOXCONN,
	64	0xE075),
e861ef52	65	.driver_data = ATH9K_PCI_CUS230 },
9b60b64b	66
1435894d	67	{ PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E AR9485 */
a508a6ea	68	{ PCI_VDEVICE(ATHEROS, 0x0033) }, /* PCI-E AR9580 */
12eea640 SM	69
	70	/* PCI-E CUS217 */
	71	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	72	0x0034,
	73	PCI_VENDOR_ID_AZWAVE,
	74	0x2116),
	75	.driver_data = ATH9K_PCI_CUS217 },
	76	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	77	0x0034,
	78	0x11AD, /* LITEON */
	79	0x6661),
	80	.driver_data = ATH9K_PCI_CUS217 },
	81
fca3c21d SM	82	/* AR9462 with WoW support */
	83	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	84	0x0034,
	85	PCI_VENDOR_ID_ATHEROS,
	86	0x3117),
	87	.driver_data = ATH9K_PCI_WOW },
	88	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	89	0x0034,
	90	PCI_VENDOR_ID_LENOVO,
	91	0x3214),
	92	.driver_data = ATH9K_PCI_WOW },
	93	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	94	0x0034,
	95	PCI_VENDOR_ID_ATTANSIC,
	96	0x0091),
	97	.driver_data = ATH9K_PCI_WOW },
	98	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	99	0x0034,
	100	PCI_VENDOR_ID_AZWAVE,
	101	0x2110),
	102	.driver_data = ATH9K_PCI_WOW },
	103	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	104	0x0034,
	105	PCI_VENDOR_ID_ASUSTEK,
	106	0x850E),
	107	.driver_data = ATH9K_PCI_WOW },
	108	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	109	0x0034,
	110	0x11AD, /* LITEON */
	111	0x6631),
	112	.driver_data = ATH9K_PCI_WOW },
	113	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	114	0x0034,
	115	0x11AD, /* LITEON */
	116	0x6641),
	117	.driver_data = ATH9K_PCI_WOW },
	118	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	119	0x0034,
	120	PCI_VENDOR_ID_HP,
	121	0x1864),
	122	.driver_data = ATH9K_PCI_WOW },
	123	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	124	0x0034,
	125	0x14CD, /* USI */
	126	0x0063),
	127	.driver_data = ATH9K_PCI_WOW },
	128	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	129	0x0034,
	130	0x14CD, /* USI */
	131	0x0064),
	132	.driver_data = ATH9K_PCI_WOW },
	133	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_ATHEROS,
	134	0x0034,
	135	0x10CF, /* Fujitsu */
	136	0x1783),
	137	.driver_data = ATH9K_PCI_WOW },
	138
423e38e8	139	{ PCI_VDEVICE(ATHEROS, 0x0034) }, /* PCI-E AR9462 */
d4e5979c	140	{ PCI_VDEVICE(ATHEROS, 0x0037) }, /* PCI-E AR1111/AR9485 */
0c8070f9	141	{ PCI_VDEVICE(ATHEROS, 0x0036) }, /* PCI-E AR9565 */
6baff7f9 GJ	142	{ 0 }
	143	};
	144
84c87dc8	145
6baff7f9	146	/* return bus cachesize in 4B word units */
5bb12791	147	static void ath_pci_read_cachesize(struct ath_common common, int csz)
6baff7f9	148	{
bc974f4a	149	struct ath_softc sc = (struct ath_softc ) common->priv;
6baff7f9 GJ	150	u8 u8tmp;
6baff7f9 GJ	151
f020979d	152	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
6baff7f9 GJ	153	*csz = (int)u8tmp;
	154
	155	/*
25985edc	156	* This check was put in to avoid "unpleasant" consequences if
6baff7f9 GJ	157	* the bootrom has not fully initialized all PCI devices.
	158	* Sometimes the cache line size register is not set
	159	*/
	160
	161	if (*csz == 0)
	162	csz = DEFAULT_CACHELINE >> 2; / Use the default size */
	163	}
	164
5bb12791	165	static bool ath_pci_eeprom_read(struct ath_common common, u32 off, u16 data)
9dbeb91a	166	{
a05b5d45 FF	167	struct ath_softc sc = (struct ath_softc ) common->priv;
	168	struct ath9k_platform_data *pdata = sc->dev->platform_data;
	169
	170	if (pdata) {
	171	if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
3800276a JP	172	ath_err(common,
	173	"%s: eeprom read failed, offset %08x is out of range\n",
	174	__func__, off);
a05b5d45 FF	175	}
	176
	177	*data = pdata->eeprom_data[off];
	178	} else {
	179	struct ath_hw ah = (struct ath_hw ) common->ah;
	180
	181	common->ops->read(ah, AR5416_EEPROM_OFFSET +
	182	(off << AR5416_EEPROM_S));
	183
	184	if (!ath9k_hw_wait(ah,
	185	AR_EEPROM_STATUS_DATA,
	186	AR_EEPROM_STATUS_DATA_BUSY \|
	187	AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
	188	AH_WAIT_TIMEOUT)) {
	189	return false;
	190	}
	191
	192	*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
	193	AR_EEPROM_STATUS_DATA_VAL);
9dbeb91a GJ	194	}
9dbeb91a GJ	195
9dbeb91a GJ	196	return true;
	197	}
	198
69ce674b	199	/* Need to be called after we discover btcoex capabilities */
d4930086 SG	200	static void ath_pci_aspm_init(struct ath_common *common)
	201	{
	202	struct ath_softc sc = (struct ath_softc ) common->priv;
	203	struct ath_hw *ah = sc->sc_ah;
	204	struct pci_dev *pdev = to_pci_dev(sc->dev);
	205	struct pci_dev *parent;
08bd1080	206	u16 aspm;
d4930086	207
d09f5f4c SM	208	if (!ah->is_pciexpress)
	209	return;
	210
d4930086	211	parent = pdev->bus->self;
22c55e6e JL	212	if (!parent)
22c55e6e JL	213	return;
69ce674b	214
046b6802 SM	215	if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) &&
046b6802 SM	216	(AR_SREV_9285(ah))) {
a875621e	217	/* Bluetooth coexistence requires disabling ASPM. */
08bd1080	218	pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
a875621e	219	PCI_EXP_LNKCTL_ASPM_L0S \| PCI_EXP_LNKCTL_ASPM_L1);
69ce674b SG	220
	221	/*
	222	* Both upstream and downstream PCIe components should
	223	* have the same ASPM settings.
	224	*/
08bd1080	225	pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
a875621e	226	PCI_EXP_LNKCTL_ASPM_L0S \| PCI_EXP_LNKCTL_ASPM_L1);
69ce674b	227
d09f5f4c	228	ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
69ce674b SG	229	return;
	230	}
	231
08bd1080	232	pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
a875621e	233	if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S \| PCI_EXP_LNKCTL_ASPM_L1)) {
d4930086 SG	234	ah->aspm_enabled = true;
d4930086 SG	235	/* Initialize PCIe PM and SERDES registers. */
84c87dc8	236	ath9k_hw_configpcipowersave(ah, false);
d09f5f4c	237	ath_info(common, "ASPM enabled: 0x%x\n", aspm);
d4930086 SG	238	}
	239	}
	240
83bd11a0	241	static const struct ath_bus_ops ath_pci_bus_ops = {
497ad9ad	242	.ath_bus_type = ATH_PCI,
6baff7f9	243	.read_cachesize = ath_pci_read_cachesize,
9dbeb91a	244	.eeprom_read = ath_pci_eeprom_read,
d4930086	245	.aspm_init = ath_pci_aspm_init,
6baff7f9 GJ	246	};
	247
	248	static int ath_pci_probe(struct pci_dev pdev, const struct pci_device_id id)
	249	{
6baff7f9 GJ	250	struct ath_softc *sc;
	251	struct ieee80211_hw *hw;
	252	u8 csz;
f0214843	253	u32 val;
6baff7f9	254	int ret = 0;
f934c4d9	255	char hw_name[64];
6baff7f9	256
b81950b1	257	if (pcim_enable_device(pdev))
6baff7f9 GJ	258	return -EIO;
6baff7f9 GJ	259
e930438c	260	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6baff7f9	261	if (ret) {
516304b0	262	pr_err("32-bit DMA not available\n");
b81950b1	263	return ret;
6baff7f9 GJ	264	}
6baff7f9 GJ	265
e930438c	266	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6baff7f9	267	if (ret) {
516304b0	268	pr_err("32-bit DMA consistent DMA enable failed\n");
b81950b1	269	return ret;
6baff7f9 GJ	270	}
	271
	272	/*
	273	* Cache line size is used to size and align various
	274	* structures used to communicate with the hardware.
	275	*/
	276	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	277	if (csz == 0) {
	278	/*
	279	* Linux 2.4.18 (at least) writes the cache line size
	280	* register as a 16-bit wide register which is wrong.
	281	* We must have this setup properly for rx buffer
	282	* DMA to work so force a reasonable value here if it
	283	* comes up zero.
	284	*/
	285	csz = L1_CACHE_BYTES / sizeof(u32);
	286	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	287	}
	288	/*
	289	* The default setting of latency timer yields poor results,
	290	* set it to the value used by other systems. It may be worth
	291	* tweaking this setting more.
	292	*/
	293	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
	294
	295	pci_set_master(pdev);
	296
f0214843 JM	297	/*
	298	* Disable the RETRY_TIMEOUT register (0x41) to keep
	299	* PCI Tx retries from interfering with C3 CPU state.
	300	*/
	301	pci_read_config_dword(pdev, 0x40, &val);
	302	if ((val & 0x0000ff00) != 0)
	303	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
	304
b81950b1	305	ret = pcim_iomap_regions(pdev, BIT(0), "ath9k");
6baff7f9 GJ	306	if (ret) {
6baff7f9 GJ	307	dev_err(&pdev->dev, "PCI memory region reserve error\n");
b81950b1	308	return -ENODEV;
6baff7f9 GJ	309	}
6baff7f9 GJ	310
9ac58615	311	hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
db6be53c	312	if (!hw) {
285f2dda	313	dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
b81950b1	314	return -ENOMEM;
6baff7f9 GJ	315	}
	316
	317	SET_IEEE80211_DEV(hw, &pdev->dev);
	318	pci_set_drvdata(pdev, hw);
	319
9ac58615	320	sc = hw->priv;
6baff7f9 GJ	321	sc->hw = hw;
6baff7f9 GJ	322	sc->dev = &pdev->dev;
b81950b1	323	sc->mem = pcim_iomap_table(pdev)[0];
9b60b64b	324	sc->driver_data = id->driver_data;
6baff7f9	325
5e4ea1f0	326	/* Will be cleared in ath9k_start() */
781b14a3	327	set_bit(SC_OP_INVALID, &sc->sc_flags);
6baff7f9	328
fc548af8	329	ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
580171f7 LR	330	if (ret) {
580171f7 LR	331	dev_err(&pdev->dev, "request_irq failed\n");
285f2dda	332	goto err_irq;
6baff7f9 GJ	333	}
	334
	335	sc->irq = pdev->irq;
	336
eb93e891	337	ret = ath9k_init_device(id->device, sc, &ath_pci_bus_ops);
285f2dda S	338	if (ret) {
	339	dev_err(&pdev->dev, "Failed to initialize device\n");
	340	goto err_init;
	341	}
	342
	343	ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
c96c31e4	344	wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n",
b81950b1	345	hw_name, (unsigned long)sc->mem, pdev->irq);
6baff7f9 GJ	346
6baff7f9 GJ	347	return 0;
285f2dda S	348
	349	err_init:
	350	free_irq(sc->irq, sc);
	351	err_irq:
6baff7f9	352	ieee80211_free_hw(hw);
6baff7f9 GJ	353	return ret;
	354	}
	355
	356	static void ath_pci_remove(struct pci_dev *pdev)
	357	{
	358	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
9ac58615	359	struct ath_softc *sc = hw->priv;
6baff7f9	360
d584747b RM	361	if (!is_ath9k_unloaded)
d584747b RM	362	sc->sc_ah->ah_flags \|= AH_UNPLUGGED;
285f2dda S	363	ath9k_deinit_device(sc);
	364	free_irq(sc->irq, sc);
	365	ieee80211_free_hw(sc->hw);
6baff7f9 GJ	366	}
6baff7f9 GJ	367
88427588	368	#ifdef CONFIG_PM_SLEEP
6baff7f9	369
f0e94b47	370	static int ath_pci_suspend(struct device *device)
6baff7f9	371	{
f0e94b47	372	struct pci_dev *pdev = to_pci_dev(device);
6baff7f9	373	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
9ac58615	374	struct ath_softc *sc = hw->priv;
6baff7f9	375
4a17a50d MSS	376	if (sc->wow_enabled)
	377	return 0;
	378
c31eb8e9 RM	379	/* The device has to be moved to FULLSLEEP forcibly.
	380	* Otherwise the chip never moved to full sleep,
	381	* when no interface is up.
	382	*/
e19f15ac	383	ath9k_stop_btcoex(sc);
c0c11741	384	ath9k_hw_disable(sc->sc_ah);
c31eb8e9 RM	385	ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
c31eb8e9 RM	386
6baff7f9 GJ	387	return 0;
	388	}
	389
f0e94b47	390	static int ath_pci_resume(struct device *device)
6baff7f9	391	{
f0e94b47	392	struct pci_dev *pdev = to_pci_dev(device);
93170516 FF	393	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
93170516 FF	394	struct ath_softc *sc = hw->priv;
ceb26a60 FF	395	struct ath_hw *ah = sc->sc_ah;
ceb26a60 FF	396	struct ath_common *common = ath9k_hw_common(ah);
f0214843	397	u32 val;
523c36fc	398
f0214843 JM	399	/*
	400	* Suspend/Resume resets the PCI configuration space, so we have to
	401	* re-disable the RETRY_TIMEOUT register (0x41) to keep
	402	* PCI Tx retries from interfering with C3 CPU state
	403	*/
	404	pci_read_config_dword(pdev, 0x40, &val);
	405	if ((val & 0x0000ff00) != 0)
	406	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
6baff7f9	407
93170516	408	ath_pci_aspm_init(common);
ceb26a60	409	ah->reset_power_on = false;
93170516	410
6baff7f9 GJ	411	return 0;
	412	}
	413
88427588	414	static SIMPLE_DEV_PM_OPS(ath9k_pm_ops, ath_pci_suspend, ath_pci_resume);
f0e94b47 RW	415
	416	#define ATH9K_PM_OPS (&ath9k_pm_ops)
	417
88427588	418	#else /* !CONFIG_PM_SLEEP */
f0e94b47 RW	419
	420	#define ATH9K_PM_OPS NULL
	421
88427588	422	#endif /* !CONFIG_PM_SLEEP */
f0e94b47	423
6baff7f9 GJ	424
	425	MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
	426
	427	static struct pci_driver ath_pci_driver = {
	428	.name = "ath9k",
	429	.id_table = ath_pci_id_table,
	430	.probe = ath_pci_probe,
	431	.remove = ath_pci_remove,
f0e94b47	432	.driver.pm = ATH9K_PM_OPS,
6baff7f9 GJ	433	};
6baff7f9 GJ	434
db0f41f5	435	int ath_pci_init(void)
6baff7f9 GJ	436	{
	437	return pci_register_driver(&ath_pci_driver);
	438	}
	439
	440	void ath_pci_exit(void)
	441	{
	442	pci_unregister_driver(&ath_pci_driver);
	443	}