[deliverable/linux.git] / drivers / net / wireless / ath / ath9k / pci.c

/*
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/nl80211.h>
#include <linux/pci.h>
#include "ath9k.h"

static struct pci_device_id ath_pci_id_table[] __devinitdata = {
	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
	{ 0 }
};

/* return bus cachesize in 4B word units */
static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	u8 u8tmp;

	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
	*csz = (int)u8tmp;

	/*
	 * This check was put in to avoid "unplesant" consequences if
	 * the bootrom has not fully initialized all PCI devices.
	 * Sometimes the cache line size register is not set
	 */

	if (*csz == 0)
		*csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
}

static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
{
	struct ath_hw *ah = (struct ath_hw *) common->ah;

	common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));

	if (!ath9k_hw_wait(ah,
			   AR_EEPROM_STATUS_DATA,
			   AR_EEPROM_STATUS_DATA_BUSY |
			   AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
			   AH_WAIT_TIMEOUT)) {
		return false;
	}

	*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
		   AR_EEPROM_STATUS_DATA_VAL);

	return true;
}

/*
 * Bluetooth coexistance requires disabling ASPM.
 */
static void ath_pci_bt_coex_prep(struct ath_common *common)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	struct pci_dev *pdev = to_pci_dev(sc->dev);
	u8 aspm;

	if (!pdev->is_pcie)
		return;

	pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
	aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
	pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
}

static const struct ath_bus_ops ath_pci_bus_ops = {
	.read_cachesize = ath_pci_read_cachesize,
	.eeprom_read = ath_pci_eeprom_read,
	.bt_coex_prep = ath_pci_bt_coex_prep,
};

static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	void __iomem *mem;
	struct ath_wiphy *aphy;
	struct ath_softc *sc;
	struct ieee80211_hw *hw;
	u8 csz;
	u16 subsysid;
	u32 val;
	int ret = 0;
	char hw_name[64];

	if (pci_enable_device(pdev))
		return -EIO;

	ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
		printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
		goto err_dma;
	}

	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
	if (ret) {
		printk(KERN_ERR "ath9k: 32-bit DMA consistent "
			"DMA enable failed\n");
		goto err_dma;
	}

	/*
	 * Cache line size is used to size and align various
	 * structures used to communicate with the hardware.
	 */
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	if (csz == 0) {
		/*
		 * Linux 2.4.18 (at least) writes the cache line size
		 * register as a 16-bit wide register which is wrong.
		 * We must have this setup properly for rx buffer
		 * DMA to work so force a reasonable value here if it
		 * comes up zero.
		 */
		csz = L1_CACHE_BYTES / sizeof(u32);
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	}
	/*
	 * The default setting of latency timer yields poor results,
	 * set it to the value used by other systems. It may be worth
	 * tweaking this setting more.
	 */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);

	pci_set_master(pdev);

	/*
	 * Disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state.
	 */
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	ret = pci_request_region(pdev, 0, "ath9k");
	if (ret) {
		dev_err(&pdev->dev, "PCI memory region reserve error\n");
		ret = -ENODEV;
		goto err_region;
	}

	mem = pci_iomap(pdev, 0, 0);
	if (!mem) {
		printk(KERN_ERR "PCI memory map error\n") ;
		ret = -EIO;
		goto err_iomap;
	}

	hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
				sizeof(struct ath_softc), &ath9k_ops);
	if (!hw) {
		dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
		ret = -ENOMEM;
		goto err_alloc_hw;
	}

	SET_IEEE80211_DEV(hw, &pdev->dev);
	pci_set_drvdata(pdev, hw);

	aphy = hw->priv;
	sc = (struct ath_softc *) (aphy + 1);
	aphy->sc = sc;
	aphy->hw = hw;
	sc->pri_wiphy = aphy;
	sc->hw = hw;
	sc->dev = &pdev->dev;
	sc->mem = mem;

	/* Will be cleared in ath9k_start() */
	sc->sc_flags |= SC_OP_INVALID;

	ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
	if (ret) {
		dev_err(&pdev->dev, "request_irq failed\n");
		goto err_irq;
	}

	sc->irq = pdev->irq;

	pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
	ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
	if (ret) {
		dev_err(&pdev->dev, "Failed to initialize device\n");
		goto err_init;
	}

	ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
	printk(KERN_INFO
	       "%s: %s mem=0x%lx, irq=%d\n",
	       wiphy_name(hw->wiphy),
	       hw_name,
	       (unsigned long)mem, pdev->irq);

	return 0;

err_init:
	free_irq(sc->irq, sc);
err_irq:
	ieee80211_free_hw(hw);
err_alloc_hw:
	pci_iounmap(pdev, mem);
err_iomap:
	pci_release_region(pdev, 0);
err_region:
	/* Nothing */
err_dma:
	pci_disable_device(pdev);
	return ret;
}

static void ath_pci_remove(struct pci_dev *pdev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
	void __iomem *mem = sc->mem;

	ath9k_deinit_device(sc);
	free_irq(sc->irq, sc);
	ieee80211_free_hw(sc->hw);

	pci_iounmap(pdev, mem);
	pci_disable_device(pdev);
	pci_release_region(pdev, 0);
}

#ifdef CONFIG_PM

static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;

	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);

	pci_save_state(pdev);
	pci_disable_device(pdev);
	pci_set_power_state(pdev, PCI_D3hot);

	return 0;
}

static int ath_pci_resume(struct pci_dev *pdev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
	u32 val;
	int err;

	pci_restore_state(pdev);

	err = pci_enable_device(pdev);
	if (err)
		return err;

	/*
	 * Suspend/Resume resets the PCI configuration space, so we have to
	 * re-disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state
	 */
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	/* Enable LED */
	ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
			    AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);

	return 0;
}

#endif /* CONFIG_PM */

MODULE_DEVICE_TABLE(pci, ath_pci_id_table);

static struct pci_driver ath_pci_driver = {
	.name       = "ath9k",
	.id_table   = ath_pci_id_table,
	.probe      = ath_pci_probe,
	.remove     = ath_pci_remove,
#ifdef CONFIG_PM
	.suspend    = ath_pci_suspend,
	.resume     = ath_pci_resume,
#endif /* CONFIG_PM */
};

int ath_pci_init(void)
{
	return pci_register_driver(&ath_pci_driver);
}

void ath_pci_exit(void)
{
	pci_unregister_driver(&ath_pci_driver);
}
Commit	Line	Data
6baff7f9	1	/*
cee075a2	2	* Copyright (c) 2008-2009 Atheros Communications Inc.
6baff7f9 GJ	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#include <linux/nl80211.h>
	18	#include <linux/pci.h>
394cf0a1	19	#include "ath9k.h"
6baff7f9 GJ	20
	21	static struct pci_device_id ath_pci_id_table[] __devinitdata = {
	22	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
	23	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
	24	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
	25	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
	26	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
	27	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
ac88b6ec VN	28	{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
ac88b6ec VN	29	{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
6baff7f9 GJ	30	{ 0 }
	31	};
	32
	33	/* return bus cachesize in 4B word units */
5bb12791	34	static void ath_pci_read_cachesize(struct ath_common common, int csz)
6baff7f9	35	{
bc974f4a	36	struct ath_softc sc = (struct ath_softc ) common->priv;
6baff7f9 GJ	37	u8 u8tmp;
6baff7f9 GJ	38
f020979d	39	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
6baff7f9 GJ	40	*csz = (int)u8tmp;
	41
	42	/*
	43	* This check was put in to avoid "unplesant" consequences if
	44	* the bootrom has not fully initialized all PCI devices.
	45	* Sometimes the cache line size register is not set
	46	*/
	47
	48	if (*csz == 0)
	49	csz = DEFAULT_CACHELINE >> 2; / Use the default size */
	50	}
	51
5bb12791	52	static bool ath_pci_eeprom_read(struct ath_common common, u32 off, u16 data)
9dbeb91a	53	{
5bb12791 LR	54	struct ath_hw ah = (struct ath_hw ) common->ah;
5bb12791 LR	55
475a6e4d	56	common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
9dbeb91a GJ	57
	58	if (!ath9k_hw_wait(ah,
	59	AR_EEPROM_STATUS_DATA,
	60	AR_EEPROM_STATUS_DATA_BUSY \|
0caa7b14 S	61	AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
0caa7b14 S	62	AH_WAIT_TIMEOUT)) {
9dbeb91a GJ	63	return false;
	64	}
	65
475a6e4d	66	*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
9dbeb91a GJ	67	AR_EEPROM_STATUS_DATA_VAL);
	68
	69	return true;
	70	}
	71
867633f0 LR	72	/*
	73	* Bluetooth coexistance requires disabling ASPM.
	74	*/
5bb12791	75	static void ath_pci_bt_coex_prep(struct ath_common *common)
867633f0	76	{
bc974f4a	77	struct ath_softc sc = (struct ath_softc ) common->priv;
867633f0 LR	78	struct pci_dev *pdev = to_pci_dev(sc->dev);
	79	u8 aspm;
	80
	81	if (!pdev->is_pcie)
	82	return;
	83
	84	pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
	85	aspm &= ~(ATH_PCIE_CAP_LINK_L0S \| ATH_PCIE_CAP_LINK_L1);
	86	pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
	87	}
	88
83bd11a0	89	static const struct ath_bus_ops ath_pci_bus_ops = {
6baff7f9	90	.read_cachesize = ath_pci_read_cachesize,
9dbeb91a	91	.eeprom_read = ath_pci_eeprom_read,
867633f0	92	.bt_coex_prep = ath_pci_bt_coex_prep,
6baff7f9 GJ	93	};
	94
	95	static int ath_pci_probe(struct pci_dev pdev, const struct pci_device_id id)
	96	{
	97	void __iomem *mem;
bce048d7	98	struct ath_wiphy *aphy;
6baff7f9 GJ	99	struct ath_softc *sc;
	100	struct ieee80211_hw *hw;
	101	u8 csz;
aeac355d	102	u16 subsysid;
f0214843	103	u32 val;
6baff7f9	104	int ret = 0;
f934c4d9	105	char hw_name[64];
6baff7f9 GJ	106
	107	if (pci_enable_device(pdev))
	108	return -EIO;
	109
e930438c	110	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6baff7f9 GJ	111	if (ret) {
6baff7f9 GJ	112	printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
285f2dda	113	goto err_dma;
6baff7f9 GJ	114	}
6baff7f9 GJ	115
e930438c	116	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6baff7f9 GJ	117	if (ret) {
	118	printk(KERN_ERR "ath9k: 32-bit DMA consistent "
	119	"DMA enable failed\n");
285f2dda	120	goto err_dma;
6baff7f9 GJ	121	}
	122
	123	/*
	124	* Cache line size is used to size and align various
	125	* structures used to communicate with the hardware.
	126	*/
	127	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	128	if (csz == 0) {
	129	/*
	130	* Linux 2.4.18 (at least) writes the cache line size
	131	* register as a 16-bit wide register which is wrong.
	132	* We must have this setup properly for rx buffer
	133	* DMA to work so force a reasonable value here if it
	134	* comes up zero.
	135	*/
	136	csz = L1_CACHE_BYTES / sizeof(u32);
	137	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	138	}
	139	/*
	140	* The default setting of latency timer yields poor results,
	141	* set it to the value used by other systems. It may be worth
	142	* tweaking this setting more.
	143	*/
	144	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
	145
	146	pci_set_master(pdev);
	147
f0214843 JM	148	/*
	149	* Disable the RETRY_TIMEOUT register (0x41) to keep
	150	* PCI Tx retries from interfering with C3 CPU state.
	151	*/
	152	pci_read_config_dword(pdev, 0x40, &val);
	153	if ((val & 0x0000ff00) != 0)
	154	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
	155
6baff7f9 GJ	156	ret = pci_request_region(pdev, 0, "ath9k");
	157	if (ret) {
	158	dev_err(&pdev->dev, "PCI memory region reserve error\n");
	159	ret = -ENODEV;
285f2dda	160	goto err_region;
6baff7f9 GJ	161	}
	162
	163	mem = pci_iomap(pdev, 0, 0);
	164	if (!mem) {
	165	printk(KERN_ERR "PCI memory map error\n") ;
	166	ret = -EIO;
285f2dda	167	goto err_iomap;
6baff7f9 GJ	168	}
6baff7f9 GJ	169
bce048d7 JM	170	hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
bce048d7 JM	171	sizeof(struct ath_softc), &ath9k_ops);
db6be53c	172	if (!hw) {
285f2dda	173	dev_err(&pdev->dev, "No memory for ieee80211_hw\n");
db6be53c	174	ret = -ENOMEM;
285f2dda	175	goto err_alloc_hw;
6baff7f9 GJ	176	}
	177
	178	SET_IEEE80211_DEV(hw, &pdev->dev);
	179	pci_set_drvdata(pdev, hw);
	180
bce048d7 JM	181	aphy = hw->priv;
	182	sc = (struct ath_softc *) (aphy + 1);
	183	aphy->sc = sc;
	184	aphy->hw = hw;
	185	sc->pri_wiphy = aphy;
6baff7f9 GJ	186	sc->hw = hw;
	187	sc->dev = &pdev->dev;
	188	sc->mem = mem;
6baff7f9	189
5e4ea1f0 S	190	/* Will be cleared in ath9k_start() */
	191	sc->sc_flags \|= SC_OP_INVALID;
	192
fc548af8	193	ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
580171f7 LR	194	if (ret) {
580171f7 LR	195	dev_err(&pdev->dev, "request_irq failed\n");
285f2dda	196	goto err_irq;
6baff7f9 GJ	197	}
	198
	199	sc->irq = pdev->irq;
	200
285f2dda S	201	pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
	202	ret = ath9k_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
	203	if (ret) {
	204	dev_err(&pdev->dev, "Failed to initialize device\n");
	205	goto err_init;
	206	}
	207
	208	ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name));
6baff7f9	209	printk(KERN_INFO
f934c4d9	210	"%s: %s mem=0x%lx, irq=%d\n",
6baff7f9	211	wiphy_name(hw->wiphy),
f934c4d9	212	hw_name,
6baff7f9 GJ	213	(unsigned long)mem, pdev->irq);
	214
	215	return 0;
285f2dda S	216
	217	err_init:
	218	free_irq(sc->irq, sc);
	219	err_irq:
6baff7f9	220	ieee80211_free_hw(hw);
285f2dda	221	err_alloc_hw:
6baff7f9	222	pci_iounmap(pdev, mem);
285f2dda	223	err_iomap:
6baff7f9	224	pci_release_region(pdev, 0);
285f2dda S	225	err_region:
	226	/* Nothing */
	227	err_dma:
6baff7f9 GJ	228	pci_disable_device(pdev);
	229	return ret;
	230	}
	231
	232	static void ath_pci_remove(struct pci_dev *pdev)
	233	{
	234	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
bce048d7 JM	235	struct ath_wiphy *aphy = hw->priv;
bce048d7 JM	236	struct ath_softc *sc = aphy->sc;
ab5132a2	237	void __iomem *mem = sc->mem;
6baff7f9	238
285f2dda S	239	ath9k_deinit_device(sc);
	240	free_irq(sc->irq, sc);
	241	ieee80211_free_hw(sc->hw);
ab5132a2 PR	242
	243	pci_iounmap(pdev, mem);
	244	pci_disable_device(pdev);
	245	pci_release_region(pdev, 0);
6baff7f9 GJ	246	}
	247
	248	#ifdef CONFIG_PM
	249
	250	static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
	251	{
	252	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
bce048d7 JM	253	struct ath_wiphy *aphy = hw->priv;
bce048d7 JM	254	struct ath_softc *sc = aphy->sc;
6baff7f9	255
08fc5c1b	256	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
6baff7f9	257
6baff7f9 GJ	258	pci_save_state(pdev);
	259	pci_disable_device(pdev);
	260	pci_set_power_state(pdev, PCI_D3hot);
	261
	262	return 0;
	263	}
	264
	265	static int ath_pci_resume(struct pci_dev *pdev)
	266	{
	267	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
bce048d7 JM	268	struct ath_wiphy *aphy = hw->priv;
bce048d7 JM	269	struct ath_softc *sc = aphy->sc;
f0214843	270	u32 val;
6baff7f9 GJ	271	int err;
6baff7f9 GJ	272
523c36fc S	273	pci_restore_state(pdev);
523c36fc S	274
6baff7f9 GJ	275	err = pci_enable_device(pdev);
	276	if (err)
	277	return err;
523c36fc	278
f0214843 JM	279	/*
	280	* Suspend/Resume resets the PCI configuration space, so we have to
	281	* re-disable the RETRY_TIMEOUT register (0x41) to keep
	282	* PCI Tx retries from interfering with C3 CPU state
	283	*/
	284	pci_read_config_dword(pdev, 0x40, &val);
	285	if ((val & 0x0000ff00) != 0)
	286	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
6baff7f9 GJ	287
6baff7f9 GJ	288	/* Enable LED */
08fc5c1b	289	ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
6baff7f9	290	AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b	291	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
6baff7f9	292
6baff7f9 GJ	293	return 0;
	294	}
	295
	296	#endif /* CONFIG_PM */
	297
	298	MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
	299
	300	static struct pci_driver ath_pci_driver = {
	301	.name = "ath9k",
	302	.id_table = ath_pci_id_table,
	303	.probe = ath_pci_probe,
	304	.remove = ath_pci_remove,
	305	#ifdef CONFIG_PM
	306	.suspend = ath_pci_suspend,
	307	.resume = ath_pci_resume,
	308	#endif /* CONFIG_PM */
	309	};
	310
db0f41f5	311	int ath_pci_init(void)
6baff7f9 GJ	312	{
	313	return pci_register_driver(&ath_pci_driver);
	314	}
	315
	316	void ath_pci_exit(void)
	317	{
	318	pci_unregister_driver(&ath_pci_driver);
	319	}