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ath5k: Update RF Buffer handling
[deliverable/linux.git] / drivers / net / wireless / ath5k / ath5k.h
CommitLineData
fa1c114f
JS		 1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _ATH5K_H
19#define _ATH5K_H
20
c6e387a2
NK		 21/* TODO: Clean up channel debuging -doesn't work anyway- and start
22 * working on reg. control code using all available eeprom information
23 * -rev. engineering needed- */
fa1c114f
JS		 24#define CHAN_DEBUG 0
25
26#include <linux/io.h>
27#include <linux/types.h>
28#include <net/mac80211.h>
29
c6e387a2
NK		 30/* RX/TX descriptor hw structs
31 * TODO: Driver part should only see sw structs */
32#include "desc.h"
33
34/* EEPROM structs/offsets
35 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
36 * and clean up common bits, then introduce set/get functions in eeprom.c */
37#include "eeprom.h"
fa1c114f
JS		 38
39/* PCI IDs */
40#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
41#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
42#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
43#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
44#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
45#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
46#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
47#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
48#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
49#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
50#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
51#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
52#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
53#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
54#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
55#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
57#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
58#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
59#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
60#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
61#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
62#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
63#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
64#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
65#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
66#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
67#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
68
69/****************************\
70 GENERIC DRIVER DEFINITIONS
71\****************************/
72
73#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
74
75#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
76 printk(_level "ath5k %s: " _fmt, \
77 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
78 ##__VA_ARGS__)
79
80#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
81 if (net_ratelimit()) \
82 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
83 } while (0)
84
85#define ATH5K_INFO(_sc, _fmt, ...) \
86 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
87
88#define ATH5K_WARN(_sc, _fmt, ...) \
89 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
90
91#define ATH5K_ERR(_sc, _fmt, ...) \
92 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
93
c6e387a2
NK		 94/*
95 * AR5K REGISTER ACCESS
96 */
97
98/* Some macros to read/write fields */
99
100/* First shift, then mask */
101#define AR5K_REG_SM(_val, _flags) \
102 (((_val) << _flags##_S) & (_flags))
103
104/* First mask, then shift */
105#define AR5K_REG_MS(_val, _flags) \
106 (((_val) & (_flags)) >> _flags##_S)
107
108/* Some registers can hold multiple values of interest. For this
109 * reason when we want to write to these registers we must first
110 * retrieve the values which we do not want to clear (lets call this
111 * old_data) and then set the register with this and our new_value:
112 * ( old_data | new_value) */
113#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
114 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
115 (((_val) << _flags##_S) & (_flags)), _reg)
116
117#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
118 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
119 (_mask)) | (_flags), _reg)
120
121#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
122 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
123
124#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
125 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
126
127/* Access to PHY registers */
128#define AR5K_PHY_READ(ah, _reg) \
129 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
130
131#define AR5K_PHY_WRITE(ah, _reg, _val) \
132 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
133
134/* Access QCU registers per queue */
135#define AR5K_REG_READ_Q(ah, _reg, _queue) \
136 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
137
138#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
139 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
140
141#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
142 _reg |= 1 << _queue; \
143} while (0)
144
145#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
146 _reg &= ~(1 << _queue); \
147} while (0)
148
149/* Used while writing initvals */
150#define AR5K_REG_WAIT(_i) do { \
151 if (_i % 64) \
152 udelay(1); \
153} while (0)
154
155/* Register dumps are done per operation mode */
156#define AR5K_INI_RFGAIN_5GHZ 0
157#define AR5K_INI_RFGAIN_2GHZ 1
158
159/* TODO: Clean this up */
160#define AR5K_INI_VAL_11A 0
161#define AR5K_INI_VAL_11A_TURBO 1
162#define AR5K_INI_VAL_11B 2
163#define AR5K_INI_VAL_11G 3
164#define AR5K_INI_VAL_11G_TURBO 4
165#define AR5K_INI_VAL_XR 0
166#define AR5K_INI_VAL_MAX 5
167
c6e387a2
NK		 168/* Used for BSSID etc manipulation */
169#define AR5K_LOW_ID(_a)( \
170(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
171)
172
173#define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8)
174
fa1c114f
JS		 175/*
176 * Some tuneable values (these should be changeable by the user)
c6e387a2 177 * TODO: Make use of them and add more options OR use debug/configfs
fa1c114f
JS		 178 */
179#define AR5K_TUNE_DMA_BEACON_RESP 2
180#define AR5K_TUNE_SW_BEACON_RESP 10
181#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
182#define AR5K_TUNE_RADAR_ALERT false
183#define AR5K_TUNE_MIN_TX_FIFO_THRES 1
184#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
185#define AR5K_TUNE_REGISTER_TIMEOUT 20000
186/* Register for RSSI threshold has a mask of 0xff, so 255 seems to
187 * be the max value. */
c6e387a2 188#define AR5K_TUNE_RSSI_THRES 129
fa1c114f
JS		 189/* This must be set when setting the RSSI threshold otherwise it can
190 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
191 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
192 * track of it. Max value depends on harware. For AR5210 this is just 7.
193 * For AR5211+ this seems to be up to 255. */
c6e387a2 194#define AR5K_TUNE_BMISS_THRES 7
fa1c114f
JS		 195#define AR5K_TUNE_REGISTER_DWELL_TIME 20000
196#define AR5K_TUNE_BEACON_INTERVAL 100
197#define AR5K_TUNE_AIFS 2
198#define AR5K_TUNE_AIFS_11B 2
199#define AR5K_TUNE_AIFS_XR 0
200#define AR5K_TUNE_CWMIN 15
201#define AR5K_TUNE_CWMIN_11B 31
202#define AR5K_TUNE_CWMIN_XR 3
203#define AR5K_TUNE_CWMAX 1023
204#define AR5K_TUNE_CWMAX_11B 1023
205#define AR5K_TUNE_CWMAX_XR 7
206#define AR5K_TUNE_NOISE_FLOOR -72
207#define AR5K_TUNE_MAX_TXPOWER 60
208#define AR5K_TUNE_DEFAULT_TXPOWER 30
209#define AR5K_TUNE_TPC_TXPOWER true
210#define AR5K_TUNE_ANT_DIVERSITY true
211#define AR5K_TUNE_HWTXTRIES 4
212
c6e387a2
NK		 213#define AR5K_INIT_CARR_SENSE_EN 1
214
215/*Swap RX/TX Descriptor for big endian archs*/
216#if defined(__BIG_ENDIAN)
217#define AR5K_INIT_CFG ( \
218 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
219)
220#else
221#define AR5K_INIT_CFG 0x00000000
222#endif
223
224/* Initial values */
225#define AR5K_INIT_TX_LATENCY 502
226#define AR5K_INIT_USEC 39
227#define AR5K_INIT_USEC_TURBO 79
228#define AR5K_INIT_USEC_32 31
229#define AR5K_INIT_SLOT_TIME 396
230#define AR5K_INIT_SLOT_TIME_TURBO 480
231#define AR5K_INIT_ACK_CTS_TIMEOUT 1024
232#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
233#define AR5K_INIT_PROG_IFS 920
234#define AR5K_INIT_PROG_IFS_TURBO 960
235#define AR5K_INIT_EIFS 3440
236#define AR5K_INIT_EIFS_TURBO 6880
237#define AR5K_INIT_SIFS 560
238#define AR5K_INIT_SIFS_TURBO 480
239#define AR5K_INIT_SH_RETRY 10
240#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
241#define AR5K_INIT_SSH_RETRY 32
242#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
243#define AR5K_INIT_TX_RETRY 10
244
245#define AR5K_INIT_TRANSMIT_LATENCY ( \
246 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
247 (AR5K_INIT_USEC) \
248)
249#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
250 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
251 (AR5K_INIT_USEC_TURBO) \
252)
253#define AR5K_INIT_PROTO_TIME_CNTRL ( \
254 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
255 (AR5K_INIT_PROG_IFS) \
256)
257#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
258 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
259 (AR5K_INIT_PROG_IFS_TURBO) \
260)
261
fa1c114f
JS		 262/* token to use for aifs, cwmin, cwmax in MadWiFi */
263#define AR5K_TXQ_USEDEFAULT ((u32) -1)
264
265/* GENERIC CHIPSET DEFINITIONS */
266
267/* MAC Chips */
268enum ath5k_version {
269 AR5K_AR5210 = 0,
270 AR5K_AR5211 = 1,
271 AR5K_AR5212 = 2,
272};
273
274/* PHY Chips */
275enum ath5k_radio {
276 AR5K_RF5110 = 0,
277 AR5K_RF5111 = 1,
278 AR5K_RF5112 = 2,
8daeef97
NK		 279 AR5K_RF2413 = 3,
280 AR5K_RF5413 = 4,
1bef016a
NK		 281 AR5K_RF2316 = 5,
282 AR5K_RF2317 = 6,
283 AR5K_RF2425 = 7,
fa1c114f
JS		 284};
285
286/*
287 * Common silicon revision/version values
288 */
289
290enum ath5k_srev_type {
1bef016a 291 AR5K_VERSION_MAC,
fa1c114f
JS		 292 AR5K_VERSION_RAD,
293};
294
295struct ath5k_srev_name {
296 const char *sr_name;
297 enum ath5k_srev_type sr_type;
298 u_int sr_val;
299};
300
301#define AR5K_SREV_UNKNOWN 0xffff
302
1bef016a
NK		 303#define AR5K_SREV_AR5210 0x00 /* Crete */
304#define AR5K_SREV_AR5311 0x10 /* Maui 1 */
305#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
306#define AR5K_SREV_AR5311B 0x30 /* Spirit */
307#define AR5K_SREV_AR5211 0x40 /* Oahu */
308#define AR5K_SREV_AR5212 0x50 /* Venice */
309#define AR5K_SREV_AR5213 0x55 /* ??? */
310#define AR5K_SREV_AR5213A 0x59 /* Hainan */
311#define AR5K_SREV_AR2413 0x78 /* Griffin lite */
312#define AR5K_SREV_AR2414 0x70 /* Griffin */
313#define AR5K_SREV_AR5424 0x90 /* Condor */
314#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
315#define AR5K_SREV_AR5414 0xa0 /* Eagle */
316#define AR5K_SREV_AR2415 0xb0 /* Cobra */
317#define AR5K_SREV_AR5416 0xc0 /* PCI-E */
318#define AR5K_SREV_AR5418 0xca /* PCI-E */
319#define AR5K_SREV_AR2425 0xe0 /* Swan */
320#define AR5K_SREV_AR2417 0xf0 /* Nala */
fa1c114f
JS		 321
322#define AR5K_SREV_RAD_5110 0x00
323#define AR5K_SREV_RAD_5111 0x10
324#define AR5K_SREV_RAD_5111A 0x15
325#define AR5K_SREV_RAD_2111 0x20
326#define AR5K_SREV_RAD_5112 0x30
327#define AR5K_SREV_RAD_5112A 0x35
e5a4ad0d 328#define AR5K_SREV_RAD_5112B 0x36
fa1c114f
JS		 329#define AR5K_SREV_RAD_2112 0x40
330#define AR5K_SREV_RAD_2112A 0x45
e5a4ad0d 331#define AR5K_SREV_RAD_2112B 0x46
1bef016a
NK		 332#define AR5K_SREV_RAD_2413 0x50
333#define AR5K_SREV_RAD_5413 0x60
334#define AR5K_SREV_RAD_2316 0x70
335#define AR5K_SREV_RAD_2317 0x80
336#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
337#define AR5K_SREV_RAD_2425 0xa2
338#define AR5K_SREV_RAD_5133 0xc0
339
340#define AR5K_SREV_PHY_5211 0x30
341#define AR5K_SREV_PHY_5212 0x41
8892e4ec 342#define AR5K_SREV_PHY_5212A 0x42
1bef016a
NK		 343#define AR5K_SREV_PHY_2112B 0x43
344#define AR5K_SREV_PHY_2413 0x45
345#define AR5K_SREV_PHY_5413 0x61
346#define AR5K_SREV_PHY_2425 0x70
fa1c114f
JS		 347
348/* IEEE defs */
fa1c114f
JS		 349#define IEEE80211_MAX_LEN 2500
350
351/* TODO add support to mac80211 for vendor-specific rates and modes */
352
353/*
354 * Some of this information is based on Documentation from:
355 *
356 * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
357 *
358 * Modulation for Atheros' eXtended Range - range enhancing extension that is
359 * supposed to double the distance an Atheros client device can keep a
360 * connection with an Atheros access point. This is achieved by increasing
361 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
362 * the 802.11 specifications demand. In addition, new (proprietary) data rates
363 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
364 *
365 * Please note that can you either use XR or TURBO but you cannot use both,
366 * they are exclusive.
367 *
368 */
369#define MODULATION_XR 0x00000200
370/*
371 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
372 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
373 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
374 * channels. To use this feature your Access Point must also suport it.
375 * There is also a distinction between "static" and "dynamic" turbo modes:
376 *
377 * - Static: is the dumb version: devices set to this mode stick to it until
378 * the mode is turned off.
379 * - Dynamic: is the intelligent version, the network decides itself if it
380 * is ok to use turbo. As soon as traffic is detected on adjacent channels
381 * (which would get used in turbo mode), or when a non-turbo station joins
382 * the network, turbo mode won't be used until the situation changes again.
383 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
384 * monitors the used radio band in order to decide whether turbo mode may
385 * be used or not.
386 *
387 * This article claims Super G sticks to bonding of channels 5 and 6 for
388 * USA:
389 *
390 * http://www.pcworld.com/article/id,113428-page,1/article.html
391 *
392 * The channel bonding seems to be driver specific though. In addition to
393 * deciding what channels will be used, these "Turbo" modes are accomplished
394 * by also enabling the following features:
395 *
396 * - Bursting: allows multiple frames to be sent at once, rather than pausing
397 * after each frame. Bursting is a standards-compliant feature that can be
398 * used with any Access Point.
399 * - Fast frames: increases the amount of information that can be sent per
400 * frame, also resulting in a reduction of transmission overhead. It is a
401 * proprietary feature that needs to be supported by the Access Point.
402 * - Compression: data frames are compressed in real time using a Lempel Ziv
403 * algorithm. This is done transparently. Once this feature is enabled,
404 * compression and decompression takes place inside the chipset, without
405 * putting additional load on the host CPU.
406 *
407 */
408#define MODULATION_TURBO 0x00000080
409
d8ee398d
LR		 410enum ath5k_driver_mode {
411 AR5K_MODE_11A = 0,
412 AR5K_MODE_11A_TURBO = 1,
413 AR5K_MODE_11B = 2,
414 AR5K_MODE_11G = 3,
415 AR5K_MODE_11G_TURBO = 4,
416 AR5K_MODE_XR = 0,
417 AR5K_MODE_MAX = 5
fa1c114f
JS		 418};
419
19fd6e55 420
fa1c114f
JS		 421/****************\
422 TX DEFINITIONS
423\****************/
424
425/*
c6e387a2 426 * TX Status descriptor
fa1c114f
JS		 427 */
428struct ath5k_tx_status {
429 u16 ts_seqnum;
430 u16 ts_tstamp;
431 u8 ts_status;
2f7fe870
FF		 432 u8 ts_rate[4];
433 u8 ts_retry[4];
434 u8 ts_final_idx;
fa1c114f
JS		 435 s8 ts_rssi;
436 u8 ts_shortretry;
437 u8 ts_longretry;
438 u8 ts_virtcol;
439 u8 ts_antenna;
440};
441
442#define AR5K_TXSTAT_ALTRATE 0x80
443#define AR5K_TXERR_XRETRY 0x01
444#define AR5K_TXERR_FILT 0x02
445#define AR5K_TXERR_FIFO 0x04
446
447/**
448 * enum ath5k_tx_queue - Queue types used to classify tx queues.
449 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
450 * @AR5K_TX_QUEUE_DATA: A normal data queue
451 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
452 * @AR5K_TX_QUEUE_BEACON: The beacon queue
453 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
454 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
455 */
456enum ath5k_tx_queue {
457 AR5K_TX_QUEUE_INACTIVE = 0,
458 AR5K_TX_QUEUE_DATA,
459 AR5K_TX_QUEUE_XR_DATA,
460 AR5K_TX_QUEUE_BEACON,
461 AR5K_TX_QUEUE_CAB,
462 AR5K_TX_QUEUE_UAPSD,
463};
464
465#define AR5K_NUM_TX_QUEUES 10
466#define AR5K_NUM_TX_QUEUES_NOQCU 2
467
468/*
469 * Queue syb-types to classify normal data queues.
470 * These are the 4 Access Categories as defined in
471 * WME spec. 0 is the lowest priority and 4 is the
472 * highest. Normal data that hasn't been classified
473 * goes to the Best Effort AC.
474 */
475enum ath5k_tx_queue_subtype {
476 AR5K_WME_AC_BK = 0, /*Background traffic*/
477 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/
478 AR5K_WME_AC_VI, /*Video traffic*/
479 AR5K_WME_AC_VO, /*Voice traffic*/
480};
481
482/*
483 * Queue ID numbers as returned by the hw functions, each number
484 * represents a hw queue. If hw does not support hw queues
485 * (eg 5210) all data goes in one queue. These match
486 * d80211 definitions (net80211/MadWiFi don't use them).
487 */
488enum ath5k_tx_queue_id {
489 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
490 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
491 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
492 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
493 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
494 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
495 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
496 AR5K_TX_QUEUE_ID_UAPSD = 8,
497 AR5K_TX_QUEUE_ID_XR_DATA = 9,
498};
499
fa1c114f
JS		 500/*
501 * Flags to set hw queue's parameters...
502 */
503#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
504#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
505#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
506#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
507#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
4c674c60
NK		 508#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
509#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
510#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
511#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
512#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
513#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
514#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
515#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
516#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
fa1c114f
JS		 517
518/*
519 * A struct to hold tx queue's parameters
520 */
521struct ath5k_txq_info {
522 enum ath5k_tx_queue tqi_type;
523 enum ath5k_tx_queue_subtype tqi_subtype;
524 u16 tqi_flags; /* Tx queue flags (see above) */
525 u32 tqi_aifs; /* Arbitrated Interframe Space */
526 s32 tqi_cw_min; /* Minimum Contention Window */
527 s32 tqi_cw_max; /* Maximum Contention Window */
528 u32 tqi_cbr_period; /* Constant bit rate period */
529 u32 tqi_cbr_overflow_limit;
530 u32 tqi_burst_time;
531 u32 tqi_ready_time; /* Not used */
532};
533
534/*
535 * Transmit packet types.
c6e387a2
NK		 536 * used on tx control descriptor
537 * TODO: Use them inside base.c corectly
fa1c114f
JS		 538 */
539enum ath5k_pkt_type {
540 AR5K_PKT_TYPE_NORMAL = 0,
541 AR5K_PKT_TYPE_ATIM = 1,
542 AR5K_PKT_TYPE_PSPOLL = 2,
543 AR5K_PKT_TYPE_BEACON = 3,
544 AR5K_PKT_TYPE_PROBE_RESP = 4,
545 AR5K_PKT_TYPE_PIFS = 5,
546};
547
548/*
549 * TX power and TPC settings
550 */
551#define AR5K_TXPOWER_OFDM(_r, _v) ( \
552 ((0 & 1) << ((_v) + 6)) | \
553 (((ah->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \
554)
555
556#define AR5K_TXPOWER_CCK(_r, _v) ( \
557 (ah->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
558)
559
560/*
561 * DMA size definitions (2^n+2)
562 */
563enum ath5k_dmasize {
564 AR5K_DMASIZE_4B = 0,
565 AR5K_DMASIZE_8B,
566 AR5K_DMASIZE_16B,
567 AR5K_DMASIZE_32B,
568 AR5K_DMASIZE_64B,
569 AR5K_DMASIZE_128B,
570 AR5K_DMASIZE_256B,
571 AR5K_DMASIZE_512B
572};
573
574
575/****************\
576 RX DEFINITIONS
577\****************/
578
579/*
c6e387a2 580 * RX Status descriptor
fa1c114f
JS		 581 */
582struct ath5k_rx_status {
583 u16 rs_datalen;
584 u16 rs_tstamp;
585 u8 rs_status;
586 u8 rs_phyerr;
587 s8 rs_rssi;
588 u8 rs_keyix;
589 u8 rs_rate;
590 u8 rs_antenna;
591 u8 rs_more;
592};
593
594#define AR5K_RXERR_CRC 0x01
595#define AR5K_RXERR_PHY 0x02
596#define AR5K_RXERR_FIFO 0x04
597#define AR5K_RXERR_DECRYPT 0x08
598#define AR5K_RXERR_MIC 0x10
599#define AR5K_RXKEYIX_INVALID ((u8) - 1)
600#define AR5K_TXKEYIX_INVALID ((u32) - 1)
601
fa1c114f 602
fa1c114f
JS		 603/**************************\
604 BEACON TIMERS DEFINITIONS
605\**************************/
606
607#define AR5K_BEACON_PERIOD 0x0000ffff
608#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
609#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
610
611#if 0
612/**
613 * struct ath5k_beacon_state - Per-station beacon timer state.
614 * @bs_interval: in TU's, can also include the above flags
615 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
616 * Point Coordination Function capable AP
617 */
618struct ath5k_beacon_state {
619 u32 bs_next_beacon;
620 u32 bs_next_dtim;
621 u32 bs_interval;
622 u8 bs_dtim_period;
623 u8 bs_cfp_period;
624 u16 bs_cfp_max_duration;
625 u16 bs_cfp_du_remain;
626 u16 bs_tim_offset;
627 u16 bs_sleep_duration;
628 u16 bs_bmiss_threshold;
629 u32 bs_cfp_next;
630};
631#endif
632
633
634/*
635 * TSF to TU conversion:
636 *
637 * TSF is a 64bit value in usec (microseconds).
e535c1ac
BR		 638 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
639 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
fa1c114f
JS		 640 */
641#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
642
643
c6e387a2
NK		 644/*******************************\
645 GAIN OPTIMIZATION DEFINITIONS
646\*******************************/
647
648enum ath5k_rfgain {
649 AR5K_RFGAIN_INACTIVE = 0,
6f3b414a 650 AR5K_RFGAIN_ACTIVE,
c6e387a2
NK		 651 AR5K_RFGAIN_READ_REQUESTED,
652 AR5K_RFGAIN_NEED_CHANGE,
653};
654
c6e387a2 655struct ath5k_gain {
6f3b414a
NK		 656 u8 g_step_idx;
657 u8 g_current;
658 u8 g_target;
659 u8 g_low;
660 u8 g_high;
661 u8 g_f_corr;
662 u8 g_state;
c6e387a2
NK		 663};
664
fa1c114f
JS		 665/********************\
666 COMMON DEFINITIONS
667\********************/
668
fa1c114f
JS		 669#define AR5K_SLOT_TIME_9 396
670#define AR5K_SLOT_TIME_20 880
671#define AR5K_SLOT_TIME_MAX 0xffff
672
673/* channel_flags */
674#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
675#define CHANNEL_TURBO 0x0010 /* Turbo Channel */
676#define CHANNEL_CCK 0x0020 /* CCK channel */
677#define CHANNEL_OFDM 0x0040 /* OFDM channel */
678#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
679#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
680#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
681#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
682#define CHANNEL_XR 0x0800 /* XR channel */
683
684#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
685#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
686#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
687#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
688#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
689#define CHANNEL_108A CHANNEL_T
690#define CHANNEL_108G CHANNEL_TG
691#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
692
693#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
694 CHANNEL_TURBO)
695
696#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
697#define CHANNEL_MODES CHANNEL_ALL
698
699/*
c6e387a2
NK		 700 * Used internaly for reset_tx_queue).
701 * Also see struct struct ieee80211_channel.
fa1c114f 702 */
d8ee398d
LR		 703#define IS_CHAN_XR(_c) ((_c.hw_value & CHANNEL_XR) != 0)
704#define IS_CHAN_B(_c) ((_c.hw_value & CHANNEL_B) != 0)
fa1c114f
JS		 705
706/*
c6e387a2 707 * The following structure is used to map 2GHz channels to
fa1c114f 708 * 5GHz Atheros channels.
c6e387a2 709 * TODO: Clean up
fa1c114f
JS		 710 */
711struct ath5k_athchan_2ghz {
712 u32 a2_flags;
713 u16 a2_athchan;
714};
715
63266a65 716
c6e387a2
NK		 717/******************\
718 RATE DEFINITIONS
719\******************/
fa1c114f 720
fa1c114f 721/**
63266a65 722 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
fa1c114f 723 *
63266a65 724 * The rate code is used to get the RX rate or set the TX rate on the
fa1c114f
JS		 725 * hardware descriptors. It is also used for internal modulation control
726 * and settings.
727 *
63266a65 728 * This is the hardware rate map we are aware of:
fa1c114f 729 *
63266a65 730 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
fa1c114f
JS		 731 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
732 *
63266a65 733 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
fa1c114f
JS		 734 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
735 *
736 * rate_code 17 18 19 20 21 22 23 24
737 * rate_kbps ? ? ? ? ? ? ? 11000
738 *
739 * rate_code 25 26 27 28 29 30 31 32
63266a65
BR		 740 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
741 *
742 * "S" indicates CCK rates with short preamble.
fa1c114f 743 *
63266a65
BR		 744 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
745 * lowest 4 bits, so they are the same as below with a 0xF mask.
746 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
747 * We handle this in ath5k_setup_bands().
fa1c114f 748 */
63266a65 749#define AR5K_MAX_RATES 32
fa1c114f 750
63266a65
BR		 751/* B */
752#define ATH5K_RATE_CODE_1M 0x1B
753#define ATH5K_RATE_CODE_2M 0x1A
754#define ATH5K_RATE_CODE_5_5M 0x19
755#define ATH5K_RATE_CODE_11M 0x18
756/* A and G */
757#define ATH5K_RATE_CODE_6M 0x0B
758#define ATH5K_RATE_CODE_9M 0x0F
759#define ATH5K_RATE_CODE_12M 0x0A
760#define ATH5K_RATE_CODE_18M 0x0E
761#define ATH5K_RATE_CODE_24M 0x09
762#define ATH5K_RATE_CODE_36M 0x0D
763#define ATH5K_RATE_CODE_48M 0x08
764#define ATH5K_RATE_CODE_54M 0x0C
765/* XR */
766#define ATH5K_RATE_CODE_XR_500K 0x07
767#define ATH5K_RATE_CODE_XR_1M 0x02
768#define ATH5K_RATE_CODE_XR_2M 0x06
769#define ATH5K_RATE_CODE_XR_3M 0x01
fa1c114f 770
c6e387a2
NK		 771/* adding this flag to rate_code enables short preamble */
772#define AR5K_SET_SHORT_PREAMBLE 0x04
fa1c114f
JS		 773
774/*
775 * Crypto definitions
776 */
777
778#define AR5K_KEYCACHE_SIZE 8
779
780/***********************\
781 HW RELATED DEFINITIONS
782\***********************/
783
784/*
785 * Misc definitions
786 */
787#define AR5K_RSSI_EP_MULTIPLIER (1<<7)
788
789#define AR5K_ASSERT_ENTRY(_e, _s) do { \
790 if (_e >= _s) \
791 return (false); \
792} while (0)
793
fa1c114f
JS		 794/*
795 * Hardware interrupt abstraction
796 */
797
798/**
799 * enum ath5k_int - Hardware interrupt masks helpers
800 *
801 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
802 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
803 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
804 * @AR5K_INT_RXNOFRM: No frame received (?)
805 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
806 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
807 * LinkPtr is NULL. For more details, refer to:
808 * http://www.freepatentsonline.com/20030225739.html
809 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
810 * Note that Rx overrun is not always fatal, on some chips we can continue
811 * operation without reseting the card, that's why int_fatal is not
812 * common for all chips.
813 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
814 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
815 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
816 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
817 * We currently do increments on interrupt by
818 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
819 * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
820 * checked. We should do this with ath5k_hw_update_mib_counters() but
821 * it seems we should also then do some noise immunity work.
822 * @AR5K_INT_RXPHY: RX PHY Error
4c674c60 823 * @AR5K_INT_RXKCM: RX Key cache miss
fa1c114f
JS		 824 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
825 * beacon that must be handled in software. The alternative is if you
826 * have VEOL support, in that case you let the hardware deal with things.
827 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
828 * beacons from the AP have associated with, we should probably try to
829 * reassociate. When in IBSS mode this might mean we have not received
830 * any beacons from any local stations. Note that every station in an
831 * IBSS schedules to send beacons at the Target Beacon Transmission Time
832 * (TBTT) with a random backoff.
833 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
834 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
835 * until properly handled
836 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
837 * errors. These types of errors we can enable seem to be of type
838 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
4c674c60 839 * @AR5K_INT_GLOBAL: Used to clear and set the IER
fa1c114f
JS		 840 * @AR5K_INT_NOCARD: signals the card has been removed
841 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
842 * bit value
843 *
844 * These are mapped to take advantage of some common bits
845 * between the MACs, to be able to set intr properties
846 * easier. Some of them are not used yet inside hw.c. Most map
847 * to the respective hw interrupt value as they are common amogst different
848 * MACs.
849 */
850enum ath5k_int {
4c674c60 851 AR5K_INT_RXOK = 0x00000001,
fa1c114f 852 AR5K_INT_RXDESC = 0x00000002,
4c674c60 853 AR5K_INT_RXERR = 0x00000004,
fa1c114f
JS		 854 AR5K_INT_RXNOFRM = 0x00000008,
855 AR5K_INT_RXEOL = 0x00000010,
856 AR5K_INT_RXORN = 0x00000020,
4c674c60 857 AR5K_INT_TXOK = 0x00000040,
fa1c114f 858 AR5K_INT_TXDESC = 0x00000080,
4c674c60
NK		 859 AR5K_INT_TXERR = 0x00000100,
860 AR5K_INT_TXNOFRM = 0x00000200,
861 AR5K_INT_TXEOL = 0x00000400,
fa1c114f
JS		 862 AR5K_INT_TXURN = 0x00000800,
863 AR5K_INT_MIB = 0x00001000,
4c674c60 864 AR5K_INT_SWI = 0x00002000,
fa1c114f
JS		 865 AR5K_INT_RXPHY = 0x00004000,
866 AR5K_INT_RXKCM = 0x00008000,
867 AR5K_INT_SWBA = 0x00010000,
4c674c60 868 AR5K_INT_BRSSI = 0x00020000,
fa1c114f 869 AR5K_INT_BMISS = 0x00040000,
4c674c60
NK		 870 AR5K_INT_FATAL = 0x00080000, /* Non common */
871 AR5K_INT_BNR = 0x00100000, /* Non common */
872 AR5K_INT_TIM = 0x00200000, /* Non common */
873 AR5K_INT_DTIM = 0x00400000, /* Non common */
874 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
875 AR5K_INT_GPIO = 0x01000000,
876 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
877 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
878 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */
879 AR5K_INT_QCBRORN = 0x10000000, /* Non common */
880 AR5K_INT_QCBRURN = 0x20000000, /* Non common */
881 AR5K_INT_QTRIG = 0x40000000, /* Non common */
882 AR5K_INT_GLOBAL = 0x80000000,
883
884 AR5K_INT_COMMON = AR5K_INT_RXOK
885 | AR5K_INT_RXDESC
886 | AR5K_INT_RXERR
887 | AR5K_INT_RXNOFRM
888 | AR5K_INT_RXEOL
889 | AR5K_INT_RXORN
890 | AR5K_INT_TXOK
891 | AR5K_INT_TXDESC
892 | AR5K_INT_TXERR
893 | AR5K_INT_TXNOFRM
894 | AR5K_INT_TXEOL
895 | AR5K_INT_TXURN
896 | AR5K_INT_MIB
897 | AR5K_INT_SWI
898 | AR5K_INT_RXPHY
899 | AR5K_INT_RXKCM
900 | AR5K_INT_SWBA
901 | AR5K_INT_BRSSI
902 | AR5K_INT_BMISS
903 | AR5K_INT_GPIO
904 | AR5K_INT_GLOBAL,
905
fa1c114f
JS		 906 AR5K_INT_NOCARD = 0xffffffff
907};
908
909/*
910 * Power management
911 */
912enum ath5k_power_mode {
913 AR5K_PM_UNDEFINED = 0,
914 AR5K_PM_AUTO,
915 AR5K_PM_AWAKE,
916 AR5K_PM_FULL_SLEEP,
917 AR5K_PM_NETWORK_SLEEP,
918};
919
920/*
921 * These match net80211 definitions (not used in
c6e387a2
NK		 922 * mac80211).
923 * TODO: Clean this up
fa1c114f
JS		 924 */
925#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
926#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
927#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
928#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
929#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
930
931/* GPIO-controlled software LED */
932#define AR5K_SOFTLED_PIN 0
933#define AR5K_SOFTLED_ON 0
934#define AR5K_SOFTLED_OFF 1
935
936/*
937 * Chipset capabilities -see ath5k_hw_get_capability-
938 * get_capability function is not yet fully implemented
c6e387a2
NK		 939 * in ath5k so most of these don't work yet...
940 * TODO: Implement these & merge with _TUNE_ stuff above
fa1c114f
JS		 941 */
942enum ath5k_capability_type {
943 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
944 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
945 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
946 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
947 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
948 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
949 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
950 AR5K_CAP_COMPRESSION = 8, /* Supports compression */
951 AR5K_CAP_BURST = 9, /* Supports packet bursting */
952 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
953 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
954 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
955 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
956 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
957 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
958 AR5K_CAP_XR = 16, /* Supports XR mode */
959 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
960 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
961 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
962 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
963};
964
400ec45a
LR		 965
966/* XXX: we *may* move cap_range stuff to struct wiphy */
fa1c114f
JS		 967struct ath5k_capabilities {
968 /*
969 * Supported PHY modes
970 * (ie. CHANNEL_A, CHANNEL_B, ...)
971 */
d8ee398d 972 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
fa1c114f
JS		 973
974 /*
975 * Frequency range (without regulation restrictions)
976 */
977 struct {
978 u16 range_2ghz_min;
979 u16 range_2ghz_max;
980 u16 range_5ghz_min;
981 u16 range_5ghz_max;
982 } cap_range;
983
fa1c114f
JS		 984 /*
985 * Values stored in the EEPROM (some of them...)
986 */
987 struct ath5k_eeprom_info cap_eeprom;
988
989 /*
990 * Queue information
991 */
992 struct {
993 u8 q_tx_num;
994 } cap_queues;
995};
996
997
998/***************************************\
999 HARDWARE ABSTRACTION LAYER STRUCTURE
1000\***************************************/
1001
1002/*
1003 * Misc defines
1004 */
1005
1006#define AR5K_MAX_GPIO 10
1007#define AR5K_MAX_RF_BANKS 8
1008
c6e387a2 1009/* TODO: Clean up and merge with ath5k_softc */
fa1c114f
JS		 1010struct ath5k_hw {
1011 u32 ah_magic;
1012
1013 struct ath5k_softc *ah_sc;
1014 void __iomem *ah_iobase;
1015
1016 enum ath5k_int ah_imr;
1017
05c914fe 1018 enum nl80211_iftype ah_op_mode;
fa1c114f
JS		 1019 enum ath5k_power_mode ah_power_mode;
1020 struct ieee80211_channel ah_current_channel;
1021 bool ah_turbo;
1022 bool ah_calibration;
1023 bool ah_running;
1024 bool ah_single_chip;
f650470a 1025 bool ah_combined_mic;
fa1c114f
JS		 1026
1027 u32 ah_mac_srev;
1028 u16 ah_mac_version;
1029 u16 ah_mac_revision;
1030 u16 ah_phy_revision;
1031 u16 ah_radio_5ghz_revision;
1032 u16 ah_radio_2ghz_revision;
0af22563 1033 u32 ah_phy_spending;
fa1c114f
JS		 1034
1035 enum ath5k_version ah_version;
1036 enum ath5k_radio ah_radio;
1037 u32 ah_phy;
1038
1039 bool ah_5ghz;
1040 bool ah_2ghz;
1041
1042#define ah_regdomain ah_capabilities.cap_regdomain.reg_current
1043#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw
1044#define ah_modes ah_capabilities.cap_mode
1045#define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1046
1047 u32 ah_atim_window;
1048 u32 ah_aifs;
1049 u32 ah_cw_min;
1050 u32 ah_cw_max;
1051 bool ah_software_retry;
1052 u32 ah_limit_tx_retries;
1053
1054 u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1055 bool ah_ant_diversity;
1056
1057 u8 ah_sta_id[ETH_ALEN];
1058
f07a6c49 1059 /* Current BSSID we are trying to assoc to / create.
fa1c114f
JS		 1060 * This is passed by mac80211 on config_interface() and cached here for
1061 * use in resets */
1062 u8 ah_bssid[ETH_ALEN];
f07a6c49 1063 u8 ah_bssid_mask[ETH_ALEN];
fa1c114f
JS		 1064
1065 u32 ah_gpio[AR5K_MAX_GPIO];
1066 int ah_gpio_npins;
1067
1068 struct ath5k_capabilities ah_capabilities;
1069
1070 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1071 u32 ah_txq_status;
1072 u32 ah_txq_imr_txok;
1073 u32 ah_txq_imr_txerr;
1074 u32 ah_txq_imr_txurn;
1075 u32 ah_txq_imr_txdesc;
1076 u32 ah_txq_imr_txeol;
4c674c60
NK		 1077 u32 ah_txq_imr_cbrorn;
1078 u32 ah_txq_imr_cbrurn;
1079 u32 ah_txq_imr_qtrig;
1080 u32 ah_txq_imr_nofrm;
1081 u32 ah_txq_isr;
fa1c114f
JS		 1082 u32 *ah_rf_banks;
1083 size_t ah_rf_banks_size;
8892e4ec 1084 size_t ah_rf_regs_count;
fa1c114f 1085 struct ath5k_gain ah_gain;
8892e4ec 1086 u8 ah_offset[AR5K_MAX_RF_BANKS];
fa1c114f
JS		 1087
1088 struct {
1089 u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
1090 u16 txp_rates[AR5K_MAX_RATES];
1091 s16 txp_min;
1092 s16 txp_max;
1093 bool txp_tpc;
1094 s16 txp_ofdm;
1095 } ah_txpower;
1096
1097 struct {
1098 bool r_enabled;
1099 int r_last_alert;
1100 struct ieee80211_channel r_last_channel;
1101 } ah_radar;
1102
1103 /* noise floor from last periodic calibration */
1104 s32 ah_noise_floor;
1105
1106 /*
1107 * Function pointers
1108 */
c6e387a2
NK		 1109 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
1110 u32 size, unsigned int flags);
fa1c114f
JS		 1111 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1112 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
1113 unsigned int, unsigned int, unsigned int, unsigned int,
1114 unsigned int, unsigned int, unsigned int);
c6e387a2 1115 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
fa1c114f
JS		 1116 unsigned int, unsigned int, unsigned int, unsigned int,
1117 unsigned int, unsigned int);
b47f407b
BR		 1118 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1119 struct ath5k_tx_status *);
1120 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1121 struct ath5k_rx_status *);
fa1c114f
JS		 1122};
1123
1124/*
1125 * Prototypes
1126 */
1127
fa1c114f
JS		 1128/* Attach/Detach Functions */
1129extern struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version);
fa1c114f 1130extern void ath5k_hw_detach(struct ath5k_hw *ah);
c6e387a2 1131
fa1c114f 1132/* Reset Functions */
c6e387a2 1133extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
05c914fe 1134extern int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, struct ieee80211_channel *channel, bool change_channel);
fa1c114f
JS		 1135/* Power management functions */
1136extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
c6e387a2 1137
fa1c114f 1138/* DMA Related Functions */
c6e387a2 1139extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
fa1c114f 1140extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
c6e387a2
NK		 1141extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1142extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1143extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
fa1c114f 1144extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
c6e387a2
NK		 1145extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1146extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1147 u32 phys_addr);
fa1c114f
JS		 1148extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1149/* Interrupt handling */
1150extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1151extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
c6e387a2
NK		 1152extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum
1153ath5k_int new_mask);
194828a2 1154extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_low_level_stats *stats);
c6e387a2 1155
fa1c114f 1156/* EEPROM access functions */
c6e387a2
NK		 1157extern int ath5k_eeprom_init(struct ath5k_hw *ah);
1158extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
1159
fa1c114f
JS		 1160/* Protocol Control Unit Functions */
1161extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
1162/* BSSID Functions */
1163extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
1164extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1165extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
1166extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1167/* Receive start/stop functions */
1168extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
c6e387a2 1169extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
fa1c114f
JS		 1170/* RX Filter functions */
1171extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
c6e387a2 1172extern int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
fa1c114f
JS		 1173extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
1174extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1175extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
c6e387a2 1176/* Beacon control functions */
fa1c114f
JS		 1177extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah);
1178extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
8cab7581 1179extern void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
fa1c114f
JS		 1180extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1181extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1182#if 0
1183extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_beacon_state *state);
1184extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
1185extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
1186#endif
fa1c114f
JS		 1187/* ACK bit rate */
1188void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1189/* ACK/CTS Timeouts */
1190extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
1191extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
1192extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
1193extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
1194/* Key table (WEP) functions */
1195extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1196extern int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry);
1197extern int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac);
1198extern int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
c6e387a2 1199
fa1c114f 1200/* Queue Control Unit, DFS Control Unit Functions */
fa1c114f 1201extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info);
c6e387a2
NK		 1202extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1203 const struct ath5k_txq_info *queue_info);
1204extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1205 enum ath5k_tx_queue queue_type,
1206 struct ath5k_txq_info *queue_info);
1207extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
fa1c114f
JS		 1208extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1209extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
fa1c114f 1210extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah);
c6e387a2
NK		 1211extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1212
fa1c114f 1213/* Hardware Descriptor Functions */
c6e387a2
NK		 1214extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1215
fa1c114f
JS		 1216/* GPIO Functions */
1217extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
fa1c114f 1218extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
c6e387a2 1219extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
fa1c114f
JS		 1220extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1221extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1222extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
c6e387a2 1223
fa1c114f 1224/* Misc functions */
c6e387a2 1225int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
fa1c114f 1226extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
c6e387a2
NK		 1227extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1228extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
fa1c114f
JS		 1229
1230/* Initial register settings functions */
1231extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
c6e387a2 1232
fa1c114f 1233/* Initialize RF */
8892e4ec
NK		 1234extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
1235 struct ieee80211_channel *channel,
1236 unsigned int mode);
6f3b414a
NK		 1237extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
1238extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1239extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
fa1c114f
JS		 1240/* PHY/RF channel functions */
1241extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1242extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1243/* PHY calibration */
1244extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel);
c6e387a2 1245extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
fa1c114f
JS		 1246/* Misc PHY functions */
1247extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1248extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
1249extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
c6e387a2 1250extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
fa1c114f
JS		 1251/* TX power setup */
1252extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int txpower);
1253extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power);
1254
c6e387a2
NK		 1255/*
1256 * Functions used internaly
1257 */
1258
1259/*
1260 * Translate usec to hw clock units
1261 */
1262static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
1263{
1264 return turbo ? (usec * 80) : (usec * 40);
1265}
fa1c114f 1266
c6e387a2
NK		 1267/*
1268 * Translate hw clock units to usec
1269 */
1270static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
1271{
1272 return turbo ? (clock / 80) : (clock / 40);
1273}
1274
1275/*
1276 * Read from a register
1277 */
fa1c114f
JS		 1278static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1279{
1280 return ioread32(ah->ah_iobase + reg);
1281}
1282
c6e387a2
NK		 1283/*
1284 * Write to a register
1285 */
fa1c114f
JS		 1286static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1287{
1288 iowrite32(val, ah->ah_iobase + reg);
1289}
1290
c6e387a2
NK		 1291#if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
1292/*
1293 * Check if a register write has been completed
1294 */
1295static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
1296 u32 val, bool is_set)
1297{
1298 int i;
1299 u32 data;
1300
1301 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
1302 data = ath5k_hw_reg_read(ah, reg);
1303 if (is_set && (data & flag))
1304 break;
1305 else if ((data & flag) == val)
1306 break;
1307 udelay(15);
1308 }
1309
1310 return (i <= 0) ? -EAGAIN : 0;
1311}
1312#endif
1313
1314static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1315{
1316 u32 retval = 0, bit, i;
1317
1318 for (i = 0; i < bits; i++) {
1319 bit = (val >> i) & 1;
1320 retval = (retval << 1) | bit;
1321 }
1322
1323 return retval;
1324}
1325
fd6effca
BC		 1326static inline int ath5k_pad_size(int hdrlen)
1327{
1328 return (hdrlen < 24) ? 0 : hdrlen & 3;
1329}
1330
fa1c114f 1331#endif
Linux kernel - Deliverables
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