Commit | Line | Data |
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f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | /* Implementation of beacon processing. */ | |
18 | ||
f078f209 LR |
19 | #include "core.h" |
20 | ||
21 | /* | |
22 | * Configure parameters for the beacon queue | |
23 | * | |
24 | * This function will modify certain transmit queue properties depending on | |
25 | * the operating mode of the station (AP or AdHoc). Parameters are AIFS | |
26 | * settings and channel width min/max | |
27 | */ | |
f078f209 LR |
28 | static int ath_beaconq_config(struct ath_softc *sc) |
29 | { | |
30 | struct ath_hal *ah = sc->sc_ah; | |
ea9880fb | 31 | struct ath9k_tx_queue_info qi; |
f078f209 | 32 | |
ea9880fb | 33 | ath9k_hw_get_txq_props(ah, sc->sc_bhalq, &qi); |
b4696c8b | 34 | if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) { |
f078f209 LR |
35 | /* Always burst out beacon and CAB traffic. */ |
36 | qi.tqi_aifs = 1; | |
37 | qi.tqi_cwmin = 0; | |
38 | qi.tqi_cwmax = 0; | |
39 | } else { | |
40 | /* Adhoc mode; important thing is to use 2x cwmin. */ | |
41 | qi.tqi_aifs = sc->sc_beacon_qi.tqi_aifs; | |
42 | qi.tqi_cwmin = 2*sc->sc_beacon_qi.tqi_cwmin; | |
43 | qi.tqi_cwmax = sc->sc_beacon_qi.tqi_cwmax; | |
44 | } | |
45 | ||
ea9880fb | 46 | if (!ath9k_hw_set_txq_props(ah, sc->sc_bhalq, &qi)) { |
f078f209 LR |
47 | DPRINTF(sc, ATH_DBG_FATAL, |
48 | "%s: unable to update h/w beacon queue parameters\n", | |
49 | __func__); | |
50 | return 0; | |
51 | } else { | |
52 | ath9k_hw_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ | |
53 | return 1; | |
54 | } | |
55 | } | |
56 | ||
57 | /* | |
58 | * Setup the beacon frame for transmit. | |
59 | * | |
60 | * Associates the beacon frame buffer with a transmit descriptor. Will set | |
61 | * up all required antenna switch parameters, rate codes, and channel flags. | |
62 | * Beacons are always sent out at the lowest rate, and are not retried. | |
63 | */ | |
f078f209 | 64 | static void ath_beacon_setup(struct ath_softc *sc, |
980b24da | 65 | struct ath_vap *avp, struct ath_buf *bf) |
f078f209 LR |
66 | { |
67 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; | |
68 | struct ath_hal *ah = sc->sc_ah; | |
69 | struct ath_desc *ds; | |
980b24da | 70 | struct ath9k_11n_rate_series series[4]; |
f078f209 | 71 | const struct ath9k_rate_table *rt; |
980b24da | 72 | int flags, antenna; |
f078f209 LR |
73 | u8 rix, rate; |
74 | int ctsrate = 0; | |
75 | int ctsduration = 0; | |
f078f209 LR |
76 | |
77 | DPRINTF(sc, ATH_DBG_BEACON, "%s: m %p len %u\n", | |
78 | __func__, skb, skb->len); | |
79 | ||
80 | /* setup descriptors */ | |
81 | ds = bf->bf_desc; | |
82 | ||
83 | flags = ATH9K_TXDESC_NOACK; | |
84 | ||
b4696c8b | 85 | if (sc->sc_ah->ah_opmode == ATH9K_M_IBSS && |
60b67f51 | 86 | (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { |
f078f209 LR |
87 | ds->ds_link = bf->bf_daddr; /* self-linked */ |
88 | flags |= ATH9K_TXDESC_VEOL; | |
89 | /* Let hardware handle antenna switching. */ | |
90 | antenna = 0; | |
91 | } else { | |
92 | ds->ds_link = 0; | |
93 | /* | |
94 | * Switch antenna every beacon. | |
95 | * Should only switch every beacon period, not for every | |
96 | * SWBA's | |
97 | * XXX assumes two antenna | |
98 | */ | |
99 | antenna = ((sc->ast_be_xmit / sc->sc_nbcnvaps) & 1 ? 2 : 1); | |
100 | } | |
101 | ||
102 | ds->ds_data = bf->bf_buf_addr; | |
103 | ||
104 | /* | |
105 | * Calculate rate code. | |
106 | * XXX everything at min xmit rate | |
107 | */ | |
86b89eed | 108 | rix = 0; |
f078f209 LR |
109 | rt = sc->sc_currates; |
110 | rate = rt->info[rix].rateCode; | |
672840ac | 111 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) |
f078f209 LR |
112 | rate |= rt->info[rix].shortPreamble; |
113 | ||
ff9b662d | 114 | ath9k_hw_set11n_txdesc(ah, ds, |
980b24da S |
115 | skb->len + FCS_LEN, /* frame length */ |
116 | ATH9K_PKT_TYPE_BEACON, /* Atheros packet type */ | |
ff9b662d | 117 | avp->av_btxctl.txpower, /* txpower XXX */ |
980b24da S |
118 | ATH9K_TXKEYIX_INVALID, /* no encryption */ |
119 | ATH9K_KEY_TYPE_CLEAR, /* no encryption */ | |
120 | flags /* no ack, | |
121 | veol for beacons */ | |
f078f209 LR |
122 | ); |
123 | ||
124 | /* NB: beacon's BufLen must be a multiple of 4 bytes */ | |
ff9b662d S |
125 | ath9k_hw_filltxdesc(ah, ds, |
126 | roundup(skb->len, 4), /* buffer length */ | |
980b24da S |
127 | true, /* first segment */ |
128 | true, /* last segment */ | |
129 | ds /* first descriptor */ | |
f078f209 LR |
130 | ); |
131 | ||
0345f37b | 132 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); |
f078f209 LR |
133 | series[0].Tries = 1; |
134 | series[0].Rate = rate; | |
135 | series[0].ChSel = sc->sc_tx_chainmask; | |
136 | series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0; | |
137 | ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, | |
138 | ctsrate, ctsduration, series, 4, 0); | |
139 | } | |
140 | ||
f078f209 LR |
141 | /* |
142 | * Generate beacon frame and queue cab data for a vap. | |
143 | * | |
144 | * Updates the contents of the beacon frame. It is assumed that the buffer for | |
145 | * the beacon frame has been allocated in the ATH object, and simply needs to | |
146 | * be filled for this cycle. Also, any CAB (crap after beacon?) traffic will | |
147 | * be added to the beacon frame at this point. | |
148 | */ | |
149 | static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) | |
150 | { | |
f078f209 LR |
151 | struct ath_buf *bf; |
152 | struct ath_vap *avp; | |
153 | struct sk_buff *skb; | |
f078f209 | 154 | struct ath_txq *cabq; |
147583c0 | 155 | struct ieee80211_tx_info *info; |
980b24da S |
156 | int cabq_depth; |
157 | ||
f078f209 | 158 | avp = sc->sc_vaps[if_id]; |
980b24da | 159 | ASSERT(avp); |
f078f209 | 160 | |
f078f209 LR |
161 | cabq = sc->sc_cabq; |
162 | ||
f078f209 LR |
163 | if (avp->av_bcbuf == NULL) { |
164 | DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n", | |
165 | __func__, avp, avp->av_bcbuf); | |
166 | return NULL; | |
167 | } | |
980b24da | 168 | |
f078f209 | 169 | bf = avp->av_bcbuf; |
980b24da | 170 | skb = (struct sk_buff *)bf->bf_mpdu; |
a8fff50e JM |
171 | if (skb) { |
172 | pci_unmap_single(sc->pdev, bf->bf_dmacontext, | |
173 | skb_end_pointer(skb) - skb->head, | |
174 | PCI_DMA_TODEVICE); | |
175 | } | |
f078f209 | 176 | |
a8fff50e JM |
177 | skb = ieee80211_beacon_get(sc->hw, avp->av_if_data); |
178 | bf->bf_mpdu = skb; | |
179 | if (skb == NULL) | |
180 | return NULL; | |
980b24da | 181 | |
147583c0 JM |
182 | info = IEEE80211_SKB_CB(skb); |
183 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
184 | /* | |
185 | * TODO: make sure the seq# gets assigned properly (vs. other | |
186 | * TX frames) | |
187 | */ | |
980b24da | 188 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
147583c0 JM |
189 | sc->seq_no += 0x10; |
190 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
191 | hdr->seq_ctrl |= cpu_to_le16(sc->seq_no); | |
192 | } | |
980b24da | 193 | |
a8fff50e JM |
194 | bf->bf_buf_addr = bf->bf_dmacontext = |
195 | pci_map_single(sc->pdev, skb->data, | |
196 | skb_end_pointer(skb) - skb->head, | |
197 | PCI_DMA_TODEVICE); | |
f078f209 | 198 | |
e022edbd | 199 | skb = ieee80211_get_buffered_bc(sc->hw, avp->av_if_data); |
f078f209 | 200 | |
f078f209 LR |
201 | /* |
202 | * if the CABQ traffic from previous DTIM is pending and the current | |
203 | * beacon is also a DTIM. | |
204 | * 1) if there is only one vap let the cab traffic continue. | |
205 | * 2) if there are more than one vap and we are using staggered | |
206 | * beacons, then drain the cabq by dropping all the frames in | |
207 | * the cabq so that the current vaps cab traffic can be scheduled. | |
208 | */ | |
209 | spin_lock_bh(&cabq->axq_lock); | |
210 | cabq_depth = cabq->axq_depth; | |
211 | spin_unlock_bh(&cabq->axq_lock); | |
212 | ||
e022edbd | 213 | if (skb && cabq_depth) { |
f078f209 LR |
214 | /* |
215 | * Unlock the cabq lock as ath_tx_draintxq acquires | |
216 | * the lock again which is a common function and that | |
217 | * acquires txq lock inside. | |
218 | */ | |
219 | if (sc->sc_nvaps > 1) { | |
220 | ath_tx_draintxq(sc, cabq, false); | |
221 | DPRINTF(sc, ATH_DBG_BEACON, | |
222 | "%s: flush previous cabq traffic\n", __func__); | |
223 | } | |
224 | } | |
225 | ||
226 | /* Construct tx descriptor. */ | |
227 | ath_beacon_setup(sc, avp, bf); | |
228 | ||
229 | /* | |
230 | * Enable the CAB queue before the beacon queue to | |
231 | * insure cab frames are triggered by this beacon. | |
232 | */ | |
e022edbd JM |
233 | while (skb) { |
234 | ath_tx_cabq(sc, skb); | |
235 | skb = ieee80211_get_buffered_bc(sc->hw, avp->av_if_data); | |
236 | } | |
f078f209 | 237 | |
f078f209 LR |
238 | return bf; |
239 | } | |
240 | ||
241 | /* | |
242 | * Startup beacon transmission for adhoc mode when they are sent entirely | |
243 | * by the hardware using the self-linked descriptor + veol trick. | |
244 | */ | |
f078f209 LR |
245 | static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id) |
246 | { | |
247 | struct ath_hal *ah = sc->sc_ah; | |
248 | struct ath_buf *bf; | |
249 | struct ath_vap *avp; | |
250 | struct sk_buff *skb; | |
251 | ||
252 | avp = sc->sc_vaps[if_id]; | |
253 | ASSERT(avp); | |
254 | ||
255 | if (avp->av_bcbuf == NULL) { | |
256 | DPRINTF(sc, ATH_DBG_BEACON, "%s: avp=%p av_bcbuf=%p\n", | |
257 | __func__, avp, avp != NULL ? avp->av_bcbuf : NULL); | |
258 | return; | |
259 | } | |
260 | bf = avp->av_bcbuf; | |
261 | skb = (struct sk_buff *) bf->bf_mpdu; | |
262 | ||
263 | /* Construct tx descriptor. */ | |
264 | ath_beacon_setup(sc, avp, bf); | |
265 | ||
266 | /* NB: caller is known to have already stopped tx dma */ | |
267 | ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); | |
268 | ath9k_hw_txstart(ah, sc->sc_bhalq); | |
269 | DPRINTF(sc, ATH_DBG_BEACON, "%s: TXDP%u = %llx (%p)\n", __func__, | |
270 | sc->sc_bhalq, ito64(bf->bf_daddr), bf->bf_desc); | |
271 | } | |
272 | ||
273 | /* | |
274 | * Setup a h/w transmit queue for beacons. | |
275 | * | |
276 | * This function allocates an information structure (struct ath9k_txq_info) | |
277 | * on the stack, sets some specific parameters (zero out channel width | |
278 | * min/max, and enable aifs). The info structure does not need to be | |
279 | * persistant. | |
280 | */ | |
f078f209 LR |
281 | int ath_beaconq_setup(struct ath_hal *ah) |
282 | { | |
ea9880fb | 283 | struct ath9k_tx_queue_info qi; |
f078f209 | 284 | |
0345f37b | 285 | memset(&qi, 0, sizeof(qi)); |
f078f209 LR |
286 | qi.tqi_aifs = 1; |
287 | qi.tqi_cwmin = 0; | |
288 | qi.tqi_cwmax = 0; | |
289 | /* NB: don't enable any interrupts */ | |
290 | return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi); | |
291 | } | |
292 | ||
293 | ||
294 | /* | |
295 | * Allocate and setup an initial beacon frame. | |
296 | * | |
297 | * Allocate a beacon state variable for a specific VAP instance created on | |
298 | * the ATH interface. This routine also calculates the beacon "slot" for | |
299 | * staggared beacons in the mBSSID case. | |
300 | */ | |
f078f209 LR |
301 | int ath_beacon_alloc(struct ath_softc *sc, int if_id) |
302 | { | |
303 | struct ath_vap *avp; | |
980b24da | 304 | struct ieee80211_hdr *hdr; |
f078f209 LR |
305 | struct ath_buf *bf; |
306 | struct sk_buff *skb; | |
459f5f90 | 307 | __le64 tstamp; |
f078f209 LR |
308 | |
309 | avp = sc->sc_vaps[if_id]; | |
310 | ASSERT(avp); | |
311 | ||
312 | /* Allocate a beacon descriptor if we haven't done so. */ | |
313 | if (!avp->av_bcbuf) { | |
980b24da S |
314 | /* Allocate beacon state for hostap/ibss. We know |
315 | * a buffer is available. */ | |
f078f209 LR |
316 | |
317 | avp->av_bcbuf = list_first_entry(&sc->sc_bbuf, | |
980b24da | 318 | struct ath_buf, list); |
f078f209 LR |
319 | list_del(&avp->av_bcbuf->list); |
320 | ||
b4696c8b | 321 | if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP || |
60b67f51 | 322 | !(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { |
f078f209 LR |
323 | int slot; |
324 | /* | |
325 | * Assign the vap to a beacon xmit slot. As | |
326 | * above, this cannot fail to find one. | |
327 | */ | |
328 | avp->av_bslot = 0; | |
329 | for (slot = 0; slot < ATH_BCBUF; slot++) | |
330 | if (sc->sc_bslot[slot] == ATH_IF_ID_ANY) { | |
331 | /* | |
332 | * XXX hack, space out slots to better | |
333 | * deal with misses | |
334 | */ | |
335 | if (slot+1 < ATH_BCBUF && | |
336 | sc->sc_bslot[slot+1] == | |
337 | ATH_IF_ID_ANY) { | |
338 | avp->av_bslot = slot+1; | |
339 | break; | |
340 | } | |
341 | avp->av_bslot = slot; | |
342 | /* NB: keep looking for a double slot */ | |
343 | } | |
344 | BUG_ON(sc->sc_bslot[avp->av_bslot] != ATH_IF_ID_ANY); | |
345 | sc->sc_bslot[avp->av_bslot] = if_id; | |
346 | sc->sc_nbcnvaps++; | |
347 | } | |
348 | } | |
349 | ||
350 | /* release the previous beacon frame , if it already exists. */ | |
351 | bf = avp->av_bcbuf; | |
352 | if (bf->bf_mpdu != NULL) { | |
353 | skb = (struct sk_buff *)bf->bf_mpdu; | |
a8fff50e JM |
354 | pci_unmap_single(sc->pdev, bf->bf_dmacontext, |
355 | skb_end_pointer(skb) - skb->head, | |
356 | PCI_DMA_TODEVICE); | |
f078f209 LR |
357 | dev_kfree_skb_any(skb); |
358 | bf->bf_mpdu = NULL; | |
359 | } | |
360 | ||
361 | /* | |
980b24da | 362 | * NB: the beacon data buffer must be 32-bit aligned. |
e022edbd | 363 | * FIXME: Fill avp->av_btxctl.txpower and |
f078f209 LR |
364 | * avp->av_btxctl.shortPreamble |
365 | */ | |
366 | skb = ieee80211_beacon_get(sc->hw, avp->av_if_data); | |
367 | if (skb == NULL) { | |
368 | DPRINTF(sc, ATH_DBG_BEACON, "%s: cannot get skb\n", | |
369 | __func__); | |
370 | return -ENOMEM; | |
371 | } | |
372 | ||
459f5f90 S |
373 | tstamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp; |
374 | sc->bc_tstamp = le64_to_cpu(tstamp); | |
375 | ||
f078f209 LR |
376 | /* |
377 | * Calculate a TSF adjustment factor required for | |
378 | * staggered beacons. Note that we assume the format | |
379 | * of the beacon frame leaves the tstamp field immediately | |
380 | * following the header. | |
381 | */ | |
382 | if (avp->av_bslot > 0) { | |
383 | u64 tsfadjust; | |
384 | __le64 val; | |
385 | int intval; | |
386 | ||
a8fff50e JM |
387 | intval = sc->hw->conf.beacon_int ? |
388 | sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL; | |
f078f209 LR |
389 | |
390 | /* | |
391 | * The beacon interval is in TU's; the TSF in usecs. | |
392 | * We figure out how many TU's to add to align the | |
393 | * timestamp then convert to TSF units and handle | |
394 | * byte swapping before writing it in the frame. | |
395 | * The hardware will then add this each time a beacon | |
396 | * frame is sent. Note that we align vap's 1..N | |
397 | * and leave vap 0 untouched. This means vap 0 | |
398 | * has a timestamp in one beacon interval while the | |
399 | * others get a timestamp aligned to the next interval. | |
400 | */ | |
401 | tsfadjust = (intval * (ATH_BCBUF - avp->av_bslot)) / ATH_BCBUF; | |
402 | val = cpu_to_le64(tsfadjust << 10); /* TU->TSF */ | |
403 | ||
404 | DPRINTF(sc, ATH_DBG_BEACON, | |
405 | "%s: %s beacons, bslot %d intval %u tsfadjust %llu\n", | |
406 | __func__, "stagger", | |
407 | avp->av_bslot, intval, (unsigned long long)tsfadjust); | |
408 | ||
980b24da S |
409 | hdr = (struct ieee80211_hdr *)skb->data; |
410 | memcpy(&hdr[1], &val, sizeof(val)); | |
f078f209 LR |
411 | } |
412 | ||
a8fff50e JM |
413 | bf->bf_buf_addr = bf->bf_dmacontext = |
414 | pci_map_single(sc->pdev, skb->data, | |
415 | skb_end_pointer(skb) - skb->head, | |
416 | PCI_DMA_TODEVICE); | |
f078f209 LR |
417 | bf->bf_mpdu = skb; |
418 | ||
419 | return 0; | |
420 | } | |
421 | ||
422 | /* | |
423 | * Reclaim beacon resources and return buffer to the pool. | |
424 | * | |
425 | * Checks the VAP to put the beacon frame buffer back to the ATH object | |
980b24da | 426 | * queue, and de-allocates any skbs that were sent as CAB traffic. |
f078f209 | 427 | */ |
f078f209 LR |
428 | void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp) |
429 | { | |
430 | if (avp->av_bcbuf != NULL) { | |
431 | struct ath_buf *bf; | |
432 | ||
433 | if (avp->av_bslot != -1) { | |
434 | sc->sc_bslot[avp->av_bslot] = ATH_IF_ID_ANY; | |
435 | sc->sc_nbcnvaps--; | |
436 | } | |
437 | ||
438 | bf = avp->av_bcbuf; | |
439 | if (bf->bf_mpdu != NULL) { | |
440 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; | |
a8fff50e JM |
441 | pci_unmap_single(sc->pdev, bf->bf_dmacontext, |
442 | skb_end_pointer(skb) - skb->head, | |
443 | PCI_DMA_TODEVICE); | |
f078f209 LR |
444 | dev_kfree_skb_any(skb); |
445 | bf->bf_mpdu = NULL; | |
446 | } | |
447 | list_add_tail(&bf->list, &sc->sc_bbuf); | |
448 | ||
449 | avp->av_bcbuf = NULL; | |
450 | } | |
451 | } | |
452 | ||
f078f209 LR |
453 | /* |
454 | * Tasklet for Sending Beacons | |
455 | * | |
456 | * Transmit one or more beacon frames at SWBA. Dynamic updates to the frame | |
457 | * contents are done as needed and the slot time is also adjusted based on | |
458 | * current state. | |
f078f209 | 459 | */ |
f078f209 LR |
460 | void ath9k_beacon_tasklet(unsigned long data) |
461 | { | |
f078f209 LR |
462 | struct ath_softc *sc = (struct ath_softc *)data; |
463 | struct ath_hal *ah = sc->sc_ah; | |
464 | struct ath_buf *bf = NULL; | |
465 | int slot, if_id; | |
466 | u32 bfaddr; | |
467 | u32 rx_clear = 0, rx_frame = 0, tx_frame = 0; | |
468 | u32 show_cycles = 0; | |
469 | u32 bc = 0; /* beacon count */ | |
470 | u64 tsf; | |
471 | u32 tsftu; | |
472 | u16 intval; | |
473 | ||
98deeea0 | 474 | if (sc->sc_flags & SC_OP_NO_RESET) { |
f078f209 LR |
475 | show_cycles = ath9k_hw_GetMibCycleCountsPct(ah, |
476 | &rx_clear, | |
477 | &rx_frame, | |
478 | &tx_frame); | |
479 | } | |
480 | ||
481 | /* | |
482 | * Check if the previous beacon has gone out. If | |
483 | * not don't try to post another, skip this period | |
484 | * and wait for the next. Missed beacons indicate | |
485 | * a problem and should not occur. If we miss too | |
486 | * many consecutive beacons reset the device. | |
980b24da S |
487 | * |
488 | * FIXME: Clean up this mess !! | |
f078f209 LR |
489 | */ |
490 | if (ath9k_hw_numtxpending(ah, sc->sc_bhalq) != 0) { | |
491 | sc->sc_bmisscount++; | |
492 | /* XXX: doth needs the chanchange IE countdown decremented. | |
493 | * We should consider adding a mac80211 call to indicate | |
494 | * a beacon miss so appropriate action could be taken | |
495 | * (in that layer). | |
496 | */ | |
497 | if (sc->sc_bmisscount < BSTUCK_THRESH) { | |
98deeea0 | 498 | if (sc->sc_flags & SC_OP_NO_RESET) { |
f078f209 LR |
499 | DPRINTF(sc, ATH_DBG_BEACON, |
500 | "%s: missed %u consecutive beacons\n", | |
501 | __func__, sc->sc_bmisscount); | |
502 | if (show_cycles) { | |
503 | /* | |
980b24da S |
504 | * Display cycle counter stats from HW |
505 | * to aide in debug of stickiness. | |
f078f209 | 506 | */ |
980b24da | 507 | DPRINTF(sc, ATH_DBG_BEACON, |
f078f209 LR |
508 | "%s: busy times: rx_clear=%d, " |
509 | "rx_frame=%d, tx_frame=%d\n", | |
510 | __func__, rx_clear, rx_frame, | |
511 | tx_frame); | |
512 | } else { | |
980b24da | 513 | DPRINTF(sc, ATH_DBG_BEACON, |
f078f209 LR |
514 | "%s: unable to obtain " |
515 | "busy times\n", __func__); | |
516 | } | |
517 | } else { | |
518 | DPRINTF(sc, ATH_DBG_BEACON, | |
519 | "%s: missed %u consecutive beacons\n", | |
520 | __func__, sc->sc_bmisscount); | |
521 | } | |
522 | } else if (sc->sc_bmisscount >= BSTUCK_THRESH) { | |
98deeea0 | 523 | if (sc->sc_flags & SC_OP_NO_RESET) { |
f078f209 | 524 | if (sc->sc_bmisscount == BSTUCK_THRESH) { |
980b24da | 525 | DPRINTF(sc, ATH_DBG_BEACON, |
f078f209 LR |
526 | "%s: beacon is officially " |
527 | "stuck\n", __func__); | |
528 | ath9k_hw_dmaRegDump(ah); | |
529 | } | |
530 | } else { | |
531 | DPRINTF(sc, ATH_DBG_BEACON, | |
532 | "%s: beacon is officially stuck\n", | |
533 | __func__); | |
534 | ath_bstuck_process(sc); | |
535 | } | |
536 | } | |
f078f209 LR |
537 | return; |
538 | } | |
980b24da | 539 | |
f078f209 | 540 | if (sc->sc_bmisscount != 0) { |
98deeea0 | 541 | if (sc->sc_flags & SC_OP_NO_RESET) { |
980b24da | 542 | DPRINTF(sc, ATH_DBG_BEACON, |
f078f209 LR |
543 | "%s: resume beacon xmit after %u misses\n", |
544 | __func__, sc->sc_bmisscount); | |
545 | } else { | |
546 | DPRINTF(sc, ATH_DBG_BEACON, | |
547 | "%s: resume beacon xmit after %u misses\n", | |
548 | __func__, sc->sc_bmisscount); | |
549 | } | |
550 | sc->sc_bmisscount = 0; | |
551 | } | |
552 | ||
553 | /* | |
554 | * Generate beacon frames. we are sending frames | |
555 | * staggered so calculate the slot for this frame based | |
556 | * on the tsf to safeguard against missing an swba. | |
557 | */ | |
558 | ||
a8fff50e JM |
559 | intval = sc->hw->conf.beacon_int ? |
560 | sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL; | |
f078f209 LR |
561 | |
562 | tsf = ath9k_hw_gettsf64(ah); | |
563 | tsftu = TSF_TO_TU(tsf>>32, tsf); | |
564 | slot = ((tsftu % intval) * ATH_BCBUF) / intval; | |
565 | if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF]; | |
980b24da | 566 | |
f078f209 | 567 | DPRINTF(sc, ATH_DBG_BEACON, |
980b24da S |
568 | "%s: slot %d [tsf %llu tsftu %u intval %u] if_id %d\n", |
569 | __func__, slot, (unsigned long long)tsf, tsftu, | |
570 | intval, if_id); | |
571 | ||
f078f209 LR |
572 | bfaddr = 0; |
573 | if (if_id != ATH_IF_ID_ANY) { | |
574 | bf = ath_beacon_generate(sc, if_id); | |
575 | if (bf != NULL) { | |
576 | bfaddr = bf->bf_daddr; | |
577 | bc = 1; | |
578 | } | |
579 | } | |
580 | /* | |
581 | * Handle slot time change when a non-ERP station joins/leaves | |
582 | * an 11g network. The 802.11 layer notifies us via callback, | |
583 | * we mark updateslot, then wait one beacon before effecting | |
584 | * the change. This gives associated stations at least one | |
585 | * beacon interval to note the state change. | |
586 | * | |
587 | * NB: The slot time change state machine is clocked according | |
588 | * to whether we are bursting or staggering beacons. We | |
589 | * recognize the request to update and record the current | |
590 | * slot then don't transition until that slot is reached | |
591 | * again. If we miss a beacon for that slot then we'll be | |
592 | * slow to transition but we'll be sure at least one beacon | |
593 | * interval has passed. When bursting slot is always left | |
594 | * set to ATH_BCBUF so this check is a noop. | |
595 | */ | |
596 | /* XXX locking */ | |
597 | if (sc->sc_updateslot == UPDATE) { | |
598 | sc->sc_updateslot = COMMIT; /* commit next beacon */ | |
599 | sc->sc_slotupdate = slot; | |
600 | } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) | |
601 | ath_setslottime(sc); /* commit change to hardware */ | |
602 | ||
603 | if (bfaddr != 0) { | |
604 | /* | |
605 | * Stop any current dma and put the new frame(s) on the queue. | |
606 | * This should never fail since we check above that no frames | |
607 | * are still pending on the queue. | |
608 | */ | |
609 | if (!ath9k_hw_stoptxdma(ah, sc->sc_bhalq)) { | |
610 | DPRINTF(sc, ATH_DBG_FATAL, | |
611 | "%s: beacon queue %u did not stop?\n", | |
612 | __func__, sc->sc_bhalq); | |
613 | /* NB: the HAL still stops DMA, so proceed */ | |
614 | } | |
615 | ||
616 | /* NB: cabq traffic should already be queued and primed */ | |
617 | ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bfaddr); | |
618 | ath9k_hw_txstart(ah, sc->sc_bhalq); | |
619 | ||
620 | sc->ast_be_xmit += bc; /* XXX per-vap? */ | |
621 | } | |
f078f209 LR |
622 | } |
623 | ||
624 | /* | |
625 | * Tasklet for Beacon Stuck processing | |
626 | * | |
627 | * Processing for Beacon Stuck. | |
980b24da | 628 | * Basically resets the chip. |
f078f209 | 629 | */ |
f078f209 LR |
630 | void ath_bstuck_process(struct ath_softc *sc) |
631 | { | |
632 | DPRINTF(sc, ATH_DBG_BEACON, | |
633 | "%s: stuck beacon; resetting (bmiss count %u)\n", | |
634 | __func__, sc->sc_bmisscount); | |
f45144ef | 635 | ath_reset(sc, false); |
f078f209 LR |
636 | } |
637 | ||
638 | /* | |
639 | * Configure the beacon and sleep timers. | |
640 | * | |
641 | * When operating as an AP this resets the TSF and sets | |
642 | * up the hardware to notify us when we need to issue beacons. | |
643 | * | |
644 | * When operating in station mode this sets up the beacon | |
645 | * timers according to the timestamp of the last received | |
646 | * beacon and the current TSF, configures PCF and DTIM | |
647 | * handling, programs the sleep registers so the hardware | |
648 | * will wakeup in time to receive beacons, and configures | |
649 | * the beacon miss handling so we'll receive a BMISS | |
650 | * interrupt when we stop seeing beacons from the AP | |
651 | * we've associated with. | |
652 | */ | |
f078f209 LR |
653 | void ath_beacon_config(struct ath_softc *sc, int if_id) |
654 | { | |
f078f209 | 655 | struct ath_hal *ah = sc->sc_ah; |
f078f209 LR |
656 | struct ath_beacon_config conf; |
657 | enum ath9k_opmode av_opmode; | |
980b24da | 658 | u32 nexttbtt, intval; |
f078f209 LR |
659 | |
660 | if (if_id != ATH_IF_ID_ANY) | |
661 | av_opmode = sc->sc_vaps[if_id]->av_opmode; | |
662 | else | |
b4696c8b | 663 | av_opmode = sc->sc_ah->ah_opmode; |
f078f209 | 664 | |
0345f37b | 665 | memset(&conf, 0, sizeof(struct ath_beacon_config)); |
f078f209 | 666 | |
a8fff50e JM |
667 | conf.beacon_interval = sc->hw->conf.beacon_int ? |
668 | sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL; | |
f078f209 LR |
669 | conf.listen_interval = 1; |
670 | conf.dtim_period = conf.beacon_interval; | |
671 | conf.dtim_count = 1; | |
672 | conf.bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf.beacon_interval; | |
673 | ||
674 | /* extract tstamp from last beacon and convert to TU */ | |
459f5f90 S |
675 | nexttbtt = TSF_TO_TU(sc->bc_tstamp >> 32, sc->bc_tstamp); |
676 | ||
f078f209 | 677 | /* XXX conditionalize multi-bss support? */ |
b4696c8b | 678 | if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) { |
f078f209 LR |
679 | /* |
680 | * For multi-bss ap support beacons are either staggered | |
681 | * evenly over N slots or burst together. For the former | |
682 | * arrange for the SWBA to be delivered for each slot. | |
683 | * Slots that are not occupied will generate nothing. | |
684 | */ | |
685 | /* NB: the beacon interval is kept internally in TU's */ | |
686 | intval = conf.beacon_interval & ATH9K_BEACON_PERIOD; | |
687 | intval /= ATH_BCBUF; /* for staggered beacons */ | |
688 | } else { | |
689 | intval = conf.beacon_interval & ATH9K_BEACON_PERIOD; | |
690 | } | |
691 | ||
980b24da | 692 | if (nexttbtt == 0) /* e.g. for ap mode */ |
f078f209 | 693 | nexttbtt = intval; |
980b24da | 694 | else if (intval) /* NB: can be 0 for monitor mode */ |
f078f209 | 695 | nexttbtt = roundup(nexttbtt, intval); |
980b24da | 696 | |
f078f209 LR |
697 | DPRINTF(sc, ATH_DBG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", |
698 | __func__, nexttbtt, intval, conf.beacon_interval); | |
980b24da | 699 | |
f078f209 | 700 | /* Check for ATH9K_M_HOSTAP and sc_nostabeacons for WDS client */ |
b4696c8b | 701 | if (sc->sc_ah->ah_opmode == ATH9K_M_STA) { |
f078f209 LR |
702 | struct ath9k_beacon_state bs; |
703 | u64 tsf; | |
704 | u32 tsftu; | |
705 | int dtimperiod, dtimcount, sleepduration; | |
706 | int cfpperiod, cfpcount; | |
707 | ||
708 | /* | |
709 | * Setup dtim and cfp parameters according to | |
710 | * last beacon we received (which may be none). | |
711 | */ | |
712 | dtimperiod = conf.dtim_period; | |
980b24da | 713 | if (dtimperiod <= 0) /* NB: 0 if not known */ |
f078f209 LR |
714 | dtimperiod = 1; |
715 | dtimcount = conf.dtim_count; | |
980b24da S |
716 | if (dtimcount >= dtimperiod) /* NB: sanity check */ |
717 | dtimcount = 0; | |
718 | cfpperiod = 1; /* NB: no PCF support yet */ | |
f078f209 LR |
719 | cfpcount = 0; |
720 | ||
721 | sleepduration = conf.listen_interval * intval; | |
722 | if (sleepduration <= 0) | |
723 | sleepduration = intval; | |
724 | ||
980b24da | 725 | #define FUDGE 2 |
f078f209 LR |
726 | /* |
727 | * Pull nexttbtt forward to reflect the current | |
728 | * TSF and calculate dtim+cfp state for the result. | |
729 | */ | |
730 | tsf = ath9k_hw_gettsf64(ah); | |
731 | tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; | |
732 | do { | |
733 | nexttbtt += intval; | |
734 | if (--dtimcount < 0) { | |
735 | dtimcount = dtimperiod - 1; | |
736 | if (--cfpcount < 0) | |
737 | cfpcount = cfpperiod - 1; | |
738 | } | |
739 | } while (nexttbtt < tsftu); | |
740 | #undef FUDGE | |
0345f37b | 741 | memset(&bs, 0, sizeof(bs)); |
f078f209 LR |
742 | bs.bs_intval = intval; |
743 | bs.bs_nexttbtt = nexttbtt; | |
744 | bs.bs_dtimperiod = dtimperiod*intval; | |
745 | bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; | |
746 | bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; | |
747 | bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; | |
748 | bs.bs_cfpmaxduration = 0; | |
980b24da | 749 | |
f078f209 LR |
750 | /* |
751 | * Calculate the number of consecutive beacons to miss | |
752 | * before taking a BMISS interrupt. The configuration | |
753 | * is specified in TU so we only need calculate based | |
754 | * on the beacon interval. Note that we clamp the | |
755 | * result to at most 15 beacons. | |
756 | */ | |
757 | if (sleepduration > intval) { | |
980b24da S |
758 | bs.bs_bmissthreshold = conf.listen_interval * |
759 | ATH_DEFAULT_BMISS_LIMIT / 2; | |
f078f209 LR |
760 | } else { |
761 | bs.bs_bmissthreshold = | |
762 | DIV_ROUND_UP(conf.bmiss_timeout, intval); | |
763 | if (bs.bs_bmissthreshold > 15) | |
764 | bs.bs_bmissthreshold = 15; | |
765 | else if (bs.bs_bmissthreshold <= 0) | |
766 | bs.bs_bmissthreshold = 1; | |
767 | } | |
768 | ||
769 | /* | |
770 | * Calculate sleep duration. The configuration is | |
771 | * given in ms. We insure a multiple of the beacon | |
772 | * period is used. Also, if the sleep duration is | |
773 | * greater than the DTIM period then it makes senses | |
774 | * to make it a multiple of that. | |
775 | * | |
776 | * XXX fixed at 100ms | |
777 | */ | |
778 | ||
980b24da S |
779 | bs.bs_sleepduration = roundup(IEEE80211_MS_TO_TU(100), |
780 | sleepduration); | |
f078f209 LR |
781 | if (bs.bs_sleepduration > bs.bs_dtimperiod) |
782 | bs.bs_sleepduration = bs.bs_dtimperiod; | |
783 | ||
784 | DPRINTF(sc, ATH_DBG_BEACON, | |
785 | "%s: tsf %llu " | |
786 | "tsf:tu %u " | |
787 | "intval %u " | |
788 | "nexttbtt %u " | |
789 | "dtim %u " | |
790 | "nextdtim %u " | |
791 | "bmiss %u " | |
792 | "sleep %u " | |
793 | "cfp:period %u " | |
794 | "maxdur %u " | |
795 | "next %u " | |
ff9b662d S |
796 | "timoffset %u\n", |
797 | __func__, | |
798 | (unsigned long long)tsf, tsftu, | |
799 | bs.bs_intval, | |
800 | bs.bs_nexttbtt, | |
801 | bs.bs_dtimperiod, | |
802 | bs.bs_nextdtim, | |
803 | bs.bs_bmissthreshold, | |
804 | bs.bs_sleepduration, | |
805 | bs.bs_cfpperiod, | |
806 | bs.bs_cfpmaxduration, | |
807 | bs.bs_cfpnext, | |
808 | bs.bs_timoffset | |
f078f209 LR |
809 | ); |
810 | ||
811 | ath9k_hw_set_interrupts(ah, 0); | |
812 | ath9k_hw_set_sta_beacon_timers(ah, &bs); | |
813 | sc->sc_imask |= ATH9K_INT_BMISS; | |
814 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | |
815 | } else { | |
816 | u64 tsf; | |
817 | u32 tsftu; | |
818 | ath9k_hw_set_interrupts(ah, 0); | |
819 | if (nexttbtt == intval) | |
820 | intval |= ATH9K_BEACON_RESET_TSF; | |
b4696c8b | 821 | if (sc->sc_ah->ah_opmode == ATH9K_M_IBSS) { |
f078f209 LR |
822 | /* |
823 | * Pull nexttbtt forward to reflect the current | |
980b24da | 824 | * TSF |
f078f209 | 825 | */ |
980b24da | 826 | #define FUDGE 2 |
f078f209 LR |
827 | if (!(intval & ATH9K_BEACON_RESET_TSF)) { |
828 | tsf = ath9k_hw_gettsf64(ah); | |
829 | tsftu = TSF_TO_TU((u32)(tsf>>32), | |
830 | (u32)tsf) + FUDGE; | |
831 | do { | |
832 | nexttbtt += intval; | |
833 | } while (nexttbtt < tsftu); | |
834 | } | |
835 | #undef FUDGE | |
836 | DPRINTF(sc, ATH_DBG_BEACON, | |
837 | "%s: IBSS nexttbtt %u intval %u (%u)\n", | |
838 | __func__, nexttbtt, | |
839 | intval & ~ATH9K_BEACON_RESET_TSF, | |
840 | conf.beacon_interval); | |
841 | ||
842 | /* | |
843 | * In IBSS mode enable the beacon timers but only | |
844 | * enable SWBA interrupts if we need to manually | |
845 | * prepare beacon frames. Otherwise we use a | |
846 | * self-linked tx descriptor and let the hardware | |
847 | * deal with things. | |
848 | */ | |
849 | intval |= ATH9K_BEACON_ENA; | |
60b67f51 | 850 | if (!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) |
f078f209 LR |
851 | sc->sc_imask |= ATH9K_INT_SWBA; |
852 | ath_beaconq_config(sc); | |
b4696c8b | 853 | } else if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) { |
f078f209 LR |
854 | /* |
855 | * In AP mode we enable the beacon timers and | |
856 | * SWBA interrupts to prepare beacon frames. | |
857 | */ | |
858 | intval |= ATH9K_BEACON_ENA; | |
859 | sc->sc_imask |= ATH9K_INT_SWBA; /* beacon prepare */ | |
860 | ath_beaconq_config(sc); | |
861 | } | |
862 | ath9k_hw_beaconinit(ah, nexttbtt, intval); | |
863 | sc->sc_bmisscount = 0; | |
864 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | |
865 | /* | |
866 | * When using a self-linked beacon descriptor in | |
867 | * ibss mode load it once here. | |
868 | */ | |
b4696c8b | 869 | if (sc->sc_ah->ah_opmode == ATH9K_M_IBSS && |
60b67f51 | 870 | (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) |
f078f209 LR |
871 | ath_beacon_start_adhoc(sc, 0); |
872 | } | |
f078f209 LR |
873 | } |
874 | ||
875 | /* Function to collect beacon rssi data and resync beacon if necessary */ | |
876 | ||
877 | void ath_beacon_sync(struct ath_softc *sc, int if_id) | |
878 | { | |
879 | /* | |
880 | * Resync beacon timers using the tsf of the | |
881 | * beacon frame we just received. | |
882 | */ | |
883 | ath_beacon_config(sc, if_id); | |
672840ac | 884 | sc->sc_flags |= SC_OP_BEACONS; |
f078f209 | 885 | } |