Commit | Line | Data |
---|---|---|
f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 LR |
17 | #include "core.h" |
18 | ||
19 | /* | |
f078f209 LR |
20 | * This function will modify certain transmit queue properties depending on |
21 | * the operating mode of the station (AP or AdHoc). Parameters are AIFS | |
22 | * settings and channel width min/max | |
23 | */ | |
f078f209 LR |
24 | static int ath_beaconq_config(struct ath_softc *sc) |
25 | { | |
26 | struct ath_hal *ah = sc->sc_ah; | |
ea9880fb | 27 | struct ath9k_tx_queue_info qi; |
f078f209 | 28 | |
ea9880fb | 29 | ath9k_hw_get_txq_props(ah, sc->sc_bhalq, &qi); |
d97809db | 30 | if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { |
f078f209 LR |
31 | /* Always burst out beacon and CAB traffic. */ |
32 | qi.tqi_aifs = 1; | |
33 | qi.tqi_cwmin = 0; | |
34 | qi.tqi_cwmax = 0; | |
35 | } else { | |
36 | /* Adhoc mode; important thing is to use 2x cwmin. */ | |
37 | qi.tqi_aifs = sc->sc_beacon_qi.tqi_aifs; | |
38 | qi.tqi_cwmin = 2*sc->sc_beacon_qi.tqi_cwmin; | |
39 | qi.tqi_cwmax = sc->sc_beacon_qi.tqi_cwmax; | |
40 | } | |
41 | ||
ea9880fb | 42 | if (!ath9k_hw_set_txq_props(ah, sc->sc_bhalq, &qi)) { |
f078f209 | 43 | DPRINTF(sc, ATH_DBG_FATAL, |
04bd4638 | 44 | "unable to update h/w beacon queue parameters\n"); |
f078f209 LR |
45 | return 0; |
46 | } else { | |
47 | ath9k_hw_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ | |
48 | return 1; | |
49 | } | |
50 | } | |
51 | ||
ff37e337 S |
52 | static void ath_bstuck_process(struct ath_softc *sc) |
53 | { | |
54 | DPRINTF(sc, ATH_DBG_BEACON, | |
04bd4638 S |
55 | "stuck beacon; resetting (bmiss count %u)\n", |
56 | sc->sc_bmisscount); | |
ff37e337 S |
57 | ath_reset(sc, false); |
58 | } | |
59 | ||
f078f209 | 60 | /* |
f078f209 LR |
61 | * Associates the beacon frame buffer with a transmit descriptor. Will set |
62 | * up all required antenna switch parameters, rate codes, and channel flags. | |
63 | * Beacons are always sent out at the lowest rate, and are not retried. | |
64 | */ | |
f078f209 | 65 | static void ath_beacon_setup(struct ath_softc *sc, |
980b24da | 66 | struct ath_vap *avp, struct ath_buf *bf) |
f078f209 LR |
67 | { |
68 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; | |
69 | struct ath_hal *ah = sc->sc_ah; | |
70 | struct ath_desc *ds; | |
980b24da | 71 | struct ath9k_11n_rate_series series[4]; |
e63835b0 | 72 | struct ath_rate_table *rt; |
980b24da | 73 | int flags, antenna; |
f078f209 LR |
74 | u8 rix, rate; |
75 | int ctsrate = 0; | |
76 | int ctsduration = 0; | |
f078f209 | 77 | |
04bd4638 | 78 | DPRINTF(sc, ATH_DBG_BEACON, "m %p len %u\n", skb, skb->len); |
f078f209 LR |
79 | |
80 | /* setup descriptors */ | |
81 | ds = bf->bf_desc; | |
82 | ||
83 | flags = ATH9K_TXDESC_NOACK; | |
84 | ||
d97809db | 85 | if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC && |
60b67f51 | 86 | (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { |
f078f209 LR |
87 | ds->ds_link = bf->bf_daddr; /* self-linked */ |
88 | flags |= ATH9K_TXDESC_VEOL; | |
89 | /* Let hardware handle antenna switching. */ | |
90 | antenna = 0; | |
91 | } else { | |
92 | ds->ds_link = 0; | |
93 | /* | |
94 | * Switch antenna every beacon. | |
95 | * Should only switch every beacon period, not for every | |
96 | * SWBA's | |
97 | * XXX assumes two antenna | |
98 | */ | |
99 | antenna = ((sc->ast_be_xmit / sc->sc_nbcnvaps) & 1 ? 2 : 1); | |
100 | } | |
101 | ||
102 | ds->ds_data = bf->bf_buf_addr; | |
103 | ||
104 | /* | |
105 | * Calculate rate code. | |
106 | * XXX everything at min xmit rate | |
107 | */ | |
86b89eed | 108 | rix = 0; |
e63835b0 S |
109 | rt = sc->hw_rate_table[sc->sc_curmode]; |
110 | rate = rt->info[rix].ratecode; | |
672840ac | 111 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) |
e63835b0 | 112 | rate |= rt->info[rix].short_preamble; |
f078f209 | 113 | |
ff9b662d | 114 | ath9k_hw_set11n_txdesc(ah, ds, |
980b24da S |
115 | skb->len + FCS_LEN, /* frame length */ |
116 | ATH9K_PKT_TYPE_BEACON, /* Atheros packet type */ | |
528f0c6b | 117 | MAX_RATE_POWER, /* FIXME */ |
980b24da S |
118 | ATH9K_TXKEYIX_INVALID, /* no encryption */ |
119 | ATH9K_KEY_TYPE_CLEAR, /* no encryption */ | |
120 | flags /* no ack, | |
121 | veol for beacons */ | |
f078f209 LR |
122 | ); |
123 | ||
124 | /* NB: beacon's BufLen must be a multiple of 4 bytes */ | |
ff9b662d S |
125 | ath9k_hw_filltxdesc(ah, ds, |
126 | roundup(skb->len, 4), /* buffer length */ | |
980b24da S |
127 | true, /* first segment */ |
128 | true, /* last segment */ | |
129 | ds /* first descriptor */ | |
f078f209 LR |
130 | ); |
131 | ||
0345f37b | 132 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); |
f078f209 LR |
133 | series[0].Tries = 1; |
134 | series[0].Rate = rate; | |
135 | series[0].ChSel = sc->sc_tx_chainmask; | |
136 | series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0; | |
137 | ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, | |
138 | ctsrate, ctsduration, series, 4, 0); | |
139 | } | |
140 | ||
ff37e337 | 141 | /* Generate beacon frame and queue cab data for a vap */ |
f078f209 LR |
142 | static struct ath_buf *ath_beacon_generate(struct ath_softc *sc, int if_id) |
143 | { | |
f078f209 LR |
144 | struct ath_buf *bf; |
145 | struct ath_vap *avp; | |
146 | struct sk_buff *skb; | |
f078f209 | 147 | struct ath_txq *cabq; |
5640b08e | 148 | struct ieee80211_vif *vif; |
147583c0 | 149 | struct ieee80211_tx_info *info; |
980b24da S |
150 | int cabq_depth; |
151 | ||
5640b08e S |
152 | vif = sc->sc_vaps[if_id]; |
153 | ASSERT(vif); | |
f078f209 | 154 | |
5640b08e | 155 | avp = (void *)vif->drv_priv; |
f078f209 LR |
156 | cabq = sc->sc_cabq; |
157 | ||
f078f209 | 158 | if (avp->av_bcbuf == NULL) { |
04bd4638 S |
159 | DPRINTF(sc, ATH_DBG_BEACON, "avp=%p av_bcbuf=%p\n", |
160 | avp, avp->av_bcbuf); | |
f078f209 LR |
161 | return NULL; |
162 | } | |
980b24da | 163 | |
f078f209 | 164 | bf = avp->av_bcbuf; |
980b24da | 165 | skb = (struct sk_buff *)bf->bf_mpdu; |
a8fff50e JM |
166 | if (skb) { |
167 | pci_unmap_single(sc->pdev, bf->bf_dmacontext, | |
ca0c7e51 | 168 | skb->len, |
a8fff50e JM |
169 | PCI_DMA_TODEVICE); |
170 | } | |
f078f209 | 171 | |
5640b08e | 172 | skb = ieee80211_beacon_get(sc->hw, vif); |
a8fff50e JM |
173 | bf->bf_mpdu = skb; |
174 | if (skb == NULL) | |
175 | return NULL; | |
980b24da | 176 | |
147583c0 JM |
177 | info = IEEE80211_SKB_CB(skb); |
178 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
179 | /* | |
180 | * TODO: make sure the seq# gets assigned properly (vs. other | |
181 | * TX frames) | |
182 | */ | |
980b24da | 183 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
147583c0 JM |
184 | sc->seq_no += 0x10; |
185 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
186 | hdr->seq_ctrl |= cpu_to_le16(sc->seq_no); | |
187 | } | |
980b24da | 188 | |
a8fff50e JM |
189 | bf->bf_buf_addr = bf->bf_dmacontext = |
190 | pci_map_single(sc->pdev, skb->data, | |
ca0c7e51 | 191 | skb->len, |
a8fff50e | 192 | PCI_DMA_TODEVICE); |
f078f209 | 193 | |
5640b08e | 194 | skb = ieee80211_get_buffered_bc(sc->hw, vif); |
f078f209 | 195 | |
f078f209 LR |
196 | /* |
197 | * if the CABQ traffic from previous DTIM is pending and the current | |
198 | * beacon is also a DTIM. | |
199 | * 1) if there is only one vap let the cab traffic continue. | |
200 | * 2) if there are more than one vap and we are using staggered | |
201 | * beacons, then drain the cabq by dropping all the frames in | |
202 | * the cabq so that the current vaps cab traffic can be scheduled. | |
203 | */ | |
204 | spin_lock_bh(&cabq->axq_lock); | |
205 | cabq_depth = cabq->axq_depth; | |
206 | spin_unlock_bh(&cabq->axq_lock); | |
207 | ||
e022edbd | 208 | if (skb && cabq_depth) { |
f078f209 LR |
209 | /* |
210 | * Unlock the cabq lock as ath_tx_draintxq acquires | |
211 | * the lock again which is a common function and that | |
212 | * acquires txq lock inside. | |
213 | */ | |
214 | if (sc->sc_nvaps > 1) { | |
215 | ath_tx_draintxq(sc, cabq, false); | |
216 | DPRINTF(sc, ATH_DBG_BEACON, | |
04bd4638 | 217 | "flush previous cabq traffic\n"); |
f078f209 LR |
218 | } |
219 | } | |
220 | ||
221 | /* Construct tx descriptor. */ | |
222 | ath_beacon_setup(sc, avp, bf); | |
223 | ||
224 | /* | |
225 | * Enable the CAB queue before the beacon queue to | |
226 | * insure cab frames are triggered by this beacon. | |
227 | */ | |
e022edbd JM |
228 | while (skb) { |
229 | ath_tx_cabq(sc, skb); | |
5640b08e | 230 | skb = ieee80211_get_buffered_bc(sc->hw, vif); |
e022edbd | 231 | } |
f078f209 | 232 | |
f078f209 LR |
233 | return bf; |
234 | } | |
235 | ||
236 | /* | |
237 | * Startup beacon transmission for adhoc mode when they are sent entirely | |
238 | * by the hardware using the self-linked descriptor + veol trick. | |
239 | */ | |
f078f209 LR |
240 | static void ath_beacon_start_adhoc(struct ath_softc *sc, int if_id) |
241 | { | |
5640b08e | 242 | struct ieee80211_vif *vif; |
f078f209 LR |
243 | struct ath_hal *ah = sc->sc_ah; |
244 | struct ath_buf *bf; | |
245 | struct ath_vap *avp; | |
246 | struct sk_buff *skb; | |
247 | ||
5640b08e S |
248 | vif = sc->sc_vaps[if_id]; |
249 | ASSERT(vif); | |
250 | ||
251 | avp = (void *)vif->drv_priv; | |
f078f209 LR |
252 | |
253 | if (avp->av_bcbuf == NULL) { | |
04bd4638 S |
254 | DPRINTF(sc, ATH_DBG_BEACON, "avp=%p av_bcbuf=%p\n", |
255 | avp, avp != NULL ? avp->av_bcbuf : NULL); | |
f078f209 LR |
256 | return; |
257 | } | |
258 | bf = avp->av_bcbuf; | |
259 | skb = (struct sk_buff *) bf->bf_mpdu; | |
260 | ||
261 | /* Construct tx descriptor. */ | |
262 | ath_beacon_setup(sc, avp, bf); | |
263 | ||
264 | /* NB: caller is known to have already stopped tx dma */ | |
265 | ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); | |
266 | ath9k_hw_txstart(ah, sc->sc_bhalq); | |
04bd4638 | 267 | DPRINTF(sc, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n", |
f078f209 LR |
268 | sc->sc_bhalq, ito64(bf->bf_daddr), bf->bf_desc); |
269 | } | |
270 | ||
f078f209 LR |
271 | int ath_beaconq_setup(struct ath_hal *ah) |
272 | { | |
ea9880fb | 273 | struct ath9k_tx_queue_info qi; |
f078f209 | 274 | |
0345f37b | 275 | memset(&qi, 0, sizeof(qi)); |
f078f209 LR |
276 | qi.tqi_aifs = 1; |
277 | qi.tqi_cwmin = 0; | |
278 | qi.tqi_cwmax = 0; | |
279 | /* NB: don't enable any interrupts */ | |
280 | return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi); | |
281 | } | |
282 | ||
f078f209 LR |
283 | int ath_beacon_alloc(struct ath_softc *sc, int if_id) |
284 | { | |
5640b08e | 285 | struct ieee80211_vif *vif; |
f078f209 | 286 | struct ath_vap *avp; |
980b24da | 287 | struct ieee80211_hdr *hdr; |
f078f209 LR |
288 | struct ath_buf *bf; |
289 | struct sk_buff *skb; | |
459f5f90 | 290 | __le64 tstamp; |
f078f209 | 291 | |
5640b08e S |
292 | vif = sc->sc_vaps[if_id]; |
293 | ASSERT(vif); | |
294 | ||
295 | avp = (void *)vif->drv_priv; | |
f078f209 LR |
296 | |
297 | /* Allocate a beacon descriptor if we haven't done so. */ | |
298 | if (!avp->av_bcbuf) { | |
980b24da S |
299 | /* Allocate beacon state for hostap/ibss. We know |
300 | * a buffer is available. */ | |
f078f209 | 301 | avp->av_bcbuf = list_first_entry(&sc->sc_bbuf, |
980b24da | 302 | struct ath_buf, list); |
f078f209 LR |
303 | list_del(&avp->av_bcbuf->list); |
304 | ||
d97809db | 305 | if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP || |
60b67f51 | 306 | !(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) { |
f078f209 LR |
307 | int slot; |
308 | /* | |
309 | * Assign the vap to a beacon xmit slot. As | |
310 | * above, this cannot fail to find one. | |
311 | */ | |
312 | avp->av_bslot = 0; | |
313 | for (slot = 0; slot < ATH_BCBUF; slot++) | |
314 | if (sc->sc_bslot[slot] == ATH_IF_ID_ANY) { | |
315 | /* | |
316 | * XXX hack, space out slots to better | |
317 | * deal with misses | |
318 | */ | |
319 | if (slot+1 < ATH_BCBUF && | |
320 | sc->sc_bslot[slot+1] == | |
321 | ATH_IF_ID_ANY) { | |
322 | avp->av_bslot = slot+1; | |
323 | break; | |
324 | } | |
325 | avp->av_bslot = slot; | |
326 | /* NB: keep looking for a double slot */ | |
327 | } | |
328 | BUG_ON(sc->sc_bslot[avp->av_bslot] != ATH_IF_ID_ANY); | |
329 | sc->sc_bslot[avp->av_bslot] = if_id; | |
330 | sc->sc_nbcnvaps++; | |
331 | } | |
332 | } | |
333 | ||
334 | /* release the previous beacon frame , if it already exists. */ | |
335 | bf = avp->av_bcbuf; | |
336 | if (bf->bf_mpdu != NULL) { | |
337 | skb = (struct sk_buff *)bf->bf_mpdu; | |
a8fff50e | 338 | pci_unmap_single(sc->pdev, bf->bf_dmacontext, |
ca0c7e51 | 339 | skb->len, |
a8fff50e | 340 | PCI_DMA_TODEVICE); |
f078f209 LR |
341 | dev_kfree_skb_any(skb); |
342 | bf->bf_mpdu = NULL; | |
343 | } | |
344 | ||
345 | /* | |
980b24da | 346 | * NB: the beacon data buffer must be 32-bit aligned. |
e022edbd | 347 | * FIXME: Fill avp->av_btxctl.txpower and |
f078f209 LR |
348 | * avp->av_btxctl.shortPreamble |
349 | */ | |
5640b08e | 350 | skb = ieee80211_beacon_get(sc->hw, vif); |
f078f209 | 351 | if (skb == NULL) { |
04bd4638 | 352 | DPRINTF(sc, ATH_DBG_BEACON, "cannot get skb\n"); |
f078f209 LR |
353 | return -ENOMEM; |
354 | } | |
355 | ||
459f5f90 S |
356 | tstamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp; |
357 | sc->bc_tstamp = le64_to_cpu(tstamp); | |
358 | ||
f078f209 LR |
359 | /* |
360 | * Calculate a TSF adjustment factor required for | |
361 | * staggered beacons. Note that we assume the format | |
362 | * of the beacon frame leaves the tstamp field immediately | |
363 | * following the header. | |
364 | */ | |
365 | if (avp->av_bslot > 0) { | |
366 | u64 tsfadjust; | |
367 | __le64 val; | |
368 | int intval; | |
369 | ||
a8fff50e JM |
370 | intval = sc->hw->conf.beacon_int ? |
371 | sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL; | |
f078f209 LR |
372 | |
373 | /* | |
374 | * The beacon interval is in TU's; the TSF in usecs. | |
375 | * We figure out how many TU's to add to align the | |
376 | * timestamp then convert to TSF units and handle | |
377 | * byte swapping before writing it in the frame. | |
378 | * The hardware will then add this each time a beacon | |
379 | * frame is sent. Note that we align vap's 1..N | |
380 | * and leave vap 0 untouched. This means vap 0 | |
381 | * has a timestamp in one beacon interval while the | |
382 | * others get a timestamp aligned to the next interval. | |
383 | */ | |
384 | tsfadjust = (intval * (ATH_BCBUF - avp->av_bslot)) / ATH_BCBUF; | |
385 | val = cpu_to_le64(tsfadjust << 10); /* TU->TSF */ | |
386 | ||
387 | DPRINTF(sc, ATH_DBG_BEACON, | |
04bd4638 | 388 | "stagger beacons, bslot %d intval %u tsfadjust %llu\n", |
f078f209 LR |
389 | avp->av_bslot, intval, (unsigned long long)tsfadjust); |
390 | ||
980b24da S |
391 | hdr = (struct ieee80211_hdr *)skb->data; |
392 | memcpy(&hdr[1], &val, sizeof(val)); | |
f078f209 LR |
393 | } |
394 | ||
a8fff50e JM |
395 | bf->bf_buf_addr = bf->bf_dmacontext = |
396 | pci_map_single(sc->pdev, skb->data, | |
ca0c7e51 | 397 | skb->len, |
a8fff50e | 398 | PCI_DMA_TODEVICE); |
f078f209 LR |
399 | bf->bf_mpdu = skb; |
400 | ||
401 | return 0; | |
402 | } | |
403 | ||
f078f209 LR |
404 | void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp) |
405 | { | |
406 | if (avp->av_bcbuf != NULL) { | |
407 | struct ath_buf *bf; | |
408 | ||
409 | if (avp->av_bslot != -1) { | |
410 | sc->sc_bslot[avp->av_bslot] = ATH_IF_ID_ANY; | |
411 | sc->sc_nbcnvaps--; | |
412 | } | |
413 | ||
414 | bf = avp->av_bcbuf; | |
415 | if (bf->bf_mpdu != NULL) { | |
416 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; | |
a8fff50e | 417 | pci_unmap_single(sc->pdev, bf->bf_dmacontext, |
ca0c7e51 | 418 | skb->len, |
a8fff50e | 419 | PCI_DMA_TODEVICE); |
f078f209 LR |
420 | dev_kfree_skb_any(skb); |
421 | bf->bf_mpdu = NULL; | |
422 | } | |
423 | list_add_tail(&bf->list, &sc->sc_bbuf); | |
424 | ||
425 | avp->av_bcbuf = NULL; | |
426 | } | |
427 | } | |
428 | ||
f078f209 LR |
429 | void ath9k_beacon_tasklet(unsigned long data) |
430 | { | |
f078f209 LR |
431 | struct ath_softc *sc = (struct ath_softc *)data; |
432 | struct ath_hal *ah = sc->sc_ah; | |
433 | struct ath_buf *bf = NULL; | |
434 | int slot, if_id; | |
435 | u32 bfaddr; | |
436 | u32 rx_clear = 0, rx_frame = 0, tx_frame = 0; | |
437 | u32 show_cycles = 0; | |
438 | u32 bc = 0; /* beacon count */ | |
439 | u64 tsf; | |
440 | u32 tsftu; | |
441 | u16 intval; | |
442 | ||
98deeea0 | 443 | if (sc->sc_flags & SC_OP_NO_RESET) { |
f078f209 | 444 | show_cycles = ath9k_hw_GetMibCycleCountsPct(ah, |
ff37e337 | 445 | &rx_clear, &rx_frame, &tx_frame); |
f078f209 LR |
446 | } |
447 | ||
448 | /* | |
449 | * Check if the previous beacon has gone out. If | |
450 | * not don't try to post another, skip this period | |
451 | * and wait for the next. Missed beacons indicate | |
452 | * a problem and should not occur. If we miss too | |
453 | * many consecutive beacons reset the device. | |
980b24da S |
454 | * |
455 | * FIXME: Clean up this mess !! | |
f078f209 LR |
456 | */ |
457 | if (ath9k_hw_numtxpending(ah, sc->sc_bhalq) != 0) { | |
458 | sc->sc_bmisscount++; | |
459 | /* XXX: doth needs the chanchange IE countdown decremented. | |
460 | * We should consider adding a mac80211 call to indicate | |
461 | * a beacon miss so appropriate action could be taken | |
462 | * (in that layer). | |
463 | */ | |
464 | if (sc->sc_bmisscount < BSTUCK_THRESH) { | |
98deeea0 | 465 | if (sc->sc_flags & SC_OP_NO_RESET) { |
f078f209 | 466 | DPRINTF(sc, ATH_DBG_BEACON, |
04bd4638 S |
467 | "missed %u consecutive beacons\n", |
468 | sc->sc_bmisscount); | |
f078f209 LR |
469 | if (show_cycles) { |
470 | /* | |
980b24da S |
471 | * Display cycle counter stats from HW |
472 | * to aide in debug of stickiness. | |
f078f209 | 473 | */ |
980b24da | 474 | DPRINTF(sc, ATH_DBG_BEACON, |
04bd4638 | 475 | "busy times: rx_clear=%d, " |
f078f209 | 476 | "rx_frame=%d, tx_frame=%d\n", |
04bd4638 | 477 | rx_clear, rx_frame, |
f078f209 LR |
478 | tx_frame); |
479 | } else { | |
980b24da | 480 | DPRINTF(sc, ATH_DBG_BEACON, |
04bd4638 S |
481 | "unable to obtain " |
482 | "busy times\n"); | |
f078f209 LR |
483 | } |
484 | } else { | |
485 | DPRINTF(sc, ATH_DBG_BEACON, | |
04bd4638 S |
486 | "missed %u consecutive beacons\n", |
487 | sc->sc_bmisscount); | |
f078f209 LR |
488 | } |
489 | } else if (sc->sc_bmisscount >= BSTUCK_THRESH) { | |
98deeea0 | 490 | if (sc->sc_flags & SC_OP_NO_RESET) { |
f078f209 | 491 | if (sc->sc_bmisscount == BSTUCK_THRESH) { |
980b24da | 492 | DPRINTF(sc, ATH_DBG_BEACON, |
04bd4638 S |
493 | "beacon is officially " |
494 | "stuck\n"); | |
f078f209 LR |
495 | } |
496 | } else { | |
497 | DPRINTF(sc, ATH_DBG_BEACON, | |
04bd4638 | 498 | "beacon is officially stuck\n"); |
f078f209 LR |
499 | ath_bstuck_process(sc); |
500 | } | |
501 | } | |
f078f209 LR |
502 | return; |
503 | } | |
980b24da | 504 | |
f078f209 | 505 | if (sc->sc_bmisscount != 0) { |
98deeea0 | 506 | if (sc->sc_flags & SC_OP_NO_RESET) { |
980b24da | 507 | DPRINTF(sc, ATH_DBG_BEACON, |
04bd4638 S |
508 | "resume beacon xmit after %u misses\n", |
509 | sc->sc_bmisscount); | |
f078f209 LR |
510 | } else { |
511 | DPRINTF(sc, ATH_DBG_BEACON, | |
04bd4638 S |
512 | "resume beacon xmit after %u misses\n", |
513 | sc->sc_bmisscount); | |
f078f209 LR |
514 | } |
515 | sc->sc_bmisscount = 0; | |
516 | } | |
517 | ||
518 | /* | |
519 | * Generate beacon frames. we are sending frames | |
520 | * staggered so calculate the slot for this frame based | |
521 | * on the tsf to safeguard against missing an swba. | |
522 | */ | |
523 | ||
a8fff50e JM |
524 | intval = sc->hw->conf.beacon_int ? |
525 | sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL; | |
f078f209 LR |
526 | |
527 | tsf = ath9k_hw_gettsf64(ah); | |
528 | tsftu = TSF_TO_TU(tsf>>32, tsf); | |
529 | slot = ((tsftu % intval) * ATH_BCBUF) / intval; | |
530 | if_id = sc->sc_bslot[(slot + 1) % ATH_BCBUF]; | |
980b24da | 531 | |
f078f209 | 532 | DPRINTF(sc, ATH_DBG_BEACON, |
04bd4638 S |
533 | "slot %d [tsf %llu tsftu %u intval %u] if_id %d\n", |
534 | slot, (unsigned long long)tsf, tsftu, | |
980b24da S |
535 | intval, if_id); |
536 | ||
f078f209 LR |
537 | bfaddr = 0; |
538 | if (if_id != ATH_IF_ID_ANY) { | |
539 | bf = ath_beacon_generate(sc, if_id); | |
540 | if (bf != NULL) { | |
541 | bfaddr = bf->bf_daddr; | |
542 | bc = 1; | |
543 | } | |
544 | } | |
545 | /* | |
546 | * Handle slot time change when a non-ERP station joins/leaves | |
547 | * an 11g network. The 802.11 layer notifies us via callback, | |
548 | * we mark updateslot, then wait one beacon before effecting | |
549 | * the change. This gives associated stations at least one | |
550 | * beacon interval to note the state change. | |
551 | * | |
552 | * NB: The slot time change state machine is clocked according | |
553 | * to whether we are bursting or staggering beacons. We | |
554 | * recognize the request to update and record the current | |
555 | * slot then don't transition until that slot is reached | |
556 | * again. If we miss a beacon for that slot then we'll be | |
557 | * slow to transition but we'll be sure at least one beacon | |
558 | * interval has passed. When bursting slot is always left | |
559 | * set to ATH_BCBUF so this check is a noop. | |
560 | */ | |
561 | /* XXX locking */ | |
562 | if (sc->sc_updateslot == UPDATE) { | |
563 | sc->sc_updateslot = COMMIT; /* commit next beacon */ | |
564 | sc->sc_slotupdate = slot; | |
ff37e337 S |
565 | } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot) { |
566 | ath9k_hw_setslottime(sc->sc_ah, sc->sc_slottime); | |
567 | sc->sc_updateslot = OK; | |
568 | } | |
f078f209 LR |
569 | if (bfaddr != 0) { |
570 | /* | |
571 | * Stop any current dma and put the new frame(s) on the queue. | |
572 | * This should never fail since we check above that no frames | |
573 | * are still pending on the queue. | |
574 | */ | |
575 | if (!ath9k_hw_stoptxdma(ah, sc->sc_bhalq)) { | |
576 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 577 | "beacon queue %u did not stop?\n", sc->sc_bhalq); |
f078f209 LR |
578 | /* NB: the HAL still stops DMA, so proceed */ |
579 | } | |
580 | ||
581 | /* NB: cabq traffic should already be queued and primed */ | |
582 | ath9k_hw_puttxbuf(ah, sc->sc_bhalq, bfaddr); | |
583 | ath9k_hw_txstart(ah, sc->sc_bhalq); | |
584 | ||
585 | sc->ast_be_xmit += bc; /* XXX per-vap? */ | |
586 | } | |
f078f209 LR |
587 | } |
588 | ||
f078f209 LR |
589 | /* |
590 | * Configure the beacon and sleep timers. | |
591 | * | |
592 | * When operating as an AP this resets the TSF and sets | |
593 | * up the hardware to notify us when we need to issue beacons. | |
594 | * | |
595 | * When operating in station mode this sets up the beacon | |
596 | * timers according to the timestamp of the last received | |
597 | * beacon and the current TSF, configures PCF and DTIM | |
598 | * handling, programs the sleep registers so the hardware | |
599 | * will wakeup in time to receive beacons, and configures | |
600 | * the beacon miss handling so we'll receive a BMISS | |
601 | * interrupt when we stop seeing beacons from the AP | |
602 | * we've associated with. | |
603 | */ | |
f078f209 LR |
604 | void ath_beacon_config(struct ath_softc *sc, int if_id) |
605 | { | |
5640b08e | 606 | struct ieee80211_vif *vif; |
f078f209 | 607 | struct ath_hal *ah = sc->sc_ah; |
f078f209 | 608 | struct ath_beacon_config conf; |
5640b08e | 609 | struct ath_vap *avp; |
d97809db | 610 | enum nl80211_iftype opmode; |
980b24da | 611 | u32 nexttbtt, intval; |
f078f209 | 612 | |
5640b08e S |
613 | if (if_id != ATH_IF_ID_ANY) { |
614 | vif = sc->sc_vaps[if_id]; | |
615 | ASSERT(vif); | |
616 | avp = (void *)vif->drv_priv; | |
d97809db | 617 | opmode = avp->av_opmode; |
5640b08e | 618 | } else { |
d97809db | 619 | opmode = sc->sc_ah->ah_opmode; |
5640b08e | 620 | } |
f078f209 | 621 | |
0345f37b | 622 | memset(&conf, 0, sizeof(struct ath_beacon_config)); |
f078f209 | 623 | |
a8fff50e JM |
624 | conf.beacon_interval = sc->hw->conf.beacon_int ? |
625 | sc->hw->conf.beacon_int : ATH_DEFAULT_BINTVAL; | |
f078f209 LR |
626 | conf.listen_interval = 1; |
627 | conf.dtim_period = conf.beacon_interval; | |
628 | conf.dtim_count = 1; | |
629 | conf.bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf.beacon_interval; | |
630 | ||
631 | /* extract tstamp from last beacon and convert to TU */ | |
459f5f90 S |
632 | nexttbtt = TSF_TO_TU(sc->bc_tstamp >> 32, sc->bc_tstamp); |
633 | ||
f078f209 | 634 | /* XXX conditionalize multi-bss support? */ |
d97809db | 635 | if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { |
f078f209 LR |
636 | /* |
637 | * For multi-bss ap support beacons are either staggered | |
638 | * evenly over N slots or burst together. For the former | |
639 | * arrange for the SWBA to be delivered for each slot. | |
640 | * Slots that are not occupied will generate nothing. | |
641 | */ | |
642 | /* NB: the beacon interval is kept internally in TU's */ | |
643 | intval = conf.beacon_interval & ATH9K_BEACON_PERIOD; | |
644 | intval /= ATH_BCBUF; /* for staggered beacons */ | |
645 | } else { | |
646 | intval = conf.beacon_interval & ATH9K_BEACON_PERIOD; | |
647 | } | |
648 | ||
980b24da | 649 | if (nexttbtt == 0) /* e.g. for ap mode */ |
f078f209 | 650 | nexttbtt = intval; |
980b24da | 651 | else if (intval) /* NB: can be 0 for monitor mode */ |
f078f209 | 652 | nexttbtt = roundup(nexttbtt, intval); |
980b24da | 653 | |
04bd4638 S |
654 | DPRINTF(sc, ATH_DBG_BEACON, "nexttbtt %u intval %u (%u)\n", |
655 | nexttbtt, intval, conf.beacon_interval); | |
980b24da | 656 | |
d97809db CM |
657 | /* Check for NL80211_IFTYPE_AP and sc_nostabeacons for WDS client */ |
658 | if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) { | |
f078f209 LR |
659 | struct ath9k_beacon_state bs; |
660 | u64 tsf; | |
661 | u32 tsftu; | |
662 | int dtimperiod, dtimcount, sleepduration; | |
663 | int cfpperiod, cfpcount; | |
664 | ||
665 | /* | |
666 | * Setup dtim and cfp parameters according to | |
667 | * last beacon we received (which may be none). | |
668 | */ | |
669 | dtimperiod = conf.dtim_period; | |
980b24da | 670 | if (dtimperiod <= 0) /* NB: 0 if not known */ |
f078f209 LR |
671 | dtimperiod = 1; |
672 | dtimcount = conf.dtim_count; | |
980b24da S |
673 | if (dtimcount >= dtimperiod) /* NB: sanity check */ |
674 | dtimcount = 0; | |
675 | cfpperiod = 1; /* NB: no PCF support yet */ | |
f078f209 LR |
676 | cfpcount = 0; |
677 | ||
678 | sleepduration = conf.listen_interval * intval; | |
679 | if (sleepduration <= 0) | |
680 | sleepduration = intval; | |
681 | ||
980b24da | 682 | #define FUDGE 2 |
f078f209 LR |
683 | /* |
684 | * Pull nexttbtt forward to reflect the current | |
685 | * TSF and calculate dtim+cfp state for the result. | |
686 | */ | |
687 | tsf = ath9k_hw_gettsf64(ah); | |
688 | tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE; | |
689 | do { | |
690 | nexttbtt += intval; | |
691 | if (--dtimcount < 0) { | |
692 | dtimcount = dtimperiod - 1; | |
693 | if (--cfpcount < 0) | |
694 | cfpcount = cfpperiod - 1; | |
695 | } | |
696 | } while (nexttbtt < tsftu); | |
697 | #undef FUDGE | |
0345f37b | 698 | memset(&bs, 0, sizeof(bs)); |
f078f209 LR |
699 | bs.bs_intval = intval; |
700 | bs.bs_nexttbtt = nexttbtt; | |
701 | bs.bs_dtimperiod = dtimperiod*intval; | |
702 | bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; | |
703 | bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; | |
704 | bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; | |
705 | bs.bs_cfpmaxduration = 0; | |
980b24da | 706 | |
f078f209 LR |
707 | /* |
708 | * Calculate the number of consecutive beacons to miss | |
709 | * before taking a BMISS interrupt. The configuration | |
710 | * is specified in TU so we only need calculate based | |
711 | * on the beacon interval. Note that we clamp the | |
712 | * result to at most 15 beacons. | |
713 | */ | |
714 | if (sleepduration > intval) { | |
980b24da S |
715 | bs.bs_bmissthreshold = conf.listen_interval * |
716 | ATH_DEFAULT_BMISS_LIMIT / 2; | |
f078f209 LR |
717 | } else { |
718 | bs.bs_bmissthreshold = | |
719 | DIV_ROUND_UP(conf.bmiss_timeout, intval); | |
720 | if (bs.bs_bmissthreshold > 15) | |
721 | bs.bs_bmissthreshold = 15; | |
722 | else if (bs.bs_bmissthreshold <= 0) | |
723 | bs.bs_bmissthreshold = 1; | |
724 | } | |
725 | ||
726 | /* | |
727 | * Calculate sleep duration. The configuration is | |
728 | * given in ms. We insure a multiple of the beacon | |
729 | * period is used. Also, if the sleep duration is | |
730 | * greater than the DTIM period then it makes senses | |
731 | * to make it a multiple of that. | |
732 | * | |
733 | * XXX fixed at 100ms | |
734 | */ | |
735 | ||
980b24da S |
736 | bs.bs_sleepduration = roundup(IEEE80211_MS_TO_TU(100), |
737 | sleepduration); | |
f078f209 LR |
738 | if (bs.bs_sleepduration > bs.bs_dtimperiod) |
739 | bs.bs_sleepduration = bs.bs_dtimperiod; | |
740 | ||
741 | DPRINTF(sc, ATH_DBG_BEACON, | |
04bd4638 | 742 | "tsf %llu " |
f078f209 LR |
743 | "tsf:tu %u " |
744 | "intval %u " | |
745 | "nexttbtt %u " | |
746 | "dtim %u " | |
747 | "nextdtim %u " | |
748 | "bmiss %u " | |
749 | "sleep %u " | |
750 | "cfp:period %u " | |
751 | "maxdur %u " | |
752 | "next %u " | |
ff9b662d | 753 | "timoffset %u\n", |
ff9b662d S |
754 | (unsigned long long)tsf, tsftu, |
755 | bs.bs_intval, | |
756 | bs.bs_nexttbtt, | |
757 | bs.bs_dtimperiod, | |
758 | bs.bs_nextdtim, | |
759 | bs.bs_bmissthreshold, | |
760 | bs.bs_sleepduration, | |
761 | bs.bs_cfpperiod, | |
762 | bs.bs_cfpmaxduration, | |
763 | bs.bs_cfpnext, | |
764 | bs.bs_timoffset | |
f078f209 LR |
765 | ); |
766 | ||
767 | ath9k_hw_set_interrupts(ah, 0); | |
768 | ath9k_hw_set_sta_beacon_timers(ah, &bs); | |
769 | sc->sc_imask |= ATH9K_INT_BMISS; | |
770 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | |
771 | } else { | |
772 | u64 tsf; | |
773 | u32 tsftu; | |
774 | ath9k_hw_set_interrupts(ah, 0); | |
775 | if (nexttbtt == intval) | |
776 | intval |= ATH9K_BEACON_RESET_TSF; | |
d97809db | 777 | if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) { |
f078f209 LR |
778 | /* |
779 | * Pull nexttbtt forward to reflect the current | |
980b24da | 780 | * TSF |
f078f209 | 781 | */ |
980b24da | 782 | #define FUDGE 2 |
f078f209 LR |
783 | if (!(intval & ATH9K_BEACON_RESET_TSF)) { |
784 | tsf = ath9k_hw_gettsf64(ah); | |
785 | tsftu = TSF_TO_TU((u32)(tsf>>32), | |
786 | (u32)tsf) + FUDGE; | |
787 | do { | |
788 | nexttbtt += intval; | |
789 | } while (nexttbtt < tsftu); | |
790 | } | |
791 | #undef FUDGE | |
792 | DPRINTF(sc, ATH_DBG_BEACON, | |
04bd4638 S |
793 | "IBSS nexttbtt %u intval %u (%u)\n", |
794 | nexttbtt, | |
f078f209 LR |
795 | intval & ~ATH9K_BEACON_RESET_TSF, |
796 | conf.beacon_interval); | |
797 | ||
798 | /* | |
799 | * In IBSS mode enable the beacon timers but only | |
800 | * enable SWBA interrupts if we need to manually | |
801 | * prepare beacon frames. Otherwise we use a | |
802 | * self-linked tx descriptor and let the hardware | |
803 | * deal with things. | |
804 | */ | |
805 | intval |= ATH9K_BEACON_ENA; | |
60b67f51 | 806 | if (!(ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) |
f078f209 LR |
807 | sc->sc_imask |= ATH9K_INT_SWBA; |
808 | ath_beaconq_config(sc); | |
d97809db | 809 | } else if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) { |
f078f209 LR |
810 | /* |
811 | * In AP mode we enable the beacon timers and | |
812 | * SWBA interrupts to prepare beacon frames. | |
813 | */ | |
814 | intval |= ATH9K_BEACON_ENA; | |
815 | sc->sc_imask |= ATH9K_INT_SWBA; /* beacon prepare */ | |
816 | ath_beaconq_config(sc); | |
817 | } | |
818 | ath9k_hw_beaconinit(ah, nexttbtt, intval); | |
819 | sc->sc_bmisscount = 0; | |
820 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | |
821 | /* | |
822 | * When using a self-linked beacon descriptor in | |
823 | * ibss mode load it once here. | |
824 | */ | |
d97809db | 825 | if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC && |
60b67f51 | 826 | (ah->ah_caps.hw_caps & ATH9K_HW_CAP_VEOL)) |
f078f209 LR |
827 | ath_beacon_start_adhoc(sc, 0); |
828 | } | |
f078f209 LR |
829 | } |
830 | ||
f078f209 LR |
831 | void ath_beacon_sync(struct ath_softc *sc, int if_id) |
832 | { | |
833 | /* | |
834 | * Resync beacon timers using the tsf of the | |
835 | * beacon frame we just received. | |
836 | */ | |
837 | ath_beacon_config(sc, if_id); | |
672840ac | 838 | sc->sc_flags |= SC_OP_BEACONS; |
f078f209 | 839 | } |