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ath9k: Ensure ath_node is not NULL when updating tx chainmask
[deliverable/linux.git] / drivers / net / wireless / ath9k / core.h
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef CORE_H
18#define CORE_H
19
20#include <linux/version.h>
21#include <linux/autoconf.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/spinlock.h>
25#include <linux/errno.h>
26#include <linux/skbuff.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/ip.h>
30#include <linux/tcp.h>
31#include <linux/in.h>
32#include <linux/delay.h>
33#include <linux/wait.h>
34#include <linux/pci.h>
35#include <linux/interrupt.h>
36#include <linux/sched.h>
37#include <linux/list.h>
38#include <asm/byteorder.h>
39#include <linux/scatterlist.h>
40#include <asm/page.h>
41#include <net/mac80211.h>
c83be688 42#include <linux/leds.h>
500c064d 43#include <linux/rfkill.h>
f078f209
LR		 44
45#include "ath9k.h"
46#include "rc.h"
47
48struct ath_node;
49
50/******************/
51/* Utility macros */
52/******************/
53
54/* Macro to expand scalars to 64-bit objects */
55
f22f558d
S		 56#define ito64(x) (sizeof(x) == 8) ? \
57 (((unsigned long long int)(x)) & (0xff)) : \
58 (sizeof(x) == 16) ? \
59 (((unsigned long long int)(x)) & 0xffff) : \
60 ((sizeof(x) == 32) ? \
f078f209 61 (((unsigned long long int)(x)) & 0xffffffff) : \
f22f558d 62 (unsigned long long int)(x))
f078f209
LR		 63
64/* increment with wrap-around */
f22f558d
S		 65#define INCR(_l, _sz) do { \
66 (_l)++; \
67 (_l) &= ((_sz) - 1); \
f078f209
LR		 68 } while (0)
69
70/* decrement with wrap-around */
f22f558d
S		 71#define DECR(_l, _sz) do { \
72 (_l)--; \
73 (_l) &= ((_sz) - 1); \
f078f209
LR		 74 } while (0)
75
76#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
77
78#define ASSERT(exp) do { \
79 if (unlikely(!(exp))) { \
80 BUG(); \
81 } \
82 } while (0)
83
19b73c7f
S		 84#define TSF_TO_TU(_h,_l) \
85 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
86
f078f209
LR		 87#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
88
89static inline unsigned long get_timestamp(void)
90{
91 return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
92}
93
7dcfdcd9
S		 94static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
95
f078f209
LR		 96/*************/
97/* Debugging */
98/*************/
99
100enum ATH_DEBUG {
101 ATH_DBG_RESET = 0x00000001,
102 ATH_DBG_PHY_IO = 0x00000002,
103 ATH_DBG_REG_IO = 0x00000004,
104 ATH_DBG_QUEUE = 0x00000008,
105 ATH_DBG_EEPROM = 0x00000010,
106 ATH_DBG_NF_CAL = 0x00000020,
107 ATH_DBG_CALIBRATE = 0x00000040,
108 ATH_DBG_CHANNEL = 0x00000080,
109 ATH_DBG_INTERRUPT = 0x00000100,
110 ATH_DBG_REGULATORY = 0x00000200,
111 ATH_DBG_ANI = 0x00000400,
112 ATH_DBG_POWER_MGMT = 0x00000800,
113 ATH_DBG_XMIT = 0x00001000,
114 ATH_DBG_BEACON = 0x00002000,
115 ATH_DBG_RATE = 0x00004000,
116 ATH_DBG_CONFIG = 0x00008000,
117 ATH_DBG_KEYCACHE = 0x00010000,
118 ATH_DBG_AGGR = 0x00020000,
119 ATH_DBG_FATAL = 0x00040000,
120 ATH_DBG_ANY = 0xffffffff
121};
122
123#define DBG_DEFAULT (ATH_DBG_FATAL)
124
125#define DPRINTF(sc, _m, _fmt, ...) do { \
126 if (sc->sc_debug & (_m)) \
127 printk(_fmt , ##__VA_ARGS__); \
128 } while (0)
129
130/***************************/
131/* Load-time Configuration */
132/***************************/
133
134/* Per-instance load-time (note: NOT run-time) configurations
135 * for Atheros Device */
136struct ath_config {
f22f558d
S		 137 u32 ath_aggr_prot;
138 u16 txpowlimit;
139 u16 txpowlimit_override;
140 u8 cabqReadytime; /* Cabq Readytime % */
141 u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */
f078f209
LR		 142};
143
144/***********************/
145/* Chainmask Selection */
146/***********************/
147
148#define ATH_CHAINMASK_SEL_TIMEOUT 6000
149/* Default - Number of last RSSI values that is used for
150 * chainmask selection */
151#define ATH_CHAINMASK_SEL_RSSI_CNT 10
152/* Means use 3x3 chainmask instead of configured chainmask */
153#define ATH_CHAINMASK_SEL_3X3 7
154/* Default - Rssi threshold below which we have to switch to 3x3 */
155#define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20
156/* Default - Rssi threshold above which we have to switch to
157 * user configured values */
158#define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35
159/* Struct to store the chainmask select related info */
160struct ath_chainmask_sel {
f22f558d
S		 161 struct timer_list timer;
162 int cur_tx_mask; /* user configured or 3x3 */
163 int cur_rx_mask; /* user configured or 3x3 */
164 int tx_avgrssi;
165 u8 switch_allowed:1, /* timer will set this */
166 cm_sel_enabled : 1;
f078f209
LR		 167};
168
169int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
170void ath_update_chainmask(struct ath_softc *sc, int is_ht);
171
172/*************************/
173/* Descriptor Management */
174/*************************/
175
f078f209
LR		 176#define ATH_TXBUF_RESET(_bf) do { \
177 (_bf)->bf_status = 0; \
178 (_bf)->bf_lastbf = NULL; \
179 (_bf)->bf_lastfrm = NULL; \
180 (_bf)->bf_next = NULL; \
0345f37b 181 memset(&((_bf)->bf_state), 0, \
f078f209
LR		 182 sizeof(struct ath_buf_state)); \
183 } while (0)
184
cd3d39a6
S		 185enum buffer_type {
186 BUF_DATA = BIT(0),
187 BUF_AGGR = BIT(1),
188 BUF_AMPDU = BIT(2),
189 BUF_HT = BIT(3),
190 BUF_RETRY = BIT(4),
191 BUF_XRETRY = BIT(5),
192 BUF_SHORT_PREAMBLE = BIT(6),
193 BUF_BAR = BIT(7),
194 BUF_PSPOLL = BIT(8),
195 BUF_AGGR_BURST = BIT(9),
196 BUF_CALC_AIRTIME = BIT(10),
197};
198
f078f209 199struct ath_buf_state {
cd3d39a6
S		 200 int bfs_nframes; /* # frames in aggregate */
201 u16 bfs_al; /* length of aggregate */
202 u16 bfs_frmlen; /* length of frame */
203 int bfs_seqno; /* sequence number */
204 int bfs_tidno; /* tid of this frame */
205 int bfs_retries; /* current retries */
f078f209 206 struct ath_rc_series bfs_rcs[4]; /* rate series */
cd3d39a6 207 u32 bf_type; /* BUF_* (enum buffer_type) */
f078f209 208 /* key type use to encrypt this frame */
528f0c6b 209 u32 bfs_keyix;
f078f209
LR		 210 enum ath9k_key_type bfs_keytype;
211};
212
213#define bf_nframes bf_state.bfs_nframes
214#define bf_al bf_state.bfs_al
215#define bf_frmlen bf_state.bfs_frmlen
216#define bf_retries bf_state.bfs_retries
217#define bf_seqno bf_state.bfs_seqno
218#define bf_tidno bf_state.bfs_tidno
219#define bf_rcs bf_state.bfs_rcs
528f0c6b 220#define bf_keyix bf_state.bfs_keyix
f078f209 221#define bf_keytype bf_state.bfs_keytype
cd3d39a6
S		 222#define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
223#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
224#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
225#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
226#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
227#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
228#define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
229#define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
230#define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
231#define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
f078f209
LR		 232
233/*
234 * Abstraction of a contiguous buffer to transmit/receive. There is only
235 * a single hw descriptor encapsulated here.
236 */
f078f209
LR		 237struct ath_buf {
238 struct list_head list;
239 struct list_head *last;
240 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
f22f558d 241 an aggregate) */
f078f209
LR		 242 struct ath_buf *bf_lastfrm; /* last buf of this frame */
243 struct ath_buf *bf_next; /* next subframe in the aggregate */
244 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */
245 void *bf_mpdu; /* enclosing frame structure */
f078f209
LR		 246 struct ath_desc *bf_desc; /* virtual addr of desc */
247 dma_addr_t bf_daddr; /* physical addr of desc */
248 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
249 u32 bf_status;
f22f558d 250 u16 bf_flags; /* tx descriptor flags */
f078f209
LR		 251 struct ath_buf_state bf_state; /* buffer state */
252 dma_addr_t bf_dmacontext;
253};
254
255/*
256 * reset the rx buffer.
257 * any new fields added to the athbuf and require
258 * reset need to be added to this macro.
259 * currently bf_status is the only one requires that
260 * requires reset.
261 */
262#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
263
264/* hw processing complete, desc processed by hal */
265#define ATH_BUFSTATUS_DONE 0x00000001
266/* hw processing complete, desc hold for hw */
267#define ATH_BUFSTATUS_STALE 0x00000002
268/* Rx-only: OS is done with this packet and it's ok to queued it to hw */
269#define ATH_BUFSTATUS_FREE 0x00000004
270
271/* DMA state for tx/rx descriptors */
272
273struct ath_descdma {
274 const char *dd_name;
275 struct ath_desc *dd_desc; /* descriptors */
276 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
277 u32 dd_desc_len; /* size of dd_desc */
278 struct ath_buf *dd_bufptr; /* associated buffers */
279 dma_addr_t dd_dmacontext;
280};
281
282/* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
283
284struct ath_rx_context {
285 struct ath_buf *ctx_rxbuf; /* associated ath_buf for rx */
286};
287#define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
288
289int ath_descdma_setup(struct ath_softc *sc,
290 struct ath_descdma *dd,
291 struct list_head *head,
292 const char *name,
293 int nbuf,
294 int ndesc);
295int ath_desc_alloc(struct ath_softc *sc);
296void ath_desc_free(struct ath_softc *sc);
297void ath_descdma_cleanup(struct ath_softc *sc,
298 struct ath_descdma *dd,
299 struct list_head *head);
300
301/******/
302/* RX */
303/******/
304
305#define ATH_MAX_ANTENNA 3
306#define ATH_RXBUF 512
307#define ATH_RX_TIMEOUT 40 /* 40 milliseconds */
308#define WME_NUM_TID 16
309#define IEEE80211_BAR_CTL_TID_M 0xF000 /* tid mask */
a477e4e6 310#define IEEE80211_BAR_CTL_TID_S 12 /* tid shift */
f078f209
LR		 311
312enum ATH_RX_TYPE {
313 ATH_RX_NON_CONSUMED = 0,
314 ATH_RX_CONSUMED
315};
316
317/* per frame rx status block */
318struct ath_recv_status {
319 u64 tsf; /* mac tsf */
320 int8_t rssi; /* RSSI (noise floor ajusted) */
321 int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
322 int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
323 int8_t abs_rssi; /* absolute RSSI */
f22f558d
S		 324 u8 rateieee; /* data rate received (IEEE rate code) */
325 u8 ratecode; /* phy rate code */
f078f209
LR		 326 int rateKbps; /* data rate received (Kbps) */
327 int antenna; /* rx antenna */
328 int flags; /* status of associated skb */
329#define ATH_RX_FCS_ERROR 0x01
330#define ATH_RX_MIC_ERROR 0x02
331#define ATH_RX_DECRYPT_ERROR 0x04
332#define ATH_RX_RSSI_VALID 0x08
333/* if any of ctl,extn chainrssis are valid */
334#define ATH_RX_CHAIN_RSSI_VALID 0x10
335/* if extn chain rssis are valid */
336#define ATH_RX_RSSI_EXTN_VALID 0x20
337/* set if 40Mhz, clear if 20Mhz */
338#define ATH_RX_40MHZ 0x40
339/* set if short GI, clear if full GI */
340#define ATH_RX_SHORT_GI 0x80
341};
342
343struct ath_rxbuf {
f22f558d
S		 344 struct sk_buff *rx_wbuf;
345 unsigned long rx_time; /* system time when received */
346 struct ath_recv_status rx_status; /* cached rx status */
f078f209
LR		 347};
348
349/* Per-TID aggregate receiver state for a node */
350struct ath_arx_tid {
f22f558d
S		 351 struct ath_node *an;
352 struct ath_rxbuf *rxbuf; /* re-ordering buffer */
353 struct timer_list timer;
354 spinlock_t tidlock;
355 int baw_head; /* seq_next at head */
356 int baw_tail; /* tail of block-ack window */
357 int seq_reset; /* need to reset start sequence */
358 int addba_exchangecomplete;
359 u16 seq_next; /* next expected sequence */
360 u16 baw_size; /* block-ack window size */
f078f209
LR		 361};
362
363/* Per-node receiver aggregate state */
364struct ath_arx {
f22f558d 365 struct ath_arx_tid tid[WME_NUM_TID];
f078f209
LR		 366};
367
368int ath_startrecv(struct ath_softc *sc);
369bool ath_stoprecv(struct ath_softc *sc);
370void ath_flushrecv(struct ath_softc *sc);
371u32 ath_calcrxfilter(struct ath_softc *sc);
372void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
c5170163 373void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
f078f209
LR		 374void ath_handle_rx_intr(struct ath_softc *sc);
375int ath_rx_init(struct ath_softc *sc, int nbufs);
376void ath_rx_cleanup(struct ath_softc *sc);
377int ath_rx_tasklet(struct ath_softc *sc, int flush);
378int ath_rx_input(struct ath_softc *sc,
379 struct ath_node *node,
f078f209
LR		 380 struct sk_buff *skb,
381 struct ath_recv_status *rx_status,
382 enum ATH_RX_TYPE *status);
19b73c7f
S		 383int _ath_rx_indicate(struct ath_softc *sc,
384 struct sk_buff *skb,
385 struct ath_recv_status *status,
386 u16 keyix);
f078f209
LR		 387int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
388 struct ath_recv_status *status);
389
390/******/
391/* TX */
392/******/
393
556bb8f1 394#define ATH_TXBUF 512
f078f209
LR		 395/* max number of transmit attempts (tries) */
396#define ATH_TXMAXTRY 13
397/* max number of 11n transmit attempts (tries) */
398#define ATH_11N_TXMAXTRY 10
399/* max number of tries for management and control frames */
400#define ATH_MGT_TXMAXTRY 4
401#define WME_BA_BMP_SIZE 64
402#define WME_MAX_BA WME_BA_BMP_SIZE
403#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
404#define TID_TO_WME_AC(_tid) \
405 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
406 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
407 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
408 WME_AC_VO)
409
410
411/* Wireless Multimedia Extension Defines */
412#define WME_AC_BE 0 /* best effort */
413#define WME_AC_BK 1 /* background */
414#define WME_AC_VI 2 /* video */
415#define WME_AC_VO 3 /* voice */
416#define WME_NUM_AC 4
417
f078f209
LR		 418/*
419 * Data transmit queue state. One of these exists for each
420 * hardware transmit queue. Packets sent to us from above
421 * are assigned to queues based on their priority. Not all
422 * devices support a complete set of hardware transmit queues.
423 * For those devices the array sc_ac2q will map multiple
424 * priorities to fewer hardware queues (typically all to one
425 * hardware queue).
426 */
427struct ath_txq {
f22f558d
S		 428 u32 axq_qnum; /* hardware q number */
429 u32 *axq_link; /* link ptr in last TX desc */
430 struct list_head axq_q; /* transmit queue */
431 spinlock_t axq_lock;
432 unsigned long axq_lockflags; /* intr state when must cli */
433 u32 axq_depth; /* queue depth */
434 u8 axq_aggr_depth; /* aggregates queued */
435 u32 axq_totalqueued; /* total ever queued */
436
f22f558d
S		 437 bool stopped; /* Is mac80211 queue stopped ? */
438 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
439
440 /* first desc of the last descriptor that contains CTS */
441 struct ath_desc *axq_lastdsWithCTS;
442
443 /* final desc of the gating desc that determines whether
444 lastdsWithCTS has been DMA'ed or not */
445 struct ath_desc *axq_gatingds;
446
447 struct list_head axq_acq;
f078f209
LR		 448};
449
450/* per TID aggregate tx state for a destination */
451struct ath_atx_tid {
f22f558d
S		 452 struct list_head list; /* round-robin tid entry */
453 struct list_head buf_q; /* pending buffers */
454 struct ath_node *an;
455 struct ath_atx_ac *ac;
456 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
457 u16 seq_start;
458 u16 seq_next;
459 u16 baw_size;
460 int tidno;
461 int baw_head; /* first un-acked tx buffer */
462 int baw_tail; /* next unused tx buffer slot */
463 int sched;
464 int paused;
465 int cleanup_inprogress;
466 u32 addba_exchangecomplete:1;
467 int32_t addba_exchangeinprogress;
468 int addba_exchangeattempts;
f078f209
LR		 469};
470
471/* per access-category aggregate tx state for a destination */
472struct ath_atx_ac {
f22f558d
S		 473 int sched; /* dest-ac is scheduled */
474 int qnum; /* H/W queue number associated
475 with this AC */
476 struct list_head list; /* round-robin txq entry */
477 struct list_head tid_q; /* queue of TIDs with buffers */
f078f209
LR		 478};
479
480/* per dest tx state */
481struct ath_atx {
f22f558d
S		 482 struct ath_atx_tid tid[WME_NUM_TID];
483 struct ath_atx_ac ac[WME_NUM_AC];
f078f209
LR		 484};
485
486/* per-frame tx control block */
487struct ath_tx_control {
528f0c6b 488 struct ath_txq *txq;
f22f558d 489 int if_id;
f078f209
LR		 490};
491
492/* per frame tx status block */
493struct ath_xmit_status {
f22f558d
S		 494 int retries; /* number of retries to successufully
495 transmit this frame */
496 int flags; /* status of transmit */
f078f209
LR		 497#define ATH_TX_ERROR 0x01
498#define ATH_TX_XRETRY 0x02
499#define ATH_TX_BAR 0x04
500};
501
502struct ath_tx_stat {
503 int rssi; /* RSSI (noise floor ajusted) */
504 int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
505 int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
506 int rateieee; /* data rate xmitted (IEEE rate code) */
507 int rateKbps; /* data rate xmitted (Kbps) */
508 int ratecode; /* phy rate code */
509 int flags; /* validity flags */
510/* if any of ctl,extn chain rssis are valid */
511#define ATH_TX_CHAIN_RSSI_VALID 0x01
512/* if extn chain rssis are valid */
513#define ATH_TX_RSSI_EXTN_VALID 0x02
514 u32 airtime; /* time on air per final tx rate */
515};
516
517struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
518void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
519int ath_tx_setup(struct ath_softc *sc, int haltype);
520void ath_draintxq(struct ath_softc *sc, bool retry_tx);
521void ath_tx_draintxq(struct ath_softc *sc,
556bb8f1 522 struct ath_txq *txq, bool retry_tx);
f078f209 523void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
b5aa9bf9 524void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
f078f209
LR		 525void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
526void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
527int ath_tx_init(struct ath_softc *sc, int nbufs);
528int ath_tx_cleanup(struct ath_softc *sc);
529int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
528f0c6b 530struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
ea9880fb
S		 531int ath_txq_update(struct ath_softc *sc, int qnum,
532 struct ath9k_tx_queue_info *q);
528f0c6b
S		 533int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
534 struct ath_tx_control *txctl);
f078f209
LR		 535void ath_tx_tasklet(struct ath_softc *sc);
536u32 ath_txq_depth(struct ath_softc *sc, int qnum);
537u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
538void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
539void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
528f0c6b 540 struct ath_xmit_status *tx_status);
e022edbd 541void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
f078f209
LR		 542
543/**********************/
544/* Node / Aggregation */
545/**********************/
546
f078f209
LR		 547#define ADDBA_EXCHANGE_ATTEMPTS 10
548#define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
549#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
550/* number of delimiters for encryption padding */
551#define ATH_AGGR_ENCRYPTDELIM 10
552/* minimum h/w qdepth to be sustained to maximize aggregation */
553#define ATH_AGGR_MIN_QDEPTH 2
554#define ATH_AMPDU_SUBFRAME_DEFAULT 32
555#define IEEE80211_SEQ_SEQ_SHIFT 4
556#define IEEE80211_SEQ_MAX 4096
557#define IEEE80211_MIN_AMPDU_BUF 0x8
b5aa9bf9 558#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
f078f209
LR		 559
560/* return whether a bit at index _n in bitmap _bm is set
561 * _sz is the size of the bitmap */
562#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
563 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
564
565/* return block-ack bitmap index given sequence and starting sequence */
566#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
567
568/* returns delimiter padding required given the packet length */
569#define ATH_AGGR_GET_NDELIM(_len) \
570 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
571 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
572
573#define BAW_WITHIN(_start, _bawsz, _seqno) \
574 ((((_seqno) - (_start)) & 4095) < (_bawsz))
575
576#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
577#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
578#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
579#define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
580
581enum ATH_AGGR_STATUS {
582 ATH_AGGR_DONE,
583 ATH_AGGR_BAW_CLOSED,
584 ATH_AGGR_LIMITED,
585 ATH_AGGR_SHORTPKT,
586 ATH_AGGR_8K_LIMITED,
587};
588
589enum ATH_AGGR_CHECK {
590 AGGR_NOT_REQUIRED,
591 AGGR_REQUIRED,
592 AGGR_CLEANUP_PROGRESS,
593 AGGR_EXCHANGE_PROGRESS,
594 AGGR_EXCHANGE_DONE
595};
596
597struct aggr_rifs_param {
598 int param_max_frames;
599 int param_max_len;
600 int param_rl;
601 int param_al;
602 struct ath_rc_series *param_rcs;
603};
604
605/* Per-node aggregation state */
606struct ath_node_aggr {
f22f558d
S		 607 struct ath_atx tx; /* node transmit state */
608 struct ath_arx rx; /* node receive state */
f078f209
LR		 609};
610
611/* driver-specific node state */
612struct ath_node {
f22f558d 613 struct ath_softc *an_sc;
f078f209 614 struct ath_chainmask_sel an_chainmask_sel;
f22f558d 615 struct ath_node_aggr an_aggr;
ae5eb026
JB		 616 u16 maxampdu;
617 u8 mpdudensity;
f078f209
LR		 618};
619
620void ath_tx_resume_tid(struct ath_softc *sc,
621 struct ath_atx_tid *tid);
622enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
623 struct ath_node *an, u8 tidno);
624void ath_tx_aggr_teardown(struct ath_softc *sc,
625 struct ath_node *an, u8 tidno);
626void ath_rx_aggr_teardown(struct ath_softc *sc,
627 struct ath_node *an, u8 tidno);
b5aa9bf9
S		 628int ath_rx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
629 u16 tid, u16 *ssn);
630int ath_rx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
631int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
632 u16 tid, u16 *ssn);
633int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
f078f209
LR		 634void ath_newassoc(struct ath_softc *sc,
635 struct ath_node *node, int isnew, int isuapsd);
b5aa9bf9
S		 636void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
637 int if_id);
638void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta);
f078f209
LR		 639
640/*******************/
641/* Beacon Handling */
642/*******************/
643
644/*
645 * Regardless of the number of beacons we stagger, (i.e. regardless of the
646 * number of BSSIDs) if a given beacon does not go out even after waiting this
647 * number of beacon intervals, the game's up.
648 */
649#define BSTUCK_THRESH (9 * ATH_BCBUF)
650#define ATH_BCBUF 4 /* number of beacon buffers */
651#define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
652#define ATH_DEFAULT_BMISS_LIMIT 10
f078f209
LR		 653#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
654
655/* beacon configuration */
656struct ath_beacon_config {
657 u16 beacon_interval;
658 u16 listen_interval;
659 u16 dtim_period;
660 u16 bmiss_timeout;
661 u8 dtim_count;
662 u8 tim_offset;
663 union {
664 u64 last_tsf;
665 u8 last_tstamp[8];
666 } u; /* last received beacon/probe response timestamp of this BSS. */
667};
668
f078f209
LR		 669void ath9k_beacon_tasklet(unsigned long data);
670void ath_beacon_config(struct ath_softc *sc, int if_id);
671int ath_beaconq_setup(struct ath_hal *ah);
672int ath_beacon_alloc(struct ath_softc *sc, int if_id);
673void ath_bstuck_process(struct ath_softc *sc);
f078f209
LR		 674void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
675void ath_beacon_sync(struct ath_softc *sc, int if_id);
f078f209
LR		 676void ath_get_beaconconfig(struct ath_softc *sc,
677 int if_id,
678 struct ath_beacon_config *conf);
f078f209
LR		 679/********/
680/* VAPs */
681/********/
682
f078f209
LR		 683/*
684 * Define the scheme that we select MAC address for multiple
685 * BSS on the same radio. The very first VAP will just use the MAC
686 * address from the EEPROM. For the next 3 VAPs, we set the
687 * U/L bit (bit 1) in MAC address, and use the next two bits as the
688 * index of the VAP.
689 */
690
691#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
692 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
693
694/* VAP configuration (from protocol layer) */
695struct ath_vap_config {
696 u32 av_fixed_rateset;
697 u32 av_fixed_retryset;
698};
699
700/* driver-specific vap state */
701struct ath_vap {
f22f558d
S		 702 struct ieee80211_vif *av_if_data;
703 enum ath9k_opmode av_opmode; /* VAP operational mode */
704 struct ath_buf *av_bcbuf; /* beacon buffer */
f22f558d
S		 705 struct ath_tx_control av_btxctl; /* txctl information for beacon */
706 int av_bslot; /* beacon slot index */
f22f558d
S		 707 struct ath_vap_config av_config;/* vap configuration parameters*/
708 struct ath_rate_node *rc_node;
f078f209
LR		 709};
710
711int ath_vap_attach(struct ath_softc *sc,
712 int if_id,
713 struct ieee80211_vif *if_data,
714 enum ath9k_opmode opmode);
715int ath_vap_detach(struct ath_softc *sc, int if_id);
716int ath_vap_config(struct ath_softc *sc,
ff9b662d 717 int if_id, struct ath_vap_config *if_config);
f078f209
LR		 718
719/*********************/
720/* Antenna diversity */
721/*********************/
722
723#define ATH_ANT_DIV_MAX_CFG 2
724#define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */
725#define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */
726
727enum ATH_ANT_DIV_STATE{
728 ATH_ANT_DIV_IDLE,
729 ATH_ANT_DIV_SCAN, /* evaluating antenna */
730};
731
732struct ath_antdiv {
733 struct ath_softc *antdiv_sc;
734 u8 antdiv_start;
735 enum ATH_ANT_DIV_STATE antdiv_state;
736 u8 antdiv_num_antcfg;
737 u8 antdiv_curcfg;
738 u8 antdiv_bestcfg;
739 int32_t antdivf_rssitrig;
740 int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
741 u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
742 u64 antdiv_laststatetsf;
743 u8 antdiv_bssid[ETH_ALEN];
744};
745
746void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
747 struct ath_softc *sc, int32_t rssitrig);
748void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
749 u8 num_antcfg,
750 const u8 *bssid);
751void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
752void ath_slow_ant_div(struct ath_antdiv *antdiv,
753 struct ieee80211_hdr *wh,
754 struct ath_rx_status *rx_stats);
755void ath_setdefantenna(void *sc, u32 antenna);
756
6f255425
LR		 757/*******/
758/* ANI */
759/*******/
760
761/* ANI values for STA only.
762 FIXME: Add appropriate values for AP later */
763
764#define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
765#define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
766#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
767#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
768
769struct ath_ani {
770 bool sc_caldone;
771 int16_t sc_noise_floor;
772 unsigned int sc_longcal_timer;
773 unsigned int sc_shortcal_timer;
774 unsigned int sc_resetcal_timer;
775 unsigned int sc_checkani_timer;
776 struct timer_list timer;
777};
778
c83be688
VT		 779/********************/
780/* LED Control */
781/********************/
782
783#define ATH_LED_PIN 1
784
785enum ath_led_type {
786 ATH_LED_RADIO,
787 ATH_LED_ASSOC,
788 ATH_LED_TX,
789 ATH_LED_RX
790};
791
792struct ath_led {
793 struct ath_softc *sc;
794 struct led_classdev led_cdev;
795 enum ath_led_type led_type;
796 char name[32];
797 bool registered;
798};
799
500c064d
VT		 800/* Rfkill */
801#define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
802
803struct ath_rfkill {
804 struct rfkill *rfkill;
805 struct delayed_work rfkill_poll;
806 char rfkill_name[32];
807};
808
f078f209
LR		 809/********************/
810/* Main driver core */
811/********************/
812
813/*
814 * Default cache line size, in bytes.
815 * Used when PCI device not fully initialized by bootrom/BIOS
816*/
817#define DEFAULT_CACHELINE 32
818#define ATH_DEFAULT_NOISE_FLOOR -95
819#define ATH_REGCLASSIDS_MAX 10
820#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
f078f209 821#define ATH_MAX_SW_RETRIES 10
f078f209
LR		 822#define ATH_CHAN_MAX 255
823#define IEEE80211_WEP_NKID 4 /* number of key ids */
824#define IEEE80211_RATE_VAL 0x7f
825/*
826 * The key cache is used for h/w cipher state and also for
827 * tracking station state such as the current tx antenna.
828 * We also setup a mapping table between key cache slot indices
829 * and station state to short-circuit node lookups on rx.
830 * Different parts have different size key caches. We handle
831 * up to ATH_KEYMAX entries (could dynamically allocate state).
832 */
833#define ATH_KEYMAX 128 /* max key cache size we handle */
834
f078f209 835#define ATH_IF_ID_ANY 0xff
f078f209
LR		 836#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
837
838#define RSSI_LPF_THRESHOLD -20
839#define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
840#define ATH_RATE_DUMMY_MARKER 0
841#define ATH_RSSI_LPF_LEN 10
842#define ATH_RSSI_DUMMY_MARKER 0x127
843
844#define ATH_EP_MUL(x, mul) ((x) * (mul))
845#define ATH_EP_RND(x, mul) \
846 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
847#define ATH_RSSI_OUT(x) \
848 (((x) != ATH_RSSI_DUMMY_MARKER) ? \
849 (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
850#define ATH_RSSI_IN(x) \
851 (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
852#define ATH_LPF_RSSI(x, y, len) \
853 ((x != ATH_RSSI_DUMMY_MARKER) ? \
854 (((x) * ((len) - 1) + (y)) / (len)) : (y))
855#define ATH_RSSI_LPF(x, y) do { \
856 if ((y) >= RSSI_LPF_THRESHOLD) \
857 x = ATH_LPF_RSSI((x), \
858 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
859 } while (0)
860
861
862enum PROT_MODE {
863 PROT_M_NONE = 0,
864 PROT_M_RTSCTS,
865 PROT_M_CTSONLY
866};
867
868enum RATE_TYPE {
869 NORMAL_RATE = 0,
870 HALF_RATE,
871 QUARTER_RATE
872};
873
874struct ath_ht_info {
875 enum ath9k_ht_macmode tx_chan_width;
f078f209
LR		 876 u8 ext_chan_offset;
877};
878
672840ac
S		 879#define SC_OP_INVALID BIT(0)
880#define SC_OP_BEACONS BIT(1)
881#define SC_OP_RXAGGR BIT(2)
882#define SC_OP_TXAGGR BIT(3)
883#define SC_OP_CHAINMASK_UPDATE BIT(4)
884#define SC_OP_FULL_RESET BIT(5)
98deeea0
S		 885#define SC_OP_NO_RESET BIT(6)
886#define SC_OP_PREAMBLE_SHORT BIT(7)
887#define SC_OP_PROTECT_ENABLE BIT(8)
888#define SC_OP_RXFLUSH BIT(9)
c83be688 889#define SC_OP_LED_ASSOCIATED BIT(10)
500c064d
VT		 890#define SC_OP_RFKILL_REGISTERED BIT(11)
891#define SC_OP_RFKILL_SW_BLOCKED BIT(12)
892#define SC_OP_RFKILL_HW_BLOCKED BIT(13)
672840ac 893
f078f209 894struct ath_softc {
ea9880fb
S		 895 struct ieee80211_hw *hw;
896 struct pci_dev *pdev;
ea9880fb
S		 897 struct tasklet_struct intr_tq;
898 struct tasklet_struct bcon_tasklet;
672840ac 899 struct ath_config sc_config;
ea9880fb 900 struct ath_hal *sc_ah;
672840ac 901 struct ath_rate_softc *sc_rc;
b4696c8b
S		 902 void __iomem *mem;
903
98deeea0
S		 904 u8 sc_curbssid[ETH_ALEN];
905 u8 sc_myaddr[ETH_ALEN];
906 u8 sc_bssidmask[ETH_ALEN];
907
b4696c8b 908 int sc_debug;
ea9880fb 909 u32 sc_intrstatus;
672840ac 910 u32 sc_flags; /* SC_OP_* */
7dcfdcd9 911 unsigned int rx_filter;
ea9880fb
S		 912 u16 sc_curtxpow;
913 u16 sc_curaid;
98deeea0
S		 914 u16 sc_cachelsz;
915 int sc_slotupdate; /* slot to next advance fsm */
916 int sc_slottime;
917 int sc_bslot[ATH_BCBUF];
918 u8 sc_tx_chainmask;
919 u8 sc_rx_chainmask;
920 enum ath9k_int sc_imask;
921 enum wireless_mode sc_curmode; /* current phy mode */
ea9880fb 922 enum PROT_MODE sc_protmode;
98deeea0 923
ea9880fb
S		 924 u8 sc_nbcnvaps; /* # of vaps sending beacons */
925 u16 sc_nvaps; /* # of active virtual ap's */
926 struct ath_vap *sc_vaps[ATH_BCBUF];
98deeea0
S		 927
928 u8 sc_mcastantenna;
ea9880fb
S		 929 u8 sc_defant; /* current default antenna */
930 u8 sc_rxotherant; /* rx's on non-default antenna */
98deeea0 931
ea9880fb 932 struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
ea9880fb 933 struct ath_ht_info sc_ht_info;
ea9880fb 934 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
98deeea0 935
f078f209 936#ifdef CONFIG_SLOW_ANT_DIV
ea9880fb 937 struct ath_antdiv sc_antdiv;
f078f209
LR		 938#endif
939 enum {
ea9880fb
S		 940 OK, /* no change needed */
941 UPDATE, /* update pending */
942 COMMIT /* beacon sent, commit change */
943 } sc_updateslot; /* slot time update fsm */
f078f209
LR		 944
945 /* Crypto */
ea9880fb
S		 946 u32 sc_keymax; /* size of key cache */
947 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */
948 u8 sc_splitmic; /* split TKIP MIC keys */
f078f209
LR		 949
950 /* RX */
ea9880fb
S		 951 struct list_head sc_rxbuf;
952 struct ath_descdma sc_rxdma;
953 int sc_rxbufsize; /* rx size based on mtu */
954 u32 *sc_rxlink; /* link ptr in last RX desc */
f078f209
LR		 955
956 /* TX */
ea9880fb
S		 957 struct list_head sc_txbuf;
958 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
959 struct ath_descdma sc_txdma;
960 u32 sc_txqsetup;
ea9880fb 961 int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */
147583c0 962 u16 seq_no; /* TX sequence number */
f078f209
LR		 963
964 /* Beacon */
ea9880fb
S		 965 struct ath9k_tx_queue_info sc_beacon_qi;
966 struct ath_descdma sc_bdma;
967 struct ath_txq *sc_cabq;
968 struct list_head sc_bbuf;
969 u32 sc_bhalq;
970 u32 sc_bmisscount;
971 u32 ast_be_xmit; /* beacons transmitted */
459f5f90 972 u64 bc_tstamp;
f078f209
LR		 973
974 /* Rate */
ea9880fb 975 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
ea9880fb
S		 976 const struct ath9k_rate_table *sc_currates;
977 u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */
ea9880fb 978 u8 sc_protrix; /* protection rate index */
f078f209 979 struct {
ea9880fb
S		 980 u32 rateKbps; /* transfer rate in kbs */
981 u8 ieeerate; /* IEEE rate */
982 } sc_hwmap[256]; /* h/w rate ix mappings */
f078f209
LR		 983
984 /* Channel, Band */
985 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
986 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
f078f209
LR		 987
988 /* Locks */
ea9880fb
S		 989 spinlock_t sc_rxflushlock;
990 spinlock_t sc_rxbuflock;
991 spinlock_t sc_txbuflock;
992 spinlock_t sc_resetlock;
c83be688
VT		 993
994 /* LEDs */
995 struct ath_led radio_led;
996 struct ath_led assoc_led;
997 struct ath_led tx_led;
998 struct ath_led rx_led;
500c064d
VT		 999
1000 /* Rfkill */
1001 struct ath_rfkill rf_kill;
6f255425
LR		 1002
1003 /* ANI */
1004 struct ath_ani sc_ani;
f078f209
LR		 1005};
1006
1007int ath_init(u16 devid, struct ath_softc *sc);
1008void ath_deinit(struct ath_softc *sc);
1009int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
1010int ath_suspend(struct ath_softc *sc);
1011irqreturn_t ath_isr(int irq, void *dev);
f45144ef 1012int ath_reset(struct ath_softc *sc, bool retry_tx);
f078f209 1013int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
f078f209
LR		 1014
1015/*********************/
1016/* Utility Functions */
1017/*********************/
1018
1019void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
1020int ath_keyset(struct ath_softc *sc,
1021 u16 keyix,
1022 struct ath9k_keyval *hk,
1023 const u8 mac[ETH_ALEN]);
1024int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
1025int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
1026void ath_setslottime(struct ath_softc *sc);
1027void ath_update_txpow(struct ath_softc *sc);
1028int ath_cabq_update(struct ath_softc *);
1029void ath_get_currentCountry(struct ath_softc *sc,
1030 struct ath9k_country_entry *ctry);
1031u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);
f078f209
LR		 1032
1033#endif /* CORE_H */
Linux kernel - Deliverables
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