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ath9k: Fix TX status reporting
[deliverable/linux.git] / drivers / net / wireless / ath9k / core.h
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef CORE_H
18#define CORE_H
19
20#include <linux/version.h>
21#include <linux/autoconf.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/spinlock.h>
25#include <linux/errno.h>
26#include <linux/skbuff.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/ip.h>
30#include <linux/tcp.h>
31#include <linux/in.h>
32#include <linux/delay.h>
33#include <linux/wait.h>
34#include <linux/pci.h>
35#include <linux/interrupt.h>
36#include <linux/sched.h>
37#include <linux/list.h>
38#include <asm/byteorder.h>
39#include <linux/scatterlist.h>
40#include <asm/page.h>
41#include <net/mac80211.h>
42
43#include "ath9k.h"
44#include "rc.h"
45
46struct ath_node;
47
48/******************/
49/* Utility macros */
50/******************/
51
52/* Macro to expand scalars to 64-bit objects */
53
f22f558d
S		 54#define ito64(x) (sizeof(x) == 8) ? \
55 (((unsigned long long int)(x)) & (0xff)) : \
56 (sizeof(x) == 16) ? \
57 (((unsigned long long int)(x)) & 0xffff) : \
58 ((sizeof(x) == 32) ? \
f078f209 59 (((unsigned long long int)(x)) & 0xffffffff) : \
f22f558d 60 (unsigned long long int)(x))
f078f209
LR		 61
62/* increment with wrap-around */
f22f558d
S		 63#define INCR(_l, _sz) do { \
64 (_l)++; \
65 (_l) &= ((_sz) - 1); \
f078f209
LR		 66 } while (0)
67
68/* decrement with wrap-around */
f22f558d
S		 69#define DECR(_l, _sz) do { \
70 (_l)--; \
71 (_l) &= ((_sz) - 1); \
f078f209
LR		 72 } while (0)
73
74#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
75
76#define ASSERT(exp) do { \
77 if (unlikely(!(exp))) { \
78 BUG(); \
79 } \
80 } while (0)
81
82/* XXX: remove */
83#define memzero(_buf, _len) memset(_buf, 0, _len)
84
85#define get_dma_mem_context(var, field) (&((var)->field))
86#define copy_dma_mem_context(dst, src) (*dst = *src)
87
88#define ATH9K_BH_STATUS_INTACT 0
89#define ATH9K_BH_STATUS_CHANGE 1
90
91#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
92
93static inline unsigned long get_timestamp(void)
94{
95 return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
96}
97
7dcfdcd9
S		 98static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
99
f078f209
LR		 100/*************/
101/* Debugging */
102/*************/
103
104enum ATH_DEBUG {
105 ATH_DBG_RESET = 0x00000001,
106 ATH_DBG_PHY_IO = 0x00000002,
107 ATH_DBG_REG_IO = 0x00000004,
108 ATH_DBG_QUEUE = 0x00000008,
109 ATH_DBG_EEPROM = 0x00000010,
110 ATH_DBG_NF_CAL = 0x00000020,
111 ATH_DBG_CALIBRATE = 0x00000040,
112 ATH_DBG_CHANNEL = 0x00000080,
113 ATH_DBG_INTERRUPT = 0x00000100,
114 ATH_DBG_REGULATORY = 0x00000200,
115 ATH_DBG_ANI = 0x00000400,
116 ATH_DBG_POWER_MGMT = 0x00000800,
117 ATH_DBG_XMIT = 0x00001000,
118 ATH_DBG_BEACON = 0x00002000,
119 ATH_DBG_RATE = 0x00004000,
120 ATH_DBG_CONFIG = 0x00008000,
121 ATH_DBG_KEYCACHE = 0x00010000,
122 ATH_DBG_AGGR = 0x00020000,
123 ATH_DBG_FATAL = 0x00040000,
124 ATH_DBG_ANY = 0xffffffff
125};
126
127#define DBG_DEFAULT (ATH_DBG_FATAL)
128
129#define DPRINTF(sc, _m, _fmt, ...) do { \
130 if (sc->sc_debug & (_m)) \
131 printk(_fmt , ##__VA_ARGS__); \
132 } while (0)
133
134/***************************/
135/* Load-time Configuration */
136/***************************/
137
138/* Per-instance load-time (note: NOT run-time) configurations
139 * for Atheros Device */
140struct ath_config {
f22f558d
S		 141 u32 ath_aggr_prot;
142 u16 txpowlimit;
143 u16 txpowlimit_override;
144 u8 cabqReadytime; /* Cabq Readytime % */
145 u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */
f078f209
LR		 146};
147
148/***********************/
149/* Chainmask Selection */
150/***********************/
151
152#define ATH_CHAINMASK_SEL_TIMEOUT 6000
153/* Default - Number of last RSSI values that is used for
154 * chainmask selection */
155#define ATH_CHAINMASK_SEL_RSSI_CNT 10
156/* Means use 3x3 chainmask instead of configured chainmask */
157#define ATH_CHAINMASK_SEL_3X3 7
158/* Default - Rssi threshold below which we have to switch to 3x3 */
159#define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20
160/* Default - Rssi threshold above which we have to switch to
161 * user configured values */
162#define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35
163/* Struct to store the chainmask select related info */
164struct ath_chainmask_sel {
f22f558d
S		 165 struct timer_list timer;
166 int cur_tx_mask; /* user configured or 3x3 */
167 int cur_rx_mask; /* user configured or 3x3 */
168 int tx_avgrssi;
169 u8 switch_allowed:1, /* timer will set this */
170 cm_sel_enabled : 1;
f078f209
LR		 171};
172
173int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
174void ath_update_chainmask(struct ath_softc *sc, int is_ht);
175
176/*************************/
177/* Descriptor Management */
178/*************************/
179
f078f209
LR		 180#define ATH_TXBUF_RESET(_bf) do { \
181 (_bf)->bf_status = 0; \
182 (_bf)->bf_lastbf = NULL; \
183 (_bf)->bf_lastfrm = NULL; \
184 (_bf)->bf_next = NULL; \
185 memzero(&((_bf)->bf_state), \
186 sizeof(struct ath_buf_state)); \
187 } while (0)
188
cd3d39a6
S		 189enum buffer_type {
190 BUF_DATA = BIT(0),
191 BUF_AGGR = BIT(1),
192 BUF_AMPDU = BIT(2),
193 BUF_HT = BIT(3),
194 BUF_RETRY = BIT(4),
195 BUF_XRETRY = BIT(5),
196 BUF_SHORT_PREAMBLE = BIT(6),
197 BUF_BAR = BIT(7),
198 BUF_PSPOLL = BIT(8),
199 BUF_AGGR_BURST = BIT(9),
200 BUF_CALC_AIRTIME = BIT(10),
201};
202
f078f209 203struct ath_buf_state {
cd3d39a6
S		 204 int bfs_nframes; /* # frames in aggregate */
205 u16 bfs_al; /* length of aggregate */
206 u16 bfs_frmlen; /* length of frame */
207 int bfs_seqno; /* sequence number */
208 int bfs_tidno; /* tid of this frame */
209 int bfs_retries; /* current retries */
f078f209 210 struct ath_rc_series bfs_rcs[4]; /* rate series */
cd3d39a6 211 u32 bf_type; /* BUF_* (enum buffer_type) */
f078f209
LR		 212 /* key type use to encrypt this frame */
213 enum ath9k_key_type bfs_keytype;
214};
215
216#define bf_nframes bf_state.bfs_nframes
217#define bf_al bf_state.bfs_al
218#define bf_frmlen bf_state.bfs_frmlen
219#define bf_retries bf_state.bfs_retries
220#define bf_seqno bf_state.bfs_seqno
221#define bf_tidno bf_state.bfs_tidno
222#define bf_rcs bf_state.bfs_rcs
f078f209 223#define bf_keytype bf_state.bfs_keytype
cd3d39a6
S		 224#define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
225#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
226#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
227#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
228#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
229#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
230#define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
231#define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
232#define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
233#define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
f078f209
LR		 234
235/*
236 * Abstraction of a contiguous buffer to transmit/receive. There is only
237 * a single hw descriptor encapsulated here.
238 */
f078f209
LR		 239struct ath_buf {
240 struct list_head list;
241 struct list_head *last;
242 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
f22f558d 243 an aggregate) */
f078f209
LR		 244 struct ath_buf *bf_lastfrm; /* last buf of this frame */
245 struct ath_buf *bf_next; /* next subframe in the aggregate */
246 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */
247 void *bf_mpdu; /* enclosing frame structure */
248 void *bf_node; /* pointer to the node */
249 struct ath_desc *bf_desc; /* virtual addr of desc */
250 dma_addr_t bf_daddr; /* physical addr of desc */
251 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
252 u32 bf_status;
f22f558d 253 u16 bf_flags; /* tx descriptor flags */
f078f209
LR		 254 struct ath_buf_state bf_state; /* buffer state */
255 dma_addr_t bf_dmacontext;
256};
257
258/*
259 * reset the rx buffer.
260 * any new fields added to the athbuf and require
261 * reset need to be added to this macro.
262 * currently bf_status is the only one requires that
263 * requires reset.
264 */
265#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
266
267/* hw processing complete, desc processed by hal */
268#define ATH_BUFSTATUS_DONE 0x00000001
269/* hw processing complete, desc hold for hw */
270#define ATH_BUFSTATUS_STALE 0x00000002
271/* Rx-only: OS is done with this packet and it's ok to queued it to hw */
272#define ATH_BUFSTATUS_FREE 0x00000004
273
274/* DMA state for tx/rx descriptors */
275
276struct ath_descdma {
277 const char *dd_name;
278 struct ath_desc *dd_desc; /* descriptors */
279 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
280 u32 dd_desc_len; /* size of dd_desc */
281 struct ath_buf *dd_bufptr; /* associated buffers */
282 dma_addr_t dd_dmacontext;
283};
284
285/* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
286
287struct ath_rx_context {
288 struct ath_buf *ctx_rxbuf; /* associated ath_buf for rx */
289};
290#define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
291
292int ath_descdma_setup(struct ath_softc *sc,
293 struct ath_descdma *dd,
294 struct list_head *head,
295 const char *name,
296 int nbuf,
297 int ndesc);
298int ath_desc_alloc(struct ath_softc *sc);
299void ath_desc_free(struct ath_softc *sc);
300void ath_descdma_cleanup(struct ath_softc *sc,
301 struct ath_descdma *dd,
302 struct list_head *head);
303
304/******/
305/* RX */
306/******/
307
308#define ATH_MAX_ANTENNA 3
309#define ATH_RXBUF 512
310#define ATH_RX_TIMEOUT 40 /* 40 milliseconds */
311#define WME_NUM_TID 16
312#define IEEE80211_BAR_CTL_TID_M 0xF000 /* tid mask */
313#define IEEE80211_BAR_CTL_TID_S 2 /* tid shift */
314
315enum ATH_RX_TYPE {
316 ATH_RX_NON_CONSUMED = 0,
317 ATH_RX_CONSUMED
318};
319
320/* per frame rx status block */
321struct ath_recv_status {
322 u64 tsf; /* mac tsf */
323 int8_t rssi; /* RSSI (noise floor ajusted) */
324 int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
325 int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
326 int8_t abs_rssi; /* absolute RSSI */
f22f558d
S		 327 u8 rateieee; /* data rate received (IEEE rate code) */
328 u8 ratecode; /* phy rate code */
f078f209
LR		 329 int rateKbps; /* data rate received (Kbps) */
330 int antenna; /* rx antenna */
331 int flags; /* status of associated skb */
332#define ATH_RX_FCS_ERROR 0x01
333#define ATH_RX_MIC_ERROR 0x02
334#define ATH_RX_DECRYPT_ERROR 0x04
335#define ATH_RX_RSSI_VALID 0x08
336/* if any of ctl,extn chainrssis are valid */
337#define ATH_RX_CHAIN_RSSI_VALID 0x10
338/* if extn chain rssis are valid */
339#define ATH_RX_RSSI_EXTN_VALID 0x20
340/* set if 40Mhz, clear if 20Mhz */
341#define ATH_RX_40MHZ 0x40
342/* set if short GI, clear if full GI */
343#define ATH_RX_SHORT_GI 0x80
344};
345
346struct ath_rxbuf {
f22f558d
S		 347 struct sk_buff *rx_wbuf;
348 unsigned long rx_time; /* system time when received */
349 struct ath_recv_status rx_status; /* cached rx status */
f078f209
LR		 350};
351
352/* Per-TID aggregate receiver state for a node */
353struct ath_arx_tid {
f22f558d
S		 354 struct ath_node *an;
355 struct ath_rxbuf *rxbuf; /* re-ordering buffer */
356 struct timer_list timer;
357 spinlock_t tidlock;
358 int baw_head; /* seq_next at head */
359 int baw_tail; /* tail of block-ack window */
360 int seq_reset; /* need to reset start sequence */
361 int addba_exchangecomplete;
362 u16 seq_next; /* next expected sequence */
363 u16 baw_size; /* block-ack window size */
f078f209
LR		 364};
365
366/* Per-node receiver aggregate state */
367struct ath_arx {
f22f558d 368 struct ath_arx_tid tid[WME_NUM_TID];
f078f209
LR		 369};
370
371int ath_startrecv(struct ath_softc *sc);
372bool ath_stoprecv(struct ath_softc *sc);
373void ath_flushrecv(struct ath_softc *sc);
374u32 ath_calcrxfilter(struct ath_softc *sc);
375void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
376void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an);
377void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
378void ath_handle_rx_intr(struct ath_softc *sc);
379int ath_rx_init(struct ath_softc *sc, int nbufs);
380void ath_rx_cleanup(struct ath_softc *sc);
381int ath_rx_tasklet(struct ath_softc *sc, int flush);
382int ath_rx_input(struct ath_softc *sc,
383 struct ath_node *node,
384 int is_ampdu,
385 struct sk_buff *skb,
386 struct ath_recv_status *rx_status,
387 enum ATH_RX_TYPE *status);
388int ath__rx_indicate(struct ath_softc *sc,
389 struct sk_buff *skb,
390 struct ath_recv_status *status,
391 u16 keyix);
392int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
393 struct ath_recv_status *status);
394
395/******/
396/* TX */
397/******/
398
556bb8f1 399#define ATH_TXBUF 512
f078f209
LR		 400/* max number of transmit attempts (tries) */
401#define ATH_TXMAXTRY 13
402/* max number of 11n transmit attempts (tries) */
403#define ATH_11N_TXMAXTRY 10
404/* max number of tries for management and control frames */
405#define ATH_MGT_TXMAXTRY 4
406#define WME_BA_BMP_SIZE 64
407#define WME_MAX_BA WME_BA_BMP_SIZE
408#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
409#define TID_TO_WME_AC(_tid) \
410 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
411 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
412 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
413 WME_AC_VO)
414
415
416/* Wireless Multimedia Extension Defines */
417#define WME_AC_BE 0 /* best effort */
418#define WME_AC_BK 1 /* background */
419#define WME_AC_VI 2 /* video */
420#define WME_AC_VO 3 /* voice */
421#define WME_NUM_AC 4
422
423enum ATH_SM_PWRSAV{
424 ATH_SM_ENABLE,
425 ATH_SM_PWRSAV_STATIC,
426 ATH_SM_PWRSAV_DYNAMIC,
427};
428
429/*
430 * Data transmit queue state. One of these exists for each
431 * hardware transmit queue. Packets sent to us from above
432 * are assigned to queues based on their priority. Not all
433 * devices support a complete set of hardware transmit queues.
434 * For those devices the array sc_ac2q will map multiple
435 * priorities to fewer hardware queues (typically all to one
436 * hardware queue).
437 */
438struct ath_txq {
f22f558d
S		 439 u32 axq_qnum; /* hardware q number */
440 u32 *axq_link; /* link ptr in last TX desc */
441 struct list_head axq_q; /* transmit queue */
442 spinlock_t axq_lock;
443 unsigned long axq_lockflags; /* intr state when must cli */
444 u32 axq_depth; /* queue depth */
445 u8 axq_aggr_depth; /* aggregates queued */
446 u32 axq_totalqueued; /* total ever queued */
447
448 /* count to determine if descriptor should generate int on this txq. */
449 u32 axq_intrcnt;
450
451 bool stopped; /* Is mac80211 queue stopped ? */
452 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
453
454 /* first desc of the last descriptor that contains CTS */
455 struct ath_desc *axq_lastdsWithCTS;
456
457 /* final desc of the gating desc that determines whether
458 lastdsWithCTS has been DMA'ed or not */
459 struct ath_desc *axq_gatingds;
460
461 struct list_head axq_acq;
f078f209
LR		 462};
463
464/* per TID aggregate tx state for a destination */
465struct ath_atx_tid {
f22f558d
S		 466 struct list_head list; /* round-robin tid entry */
467 struct list_head buf_q; /* pending buffers */
468 struct ath_node *an;
469 struct ath_atx_ac *ac;
470 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
471 u16 seq_start;
472 u16 seq_next;
473 u16 baw_size;
474 int tidno;
475 int baw_head; /* first un-acked tx buffer */
476 int baw_tail; /* next unused tx buffer slot */
477 int sched;
478 int paused;
479 int cleanup_inprogress;
480 u32 addba_exchangecomplete:1;
481 int32_t addba_exchangeinprogress;
482 int addba_exchangeattempts;
f078f209
LR		 483};
484
485/* per access-category aggregate tx state for a destination */
486struct ath_atx_ac {
f22f558d
S		 487 int sched; /* dest-ac is scheduled */
488 int qnum; /* H/W queue number associated
489 with this AC */
490 struct list_head list; /* round-robin txq entry */
491 struct list_head tid_q; /* queue of TIDs with buffers */
f078f209
LR		 492};
493
494/* per dest tx state */
495struct ath_atx {
f22f558d
S		 496 struct ath_atx_tid tid[WME_NUM_TID];
497 struct ath_atx_ac ac[WME_NUM_AC];
f078f209
LR		 498};
499
500/* per-frame tx control block */
501struct ath_tx_control {
f22f558d
S		 502 struct ath_node *an;
503 int if_id;
504 int qnum;
505 u32 ht:1;
506 u32 ps:1;
507 u32 use_minrate:1;
508 enum ath9k_pkt_type atype;
509 enum ath9k_key_type keytype;
510 u32 flags;
511 u16 seqno;
512 u16 tidno;
513 u16 txpower;
514 u16 frmlen;
515 u32 keyix;
516 int min_rate;
517 int mcast_rate;
518 u16 nextfraglen;
519 struct ath_softc *dev;
f078f209
LR		 520 dma_addr_t dmacontext;
521};
522
523/* per frame tx status block */
524struct ath_xmit_status {
f22f558d
S		 525 int retries; /* number of retries to successufully
526 transmit this frame */
527 int flags; /* status of transmit */
f078f209
LR		 528#define ATH_TX_ERROR 0x01
529#define ATH_TX_XRETRY 0x02
530#define ATH_TX_BAR 0x04
531};
532
533struct ath_tx_stat {
534 int rssi; /* RSSI (noise floor ajusted) */
535 int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
536 int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
537 int rateieee; /* data rate xmitted (IEEE rate code) */
538 int rateKbps; /* data rate xmitted (Kbps) */
539 int ratecode; /* phy rate code */
540 int flags; /* validity flags */
541/* if any of ctl,extn chain rssis are valid */
542#define ATH_TX_CHAIN_RSSI_VALID 0x01
543/* if extn chain rssis are valid */
544#define ATH_TX_RSSI_EXTN_VALID 0x02
545 u32 airtime; /* time on air per final tx rate */
546};
547
548struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
549void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
550int ath_tx_setup(struct ath_softc *sc, int haltype);
551void ath_draintxq(struct ath_softc *sc, bool retry_tx);
552void ath_tx_draintxq(struct ath_softc *sc,
556bb8f1 553 struct ath_txq *txq, bool retry_tx);
f078f209
LR		 554void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
555void ath_tx_node_cleanup(struct ath_softc *sc,
556bb8f1 556 struct ath_node *an, bool bh_flag);
f078f209
LR		 557void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
558void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
559int ath_tx_init(struct ath_softc *sc, int nbufs);
560int ath_tx_cleanup(struct ath_softc *sc);
561int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
ea9880fb
S		 562int ath_txq_update(struct ath_softc *sc, int qnum,
563 struct ath9k_tx_queue_info *q);
f078f209
LR		 564int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb);
565void ath_tx_tasklet(struct ath_softc *sc);
566u32 ath_txq_depth(struct ath_softc *sc, int qnum);
567u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
568void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
569void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
570 struct ath_xmit_status *tx_status, struct ath_node *an);
571
572/**********************/
573/* Node / Aggregation */
574/**********************/
575
576/* indicates the node is clened up */
577#define ATH_NODE_CLEAN 0x1
578/* indicates the node is 80211 power save */
579#define ATH_NODE_PWRSAVE 0x2
580
f078f209
LR		 581#define ADDBA_EXCHANGE_ATTEMPTS 10
582#define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
583#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
584/* number of delimiters for encryption padding */
585#define ATH_AGGR_ENCRYPTDELIM 10
586/* minimum h/w qdepth to be sustained to maximize aggregation */
587#define ATH_AGGR_MIN_QDEPTH 2
588#define ATH_AMPDU_SUBFRAME_DEFAULT 32
589#define IEEE80211_SEQ_SEQ_SHIFT 4
590#define IEEE80211_SEQ_MAX 4096
591#define IEEE80211_MIN_AMPDU_BUF 0x8
592
593/* return whether a bit at index _n in bitmap _bm is set
594 * _sz is the size of the bitmap */
595#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
596 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
597
598/* return block-ack bitmap index given sequence and starting sequence */
599#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
600
601/* returns delimiter padding required given the packet length */
602#define ATH_AGGR_GET_NDELIM(_len) \
603 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
604 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
605
606#define BAW_WITHIN(_start, _bawsz, _seqno) \
607 ((((_seqno) - (_start)) & 4095) < (_bawsz))
608
609#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
610#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
611#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
612#define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
613
614enum ATH_AGGR_STATUS {
615 ATH_AGGR_DONE,
616 ATH_AGGR_BAW_CLOSED,
617 ATH_AGGR_LIMITED,
618 ATH_AGGR_SHORTPKT,
619 ATH_AGGR_8K_LIMITED,
620};
621
622enum ATH_AGGR_CHECK {
623 AGGR_NOT_REQUIRED,
624 AGGR_REQUIRED,
625 AGGR_CLEANUP_PROGRESS,
626 AGGR_EXCHANGE_PROGRESS,
627 AGGR_EXCHANGE_DONE
628};
629
630struct aggr_rifs_param {
631 int param_max_frames;
632 int param_max_len;
633 int param_rl;
634 int param_al;
635 struct ath_rc_series *param_rcs;
636};
637
638/* Per-node aggregation state */
639struct ath_node_aggr {
f22f558d
S		 640 struct ath_atx tx; /* node transmit state */
641 struct ath_arx rx; /* node receive state */
f078f209
LR		 642};
643
644/* driver-specific node state */
645struct ath_node {
f22f558d
S		 646 struct list_head list;
647 struct ath_softc *an_sc;
648 atomic_t an_refcnt;
f078f209 649 struct ath_chainmask_sel an_chainmask_sel;
f22f558d
S		 650 struct ath_node_aggr an_aggr;
651 u8 an_smmode; /* SM Power save mode */
652 u8 an_flags;
653 u8 an_addr[ETH_ALEN];
f078f209
LR		 654};
655
656void ath_tx_resume_tid(struct ath_softc *sc,
657 struct ath_atx_tid *tid);
658enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
659 struct ath_node *an, u8 tidno);
660void ath_tx_aggr_teardown(struct ath_softc *sc,
661 struct ath_node *an, u8 tidno);
662void ath_rx_aggr_teardown(struct ath_softc *sc,
663 struct ath_node *an, u8 tidno);
664int ath_rx_aggr_start(struct ath_softc *sc,
665 const u8 *addr,
666 u16 tid,
667 u16 *ssn);
668int ath_rx_aggr_stop(struct ath_softc *sc,
669 const u8 *addr,
670 u16 tid);
671int ath_tx_aggr_start(struct ath_softc *sc,
672 const u8 *addr,
673 u16 tid,
674 u16 *ssn);
675int ath_tx_aggr_stop(struct ath_softc *sc,
676 const u8 *addr,
677 u16 tid);
678void ath_newassoc(struct ath_softc *sc,
679 struct ath_node *node, int isnew, int isuapsd);
680struct ath_node *ath_node_attach(struct ath_softc *sc,
681 u8 addr[ETH_ALEN], int if_id);
682void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
683struct ath_node *ath_node_get(struct ath_softc *sc, u8 addr[ETH_ALEN]);
684void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
685struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr);
686
687/*******************/
688/* Beacon Handling */
689/*******************/
690
691/*
692 * Regardless of the number of beacons we stagger, (i.e. regardless of the
693 * number of BSSIDs) if a given beacon does not go out even after waiting this
694 * number of beacon intervals, the game's up.
695 */
696#define BSTUCK_THRESH (9 * ATH_BCBUF)
697#define ATH_BCBUF 4 /* number of beacon buffers */
698#define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
699#define ATH_DEFAULT_BMISS_LIMIT 10
f078f209
LR		 700#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
701
702/* beacon configuration */
703struct ath_beacon_config {
704 u16 beacon_interval;
705 u16 listen_interval;
706 u16 dtim_period;
707 u16 bmiss_timeout;
708 u8 dtim_count;
709 u8 tim_offset;
710 union {
711 u64 last_tsf;
712 u8 last_tstamp[8];
713 } u; /* last received beacon/probe response timestamp of this BSS. */
714};
715
716/* offsets in a beacon frame for
717 * quick acess of beacon content by low-level driver */
718struct ath_beacon_offset {
719 u8 *bo_tim; /* start of atim/dtim */
720};
721
722void ath9k_beacon_tasklet(unsigned long data);
723void ath_beacon_config(struct ath_softc *sc, int if_id);
724int ath_beaconq_setup(struct ath_hal *ah);
725int ath_beacon_alloc(struct ath_softc *sc, int if_id);
726void ath_bstuck_process(struct ath_softc *sc);
f078f209
LR		 727void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
728void ath_beacon_sync(struct ath_softc *sc, int if_id);
f078f209
LR		 729void ath_get_beaconconfig(struct ath_softc *sc,
730 int if_id,
731 struct ath_beacon_config *conf);
f078f209
LR		 732/********/
733/* VAPs */
734/********/
735
f078f209
LR		 736/*
737 * Define the scheme that we select MAC address for multiple
738 * BSS on the same radio. The very first VAP will just use the MAC
739 * address from the EEPROM. For the next 3 VAPs, we set the
740 * U/L bit (bit 1) in MAC address, and use the next two bits as the
741 * index of the VAP.
742 */
743
744#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
745 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
746
747/* VAP configuration (from protocol layer) */
748struct ath_vap_config {
749 u32 av_fixed_rateset;
750 u32 av_fixed_retryset;
751};
752
753/* driver-specific vap state */
754struct ath_vap {
f22f558d
S		 755 struct ieee80211_vif *av_if_data;
756 enum ath9k_opmode av_opmode; /* VAP operational mode */
757 struct ath_buf *av_bcbuf; /* beacon buffer */
758 struct ath_beacon_offset av_boff; /* dynamic update state */
759 struct ath_tx_control av_btxctl; /* txctl information for beacon */
760 int av_bslot; /* beacon slot index */
761 struct ath_txq av_mcastq; /* multicast transmit queue */
762 struct ath_vap_config av_config;/* vap configuration parameters*/
763 struct ath_rate_node *rc_node;
f078f209
LR		 764};
765
766int ath_vap_attach(struct ath_softc *sc,
767 int if_id,
768 struct ieee80211_vif *if_data,
769 enum ath9k_opmode opmode);
770int ath_vap_detach(struct ath_softc *sc, int if_id);
771int ath_vap_config(struct ath_softc *sc,
772 int if_id, struct ath_vap_config *if_config);
773int ath_vap_listen(struct ath_softc *sc, int if_id);
774
775/*********************/
776/* Antenna diversity */
777/*********************/
778
779#define ATH_ANT_DIV_MAX_CFG 2
780#define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */
781#define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */
782
783enum ATH_ANT_DIV_STATE{
784 ATH_ANT_DIV_IDLE,
785 ATH_ANT_DIV_SCAN, /* evaluating antenna */
786};
787
788struct ath_antdiv {
789 struct ath_softc *antdiv_sc;
790 u8 antdiv_start;
791 enum ATH_ANT_DIV_STATE antdiv_state;
792 u8 antdiv_num_antcfg;
793 u8 antdiv_curcfg;
794 u8 antdiv_bestcfg;
795 int32_t antdivf_rssitrig;
796 int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
797 u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
798 u64 antdiv_laststatetsf;
799 u8 antdiv_bssid[ETH_ALEN];
800};
801
802void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
803 struct ath_softc *sc, int32_t rssitrig);
804void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
805 u8 num_antcfg,
806 const u8 *bssid);
807void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
808void ath_slow_ant_div(struct ath_antdiv *antdiv,
809 struct ieee80211_hdr *wh,
810 struct ath_rx_status *rx_stats);
811void ath_setdefantenna(void *sc, u32 antenna);
812
813/********************/
814/* Main driver core */
815/********************/
816
817/*
818 * Default cache line size, in bytes.
819 * Used when PCI device not fully initialized by bootrom/BIOS
820*/
821#define DEFAULT_CACHELINE 32
822#define ATH_DEFAULT_NOISE_FLOOR -95
823#define ATH_REGCLASSIDS_MAX 10
824#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
f078f209 825#define ATH_MAX_SW_RETRIES 10
f078f209
LR		 826#define ATH_CHAN_MAX 255
827#define IEEE80211_WEP_NKID 4 /* number of key ids */
828#define IEEE80211_RATE_VAL 0x7f
829/*
830 * The key cache is used for h/w cipher state and also for
831 * tracking station state such as the current tx antenna.
832 * We also setup a mapping table between key cache slot indices
833 * and station state to short-circuit node lookups on rx.
834 * Different parts have different size key caches. We handle
835 * up to ATH_KEYMAX entries (could dynamically allocate state).
836 */
837#define ATH_KEYMAX 128 /* max key cache size we handle */
838
f078f209 839#define ATH_IF_ID_ANY 0xff
f078f209
LR		 840#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
841
842#define RSSI_LPF_THRESHOLD -20
843#define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
844#define ATH_RATE_DUMMY_MARKER 0
845#define ATH_RSSI_LPF_LEN 10
846#define ATH_RSSI_DUMMY_MARKER 0x127
847
848#define ATH_EP_MUL(x, mul) ((x) * (mul))
849#define ATH_EP_RND(x, mul) \
850 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
851#define ATH_RSSI_OUT(x) \
852 (((x) != ATH_RSSI_DUMMY_MARKER) ? \
853 (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
854#define ATH_RSSI_IN(x) \
855 (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
856#define ATH_LPF_RSSI(x, y, len) \
857 ((x != ATH_RSSI_DUMMY_MARKER) ? \
858 (((x) * ((len) - 1) + (y)) / (len)) : (y))
859#define ATH_RSSI_LPF(x, y) do { \
860 if ((y) >= RSSI_LPF_THRESHOLD) \
861 x = ATH_LPF_RSSI((x), \
862 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
863 } while (0)
864
865
866enum PROT_MODE {
867 PROT_M_NONE = 0,
868 PROT_M_RTSCTS,
869 PROT_M_CTSONLY
870};
871
872enum RATE_TYPE {
873 NORMAL_RATE = 0,
874 HALF_RATE,
875 QUARTER_RATE
876};
877
878struct ath_ht_info {
879 enum ath9k_ht_macmode tx_chan_width;
880 u16 maxampdu;
881 u8 mpdudensity;
882 u8 ext_chan_offset;
883};
884
672840ac
S		 885#define SC_OP_INVALID BIT(0)
886#define SC_OP_BEACONS BIT(1)
887#define SC_OP_RXAGGR BIT(2)
888#define SC_OP_TXAGGR BIT(3)
889#define SC_OP_CHAINMASK_UPDATE BIT(4)
890#define SC_OP_FULL_RESET BIT(5)
98deeea0
S		 891#define SC_OP_NO_RESET BIT(6)
892#define SC_OP_PREAMBLE_SHORT BIT(7)
893#define SC_OP_PROTECT_ENABLE BIT(8)
894#define SC_OP_RXFLUSH BIT(9)
672840ac 895
f078f209 896struct ath_softc {
ea9880fb
S		 897 struct ieee80211_hw *hw;
898 struct pci_dev *pdev;
ea9880fb
S		 899 struct tasklet_struct intr_tq;
900 struct tasklet_struct bcon_tasklet;
672840ac 901 struct ath_config sc_config;
ea9880fb 902 struct ath_hal *sc_ah;
672840ac 903 struct ath_rate_softc *sc_rc;
b4696c8b
S		 904 void __iomem *mem;
905
98deeea0
S		 906 u8 sc_curbssid[ETH_ALEN];
907 u8 sc_myaddr[ETH_ALEN];
908 u8 sc_bssidmask[ETH_ALEN];
909
b4696c8b 910 int sc_debug;
ea9880fb 911 u32 sc_intrstatus;
672840ac 912 u32 sc_flags; /* SC_OP_* */
7dcfdcd9 913 unsigned int rx_filter;
ea9880fb
S		 914 u16 sc_curtxpow;
915 u16 sc_curaid;
98deeea0
S		 916 u16 sc_cachelsz;
917 int sc_slotupdate; /* slot to next advance fsm */
918 int sc_slottime;
919 int sc_bslot[ATH_BCBUF];
920 u8 sc_tx_chainmask;
921 u8 sc_rx_chainmask;
922 enum ath9k_int sc_imask;
923 enum wireless_mode sc_curmode; /* current phy mode */
ea9880fb 924 enum PROT_MODE sc_protmode;
98deeea0 925
ea9880fb
S		 926 u8 sc_nbcnvaps; /* # of vaps sending beacons */
927 u16 sc_nvaps; /* # of active virtual ap's */
928 struct ath_vap *sc_vaps[ATH_BCBUF];
98deeea0
S		 929
930 u8 sc_mcastantenna;
ea9880fb
S		 931 u8 sc_defant; /* current default antenna */
932 u8 sc_rxotherant; /* rx's on non-default antenna */
98deeea0 933
ea9880fb
S		 934 struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
935 struct list_head node_list;
936 struct ath_ht_info sc_ht_info;
ea9880fb 937 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
98deeea0 938
f078f209 939#ifdef CONFIG_SLOW_ANT_DIV
ea9880fb 940 struct ath_antdiv sc_antdiv;
f078f209
LR		 941#endif
942 enum {
ea9880fb
S		 943 OK, /* no change needed */
944 UPDATE, /* update pending */
945 COMMIT /* beacon sent, commit change */
946 } sc_updateslot; /* slot time update fsm */
f078f209
LR		 947
948 /* Crypto */
ea9880fb
S		 949 u32 sc_keymax; /* size of key cache */
950 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */
951 u8 sc_splitmic; /* split TKIP MIC keys */
952 int sc_keytype;
f078f209
LR		 953
954 /* RX */
ea9880fb
S		 955 struct list_head sc_rxbuf;
956 struct ath_descdma sc_rxdma;
957 int sc_rxbufsize; /* rx size based on mtu */
958 u32 *sc_rxlink; /* link ptr in last RX desc */
ea9880fb 959 u64 sc_lastrx; /* tsf of last rx'd frame */
f078f209
LR		 960
961 /* TX */
ea9880fb
S		 962 struct list_head sc_txbuf;
963 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
964 struct ath_descdma sc_txdma;
965 u32 sc_txqsetup;
966 u32 sc_txintrperiod; /* tx interrupt batching */
967 int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */
f078f209
LR		 968
969 /* Beacon */
ea9880fb
S		 970 struct ath9k_tx_queue_info sc_beacon_qi;
971 struct ath_descdma sc_bdma;
972 struct ath_txq *sc_cabq;
973 struct list_head sc_bbuf;
974 u32 sc_bhalq;
975 u32 sc_bmisscount;
976 u32 ast_be_xmit; /* beacons transmitted */
f078f209
LR		 977
978 /* Rate */
ea9880fb 979 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
ea9880fb
S		 980 const struct ath9k_rate_table *sc_currates;
981 u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */
ea9880fb 982 u8 sc_protrix; /* protection rate index */
f078f209 983 struct {
ea9880fb
S		 984 u32 rateKbps; /* transfer rate in kbs */
985 u8 ieeerate; /* IEEE rate */
986 } sc_hwmap[256]; /* h/w rate ix mappings */
f078f209
LR		 987
988 /* Channel, Band */
989 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
990 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
f078f209
LR		 991
992 /* Locks */
ea9880fb
S		 993 spinlock_t sc_rxflushlock;
994 spinlock_t sc_rxbuflock;
995 spinlock_t sc_txbuflock;
996 spinlock_t sc_resetlock;
997 spinlock_t node_lock;
f078f209
LR		 998};
999
1000int ath_init(u16 devid, struct ath_softc *sc);
1001void ath_deinit(struct ath_softc *sc);
1002int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
1003int ath_suspend(struct ath_softc *sc);
1004irqreturn_t ath_isr(int irq, void *dev);
f45144ef 1005int ath_reset(struct ath_softc *sc, bool retry_tx);
f078f209 1006int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
f078f209
LR		 1007
1008/*********************/
1009/* Utility Functions */
1010/*********************/
1011
1012void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
1013int ath_keyset(struct ath_softc *sc,
1014 u16 keyix,
1015 struct ath9k_keyval *hk,
1016 const u8 mac[ETH_ALEN]);
1017int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
1018int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
1019void ath_setslottime(struct ath_softc *sc);
1020void ath_update_txpow(struct ath_softc *sc);
1021int ath_cabq_update(struct ath_softc *);
1022void ath_get_currentCountry(struct ath_softc *sc,
1023 struct ath9k_country_entry *ctry);
1024u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);
f078f209
LR		 1025dma_addr_t ath_skb_map_single(struct ath_softc *sc,
1026 struct sk_buff *skb,
1027 int direction,
1028 dma_addr_t *pa);
1029void ath_skb_unmap_single(struct ath_softc *sc,
1030 struct sk_buff *skb,
1031 int direction,
1032 dma_addr_t *pa);
f078f209
LR		 1033enum ath9k_ht_macmode ath_cwm_macmode(struct ath_softc *sc);
1034
1035#endif /* CORE_H */
Linux kernel - Deliverables
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