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ath9k: Use definition from ieee80211.h
[deliverable/linux.git] / drivers / net / wireless / ath9k / core.h
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef CORE_H
18#define CORE_H
19
20#include <linux/version.h>
21#include <linux/autoconf.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/spinlock.h>
25#include <linux/errno.h>
26#include <linux/skbuff.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/ip.h>
30#include <linux/tcp.h>
31#include <linux/in.h>
32#include <linux/delay.h>
33#include <linux/wait.h>
34#include <linux/pci.h>
35#include <linux/interrupt.h>
36#include <linux/sched.h>
37#include <linux/list.h>
38#include <asm/byteorder.h>
39#include <linux/scatterlist.h>
40#include <asm/page.h>
41#include <net/mac80211.h>
42
43#include "ath9k.h"
44#include "rc.h"
45
46struct ath_node;
47
48/******************/
49/* Utility macros */
50/******************/
51
52/* Macro to expand scalars to 64-bit objects */
53
f22f558d
S		 54#define ito64(x) (sizeof(x) == 8) ? \
55 (((unsigned long long int)(x)) & (0xff)) : \
56 (sizeof(x) == 16) ? \
57 (((unsigned long long int)(x)) & 0xffff) : \
58 ((sizeof(x) == 32) ? \
f078f209 59 (((unsigned long long int)(x)) & 0xffffffff) : \
f22f558d 60 (unsigned long long int)(x))
f078f209
LR		 61
62/* increment with wrap-around */
f22f558d
S		 63#define INCR(_l, _sz) do { \
64 (_l)++; \
65 (_l) &= ((_sz) - 1); \
f078f209
LR		 66 } while (0)
67
68/* decrement with wrap-around */
f22f558d
S		 69#define DECR(_l, _sz) do { \
70 (_l)--; \
71 (_l) &= ((_sz) - 1); \
f078f209
LR		 72 } while (0)
73
74#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
75
76#define ASSERT(exp) do { \
77 if (unlikely(!(exp))) { \
78 BUG(); \
79 } \
80 } while (0)
81
82/* XXX: remove */
83#define memzero(_buf, _len) memset(_buf, 0, _len)
84
f078f209
LR		 85#define ATH9K_BH_STATUS_INTACT 0
86#define ATH9K_BH_STATUS_CHANGE 1
87
88#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
89
90static inline unsigned long get_timestamp(void)
91{
92 return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
93}
94
7dcfdcd9
S		 95static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
96
f078f209
LR		 97/*************/
98/* Debugging */
99/*************/
100
101enum ATH_DEBUG {
102 ATH_DBG_RESET = 0x00000001,
103 ATH_DBG_PHY_IO = 0x00000002,
104 ATH_DBG_REG_IO = 0x00000004,
105 ATH_DBG_QUEUE = 0x00000008,
106 ATH_DBG_EEPROM = 0x00000010,
107 ATH_DBG_NF_CAL = 0x00000020,
108 ATH_DBG_CALIBRATE = 0x00000040,
109 ATH_DBG_CHANNEL = 0x00000080,
110 ATH_DBG_INTERRUPT = 0x00000100,
111 ATH_DBG_REGULATORY = 0x00000200,
112 ATH_DBG_ANI = 0x00000400,
113 ATH_DBG_POWER_MGMT = 0x00000800,
114 ATH_DBG_XMIT = 0x00001000,
115 ATH_DBG_BEACON = 0x00002000,
116 ATH_DBG_RATE = 0x00004000,
117 ATH_DBG_CONFIG = 0x00008000,
118 ATH_DBG_KEYCACHE = 0x00010000,
119 ATH_DBG_AGGR = 0x00020000,
120 ATH_DBG_FATAL = 0x00040000,
121 ATH_DBG_ANY = 0xffffffff
122};
123
124#define DBG_DEFAULT (ATH_DBG_FATAL)
125
126#define DPRINTF(sc, _m, _fmt, ...) do { \
127 if (sc->sc_debug & (_m)) \
128 printk(_fmt , ##__VA_ARGS__); \
129 } while (0)
130
131/***************************/
132/* Load-time Configuration */
133/***************************/
134
135/* Per-instance load-time (note: NOT run-time) configurations
136 * for Atheros Device */
137struct ath_config {
f22f558d
S		 138 u32 ath_aggr_prot;
139 u16 txpowlimit;
140 u16 txpowlimit_override;
141 u8 cabqReadytime; /* Cabq Readytime % */
142 u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */
f078f209
LR		 143};
144
145/***********************/
146/* Chainmask Selection */
147/***********************/
148
149#define ATH_CHAINMASK_SEL_TIMEOUT 6000
150/* Default - Number of last RSSI values that is used for
151 * chainmask selection */
152#define ATH_CHAINMASK_SEL_RSSI_CNT 10
153/* Means use 3x3 chainmask instead of configured chainmask */
154#define ATH_CHAINMASK_SEL_3X3 7
155/* Default - Rssi threshold below which we have to switch to 3x3 */
156#define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20
157/* Default - Rssi threshold above which we have to switch to
158 * user configured values */
159#define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35
160/* Struct to store the chainmask select related info */
161struct ath_chainmask_sel {
f22f558d
S		 162 struct timer_list timer;
163 int cur_tx_mask; /* user configured or 3x3 */
164 int cur_rx_mask; /* user configured or 3x3 */
165 int tx_avgrssi;
166 u8 switch_allowed:1, /* timer will set this */
167 cm_sel_enabled : 1;
f078f209
LR		 168};
169
170int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
171void ath_update_chainmask(struct ath_softc *sc, int is_ht);
172
173/*************************/
174/* Descriptor Management */
175/*************************/
176
f078f209
LR		 177#define ATH_TXBUF_RESET(_bf) do { \
178 (_bf)->bf_status = 0; \
179 (_bf)->bf_lastbf = NULL; \
180 (_bf)->bf_lastfrm = NULL; \
181 (_bf)->bf_next = NULL; \
182 memzero(&((_bf)->bf_state), \
183 sizeof(struct ath_buf_state)); \
184 } while (0)
185
cd3d39a6
S		 186enum buffer_type {
187 BUF_DATA = BIT(0),
188 BUF_AGGR = BIT(1),
189 BUF_AMPDU = BIT(2),
190 BUF_HT = BIT(3),
191 BUF_RETRY = BIT(4),
192 BUF_XRETRY = BIT(5),
193 BUF_SHORT_PREAMBLE = BIT(6),
194 BUF_BAR = BIT(7),
195 BUF_PSPOLL = BIT(8),
196 BUF_AGGR_BURST = BIT(9),
197 BUF_CALC_AIRTIME = BIT(10),
198};
199
f078f209 200struct ath_buf_state {
cd3d39a6
S		 201 int bfs_nframes; /* # frames in aggregate */
202 u16 bfs_al; /* length of aggregate */
203 u16 bfs_frmlen; /* length of frame */
204 int bfs_seqno; /* sequence number */
205 int bfs_tidno; /* tid of this frame */
206 int bfs_retries; /* current retries */
f078f209 207 struct ath_rc_series bfs_rcs[4]; /* rate series */
cd3d39a6 208 u32 bf_type; /* BUF_* (enum buffer_type) */
f078f209
LR		 209 /* key type use to encrypt this frame */
210 enum ath9k_key_type bfs_keytype;
211};
212
213#define bf_nframes bf_state.bfs_nframes
214#define bf_al bf_state.bfs_al
215#define bf_frmlen bf_state.bfs_frmlen
216#define bf_retries bf_state.bfs_retries
217#define bf_seqno bf_state.bfs_seqno
218#define bf_tidno bf_state.bfs_tidno
219#define bf_rcs bf_state.bfs_rcs
f078f209 220#define bf_keytype bf_state.bfs_keytype
cd3d39a6
S		 221#define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
222#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
223#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
224#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
225#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
226#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
227#define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
228#define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
229#define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
230#define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
f078f209
LR		 231
232/*
233 * Abstraction of a contiguous buffer to transmit/receive. There is only
234 * a single hw descriptor encapsulated here.
235 */
f078f209
LR		 236struct ath_buf {
237 struct list_head list;
238 struct list_head *last;
239 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
f22f558d 240 an aggregate) */
f078f209
LR		 241 struct ath_buf *bf_lastfrm; /* last buf of this frame */
242 struct ath_buf *bf_next; /* next subframe in the aggregate */
243 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */
244 void *bf_mpdu; /* enclosing frame structure */
245 void *bf_node; /* pointer to the node */
246 struct ath_desc *bf_desc; /* virtual addr of desc */
247 dma_addr_t bf_daddr; /* physical addr of desc */
248 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
249 u32 bf_status;
f22f558d 250 u16 bf_flags; /* tx descriptor flags */
f078f209
LR		 251 struct ath_buf_state bf_state; /* buffer state */
252 dma_addr_t bf_dmacontext;
253};
254
255/*
256 * reset the rx buffer.
257 * any new fields added to the athbuf and require
258 * reset need to be added to this macro.
259 * currently bf_status is the only one requires that
260 * requires reset.
261 */
262#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
263
264/* hw processing complete, desc processed by hal */
265#define ATH_BUFSTATUS_DONE 0x00000001
266/* hw processing complete, desc hold for hw */
267#define ATH_BUFSTATUS_STALE 0x00000002
268/* Rx-only: OS is done with this packet and it's ok to queued it to hw */
269#define ATH_BUFSTATUS_FREE 0x00000004
270
271/* DMA state for tx/rx descriptors */
272
273struct ath_descdma {
274 const char *dd_name;
275 struct ath_desc *dd_desc; /* descriptors */
276 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
277 u32 dd_desc_len; /* size of dd_desc */
278 struct ath_buf *dd_bufptr; /* associated buffers */
279 dma_addr_t dd_dmacontext;
280};
281
282/* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
283
284struct ath_rx_context {
285 struct ath_buf *ctx_rxbuf; /* associated ath_buf for rx */
286};
287#define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
288
289int ath_descdma_setup(struct ath_softc *sc,
290 struct ath_descdma *dd,
291 struct list_head *head,
292 const char *name,
293 int nbuf,
294 int ndesc);
295int ath_desc_alloc(struct ath_softc *sc);
296void ath_desc_free(struct ath_softc *sc);
297void ath_descdma_cleanup(struct ath_softc *sc,
298 struct ath_descdma *dd,
299 struct list_head *head);
300
301/******/
302/* RX */
303/******/
304
305#define ATH_MAX_ANTENNA 3
306#define ATH_RXBUF 512
307#define ATH_RX_TIMEOUT 40 /* 40 milliseconds */
308#define WME_NUM_TID 16
309#define IEEE80211_BAR_CTL_TID_M 0xF000 /* tid mask */
310#define IEEE80211_BAR_CTL_TID_S 2 /* tid shift */
311
312enum ATH_RX_TYPE {
313 ATH_RX_NON_CONSUMED = 0,
314 ATH_RX_CONSUMED
315};
316
317/* per frame rx status block */
318struct ath_recv_status {
319 u64 tsf; /* mac tsf */
320 int8_t rssi; /* RSSI (noise floor ajusted) */
321 int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
322 int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
323 int8_t abs_rssi; /* absolute RSSI */
f22f558d
S		 324 u8 rateieee; /* data rate received (IEEE rate code) */
325 u8 ratecode; /* phy rate code */
f078f209
LR		 326 int rateKbps; /* data rate received (Kbps) */
327 int antenna; /* rx antenna */
328 int flags; /* status of associated skb */
329#define ATH_RX_FCS_ERROR 0x01
330#define ATH_RX_MIC_ERROR 0x02
331#define ATH_RX_DECRYPT_ERROR 0x04
332#define ATH_RX_RSSI_VALID 0x08
333/* if any of ctl,extn chainrssis are valid */
334#define ATH_RX_CHAIN_RSSI_VALID 0x10
335/* if extn chain rssis are valid */
336#define ATH_RX_RSSI_EXTN_VALID 0x20
337/* set if 40Mhz, clear if 20Mhz */
338#define ATH_RX_40MHZ 0x40
339/* set if short GI, clear if full GI */
340#define ATH_RX_SHORT_GI 0x80
341};
342
343struct ath_rxbuf {
f22f558d
S		 344 struct sk_buff *rx_wbuf;
345 unsigned long rx_time; /* system time when received */
346 struct ath_recv_status rx_status; /* cached rx status */
f078f209
LR		 347};
348
349/* Per-TID aggregate receiver state for a node */
350struct ath_arx_tid {
f22f558d
S		 351 struct ath_node *an;
352 struct ath_rxbuf *rxbuf; /* re-ordering buffer */
353 struct timer_list timer;
354 spinlock_t tidlock;
355 int baw_head; /* seq_next at head */
356 int baw_tail; /* tail of block-ack window */
357 int seq_reset; /* need to reset start sequence */
358 int addba_exchangecomplete;
359 u16 seq_next; /* next expected sequence */
360 u16 baw_size; /* block-ack window size */
f078f209
LR		 361};
362
363/* Per-node receiver aggregate state */
364struct ath_arx {
f22f558d 365 struct ath_arx_tid tid[WME_NUM_TID];
f078f209
LR		 366};
367
368int ath_startrecv(struct ath_softc *sc);
369bool ath_stoprecv(struct ath_softc *sc);
370void ath_flushrecv(struct ath_softc *sc);
371u32 ath_calcrxfilter(struct ath_softc *sc);
372void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
373void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an);
374void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
375void ath_handle_rx_intr(struct ath_softc *sc);
376int ath_rx_init(struct ath_softc *sc, int nbufs);
377void ath_rx_cleanup(struct ath_softc *sc);
378int ath_rx_tasklet(struct ath_softc *sc, int flush);
379int ath_rx_input(struct ath_softc *sc,
380 struct ath_node *node,
381 int is_ampdu,
382 struct sk_buff *skb,
383 struct ath_recv_status *rx_status,
384 enum ATH_RX_TYPE *status);
385int ath__rx_indicate(struct ath_softc *sc,
386 struct sk_buff *skb,
387 struct ath_recv_status *status,
388 u16 keyix);
389int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
390 struct ath_recv_status *status);
391
392/******/
393/* TX */
394/******/
395
556bb8f1 396#define ATH_TXBUF 512
f078f209
LR		 397/* max number of transmit attempts (tries) */
398#define ATH_TXMAXTRY 13
399/* max number of 11n transmit attempts (tries) */
400#define ATH_11N_TXMAXTRY 10
401/* max number of tries for management and control frames */
402#define ATH_MGT_TXMAXTRY 4
403#define WME_BA_BMP_SIZE 64
404#define WME_MAX_BA WME_BA_BMP_SIZE
405#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
406#define TID_TO_WME_AC(_tid) \
407 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
408 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
409 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
410 WME_AC_VO)
411
412
413/* Wireless Multimedia Extension Defines */
414#define WME_AC_BE 0 /* best effort */
415#define WME_AC_BK 1 /* background */
416#define WME_AC_VI 2 /* video */
417#define WME_AC_VO 3 /* voice */
418#define WME_NUM_AC 4
419
420enum ATH_SM_PWRSAV{
421 ATH_SM_ENABLE,
422 ATH_SM_PWRSAV_STATIC,
423 ATH_SM_PWRSAV_DYNAMIC,
424};
425
426/*
427 * Data transmit queue state. One of these exists for each
428 * hardware transmit queue. Packets sent to us from above
429 * are assigned to queues based on their priority. Not all
430 * devices support a complete set of hardware transmit queues.
431 * For those devices the array sc_ac2q will map multiple
432 * priorities to fewer hardware queues (typically all to one
433 * hardware queue).
434 */
435struct ath_txq {
f22f558d
S		 436 u32 axq_qnum; /* hardware q number */
437 u32 *axq_link; /* link ptr in last TX desc */
438 struct list_head axq_q; /* transmit queue */
439 spinlock_t axq_lock;
440 unsigned long axq_lockflags; /* intr state when must cli */
441 u32 axq_depth; /* queue depth */
442 u8 axq_aggr_depth; /* aggregates queued */
443 u32 axq_totalqueued; /* total ever queued */
444
445 /* count to determine if descriptor should generate int on this txq. */
446 u32 axq_intrcnt;
447
448 bool stopped; /* Is mac80211 queue stopped ? */
449 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
450
451 /* first desc of the last descriptor that contains CTS */
452 struct ath_desc *axq_lastdsWithCTS;
453
454 /* final desc of the gating desc that determines whether
455 lastdsWithCTS has been DMA'ed or not */
456 struct ath_desc *axq_gatingds;
457
458 struct list_head axq_acq;
f078f209
LR		 459};
460
461/* per TID aggregate tx state for a destination */
462struct ath_atx_tid {
f22f558d
S		 463 struct list_head list; /* round-robin tid entry */
464 struct list_head buf_q; /* pending buffers */
465 struct ath_node *an;
466 struct ath_atx_ac *ac;
467 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
468 u16 seq_start;
469 u16 seq_next;
470 u16 baw_size;
471 int tidno;
472 int baw_head; /* first un-acked tx buffer */
473 int baw_tail; /* next unused tx buffer slot */
474 int sched;
475 int paused;
476 int cleanup_inprogress;
477 u32 addba_exchangecomplete:1;
478 int32_t addba_exchangeinprogress;
479 int addba_exchangeattempts;
f078f209
LR		 480};
481
482/* per access-category aggregate tx state for a destination */
483struct ath_atx_ac {
f22f558d
S		 484 int sched; /* dest-ac is scheduled */
485 int qnum; /* H/W queue number associated
486 with this AC */
487 struct list_head list; /* round-robin txq entry */
488 struct list_head tid_q; /* queue of TIDs with buffers */
f078f209
LR		 489};
490
491/* per dest tx state */
492struct ath_atx {
f22f558d
S		 493 struct ath_atx_tid tid[WME_NUM_TID];
494 struct ath_atx_ac ac[WME_NUM_AC];
f078f209
LR		 495};
496
497/* per-frame tx control block */
498struct ath_tx_control {
f22f558d
S		 499 struct ath_node *an;
500 int if_id;
501 int qnum;
502 u32 ht:1;
503 u32 ps:1;
504 u32 use_minrate:1;
505 enum ath9k_pkt_type atype;
506 enum ath9k_key_type keytype;
507 u32 flags;
508 u16 seqno;
509 u16 tidno;
510 u16 txpower;
511 u16 frmlen;
512 u32 keyix;
513 int min_rate;
514 int mcast_rate;
515 u16 nextfraglen;
516 struct ath_softc *dev;
f078f209
LR		 517 dma_addr_t dmacontext;
518};
519
520/* per frame tx status block */
521struct ath_xmit_status {
f22f558d
S		 522 int retries; /* number of retries to successufully
523 transmit this frame */
524 int flags; /* status of transmit */
f078f209
LR		 525#define ATH_TX_ERROR 0x01
526#define ATH_TX_XRETRY 0x02
527#define ATH_TX_BAR 0x04
528};
529
530struct ath_tx_stat {
531 int rssi; /* RSSI (noise floor ajusted) */
532 int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
533 int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
534 int rateieee; /* data rate xmitted (IEEE rate code) */
535 int rateKbps; /* data rate xmitted (Kbps) */
536 int ratecode; /* phy rate code */
537 int flags; /* validity flags */
538/* if any of ctl,extn chain rssis are valid */
539#define ATH_TX_CHAIN_RSSI_VALID 0x01
540/* if extn chain rssis are valid */
541#define ATH_TX_RSSI_EXTN_VALID 0x02
542 u32 airtime; /* time on air per final tx rate */
543};
544
545struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
546void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
547int ath_tx_setup(struct ath_softc *sc, int haltype);
548void ath_draintxq(struct ath_softc *sc, bool retry_tx);
549void ath_tx_draintxq(struct ath_softc *sc,
556bb8f1 550 struct ath_txq *txq, bool retry_tx);
f078f209
LR		 551void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
552void ath_tx_node_cleanup(struct ath_softc *sc,
556bb8f1 553 struct ath_node *an, bool bh_flag);
f078f209
LR		 554void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
555void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
556int ath_tx_init(struct ath_softc *sc, int nbufs);
557int ath_tx_cleanup(struct ath_softc *sc);
558int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
ea9880fb
S		 559int ath_txq_update(struct ath_softc *sc, int qnum,
560 struct ath9k_tx_queue_info *q);
f078f209
LR		 561int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb);
562void ath_tx_tasklet(struct ath_softc *sc);
563u32 ath_txq_depth(struct ath_softc *sc, int qnum);
564u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
565void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
566void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
567 struct ath_xmit_status *tx_status, struct ath_node *an);
568
569/**********************/
570/* Node / Aggregation */
571/**********************/
572
573/* indicates the node is clened up */
574#define ATH_NODE_CLEAN 0x1
575/* indicates the node is 80211 power save */
576#define ATH_NODE_PWRSAVE 0x2
577
f078f209
LR		 578#define ADDBA_EXCHANGE_ATTEMPTS 10
579#define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
580#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
581/* number of delimiters for encryption padding */
582#define ATH_AGGR_ENCRYPTDELIM 10
583/* minimum h/w qdepth to be sustained to maximize aggregation */
584#define ATH_AGGR_MIN_QDEPTH 2
585#define ATH_AMPDU_SUBFRAME_DEFAULT 32
586#define IEEE80211_SEQ_SEQ_SHIFT 4
587#define IEEE80211_SEQ_MAX 4096
588#define IEEE80211_MIN_AMPDU_BUF 0x8
589
590/* return whether a bit at index _n in bitmap _bm is set
591 * _sz is the size of the bitmap */
592#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
593 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
594
595/* return block-ack bitmap index given sequence and starting sequence */
596#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
597
598/* returns delimiter padding required given the packet length */
599#define ATH_AGGR_GET_NDELIM(_len) \
600 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
601 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
602
603#define BAW_WITHIN(_start, _bawsz, _seqno) \
604 ((((_seqno) - (_start)) & 4095) < (_bawsz))
605
606#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
607#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
608#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
609#define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
610
611enum ATH_AGGR_STATUS {
612 ATH_AGGR_DONE,
613 ATH_AGGR_BAW_CLOSED,
614 ATH_AGGR_LIMITED,
615 ATH_AGGR_SHORTPKT,
616 ATH_AGGR_8K_LIMITED,
617};
618
619enum ATH_AGGR_CHECK {
620 AGGR_NOT_REQUIRED,
621 AGGR_REQUIRED,
622 AGGR_CLEANUP_PROGRESS,
623 AGGR_EXCHANGE_PROGRESS,
624 AGGR_EXCHANGE_DONE
625};
626
627struct aggr_rifs_param {
628 int param_max_frames;
629 int param_max_len;
630 int param_rl;
631 int param_al;
632 struct ath_rc_series *param_rcs;
633};
634
635/* Per-node aggregation state */
636struct ath_node_aggr {
f22f558d
S		 637 struct ath_atx tx; /* node transmit state */
638 struct ath_arx rx; /* node receive state */
f078f209
LR		 639};
640
641/* driver-specific node state */
642struct ath_node {
f22f558d
S		 643 struct list_head list;
644 struct ath_softc *an_sc;
645 atomic_t an_refcnt;
f078f209 646 struct ath_chainmask_sel an_chainmask_sel;
f22f558d
S		 647 struct ath_node_aggr an_aggr;
648 u8 an_smmode; /* SM Power save mode */
649 u8 an_flags;
650 u8 an_addr[ETH_ALEN];
f078f209
LR		 651};
652
653void ath_tx_resume_tid(struct ath_softc *sc,
654 struct ath_atx_tid *tid);
655enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
656 struct ath_node *an, u8 tidno);
657void ath_tx_aggr_teardown(struct ath_softc *sc,
658 struct ath_node *an, u8 tidno);
659void ath_rx_aggr_teardown(struct ath_softc *sc,
660 struct ath_node *an, u8 tidno);
661int ath_rx_aggr_start(struct ath_softc *sc,
662 const u8 *addr,
663 u16 tid,
664 u16 *ssn);
665int ath_rx_aggr_stop(struct ath_softc *sc,
666 const u8 *addr,
667 u16 tid);
668int ath_tx_aggr_start(struct ath_softc *sc,
669 const u8 *addr,
670 u16 tid,
671 u16 *ssn);
672int ath_tx_aggr_stop(struct ath_softc *sc,
673 const u8 *addr,
674 u16 tid);
675void ath_newassoc(struct ath_softc *sc,
676 struct ath_node *node, int isnew, int isuapsd);
677struct ath_node *ath_node_attach(struct ath_softc *sc,
678 u8 addr[ETH_ALEN], int if_id);
679void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
680struct ath_node *ath_node_get(struct ath_softc *sc, u8 addr[ETH_ALEN]);
681void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag);
682struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr);
683
684/*******************/
685/* Beacon Handling */
686/*******************/
687
688/*
689 * Regardless of the number of beacons we stagger, (i.e. regardless of the
690 * number of BSSIDs) if a given beacon does not go out even after waiting this
691 * number of beacon intervals, the game's up.
692 */
693#define BSTUCK_THRESH (9 * ATH_BCBUF)
694#define ATH_BCBUF 4 /* number of beacon buffers */
695#define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
696#define ATH_DEFAULT_BMISS_LIMIT 10
f078f209
LR		 697#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
698
699/* beacon configuration */
700struct ath_beacon_config {
701 u16 beacon_interval;
702 u16 listen_interval;
703 u16 dtim_period;
704 u16 bmiss_timeout;
705 u8 dtim_count;
706 u8 tim_offset;
707 union {
708 u64 last_tsf;
709 u8 last_tstamp[8];
710 } u; /* last received beacon/probe response timestamp of this BSS. */
711};
712
713/* offsets in a beacon frame for
714 * quick acess of beacon content by low-level driver */
715struct ath_beacon_offset {
716 u8 *bo_tim; /* start of atim/dtim */
717};
718
719void ath9k_beacon_tasklet(unsigned long data);
720void ath_beacon_config(struct ath_softc *sc, int if_id);
721int ath_beaconq_setup(struct ath_hal *ah);
722int ath_beacon_alloc(struct ath_softc *sc, int if_id);
723void ath_bstuck_process(struct ath_softc *sc);
f078f209
LR		 724void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
725void ath_beacon_sync(struct ath_softc *sc, int if_id);
f078f209
LR		 726void ath_get_beaconconfig(struct ath_softc *sc,
727 int if_id,
728 struct ath_beacon_config *conf);
f078f209
LR		 729/********/
730/* VAPs */
731/********/
732
f078f209
LR		 733/*
734 * Define the scheme that we select MAC address for multiple
735 * BSS on the same radio. The very first VAP will just use the MAC
736 * address from the EEPROM. For the next 3 VAPs, we set the
737 * U/L bit (bit 1) in MAC address, and use the next two bits as the
738 * index of the VAP.
739 */
740
741#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
742 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
743
744/* VAP configuration (from protocol layer) */
745struct ath_vap_config {
746 u32 av_fixed_rateset;
747 u32 av_fixed_retryset;
748};
749
750/* driver-specific vap state */
751struct ath_vap {
f22f558d
S		 752 struct ieee80211_vif *av_if_data;
753 enum ath9k_opmode av_opmode; /* VAP operational mode */
754 struct ath_buf *av_bcbuf; /* beacon buffer */
755 struct ath_beacon_offset av_boff; /* dynamic update state */
756 struct ath_tx_control av_btxctl; /* txctl information for beacon */
757 int av_bslot; /* beacon slot index */
758 struct ath_txq av_mcastq; /* multicast transmit queue */
759 struct ath_vap_config av_config;/* vap configuration parameters*/
760 struct ath_rate_node *rc_node;
f078f209
LR		 761};
762
763int ath_vap_attach(struct ath_softc *sc,
764 int if_id,
765 struct ieee80211_vif *if_data,
766 enum ath9k_opmode opmode);
767int ath_vap_detach(struct ath_softc *sc, int if_id);
768int ath_vap_config(struct ath_softc *sc,
ff9b662d 769 int if_id, struct ath_vap_config *if_config);
f078f209
LR		 770
771/*********************/
772/* Antenna diversity */
773/*********************/
774
775#define ATH_ANT_DIV_MAX_CFG 2
776#define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */
777#define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */
778
779enum ATH_ANT_DIV_STATE{
780 ATH_ANT_DIV_IDLE,
781 ATH_ANT_DIV_SCAN, /* evaluating antenna */
782};
783
784struct ath_antdiv {
785 struct ath_softc *antdiv_sc;
786 u8 antdiv_start;
787 enum ATH_ANT_DIV_STATE antdiv_state;
788 u8 antdiv_num_antcfg;
789 u8 antdiv_curcfg;
790 u8 antdiv_bestcfg;
791 int32_t antdivf_rssitrig;
792 int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
793 u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
794 u64 antdiv_laststatetsf;
795 u8 antdiv_bssid[ETH_ALEN];
796};
797
798void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
799 struct ath_softc *sc, int32_t rssitrig);
800void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
801 u8 num_antcfg,
802 const u8 *bssid);
803void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
804void ath_slow_ant_div(struct ath_antdiv *antdiv,
805 struct ieee80211_hdr *wh,
806 struct ath_rx_status *rx_stats);
807void ath_setdefantenna(void *sc, u32 antenna);
808
809/********************/
810/* Main driver core */
811/********************/
812
813/*
814 * Default cache line size, in bytes.
815 * Used when PCI device not fully initialized by bootrom/BIOS
816*/
817#define DEFAULT_CACHELINE 32
818#define ATH_DEFAULT_NOISE_FLOOR -95
819#define ATH_REGCLASSIDS_MAX 10
820#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
f078f209 821#define ATH_MAX_SW_RETRIES 10
f078f209
LR		 822#define ATH_CHAN_MAX 255
823#define IEEE80211_WEP_NKID 4 /* number of key ids */
824#define IEEE80211_RATE_VAL 0x7f
825/*
826 * The key cache is used for h/w cipher state and also for
827 * tracking station state such as the current tx antenna.
828 * We also setup a mapping table between key cache slot indices
829 * and station state to short-circuit node lookups on rx.
830 * Different parts have different size key caches. We handle
831 * up to ATH_KEYMAX entries (could dynamically allocate state).
832 */
833#define ATH_KEYMAX 128 /* max key cache size we handle */
834
f078f209 835#define ATH_IF_ID_ANY 0xff
f078f209
LR		 836#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
837
838#define RSSI_LPF_THRESHOLD -20
839#define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
840#define ATH_RATE_DUMMY_MARKER 0
841#define ATH_RSSI_LPF_LEN 10
842#define ATH_RSSI_DUMMY_MARKER 0x127
843
844#define ATH_EP_MUL(x, mul) ((x) * (mul))
845#define ATH_EP_RND(x, mul) \
846 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
847#define ATH_RSSI_OUT(x) \
848 (((x) != ATH_RSSI_DUMMY_MARKER) ? \
849 (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
850#define ATH_RSSI_IN(x) \
851 (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
852#define ATH_LPF_RSSI(x, y, len) \
853 ((x != ATH_RSSI_DUMMY_MARKER) ? \
854 (((x) * ((len) - 1) + (y)) / (len)) : (y))
855#define ATH_RSSI_LPF(x, y) do { \
856 if ((y) >= RSSI_LPF_THRESHOLD) \
857 x = ATH_LPF_RSSI((x), \
858 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
859 } while (0)
860
861
862enum PROT_MODE {
863 PROT_M_NONE = 0,
864 PROT_M_RTSCTS,
865 PROT_M_CTSONLY
866};
867
868enum RATE_TYPE {
869 NORMAL_RATE = 0,
870 HALF_RATE,
871 QUARTER_RATE
872};
873
874struct ath_ht_info {
875 enum ath9k_ht_macmode tx_chan_width;
876 u16 maxampdu;
877 u8 mpdudensity;
878 u8 ext_chan_offset;
879};
880
672840ac
S		 881#define SC_OP_INVALID BIT(0)
882#define SC_OP_BEACONS BIT(1)
883#define SC_OP_RXAGGR BIT(2)
884#define SC_OP_TXAGGR BIT(3)
885#define SC_OP_CHAINMASK_UPDATE BIT(4)
886#define SC_OP_FULL_RESET BIT(5)
98deeea0
S		 887#define SC_OP_NO_RESET BIT(6)
888#define SC_OP_PREAMBLE_SHORT BIT(7)
889#define SC_OP_PROTECT_ENABLE BIT(8)
890#define SC_OP_RXFLUSH BIT(9)
672840ac 891
f078f209 892struct ath_softc {
ea9880fb
S		 893 struct ieee80211_hw *hw;
894 struct pci_dev *pdev;
ea9880fb
S		 895 struct tasklet_struct intr_tq;
896 struct tasklet_struct bcon_tasklet;
672840ac 897 struct ath_config sc_config;
ea9880fb 898 struct ath_hal *sc_ah;
672840ac 899 struct ath_rate_softc *sc_rc;
b4696c8b
S		 900 void __iomem *mem;
901
98deeea0
S		 902 u8 sc_curbssid[ETH_ALEN];
903 u8 sc_myaddr[ETH_ALEN];
904 u8 sc_bssidmask[ETH_ALEN];
905
b4696c8b 906 int sc_debug;
ea9880fb 907 u32 sc_intrstatus;
672840ac 908 u32 sc_flags; /* SC_OP_* */
7dcfdcd9 909 unsigned int rx_filter;
ea9880fb
S		 910 u16 sc_curtxpow;
911 u16 sc_curaid;
98deeea0
S		 912 u16 sc_cachelsz;
913 int sc_slotupdate; /* slot to next advance fsm */
914 int sc_slottime;
915 int sc_bslot[ATH_BCBUF];
916 u8 sc_tx_chainmask;
917 u8 sc_rx_chainmask;
918 enum ath9k_int sc_imask;
919 enum wireless_mode sc_curmode; /* current phy mode */
ea9880fb 920 enum PROT_MODE sc_protmode;
98deeea0 921
ea9880fb
S		 922 u8 sc_nbcnvaps; /* # of vaps sending beacons */
923 u16 sc_nvaps; /* # of active virtual ap's */
924 struct ath_vap *sc_vaps[ATH_BCBUF];
98deeea0
S		 925
926 u8 sc_mcastantenna;
ea9880fb
S		 927 u8 sc_defant; /* current default antenna */
928 u8 sc_rxotherant; /* rx's on non-default antenna */
98deeea0 929
ea9880fb
S		 930 struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
931 struct list_head node_list;
932 struct ath_ht_info sc_ht_info;
ea9880fb 933 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
98deeea0 934
f078f209 935#ifdef CONFIG_SLOW_ANT_DIV
ea9880fb 936 struct ath_antdiv sc_antdiv;
f078f209
LR		 937#endif
938 enum {
ea9880fb
S		 939 OK, /* no change needed */
940 UPDATE, /* update pending */
941 COMMIT /* beacon sent, commit change */
942 } sc_updateslot; /* slot time update fsm */
f078f209
LR		 943
944 /* Crypto */
ea9880fb
S		 945 u32 sc_keymax; /* size of key cache */
946 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */
947 u8 sc_splitmic; /* split TKIP MIC keys */
948 int sc_keytype;
f078f209
LR		 949
950 /* RX */
ea9880fb
S		 951 struct list_head sc_rxbuf;
952 struct ath_descdma sc_rxdma;
953 int sc_rxbufsize; /* rx size based on mtu */
954 u32 *sc_rxlink; /* link ptr in last RX desc */
ea9880fb 955 u64 sc_lastrx; /* tsf of last rx'd frame */
f078f209
LR		 956
957 /* TX */
ea9880fb
S		 958 struct list_head sc_txbuf;
959 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
960 struct ath_descdma sc_txdma;
961 u32 sc_txqsetup;
962 u32 sc_txintrperiod; /* tx interrupt batching */
963 int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */
147583c0 964 u16 seq_no; /* TX sequence number */
f078f209
LR		 965
966 /* Beacon */
ea9880fb
S		 967 struct ath9k_tx_queue_info sc_beacon_qi;
968 struct ath_descdma sc_bdma;
969 struct ath_txq *sc_cabq;
970 struct list_head sc_bbuf;
971 u32 sc_bhalq;
972 u32 sc_bmisscount;
973 u32 ast_be_xmit; /* beacons transmitted */
f078f209
LR		 974
975 /* Rate */
ea9880fb 976 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
ea9880fb
S		 977 const struct ath9k_rate_table *sc_currates;
978 u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */
ea9880fb 979 u8 sc_protrix; /* protection rate index */
f078f209 980 struct {
ea9880fb
S		 981 u32 rateKbps; /* transfer rate in kbs */
982 u8 ieeerate; /* IEEE rate */
983 } sc_hwmap[256]; /* h/w rate ix mappings */
f078f209
LR		 984
985 /* Channel, Band */
986 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
987 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
f078f209
LR		 988
989 /* Locks */
ea9880fb
S		 990 spinlock_t sc_rxflushlock;
991 spinlock_t sc_rxbuflock;
992 spinlock_t sc_txbuflock;
993 spinlock_t sc_resetlock;
994 spinlock_t node_lock;
f078f209
LR		 995};
996
997int ath_init(u16 devid, struct ath_softc *sc);
998void ath_deinit(struct ath_softc *sc);
999int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
1000int ath_suspend(struct ath_softc *sc);
1001irqreturn_t ath_isr(int irq, void *dev);
f45144ef 1002int ath_reset(struct ath_softc *sc, bool retry_tx);
f078f209 1003int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
f078f209
LR		 1004
1005/*********************/
1006/* Utility Functions */
1007/*********************/
1008
1009void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
1010int ath_keyset(struct ath_softc *sc,
1011 u16 keyix,
1012 struct ath9k_keyval *hk,
1013 const u8 mac[ETH_ALEN]);
1014int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
1015int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
1016void ath_setslottime(struct ath_softc *sc);
1017void ath_update_txpow(struct ath_softc *sc);
1018int ath_cabq_update(struct ath_softc *);
1019void ath_get_currentCountry(struct ath_softc *sc,
1020 struct ath9k_country_entry *ctry);
1021u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);
f078f209
LR		 1022
1023#endif /* CORE_H */
Linux kernel - Deliverables
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