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ath9k: Simplify node attach/detach routines
[deliverable/linux.git] / drivers / net / wireless / ath9k / core.h
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef CORE_H
18#define CORE_H
19
20#include <linux/version.h>
21#include <linux/autoconf.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/spinlock.h>
25#include <linux/errno.h>
26#include <linux/skbuff.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/ip.h>
30#include <linux/tcp.h>
31#include <linux/in.h>
32#include <linux/delay.h>
33#include <linux/wait.h>
34#include <linux/pci.h>
35#include <linux/interrupt.h>
36#include <linux/sched.h>
37#include <linux/list.h>
38#include <asm/byteorder.h>
39#include <linux/scatterlist.h>
40#include <asm/page.h>
41#include <net/mac80211.h>
c83be688 42#include <linux/leds.h>
500c064d 43#include <linux/rfkill.h>
f078f209
LR		 44
45#include "ath9k.h"
46#include "rc.h"
47
48struct ath_node;
49
50/******************/
51/* Utility macros */
52/******************/
53
54/* Macro to expand scalars to 64-bit objects */
55
f22f558d
S		 56#define ito64(x) (sizeof(x) == 8) ? \
57 (((unsigned long long int)(x)) & (0xff)) : \
58 (sizeof(x) == 16) ? \
59 (((unsigned long long int)(x)) & 0xffff) : \
60 ((sizeof(x) == 32) ? \
f078f209 61 (((unsigned long long int)(x)) & 0xffffffff) : \
f22f558d 62 (unsigned long long int)(x))
f078f209
LR		 63
64/* increment with wrap-around */
f22f558d
S		 65#define INCR(_l, _sz) do { \
66 (_l)++; \
67 (_l) &= ((_sz) - 1); \
f078f209
LR		 68 } while (0)
69
70/* decrement with wrap-around */
f22f558d
S		 71#define DECR(_l, _sz) do { \
72 (_l)--; \
73 (_l) &= ((_sz) - 1); \
f078f209
LR		 74 } while (0)
75
76#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
77
78#define ASSERT(exp) do { \
79 if (unlikely(!(exp))) { \
80 BUG(); \
81 } \
82 } while (0)
83
19b73c7f
S		 84#define TSF_TO_TU(_h,_l) \
85 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
86
f078f209
LR		 87#define ATH9K_BH_STATUS_INTACT 0
88#define ATH9K_BH_STATUS_CHANGE 1
89
90#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
91
92static inline unsigned long get_timestamp(void)
93{
94 return ((jiffies / HZ) * 1000) + (jiffies % HZ) * (1000 / HZ);
95}
96
7dcfdcd9
S		 97static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
98
f078f209
LR		 99/*************/
100/* Debugging */
101/*************/
102
103enum ATH_DEBUG {
104 ATH_DBG_RESET = 0x00000001,
105 ATH_DBG_PHY_IO = 0x00000002,
106 ATH_DBG_REG_IO = 0x00000004,
107 ATH_DBG_QUEUE = 0x00000008,
108 ATH_DBG_EEPROM = 0x00000010,
109 ATH_DBG_NF_CAL = 0x00000020,
110 ATH_DBG_CALIBRATE = 0x00000040,
111 ATH_DBG_CHANNEL = 0x00000080,
112 ATH_DBG_INTERRUPT = 0x00000100,
113 ATH_DBG_REGULATORY = 0x00000200,
114 ATH_DBG_ANI = 0x00000400,
115 ATH_DBG_POWER_MGMT = 0x00000800,
116 ATH_DBG_XMIT = 0x00001000,
117 ATH_DBG_BEACON = 0x00002000,
118 ATH_DBG_RATE = 0x00004000,
119 ATH_DBG_CONFIG = 0x00008000,
120 ATH_DBG_KEYCACHE = 0x00010000,
121 ATH_DBG_AGGR = 0x00020000,
122 ATH_DBG_FATAL = 0x00040000,
123 ATH_DBG_ANY = 0xffffffff
124};
125
126#define DBG_DEFAULT (ATH_DBG_FATAL)
127
128#define DPRINTF(sc, _m, _fmt, ...) do { \
129 if (sc->sc_debug & (_m)) \
130 printk(_fmt , ##__VA_ARGS__); \
131 } while (0)
132
133/***************************/
134/* Load-time Configuration */
135/***************************/
136
137/* Per-instance load-time (note: NOT run-time) configurations
138 * for Atheros Device */
139struct ath_config {
f22f558d
S		 140 u32 ath_aggr_prot;
141 u16 txpowlimit;
142 u16 txpowlimit_override;
143 u8 cabqReadytime; /* Cabq Readytime % */
144 u8 swBeaconProcess; /* Process received beacons in SW (vs HW) */
f078f209
LR		 145};
146
147/***********************/
148/* Chainmask Selection */
149/***********************/
150
151#define ATH_CHAINMASK_SEL_TIMEOUT 6000
152/* Default - Number of last RSSI values that is used for
153 * chainmask selection */
154#define ATH_CHAINMASK_SEL_RSSI_CNT 10
155/* Means use 3x3 chainmask instead of configured chainmask */
156#define ATH_CHAINMASK_SEL_3X3 7
157/* Default - Rssi threshold below which we have to switch to 3x3 */
158#define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20
159/* Default - Rssi threshold above which we have to switch to
160 * user configured values */
161#define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35
162/* Struct to store the chainmask select related info */
163struct ath_chainmask_sel {
f22f558d
S		 164 struct timer_list timer;
165 int cur_tx_mask; /* user configured or 3x3 */
166 int cur_rx_mask; /* user configured or 3x3 */
167 int tx_avgrssi;
168 u8 switch_allowed:1, /* timer will set this */
169 cm_sel_enabled : 1;
f078f209
LR		 170};
171
172int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an);
173void ath_update_chainmask(struct ath_softc *sc, int is_ht);
174
175/*************************/
176/* Descriptor Management */
177/*************************/
178
f078f209
LR		 179#define ATH_TXBUF_RESET(_bf) do { \
180 (_bf)->bf_status = 0; \
181 (_bf)->bf_lastbf = NULL; \
182 (_bf)->bf_lastfrm = NULL; \
183 (_bf)->bf_next = NULL; \
0345f37b 184 memset(&((_bf)->bf_state), 0, \
f078f209
LR		 185 sizeof(struct ath_buf_state)); \
186 } while (0)
187
cd3d39a6
S		 188enum buffer_type {
189 BUF_DATA = BIT(0),
190 BUF_AGGR = BIT(1),
191 BUF_AMPDU = BIT(2),
192 BUF_HT = BIT(3),
193 BUF_RETRY = BIT(4),
194 BUF_XRETRY = BIT(5),
195 BUF_SHORT_PREAMBLE = BIT(6),
196 BUF_BAR = BIT(7),
197 BUF_PSPOLL = BIT(8),
198 BUF_AGGR_BURST = BIT(9),
199 BUF_CALC_AIRTIME = BIT(10),
200};
201
f078f209 202struct ath_buf_state {
cd3d39a6
S		 203 int bfs_nframes; /* # frames in aggregate */
204 u16 bfs_al; /* length of aggregate */
205 u16 bfs_frmlen; /* length of frame */
206 int bfs_seqno; /* sequence number */
207 int bfs_tidno; /* tid of this frame */
208 int bfs_retries; /* current retries */
f078f209 209 struct ath_rc_series bfs_rcs[4]; /* rate series */
cd3d39a6 210 u32 bf_type; /* BUF_* (enum buffer_type) */
f078f209
LR		 211 /* key type use to encrypt this frame */
212 enum ath9k_key_type bfs_keytype;
213};
214
215#define bf_nframes bf_state.bfs_nframes
216#define bf_al bf_state.bfs_al
217#define bf_frmlen bf_state.bfs_frmlen
218#define bf_retries bf_state.bfs_retries
219#define bf_seqno bf_state.bfs_seqno
220#define bf_tidno bf_state.bfs_tidno
221#define bf_rcs bf_state.bfs_rcs
f078f209 222#define bf_keytype bf_state.bfs_keytype
cd3d39a6
S		 223#define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
224#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
225#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
226#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
227#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
228#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
229#define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
230#define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
231#define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
232#define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
f078f209
LR		 233
234/*
235 * Abstraction of a contiguous buffer to transmit/receive. There is only
236 * a single hw descriptor encapsulated here.
237 */
f078f209
LR		 238struct ath_buf {
239 struct list_head list;
240 struct list_head *last;
241 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
f22f558d 242 an aggregate) */
f078f209
LR		 243 struct ath_buf *bf_lastfrm; /* last buf of this frame */
244 struct ath_buf *bf_next; /* next subframe in the aggregate */
245 struct ath_buf *bf_rifslast; /* last buf for RIFS burst */
246 void *bf_mpdu; /* enclosing frame structure */
247 void *bf_node; /* pointer to the node */
248 struct ath_desc *bf_desc; /* virtual addr of desc */
249 dma_addr_t bf_daddr; /* physical addr of desc */
250 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
251 u32 bf_status;
f22f558d 252 u16 bf_flags; /* tx descriptor flags */
f078f209
LR		 253 struct ath_buf_state bf_state; /* buffer state */
254 dma_addr_t bf_dmacontext;
255};
256
257/*
258 * reset the rx buffer.
259 * any new fields added to the athbuf and require
260 * reset need to be added to this macro.
261 * currently bf_status is the only one requires that
262 * requires reset.
263 */
264#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
265
266/* hw processing complete, desc processed by hal */
267#define ATH_BUFSTATUS_DONE 0x00000001
268/* hw processing complete, desc hold for hw */
269#define ATH_BUFSTATUS_STALE 0x00000002
270/* Rx-only: OS is done with this packet and it's ok to queued it to hw */
271#define ATH_BUFSTATUS_FREE 0x00000004
272
273/* DMA state for tx/rx descriptors */
274
275struct ath_descdma {
276 const char *dd_name;
277 struct ath_desc *dd_desc; /* descriptors */
278 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
279 u32 dd_desc_len; /* size of dd_desc */
280 struct ath_buf *dd_bufptr; /* associated buffers */
281 dma_addr_t dd_dmacontext;
282};
283
284/* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
285
286struct ath_rx_context {
287 struct ath_buf *ctx_rxbuf; /* associated ath_buf for rx */
288};
289#define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
290
291int ath_descdma_setup(struct ath_softc *sc,
292 struct ath_descdma *dd,
293 struct list_head *head,
294 const char *name,
295 int nbuf,
296 int ndesc);
297int ath_desc_alloc(struct ath_softc *sc);
298void ath_desc_free(struct ath_softc *sc);
299void ath_descdma_cleanup(struct ath_softc *sc,
300 struct ath_descdma *dd,
301 struct list_head *head);
302
303/******/
304/* RX */
305/******/
306
307#define ATH_MAX_ANTENNA 3
308#define ATH_RXBUF 512
309#define ATH_RX_TIMEOUT 40 /* 40 milliseconds */
310#define WME_NUM_TID 16
311#define IEEE80211_BAR_CTL_TID_M 0xF000 /* tid mask */
a477e4e6 312#define IEEE80211_BAR_CTL_TID_S 12 /* tid shift */
f078f209
LR		 313
314enum ATH_RX_TYPE {
315 ATH_RX_NON_CONSUMED = 0,
316 ATH_RX_CONSUMED
317};
318
319/* per frame rx status block */
320struct ath_recv_status {
321 u64 tsf; /* mac tsf */
322 int8_t rssi; /* RSSI (noise floor ajusted) */
323 int8_t rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
324 int8_t rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
325 int8_t abs_rssi; /* absolute RSSI */
f22f558d
S		 326 u8 rateieee; /* data rate received (IEEE rate code) */
327 u8 ratecode; /* phy rate code */
f078f209
LR		 328 int rateKbps; /* data rate received (Kbps) */
329 int antenna; /* rx antenna */
330 int flags; /* status of associated skb */
331#define ATH_RX_FCS_ERROR 0x01
332#define ATH_RX_MIC_ERROR 0x02
333#define ATH_RX_DECRYPT_ERROR 0x04
334#define ATH_RX_RSSI_VALID 0x08
335/* if any of ctl,extn chainrssis are valid */
336#define ATH_RX_CHAIN_RSSI_VALID 0x10
337/* if extn chain rssis are valid */
338#define ATH_RX_RSSI_EXTN_VALID 0x20
339/* set if 40Mhz, clear if 20Mhz */
340#define ATH_RX_40MHZ 0x40
341/* set if short GI, clear if full GI */
342#define ATH_RX_SHORT_GI 0x80
343};
344
345struct ath_rxbuf {
f22f558d
S		 346 struct sk_buff *rx_wbuf;
347 unsigned long rx_time; /* system time when received */
348 struct ath_recv_status rx_status; /* cached rx status */
f078f209
LR		 349};
350
351/* Per-TID aggregate receiver state for a node */
352struct ath_arx_tid {
f22f558d
S		 353 struct ath_node *an;
354 struct ath_rxbuf *rxbuf; /* re-ordering buffer */
355 struct timer_list timer;
356 spinlock_t tidlock;
357 int baw_head; /* seq_next at head */
358 int baw_tail; /* tail of block-ack window */
359 int seq_reset; /* need to reset start sequence */
360 int addba_exchangecomplete;
361 u16 seq_next; /* next expected sequence */
362 u16 baw_size; /* block-ack window size */
f078f209
LR		 363};
364
365/* Per-node receiver aggregate state */
366struct ath_arx {
f22f558d 367 struct ath_arx_tid tid[WME_NUM_TID];
f078f209
LR		 368};
369
370int ath_startrecv(struct ath_softc *sc);
371bool ath_stoprecv(struct ath_softc *sc);
372void ath_flushrecv(struct ath_softc *sc);
373u32 ath_calcrxfilter(struct ath_softc *sc);
374void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
c5170163 375void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
f078f209
LR		 376void ath_handle_rx_intr(struct ath_softc *sc);
377int ath_rx_init(struct ath_softc *sc, int nbufs);
378void ath_rx_cleanup(struct ath_softc *sc);
379int ath_rx_tasklet(struct ath_softc *sc, int flush);
380int ath_rx_input(struct ath_softc *sc,
381 struct ath_node *node,
f078f209
LR		 382 struct sk_buff *skb,
383 struct ath_recv_status *rx_status,
384 enum ATH_RX_TYPE *status);
19b73c7f
S		 385int _ath_rx_indicate(struct ath_softc *sc,
386 struct sk_buff *skb,
387 struct ath_recv_status *status,
388 u16 keyix);
f078f209
LR		 389int ath_rx_subframe(struct ath_node *an, struct sk_buff *skb,
390 struct ath_recv_status *status);
391
392/******/
393/* TX */
394/******/
395
556bb8f1 396#define ATH_TXBUF 512
f078f209
LR		 397/* max number of transmit attempts (tries) */
398#define ATH_TXMAXTRY 13
399/* max number of 11n transmit attempts (tries) */
400#define ATH_11N_TXMAXTRY 10
401/* max number of tries for management and control frames */
402#define ATH_MGT_TXMAXTRY 4
403#define WME_BA_BMP_SIZE 64
404#define WME_MAX_BA WME_BA_BMP_SIZE
405#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
406#define TID_TO_WME_AC(_tid) \
407 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
408 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
409 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
410 WME_AC_VO)
411
412
413/* Wireless Multimedia Extension Defines */
414#define WME_AC_BE 0 /* best effort */
415#define WME_AC_BK 1 /* background */
416#define WME_AC_VI 2 /* video */
417#define WME_AC_VO 3 /* voice */
418#define WME_NUM_AC 4
419
420enum ATH_SM_PWRSAV{
421 ATH_SM_ENABLE,
422 ATH_SM_PWRSAV_STATIC,
423 ATH_SM_PWRSAV_DYNAMIC,
424};
425
426/*
427 * Data transmit queue state. One of these exists for each
428 * hardware transmit queue. Packets sent to us from above
429 * are assigned to queues based on their priority. Not all
430 * devices support a complete set of hardware transmit queues.
431 * For those devices the array sc_ac2q will map multiple
432 * priorities to fewer hardware queues (typically all to one
433 * hardware queue).
434 */
435struct ath_txq {
f22f558d
S		 436 u32 axq_qnum; /* hardware q number */
437 u32 *axq_link; /* link ptr in last TX desc */
438 struct list_head axq_q; /* transmit queue */
439 spinlock_t axq_lock;
440 unsigned long axq_lockflags; /* intr state when must cli */
441 u32 axq_depth; /* queue depth */
442 u8 axq_aggr_depth; /* aggregates queued */
443 u32 axq_totalqueued; /* total ever queued */
444
f22f558d
S		 445 bool stopped; /* Is mac80211 queue stopped ? */
446 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
447
448 /* first desc of the last descriptor that contains CTS */
449 struct ath_desc *axq_lastdsWithCTS;
450
451 /* final desc of the gating desc that determines whether
452 lastdsWithCTS has been DMA'ed or not */
453 struct ath_desc *axq_gatingds;
454
455 struct list_head axq_acq;
f078f209
LR		 456};
457
458/* per TID aggregate tx state for a destination */
459struct ath_atx_tid {
f22f558d
S		 460 struct list_head list; /* round-robin tid entry */
461 struct list_head buf_q; /* pending buffers */
462 struct ath_node *an;
463 struct ath_atx_ac *ac;
464 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
465 u16 seq_start;
466 u16 seq_next;
467 u16 baw_size;
468 int tidno;
469 int baw_head; /* first un-acked tx buffer */
470 int baw_tail; /* next unused tx buffer slot */
471 int sched;
472 int paused;
473 int cleanup_inprogress;
474 u32 addba_exchangecomplete:1;
475 int32_t addba_exchangeinprogress;
476 int addba_exchangeattempts;
f078f209
LR		 477};
478
479/* per access-category aggregate tx state for a destination */
480struct ath_atx_ac {
f22f558d
S		 481 int sched; /* dest-ac is scheduled */
482 int qnum; /* H/W queue number associated
483 with this AC */
484 struct list_head list; /* round-robin txq entry */
485 struct list_head tid_q; /* queue of TIDs with buffers */
f078f209
LR		 486};
487
488/* per dest tx state */
489struct ath_atx {
f22f558d
S		 490 struct ath_atx_tid tid[WME_NUM_TID];
491 struct ath_atx_ac ac[WME_NUM_AC];
f078f209
LR		 492};
493
494/* per-frame tx control block */
495struct ath_tx_control {
f22f558d
S		 496 struct ath_node *an;
497 int if_id;
498 int qnum;
499 u32 ht:1;
500 u32 ps:1;
501 u32 use_minrate:1;
502 enum ath9k_pkt_type atype;
503 enum ath9k_key_type keytype;
504 u32 flags;
505 u16 seqno;
506 u16 tidno;
507 u16 txpower;
508 u16 frmlen;
509 u32 keyix;
510 int min_rate;
511 int mcast_rate;
f22f558d 512 struct ath_softc *dev;
f078f209
LR		 513 dma_addr_t dmacontext;
514};
515
516/* per frame tx status block */
517struct ath_xmit_status {
f22f558d
S		 518 int retries; /* number of retries to successufully
519 transmit this frame */
520 int flags; /* status of transmit */
f078f209
LR		 521#define ATH_TX_ERROR 0x01
522#define ATH_TX_XRETRY 0x02
523#define ATH_TX_BAR 0x04
524};
525
526struct ath_tx_stat {
527 int rssi; /* RSSI (noise floor ajusted) */
528 int rssictl[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
529 int rssiextn[ATH_MAX_ANTENNA]; /* RSSI (noise floor ajusted) */
530 int rateieee; /* data rate xmitted (IEEE rate code) */
531 int rateKbps; /* data rate xmitted (Kbps) */
532 int ratecode; /* phy rate code */
533 int flags; /* validity flags */
534/* if any of ctl,extn chain rssis are valid */
535#define ATH_TX_CHAIN_RSSI_VALID 0x01
536/* if extn chain rssis are valid */
537#define ATH_TX_RSSI_EXTN_VALID 0x02
538 u32 airtime; /* time on air per final tx rate */
539};
540
541struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
542void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
543int ath_tx_setup(struct ath_softc *sc, int haltype);
544void ath_draintxq(struct ath_softc *sc, bool retry_tx);
545void ath_tx_draintxq(struct ath_softc *sc,
556bb8f1 546 struct ath_txq *txq, bool retry_tx);
f078f209 547void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
b5aa9bf9 548void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
f078f209
LR		 549void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an);
550void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
551int ath_tx_init(struct ath_softc *sc, int nbufs);
552int ath_tx_cleanup(struct ath_softc *sc);
553int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype);
ea9880fb
S		 554int ath_txq_update(struct ath_softc *sc, int qnum,
555 struct ath9k_tx_queue_info *q);
f078f209
LR		 556int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb);
557void ath_tx_tasklet(struct ath_softc *sc);
558u32 ath_txq_depth(struct ath_softc *sc, int qnum);
559u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum);
560void ath_notify_txq_status(struct ath_softc *sc, u16 queue_depth);
561void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
562 struct ath_xmit_status *tx_status, struct ath_node *an);
e022edbd 563void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
f078f209
LR		 564
565/**********************/
566/* Node / Aggregation */
567/**********************/
568
f078f209
LR		 569#define ADDBA_EXCHANGE_ATTEMPTS 10
570#define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
571#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
572/* number of delimiters for encryption padding */
573#define ATH_AGGR_ENCRYPTDELIM 10
574/* minimum h/w qdepth to be sustained to maximize aggregation */
575#define ATH_AGGR_MIN_QDEPTH 2
576#define ATH_AMPDU_SUBFRAME_DEFAULT 32
577#define IEEE80211_SEQ_SEQ_SHIFT 4
578#define IEEE80211_SEQ_MAX 4096
579#define IEEE80211_MIN_AMPDU_BUF 0x8
b5aa9bf9 580#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
f078f209
LR		 581
582/* return whether a bit at index _n in bitmap _bm is set
583 * _sz is the size of the bitmap */
584#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
585 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
586
587/* return block-ack bitmap index given sequence and starting sequence */
588#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
589
590/* returns delimiter padding required given the packet length */
591#define ATH_AGGR_GET_NDELIM(_len) \
592 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
593 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
594
595#define BAW_WITHIN(_start, _bawsz, _seqno) \
596 ((((_seqno) - (_start)) & 4095) < (_bawsz))
597
598#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
599#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
600#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
601#define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
602
603enum ATH_AGGR_STATUS {
604 ATH_AGGR_DONE,
605 ATH_AGGR_BAW_CLOSED,
606 ATH_AGGR_LIMITED,
607 ATH_AGGR_SHORTPKT,
608 ATH_AGGR_8K_LIMITED,
609};
610
611enum ATH_AGGR_CHECK {
612 AGGR_NOT_REQUIRED,
613 AGGR_REQUIRED,
614 AGGR_CLEANUP_PROGRESS,
615 AGGR_EXCHANGE_PROGRESS,
616 AGGR_EXCHANGE_DONE
617};
618
619struct aggr_rifs_param {
620 int param_max_frames;
621 int param_max_len;
622 int param_rl;
623 int param_al;
624 struct ath_rc_series *param_rcs;
625};
626
627/* Per-node aggregation state */
628struct ath_node_aggr {
f22f558d
S		 629 struct ath_atx tx; /* node transmit state */
630 struct ath_arx rx; /* node receive state */
f078f209
LR		 631};
632
633/* driver-specific node state */
634struct ath_node {
f22f558d 635 struct ath_softc *an_sc;
f078f209 636 struct ath_chainmask_sel an_chainmask_sel;
f22f558d
S		 637 struct ath_node_aggr an_aggr;
638 u8 an_smmode; /* SM Power save mode */
ae5eb026
JB		 639 u16 maxampdu;
640 u8 mpdudensity;
f078f209
LR		 641};
642
643void ath_tx_resume_tid(struct ath_softc *sc,
644 struct ath_atx_tid *tid);
645enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
646 struct ath_node *an, u8 tidno);
647void ath_tx_aggr_teardown(struct ath_softc *sc,
648 struct ath_node *an, u8 tidno);
649void ath_rx_aggr_teardown(struct ath_softc *sc,
650 struct ath_node *an, u8 tidno);
b5aa9bf9
S		 651int ath_rx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
652 u16 tid, u16 *ssn);
653int ath_rx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
654int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
655 u16 tid, u16 *ssn);
656int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
f078f209
LR		 657void ath_newassoc(struct ath_softc *sc,
658 struct ath_node *node, int isnew, int isuapsd);
b5aa9bf9
S		 659void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
660 int if_id);
661void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta);
f078f209
LR		 662
663/*******************/
664/* Beacon Handling */
665/*******************/
666
667/*
668 * Regardless of the number of beacons we stagger, (i.e. regardless of the
669 * number of BSSIDs) if a given beacon does not go out even after waiting this
670 * number of beacon intervals, the game's up.
671 */
672#define BSTUCK_THRESH (9 * ATH_BCBUF)
673#define ATH_BCBUF 4 /* number of beacon buffers */
674#define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
675#define ATH_DEFAULT_BMISS_LIMIT 10
f078f209
LR		 676#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
677
678/* beacon configuration */
679struct ath_beacon_config {
680 u16 beacon_interval;
681 u16 listen_interval;
682 u16 dtim_period;
683 u16 bmiss_timeout;
684 u8 dtim_count;
685 u8 tim_offset;
686 union {
687 u64 last_tsf;
688 u8 last_tstamp[8];
689 } u; /* last received beacon/probe response timestamp of this BSS. */
690};
691
f078f209
LR		 692void ath9k_beacon_tasklet(unsigned long data);
693void ath_beacon_config(struct ath_softc *sc, int if_id);
694int ath_beaconq_setup(struct ath_hal *ah);
695int ath_beacon_alloc(struct ath_softc *sc, int if_id);
696void ath_bstuck_process(struct ath_softc *sc);
f078f209
LR		 697void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
698void ath_beacon_sync(struct ath_softc *sc, int if_id);
f078f209
LR		 699void ath_get_beaconconfig(struct ath_softc *sc,
700 int if_id,
701 struct ath_beacon_config *conf);
f078f209
LR		 702/********/
703/* VAPs */
704/********/
705
f078f209
LR		 706/*
707 * Define the scheme that we select MAC address for multiple
708 * BSS on the same radio. The very first VAP will just use the MAC
709 * address from the EEPROM. For the next 3 VAPs, we set the
710 * U/L bit (bit 1) in MAC address, and use the next two bits as the
711 * index of the VAP.
712 */
713
714#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
715 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
716
717/* VAP configuration (from protocol layer) */
718struct ath_vap_config {
719 u32 av_fixed_rateset;
720 u32 av_fixed_retryset;
721};
722
723/* driver-specific vap state */
724struct ath_vap {
f22f558d
S		 725 struct ieee80211_vif *av_if_data;
726 enum ath9k_opmode av_opmode; /* VAP operational mode */
727 struct ath_buf *av_bcbuf; /* beacon buffer */
f22f558d
S		 728 struct ath_tx_control av_btxctl; /* txctl information for beacon */
729 int av_bslot; /* beacon slot index */
f22f558d
S		 730 struct ath_vap_config av_config;/* vap configuration parameters*/
731 struct ath_rate_node *rc_node;
f078f209
LR		 732};
733
734int ath_vap_attach(struct ath_softc *sc,
735 int if_id,
736 struct ieee80211_vif *if_data,
737 enum ath9k_opmode opmode);
738int ath_vap_detach(struct ath_softc *sc, int if_id);
739int ath_vap_config(struct ath_softc *sc,
ff9b662d 740 int if_id, struct ath_vap_config *if_config);
f078f209
LR		 741
742/*********************/
743/* Antenna diversity */
744/*********************/
745
746#define ATH_ANT_DIV_MAX_CFG 2
747#define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */
748#define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */
749
750enum ATH_ANT_DIV_STATE{
751 ATH_ANT_DIV_IDLE,
752 ATH_ANT_DIV_SCAN, /* evaluating antenna */
753};
754
755struct ath_antdiv {
756 struct ath_softc *antdiv_sc;
757 u8 antdiv_start;
758 enum ATH_ANT_DIV_STATE antdiv_state;
759 u8 antdiv_num_antcfg;
760 u8 antdiv_curcfg;
761 u8 antdiv_bestcfg;
762 int32_t antdivf_rssitrig;
763 int32_t antdiv_lastbrssi[ATH_ANT_DIV_MAX_CFG];
764 u64 antdiv_lastbtsf[ATH_ANT_DIV_MAX_CFG];
765 u64 antdiv_laststatetsf;
766 u8 antdiv_bssid[ETH_ALEN];
767};
768
769void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
770 struct ath_softc *sc, int32_t rssitrig);
771void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
772 u8 num_antcfg,
773 const u8 *bssid);
774void ath_slow_ant_div_stop(struct ath_antdiv *antdiv);
775void ath_slow_ant_div(struct ath_antdiv *antdiv,
776 struct ieee80211_hdr *wh,
777 struct ath_rx_status *rx_stats);
778void ath_setdefantenna(void *sc, u32 antenna);
779
6f255425
LR		 780/*******/
781/* ANI */
782/*******/
783
784/* ANI values for STA only.
785 FIXME: Add appropriate values for AP later */
786
787#define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
788#define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
789#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
790#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
791
792struct ath_ani {
793 bool sc_caldone;
794 int16_t sc_noise_floor;
795 unsigned int sc_longcal_timer;
796 unsigned int sc_shortcal_timer;
797 unsigned int sc_resetcal_timer;
798 unsigned int sc_checkani_timer;
799 struct timer_list timer;
800};
801
c83be688
VT		 802/********************/
803/* LED Control */
804/********************/
805
806#define ATH_LED_PIN 1
807
808enum ath_led_type {
809 ATH_LED_RADIO,
810 ATH_LED_ASSOC,
811 ATH_LED_TX,
812 ATH_LED_RX
813};
814
815struct ath_led {
816 struct ath_softc *sc;
817 struct led_classdev led_cdev;
818 enum ath_led_type led_type;
819 char name[32];
820 bool registered;
821};
822
500c064d
VT		 823/* Rfkill */
824#define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
825
826struct ath_rfkill {
827 struct rfkill *rfkill;
828 struct delayed_work rfkill_poll;
829 char rfkill_name[32];
830};
831
f078f209
LR		 832/********************/
833/* Main driver core */
834/********************/
835
836/*
837 * Default cache line size, in bytes.
838 * Used when PCI device not fully initialized by bootrom/BIOS
839*/
840#define DEFAULT_CACHELINE 32
841#define ATH_DEFAULT_NOISE_FLOOR -95
842#define ATH_REGCLASSIDS_MAX 10
843#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
f078f209 844#define ATH_MAX_SW_RETRIES 10
f078f209
LR		 845#define ATH_CHAN_MAX 255
846#define IEEE80211_WEP_NKID 4 /* number of key ids */
847#define IEEE80211_RATE_VAL 0x7f
848/*
849 * The key cache is used for h/w cipher state and also for
850 * tracking station state such as the current tx antenna.
851 * We also setup a mapping table between key cache slot indices
852 * and station state to short-circuit node lookups on rx.
853 * Different parts have different size key caches. We handle
854 * up to ATH_KEYMAX entries (could dynamically allocate state).
855 */
856#define ATH_KEYMAX 128 /* max key cache size we handle */
857
f078f209 858#define ATH_IF_ID_ANY 0xff
f078f209
LR		 859#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
860
861#define RSSI_LPF_THRESHOLD -20
862#define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
863#define ATH_RATE_DUMMY_MARKER 0
864#define ATH_RSSI_LPF_LEN 10
865#define ATH_RSSI_DUMMY_MARKER 0x127
866
867#define ATH_EP_MUL(x, mul) ((x) * (mul))
868#define ATH_EP_RND(x, mul) \
869 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
870#define ATH_RSSI_OUT(x) \
871 (((x) != ATH_RSSI_DUMMY_MARKER) ? \
872 (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
873#define ATH_RSSI_IN(x) \
874 (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
875#define ATH_LPF_RSSI(x, y, len) \
876 ((x != ATH_RSSI_DUMMY_MARKER) ? \
877 (((x) * ((len) - 1) + (y)) / (len)) : (y))
878#define ATH_RSSI_LPF(x, y) do { \
879 if ((y) >= RSSI_LPF_THRESHOLD) \
880 x = ATH_LPF_RSSI((x), \
881 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
882 } while (0)
883
884
885enum PROT_MODE {
886 PROT_M_NONE = 0,
887 PROT_M_RTSCTS,
888 PROT_M_CTSONLY
889};
890
891enum RATE_TYPE {
892 NORMAL_RATE = 0,
893 HALF_RATE,
894 QUARTER_RATE
895};
896
897struct ath_ht_info {
898 enum ath9k_ht_macmode tx_chan_width;
f078f209
LR		 899 u8 ext_chan_offset;
900};
901
672840ac
S		 902#define SC_OP_INVALID BIT(0)
903#define SC_OP_BEACONS BIT(1)
904#define SC_OP_RXAGGR BIT(2)
905#define SC_OP_TXAGGR BIT(3)
906#define SC_OP_CHAINMASK_UPDATE BIT(4)
907#define SC_OP_FULL_RESET BIT(5)
98deeea0
S		 908#define SC_OP_NO_RESET BIT(6)
909#define SC_OP_PREAMBLE_SHORT BIT(7)
910#define SC_OP_PROTECT_ENABLE BIT(8)
911#define SC_OP_RXFLUSH BIT(9)
c83be688 912#define SC_OP_LED_ASSOCIATED BIT(10)
500c064d
VT		 913#define SC_OP_RFKILL_REGISTERED BIT(11)
914#define SC_OP_RFKILL_SW_BLOCKED BIT(12)
915#define SC_OP_RFKILL_HW_BLOCKED BIT(13)
672840ac 916
f078f209 917struct ath_softc {
ea9880fb
S		 918 struct ieee80211_hw *hw;
919 struct pci_dev *pdev;
ea9880fb
S		 920 struct tasklet_struct intr_tq;
921 struct tasklet_struct bcon_tasklet;
672840ac 922 struct ath_config sc_config;
ea9880fb 923 struct ath_hal *sc_ah;
672840ac 924 struct ath_rate_softc *sc_rc;
b4696c8b
S		 925 void __iomem *mem;
926
98deeea0
S		 927 u8 sc_curbssid[ETH_ALEN];
928 u8 sc_myaddr[ETH_ALEN];
929 u8 sc_bssidmask[ETH_ALEN];
930
b4696c8b 931 int sc_debug;
ea9880fb 932 u32 sc_intrstatus;
672840ac 933 u32 sc_flags; /* SC_OP_* */
7dcfdcd9 934 unsigned int rx_filter;
ea9880fb
S		 935 u16 sc_curtxpow;
936 u16 sc_curaid;
98deeea0
S		 937 u16 sc_cachelsz;
938 int sc_slotupdate; /* slot to next advance fsm */
939 int sc_slottime;
940 int sc_bslot[ATH_BCBUF];
941 u8 sc_tx_chainmask;
942 u8 sc_rx_chainmask;
943 enum ath9k_int sc_imask;
944 enum wireless_mode sc_curmode; /* current phy mode */
ea9880fb 945 enum PROT_MODE sc_protmode;
98deeea0 946
ea9880fb
S		 947 u8 sc_nbcnvaps; /* # of vaps sending beacons */
948 u16 sc_nvaps; /* # of active virtual ap's */
949 struct ath_vap *sc_vaps[ATH_BCBUF];
98deeea0
S		 950
951 u8 sc_mcastantenna;
ea9880fb
S		 952 u8 sc_defant; /* current default antenna */
953 u8 sc_rxotherant; /* rx's on non-default antenna */
98deeea0 954
ea9880fb 955 struct ath9k_node_stats sc_halstats; /* station-mode rssi stats */
ea9880fb 956 struct ath_ht_info sc_ht_info;
ea9880fb 957 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
98deeea0 958
f078f209 959#ifdef CONFIG_SLOW_ANT_DIV
ea9880fb 960 struct ath_antdiv sc_antdiv;
f078f209
LR		 961#endif
962 enum {
ea9880fb
S		 963 OK, /* no change needed */
964 UPDATE, /* update pending */
965 COMMIT /* beacon sent, commit change */
966 } sc_updateslot; /* slot time update fsm */
f078f209
LR		 967
968 /* Crypto */
ea9880fb
S		 969 u32 sc_keymax; /* size of key cache */
970 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX); /* key use bit map */
971 u8 sc_splitmic; /* split TKIP MIC keys */
f078f209
LR		 972
973 /* RX */
ea9880fb
S		 974 struct list_head sc_rxbuf;
975 struct ath_descdma sc_rxdma;
976 int sc_rxbufsize; /* rx size based on mtu */
977 u32 *sc_rxlink; /* link ptr in last RX desc */
f078f209
LR		 978
979 /* TX */
ea9880fb
S		 980 struct list_head sc_txbuf;
981 struct ath_txq sc_txq[ATH9K_NUM_TX_QUEUES];
982 struct ath_descdma sc_txdma;
983 u32 sc_txqsetup;
ea9880fb 984 int sc_haltype2q[ATH9K_WME_AC_VO+1]; /* HAL WME AC -> h/w qnum */
147583c0 985 u16 seq_no; /* TX sequence number */
f078f209
LR		 986
987 /* Beacon */
ea9880fb
S		 988 struct ath9k_tx_queue_info sc_beacon_qi;
989 struct ath_descdma sc_bdma;
990 struct ath_txq *sc_cabq;
991 struct list_head sc_bbuf;
992 u32 sc_bhalq;
993 u32 sc_bmisscount;
994 u32 ast_be_xmit; /* beacons transmitted */
459f5f90 995 u64 bc_tstamp;
f078f209
LR		 996
997 /* Rate */
ea9880fb 998 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
ea9880fb
S		 999 const struct ath9k_rate_table *sc_currates;
1000 u8 sc_rixmap[256]; /* IEEE to h/w rate table ix */
ea9880fb 1001 u8 sc_protrix; /* protection rate index */
f078f209 1002 struct {
ea9880fb
S		 1003 u32 rateKbps; /* transfer rate in kbs */
1004 u8 ieeerate; /* IEEE rate */
1005 } sc_hwmap[256]; /* h/w rate ix mappings */
f078f209
LR		 1006
1007 /* Channel, Band */
1008 struct ieee80211_channel channels[IEEE80211_NUM_BANDS][ATH_CHAN_MAX];
1009 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
f078f209
LR		 1010
1011 /* Locks */
ea9880fb
S		 1012 spinlock_t sc_rxflushlock;
1013 spinlock_t sc_rxbuflock;
1014 spinlock_t sc_txbuflock;
1015 spinlock_t sc_resetlock;
c83be688
VT		 1016
1017 /* LEDs */
1018 struct ath_led radio_led;
1019 struct ath_led assoc_led;
1020 struct ath_led tx_led;
1021 struct ath_led rx_led;
500c064d
VT		 1022
1023 /* Rfkill */
1024 struct ath_rfkill rf_kill;
6f255425
LR		 1025
1026 /* ANI */
1027 struct ath_ani sc_ani;
f078f209
LR		 1028};
1029
1030int ath_init(u16 devid, struct ath_softc *sc);
1031void ath_deinit(struct ath_softc *sc);
1032int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan);
1033int ath_suspend(struct ath_softc *sc);
1034irqreturn_t ath_isr(int irq, void *dev);
f45144ef 1035int ath_reset(struct ath_softc *sc, bool retry_tx);
f078f209 1036int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan);
f078f209
LR		 1037
1038/*********************/
1039/* Utility Functions */
1040/*********************/
1041
1042void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot);
1043int ath_keyset(struct ath_softc *sc,
1044 u16 keyix,
1045 struct ath9k_keyval *hk,
1046 const u8 mac[ETH_ALEN]);
1047int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
1048int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
1049void ath_setslottime(struct ath_softc *sc);
1050void ath_update_txpow(struct ath_softc *sc);
1051int ath_cabq_update(struct ath_softc *);
1052void ath_get_currentCountry(struct ath_softc *sc,
1053 struct ath9k_country_entry *ctry);
1054u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp);
f078f209
LR		 1055
1056#endif /* CORE_H */
Linux kernel - Deliverables
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