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f1dc5600 S |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include "core.h" | |
18 | #include "hw.h" | |
19 | #include "reg.h" | |
20 | #include "phy.h" | |
21 | ||
22 | static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah, | |
23 | u32 reg, u32 mask, | |
24 | u32 shift, u32 val) | |
25 | { | |
26 | u32 regVal; | |
27 | ||
28 | regVal = REG_READ(ah, reg) & ~mask; | |
29 | regVal |= (val << shift) & mask; | |
30 | ||
31 | REG_WRITE(ah, reg, regVal); | |
32 | ||
33 | if (ah->ah_config.analog_shiftreg) | |
34 | udelay(100); | |
35 | ||
36 | return; | |
37 | } | |
38 | ||
39 | static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) | |
40 | { | |
41 | ||
42 | if (fbin == AR5416_BCHAN_UNUSED) | |
43 | return fbin; | |
44 | ||
45 | return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); | |
46 | } | |
47 | ||
48 | static inline int16_t ath9k_hw_interpolate(u16 target, | |
49 | u16 srcLeft, u16 srcRight, | |
50 | int16_t targetLeft, | |
51 | int16_t targetRight) | |
52 | { | |
53 | int16_t rv; | |
54 | ||
55 | if (srcRight == srcLeft) { | |
56 | rv = targetLeft; | |
57 | } else { | |
58 | rv = (int16_t) (((target - srcLeft) * targetRight + | |
59 | (srcRight - target) * targetLeft) / | |
60 | (srcRight - srcLeft)); | |
61 | } | |
62 | return rv; | |
63 | } | |
64 | ||
65 | static inline bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, | |
66 | u16 listSize, u16 *indexL, | |
67 | u16 *indexR) | |
68 | { | |
69 | u16 i; | |
70 | ||
71 | if (target <= pList[0]) { | |
72 | *indexL = *indexR = 0; | |
73 | return true; | |
74 | } | |
75 | if (target >= pList[listSize - 1]) { | |
76 | *indexL = *indexR = (u16) (listSize - 1); | |
77 | return true; | |
78 | } | |
79 | ||
80 | for (i = 0; i < listSize - 1; i++) { | |
81 | if (pList[i] == target) { | |
82 | *indexL = *indexR = i; | |
83 | return true; | |
84 | } | |
85 | if (target < pList[i + 1]) { | |
86 | *indexL = i; | |
87 | *indexR = (u16) (i + 1); | |
88 | return false; | |
89 | } | |
90 | } | |
91 | return false; | |
92 | } | |
93 | ||
94 | static bool ath9k_hw_eeprom_read(struct ath_hal *ah, u32 off, u16 *data) | |
95 | { | |
96 | (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); | |
97 | ||
98 | if (!ath9k_hw_wait(ah, | |
99 | AR_EEPROM_STATUS_DATA, | |
100 | AR_EEPROM_STATUS_DATA_BUSY | | |
101 | AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) { | |
102 | return false; | |
103 | } | |
104 | ||
105 | *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA), | |
106 | AR_EEPROM_STATUS_DATA_VAL); | |
107 | ||
108 | return true; | |
109 | } | |
110 | ||
111 | static int ath9k_hw_flash_map(struct ath_hal *ah) | |
112 | { | |
113 | struct ath_hal_5416 *ahp = AH5416(ah); | |
114 | ||
115 | ahp->ah_cal_mem = ioremap(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX); | |
116 | ||
117 | if (!ahp->ah_cal_mem) { | |
118 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
04bd4638 | 119 | "cannot remap eeprom region \n"); |
f1dc5600 S |
120 | return -EIO; |
121 | } | |
122 | ||
123 | return 0; | |
124 | } | |
125 | ||
126 | static bool ath9k_hw_flash_read(struct ath_hal *ah, u32 off, u16 *data) | |
127 | { | |
128 | struct ath_hal_5416 *ahp = AH5416(ah); | |
129 | ||
130 | *data = ioread16(ahp->ah_cal_mem + off); | |
131 | ||
132 | return true; | |
133 | } | |
134 | ||
135 | static inline bool ath9k_hw_nvram_read(struct ath_hal *ah, u32 off, u16 *data) | |
136 | { | |
137 | if (ath9k_hw_use_flash(ah)) | |
138 | return ath9k_hw_flash_read(ah, off, data); | |
139 | else | |
140 | return ath9k_hw_eeprom_read(ah, off, data); | |
141 | } | |
142 | ||
143 | static bool ath9k_hw_fill_eeprom(struct ath_hal *ah) | |
144 | { | |
145 | struct ath_hal_5416 *ahp = AH5416(ah); | |
146 | struct ar5416_eeprom *eep = &ahp->ah_eeprom; | |
147 | u16 *eep_data; | |
148 | int addr, ar5416_eep_start_loc = 0; | |
149 | ||
150 | if (!ath9k_hw_use_flash(ah)) { | |
151 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
04bd4638 | 152 | "Reading from EEPROM, not flash\n"); |
f1dc5600 S |
153 | ar5416_eep_start_loc = 256; |
154 | } | |
155 | ||
156 | if (AR_SREV_9100(ah)) | |
157 | ar5416_eep_start_loc = 256; | |
158 | ||
159 | eep_data = (u16 *)eep; | |
160 | ||
161 | for (addr = 0; addr < sizeof(struct ar5416_eeprom) / sizeof(u16); addr++) { | |
162 | if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, | |
163 | eep_data)) { | |
164 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
04bd4638 | 165 | "Unable to read eeprom region \n"); |
f1dc5600 S |
166 | return false; |
167 | } | |
168 | eep_data++; | |
169 | } | |
170 | return true; | |
171 | } | |
172 | ||
173 | static int ath9k_hw_check_eeprom(struct ath_hal *ah) | |
174 | { | |
175 | struct ath_hal_5416 *ahp = AH5416(ah); | |
176 | struct ar5416_eeprom *eep = | |
177 | (struct ar5416_eeprom *) &ahp->ah_eeprom; | |
178 | u16 *eepdata, temp, magic, magic2; | |
179 | u32 sum = 0, el; | |
180 | bool need_swap = false; | |
181 | int i, addr, size; | |
182 | ||
183 | if (!ath9k_hw_use_flash(ah)) { | |
184 | if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, | |
185 | &magic)) { | |
186 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
04bd4638 | 187 | "Reading Magic # failed\n"); |
f1dc5600 S |
188 | return false; |
189 | } | |
190 | ||
04bd4638 | 191 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "Read Magic = 0x%04X\n", magic); |
f1dc5600 S |
192 | |
193 | if (magic != AR5416_EEPROM_MAGIC) { | |
194 | magic2 = swab16(magic); | |
195 | ||
196 | if (magic2 == AR5416_EEPROM_MAGIC) { | |
197 | size = sizeof(struct ar5416_eeprom); | |
198 | need_swap = true; | |
199 | eepdata = (u16 *) (&ahp->ah_eeprom); | |
200 | ||
201 | for (addr = 0; addr < size / sizeof(u16); addr++) { | |
202 | temp = swab16(*eepdata); | |
203 | *eepdata = temp; | |
204 | eepdata++; | |
205 | ||
206 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
207 | "0x%04X ", *eepdata); | |
208 | ||
209 | if (((addr + 1) % 6) == 0) | |
210 | DPRINTF(ah->ah_sc, | |
211 | ATH_DBG_EEPROM, "\n"); | |
212 | } | |
213 | } else { | |
214 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
215 | "Invalid EEPROM Magic. " | |
216 | "endianness mismatch.\n"); | |
217 | return -EINVAL; | |
218 | } | |
219 | } | |
220 | } | |
221 | ||
222 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", | |
223 | need_swap ? "True" : "False"); | |
224 | ||
225 | if (need_swap) | |
226 | el = swab16(ahp->ah_eeprom.baseEepHeader.length); | |
227 | else | |
228 | el = ahp->ah_eeprom.baseEepHeader.length; | |
229 | ||
230 | if (el > sizeof(struct ar5416_eeprom)) | |
231 | el = sizeof(struct ar5416_eeprom) / sizeof(u16); | |
232 | else | |
233 | el = el / sizeof(u16); | |
234 | ||
235 | eepdata = (u16 *)(&ahp->ah_eeprom); | |
236 | ||
237 | for (i = 0; i < el; i++) | |
238 | sum ^= *eepdata++; | |
239 | ||
240 | if (need_swap) { | |
241 | u32 integer, j; | |
242 | u16 word; | |
243 | ||
244 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
245 | "EEPROM Endianness is not native.. Changing \n"); | |
246 | ||
247 | word = swab16(eep->baseEepHeader.length); | |
248 | eep->baseEepHeader.length = word; | |
249 | ||
250 | word = swab16(eep->baseEepHeader.checksum); | |
251 | eep->baseEepHeader.checksum = word; | |
252 | ||
253 | word = swab16(eep->baseEepHeader.version); | |
254 | eep->baseEepHeader.version = word; | |
255 | ||
256 | word = swab16(eep->baseEepHeader.regDmn[0]); | |
257 | eep->baseEepHeader.regDmn[0] = word; | |
258 | ||
259 | word = swab16(eep->baseEepHeader.regDmn[1]); | |
260 | eep->baseEepHeader.regDmn[1] = word; | |
261 | ||
262 | word = swab16(eep->baseEepHeader.rfSilent); | |
263 | eep->baseEepHeader.rfSilent = word; | |
264 | ||
265 | word = swab16(eep->baseEepHeader.blueToothOptions); | |
266 | eep->baseEepHeader.blueToothOptions = word; | |
267 | ||
268 | word = swab16(eep->baseEepHeader.deviceCap); | |
269 | eep->baseEepHeader.deviceCap = word; | |
270 | ||
271 | for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) { | |
272 | struct modal_eep_header *pModal = | |
273 | &eep->modalHeader[j]; | |
274 | integer = swab32(pModal->antCtrlCommon); | |
275 | pModal->antCtrlCommon = integer; | |
276 | ||
277 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
278 | integer = swab32(pModal->antCtrlChain[i]); | |
279 | pModal->antCtrlChain[i] = integer; | |
280 | } | |
281 | ||
282 | for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { | |
283 | word = swab16(pModal->spurChans[i].spurChan); | |
284 | pModal->spurChans[i].spurChan = word; | |
285 | } | |
286 | } | |
287 | } | |
288 | ||
289 | if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER || | |
290 | ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) { | |
291 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
292 | "Bad EEPROM checksum 0x%x or revision 0x%04x\n", | |
293 | sum, ar5416_get_eep_ver(ahp)); | |
294 | return -EINVAL; | |
295 | } | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
300 | static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, | |
301 | u8 *pVpdList, u16 numIntercepts, | |
302 | u8 *pRetVpdList) | |
303 | { | |
304 | u16 i, k; | |
305 | u8 currPwr = pwrMin; | |
306 | u16 idxL = 0, idxR = 0; | |
307 | ||
308 | for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) { | |
309 | ath9k_hw_get_lower_upper_index(currPwr, pPwrList, | |
310 | numIntercepts, &(idxL), | |
311 | &(idxR)); | |
312 | if (idxR < 1) | |
313 | idxR = 1; | |
314 | if (idxL == numIntercepts - 1) | |
315 | idxL = (u16) (numIntercepts - 2); | |
316 | if (pPwrList[idxL] == pPwrList[idxR]) | |
317 | k = pVpdList[idxL]; | |
318 | else | |
319 | k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] + | |
320 | (pPwrList[idxR] - currPwr) * pVpdList[idxL]) / | |
321 | (pPwrList[idxR] - pPwrList[idxL])); | |
322 | pRetVpdList[i] = (u8) k; | |
323 | currPwr += 2; | |
324 | } | |
325 | ||
326 | return true; | |
327 | } | |
328 | ||
329 | static void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah, | |
330 | struct ath9k_channel *chan, | |
331 | struct cal_data_per_freq *pRawDataSet, | |
332 | u8 *bChans, u16 availPiers, | |
333 | u16 tPdGainOverlap, int16_t *pMinCalPower, | |
334 | u16 *pPdGainBoundaries, u8 *pPDADCValues, | |
335 | u16 numXpdGains) | |
336 | { | |
337 | int i, j, k; | |
338 | int16_t ss; | |
339 | u16 idxL = 0, idxR = 0, numPiers; | |
340 | static u8 vpdTableL[AR5416_NUM_PD_GAINS] | |
341 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | |
342 | static u8 vpdTableR[AR5416_NUM_PD_GAINS] | |
343 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | |
344 | static u8 vpdTableI[AR5416_NUM_PD_GAINS] | |
345 | [AR5416_MAX_PWR_RANGE_IN_HALF_DB]; | |
346 | ||
347 | u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR; | |
348 | u8 minPwrT4[AR5416_NUM_PD_GAINS]; | |
349 | u8 maxPwrT4[AR5416_NUM_PD_GAINS]; | |
350 | int16_t vpdStep; | |
351 | int16_t tmpVal; | |
352 | u16 sizeCurrVpdTable, maxIndex, tgtIndex; | |
353 | bool match; | |
354 | int16_t minDelta = 0; | |
355 | struct chan_centers centers; | |
356 | ||
357 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
358 | ||
359 | for (numPiers = 0; numPiers < availPiers; numPiers++) { | |
360 | if (bChans[numPiers] == AR5416_BCHAN_UNUSED) | |
361 | break; | |
362 | } | |
363 | ||
364 | match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center, | |
365 | IS_CHAN_2GHZ(chan)), | |
366 | bChans, numPiers, &idxL, &idxR); | |
367 | ||
368 | if (match) { | |
369 | for (i = 0; i < numXpdGains; i++) { | |
370 | minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; | |
371 | maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; | |
372 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | |
373 | pRawDataSet[idxL].pwrPdg[i], | |
374 | pRawDataSet[idxL].vpdPdg[i], | |
375 | AR5416_PD_GAIN_ICEPTS, | |
376 | vpdTableI[i]); | |
377 | } | |
378 | } else { | |
379 | for (i = 0; i < numXpdGains; i++) { | |
380 | pVpdL = pRawDataSet[idxL].vpdPdg[i]; | |
381 | pPwrL = pRawDataSet[idxL].pwrPdg[i]; | |
382 | pVpdR = pRawDataSet[idxR].vpdPdg[i]; | |
383 | pPwrR = pRawDataSet[idxR].pwrPdg[i]; | |
384 | ||
385 | minPwrT4[i] = max(pPwrL[0], pPwrR[0]); | |
386 | ||
387 | maxPwrT4[i] = | |
388 | min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], | |
389 | pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); | |
390 | ||
391 | ||
392 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | |
393 | pPwrL, pVpdL, | |
394 | AR5416_PD_GAIN_ICEPTS, | |
395 | vpdTableL[i]); | |
396 | ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i], | |
397 | pPwrR, pVpdR, | |
398 | AR5416_PD_GAIN_ICEPTS, | |
399 | vpdTableR[i]); | |
400 | ||
401 | for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { | |
402 | vpdTableI[i][j] = | |
403 | (u8)(ath9k_hw_interpolate((u16) | |
404 | FREQ2FBIN(centers. | |
405 | synth_center, | |
406 | IS_CHAN_2GHZ | |
407 | (chan)), | |
408 | bChans[idxL], bChans[idxR], | |
409 | vpdTableL[i][j], vpdTableR[i][j])); | |
410 | } | |
411 | } | |
412 | } | |
413 | ||
414 | *pMinCalPower = (int16_t)(minPwrT4[0] / 2); | |
415 | ||
416 | k = 0; | |
417 | ||
418 | for (i = 0; i < numXpdGains; i++) { | |
419 | if (i == (numXpdGains - 1)) | |
420 | pPdGainBoundaries[i] = | |
421 | (u16)(maxPwrT4[i] / 2); | |
422 | else | |
423 | pPdGainBoundaries[i] = | |
424 | (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4); | |
425 | ||
426 | pPdGainBoundaries[i] = | |
427 | min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); | |
428 | ||
429 | if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) { | |
430 | minDelta = pPdGainBoundaries[0] - 23; | |
431 | pPdGainBoundaries[0] = 23; | |
432 | } else { | |
433 | minDelta = 0; | |
434 | } | |
435 | ||
436 | if (i == 0) { | |
437 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
438 | ss = (int16_t)(0 - (minPwrT4[i] / 2)); | |
439 | else | |
440 | ss = 0; | |
441 | } else { | |
442 | ss = (int16_t)((pPdGainBoundaries[i - 1] - | |
443 | (minPwrT4[i] / 2)) - | |
444 | tPdGainOverlap + 1 + minDelta); | |
445 | } | |
446 | vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); | |
447 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); | |
448 | ||
449 | while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { | |
450 | tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); | |
451 | pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal); | |
452 | ss++; | |
453 | } | |
454 | ||
455 | sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1); | |
456 | tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap - | |
457 | (minPwrT4[i] / 2)); | |
458 | maxIndex = (tgtIndex < sizeCurrVpdTable) ? | |
459 | tgtIndex : sizeCurrVpdTable; | |
460 | ||
461 | while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { | |
462 | pPDADCValues[k++] = vpdTableI[i][ss++]; | |
463 | } | |
464 | ||
465 | vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - | |
466 | vpdTableI[i][sizeCurrVpdTable - 2]); | |
467 | vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); | |
468 | ||
469 | if (tgtIndex > maxIndex) { | |
470 | while ((ss <= tgtIndex) && | |
471 | (k < (AR5416_NUM_PDADC_VALUES - 1))) { | |
472 | tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + | |
473 | (ss - maxIndex + 1) * vpdStep)); | |
474 | pPDADCValues[k++] = (u8)((tmpVal > 255) ? | |
475 | 255 : tmpVal); | |
476 | ss++; | |
477 | } | |
478 | } | |
479 | } | |
480 | ||
481 | while (i < AR5416_PD_GAINS_IN_MASK) { | |
482 | pPdGainBoundaries[i] = pPdGainBoundaries[i - 1]; | |
483 | i++; | |
484 | } | |
485 | ||
486 | while (k < AR5416_NUM_PDADC_VALUES) { | |
487 | pPDADCValues[k] = pPDADCValues[k - 1]; | |
488 | k++; | |
489 | } | |
490 | ||
491 | return; | |
492 | } | |
493 | ||
494 | static void ath9k_hw_get_legacy_target_powers(struct ath_hal *ah, | |
495 | struct ath9k_channel *chan, | |
496 | struct cal_target_power_leg *powInfo, | |
497 | u16 numChannels, | |
498 | struct cal_target_power_leg *pNewPower, | |
499 | u16 numRates, bool isExtTarget) | |
500 | { | |
501 | struct chan_centers centers; | |
502 | u16 clo, chi; | |
503 | int i; | |
504 | int matchIndex = -1, lowIndex = -1; | |
505 | u16 freq; | |
506 | ||
507 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
508 | freq = (isExtTarget) ? centers.ext_center : centers.ctl_center; | |
509 | ||
510 | if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, | |
511 | IS_CHAN_2GHZ(chan))) { | |
512 | matchIndex = 0; | |
513 | } else { | |
514 | for (i = 0; (i < numChannels) && | |
515 | (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { | |
516 | if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel, | |
517 | IS_CHAN_2GHZ(chan))) { | |
518 | matchIndex = i; | |
519 | break; | |
520 | } else if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel, | |
521 | IS_CHAN_2GHZ(chan))) && | |
522 | (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel, | |
523 | IS_CHAN_2GHZ(chan)))) { | |
524 | lowIndex = i - 1; | |
525 | break; | |
526 | } | |
527 | } | |
528 | if ((matchIndex == -1) && (lowIndex == -1)) | |
529 | matchIndex = i - 1; | |
530 | } | |
531 | ||
532 | if (matchIndex != -1) { | |
533 | *pNewPower = powInfo[matchIndex]; | |
534 | } else { | |
535 | clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, | |
536 | IS_CHAN_2GHZ(chan)); | |
537 | chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, | |
538 | IS_CHAN_2GHZ(chan)); | |
539 | ||
540 | for (i = 0; i < numRates; i++) { | |
541 | pNewPower->tPow2x[i] = | |
542 | (u8)ath9k_hw_interpolate(freq, clo, chi, | |
543 | powInfo[lowIndex].tPow2x[i], | |
544 | powInfo[lowIndex + 1].tPow2x[i]); | |
545 | } | |
546 | } | |
547 | } | |
548 | ||
549 | static void ath9k_hw_get_target_powers(struct ath_hal *ah, | |
550 | struct ath9k_channel *chan, | |
551 | struct cal_target_power_ht *powInfo, | |
552 | u16 numChannels, | |
553 | struct cal_target_power_ht *pNewPower, | |
554 | u16 numRates, bool isHt40Target) | |
555 | { | |
556 | struct chan_centers centers; | |
557 | u16 clo, chi; | |
558 | int i; | |
559 | int matchIndex = -1, lowIndex = -1; | |
560 | u16 freq; | |
561 | ||
562 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
563 | freq = isHt40Target ? centers.synth_center : centers.ctl_center; | |
564 | ||
565 | if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) { | |
566 | matchIndex = 0; | |
567 | } else { | |
568 | for (i = 0; (i < numChannels) && | |
569 | (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { | |
570 | if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel, | |
571 | IS_CHAN_2GHZ(chan))) { | |
572 | matchIndex = i; | |
573 | break; | |
574 | } else | |
575 | if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel, | |
576 | IS_CHAN_2GHZ(chan))) && | |
577 | (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel, | |
578 | IS_CHAN_2GHZ(chan)))) { | |
579 | lowIndex = i - 1; | |
580 | break; | |
581 | } | |
582 | } | |
583 | if ((matchIndex == -1) && (lowIndex == -1)) | |
584 | matchIndex = i - 1; | |
585 | } | |
586 | ||
587 | if (matchIndex != -1) { | |
588 | *pNewPower = powInfo[matchIndex]; | |
589 | } else { | |
590 | clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel, | |
591 | IS_CHAN_2GHZ(chan)); | |
592 | chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel, | |
593 | IS_CHAN_2GHZ(chan)); | |
594 | ||
595 | for (i = 0; i < numRates; i++) { | |
596 | pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq, | |
597 | clo, chi, | |
598 | powInfo[lowIndex].tPow2x[i], | |
599 | powInfo[lowIndex + 1].tPow2x[i]); | |
600 | } | |
601 | } | |
602 | } | |
603 | ||
604 | static u16 ath9k_hw_get_max_edge_power(u16 freq, | |
605 | struct cal_ctl_edges *pRdEdgesPower, | |
606 | bool is2GHz) | |
607 | { | |
608 | u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | |
609 | int i; | |
610 | ||
611 | for (i = 0; (i < AR5416_NUM_BAND_EDGES) && | |
612 | (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) { | |
613 | if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) { | |
614 | twiceMaxEdgePower = pRdEdgesPower[i].tPower; | |
615 | break; | |
616 | } else if ((i > 0) && | |
617 | (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, | |
618 | is2GHz))) { | |
619 | if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel, | |
620 | is2GHz) < freq && | |
621 | pRdEdgesPower[i - 1].flag) { | |
622 | twiceMaxEdgePower = | |
623 | pRdEdgesPower[i - 1].tPower; | |
624 | } | |
625 | break; | |
626 | } | |
627 | } | |
628 | ||
629 | return twiceMaxEdgePower; | |
630 | } | |
631 | ||
632 | int ath9k_hw_set_txpower(struct ath_hal *ah, | |
633 | struct ath9k_channel *chan, | |
634 | u16 cfgCtl, | |
635 | u8 twiceAntennaReduction, | |
636 | u8 twiceMaxRegulatoryPower, | |
637 | u8 powerLimit) | |
638 | { | |
639 | struct ath_hal_5416 *ahp = AH5416(ah); | |
640 | struct ar5416_eeprom *pEepData = &ahp->ah_eeprom; | |
641 | struct modal_eep_header *pModal = | |
642 | &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]); | |
643 | int16_t ratesArray[Ar5416RateSize]; | |
644 | int16_t txPowerIndexOffset = 0; | |
645 | u8 ht40PowerIncForPdadc = 2; | |
646 | int i; | |
647 | ||
648 | memset(ratesArray, 0, sizeof(ratesArray)); | |
649 | ||
650 | if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
651 | AR5416_EEP_MINOR_VER_2) { | |
652 | ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; | |
653 | } | |
654 | ||
655 | if (!ath9k_hw_set_power_per_rate_table(ah, chan, | |
656 | &ratesArray[0], cfgCtl, | |
657 | twiceAntennaReduction, | |
658 | twiceMaxRegulatoryPower, | |
659 | powerLimit)) { | |
660 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
661 | "ath9k_hw_set_txpower: unable to set " | |
662 | "tx power per rate table\n"); | |
663 | return -EIO; | |
664 | } | |
665 | ||
666 | if (!ath9k_hw_set_power_cal_table(ah, chan, &txPowerIndexOffset)) { | |
667 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, | |
668 | "ath9k_hw_set_txpower: unable to set power table\n"); | |
669 | return -EIO; | |
670 | } | |
671 | ||
672 | for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { | |
673 | ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); | |
674 | if (ratesArray[i] > AR5416_MAX_RATE_POWER) | |
675 | ratesArray[i] = AR5416_MAX_RATE_POWER; | |
676 | } | |
677 | ||
678 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
679 | for (i = 0; i < Ar5416RateSize; i++) | |
680 | ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2; | |
681 | } | |
682 | ||
683 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, | |
684 | ATH9K_POW_SM(ratesArray[rate18mb], 24) | |
685 | | ATH9K_POW_SM(ratesArray[rate12mb], 16) | |
686 | | ATH9K_POW_SM(ratesArray[rate9mb], 8) | |
687 | | ATH9K_POW_SM(ratesArray[rate6mb], 0)); | |
688 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, | |
689 | ATH9K_POW_SM(ratesArray[rate54mb], 24) | |
690 | | ATH9K_POW_SM(ratesArray[rate48mb], 16) | |
691 | | ATH9K_POW_SM(ratesArray[rate36mb], 8) | |
692 | | ATH9K_POW_SM(ratesArray[rate24mb], 0)); | |
693 | ||
694 | if (IS_CHAN_2GHZ(chan)) { | |
695 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, | |
696 | ATH9K_POW_SM(ratesArray[rate2s], 24) | |
697 | | ATH9K_POW_SM(ratesArray[rate2l], 16) | |
698 | | ATH9K_POW_SM(ratesArray[rateXr], 8) | |
699 | | ATH9K_POW_SM(ratesArray[rate1l], 0)); | |
700 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, | |
701 | ATH9K_POW_SM(ratesArray[rate11s], 24) | |
702 | | ATH9K_POW_SM(ratesArray[rate11l], 16) | |
703 | | ATH9K_POW_SM(ratesArray[rate5_5s], 8) | |
704 | | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); | |
705 | } | |
706 | ||
707 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, | |
708 | ATH9K_POW_SM(ratesArray[rateHt20_3], 24) | |
709 | | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) | |
710 | | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) | |
711 | | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); | |
712 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, | |
713 | ATH9K_POW_SM(ratesArray[rateHt20_7], 24) | |
714 | | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) | |
715 | | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) | |
716 | | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); | |
717 | ||
718 | if (IS_CHAN_HT40(chan)) { | |
719 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, | |
720 | ATH9K_POW_SM(ratesArray[rateHt40_3] + | |
721 | ht40PowerIncForPdadc, 24) | |
722 | | ATH9K_POW_SM(ratesArray[rateHt40_2] + | |
723 | ht40PowerIncForPdadc, 16) | |
724 | | ATH9K_POW_SM(ratesArray[rateHt40_1] + | |
725 | ht40PowerIncForPdadc, 8) | |
726 | | ATH9K_POW_SM(ratesArray[rateHt40_0] + | |
727 | ht40PowerIncForPdadc, 0)); | |
728 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, | |
729 | ATH9K_POW_SM(ratesArray[rateHt40_7] + | |
730 | ht40PowerIncForPdadc, 24) | |
731 | | ATH9K_POW_SM(ratesArray[rateHt40_6] + | |
732 | ht40PowerIncForPdadc, 16) | |
733 | | ATH9K_POW_SM(ratesArray[rateHt40_5] + | |
734 | ht40PowerIncForPdadc, 8) | |
735 | | ATH9K_POW_SM(ratesArray[rateHt40_4] + | |
736 | ht40PowerIncForPdadc, 0)); | |
737 | ||
738 | REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, | |
739 | ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) | |
740 | | ATH9K_POW_SM(ratesArray[rateExtCck], 16) | |
741 | | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) | |
742 | | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); | |
743 | } | |
744 | ||
745 | REG_WRITE(ah, AR_PHY_POWER_TX_SUB, | |
746 | ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6) | |
747 | | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)); | |
748 | ||
749 | i = rate6mb; | |
750 | ||
751 | if (IS_CHAN_HT40(chan)) | |
752 | i = rateHt40_0; | |
753 | else if (IS_CHAN_HT20(chan)) | |
754 | i = rateHt20_0; | |
755 | ||
756 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
757 | ah->ah_maxPowerLevel = | |
758 | ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2; | |
759 | else | |
760 | ah->ah_maxPowerLevel = ratesArray[i]; | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan) | |
766 | { | |
767 | struct modal_eep_header *pModal; | |
768 | struct ath_hal_5416 *ahp = AH5416(ah); | |
769 | struct ar5416_eeprom *eep = &ahp->ah_eeprom; | |
770 | u8 biaslevel; | |
771 | ||
772 | if (ah->ah_macVersion != AR_SREV_VERSION_9160) | |
773 | return; | |
774 | ||
775 | if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7) | |
776 | return; | |
777 | ||
778 | pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); | |
779 | ||
780 | if (pModal->xpaBiasLvl != 0xff) { | |
781 | biaslevel = pModal->xpaBiasLvl; | |
782 | } else { | |
783 | u16 resetFreqBin, freqBin, freqCount = 0; | |
784 | struct chan_centers centers; | |
785 | ||
786 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
787 | ||
788 | resetFreqBin = FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)); | |
789 | freqBin = pModal->xpaBiasLvlFreq[0] & 0xff; | |
790 | biaslevel = (u8) (pModal->xpaBiasLvlFreq[0] >> 14); | |
791 | ||
792 | freqCount++; | |
793 | ||
794 | while (freqCount < 3) { | |
795 | if (pModal->xpaBiasLvlFreq[freqCount] == 0x0) | |
796 | break; | |
797 | ||
798 | freqBin = pModal->xpaBiasLvlFreq[freqCount] & 0xff; | |
799 | if (resetFreqBin >= freqBin) { | |
800 | biaslevel = (u8)(pModal->xpaBiasLvlFreq[freqCount] >> 14); | |
801 | } else { | |
802 | break; | |
803 | } | |
804 | freqCount++; | |
805 | } | |
806 | } | |
807 | ||
808 | if (IS_CHAN_2GHZ(chan)) { | |
809 | INI_RA(&ahp->ah_iniAddac, 7, 1) = | |
810 | (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel << 3; | |
811 | } else { | |
812 | INI_RA(&ahp->ah_iniAddac, 6, 1) = | |
813 | (INI_RA(&ahp->ah_iniAddac, 6, 1) & (~0xc0)) | biaslevel << 6; | |
814 | } | |
815 | } | |
816 | ||
817 | bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah, | |
818 | struct ath9k_channel *chan, | |
819 | int16_t *ratesArray, | |
820 | u16 cfgCtl, | |
821 | u8 AntennaReduction, | |
822 | u8 twiceMaxRegulatoryPower, | |
823 | u8 powerLimit) | |
824 | { | |
825 | struct ath_hal_5416 *ahp = AH5416(ah); | |
826 | struct ar5416_eeprom *pEepData = &ahp->ah_eeprom; | |
827 | u8 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | |
828 | static const u16 tpScaleReductionTable[5] = | |
829 | { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; | |
830 | ||
831 | int i; | |
832 | int8_t twiceLargestAntenna; | |
833 | struct cal_ctl_data *rep; | |
834 | struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { | |
835 | 0, { 0, 0, 0, 0} | |
836 | }; | |
837 | struct cal_target_power_leg targetPowerOfdmExt = { | |
838 | 0, { 0, 0, 0, 0} }, targetPowerCckExt = { | |
839 | 0, { 0, 0, 0, 0 } | |
840 | }; | |
841 | struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { | |
842 | 0, {0, 0, 0, 0} | |
843 | }; | |
844 | u8 scaledPower = 0, minCtlPower, maxRegAllowedPower; | |
845 | u16 ctlModesFor11a[] = | |
846 | { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 }; | |
847 | u16 ctlModesFor11g[] = | |
848 | { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, | |
849 | CTL_2GHT40 | |
850 | }; | |
851 | u16 numCtlModes, *pCtlMode, ctlMode, freq; | |
852 | struct chan_centers centers; | |
853 | int tx_chainmask; | |
854 | u8 twiceMinEdgePower; | |
855 | ||
856 | tx_chainmask = ahp->ah_txchainmask; | |
857 | ||
858 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
859 | ||
860 | twiceLargestAntenna = max( | |
861 | pEepData->modalHeader | |
862 | [IS_CHAN_2GHZ(chan)].antennaGainCh[0], | |
863 | pEepData->modalHeader | |
864 | [IS_CHAN_2GHZ(chan)].antennaGainCh[1]); | |
865 | ||
866 | twiceLargestAntenna = max((u8)twiceLargestAntenna, | |
867 | pEepData->modalHeader | |
868 | [IS_CHAN_2GHZ(chan)].antennaGainCh[2]); | |
869 | ||
870 | twiceLargestAntenna = (int8_t)min(AntennaReduction - twiceLargestAntenna, 0); | |
871 | ||
872 | maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; | |
873 | ||
874 | if (ah->ah_tpScale != ATH9K_TP_SCALE_MAX) { | |
875 | maxRegAllowedPower -= | |
876 | (tpScaleReductionTable[(ah->ah_tpScale)] * 2); | |
877 | } | |
878 | ||
879 | scaledPower = min(powerLimit, maxRegAllowedPower); | |
880 | ||
881 | switch (ar5416_get_ntxchains(tx_chainmask)) { | |
882 | case 1: | |
883 | break; | |
884 | case 2: | |
885 | scaledPower -= | |
886 | pEepData->modalHeader[IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain; | |
887 | break; | |
888 | case 3: | |
889 | scaledPower -= | |
890 | pEepData->modalHeader[IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain; | |
891 | break; | |
892 | } | |
893 | ||
894 | scaledPower = max(0, (int32_t) scaledPower); | |
895 | ||
896 | if (IS_CHAN_2GHZ(chan)) { | |
897 | numCtlModes = ARRAY_SIZE(ctlModesFor11g) - | |
898 | SUB_NUM_CTL_MODES_AT_2G_40; | |
899 | pCtlMode = ctlModesFor11g; | |
900 | ||
901 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
902 | pEepData->calTargetPowerCck, | |
903 | AR5416_NUM_2G_CCK_TARGET_POWERS, | |
904 | &targetPowerCck, 4, false); | |
905 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
906 | pEepData->calTargetPower2G, | |
907 | AR5416_NUM_2G_20_TARGET_POWERS, | |
908 | &targetPowerOfdm, 4, false); | |
909 | ath9k_hw_get_target_powers(ah, chan, | |
910 | pEepData->calTargetPower2GHT20, | |
911 | AR5416_NUM_2G_20_TARGET_POWERS, | |
912 | &targetPowerHt20, 8, false); | |
913 | ||
914 | if (IS_CHAN_HT40(chan)) { | |
915 | numCtlModes = ARRAY_SIZE(ctlModesFor11g); | |
916 | ath9k_hw_get_target_powers(ah, chan, | |
917 | pEepData->calTargetPower2GHT40, | |
918 | AR5416_NUM_2G_40_TARGET_POWERS, | |
919 | &targetPowerHt40, 8, true); | |
920 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
921 | pEepData->calTargetPowerCck, | |
922 | AR5416_NUM_2G_CCK_TARGET_POWERS, | |
923 | &targetPowerCckExt, 4, true); | |
924 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
925 | pEepData->calTargetPower2G, | |
926 | AR5416_NUM_2G_20_TARGET_POWERS, | |
927 | &targetPowerOfdmExt, 4, true); | |
928 | } | |
929 | } else { | |
930 | numCtlModes = ARRAY_SIZE(ctlModesFor11a) - | |
931 | SUB_NUM_CTL_MODES_AT_5G_40; | |
932 | pCtlMode = ctlModesFor11a; | |
933 | ||
934 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
935 | pEepData->calTargetPower5G, | |
936 | AR5416_NUM_5G_20_TARGET_POWERS, | |
937 | &targetPowerOfdm, 4, false); | |
938 | ath9k_hw_get_target_powers(ah, chan, | |
939 | pEepData->calTargetPower5GHT20, | |
940 | AR5416_NUM_5G_20_TARGET_POWERS, | |
941 | &targetPowerHt20, 8, false); | |
942 | ||
943 | if (IS_CHAN_HT40(chan)) { | |
944 | numCtlModes = ARRAY_SIZE(ctlModesFor11a); | |
945 | ath9k_hw_get_target_powers(ah, chan, | |
946 | pEepData->calTargetPower5GHT40, | |
947 | AR5416_NUM_5G_40_TARGET_POWERS, | |
948 | &targetPowerHt40, 8, true); | |
949 | ath9k_hw_get_legacy_target_powers(ah, chan, | |
950 | pEepData->calTargetPower5G, | |
951 | AR5416_NUM_5G_20_TARGET_POWERS, | |
952 | &targetPowerOfdmExt, 4, true); | |
953 | } | |
954 | } | |
955 | ||
956 | for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { | |
957 | bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || | |
958 | (pCtlMode[ctlMode] == CTL_2GHT40); | |
959 | if (isHt40CtlMode) | |
960 | freq = centers.synth_center; | |
961 | else if (pCtlMode[ctlMode] & EXT_ADDITIVE) | |
962 | freq = centers.ext_center; | |
963 | else | |
964 | freq = centers.ctl_center; | |
965 | ||
966 | if (ar5416_get_eep_ver(ahp) == 14 && ar5416_get_eep_rev(ahp) <= 2) | |
967 | twiceMaxEdgePower = AR5416_MAX_RATE_POWER; | |
968 | ||
969 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
970 | "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, " | |
971 | "EXT_ADDITIVE %d\n", | |
972 | ctlMode, numCtlModes, isHt40CtlMode, | |
973 | (pCtlMode[ctlMode] & EXT_ADDITIVE)); | |
974 | ||
975 | for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { | |
976 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
977 | " LOOP-Ctlidx %d: cfgCtl 0x%2.2x " | |
978 | "pCtlMode 0x%2.2x ctlIndex 0x%2.2x " | |
979 | "chan %d\n", | |
980 | i, cfgCtl, pCtlMode[ctlMode], | |
981 | pEepData->ctlIndex[i], chan->channel); | |
982 | ||
983 | if ((((cfgCtl & ~CTL_MODE_M) | | |
984 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | |
985 | pEepData->ctlIndex[i]) || | |
986 | (((cfgCtl & ~CTL_MODE_M) | | |
987 | (pCtlMode[ctlMode] & CTL_MODE_M)) == | |
988 | ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { | |
989 | rep = &(pEepData->ctlData[i]); | |
990 | ||
991 | twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq, | |
992 | rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1], | |
993 | IS_CHAN_2GHZ(chan)); | |
994 | ||
995 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
996 | " MATCH-EE_IDX %d: ch %d is2 %d " | |
997 | "2xMinEdge %d chainmask %d chains %d\n", | |
998 | i, freq, IS_CHAN_2GHZ(chan), | |
999 | twiceMinEdgePower, tx_chainmask, | |
1000 | ar5416_get_ntxchains | |
1001 | (tx_chainmask)); | |
1002 | if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { | |
1003 | twiceMaxEdgePower = min(twiceMaxEdgePower, | |
1004 | twiceMinEdgePower); | |
1005 | } else { | |
1006 | twiceMaxEdgePower = twiceMinEdgePower; | |
1007 | break; | |
1008 | } | |
1009 | } | |
1010 | } | |
1011 | ||
1012 | minCtlPower = min(twiceMaxEdgePower, scaledPower); | |
1013 | ||
1014 | DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, | |
1015 | " SEL-Min ctlMode %d pCtlMode %d " | |
1016 | "2xMaxEdge %d sP %d minCtlPwr %d\n", | |
1017 | ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower, | |
1018 | scaledPower, minCtlPower); | |
1019 | ||
1020 | switch (pCtlMode[ctlMode]) { | |
1021 | case CTL_11B: | |
1022 | for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) { | |
1023 | targetPowerCck.tPow2x[i] = | |
1024 | min(targetPowerCck.tPow2x[i], | |
1025 | minCtlPower); | |
1026 | } | |
1027 | break; | |
1028 | case CTL_11A: | |
1029 | case CTL_11G: | |
1030 | for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) { | |
1031 | targetPowerOfdm.tPow2x[i] = | |
1032 | min(targetPowerOfdm.tPow2x[i], | |
1033 | minCtlPower); | |
1034 | } | |
1035 | break; | |
1036 | case CTL_5GHT20: | |
1037 | case CTL_2GHT20: | |
1038 | for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) { | |
1039 | targetPowerHt20.tPow2x[i] = | |
1040 | min(targetPowerHt20.tPow2x[i], | |
1041 | minCtlPower); | |
1042 | } | |
1043 | break; | |
1044 | case CTL_11B_EXT: | |
1045 | targetPowerCckExt.tPow2x[0] = | |
1046 | min(targetPowerCckExt.tPow2x[0], minCtlPower); | |
1047 | break; | |
1048 | case CTL_11A_EXT: | |
1049 | case CTL_11G_EXT: | |
1050 | targetPowerOfdmExt.tPow2x[0] = | |
1051 | min(targetPowerOfdmExt.tPow2x[0], minCtlPower); | |
1052 | break; | |
1053 | case CTL_5GHT40: | |
1054 | case CTL_2GHT40: | |
1055 | for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { | |
1056 | targetPowerHt40.tPow2x[i] = | |
1057 | min(targetPowerHt40.tPow2x[i], | |
1058 | minCtlPower); | |
1059 | } | |
1060 | break; | |
1061 | default: | |
1062 | break; | |
1063 | } | |
1064 | } | |
1065 | ||
1066 | ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = | |
1067 | ratesArray[rate18mb] = ratesArray[rate24mb] = | |
1068 | targetPowerOfdm.tPow2x[0]; | |
1069 | ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; | |
1070 | ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; | |
1071 | ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; | |
1072 | ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; | |
1073 | ||
1074 | for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) | |
1075 | ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; | |
1076 | ||
1077 | if (IS_CHAN_2GHZ(chan)) { | |
1078 | ratesArray[rate1l] = targetPowerCck.tPow2x[0]; | |
1079 | ratesArray[rate2s] = ratesArray[rate2l] = | |
1080 | targetPowerCck.tPow2x[1]; | |
1081 | ratesArray[rate5_5s] = ratesArray[rate5_5l] = | |
1082 | targetPowerCck.tPow2x[2]; | |
1083 | ; | |
1084 | ratesArray[rate11s] = ratesArray[rate11l] = | |
1085 | targetPowerCck.tPow2x[3]; | |
1086 | ; | |
1087 | } | |
1088 | if (IS_CHAN_HT40(chan)) { | |
1089 | for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) { | |
1090 | ratesArray[rateHt40_0 + i] = | |
1091 | targetPowerHt40.tPow2x[i]; | |
1092 | } | |
1093 | ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; | |
1094 | ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; | |
1095 | ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; | |
1096 | if (IS_CHAN_2GHZ(chan)) { | |
1097 | ratesArray[rateExtCck] = | |
1098 | targetPowerCckExt.tPow2x[0]; | |
1099 | } | |
1100 | } | |
1101 | return true; | |
1102 | } | |
1103 | ||
1104 | bool ath9k_hw_set_power_cal_table(struct ath_hal *ah, | |
1105 | struct ath9k_channel *chan, | |
1106 | int16_t *pTxPowerIndexOffset) | |
1107 | { | |
1108 | struct ath_hal_5416 *ahp = AH5416(ah); | |
1109 | struct ar5416_eeprom *pEepData = &ahp->ah_eeprom; | |
1110 | struct cal_data_per_freq *pRawDataset; | |
1111 | u8 *pCalBChans = NULL; | |
1112 | u16 pdGainOverlap_t2; | |
1113 | static u8 pdadcValues[AR5416_NUM_PDADC_VALUES]; | |
1114 | u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK]; | |
1115 | u16 numPiers, i, j; | |
1116 | int16_t tMinCalPower; | |
1117 | u16 numXpdGain, xpdMask; | |
1118 | u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 }; | |
1119 | u32 reg32, regOffset, regChainOffset; | |
1120 | int16_t modalIdx; | |
1121 | ||
1122 | modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0; | |
1123 | xpdMask = pEepData->modalHeader[modalIdx].xpdGain; | |
1124 | ||
1125 | if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
1126 | AR5416_EEP_MINOR_VER_2) { | |
1127 | pdGainOverlap_t2 = | |
1128 | pEepData->modalHeader[modalIdx].pdGainOverlap; | |
1129 | } else { | |
1130 | pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), | |
1131 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); | |
1132 | } | |
1133 | ||
1134 | if (IS_CHAN_2GHZ(chan)) { | |
1135 | pCalBChans = pEepData->calFreqPier2G; | |
1136 | numPiers = AR5416_NUM_2G_CAL_PIERS; | |
1137 | } else { | |
1138 | pCalBChans = pEepData->calFreqPier5G; | |
1139 | numPiers = AR5416_NUM_5G_CAL_PIERS; | |
1140 | } | |
1141 | ||
1142 | numXpdGain = 0; | |
1143 | ||
1144 | for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { | |
1145 | if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { | |
1146 | if (numXpdGain >= AR5416_NUM_PD_GAINS) | |
1147 | break; | |
1148 | xpdGainValues[numXpdGain] = | |
1149 | (u16)(AR5416_PD_GAINS_IN_MASK - i); | |
1150 | numXpdGain++; | |
1151 | } | |
1152 | } | |
1153 | ||
1154 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, | |
1155 | (numXpdGain - 1) & 0x3); | |
1156 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, | |
1157 | xpdGainValues[0]); | |
1158 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, | |
1159 | xpdGainValues[1]); | |
1160 | REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, | |
1161 | xpdGainValues[2]); | |
1162 | ||
1163 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
1164 | if (AR_SREV_5416_V20_OR_LATER(ah) && | |
1165 | (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) && | |
1166 | (i != 0)) { | |
1167 | regChainOffset = (i == 1) ? 0x2000 : 0x1000; | |
1168 | } else | |
1169 | regChainOffset = i * 0x1000; | |
1170 | ||
1171 | if (pEepData->baseEepHeader.txMask & (1 << i)) { | |
1172 | if (IS_CHAN_2GHZ(chan)) | |
1173 | pRawDataset = pEepData->calPierData2G[i]; | |
1174 | else | |
1175 | pRawDataset = pEepData->calPierData5G[i]; | |
1176 | ||
1177 | ath9k_hw_get_gain_boundaries_pdadcs(ah, chan, | |
1178 | pRawDataset, pCalBChans, | |
1179 | numPiers, pdGainOverlap_t2, | |
1180 | &tMinCalPower, gainBoundaries, | |
1181 | pdadcValues, numXpdGain); | |
1182 | ||
1183 | if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { | |
1184 | REG_WRITE(ah, | |
1185 | AR_PHY_TPCRG5 + regChainOffset, | |
1186 | SM(pdGainOverlap_t2, | |
1187 | AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | |
1188 | | SM(gainBoundaries[0], | |
1189 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | |
1190 | | SM(gainBoundaries[1], | |
1191 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | |
1192 | | SM(gainBoundaries[2], | |
1193 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | |
1194 | | SM(gainBoundaries[3], | |
1195 | AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); | |
1196 | } | |
1197 | ||
1198 | regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; | |
1199 | for (j = 0; j < 32; j++) { | |
1200 | reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) | | |
1201 | ((pdadcValues[4 * j + 1] & 0xFF) << 8) | | |
1202 | ((pdadcValues[4 * j + 2] & 0xFF) << 16) | | |
1203 | ((pdadcValues[4 * j + 3] & 0xFF) << 24); | |
1204 | REG_WRITE(ah, regOffset, reg32); | |
1205 | ||
04bd4638 | 1206 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, |
f1dc5600 S |
1207 | "PDADC (%d,%4x): %4.4x %8.8x\n", |
1208 | i, regChainOffset, regOffset, | |
1209 | reg32); | |
04bd4638 | 1210 | DPRINTF(ah->ah_sc, ATH_DBG_REG_IO, |
f1dc5600 S |
1211 | "PDADC: Chain %d | PDADC %3d Value %3d | " |
1212 | "PDADC %3d Value %3d | PDADC %3d Value %3d | " | |
1213 | "PDADC %3d Value %3d |\n", | |
1214 | i, 4 * j, pdadcValues[4 * j], | |
1215 | 4 * j + 1, pdadcValues[4 * j + 1], | |
1216 | 4 * j + 2, pdadcValues[4 * j + 2], | |
1217 | 4 * j + 3, | |
1218 | pdadcValues[4 * j + 3]); | |
1219 | ||
1220 | regOffset += 4; | |
1221 | } | |
1222 | } | |
1223 | } | |
1224 | ||
1225 | *pTxPowerIndexOffset = 0; | |
1226 | ||
1227 | return true; | |
1228 | } | |
1229 | ||
1230 | /* XXX: Clean me up, make me more legible */ | |
1231 | bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah, | |
1232 | struct ath9k_channel *chan) | |
1233 | { | |
1234 | struct modal_eep_header *pModal; | |
1235 | struct ath_hal_5416 *ahp = AH5416(ah); | |
1236 | struct ar5416_eeprom *eep = &ahp->ah_eeprom; | |
1237 | int i, regChainOffset; | |
1238 | u8 txRxAttenLocal; | |
1239 | u16 ant_config; | |
1240 | ||
1241 | pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); | |
1242 | ||
1243 | txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44; | |
1244 | ||
4d3601b2 | 1245 | ath9k_hw_get_eeprom_antenna_cfg(ah, chan, 0, &ant_config); |
f1dc5600 S |
1246 | REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); |
1247 | ||
1248 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
1249 | if (AR_SREV_9280(ah)) { | |
1250 | if (i >= 2) | |
1251 | break; | |
1252 | } | |
1253 | ||
1254 | if (AR_SREV_5416_V20_OR_LATER(ah) && | |
1255 | (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5) | |
1256 | && (i != 0)) | |
1257 | regChainOffset = (i == 1) ? 0x2000 : 0x1000; | |
1258 | else | |
1259 | regChainOffset = i * 0x1000; | |
1260 | ||
1261 | REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, | |
1262 | pModal->antCtrlChain[i]); | |
1263 | ||
1264 | REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, | |
1265 | (REG_READ(ah, | |
1266 | AR_PHY_TIMING_CTRL4(0) + | |
1267 | regChainOffset) & | |
1268 | ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | | |
1269 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | | |
1270 | SM(pModal->iqCalICh[i], | |
1271 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | | |
1272 | SM(pModal->iqCalQCh[i], | |
1273 | AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); | |
1274 | ||
1275 | if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) { | |
1276 | if ((eep->baseEepHeader.version & | |
1277 | AR5416_EEP_VER_MINOR_MASK) >= | |
1278 | AR5416_EEP_MINOR_VER_3) { | |
1279 | txRxAttenLocal = pModal->txRxAttenCh[i]; | |
1280 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
1281 | REG_RMW_FIELD(ah, | |
1282 | AR_PHY_GAIN_2GHZ + | |
1283 | regChainOffset, | |
1284 | AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, | |
1285 | pModal-> | |
1286 | bswMargin[i]); | |
1287 | REG_RMW_FIELD(ah, | |
1288 | AR_PHY_GAIN_2GHZ + | |
1289 | regChainOffset, | |
1290 | AR_PHY_GAIN_2GHZ_XATTEN1_DB, | |
1291 | pModal-> | |
1292 | bswAtten[i]); | |
1293 | REG_RMW_FIELD(ah, | |
1294 | AR_PHY_GAIN_2GHZ + | |
1295 | regChainOffset, | |
1296 | AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, | |
1297 | pModal-> | |
1298 | xatten2Margin[i]); | |
1299 | REG_RMW_FIELD(ah, | |
1300 | AR_PHY_GAIN_2GHZ + | |
1301 | regChainOffset, | |
1302 | AR_PHY_GAIN_2GHZ_XATTEN2_DB, | |
1303 | pModal-> | |
1304 | xatten2Db[i]); | |
1305 | } else { | |
1306 | REG_WRITE(ah, | |
1307 | AR_PHY_GAIN_2GHZ + | |
1308 | regChainOffset, | |
1309 | (REG_READ(ah, | |
1310 | AR_PHY_GAIN_2GHZ + | |
1311 | regChainOffset) & | |
1312 | ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) | |
1313 | | SM(pModal-> | |
1314 | bswMargin[i], | |
1315 | AR_PHY_GAIN_2GHZ_BSW_MARGIN)); | |
1316 | REG_WRITE(ah, | |
1317 | AR_PHY_GAIN_2GHZ + | |
1318 | regChainOffset, | |
1319 | (REG_READ(ah, | |
1320 | AR_PHY_GAIN_2GHZ + | |
1321 | regChainOffset) & | |
1322 | ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) | |
1323 | | SM(pModal->bswAtten[i], | |
1324 | AR_PHY_GAIN_2GHZ_BSW_ATTEN)); | |
1325 | } | |
1326 | } | |
1327 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
1328 | REG_RMW_FIELD(ah, | |
1329 | AR_PHY_RXGAIN + | |
1330 | regChainOffset, | |
1331 | AR9280_PHY_RXGAIN_TXRX_ATTEN, | |
1332 | txRxAttenLocal); | |
1333 | REG_RMW_FIELD(ah, | |
1334 | AR_PHY_RXGAIN + | |
1335 | regChainOffset, | |
1336 | AR9280_PHY_RXGAIN_TXRX_MARGIN, | |
1337 | pModal->rxTxMarginCh[i]); | |
1338 | } else { | |
1339 | REG_WRITE(ah, | |
1340 | AR_PHY_RXGAIN + regChainOffset, | |
1341 | (REG_READ(ah, | |
1342 | AR_PHY_RXGAIN + | |
1343 | regChainOffset) & | |
1344 | ~AR_PHY_RXGAIN_TXRX_ATTEN) | | |
1345 | SM(txRxAttenLocal, | |
1346 | AR_PHY_RXGAIN_TXRX_ATTEN)); | |
1347 | REG_WRITE(ah, | |
1348 | AR_PHY_GAIN_2GHZ + | |
1349 | regChainOffset, | |
1350 | (REG_READ(ah, | |
1351 | AR_PHY_GAIN_2GHZ + | |
1352 | regChainOffset) & | |
1353 | ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) | | |
1354 | SM(pModal->rxTxMarginCh[i], | |
1355 | AR_PHY_GAIN_2GHZ_RXTX_MARGIN)); | |
1356 | } | |
1357 | } | |
1358 | } | |
1359 | ||
1360 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
1361 | if (IS_CHAN_2GHZ(chan)) { | |
1362 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, | |
1363 | AR_AN_RF2G1_CH0_OB, | |
1364 | AR_AN_RF2G1_CH0_OB_S, | |
1365 | pModal->ob); | |
1366 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, | |
1367 | AR_AN_RF2G1_CH0_DB, | |
1368 | AR_AN_RF2G1_CH0_DB_S, | |
1369 | pModal->db); | |
1370 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, | |
1371 | AR_AN_RF2G1_CH1_OB, | |
1372 | AR_AN_RF2G1_CH1_OB_S, | |
1373 | pModal->ob_ch1); | |
1374 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, | |
1375 | AR_AN_RF2G1_CH1_DB, | |
1376 | AR_AN_RF2G1_CH1_DB_S, | |
1377 | pModal->db_ch1); | |
1378 | } else { | |
1379 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, | |
1380 | AR_AN_RF5G1_CH0_OB5, | |
1381 | AR_AN_RF5G1_CH0_OB5_S, | |
1382 | pModal->ob); | |
1383 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, | |
1384 | AR_AN_RF5G1_CH0_DB5, | |
1385 | AR_AN_RF5G1_CH0_DB5_S, | |
1386 | pModal->db); | |
1387 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, | |
1388 | AR_AN_RF5G1_CH1_OB5, | |
1389 | AR_AN_RF5G1_CH1_OB5_S, | |
1390 | pModal->ob_ch1); | |
1391 | ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, | |
1392 | AR_AN_RF5G1_CH1_DB5, | |
1393 | AR_AN_RF5G1_CH1_DB5_S, | |
1394 | pModal->db_ch1); | |
1395 | } | |
1396 | ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, | |
1397 | AR_AN_TOP2_XPABIAS_LVL, | |
1398 | AR_AN_TOP2_XPABIAS_LVL_S, | |
1399 | pModal->xpaBiasLvl); | |
1400 | ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, | |
1401 | AR_AN_TOP2_LOCALBIAS, | |
1402 | AR_AN_TOP2_LOCALBIAS_S, | |
1403 | pModal->local_bias); | |
1404 | DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "ForceXPAon: %d\n", | |
1405 | pModal->force_xpaon); | |
1406 | REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, | |
1407 | pModal->force_xpaon); | |
1408 | } | |
1409 | ||
1410 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, | |
1411 | pModal->switchSettling); | |
1412 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, | |
1413 | pModal->adcDesiredSize); | |
1414 | ||
1415 | if (!AR_SREV_9280_10_OR_LATER(ah)) | |
1416 | REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, | |
1417 | AR_PHY_DESIRED_SZ_PGA, | |
1418 | pModal->pgaDesiredSize); | |
1419 | ||
1420 | REG_WRITE(ah, AR_PHY_RF_CTL4, | |
1421 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) | |
1422 | | SM(pModal->txEndToXpaOff, | |
1423 | AR_PHY_RF_CTL4_TX_END_XPAB_OFF) | |
1424 | | SM(pModal->txFrameToXpaOn, | |
1425 | AR_PHY_RF_CTL4_FRAME_XPAA_ON) | |
1426 | | SM(pModal->txFrameToXpaOn, | |
1427 | AR_PHY_RF_CTL4_FRAME_XPAB_ON)); | |
1428 | ||
1429 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, | |
1430 | pModal->txEndToRxOn); | |
1431 | if (AR_SREV_9280_10_OR_LATER(ah)) { | |
1432 | REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, | |
1433 | pModal->thresh62); | |
1434 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, | |
1435 | AR_PHY_EXT_CCA0_THRESH62, | |
1436 | pModal->thresh62); | |
1437 | } else { | |
1438 | REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, | |
1439 | pModal->thresh62); | |
1440 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, | |
1441 | AR_PHY_EXT_CCA_THRESH62, | |
1442 | pModal->thresh62); | |
1443 | } | |
1444 | ||
1445 | if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
1446 | AR5416_EEP_MINOR_VER_2) { | |
1447 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, | |
1448 | AR_PHY_TX_END_DATA_START, | |
1449 | pModal->txFrameToDataStart); | |
1450 | REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, | |
1451 | pModal->txFrameToPaOn); | |
1452 | } | |
1453 | ||
1454 | if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >= | |
1455 | AR5416_EEP_MINOR_VER_3) { | |
1456 | if (IS_CHAN_HT40(chan)) | |
1457 | REG_RMW_FIELD(ah, AR_PHY_SETTLING, | |
1458 | AR_PHY_SETTLING_SWITCH, | |
1459 | pModal->swSettleHt40); | |
1460 | } | |
1461 | ||
1462 | return true; | |
1463 | } | |
1464 | ||
1465 | int ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah, | |
1466 | struct ath9k_channel *chan, | |
1467 | u8 index, u16 *config) | |
1468 | { | |
1469 | struct ath_hal_5416 *ahp = AH5416(ah); | |
1470 | struct ar5416_eeprom *eep = &ahp->ah_eeprom; | |
1471 | struct modal_eep_header *pModal = | |
1472 | &(eep->modalHeader[IS_CHAN_2GHZ(chan)]); | |
1473 | struct base_eep_header *pBase = &eep->baseEepHeader; | |
1474 | ||
1475 | switch (index) { | |
1476 | case 0: | |
1477 | *config = pModal->antCtrlCommon & 0xFFFF; | |
1478 | return 0; | |
1479 | case 1: | |
1480 | if (pBase->version >= 0x0E0D) { | |
1481 | if (pModal->useAnt1) { | |
1482 | *config = | |
1483 | ((pModal->antCtrlCommon & 0xFFFF0000) >> 16); | |
1484 | return 0; | |
1485 | } | |
1486 | } | |
1487 | break; | |
1488 | default: | |
1489 | break; | |
1490 | } | |
1491 | ||
1492 | return -EINVAL; | |
1493 | } | |
1494 | ||
1495 | u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah, | |
1496 | enum ieee80211_band freq_band) | |
1497 | { | |
1498 | struct ath_hal_5416 *ahp = AH5416(ah); | |
1499 | struct ar5416_eeprom *eep = &ahp->ah_eeprom; | |
1500 | struct modal_eep_header *pModal = | |
1501 | &(eep->modalHeader[IEEE80211_BAND_5GHZ == freq_band]); | |
1502 | struct base_eep_header *pBase = &eep->baseEepHeader; | |
1503 | u8 num_ant_config; | |
1504 | ||
1505 | num_ant_config = 1; | |
1506 | ||
1507 | if (pBase->version >= 0x0E0D) | |
1508 | if (pModal->useAnt1) | |
1509 | num_ant_config += 1; | |
1510 | ||
1511 | return num_ant_config; | |
1512 | } | |
1513 | ||
1514 | u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz) | |
1515 | { | |
1516 | struct ath_hal_5416 *ahp = AH5416(ah); | |
1517 | struct ar5416_eeprom *eep = | |
1518 | (struct ar5416_eeprom *) &ahp->ah_eeprom; | |
1519 | u16 spur_val = AR_NO_SPUR; | |
1520 | ||
1521 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | |
1522 | "Getting spur idx %d is2Ghz. %d val %x\n", | |
1523 | i, is2GHz, ah->ah_config.spurchans[i][is2GHz]); | |
1524 | ||
1525 | switch (ah->ah_config.spurmode) { | |
1526 | case SPUR_DISABLE: | |
1527 | break; | |
1528 | case SPUR_ENABLE_IOCTL: | |
1529 | spur_val = ah->ah_config.spurchans[i][is2GHz]; | |
1530 | DPRINTF(ah->ah_sc, ATH_DBG_ANI, | |
1531 | "Getting spur val from new loc. %d\n", spur_val); | |
1532 | break; | |
1533 | case SPUR_ENABLE_EEPROM: | |
1534 | spur_val = eep->modalHeader[is2GHz].spurChans[i].spurChan; | |
1535 | break; | |
1536 | ||
1537 | } | |
1538 | ||
1539 | return spur_val; | |
1540 | } | |
1541 | ||
1542 | u32 ath9k_hw_get_eeprom(struct ath_hal *ah, | |
1543 | enum eeprom_param param) | |
1544 | { | |
1545 | struct ath_hal_5416 *ahp = AH5416(ah); | |
1546 | struct ar5416_eeprom *eep = &ahp->ah_eeprom; | |
1547 | struct modal_eep_header *pModal = eep->modalHeader; | |
1548 | struct base_eep_header *pBase = &eep->baseEepHeader; | |
1549 | ||
1550 | switch (param) { | |
1551 | case EEP_NFTHRESH_5: | |
f9bbf431 | 1552 | return pModal[0].noiseFloorThreshCh[0]; |
f1dc5600 | 1553 | case EEP_NFTHRESH_2: |
f9bbf431 | 1554 | return pModal[1].noiseFloorThreshCh[0]; |
f1dc5600 S |
1555 | case AR_EEPROM_MAC(0): |
1556 | return pBase->macAddr[0] << 8 | pBase->macAddr[1]; | |
1557 | case AR_EEPROM_MAC(1): | |
1558 | return pBase->macAddr[2] << 8 | pBase->macAddr[3]; | |
1559 | case AR_EEPROM_MAC(2): | |
1560 | return pBase->macAddr[4] << 8 | pBase->macAddr[5]; | |
1561 | case EEP_REG_0: | |
1562 | return pBase->regDmn[0]; | |
1563 | case EEP_REG_1: | |
1564 | return pBase->regDmn[1]; | |
1565 | case EEP_OP_CAP: | |
1566 | return pBase->deviceCap; | |
1567 | case EEP_OP_MODE: | |
1568 | return pBase->opCapFlags; | |
1569 | case EEP_RF_SILENT: | |
1570 | return pBase->rfSilent; | |
1571 | case EEP_OB_5: | |
1572 | return pModal[0].ob; | |
1573 | case EEP_DB_5: | |
1574 | return pModal[0].db; | |
1575 | case EEP_OB_2: | |
1576 | return pModal[1].ob; | |
1577 | case EEP_DB_2: | |
1578 | return pModal[1].db; | |
1579 | case EEP_MINOR_REV: | |
1580 | return pBase->version & AR5416_EEP_VER_MINOR_MASK; | |
1581 | case EEP_TX_MASK: | |
1582 | return pBase->txMask; | |
1583 | case EEP_RX_MASK: | |
1584 | return pBase->rxMask; | |
9f804202 SB |
1585 | case EEP_RXGAIN_TYPE: |
1586 | return pBase->rxGainType; | |
1587 | case EEP_TXGAIN_TYPE: | |
1588 | return pBase->txGainType; | |
1589 | ||
f1dc5600 S |
1590 | default: |
1591 | return 0; | |
1592 | } | |
1593 | } | |
1594 | ||
1595 | int ath9k_hw_eeprom_attach(struct ath_hal *ah) | |
1596 | { | |
1597 | int status; | |
1598 | ||
1599 | if (ath9k_hw_use_flash(ah)) | |
1600 | ath9k_hw_flash_map(ah); | |
1601 | ||
1602 | if (!ath9k_hw_fill_eeprom(ah)) | |
1603 | return -EIO; | |
1604 | ||
1605 | status = ath9k_hw_check_eeprom(ah); | |
1606 | ||
1607 | return status; | |
1608 | } |