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ath9k: Enable Fractional N mode
[deliverable/linux.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
5f8e077c
LR		 29/* We use the hw_value as an index into our private channel structure */
30
31#define CHAN2G(_freq, _idx) { \
32 .center_freq = (_freq), \
33 .hw_value = (_idx), \
34 .max_power = 30, \
35}
36
37#define CHAN5G(_freq, _idx) { \
38 .band = IEEE80211_BAND_5GHZ, \
39 .center_freq = (_freq), \
40 .hw_value = (_idx), \
41 .max_power = 30, \
42}
43
44/* Some 2 GHz radios are actually tunable on 2312-2732
45 * on 5 MHz steps, we support the channels which we know
46 * we have calibration data for all cards though to make
47 * this static */
48static struct ieee80211_channel ath9k_2ghz_chantable[] = {
49 CHAN2G(2412, 0), /* Channel 1 */
50 CHAN2G(2417, 1), /* Channel 2 */
51 CHAN2G(2422, 2), /* Channel 3 */
52 CHAN2G(2427, 3), /* Channel 4 */
53 CHAN2G(2432, 4), /* Channel 5 */
54 CHAN2G(2437, 5), /* Channel 6 */
55 CHAN2G(2442, 6), /* Channel 7 */
56 CHAN2G(2447, 7), /* Channel 8 */
57 CHAN2G(2452, 8), /* Channel 9 */
58 CHAN2G(2457, 9), /* Channel 10 */
59 CHAN2G(2462, 10), /* Channel 11 */
60 CHAN2G(2467, 11), /* Channel 12 */
61 CHAN2G(2472, 12), /* Channel 13 */
62 CHAN2G(2484, 13), /* Channel 14 */
63};
64
65/* Some 5 GHz radios are actually tunable on XXXX-YYYY
66 * on 5 MHz steps, we support the channels which we know
67 * we have calibration data for all cards though to make
68 * this static */
69static struct ieee80211_channel ath9k_5ghz_chantable[] = {
70 /* _We_ call this UNII 1 */
71 CHAN5G(5180, 14), /* Channel 36 */
72 CHAN5G(5200, 15), /* Channel 40 */
73 CHAN5G(5220, 16), /* Channel 44 */
74 CHAN5G(5240, 17), /* Channel 48 */
75 /* _We_ call this UNII 2 */
76 CHAN5G(5260, 18), /* Channel 52 */
77 CHAN5G(5280, 19), /* Channel 56 */
78 CHAN5G(5300, 20), /* Channel 60 */
79 CHAN5G(5320, 21), /* Channel 64 */
80 /* _We_ call this "Middle band" */
81 CHAN5G(5500, 22), /* Channel 100 */
82 CHAN5G(5520, 23), /* Channel 104 */
83 CHAN5G(5540, 24), /* Channel 108 */
84 CHAN5G(5560, 25), /* Channel 112 */
85 CHAN5G(5580, 26), /* Channel 116 */
86 CHAN5G(5600, 27), /* Channel 120 */
87 CHAN5G(5620, 28), /* Channel 124 */
88 CHAN5G(5640, 29), /* Channel 128 */
89 CHAN5G(5660, 30), /* Channel 132 */
90 CHAN5G(5680, 31), /* Channel 136 */
91 CHAN5G(5700, 32), /* Channel 140 */
92 /* _We_ call this UNII 3 */
93 CHAN5G(5745, 33), /* Channel 149 */
94 CHAN5G(5765, 34), /* Channel 153 */
95 CHAN5G(5785, 35), /* Channel 157 */
96 CHAN5G(5805, 36), /* Channel 161 */
97 CHAN5G(5825, 37), /* Channel 165 */
98};
99
ce111bad
LR		 100static void ath_cache_conf_rate(struct ath_softc *sc,
101 struct ieee80211_conf *conf)
ff37e337 102{
030bb495
LR		 103 switch (conf->channel->band) {
104 case IEEE80211_BAND_2GHZ:
105 if (conf_is_ht20(conf))
106 sc->cur_rate_table =
107 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
108 else if (conf_is_ht40_minus(conf))
109 sc->cur_rate_table =
110 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
111 else if (conf_is_ht40_plus(conf))
112 sc->cur_rate_table =
113 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 114 else
030bb495
LR		 115 sc->cur_rate_table =
116 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 117 break;
118 case IEEE80211_BAND_5GHZ:
119 if (conf_is_ht20(conf))
120 sc->cur_rate_table =
121 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
122 else if (conf_is_ht40_minus(conf))
123 sc->cur_rate_table =
124 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
125 else if (conf_is_ht40_plus(conf))
126 sc->cur_rate_table =
127 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
128 else
96742256
LR		 129 sc->cur_rate_table =
130 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 131 break;
132 default:
ce111bad 133 BUG_ON(1);
030bb495
LR		 134 break;
135 }
ff37e337
S		 136}
137
138static void ath_update_txpow(struct ath_softc *sc)
139{
cbe61d8a 140 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 141 u32 txpow;
142
17d7904d
S		 143 if (sc->curtxpow != sc->config.txpowlimit) {
144 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 145 /* read back in case value is clamped */
146 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 147 sc->curtxpow = txpow;
ff37e337
S		 148 }
149}
150
151static u8 parse_mpdudensity(u8 mpdudensity)
152{
153 /*
154 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
155 * 0 for no restriction
156 * 1 for 1/4 us
157 * 2 for 1/2 us
158 * 3 for 1 us
159 * 4 for 2 us
160 * 5 for 4 us
161 * 6 for 8 us
162 * 7 for 16 us
163 */
164 switch (mpdudensity) {
165 case 0:
166 return 0;
167 case 1:
168 case 2:
169 case 3:
170 /* Our lower layer calculations limit our precision to
171 1 microsecond */
172 return 1;
173 case 4:
174 return 2;
175 case 5:
176 return 4;
177 case 6:
178 return 8;
179 case 7:
180 return 16;
181 default:
182 return 0;
183 }
184}
185
186static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
187{
188 struct ath_rate_table *rate_table = NULL;
189 struct ieee80211_supported_band *sband;
190 struct ieee80211_rate *rate;
191 int i, maxrates;
192
193 switch (band) {
194 case IEEE80211_BAND_2GHZ:
195 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
196 break;
197 case IEEE80211_BAND_5GHZ:
198 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
199 break;
200 default:
201 break;
202 }
203
204 if (rate_table == NULL)
205 return;
206
207 sband = &sc->sbands[band];
208 rate = sc->rates[band];
209
210 if (rate_table->rate_cnt > ATH_RATE_MAX)
211 maxrates = ATH_RATE_MAX;
212 else
213 maxrates = rate_table->rate_cnt;
214
215 for (i = 0; i < maxrates; i++) {
216 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
217 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 218 if (rate_table->info[i].short_preamble) {
219 rate[i].hw_value_short = rate_table->info[i].ratecode |
220 rate_table->info[i].short_preamble;
221 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
222 }
ff37e337 223 sband->n_bitrates++;
f46730d1 224
04bd4638
S		 225 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
226 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 227 }
228}
229
ff37e337
S		 230/*
231 * Set/change channels. If the channel is really being changed, it's done
232 * by reseting the chip. To accomplish this we must first cleanup any pending
233 * DMA, then restart stuff.
234*/
235static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
236{
cbe61d8a 237 struct ath_hw *ah = sc->sc_ah;
ff37e337 238 bool fastcc = true, stopped;
030bb495 239 struct ieee80211_hw *hw = sc->hw;
ae8d2858
LR		 240 struct ieee80211_channel *channel = hw->conf.channel;
241 int r;
ff37e337
S		 242
243 if (sc->sc_flags & SC_OP_INVALID)
244 return -EIO;
245
3cbb5dd7
VN		 246 ath9k_ps_wakeup(sc);
247
c0d7c7af
LR		 248 /*
249 * This is only performed if the channel settings have
250 * actually changed.
251 *
252 * To switch channels clear any pending DMA operations;
253 * wait long enough for the RX fifo to drain, reset the
254 * hardware at the new frequency, and then re-enable
255 * the relevant bits of the h/w.
256 */
257 ath9k_hw_set_interrupts(ah, 0);
043a0405 258 ath_drain_all_txq(sc, false);
c0d7c7af 259 stopped = ath_stoprecv(sc);
ff37e337 260
c0d7c7af
LR		 261 /* XXX: do not flush receive queue here. We don't want
262 * to flush data frames already in queue because of
263 * changing channel. */
ff37e337 264
c0d7c7af
LR		 265 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
266 fastcc = false;
267
268 DPRINTF(sc, ATH_DBG_CONFIG,
269 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 270 sc->sc_ah->curchan->channel,
c0d7c7af 271 channel->center_freq, sc->tx_chan_width);
ff37e337 272
c0d7c7af
LR		 273 spin_lock_bh(&sc->sc_resetlock);
274
275 r = ath9k_hw_reset(ah, hchan, fastcc);
276 if (r) {
277 DPRINTF(sc, ATH_DBG_FATAL,
278 "Unable to reset channel (%u Mhz) "
279 "reset status %u\n",
280 channel->center_freq, r);
281 spin_unlock_bh(&sc->sc_resetlock);
282 return r;
ff37e337 283 }
c0d7c7af
LR		 284 spin_unlock_bh(&sc->sc_resetlock);
285
286 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
287 sc->sc_flags &= ~SC_OP_FULL_RESET;
288
289 if (ath_startrecv(sc) != 0) {
290 DPRINTF(sc, ATH_DBG_FATAL,
291 "Unable to restart recv logic\n");
292 return -EIO;
293 }
294
295 ath_cache_conf_rate(sc, &hw->conf);
296 ath_update_txpow(sc);
17d7904d 297 ath9k_hw_set_interrupts(ah, sc->imask);
3cbb5dd7 298 ath9k_ps_restore(sc);
ff37e337
S		 299 return 0;
300}
301
302/*
303 * This routine performs the periodic noise floor calibration function
304 * that is used to adjust and optimize the chip performance. This
305 * takes environmental changes (location, temperature) into account.
306 * When the task is complete, it reschedules itself depending on the
307 * appropriate interval that was calculated.
308 */
309static void ath_ani_calibrate(unsigned long data)
310{
311 struct ath_softc *sc;
cbe61d8a 312 struct ath_hw *ah;
ff37e337
S		 313 bool longcal = false;
314 bool shortcal = false;
315 bool aniflag = false;
316 unsigned int timestamp = jiffies_to_msecs(jiffies);
317 u32 cal_interval;
318
319 sc = (struct ath_softc *)data;
320 ah = sc->sc_ah;
321
322 /*
323 * don't calibrate when we're scanning.
324 * we are most likely not on our home channel.
325 */
b77f483f 326 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
ff37e337
S		 327 return;
328
329 /* Long calibration runs independently of short calibration. */
17d7904d 330 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 331 longcal = true;
04bd4638 332 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 333 sc->ani.longcal_timer = timestamp;
ff37e337
S		 334 }
335
17d7904d
S		 336 /* Short calibration applies only while caldone is false */
337 if (!sc->ani.caldone) {
338 if ((timestamp - sc->ani.shortcal_timer) >=
ff37e337
S		 339 ATH_SHORT_CALINTERVAL) {
340 shortcal = true;
04bd4638 341 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 342 sc->ani.shortcal_timer = timestamp;
343 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 344 }
345 } else {
17d7904d 346 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 347 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 348 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
349 if (sc->ani.caldone)
350 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 351 }
352 }
353
354 /* Verify whether we must check ANI */
17d7904d 355 if ((timestamp - sc->ani.checkani_timer) >=
ff37e337
S		 356 ATH_ANI_POLLINTERVAL) {
357 aniflag = true;
17d7904d 358 sc->ani.checkani_timer = timestamp;
ff37e337
S		 359 }
360
361 /* Skip all processing if there's nothing to do. */
362 if (longcal || shortcal || aniflag) {
363 /* Call ANI routine if necessary */
364 if (aniflag)
17d7904d 365 ath9k_hw_ani_monitor(ah, &sc->nodestats,
2660b81a 366 ah->curchan);
ff37e337
S		 367
368 /* Perform calibration if necessary */
369 if (longcal || shortcal) {
370 bool iscaldone = false;
371
2660b81a 372 if (ath9k_hw_calibrate(ah, ah->curchan,
17d7904d 373 sc->rx_chainmask, longcal,
ff37e337
S		 374 &iscaldone)) {
375 if (longcal)
17d7904d 376 sc->ani.noise_floor =
ff37e337 377 ath9k_hw_getchan_noise(ah,
2660b81a 378 ah->curchan);
ff37e337
S		 379
380 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 381 "calibrate chan %u/%x nf: %d\n",
2660b81a
S		 382 ah->curchan->channel,
383 ah->curchan->channelFlags,
17d7904d 384 sc->ani.noise_floor);
ff37e337
S		 385 } else {
386 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 387 "calibrate chan %u/%x failed\n",
2660b81a
S		 388 ah->curchan->channel,
389 ah->curchan->channelFlags);
ff37e337 390 }
17d7904d 391 sc->ani.caldone = iscaldone;
ff37e337
S		 392 }
393 }
394
395 /*
396 * Set timer interval based on previous results.
397 * The interval must be the shortest necessary to satisfy ANI,
398 * short calibration and long calibration.
399 */
aac9207e 400 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 401 if (sc->sc_ah->config.enable_ani)
aac9207e 402 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 403 if (!sc->ani.caldone)
ff37e337
S		 404 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
405
17d7904d 406 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 407}
408
409/*
410 * Update tx/rx chainmask. For legacy association,
411 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 412 * the chainmask configuration, for bt coexistence, use
413 * the chainmask configuration even in legacy mode.
ff37e337
S		 414 */
415static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
416{
417 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
c97c92d9 418 if (is_ht ||
2660b81a
S		 419 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
420 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
421 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 422 } else {
17d7904d
S		 423 sc->tx_chainmask = 1;
424 sc->rx_chainmask = 1;
ff37e337
S		 425 }
426
04bd4638 427 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 428 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 429}
430
431static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
432{
433 struct ath_node *an;
434
435 an = (struct ath_node *)sta->drv_priv;
436
437 if (sc->sc_flags & SC_OP_TXAGGR)
438 ath_tx_node_init(sc, an);
439
440 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
441 sta->ht_cap.ampdu_factor);
442 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
443}
444
445static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
446{
447 struct ath_node *an = (struct ath_node *)sta->drv_priv;
448
449 if (sc->sc_flags & SC_OP_TXAGGR)
450 ath_tx_node_cleanup(sc, an);
451}
452
453static void ath9k_tasklet(unsigned long data)
454{
455 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 456 u32 status = sc->intrstatus;
ff37e337
S		 457
458 if (status & ATH9K_INT_FATAL) {
459 /* need a chip reset */
460 ath_reset(sc, false);
461 return;
462 } else {
463
464 if (status &
465 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 466 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 467 ath_rx_tasklet(sc, 0);
b77f483f 468 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 469 }
470 /* XXX: optimize this */
471 if (status & ATH9K_INT_TX)
472 ath_tx_tasklet(sc);
473 }
474
475 /* re-enable hardware interrupt */
17d7904d 476 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337
S		 477}
478
6baff7f9 479irqreturn_t ath_isr(int irq, void *dev)
ff37e337
S		 480{
481 struct ath_softc *sc = dev;
cbe61d8a 482 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 483 enum ath9k_int status;
484 bool sched = false;
485
486 do {
487 if (sc->sc_flags & SC_OP_INVALID) {
488 /*
489 * The hardware is not ready/present, don't
490 * touch anything. Note this can happen early
491 * on if the IRQ is shared.
492 */
493 return IRQ_NONE;
494 }
495 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
496 return IRQ_NONE;
497 }
498
499 /*
500 * Figure out the reason(s) for the interrupt. Note
501 * that the hal returns a pseudo-ISR that may include
502 * bits we haven't explicitly enabled so we mask the
503 * value to insure we only process bits we requested.
504 */
505 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
506
17d7904d 507 status &= sc->imask; /* discard unasked-for bits */
ff37e337
S		 508
509 /*
510 * If there are no status bits set, then this interrupt was not
511 * for me (should have been caught above).
512 */
513 if (!status)
514 return IRQ_NONE;
515
17d7904d 516 sc->intrstatus = status;
ff37e337
S		 517
518 if (status & ATH9K_INT_FATAL) {
519 /* need a chip reset */
520 sched = true;
521 } else if (status & ATH9K_INT_RXORN) {
522 /* need a chip reset */
523 sched = true;
524 } else {
525 if (status & ATH9K_INT_SWBA) {
526 /* schedule a tasklet for beacon handling */
527 tasklet_schedule(&sc->bcon_tasklet);
528 }
529 if (status & ATH9K_INT_RXEOL) {
530 /*
531 * NB: the hardware should re-read the link when
532 * RXE bit is written, but it doesn't work
533 * at least on older hardware revs.
534 */
535 sched = true;
536 }
537
538 if (status & ATH9K_INT_TXURN)
539 /* bump tx trigger level */
540 ath9k_hw_updatetxtriglevel(ah, true);
541 /* XXX: optimize this */
542 if (status & ATH9K_INT_RX)
543 sched = true;
544 if (status & ATH9K_INT_TX)
545 sched = true;
546 if (status & ATH9K_INT_BMISS)
547 sched = true;
548 /* carrier sense timeout */
549 if (status & ATH9K_INT_CST)
550 sched = true;
551 if (status & ATH9K_INT_MIB) {
552 /*
553 * Disable interrupts until we service the MIB
554 * interrupt; otherwise it will continue to
555 * fire.
556 */
557 ath9k_hw_set_interrupts(ah, 0);
558 /*
559 * Let the hal handle the event. We assume
560 * it will clear whatever condition caused
561 * the interrupt.
562 */
17d7904d
S		 563 ath9k_hw_procmibevent(ah, &sc->nodestats);
564 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 565 }
566 if (status & ATH9K_INT_TIM_TIMER) {
2660b81a 567 if (!(ah->caps.hw_caps &
ff37e337
S		 568 ATH9K_HW_CAP_AUTOSLEEP)) {
569 /* Clear RxAbort bit so that we can
570 * receive frames */
3cbb5dd7 571 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
ff37e337
S		 572 ath9k_hw_setrxabort(ah, 0);
573 sched = true;
3cbb5dd7 574 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337
S		 575 }
576 }
577 }
578 } while (0);
579
817e11de
S		 580 ath_debug_stat_interrupt(sc, status);
581
ff37e337
S		 582 if (sched) {
583 /* turn off every interrupt except SWBA */
17d7904d 584 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 585 tasklet_schedule(&sc->intr_tq);
586 }
587
588 return IRQ_HANDLED;
589}
590
f078f209 591static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 592 struct ieee80211_channel *chan,
094d05dc 593 enum nl80211_channel_type channel_type)
f078f209
LR		 594{
595 u32 chanmode = 0;
f078f209
LR		 596
597 switch (chan->band) {
598 case IEEE80211_BAND_2GHZ:
094d05dc
S		 599 switch(channel_type) {
600 case NL80211_CHAN_NO_HT:
601 case NL80211_CHAN_HT20:
f078f209 602 chanmode = CHANNEL_G_HT20;
094d05dc
S		 603 break;
604 case NL80211_CHAN_HT40PLUS:
f078f209 605 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 606 break;
607 case NL80211_CHAN_HT40MINUS:
f078f209 608 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 609 break;
610 }
f078f209
LR		 611 break;
612 case IEEE80211_BAND_5GHZ:
094d05dc
S		 613 switch(channel_type) {
614 case NL80211_CHAN_NO_HT:
615 case NL80211_CHAN_HT20:
f078f209 616 chanmode = CHANNEL_A_HT20;
094d05dc
S		 617 break;
618 case NL80211_CHAN_HT40PLUS:
f078f209 619 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 620 break;
621 case NL80211_CHAN_HT40MINUS:
f078f209 622 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 623 break;
624 }
f078f209
LR		 625 break;
626 default:
627 break;
628 }
629
630 return chanmode;
631}
632
ff37e337
S		 633static int ath_keyset(struct ath_softc *sc, u16 keyix,
634 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
635{
636 bool status;
637
638 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
639 keyix, hk, mac, false);
640
641 return status != false;
642}
f078f209 643
6ace2891 644static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
f078f209
LR		 645 struct ath9k_keyval *hk,
646 const u8 *addr)
647{
6ace2891
JM		 648 const u8 *key_rxmic;
649 const u8 *key_txmic;
f078f209 650
6ace2891
JM		 651 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
652 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 653
654 if (addr == NULL) {
655 /* Group key installation */
6ace2891
JM		 656 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
657 return ath_keyset(sc, keyix, hk, addr);
f078f209 658 }
17d7904d 659 if (!sc->splitmic) {
f078f209
LR		 660 /*
661 * data key goes at first index,
662 * the hal handles the MIC keys at index+64.
663 */
664 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
665 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
6ace2891 666 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 667 }
668 /*
669 * TX key goes at first index, RX key at +32.
670 * The hal handles the MIC keys at index+64.
671 */
672 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
6ace2891 673 if (!ath_keyset(sc, keyix, hk, NULL)) {
f078f209
LR		 674 /* Txmic entry failed. No need to proceed further */
675 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 676 "Setting TX MIC Key Failed\n");
f078f209
LR		 677 return 0;
678 }
679
680 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
681 /* XXX delete tx key on failure? */
6ace2891
JM		 682 return ath_keyset(sc, keyix + 32, hk, addr);
683}
684
685static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
686{
687 int i;
688
17d7904d
S		 689 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
690 if (test_bit(i, sc->keymap) ||
691 test_bit(i + 64, sc->keymap))
6ace2891 692 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 693 if (sc->splitmic &&
694 (test_bit(i + 32, sc->keymap) ||
695 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 696 continue; /* At least one part of TKIP key allocated */
697
698 /* Found a free slot for a TKIP key */
699 return i;
700 }
701 return -1;
702}
703
704static int ath_reserve_key_cache_slot(struct ath_softc *sc)
705{
706 int i;
707
708 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 709 if (sc->splitmic) {
710 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
711 if (!test_bit(i, sc->keymap) &&
712 (test_bit(i + 32, sc->keymap) ||
713 test_bit(i + 64, sc->keymap) ||
714 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 715 return i;
17d7904d
S		 716 if (!test_bit(i + 32, sc->keymap) &&
717 (test_bit(i, sc->keymap) ||
718 test_bit(i + 64, sc->keymap) ||
719 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 720 return i + 32;
17d7904d
S		 721 if (!test_bit(i + 64, sc->keymap) &&
722 (test_bit(i , sc->keymap) ||
723 test_bit(i + 32, sc->keymap) ||
724 test_bit(i + 64 + 32, sc->keymap)))
ea612132 725 return i + 64;
17d7904d
S		 726 if (!test_bit(i + 64 + 32, sc->keymap) &&
727 (test_bit(i, sc->keymap) ||
728 test_bit(i + 32, sc->keymap) ||
729 test_bit(i + 64, sc->keymap)))
ea612132 730 return i + 64 + 32;
6ace2891
JM		 731 }
732 } else {
17d7904d
S		 733 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
734 if (!test_bit(i, sc->keymap) &&
735 test_bit(i + 64, sc->keymap))
6ace2891 736 return i;
17d7904d
S		 737 if (test_bit(i, sc->keymap) &&
738 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 739 return i + 64;
740 }
741 }
742
743 /* No partially used TKIP slots, pick any available slot */
17d7904d 744 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 745 /* Do not allow slots that could be needed for TKIP group keys
746 * to be used. This limitation could be removed if we know that
747 * TKIP will not be used. */
748 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
749 continue;
17d7904d 750 if (sc->splitmic) {
be2864cf
JM		 751 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
752 continue;
753 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
754 continue;
755 }
756
17d7904d 757 if (!test_bit(i, sc->keymap))
6ace2891
JM		 758 return i; /* Found a free slot for a key */
759 }
760
761 /* No free slot found */
762 return -1;
f078f209
LR		 763}
764
765static int ath_key_config(struct ath_softc *sc,
dc822b5d 766 struct ieee80211_sta *sta,
f078f209
LR		 767 struct ieee80211_key_conf *key)
768{
f078f209
LR		 769 struct ath9k_keyval hk;
770 const u8 *mac = NULL;
771 int ret = 0;
6ace2891 772 int idx;
f078f209
LR		 773
774 memset(&hk, 0, sizeof(hk));
775
776 switch (key->alg) {
777 case ALG_WEP:
778 hk.kv_type = ATH9K_CIPHER_WEP;
779 break;
780 case ALG_TKIP:
781 hk.kv_type = ATH9K_CIPHER_TKIP;
782 break;
783 case ALG_CCMP:
784 hk.kv_type = ATH9K_CIPHER_AES_CCM;
785 break;
786 default:
ca470b29 787 return -EOPNOTSUPP;
f078f209
LR		 788 }
789
6ace2891 790 hk.kv_len = key->keylen;
f078f209
LR		 791 memcpy(hk.kv_val, key->key, key->keylen);
792
6ace2891
JM		 793 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
794 /* For now, use the default keys for broadcast keys. This may
795 * need to change with virtual interfaces. */
796 idx = key->keyidx;
797 } else if (key->keyidx) {
798 struct ieee80211_vif *vif;
f078f209 799
dc822b5d
JB		 800 if (WARN_ON(!sta))
801 return -EOPNOTSUPP;
802 mac = sta->addr;
803
17d7904d 804 vif = sc->vifs[0];
6ace2891
JM		 805 if (vif->type != NL80211_IFTYPE_AP) {
806 /* Only keyidx 0 should be used with unicast key, but
807 * allow this for client mode for now. */
808 idx = key->keyidx;
809 } else
810 return -EIO;
f078f209 811 } else {
dc822b5d
JB		 812 if (WARN_ON(!sta))
813 return -EOPNOTSUPP;
814 mac = sta->addr;
815
6ace2891
JM		 816 if (key->alg == ALG_TKIP)
817 idx = ath_reserve_key_cache_slot_tkip(sc);
818 else
819 idx = ath_reserve_key_cache_slot(sc);
820 if (idx < 0)
ca470b29 821 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 822 }
823
824 if (key->alg == ALG_TKIP)
6ace2891 825 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
f078f209 826 else
6ace2891 827 ret = ath_keyset(sc, idx, &hk, mac);
f078f209
LR		 828
829 if (!ret)
830 return -EIO;
831
17d7904d 832 set_bit(idx, sc->keymap);
6ace2891 833 if (key->alg == ALG_TKIP) {
17d7904d
S		 834 set_bit(idx + 64, sc->keymap);
835 if (sc->splitmic) {
836 set_bit(idx + 32, sc->keymap);
837 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 838 }
839 }
840
841 return idx;
f078f209
LR		 842}
843
844static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
845{
6ace2891
JM		 846 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
847 if (key->hw_key_idx < IEEE80211_WEP_NKID)
848 return;
849
17d7904d 850 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 851 if (key->alg != ALG_TKIP)
852 return;
f078f209 853
17d7904d
S		 854 clear_bit(key->hw_key_idx + 64, sc->keymap);
855 if (sc->splitmic) {
856 clear_bit(key->hw_key_idx + 32, sc->keymap);
857 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 858 }
f078f209
LR		 859}
860
eb2599ca
S		 861static void setup_ht_cap(struct ath_softc *sc,
862 struct ieee80211_sta_ht_cap *ht_info)
f078f209 863{
60653678
S		 864#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
865#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 866
d9fe60de
JB		 867 ht_info->ht_supported = true;
868 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
869 IEEE80211_HT_CAP_SM_PS |
870 IEEE80211_HT_CAP_SGI_40 |
871 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 872
60653678
S		 873 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
874 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 875
d9fe60de
JB		 876 /* set up supported mcs set */
877 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca 878
17d7904d 879 switch(sc->rx_chainmask) {
eb2599ca
S		 880 case 1:
881 ht_info->mcs.rx_mask[0] = 0xff;
882 break;
3c457265 883 case 3:
eb2599ca
S		 884 case 5:
885 case 7:
886 default:
887 ht_info->mcs.rx_mask[0] = 0xff;
888 ht_info->mcs.rx_mask[1] = 0xff;
889 break;
890 }
891
d9fe60de 892 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 893}
894
8feceb67 895static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 896 struct ieee80211_vif *vif,
8feceb67 897 struct ieee80211_bss_conf *bss_conf)
f078f209 898{
17d7904d 899 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 900
8feceb67 901 if (bss_conf->assoc) {
094d05dc 902 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 903 bss_conf->aid, sc->curbssid);
f078f209 904
8feceb67 905 /* New association, store aid */
d97809db 906 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
17d7904d 907 sc->curaid = bss_conf->aid;
ba52da58 908 ath9k_hw_write_associd(sc);
8feceb67 909 }
f078f209 910
8feceb67
VT		 911 /* Configure the beacon */
912 ath_beacon_config(sc, 0);
913 sc->sc_flags |= SC_OP_BEACONS;
f078f209 914
8feceb67 915 /* Reset rssi stats */
17d7904d
S		 916 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
917 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
918 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
919 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 920
6f255425 921 /* Start ANI */
17d7904d 922 mod_timer(&sc->ani.timer,
6f255425
LR		 923 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
924
8feceb67 925 } else {
04bd4638 926 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
17d7904d 927 sc->curaid = 0;
f078f209 928 }
8feceb67 929}
f078f209 930
8feceb67
VT		 931/********************************/
932/* LED functions */
933/********************************/
f078f209 934
f2bffa7e
VT		 935static void ath_led_blink_work(struct work_struct *work)
936{
937 struct ath_softc *sc = container_of(work, struct ath_softc,
938 ath_led_blink_work.work);
939
940 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
941 return;
942 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
943 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
944
945 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
946 (sc->sc_flags & SC_OP_LED_ON) ?
947 msecs_to_jiffies(sc->led_off_duration) :
948 msecs_to_jiffies(sc->led_on_duration));
949
950 sc->led_on_duration =
951 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
952 sc->led_off_duration =
953 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
954 sc->led_on_cnt = sc->led_off_cnt = 0;
955 if (sc->sc_flags & SC_OP_LED_ON)
956 sc->sc_flags &= ~SC_OP_LED_ON;
957 else
958 sc->sc_flags |= SC_OP_LED_ON;
959}
960
8feceb67
VT		 961static void ath_led_brightness(struct led_classdev *led_cdev,
962 enum led_brightness brightness)
963{
964 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
965 struct ath_softc *sc = led->sc;
f078f209 966
8feceb67
VT		 967 switch (brightness) {
968 case LED_OFF:
969 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 970 led->led_type == ATH_LED_RADIO) {
971 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
972 (led->led_type == ATH_LED_RADIO));
8feceb67 973 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 974 if (led->led_type == ATH_LED_RADIO)
975 sc->sc_flags &= ~SC_OP_LED_ON;
976 } else {
977 sc->led_off_cnt++;
978 }
8feceb67
VT		 979 break;
980 case LED_FULL:
f2bffa7e 981 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 982 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 983 queue_delayed_work(sc->hw->workqueue,
984 &sc->ath_led_blink_work, 0);
985 } else if (led->led_type == ATH_LED_RADIO) {
986 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
987 sc->sc_flags |= SC_OP_LED_ON;
988 } else {
989 sc->led_on_cnt++;
990 }
8feceb67
VT		 991 break;
992 default:
993 break;
f078f209 994 }
8feceb67 995}
f078f209 996
8feceb67
VT		 997static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
998 char *trigger)
999{
1000 int ret;
f078f209 1001
8feceb67
VT		 1002 led->sc = sc;
1003 led->led_cdev.name = led->name;
1004 led->led_cdev.default_trigger = trigger;
1005 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1006
8feceb67
VT		 1007 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1008 if (ret)
1009 DPRINTF(sc, ATH_DBG_FATAL,
1010 "Failed to register led:%s", led->name);
1011 else
1012 led->registered = 1;
1013 return ret;
1014}
f078f209 1015
8feceb67
VT		 1016static void ath_unregister_led(struct ath_led *led)
1017{
1018 if (led->registered) {
1019 led_classdev_unregister(&led->led_cdev);
1020 led->registered = 0;
f078f209 1021 }
f078f209
LR		 1022}
1023
8feceb67 1024static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1025{
f2bffa7e 1026 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1027 ath_unregister_led(&sc->assoc_led);
1028 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1029 ath_unregister_led(&sc->tx_led);
1030 ath_unregister_led(&sc->rx_led);
1031 ath_unregister_led(&sc->radio_led);
1032 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1033}
f078f209 1034
8feceb67
VT		 1035static void ath_init_leds(struct ath_softc *sc)
1036{
1037 char *trigger;
1038 int ret;
f078f209 1039
8feceb67
VT		 1040 /* Configure gpio 1 for output */
1041 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1042 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1043 /* LED off, active low */
1044 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1045
f2bffa7e
VT		 1046 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1047
8feceb67
VT		 1048 trigger = ieee80211_get_radio_led_name(sc->hw);
1049 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1050 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1051 ret = ath_register_led(sc, &sc->radio_led, trigger);
1052 sc->radio_led.led_type = ATH_LED_RADIO;
1053 if (ret)
1054 goto fail;
7dcfdcd9 1055
8feceb67
VT		 1056 trigger = ieee80211_get_assoc_led_name(sc->hw);
1057 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1058 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1059 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1060 sc->assoc_led.led_type = ATH_LED_ASSOC;
1061 if (ret)
1062 goto fail;
f078f209 1063
8feceb67
VT		 1064 trigger = ieee80211_get_tx_led_name(sc->hw);
1065 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1066 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1067 ret = ath_register_led(sc, &sc->tx_led, trigger);
1068 sc->tx_led.led_type = ATH_LED_TX;
1069 if (ret)
1070 goto fail;
f078f209 1071
8feceb67
VT		 1072 trigger = ieee80211_get_rx_led_name(sc->hw);
1073 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1074 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1075 ret = ath_register_led(sc, &sc->rx_led, trigger);
1076 sc->rx_led.led_type = ATH_LED_RX;
1077 if (ret)
1078 goto fail;
f078f209 1079
8feceb67
VT		 1080 return;
1081
1082fail:
1083 ath_deinit_leds(sc);
f078f209
LR		 1084}
1085
e97275cb 1086#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1087
500c064d
VT		 1088/*******************/
1089/* Rfkill */
1090/*******************/
1091
1092static void ath_radio_enable(struct ath_softc *sc)
1093{
cbe61d8a 1094 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1095 struct ieee80211_channel *channel = sc->hw->conf.channel;
1096 int r;
500c064d 1097
3cbb5dd7 1098 ath9k_ps_wakeup(sc);
500c064d 1099 spin_lock_bh(&sc->sc_resetlock);
ae8d2858 1100
2660b81a 1101 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858
LR		 1102
1103 if (r) {
500c064d 1104 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1105 "Unable to reset channel %u (%uMhz) ",
1106 "reset status %u\n",
1107 channel->center_freq, r);
500c064d
VT		 1108 }
1109 spin_unlock_bh(&sc->sc_resetlock);
1110
1111 ath_update_txpow(sc);
1112 if (ath_startrecv(sc) != 0) {
1113 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1114 "Unable to restart recv logic\n");
500c064d
VT		 1115 return;
1116 }
1117
1118 if (sc->sc_flags & SC_OP_BEACONS)
1119 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1120
1121 /* Re-Enable interrupts */
17d7904d 1122 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1123
1124 /* Enable LED */
1125 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1126 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1127 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1128
1129 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1130 ath9k_ps_restore(sc);
500c064d
VT		 1131}
1132
1133static void ath_radio_disable(struct ath_softc *sc)
1134{
cbe61d8a 1135 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1136 struct ieee80211_channel *channel = sc->hw->conf.channel;
1137 int r;
500c064d 1138
3cbb5dd7 1139 ath9k_ps_wakeup(sc);
500c064d
VT		 1140 ieee80211_stop_queues(sc->hw);
1141
1142 /* Disable LED */
1143 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1144 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1145
1146 /* Disable interrupts */
1147 ath9k_hw_set_interrupts(ah, 0);
1148
043a0405 1149 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1150 ath_stoprecv(sc); /* turn off frame recv */
1151 ath_flushrecv(sc); /* flush recv queue */
1152
1153 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1154 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1155 if (r) {
500c064d 1156 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1157 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1158 "reset status %u\n",
1159 channel->center_freq, r);
500c064d
VT		 1160 }
1161 spin_unlock_bh(&sc->sc_resetlock);
1162
1163 ath9k_hw_phy_disable(ah);
1164 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1165 ath9k_ps_restore(sc);
500c064d
VT		 1166}
1167
1168static bool ath_is_rfkill_set(struct ath_softc *sc)
1169{
cbe61d8a 1170 struct ath_hw *ah = sc->sc_ah;
500c064d 1171
2660b81a
S		 1172 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1173 ah->rfkill_polarity;
500c064d
VT		 1174}
1175
1176/* h/w rfkill poll function */
1177static void ath_rfkill_poll(struct work_struct *work)
1178{
1179 struct ath_softc *sc = container_of(work, struct ath_softc,
1180 rf_kill.rfkill_poll.work);
1181 bool radio_on;
1182
1183 if (sc->sc_flags & SC_OP_INVALID)
1184 return;
1185
1186 radio_on = !ath_is_rfkill_set(sc);
1187
1188 /*
1189 * enable/disable radio only when there is a
1190 * state change in RF switch
1191 */
1192 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1193 enum rfkill_state state;
1194
1195 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1196 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1197 : RFKILL_STATE_HARD_BLOCKED;
1198 } else if (radio_on) {
1199 ath_radio_enable(sc);
1200 state = RFKILL_STATE_UNBLOCKED;
1201 } else {
1202 ath_radio_disable(sc);
1203 state = RFKILL_STATE_HARD_BLOCKED;
1204 }
1205
1206 if (state == RFKILL_STATE_HARD_BLOCKED)
1207 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1208 else
1209 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1210
1211 rfkill_force_state(sc->rf_kill.rfkill, state);
1212 }
1213
1214 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1215 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1216}
1217
1218/* s/w rfkill handler */
1219static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1220{
1221 struct ath_softc *sc = data;
1222
1223 switch (state) {
1224 case RFKILL_STATE_SOFT_BLOCKED:
1225 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1226 SC_OP_RFKILL_SW_BLOCKED)))
1227 ath_radio_disable(sc);
1228 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1229 return 0;
1230 case RFKILL_STATE_UNBLOCKED:
1231 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1232 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1233 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1234 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1235 "radio as it is disabled by h/w\n");
500c064d
VT		 1236 return -EPERM;
1237 }
1238 ath_radio_enable(sc);
1239 }
1240 return 0;
1241 default:
1242 return -EINVAL;
1243 }
1244}
1245
1246/* Init s/w rfkill */
1247static int ath_init_sw_rfkill(struct ath_softc *sc)
1248{
1249 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1250 RFKILL_TYPE_WLAN);
1251 if (!sc->rf_kill.rfkill) {
1252 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1253 return -ENOMEM;
1254 }
1255
1256 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
0818cb8a 1257 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
500c064d
VT		 1258 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1259 sc->rf_kill.rfkill->data = sc;
1260 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1261 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1262 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1263
1264 return 0;
1265}
1266
1267/* Deinitialize rfkill */
1268static void ath_deinit_rfkill(struct ath_softc *sc)
1269{
2660b81a 1270 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1271 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1272
1273 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1274 rfkill_unregister(sc->rf_kill.rfkill);
1275 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1276 sc->rf_kill.rfkill = NULL;
1277 }
1278}
9c84b797
S		 1279
1280static int ath_start_rfkill_poll(struct ath_softc *sc)
1281{
2660b81a 1282 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
9c84b797
S		 1283 queue_delayed_work(sc->hw->workqueue,
1284 &sc->rf_kill.rfkill_poll, 0);
1285
1286 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1287 if (rfkill_register(sc->rf_kill.rfkill)) {
1288 DPRINTF(sc, ATH_DBG_FATAL,
1289 "Unable to register rfkill\n");
1290 rfkill_free(sc->rf_kill.rfkill);
1291
1292 /* Deinitialize the device */
39c3c2f2 1293 ath_cleanup(sc);
9c84b797
S		 1294 return -EIO;
1295 } else {
1296 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1297 }
1298 }
1299
1300 return 0;
1301}
500c064d
VT		 1302#endif /* CONFIG_RFKILL */
1303
6baff7f9 1304void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1305{
1306 ath_detach(sc);
1307 free_irq(sc->irq, sc);
1308 ath_bus_cleanup(sc);
1309 ieee80211_free_hw(sc->hw);
1310}
1311
6baff7f9 1312void ath_detach(struct ath_softc *sc)
f078f209 1313{
8feceb67 1314 struct ieee80211_hw *hw = sc->hw;
9c84b797 1315 int i = 0;
f078f209 1316
3cbb5dd7
VN		 1317 ath9k_ps_wakeup(sc);
1318
04bd4638 1319 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1320
e97275cb 1321#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1322 ath_deinit_rfkill(sc);
1323#endif
3fcdfb4b
VT		 1324 ath_deinit_leds(sc);
1325
1326 ieee80211_unregister_hw(hw);
8feceb67
VT		 1327 ath_rx_cleanup(sc);
1328 ath_tx_cleanup(sc);
f078f209 1329
9c84b797
S		 1330 tasklet_kill(&sc->intr_tq);
1331 tasklet_kill(&sc->bcon_tasklet);
f078f209 1332
9c84b797
S		 1333 if (!(sc->sc_flags & SC_OP_INVALID))
1334 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1335
9c84b797
S		 1336 /* cleanup tx queues */
1337 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1338 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1339 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1340
1341 ath9k_hw_detach(sc->sc_ah);
826d2680 1342 ath9k_exit_debug(sc);
3cbb5dd7 1343 ath9k_ps_restore(sc);
f078f209
LR		 1344}
1345
ff37e337
S		 1346static int ath_init(u16 devid, struct ath_softc *sc)
1347{
cbe61d8a 1348 struct ath_hw *ah = NULL;
ff37e337
S		 1349 int status;
1350 int error = 0, i;
1351 int csz = 0;
1352
1353 /* XXX: hardware will not be ready until ath_open() being called */
1354 sc->sc_flags |= SC_OP_INVALID;
88b126af 1355
826d2680
S		 1356 if (ath9k_init_debug(sc) < 0)
1357 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S		 1358
1359 spin_lock_init(&sc->sc_resetlock);
aa33de09 1360 mutex_init(&sc->mutex);
ff37e337
S		 1361 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1362 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1363 (unsigned long)sc);
1364
1365 /*
1366 * Cache line size is used to size and align various
1367 * structures used to communicate with the hardware.
1368 */
88d15707 1369 ath_read_cachesize(sc, &csz);
ff37e337 1370 /* XXX assert csz is non-zero */
17d7904d 1371 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1372
cbe61d8a 1373 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1374 if (ah == NULL) {
1375 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1376 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1377 error = -ENXIO;
1378 goto bad;
1379 }
1380 sc->sc_ah = ah;
1381
1382 /* Get the hardware key cache size. */
2660b81a 1383 sc->keymax = ah->caps.keycache_size;
17d7904d 1384 if (sc->keymax > ATH_KEYMAX) {
ff37e337 1385 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 1386 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1387 ATH_KEYMAX, sc->keymax);
1388 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1389 }
1390
1391 /*
1392 * Reset the key cache since some parts do not
1393 * reset the contents on initial power up.
1394 */
17d7904d 1395 for (i = 0; i < sc->keymax; i++)
ff37e337 1396 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1397
5f8e077c 1398 if (ath9k_regd_init(sc->sc_ah))
ff37e337
S		 1399 goto bad;
1400
1401 /* default to MONITOR mode */
2660b81a 1402 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1403
ff37e337
S		 1404 /* Setup rate tables */
1405
1406 ath_rate_attach(sc);
1407 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1408 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1409
1410 /*
1411 * Allocate hardware transmit queues: one queue for
1412 * beacon frames and one data queue for each QoS
1413 * priority. Note that the hal handles reseting
1414 * these queues at the needed time.
1415 */
b77f483f
S		 1416 sc->beacon.beaconq = ath_beaconq_setup(ah);
1417 if (sc->beacon.beaconq == -1) {
ff37e337 1418 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1419 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1420 error = -EIO;
1421 goto bad2;
1422 }
b77f483f
S		 1423 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1424 if (sc->beacon.cabq == NULL) {
ff37e337 1425 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1426 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1427 error = -EIO;
1428 goto bad2;
1429 }
1430
17d7904d 1431 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1432 ath_cabq_update(sc);
1433
b77f483f
S		 1434 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1435 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1436
1437 /* Setup data queues */
1438 /* NB: ensure BK queue is the lowest priority h/w queue */
1439 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1440 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1441 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1442 error = -EIO;
1443 goto bad2;
1444 }
1445
1446 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1447 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1448 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1449 error = -EIO;
1450 goto bad2;
1451 }
1452 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1453 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1454 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1455 error = -EIO;
1456 goto bad2;
1457 }
1458 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1459 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1460 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1461 error = -EIO;
1462 goto bad2;
1463 }
1464
1465 /* Initializes the noise floor to a reasonable default value.
1466 * Later on this will be updated during ANI processing. */
1467
17d7904d
S		 1468 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1469 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1470
1471 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1472 ATH9K_CIPHER_TKIP, NULL)) {
1473 /*
1474 * Whether we should enable h/w TKIP MIC.
1475 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1476 * report WMM capable, so it's always safe to turn on
1477 * TKIP MIC in this case.
1478 */
1479 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1480 0, 1, NULL);
1481 }
1482
1483 /*
1484 * Check whether the separate key cache entries
1485 * are required to handle both tx+rx MIC keys.
1486 * With split mic keys the number of stations is limited
1487 * to 27 otherwise 59.
1488 */
1489 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1490 ATH9K_CIPHER_TKIP, NULL)
1491 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1492 ATH9K_CIPHER_MIC, NULL)
1493 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1494 0, NULL))
17d7904d 1495 sc->splitmic = 1;
ff37e337
S		 1496
1497 /* turn on mcast key search if possible */
1498 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1499 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1500 1, NULL);
1501
17d7904d 1502 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1503
1504 /* 11n Capabilities */
2660b81a 1505 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1506 sc->sc_flags |= SC_OP_TXAGGR;
1507 sc->sc_flags |= SC_OP_RXAGGR;
1508 }
1509
2660b81a
S		 1510 sc->tx_chainmask = ah->caps.tx_chainmask;
1511 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1512
1513 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1514 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1515
2660b81a 1516 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
ba52da58 1517 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
17d7904d 1518 ATH_SET_VIF_BSSID_MASK(sc->bssidmask);
ba52da58 1519 ath9k_hw_setbssidmask(sc);
ff37e337
S		 1520 }
1521
b77f483f 1522 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1523
1524 /* initialize beacon slots */
b77f483f
S		 1525 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1526 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
ff37e337
S		 1527
1528 /* save MISC configurations */
17d7904d 1529 sc->config.swBeaconProcess = 1;
ff37e337 1530
ff37e337
S		 1531 /* setup channels and rates */
1532
5f8e077c 1533 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1534 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1535 sc->rates[IEEE80211_BAND_2GHZ];
1536 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1537 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1538 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1539
2660b81a 1540 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1541 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1542 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1543 sc->rates[IEEE80211_BAND_5GHZ];
1544 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1545 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1546 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1547 }
1548
2660b81a 1549 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1550 ath9k_hw_btcoex_enable(sc->sc_ah);
1551
ff37e337
S		 1552 return 0;
1553bad2:
1554 /* cleanup tx queues */
1555 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1556 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1557 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1558bad:
1559 if (ah)
1560 ath9k_hw_detach(ah);
40b130a9 1561 ath9k_exit_debug(sc);
ff37e337
S		 1562
1563 return error;
1564}
1565
6baff7f9 1566int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1567{
8feceb67 1568 struct ieee80211_hw *hw = sc->hw;
40b130a9 1569 int error = 0, i;
f078f209 1570
04bd4638 1571 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1572
8feceb67
VT		 1573 error = ath_init(devid, sc);
1574 if (error != 0)
1575 return error;
f078f209 1576
8feceb67 1577 /* get mac address from hardware and set in mac80211 */
f078f209 1578
ba52da58 1579 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
f078f209 1580
9c84b797
S		 1581 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1582 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1583 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1584 IEEE80211_HW_AMPDU_AGGREGATION |
1585 IEEE80211_HW_SUPPORTS_PS |
1586 IEEE80211_HW_PS_NULLFUNC_STACK;
f078f209 1587
0ced0e17
JM		 1588 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1589 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1590
9c84b797
S		 1591 hw->wiphy->interface_modes =
1592 BIT(NL80211_IFTYPE_AP) |
1593 BIT(NL80211_IFTYPE_STATION) |
1594 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1595
5f8e077c
LR		 1596 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1597 hw->wiphy->strict_regulatory = true;
1598
8feceb67 1599 hw->queues = 4;
e63835b0
S		 1600 hw->max_rates = 4;
1601 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1602 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1603 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1604
8feceb67 1605 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1606
2660b81a 1607 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1608 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1609 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1610 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1611 }
1612
1613 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
2660b81a 1614 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
9c84b797
S		 1615 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1616 &sc->sbands[IEEE80211_BAND_5GHZ];
1617
db93e7b5
SB		 1618 /* initialize tx/rx engine */
1619 error = ath_tx_init(sc, ATH_TXBUF);
1620 if (error != 0)
40b130a9 1621 goto error_attach;
8feceb67 1622
db93e7b5
SB		 1623 error = ath_rx_init(sc, ATH_RXBUF);
1624 if (error != 0)
40b130a9 1625 goto error_attach;
8feceb67 1626
e97275cb 1627#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d 1628 /* Initialze h/w Rfkill */
2660b81a 1629 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1630 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1631
1632 /* Initialize s/w rfkill */
40b130a9
VT		 1633 error = ath_init_sw_rfkill(sc);
1634 if (error)
1635 goto error_attach;
500c064d
VT		 1636#endif
1637
5f8e077c
LR		 1638 if (ath9k_is_world_regd(sc->sc_ah)) {
1639 /* Anything applied here (prior to wiphy registratoin) gets
1640 * saved on the wiphy orig_* parameters */
1641 const struct ieee80211_regdomain *regd =
1642 ath9k_world_regdomain(sc->sc_ah);
1643 hw->wiphy->custom_regulatory = true;
1644 hw->wiphy->strict_regulatory = false;
1645 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1646 ath9k_reg_apply_radar_flags(hw->wiphy);
1647 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1648 } else {
1649 /* This gets applied in the case of the absense of CRDA,
1650 * its our own custom world regulatory domain, similar to
1651 * cfg80211's but we enable passive scanning */
1652 const struct ieee80211_regdomain *regd =
1653 ath9k_default_world_regdomain();
1654 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1655 ath9k_reg_apply_radar_flags(hw->wiphy);
1656 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1657 }
1658
db93e7b5 1659 error = ieee80211_register_hw(hw);
8feceb67 1660
5f8e077c 1661 if (!ath9k_is_world_regd(sc->sc_ah))
d6bad496 1662 regulatory_hint(hw->wiphy, sc->sc_ah->regulatory.alpha2);
5f8e077c 1663
db93e7b5
SB		 1664 /* Initialize LED control */
1665 ath_init_leds(sc);
8feceb67 1666
5f8e077c 1667
8feceb67 1668 return 0;
40b130a9
VT		 1669
1670error_attach:
1671 /* cleanup tx queues */
1672 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1673 if (ATH_TXQ_SETUP(sc, i))
1674 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1675
1676 ath9k_hw_detach(sc->sc_ah);
1677 ath9k_exit_debug(sc);
1678
8feceb67 1679 return error;
f078f209
LR		 1680}
1681
ff37e337
S		 1682int ath_reset(struct ath_softc *sc, bool retry_tx)
1683{
cbe61d8a 1684 struct ath_hw *ah = sc->sc_ah;
030bb495 1685 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1686 int r;
ff37e337
S		 1687
1688 ath9k_hw_set_interrupts(ah, 0);
043a0405 1689 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1690 ath_stoprecv(sc);
1691 ath_flushrecv(sc);
1692
1693 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1694 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1695 if (r)
ff37e337 1696 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1697 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1698 spin_unlock_bh(&sc->sc_resetlock);
1699
1700 if (ath_startrecv(sc) != 0)
04bd4638 1701 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1702
1703 /*
1704 * We may be doing a reset in response to a request
1705 * that changes the channel so update any state that
1706 * might change as a result.
1707 */
ce111bad 1708 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1709
1710 ath_update_txpow(sc);
1711
1712 if (sc->sc_flags & SC_OP_BEACONS)
1713 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1714
17d7904d 1715 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1716
1717 if (retry_tx) {
1718 int i;
1719 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1720 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1721 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1722 ath_txq_schedule(sc, &sc->tx.txq[i]);
1723 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1724 }
1725 }
1726 }
1727
ae8d2858 1728 return r;
ff37e337
S		 1729}
1730
1731/*
1732 * This function will allocate both the DMA descriptor structure, and the
1733 * buffers it contains. These are used to contain the descriptors used
1734 * by the system.
1735*/
1736int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1737 struct list_head *head, const char *name,
1738 int nbuf, int ndesc)
1739{
1740#define DS2PHYS(_dd, _ds) \
1741 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1742#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1743#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1744
1745 struct ath_desc *ds;
1746 struct ath_buf *bf;
1747 int i, bsize, error;
1748
04bd4638
S		 1749 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1750 name, nbuf, ndesc);
ff37e337
S		 1751
1752 /* ath_desc must be a multiple of DWORDs */
1753 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1754 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1755 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1756 error = -ENOMEM;
1757 goto fail;
1758 }
1759
1760 dd->dd_name = name;
1761 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1762
1763 /*
1764 * Need additional DMA memory because we can't use
1765 * descriptors that cross the 4K page boundary. Assume
1766 * one skipped descriptor per 4K page.
1767 */
2660b81a 1768 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1769 u32 ndesc_skipped =
1770 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1771 u32 dma_len;
1772
1773 while (ndesc_skipped) {
1774 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1775 dd->dd_desc_len += dma_len;
1776
1777 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1778 };
1779 }
1780
1781 /* allocate descriptors */
7da3c55c
GJ		 1782 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1783 &dd->dd_desc_paddr, GFP_ATOMIC);
ff37e337
S		 1784 if (dd->dd_desc == NULL) {
1785 error = -ENOMEM;
1786 goto fail;
1787 }
1788 ds = dd->dd_desc;
04bd4638
S		 1789 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1790 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1791 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1792
1793 /* allocate buffers */
1794 bsize = sizeof(struct ath_buf) * nbuf;
1795 bf = kmalloc(bsize, GFP_KERNEL);
1796 if (bf == NULL) {
1797 error = -ENOMEM;
1798 goto fail2;
1799 }
1800 memset(bf, 0, bsize);
1801 dd->dd_bufptr = bf;
1802
1803 INIT_LIST_HEAD(head);
1804 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1805 bf->bf_desc = ds;
1806 bf->bf_daddr = DS2PHYS(dd, ds);
1807
2660b81a 1808 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1809 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1810 /*
1811 * Skip descriptor addresses which can cause 4KB
1812 * boundary crossing (addr + length) with a 32 dword
1813 * descriptor fetch.
1814 */
1815 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1816 ASSERT((caddr_t) bf->bf_desc <
1817 ((caddr_t) dd->dd_desc +
1818 dd->dd_desc_len));
1819
1820 ds += ndesc;
1821 bf->bf_desc = ds;
1822 bf->bf_daddr = DS2PHYS(dd, ds);
1823 }
1824 }
1825 list_add_tail(&bf->list, head);
1826 }
1827 return 0;
1828fail2:
7da3c55c
GJ		 1829 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1830 dd->dd_desc_paddr);
ff37e337
S		 1831fail:
1832 memset(dd, 0, sizeof(*dd));
1833 return error;
1834#undef ATH_DESC_4KB_BOUND_CHECK
1835#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1836#undef DS2PHYS
1837}
1838
1839void ath_descdma_cleanup(struct ath_softc *sc,
1840 struct ath_descdma *dd,
1841 struct list_head *head)
1842{
7da3c55c
GJ		 1843 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1844 dd->dd_desc_paddr);
ff37e337
S		 1845
1846 INIT_LIST_HEAD(head);
1847 kfree(dd->dd_bufptr);
1848 memset(dd, 0, sizeof(*dd));
1849}
1850
1851int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1852{
1853 int qnum;
1854
1855 switch (queue) {
1856 case 0:
b77f483f 1857 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1858 break;
1859 case 1:
b77f483f 1860 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1861 break;
1862 case 2:
b77f483f 1863 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1864 break;
1865 case 3:
b77f483f 1866 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1867 break;
1868 default:
b77f483f 1869 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1870 break;
1871 }
1872
1873 return qnum;
1874}
1875
1876int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1877{
1878 int qnum;
1879
1880 switch (queue) {
1881 case ATH9K_WME_AC_VO:
1882 qnum = 0;
1883 break;
1884 case ATH9K_WME_AC_VI:
1885 qnum = 1;
1886 break;
1887 case ATH9K_WME_AC_BE:
1888 qnum = 2;
1889 break;
1890 case ATH9K_WME_AC_BK:
1891 qnum = 3;
1892 break;
1893 default:
1894 qnum = -1;
1895 break;
1896 }
1897
1898 return qnum;
1899}
1900
5f8e077c
LR		 1901/* XXX: Remove me once we don't depend on ath9k_channel for all
1902 * this redundant data */
1903static void ath9k_update_ichannel(struct ath_softc *sc,
1904 struct ath9k_channel *ichan)
1905{
1906 struct ieee80211_hw *hw = sc->hw;
1907 struct ieee80211_channel *chan = hw->conf.channel;
1908 struct ieee80211_conf *conf = &hw->conf;
1909
1910 ichan->channel = chan->center_freq;
1911 ichan->chan = chan;
1912
1913 if (chan->band == IEEE80211_BAND_2GHZ) {
1914 ichan->chanmode = CHANNEL_G;
1915 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1916 } else {
1917 ichan->chanmode = CHANNEL_A;
1918 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1919 }
1920
1921 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1922
1923 if (conf_is_ht(conf)) {
1924 if (conf_is_ht40(conf))
1925 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1926
1927 ichan->chanmode = ath_get_extchanmode(sc, chan,
1928 conf->channel_type);
1929 }
1930}
1931
ff37e337
S		 1932/**********************/
1933/* mac80211 callbacks */
1934/**********************/
1935
8feceb67 1936static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR		 1937{
1938 struct ath_softc *sc = hw->priv;
8feceb67 1939 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1940 struct ath9k_channel *init_channel;
ae8d2858 1941 int r, pos;
f078f209 1942
04bd4638
S		 1943 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1944 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1945
141b38b6
S		 1946 mutex_lock(&sc->mutex);
1947
8feceb67 1948 /* setup initial channel */
f078f209 1949
5f8e077c 1950 pos = curchan->hw_value;
f078f209 1951
2660b81a 1952 init_channel = &sc->sc_ah->channels[pos];
5f8e077c 1953 ath9k_update_ichannel(sc, init_channel);
ff37e337
S		 1954
1955 /* Reset SERDES registers */
1956 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1957
1958 /*
1959 * The basic interface to setting the hardware in a good
1960 * state is ``reset''. On return the hardware is known to
1961 * be powered up and with interrupts disabled. This must
1962 * be followed by initialization of the appropriate bits
1963 * and then setup of the interrupt mask.
1964 */
1965 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1966 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1967 if (r) {
ff37e337 1968 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1969 "Unable to reset hardware; reset status %u "
1970 "(freq %u MHz)\n", r,
1971 curchan->center_freq);
ff37e337 1972 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1973 goto mutex_unlock;
ff37e337
S		 1974 }
1975 spin_unlock_bh(&sc->sc_resetlock);
1976
1977 /*
1978 * This is needed only to setup initial state
1979 * but it's best done after a reset.
1980 */
1981 ath_update_txpow(sc);
8feceb67 1982
ff37e337
S		 1983 /*
1984 * Setup the hardware after reset:
1985 * The receive engine is set going.
1986 * Frame transmit is handled entirely
1987 * in the frame output path; there's nothing to do
1988 * here except setup the interrupt mask.
1989 */
1990 if (ath_startrecv(sc) != 0) {
8feceb67 1991 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1992 "Unable to start recv logic\n");
141b38b6
S		 1993 r = -EIO;
1994 goto mutex_unlock;
f078f209 1995 }
8feceb67 1996
ff37e337 1997 /* Setup our intr mask. */
17d7904d 1998 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 1999 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2000 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2001
2660b81a 2002 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2003 sc->imask |= ATH9K_INT_GTT;
ff37e337 2004
2660b81a 2005 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2006 sc->imask |= ATH9K_INT_CST;
ff37e337 2007
ce111bad 2008 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2009
2010 sc->sc_flags &= ~SC_OP_INVALID;
2011
2012 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 2013 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2014 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337
S		 2015
2016 ieee80211_wake_queues(sc->hw);
2017
e97275cb 2018#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 2019 r = ath_start_rfkill_poll(sc);
500c064d 2020#endif
141b38b6
S		 2021
2022mutex_unlock:
2023 mutex_unlock(&sc->mutex);
2024
ae8d2858 2025 return r;
f078f209
LR		 2026}
2027
8feceb67
VT		 2028static int ath9k_tx(struct ieee80211_hw *hw,
2029 struct sk_buff *skb)
f078f209 2030{
528f0c6b 2031 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 2032 struct ath_softc *sc = hw->priv;
528f0c6b 2033 struct ath_tx_control txctl;
8feceb67 2034 int hdrlen, padsize;
528f0c6b
S		 2035
2036 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2037
8feceb67
VT		 2038 /*
2039 * As a temporary workaround, assign seq# here; this will likely need
2040 * to be cleaned up to work better with Beacon transmission and virtual
2041 * BSSes.
2042 */
2043 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2044 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2045 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2046 sc->tx.seq_no += 0x10;
8feceb67 2047 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2048 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2049 }
f078f209 2050
8feceb67
VT		 2051 /* Add the padding after the header if this is not already done */
2052 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2053 if (hdrlen & 3) {
2054 padsize = hdrlen % 4;
2055 if (skb_headroom(skb) < padsize)
2056 return -1;
2057 skb_push(skb, padsize);
2058 memmove(skb->data, skb->data + padsize, hdrlen);
2059 }
2060
528f0c6b
S		 2061 /* Check if a tx queue is available */
2062
2063 txctl.txq = ath_test_get_txq(sc, skb);
2064 if (!txctl.txq)
2065 goto exit;
2066
04bd4638 2067 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2068
528f0c6b 2069 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 2070 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2071 goto exit;
8feceb67
VT		 2072 }
2073
528f0c6b
S		 2074 return 0;
2075exit:
2076 dev_kfree_skb_any(skb);
8feceb67 2077 return 0;
f078f209
LR		 2078}
2079
8feceb67 2080static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR		 2081{
2082 struct ath_softc *sc = hw->priv;
f078f209 2083
9c84b797 2084 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2085 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2086 return;
2087 }
8feceb67 2088
141b38b6 2089 mutex_lock(&sc->mutex);
ff37e337
S		 2090
2091 ieee80211_stop_queues(sc->hw);
2092
2093 /* make sure h/w will not generate any interrupt
2094 * before setting the invalid flag. */
2095 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2096
2097 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2098 ath_drain_all_txq(sc, false);
ff37e337
S		 2099 ath_stoprecv(sc);
2100 ath9k_hw_phy_disable(sc->sc_ah);
2101 } else
b77f483f 2102 sc->rx.rxlink = NULL;
ff37e337
S		 2103
2104#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a 2105 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
ff37e337
S		 2106 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2107#endif
2108 /* disable HAL and put h/w to sleep */
2109 ath9k_hw_disable(sc->sc_ah);
2110 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2111
2112 sc->sc_flags |= SC_OP_INVALID;
500c064d 2113
141b38b6
S		 2114 mutex_unlock(&sc->mutex);
2115
04bd4638 2116 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2117}
2118
8feceb67
VT		 2119static int ath9k_add_interface(struct ieee80211_hw *hw,
2120 struct ieee80211_if_init_conf *conf)
f078f209
LR		 2121{
2122 struct ath_softc *sc = hw->priv;
17d7904d 2123 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2124 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
f078f209 2125
17d7904d 2126 /* Support only vif for now */
8feceb67 2127
17d7904d 2128 if (sc->nvifs)
8feceb67
VT		 2129 return -ENOBUFS;
2130
141b38b6
S		 2131 mutex_lock(&sc->mutex);
2132
8feceb67 2133 switch (conf->type) {
05c914fe 2134 case NL80211_IFTYPE_STATION:
d97809db 2135 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2136 break;
05c914fe 2137 case NL80211_IFTYPE_ADHOC:
d97809db 2138 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2139 break;
05c914fe 2140 case NL80211_IFTYPE_AP:
d97809db 2141 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR		 2142 break;
2143 default:
2144 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2145 "Interface type %d not yet supported\n", conf->type);
8feceb67 2146 return -EOPNOTSUPP;
f078f209
LR		 2147 }
2148
17d7904d 2149 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2150
17d7904d 2151 /* Set the VIF opmode */
5640b08e
S		 2152 avp->av_opmode = ic_opmode;
2153 avp->av_bslot = -1;
2154
d97809db 2155 if (ic_opmode == NL80211_IFTYPE_AP)
5640b08e
S		 2156 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2157
17d7904d
S		 2158 sc->vifs[0] = conf->vif;
2159 sc->nvifs++;
5640b08e
S		 2160
2161 /* Set the device opmode */
2660b81a 2162 sc->sc_ah->opmode = ic_opmode;
5640b08e 2163
4e30ffa2
VN		 2164 /*
2165 * Enable MIB interrupts when there are hardware phy counters.
2166 * Note we only do this (at the moment) for station mode.
2167 */
2168 if (ath9k_hw_phycounters(sc->sc_ah) &&
2169 ((conf->type == NL80211_IFTYPE_STATION) ||
2170 (conf->type == NL80211_IFTYPE_ADHOC)))
17d7904d 2171 sc->imask |= ATH9K_INT_MIB;
4e30ffa2
VN		 2172 /*
2173 * Some hardware processes the TIM IE and fires an
2174 * interrupt when the TIM bit is set. For hardware
2175 * that does, if not overridden by configuration,
2176 * enable the TIM interrupt when operating as station.
2177 */
2660b81a 2178 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
4e30ffa2 2179 (conf->type == NL80211_IFTYPE_STATION) &&
17d7904d
S		 2180 !sc->config.swBeaconProcess)
2181 sc->imask |= ATH9K_INT_TIM;
4e30ffa2 2182
17d7904d 2183 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2184
6f255425
LR		 2185 if (conf->type == NL80211_IFTYPE_AP) {
2186 /* TODO: is this a suitable place to start ANI for AP mode? */
2187 /* Start ANI */
17d7904d 2188 mod_timer(&sc->ani.timer,
6f255425
LR		 2189 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2190 }
2191
141b38b6
S		 2192 mutex_unlock(&sc->mutex);
2193
8feceb67 2194 return 0;
f078f209
LR		 2195}
2196
8feceb67
VT		 2197static void ath9k_remove_interface(struct ieee80211_hw *hw,
2198 struct ieee80211_if_init_conf *conf)
f078f209 2199{
8feceb67 2200 struct ath_softc *sc = hw->priv;
17d7904d 2201 struct ath_vif *avp = (void *)conf->vif->drv_priv;
f078f209 2202
04bd4638 2203 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2204
141b38b6
S		 2205 mutex_lock(&sc->mutex);
2206
6f255425 2207 /* Stop ANI */
17d7904d 2208 del_timer_sync(&sc->ani.timer);
580f0b8a 2209
8feceb67 2210 /* Reclaim beacon resources */
2660b81a
S		 2211 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
2212 sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2213 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2214 ath_beacon_return(sc, avp);
580f0b8a 2215 }
f078f209 2216
8feceb67 2217 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2218
17d7904d
S		 2219 sc->vifs[0] = NULL;
2220 sc->nvifs--;
141b38b6
S		 2221
2222 mutex_unlock(&sc->mutex);
f078f209
LR		 2223}
2224
e8975581 2225static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2226{
8feceb67 2227 struct ath_softc *sc = hw->priv;
e8975581 2228 struct ieee80211_conf *conf = &hw->conf;
f078f209 2229
aa33de09 2230 mutex_lock(&sc->mutex);
141b38b6 2231
3cbb5dd7
VN		 2232 if (changed & IEEE80211_CONF_CHANGE_PS) {
2233 if (conf->flags & IEEE80211_CONF_PS) {
17d7904d
S		 2234 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2235 sc->imask |= ATH9K_INT_TIM_TIMER;
3cbb5dd7 2236 ath9k_hw_set_interrupts(sc->sc_ah,
17d7904d 2237 sc->imask);
3cbb5dd7
VN		 2238 }
2239 ath9k_hw_setrxabort(sc->sc_ah, 1);
2240 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2241 } else {
2242 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2243 ath9k_hw_setrxabort(sc->sc_ah, 0);
2244 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
17d7904d
S		 2245 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2246 sc->imask &= ~ATH9K_INT_TIM_TIMER;
3cbb5dd7 2247 ath9k_hw_set_interrupts(sc->sc_ah,
17d7904d 2248 sc->imask);
3cbb5dd7
VN		 2249 }
2250 }
2251 }
2252
4797938c 2253 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2254 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2255 int pos = curchan->hw_value;
ae5eb026 2256
04bd4638
S		 2257 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2258 curchan->center_freq);
f078f209 2259
5f8e077c 2260 /* XXX: remove me eventualy */
2660b81a 2261 ath9k_update_ichannel(sc, &sc->sc_ah->channels[pos]);
e11602b7 2262
ecf70441 2263 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2264
2660b81a 2265 if (ath_set_channel(sc, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2266 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2267 mutex_unlock(&sc->mutex);
e11602b7
S		 2268 return -EINVAL;
2269 }
094d05dc 2270 }
f078f209 2271
5c020dc6 2272 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2273 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2274
aa33de09 2275 mutex_unlock(&sc->mutex);
141b38b6 2276
f078f209
LR		 2277 return 0;
2278}
2279
8feceb67
VT		 2280static int ath9k_config_interface(struct ieee80211_hw *hw,
2281 struct ieee80211_vif *vif,
2282 struct ieee80211_if_conf *conf)
c83be688 2283{
8feceb67 2284 struct ath_softc *sc = hw->priv;
cbe61d8a 2285 struct ath_hw *ah = sc->sc_ah;
17d7904d 2286 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67
VT		 2287 u32 rfilt = 0;
2288 int error, i;
c83be688 2289
8feceb67
VT		 2290 /* TODO: Need to decide which hw opmode to use for multi-interface
2291 * cases */
05c914fe 2292 if (vif->type == NL80211_IFTYPE_AP &&
2660b81a
S		 2293 ah->opmode != NL80211_IFTYPE_AP) {
2294 ah->opmode = NL80211_IFTYPE_STATION;
8feceb67 2295 ath9k_hw_setopmode(ah);
ba52da58
S		 2296 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2297 sc->curaid = 0;
2298 ath9k_hw_write_associd(sc);
8feceb67
VT		 2299 /* Request full reset to get hw opmode changed properly */
2300 sc->sc_flags |= SC_OP_FULL_RESET;
2301 }
c83be688 2302
8feceb67
VT		 2303 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2304 !is_zero_ether_addr(conf->bssid)) {
2305 switch (vif->type) {
05c914fe
JB		 2306 case NL80211_IFTYPE_STATION:
2307 case NL80211_IFTYPE_ADHOC:
8feceb67 2308 /* Set BSSID */
17d7904d
S		 2309 memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2310 sc->curaid = 0;
ba52da58 2311 ath9k_hw_write_associd(sc);
c83be688 2312
8feceb67 2313 /* Set aggregation protection mode parameters */
17d7904d 2314 sc->config.ath_aggr_prot = 0;
c83be688 2315
8feceb67 2316 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2317 "RX filter 0x%x bssid %pM aid 0x%x\n",
17d7904d 2318 rfilt, sc->curbssid, sc->curaid);
c83be688 2319
8feceb67
VT		 2320 /* need to reconfigure the beacon */
2321 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2322
8feceb67
VT		 2323 break;
2324 default:
2325 break;
2326 }
2327 }
c83be688 2328
1f7d6cbf
S		 2329 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2330 (vif->type == NL80211_IFTYPE_AP)) {
2331 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2332 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2333 conf->enable_beacon)) {
2334 /*
2335 * Allocate and setup the beacon frame.
2336 *
2337 * Stop any previous beacon DMA. This may be
2338 * necessary, for example, when an ibss merge
2339 * causes reconfiguration; we may be called
2340 * with beacon transmission active.
2341 */
2342 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2343
1f7d6cbf
S		 2344 error = ath_beacon_alloc(sc, 0);
2345 if (error != 0)
2346 return error;
c83be688 2347
1f7d6cbf
S		 2348 ath_beacon_sync(sc, 0);
2349 }
8feceb67 2350 }
c83be688 2351
8feceb67 2352 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2353 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2354 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2355 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2356 ath9k_hw_keysetmac(sc->sc_ah,
2357 (u16)i,
17d7904d 2358 sc->curbssid);
8feceb67 2359 }
c83be688 2360
8feceb67 2361 /* Only legacy IBSS for now */
05c914fe 2362 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2363 ath_update_chainmask(sc, 0);
f078f209 2364
8feceb67
VT		 2365 return 0;
2366}
f078f209 2367
8feceb67
VT		 2368#define SUPPORTED_FILTERS \
2369 (FIF_PROMISC_IN_BSS | \
2370 FIF_ALLMULTI | \
2371 FIF_CONTROL | \
2372 FIF_OTHER_BSS | \
2373 FIF_BCN_PRBRESP_PROMISC | \
2374 FIF_FCSFAIL)
c83be688 2375
8feceb67
VT		 2376/* FIXME: sc->sc_full_reset ? */
2377static void ath9k_configure_filter(struct ieee80211_hw *hw,
2378 unsigned int changed_flags,
2379 unsigned int *total_flags,
2380 int mc_count,
2381 struct dev_mc_list *mclist)
2382{
2383 struct ath_softc *sc = hw->priv;
2384 u32 rfilt;
f078f209 2385
8feceb67
VT		 2386 changed_flags &= SUPPORTED_FILTERS;
2387 *total_flags &= SUPPORTED_FILTERS;
f078f209 2388
b77f483f 2389 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2390 rfilt = ath_calcrxfilter(sc);
2391 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2392
8feceb67 2393 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
ba52da58
S		 2394 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2395 memcpy(sc->curbssid, ath_bcast_mac, ETH_ALEN);
2396 sc->curaid = 0;
2397 ath9k_hw_write_associd(sc);
2398 }
8feceb67 2399 }
f078f209 2400
b77f483f 2401 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2402}
f078f209 2403
8feceb67
VT		 2404static void ath9k_sta_notify(struct ieee80211_hw *hw,
2405 struct ieee80211_vif *vif,
2406 enum sta_notify_cmd cmd,
17741cdc 2407 struct ieee80211_sta *sta)
8feceb67
VT		 2408{
2409 struct ath_softc *sc = hw->priv;
f078f209 2410
8feceb67
VT		 2411 switch (cmd) {
2412 case STA_NOTIFY_ADD:
5640b08e 2413 ath_node_attach(sc, sta);
8feceb67
VT		 2414 break;
2415 case STA_NOTIFY_REMOVE:
b5aa9bf9 2416 ath_node_detach(sc, sta);
8feceb67
VT		 2417 break;
2418 default:
2419 break;
2420 }
f078f209
LR		 2421}
2422
141b38b6 2423static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2424 const struct ieee80211_tx_queue_params *params)
f078f209 2425{
8feceb67
VT		 2426 struct ath_softc *sc = hw->priv;
2427 struct ath9k_tx_queue_info qi;
2428 int ret = 0, qnum;
f078f209 2429
8feceb67
VT		 2430 if (queue >= WME_NUM_AC)
2431 return 0;
f078f209 2432
141b38b6
S		 2433 mutex_lock(&sc->mutex);
2434
8feceb67
VT		 2435 qi.tqi_aifs = params->aifs;
2436 qi.tqi_cwmin = params->cw_min;
2437 qi.tqi_cwmax = params->cw_max;
2438 qi.tqi_burstTime = params->txop;
2439 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2440
8feceb67 2441 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2442 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2443 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2444 queue, qnum, params->aifs, params->cw_min,
2445 params->cw_max, params->txop);
f078f209 2446
8feceb67
VT		 2447 ret = ath_txq_update(sc, qnum, &qi);
2448 if (ret)
04bd4638 2449 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2450
141b38b6
S		 2451 mutex_unlock(&sc->mutex);
2452
8feceb67
VT		 2453 return ret;
2454}
f078f209 2455
8feceb67
VT		 2456static int ath9k_set_key(struct ieee80211_hw *hw,
2457 enum set_key_cmd cmd,
dc822b5d
JB		 2458 struct ieee80211_vif *vif,
2459 struct ieee80211_sta *sta,
8feceb67
VT		 2460 struct ieee80211_key_conf *key)
2461{
2462 struct ath_softc *sc = hw->priv;
2463 int ret = 0;
f078f209 2464
141b38b6 2465 mutex_lock(&sc->mutex);
3cbb5dd7 2466 ath9k_ps_wakeup(sc);
04bd4638 2467 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2468
8feceb67
VT		 2469 switch (cmd) {
2470 case SET_KEY:
dc822b5d 2471 ret = ath_key_config(sc, sta, key);
6ace2891
JM		 2472 if (ret >= 0) {
2473 key->hw_key_idx = ret;
8feceb67
VT		 2474 /* push IV and Michael MIC generation to stack */
2475 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2476 if (key->alg == ALG_TKIP)
2477 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2478 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2479 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2480 ret = 0;
8feceb67
VT		 2481 }
2482 break;
2483 case DISABLE_KEY:
2484 ath_key_delete(sc, key);
8feceb67
VT		 2485 break;
2486 default:
2487 ret = -EINVAL;
2488 }
f078f209 2489
3cbb5dd7 2490 ath9k_ps_restore(sc);
141b38b6
S		 2491 mutex_unlock(&sc->mutex);
2492
8feceb67
VT		 2493 return ret;
2494}
f078f209 2495
8feceb67
VT		 2496static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2497 struct ieee80211_vif *vif,
2498 struct ieee80211_bss_conf *bss_conf,
2499 u32 changed)
2500{
2501 struct ath_softc *sc = hw->priv;
f078f209 2502
141b38b6
S		 2503 mutex_lock(&sc->mutex);
2504
8feceb67 2505 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2506 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2507 bss_conf->use_short_preamble);
2508 if (bss_conf->use_short_preamble)
2509 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2510 else
2511 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2512 }
f078f209 2513
8feceb67 2514 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2515 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2516 bss_conf->use_cts_prot);
2517 if (bss_conf->use_cts_prot &&
2518 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2519 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2520 else
2521 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2522 }
f078f209 2523
8feceb67 2524 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2525 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2526 bss_conf->assoc);
5640b08e 2527 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2528 }
141b38b6
S		 2529
2530 mutex_unlock(&sc->mutex);
8feceb67 2531}
f078f209 2532
8feceb67
VT		 2533static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2534{
2535 u64 tsf;
2536 struct ath_softc *sc = hw->priv;
f078f209 2537
141b38b6
S		 2538 mutex_lock(&sc->mutex);
2539 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2540 mutex_unlock(&sc->mutex);
f078f209 2541
8feceb67
VT		 2542 return tsf;
2543}
f078f209 2544
3b5d665b
AF		 2545static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2546{
2547 struct ath_softc *sc = hw->priv;
3b5d665b 2548
141b38b6
S		 2549 mutex_lock(&sc->mutex);
2550 ath9k_hw_settsf64(sc->sc_ah, tsf);
2551 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2552}
2553
8feceb67
VT		 2554static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2555{
2556 struct ath_softc *sc = hw->priv;
c83be688 2557
141b38b6
S		 2558 mutex_lock(&sc->mutex);
2559 ath9k_hw_reset_tsf(sc->sc_ah);
2560 mutex_unlock(&sc->mutex);
8feceb67 2561}
f078f209 2562
8feceb67 2563static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2564 enum ieee80211_ampdu_mlme_action action,
2565 struct ieee80211_sta *sta,
2566 u16 tid, u16 *ssn)
8feceb67
VT		 2567{
2568 struct ath_softc *sc = hw->priv;
2569 int ret = 0;
f078f209 2570
8feceb67
VT		 2571 switch (action) {
2572 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2573 if (!(sc->sc_flags & SC_OP_RXAGGR))
2574 ret = -ENOTSUPP;
8feceb67
VT		 2575 break;
2576 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2577 break;
2578 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2579 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2580 if (ret < 0)
2581 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2582 "Unable to start TX aggregation\n");
8feceb67 2583 else
17741cdc 2584 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2585 break;
2586 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2587 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2588 if (ret < 0)
2589 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2590 "Unable to stop TX aggregation\n");
f078f209 2591
17741cdc 2592 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2593 break;
8469cdef
S		 2594 case IEEE80211_AMPDU_TX_RESUME:
2595 ath_tx_aggr_resume(sc, sta, tid);
2596 break;
8feceb67 2597 default:
04bd4638 2598 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2599 }
2600
2601 return ret;
f078f209
LR		 2602}
2603
6baff7f9 2604struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2605 .tx = ath9k_tx,
2606 .start = ath9k_start,
2607 .stop = ath9k_stop,
2608 .add_interface = ath9k_add_interface,
2609 .remove_interface = ath9k_remove_interface,
2610 .config = ath9k_config,
2611 .config_interface = ath9k_config_interface,
2612 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2613 .sta_notify = ath9k_sta_notify,
2614 .conf_tx = ath9k_conf_tx,
8feceb67 2615 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2616 .set_key = ath9k_set_key,
8feceb67 2617 .get_tsf = ath9k_get_tsf,
3b5d665b 2618 .set_tsf = ath9k_set_tsf,
8feceb67 2619 .reset_tsf = ath9k_reset_tsf,
4233df6b 2620 .ampdu_action = ath9k_ampdu_action,
8feceb67
VT		 2621};
2622
392dff83
BP		 2623static struct {
2624 u32 version;
2625 const char * name;
2626} ath_mac_bb_names[] = {
2627 { AR_SREV_VERSION_5416_PCI, "5416" },
2628 { AR_SREV_VERSION_5416_PCIE, "5418" },
2629 { AR_SREV_VERSION_9100, "9100" },
2630 { AR_SREV_VERSION_9160, "9160" },
2631 { AR_SREV_VERSION_9280, "9280" },
2632 { AR_SREV_VERSION_9285, "9285" }
2633};
2634
2635static struct {
2636 u16 version;
2637 const char * name;
2638} ath_rf_names[] = {
2639 { 0, "5133" },
2640 { AR_RAD5133_SREV_MAJOR, "5133" },
2641 { AR_RAD5122_SREV_MAJOR, "5122" },
2642 { AR_RAD2133_SREV_MAJOR, "2133" },
2643 { AR_RAD2122_SREV_MAJOR, "2122" }
2644};
2645
2646/*
2647 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2648 */
6baff7f9 2649const char *
392dff83
BP		 2650ath_mac_bb_name(u32 mac_bb_version)
2651{
2652 int i;
2653
2654 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2655 if (ath_mac_bb_names[i].version == mac_bb_version) {
2656 return ath_mac_bb_names[i].name;
2657 }
2658 }
2659
2660 return "????";
2661}
2662
2663/*
2664 * Return the RF name. "????" is returned if the RF is unknown.
2665 */
6baff7f9 2666const char *
392dff83
BP		 2667ath_rf_name(u16 rf_version)
2668{
2669 int i;
2670
2671 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2672 if (ath_rf_names[i].version == rf_version) {
2673 return ath_rf_names[i].name;
2674 }
2675 }
2676
2677 return "????";
2678}
2679
6baff7f9 2680static int __init ath9k_init(void)
f078f209 2681{
ca8a8560
VT		 2682 int error;
2683
ca8a8560
VT		 2684 /* Register rate control algorithm */
2685 error = ath_rate_control_register();
2686 if (error != 0) {
2687 printk(KERN_ERR
b51bb3cd
LR		 2688 "ath9k: Unable to register rate control "
2689 "algorithm: %d\n",
ca8a8560 2690 error);
6baff7f9 2691 goto err_out;
ca8a8560
VT		 2692 }
2693
6baff7f9
GJ		 2694 error = ath_pci_init();
2695 if (error < 0) {
f078f209 2696 printk(KERN_ERR
b51bb3cd 2697 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9
GJ		 2698 error = -ENODEV;
2699 goto err_rate_unregister;
f078f209
LR		 2700 }
2701
09329d37
GJ		 2702 error = ath_ahb_init();
2703 if (error < 0) {
2704 error = -ENODEV;
2705 goto err_pci_exit;
2706 }
2707
f078f209 2708 return 0;
6baff7f9 2709
09329d37
GJ		 2710 err_pci_exit:
2711 ath_pci_exit();
2712
6baff7f9
GJ		 2713 err_rate_unregister:
2714 ath_rate_control_unregister();
2715 err_out:
2716 return error;
f078f209 2717}
6baff7f9 2718module_init(ath9k_init);
f078f209 2719
6baff7f9 2720static void __exit ath9k_exit(void)
f078f209 2721{
09329d37 2722 ath_ahb_exit();
6baff7f9 2723 ath_pci_exit();
ca8a8560 2724 ath_rate_control_unregister();
04bd4638 2725 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2726}
6baff7f9 2727module_exit(ath9k_exit);
Linux kernel - Deliverables
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