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iwl3945: report killswitch changes even if the interface is down
[deliverable/linux.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209
LR		 17#include <linux/nl80211.h>
18#include "core.h"
392dff83 19#include "reg.h"
2a163c6d 20#include "hw.h"
f078f209
LR		 21
22#define ATH_PCI_VERSION "0.1"
23
f078f209
LR		 24static char *dev_info = "ath9k";
25
26MODULE_AUTHOR("Atheros Communications");
27MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29MODULE_LICENSE("Dual BSD/GPL");
30
31static struct pci_device_id ath_pci_id_table[] __devinitdata = {
32 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
33 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
34 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
35 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
36 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
e7594072 37 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
f078f209
LR		 38 { 0 }
39};
40
9757d556
S		 41static void ath_detach(struct ath_softc *sc);
42
ff37e337
S		 43/* return bus cachesize in 4B word units */
44
45static void bus_read_cachesize(struct ath_softc *sc, int *csz)
46{
47 u8 u8tmp;
48
49 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
50 *csz = (int)u8tmp;
51
52 /*
53 * This check was put in to avoid "unplesant" consequences if
54 * the bootrom has not fully initialized all PCI devices.
55 * Sometimes the cache line size register is not set
56 */
57
58 if (*csz == 0)
59 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
60}
61
ce111bad
LR		 62static void ath_cache_conf_rate(struct ath_softc *sc,
63 struct ieee80211_conf *conf)
ff37e337 64{
030bb495
LR		 65 switch (conf->channel->band) {
66 case IEEE80211_BAND_2GHZ:
67 if (conf_is_ht20(conf))
68 sc->cur_rate_table =
69 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
70 else if (conf_is_ht40_minus(conf))
71 sc->cur_rate_table =
72 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
73 else if (conf_is_ht40_plus(conf))
74 sc->cur_rate_table =
75 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 76 else
030bb495
LR		 77 sc->cur_rate_table =
78 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 79 break;
80 case IEEE80211_BAND_5GHZ:
81 if (conf_is_ht20(conf))
82 sc->cur_rate_table =
83 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
84 else if (conf_is_ht40_minus(conf))
85 sc->cur_rate_table =
86 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
87 else if (conf_is_ht40_plus(conf))
88 sc->cur_rate_table =
89 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
90 else
96742256
LR		 91 sc->cur_rate_table =
92 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 93 break;
94 default:
ce111bad 95 BUG_ON(1);
030bb495
LR		 96 break;
97 }
ff37e337
S		 98}
99
100static void ath_update_txpow(struct ath_softc *sc)
101{
102 struct ath_hal *ah = sc->sc_ah;
103 u32 txpow;
104
105 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
106 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
107 /* read back in case value is clamped */
108 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
109 sc->sc_curtxpow = txpow;
110 }
111}
112
113static u8 parse_mpdudensity(u8 mpdudensity)
114{
115 /*
116 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
117 * 0 for no restriction
118 * 1 for 1/4 us
119 * 2 for 1/2 us
120 * 3 for 1 us
121 * 4 for 2 us
122 * 5 for 4 us
123 * 6 for 8 us
124 * 7 for 16 us
125 */
126 switch (mpdudensity) {
127 case 0:
128 return 0;
129 case 1:
130 case 2:
131 case 3:
132 /* Our lower layer calculations limit our precision to
133 1 microsecond */
134 return 1;
135 case 4:
136 return 2;
137 case 5:
138 return 4;
139 case 6:
140 return 8;
141 case 7:
142 return 16;
143 default:
144 return 0;
145 }
146}
147
148static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
149{
150 struct ath_rate_table *rate_table = NULL;
151 struct ieee80211_supported_band *sband;
152 struct ieee80211_rate *rate;
153 int i, maxrates;
154
155 switch (band) {
156 case IEEE80211_BAND_2GHZ:
157 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
158 break;
159 case IEEE80211_BAND_5GHZ:
160 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
161 break;
162 default:
163 break;
164 }
165
166 if (rate_table == NULL)
167 return;
168
169 sband = &sc->sbands[band];
170 rate = sc->rates[band];
171
172 if (rate_table->rate_cnt > ATH_RATE_MAX)
173 maxrates = ATH_RATE_MAX;
174 else
175 maxrates = rate_table->rate_cnt;
176
177 for (i = 0; i < maxrates; i++) {
178 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
179 rate[i].hw_value = rate_table->info[i].ratecode;
180 sband->n_bitrates++;
04bd4638
S		 181 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
182 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 183 }
184}
185
186static int ath_setup_channels(struct ath_softc *sc)
187{
188 struct ath_hal *ah = sc->sc_ah;
189 int nchan, i, a = 0, b = 0;
190 u8 regclassids[ATH_REGCLASSIDS_MAX];
191 u32 nregclass = 0;
192 struct ieee80211_supported_band *band_2ghz;
193 struct ieee80211_supported_band *band_5ghz;
194 struct ieee80211_channel *chan_2ghz;
195 struct ieee80211_channel *chan_5ghz;
196 struct ath9k_channel *c;
197
198 /* Fill in ah->ah_channels */
199 if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
200 regclassids, ATH_REGCLASSIDS_MAX,
201 &nregclass, CTRY_DEFAULT, false, 1)) {
202 u32 rd = ah->ah_currentRD;
203 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 204 "Unable to collect channel list; "
ff37e337 205 "regdomain likely %u country code %u\n",
04bd4638 206 rd, CTRY_DEFAULT);
ff37e337
S		 207 return -EINVAL;
208 }
209
210 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
211 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
212 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
213 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
214
215 for (i = 0; i < nchan; i++) {
216 c = &ah->ah_channels[i];
217 if (IS_CHAN_2GHZ(c)) {
218 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
219 chan_2ghz[a].center_freq = c->channel;
220 chan_2ghz[a].max_power = c->maxTxPower;
76061abb 221 c->chan = &chan_2ghz[a];
ff37e337
S		 222
223 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
224 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
225 if (c->channelFlags & CHANNEL_PASSIVE)
226 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
227
228 band_2ghz->n_channels = ++a;
229
04bd4638 230 DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
ff37e337 231 "channelFlags: 0x%x\n",
04bd4638 232 c->channel, c->channelFlags);
ff37e337
S		 233 } else if (IS_CHAN_5GHZ(c)) {
234 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
235 chan_5ghz[b].center_freq = c->channel;
236 chan_5ghz[b].max_power = c->maxTxPower;
76061abb 237 c->chan = &chan_5ghz[a];
ff37e337
S		 238
239 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
240 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
241 if (c->channelFlags & CHANNEL_PASSIVE)
242 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
243
244 band_5ghz->n_channels = ++b;
245
04bd4638 246 DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
ff37e337 247 "channelFlags: 0x%x\n",
04bd4638 248 c->channel, c->channelFlags);
ff37e337
S		 249 }
250 }
251
252 return 0;
253}
254
255/*
256 * Set/change channels. If the channel is really being changed, it's done
257 * by reseting the chip. To accomplish this we must first cleanup any pending
258 * DMA, then restart stuff.
259*/
260static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
261{
262 struct ath_hal *ah = sc->sc_ah;
263 bool fastcc = true, stopped;
030bb495 264 struct ieee80211_hw *hw = sc->hw;
ae8d2858
LR		 265 struct ieee80211_channel *channel = hw->conf.channel;
266 int r;
ff37e337
S		 267
268 if (sc->sc_flags & SC_OP_INVALID)
269 return -EIO;
270
c0d7c7af
LR		 271 /*
272 * This is only performed if the channel settings have
273 * actually changed.
274 *
275 * To switch channels clear any pending DMA operations;
276 * wait long enough for the RX fifo to drain, reset the
277 * hardware at the new frequency, and then re-enable
278 * the relevant bits of the h/w.
279 */
280 ath9k_hw_set_interrupts(ah, 0);
281 ath_draintxq(sc, false);
282 stopped = ath_stoprecv(sc);
ff37e337 283
c0d7c7af
LR		 284 /* XXX: do not flush receive queue here. We don't want
285 * to flush data frames already in queue because of
286 * changing channel. */
ff37e337 287
c0d7c7af
LR		 288 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
289 fastcc = false;
290
291 DPRINTF(sc, ATH_DBG_CONFIG,
292 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
293 sc->sc_ah->ah_curchan->channel,
294 channel->center_freq, sc->tx_chan_width);
ff37e337 295
c0d7c7af
LR		 296 spin_lock_bh(&sc->sc_resetlock);
297
298 r = ath9k_hw_reset(ah, hchan, fastcc);
299 if (r) {
300 DPRINTF(sc, ATH_DBG_FATAL,
301 "Unable to reset channel (%u Mhz) "
302 "reset status %u\n",
303 channel->center_freq, r);
304 spin_unlock_bh(&sc->sc_resetlock);
305 return r;
ff37e337 306 }
c0d7c7af
LR		 307 spin_unlock_bh(&sc->sc_resetlock);
308
309 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
310 sc->sc_flags &= ~SC_OP_FULL_RESET;
311
312 if (ath_startrecv(sc) != 0) {
313 DPRINTF(sc, ATH_DBG_FATAL,
314 "Unable to restart recv logic\n");
315 return -EIO;
316 }
317
318 ath_cache_conf_rate(sc, &hw->conf);
319 ath_update_txpow(sc);
320 ath9k_hw_set_interrupts(ah, sc->sc_imask);
ff37e337
S		 321 return 0;
322}
323
324/*
325 * This routine performs the periodic noise floor calibration function
326 * that is used to adjust and optimize the chip performance. This
327 * takes environmental changes (location, temperature) into account.
328 * When the task is complete, it reschedules itself depending on the
329 * appropriate interval that was calculated.
330 */
331static void ath_ani_calibrate(unsigned long data)
332{
333 struct ath_softc *sc;
334 struct ath_hal *ah;
335 bool longcal = false;
336 bool shortcal = false;
337 bool aniflag = false;
338 unsigned int timestamp = jiffies_to_msecs(jiffies);
339 u32 cal_interval;
340
341 sc = (struct ath_softc *)data;
342 ah = sc->sc_ah;
343
344 /*
345 * don't calibrate when we're scanning.
346 * we are most likely not on our home channel.
347 */
b77f483f 348 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
ff37e337
S		 349 return;
350
351 /* Long calibration runs independently of short calibration. */
352 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
353 longcal = true;
04bd4638 354 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
ff37e337
S		 355 sc->sc_ani.sc_longcal_timer = timestamp;
356 }
357
358 /* Short calibration applies only while sc_caldone is false */
359 if (!sc->sc_ani.sc_caldone) {
360 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
361 ATH_SHORT_CALINTERVAL) {
362 shortcal = true;
04bd4638 363 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
ff37e337
S		 364 sc->sc_ani.sc_shortcal_timer = timestamp;
365 sc->sc_ani.sc_resetcal_timer = timestamp;
366 }
367 } else {
368 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
369 ATH_RESTART_CALINTERVAL) {
c9e27d94 370 sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
ff37e337
S		 371 if (sc->sc_ani.sc_caldone)
372 sc->sc_ani.sc_resetcal_timer = timestamp;
373 }
374 }
375
376 /* Verify whether we must check ANI */
377 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
378 ATH_ANI_POLLINTERVAL) {
379 aniflag = true;
380 sc->sc_ani.sc_checkani_timer = timestamp;
381 }
382
383 /* Skip all processing if there's nothing to do. */
384 if (longcal || shortcal || aniflag) {
385 /* Call ANI routine if necessary */
386 if (aniflag)
387 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
388 ah->ah_curchan);
389
390 /* Perform calibration if necessary */
391 if (longcal || shortcal) {
392 bool iscaldone = false;
393
394 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
395 sc->sc_rx_chainmask, longcal,
396 &iscaldone)) {
397 if (longcal)
398 sc->sc_ani.sc_noise_floor =
399 ath9k_hw_getchan_noise(ah,
400 ah->ah_curchan);
401
402 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 403 "calibrate chan %u/%x nf: %d\n",
ff37e337
S		 404 ah->ah_curchan->channel,
405 ah->ah_curchan->channelFlags,
406 sc->sc_ani.sc_noise_floor);
407 } else {
408 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 409 "calibrate chan %u/%x failed\n",
ff37e337
S		 410 ah->ah_curchan->channel,
411 ah->ah_curchan->channelFlags);
412 }
413 sc->sc_ani.sc_caldone = iscaldone;
414 }
415 }
416
417 /*
418 * Set timer interval based on previous results.
419 * The interval must be the shortest necessary to satisfy ANI,
420 * short calibration and long calibration.
421 */
aac9207e
S		 422 cal_interval = ATH_LONG_CALINTERVAL;
423 if (sc->sc_ah->ah_config.enable_ani)
424 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
ff37e337
S		 425 if (!sc->sc_ani.sc_caldone)
426 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
427
428 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
429}
430
431/*
432 * Update tx/rx chainmask. For legacy association,
433 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 434 * the chainmask configuration, for bt coexistence, use
435 * the chainmask configuration even in legacy mode.
ff37e337
S		 436 */
437static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
438{
439 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
c97c92d9
VT		 440 if (is_ht ||
441 (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
ff37e337
S		 442 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
443 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
444 } else {
445 sc->sc_tx_chainmask = 1;
446 sc->sc_rx_chainmask = 1;
447 }
448
04bd4638
S		 449 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
450 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
ff37e337
S		 451}
452
453static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
454{
455 struct ath_node *an;
456
457 an = (struct ath_node *)sta->drv_priv;
458
459 if (sc->sc_flags & SC_OP_TXAGGR)
460 ath_tx_node_init(sc, an);
461
462 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
463 sta->ht_cap.ampdu_factor);
464 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
465}
466
467static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
468{
469 struct ath_node *an = (struct ath_node *)sta->drv_priv;
470
471 if (sc->sc_flags & SC_OP_TXAGGR)
472 ath_tx_node_cleanup(sc, an);
473}
474
475static void ath9k_tasklet(unsigned long data)
476{
477 struct ath_softc *sc = (struct ath_softc *)data;
478 u32 status = sc->sc_intrstatus;
479
480 if (status & ATH9K_INT_FATAL) {
481 /* need a chip reset */
482 ath_reset(sc, false);
483 return;
484 } else {
485
486 if (status &
487 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 488 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 489 ath_rx_tasklet(sc, 0);
b77f483f 490 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 491 }
492 /* XXX: optimize this */
493 if (status & ATH9K_INT_TX)
494 ath_tx_tasklet(sc);
495 }
496
497 /* re-enable hardware interrupt */
498 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
499}
500
501static irqreturn_t ath_isr(int irq, void *dev)
502{
503 struct ath_softc *sc = dev;
504 struct ath_hal *ah = sc->sc_ah;
505 enum ath9k_int status;
506 bool sched = false;
507
508 do {
509 if (sc->sc_flags & SC_OP_INVALID) {
510 /*
511 * The hardware is not ready/present, don't
512 * touch anything. Note this can happen early
513 * on if the IRQ is shared.
514 */
515 return IRQ_NONE;
516 }
517 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
518 return IRQ_NONE;
519 }
520
521 /*
522 * Figure out the reason(s) for the interrupt. Note
523 * that the hal returns a pseudo-ISR that may include
524 * bits we haven't explicitly enabled so we mask the
525 * value to insure we only process bits we requested.
526 */
527 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
528
529 status &= sc->sc_imask; /* discard unasked-for bits */
530
531 /*
532 * If there are no status bits set, then this interrupt was not
533 * for me (should have been caught above).
534 */
535 if (!status)
536 return IRQ_NONE;
537
538 sc->sc_intrstatus = status;
539
540 if (status & ATH9K_INT_FATAL) {
541 /* need a chip reset */
542 sched = true;
543 } else if (status & ATH9K_INT_RXORN) {
544 /* need a chip reset */
545 sched = true;
546 } else {
547 if (status & ATH9K_INT_SWBA) {
548 /* schedule a tasklet for beacon handling */
549 tasklet_schedule(&sc->bcon_tasklet);
550 }
551 if (status & ATH9K_INT_RXEOL) {
552 /*
553 * NB: the hardware should re-read the link when
554 * RXE bit is written, but it doesn't work
555 * at least on older hardware revs.
556 */
557 sched = true;
558 }
559
560 if (status & ATH9K_INT_TXURN)
561 /* bump tx trigger level */
562 ath9k_hw_updatetxtriglevel(ah, true);
563 /* XXX: optimize this */
564 if (status & ATH9K_INT_RX)
565 sched = true;
566 if (status & ATH9K_INT_TX)
567 sched = true;
568 if (status & ATH9K_INT_BMISS)
569 sched = true;
570 /* carrier sense timeout */
571 if (status & ATH9K_INT_CST)
572 sched = true;
573 if (status & ATH9K_INT_MIB) {
574 /*
575 * Disable interrupts until we service the MIB
576 * interrupt; otherwise it will continue to
577 * fire.
578 */
579 ath9k_hw_set_interrupts(ah, 0);
580 /*
581 * Let the hal handle the event. We assume
582 * it will clear whatever condition caused
583 * the interrupt.
584 */
585 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
586 ath9k_hw_set_interrupts(ah, sc->sc_imask);
587 }
588 if (status & ATH9K_INT_TIM_TIMER) {
589 if (!(ah->ah_caps.hw_caps &
590 ATH9K_HW_CAP_AUTOSLEEP)) {
591 /* Clear RxAbort bit so that we can
592 * receive frames */
593 ath9k_hw_setrxabort(ah, 0);
594 sched = true;
595 }
596 }
597 }
598 } while (0);
599
817e11de
S		 600 ath_debug_stat_interrupt(sc, status);
601
ff37e337
S		 602 if (sched) {
603 /* turn off every interrupt except SWBA */
604 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
605 tasklet_schedule(&sc->intr_tq);
606 }
607
608 return IRQ_HANDLED;
609}
610
f078f209
LR		 611static int ath_get_channel(struct ath_softc *sc,
612 struct ieee80211_channel *chan)
613{
614 int i;
615
616 for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
617 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
618 return i;
619 }
620
621 return -1;
622}
623
624static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 625 struct ieee80211_channel *chan,
094d05dc 626 enum nl80211_channel_type channel_type)
f078f209
LR		 627{
628 u32 chanmode = 0;
f078f209
LR		 629
630 switch (chan->band) {
631 case IEEE80211_BAND_2GHZ:
094d05dc
S		 632 switch(channel_type) {
633 case NL80211_CHAN_NO_HT:
634 case NL80211_CHAN_HT20:
f078f209 635 chanmode = CHANNEL_G_HT20;
094d05dc
S		 636 break;
637 case NL80211_CHAN_HT40PLUS:
f078f209 638 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 639 break;
640 case NL80211_CHAN_HT40MINUS:
f078f209 641 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 642 break;
643 }
f078f209
LR		 644 break;
645 case IEEE80211_BAND_5GHZ:
094d05dc
S		 646 switch(channel_type) {
647 case NL80211_CHAN_NO_HT:
648 case NL80211_CHAN_HT20:
f078f209 649 chanmode = CHANNEL_A_HT20;
094d05dc
S		 650 break;
651 case NL80211_CHAN_HT40PLUS:
f078f209 652 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 653 break;
654 case NL80211_CHAN_HT40MINUS:
f078f209 655 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 656 break;
657 }
f078f209
LR		 658 break;
659 default:
660 break;
661 }
662
663 return chanmode;
664}
665
ff37e337
S		 666static int ath_keyset(struct ath_softc *sc, u16 keyix,
667 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
668{
669 bool status;
670
671 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
672 keyix, hk, mac, false);
673
674 return status != false;
675}
f078f209 676
6ace2891 677static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
f078f209
LR		 678 struct ath9k_keyval *hk,
679 const u8 *addr)
680{
6ace2891
JM		 681 const u8 *key_rxmic;
682 const u8 *key_txmic;
f078f209 683
6ace2891
JM		 684 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
685 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 686
687 if (addr == NULL) {
688 /* Group key installation */
6ace2891
JM		 689 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
690 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 691 }
692 if (!sc->sc_splitmic) {
693 /*
694 * data key goes at first index,
695 * the hal handles the MIC keys at index+64.
696 */
697 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
698 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
6ace2891 699 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 700 }
701 /*
702 * TX key goes at first index, RX key at +32.
703 * The hal handles the MIC keys at index+64.
704 */
705 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
6ace2891 706 if (!ath_keyset(sc, keyix, hk, NULL)) {
f078f209
LR		 707 /* Txmic entry failed. No need to proceed further */
708 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 709 "Setting TX MIC Key Failed\n");
f078f209
LR		 710 return 0;
711 }
712
713 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
714 /* XXX delete tx key on failure? */
6ace2891
JM		 715 return ath_keyset(sc, keyix + 32, hk, addr);
716}
717
718static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
719{
720 int i;
721
722 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
723 if (test_bit(i, sc->sc_keymap) ||
724 test_bit(i + 64, sc->sc_keymap))
725 continue; /* At least one part of TKIP key allocated */
726 if (sc->sc_splitmic &&
727 (test_bit(i + 32, sc->sc_keymap) ||
728 test_bit(i + 64 + 32, sc->sc_keymap)))
729 continue; /* At least one part of TKIP key allocated */
730
731 /* Found a free slot for a TKIP key */
732 return i;
733 }
734 return -1;
735}
736
737static int ath_reserve_key_cache_slot(struct ath_softc *sc)
738{
739 int i;
740
741 /* First, try to find slots that would not be available for TKIP. */
742 if (sc->sc_splitmic) {
743 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
744 if (!test_bit(i, sc->sc_keymap) &&
745 (test_bit(i + 32, sc->sc_keymap) ||
746 test_bit(i + 64, sc->sc_keymap) ||
747 test_bit(i + 64 + 32, sc->sc_keymap)))
748 return i;
749 if (!test_bit(i + 32, sc->sc_keymap) &&
750 (test_bit(i, sc->sc_keymap) ||
751 test_bit(i + 64, sc->sc_keymap) ||
752 test_bit(i + 64 + 32, sc->sc_keymap)))
753 return i + 32;
754 if (!test_bit(i + 64, sc->sc_keymap) &&
755 (test_bit(i , sc->sc_keymap) ||
756 test_bit(i + 32, sc->sc_keymap) ||
757 test_bit(i + 64 + 32, sc->sc_keymap)))
ea612132 758 return i + 64;
6ace2891
JM		 759 if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
760 (test_bit(i, sc->sc_keymap) ||
761 test_bit(i + 32, sc->sc_keymap) ||
762 test_bit(i + 64, sc->sc_keymap)))
ea612132 763 return i + 64 + 32;
6ace2891
JM		 764 }
765 } else {
766 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
767 if (!test_bit(i, sc->sc_keymap) &&
768 test_bit(i + 64, sc->sc_keymap))
769 return i;
770 if (test_bit(i, sc->sc_keymap) &&
771 !test_bit(i + 64, sc->sc_keymap))
772 return i + 64;
773 }
774 }
775
776 /* No partially used TKIP slots, pick any available slot */
777 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
be2864cf
JM		 778 /* Do not allow slots that could be needed for TKIP group keys
779 * to be used. This limitation could be removed if we know that
780 * TKIP will not be used. */
781 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
782 continue;
783 if (sc->sc_splitmic) {
784 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
785 continue;
786 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
787 continue;
788 }
789
6ace2891
JM		 790 if (!test_bit(i, sc->sc_keymap))
791 return i; /* Found a free slot for a key */
792 }
793
794 /* No free slot found */
795 return -1;
f078f209
LR		 796}
797
798static int ath_key_config(struct ath_softc *sc,
dc822b5d 799 struct ieee80211_sta *sta,
f078f209
LR		 800 struct ieee80211_key_conf *key)
801{
f078f209
LR		 802 struct ath9k_keyval hk;
803 const u8 *mac = NULL;
804 int ret = 0;
6ace2891 805 int idx;
f078f209
LR		 806
807 memset(&hk, 0, sizeof(hk));
808
809 switch (key->alg) {
810 case ALG_WEP:
811 hk.kv_type = ATH9K_CIPHER_WEP;
812 break;
813 case ALG_TKIP:
814 hk.kv_type = ATH9K_CIPHER_TKIP;
815 break;
816 case ALG_CCMP:
817 hk.kv_type = ATH9K_CIPHER_AES_CCM;
818 break;
819 default:
ca470b29 820 return -EOPNOTSUPP;
f078f209
LR		 821 }
822
6ace2891 823 hk.kv_len = key->keylen;
f078f209
LR		 824 memcpy(hk.kv_val, key->key, key->keylen);
825
6ace2891
JM		 826 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
827 /* For now, use the default keys for broadcast keys. This may
828 * need to change with virtual interfaces. */
829 idx = key->keyidx;
830 } else if (key->keyidx) {
831 struct ieee80211_vif *vif;
f078f209 832
dc822b5d
JB		 833 if (WARN_ON(!sta))
834 return -EOPNOTSUPP;
835 mac = sta->addr;
836
6ace2891
JM		 837 vif = sc->sc_vaps[0];
838 if (vif->type != NL80211_IFTYPE_AP) {
839 /* Only keyidx 0 should be used with unicast key, but
840 * allow this for client mode for now. */
841 idx = key->keyidx;
842 } else
843 return -EIO;
f078f209 844 } else {
dc822b5d
JB		 845 if (WARN_ON(!sta))
846 return -EOPNOTSUPP;
847 mac = sta->addr;
848
6ace2891
JM		 849 if (key->alg == ALG_TKIP)
850 idx = ath_reserve_key_cache_slot_tkip(sc);
851 else
852 idx = ath_reserve_key_cache_slot(sc);
853 if (idx < 0)
ca470b29 854 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 855 }
856
857 if (key->alg == ALG_TKIP)
6ace2891 858 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
f078f209 859 else
6ace2891 860 ret = ath_keyset(sc, idx, &hk, mac);
f078f209
LR		 861
862 if (!ret)
863 return -EIO;
864
6ace2891
JM		 865 set_bit(idx, sc->sc_keymap);
866 if (key->alg == ALG_TKIP) {
867 set_bit(idx + 64, sc->sc_keymap);
868 if (sc->sc_splitmic) {
869 set_bit(idx + 32, sc->sc_keymap);
870 set_bit(idx + 64 + 32, sc->sc_keymap);
871 }
872 }
873
874 return idx;
f078f209
LR		 875}
876
877static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
878{
6ace2891
JM		 879 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
880 if (key->hw_key_idx < IEEE80211_WEP_NKID)
881 return;
882
883 clear_bit(key->hw_key_idx, sc->sc_keymap);
884 if (key->alg != ALG_TKIP)
885 return;
f078f209 886
6ace2891
JM		 887 clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
888 if (sc->sc_splitmic) {
889 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
890 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
891 }
f078f209
LR		 892}
893
d9fe60de 894static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
f078f209 895{
60653678
S		 896#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
897#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 898
d9fe60de
JB		 899 ht_info->ht_supported = true;
900 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
901 IEEE80211_HT_CAP_SM_PS |
902 IEEE80211_HT_CAP_SGI_40 |
903 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 904
60653678
S		 905 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
906 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
d9fe60de
JB		 907 /* set up supported mcs set */
908 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
909 ht_info->mcs.rx_mask[0] = 0xff;
910 ht_info->mcs.rx_mask[1] = 0xff;
911 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 912}
913
8feceb67 914static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 915 struct ieee80211_vif *vif,
8feceb67 916 struct ieee80211_bss_conf *bss_conf)
f078f209 917{
5640b08e 918 struct ath_vap *avp = (void *)vif->drv_priv;
f078f209 919
8feceb67 920 if (bss_conf->assoc) {
094d05dc
S		 921 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
922 bss_conf->aid, sc->sc_curbssid);
f078f209 923
8feceb67 924 /* New association, store aid */
d97809db 925 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
8feceb67
VT		 926 sc->sc_curaid = bss_conf->aid;
927 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
928 sc->sc_curaid);
929 }
f078f209 930
8feceb67
VT		 931 /* Configure the beacon */
932 ath_beacon_config(sc, 0);
933 sc->sc_flags |= SC_OP_BEACONS;
f078f209 934
8feceb67
VT		 935 /* Reset rssi stats */
936 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
937 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
938 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
939 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 940
6f255425
LR		 941 /* Start ANI */
942 mod_timer(&sc->sc_ani.timer,
943 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
944
8feceb67 945 } else {
04bd4638 946 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
8feceb67 947 sc->sc_curaid = 0;
f078f209 948 }
8feceb67 949}
f078f209 950
8feceb67
VT		 951/********************************/
952/* LED functions */
953/********************************/
f078f209 954
8feceb67
VT		 955static void ath_led_brightness(struct led_classdev *led_cdev,
956 enum led_brightness brightness)
957{
958 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
959 struct ath_softc *sc = led->sc;
f078f209 960
8feceb67
VT		 961 switch (brightness) {
962 case LED_OFF:
963 if (led->led_type == ATH_LED_ASSOC ||
964 led->led_type == ATH_LED_RADIO)
965 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
966 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
967 (led->led_type == ATH_LED_RADIO) ? 1 :
968 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
969 break;
970 case LED_FULL:
971 if (led->led_type == ATH_LED_ASSOC)
972 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
973 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
974 break;
975 default:
976 break;
f078f209 977 }
8feceb67 978}
f078f209 979
8feceb67
VT		 980static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
981 char *trigger)
982{
983 int ret;
f078f209 984
8feceb67
VT		 985 led->sc = sc;
986 led->led_cdev.name = led->name;
987 led->led_cdev.default_trigger = trigger;
988 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 989
8feceb67
VT		 990 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
991 if (ret)
992 DPRINTF(sc, ATH_DBG_FATAL,
993 "Failed to register led:%s", led->name);
994 else
995 led->registered = 1;
996 return ret;
997}
f078f209 998
8feceb67
VT		 999static void ath_unregister_led(struct ath_led *led)
1000{
1001 if (led->registered) {
1002 led_classdev_unregister(&led->led_cdev);
1003 led->registered = 0;
f078f209 1004 }
f078f209
LR		 1005}
1006
8feceb67 1007static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1008{
8feceb67
VT		 1009 ath_unregister_led(&sc->assoc_led);
1010 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1011 ath_unregister_led(&sc->tx_led);
1012 ath_unregister_led(&sc->rx_led);
1013 ath_unregister_led(&sc->radio_led);
1014 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1015}
f078f209 1016
8feceb67
VT		 1017static void ath_init_leds(struct ath_softc *sc)
1018{
1019 char *trigger;
1020 int ret;
f078f209 1021
8feceb67
VT		 1022 /* Configure gpio 1 for output */
1023 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1024 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1025 /* LED off, active low */
1026 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1027
8feceb67
VT		 1028 trigger = ieee80211_get_radio_led_name(sc->hw);
1029 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1030 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1031 ret = ath_register_led(sc, &sc->radio_led, trigger);
1032 sc->radio_led.led_type = ATH_LED_RADIO;
1033 if (ret)
1034 goto fail;
7dcfdcd9 1035
8feceb67
VT		 1036 trigger = ieee80211_get_assoc_led_name(sc->hw);
1037 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1038 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1039 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1040 sc->assoc_led.led_type = ATH_LED_ASSOC;
1041 if (ret)
1042 goto fail;
f078f209 1043
8feceb67
VT		 1044 trigger = ieee80211_get_tx_led_name(sc->hw);
1045 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1046 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1047 ret = ath_register_led(sc, &sc->tx_led, trigger);
1048 sc->tx_led.led_type = ATH_LED_TX;
1049 if (ret)
1050 goto fail;
f078f209 1051
8feceb67
VT		 1052 trigger = ieee80211_get_rx_led_name(sc->hw);
1053 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1054 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1055 ret = ath_register_led(sc, &sc->rx_led, trigger);
1056 sc->rx_led.led_type = ATH_LED_RX;
1057 if (ret)
1058 goto fail;
f078f209 1059
8feceb67
VT		 1060 return;
1061
1062fail:
1063 ath_deinit_leds(sc);
f078f209
LR		 1064}
1065
e97275cb 1066#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1067
500c064d
VT		 1068/*******************/
1069/* Rfkill */
1070/*******************/
1071
1072static void ath_radio_enable(struct ath_softc *sc)
1073{
1074 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1075 struct ieee80211_channel *channel = sc->hw->conf.channel;
1076 int r;
500c064d
VT		 1077
1078 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1079
1080 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1081
1082 if (r) {
500c064d 1083 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1084 "Unable to reset channel %u (%uMhz) ",
1085 "reset status %u\n",
1086 channel->center_freq, r);
500c064d
VT		 1087 }
1088 spin_unlock_bh(&sc->sc_resetlock);
1089
1090 ath_update_txpow(sc);
1091 if (ath_startrecv(sc) != 0) {
1092 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1093 "Unable to restart recv logic\n");
500c064d
VT		 1094 return;
1095 }
1096
1097 if (sc->sc_flags & SC_OP_BEACONS)
1098 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1099
1100 /* Re-Enable interrupts */
1101 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1102
1103 /* Enable LED */
1104 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1105 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1106 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1107
1108 ieee80211_wake_queues(sc->hw);
1109}
1110
1111static void ath_radio_disable(struct ath_softc *sc)
1112{
1113 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1114 struct ieee80211_channel *channel = sc->hw->conf.channel;
1115 int r;
500c064d
VT		 1116
1117 ieee80211_stop_queues(sc->hw);
1118
1119 /* Disable LED */
1120 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1121 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1122
1123 /* Disable interrupts */
1124 ath9k_hw_set_interrupts(ah, 0);
1125
1126 ath_draintxq(sc, false); /* clear pending tx frames */
1127 ath_stoprecv(sc); /* turn off frame recv */
1128 ath_flushrecv(sc); /* flush recv queue */
1129
1130 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1131 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1132 if (r) {
500c064d 1133 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1134 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1135 "reset status %u\n",
1136 channel->center_freq, r);
500c064d
VT		 1137 }
1138 spin_unlock_bh(&sc->sc_resetlock);
1139
1140 ath9k_hw_phy_disable(ah);
1141 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1142}
1143
1144static bool ath_is_rfkill_set(struct ath_softc *sc)
1145{
1146 struct ath_hal *ah = sc->sc_ah;
1147
1148 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1149 ah->ah_rfkill_polarity;
1150}
1151
1152/* h/w rfkill poll function */
1153static void ath_rfkill_poll(struct work_struct *work)
1154{
1155 struct ath_softc *sc = container_of(work, struct ath_softc,
1156 rf_kill.rfkill_poll.work);
1157 bool radio_on;
1158
1159 if (sc->sc_flags & SC_OP_INVALID)
1160 return;
1161
1162 radio_on = !ath_is_rfkill_set(sc);
1163
1164 /*
1165 * enable/disable radio only when there is a
1166 * state change in RF switch
1167 */
1168 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1169 enum rfkill_state state;
1170
1171 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1172 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1173 : RFKILL_STATE_HARD_BLOCKED;
1174 } else if (radio_on) {
1175 ath_radio_enable(sc);
1176 state = RFKILL_STATE_UNBLOCKED;
1177 } else {
1178 ath_radio_disable(sc);
1179 state = RFKILL_STATE_HARD_BLOCKED;
1180 }
1181
1182 if (state == RFKILL_STATE_HARD_BLOCKED)
1183 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1184 else
1185 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1186
1187 rfkill_force_state(sc->rf_kill.rfkill, state);
1188 }
1189
1190 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1191 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1192}
1193
1194/* s/w rfkill handler */
1195static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1196{
1197 struct ath_softc *sc = data;
1198
1199 switch (state) {
1200 case RFKILL_STATE_SOFT_BLOCKED:
1201 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1202 SC_OP_RFKILL_SW_BLOCKED)))
1203 ath_radio_disable(sc);
1204 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1205 return 0;
1206 case RFKILL_STATE_UNBLOCKED:
1207 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1208 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1209 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1210 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1211 "radio as it is disabled by h/w\n");
500c064d
VT		 1212 return -EPERM;
1213 }
1214 ath_radio_enable(sc);
1215 }
1216 return 0;
1217 default:
1218 return -EINVAL;
1219 }
1220}
1221
1222/* Init s/w rfkill */
1223static int ath_init_sw_rfkill(struct ath_softc *sc)
1224{
1225 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1226 RFKILL_TYPE_WLAN);
1227 if (!sc->rf_kill.rfkill) {
1228 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1229 return -ENOMEM;
1230 }
1231
1232 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1233 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1234 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1235 sc->rf_kill.rfkill->data = sc;
1236 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1237 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1238 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1239
1240 return 0;
1241}
1242
1243/* Deinitialize rfkill */
1244static void ath_deinit_rfkill(struct ath_softc *sc)
1245{
1246 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1247 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1248
1249 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1250 rfkill_unregister(sc->rf_kill.rfkill);
1251 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1252 sc->rf_kill.rfkill = NULL;
1253 }
1254}
9c84b797
S		 1255
1256static int ath_start_rfkill_poll(struct ath_softc *sc)
1257{
1258 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1259 queue_delayed_work(sc->hw->workqueue,
1260 &sc->rf_kill.rfkill_poll, 0);
1261
1262 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1263 if (rfkill_register(sc->rf_kill.rfkill)) {
1264 DPRINTF(sc, ATH_DBG_FATAL,
1265 "Unable to register rfkill\n");
1266 rfkill_free(sc->rf_kill.rfkill);
1267
1268 /* Deinitialize the device */
306efdd1 1269 ath_detach(sc);
9c84b797
S		 1270 if (sc->pdev->irq)
1271 free_irq(sc->pdev->irq, sc);
9c84b797
S		 1272 pci_iounmap(sc->pdev, sc->mem);
1273 pci_release_region(sc->pdev, 0);
1274 pci_disable_device(sc->pdev);
9757d556 1275 ieee80211_free_hw(sc->hw);
9c84b797
S		 1276 return -EIO;
1277 } else {
1278 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1279 }
1280 }
1281
1282 return 0;
1283}
500c064d
VT		 1284#endif /* CONFIG_RFKILL */
1285
9c84b797 1286static void ath_detach(struct ath_softc *sc)
f078f209 1287{
8feceb67 1288 struct ieee80211_hw *hw = sc->hw;
9c84b797 1289 int i = 0;
f078f209 1290
04bd4638 1291 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1292
e97275cb 1293#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1294 ath_deinit_rfkill(sc);
1295#endif
3fcdfb4b
VT		 1296 ath_deinit_leds(sc);
1297
1298 ieee80211_unregister_hw(hw);
8feceb67
VT		 1299 ath_rx_cleanup(sc);
1300 ath_tx_cleanup(sc);
f078f209 1301
9c84b797
S		 1302 tasklet_kill(&sc->intr_tq);
1303 tasklet_kill(&sc->bcon_tasklet);
f078f209 1304
9c84b797
S		 1305 if (!(sc->sc_flags & SC_OP_INVALID))
1306 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1307
9c84b797
S		 1308 /* cleanup tx queues */
1309 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1310 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1311 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1312
1313 ath9k_hw_detach(sc->sc_ah);
826d2680 1314 ath9k_exit_debug(sc);
f078f209
LR		 1315}
1316
ff37e337
S		 1317static int ath_init(u16 devid, struct ath_softc *sc)
1318{
1319 struct ath_hal *ah = NULL;
1320 int status;
1321 int error = 0, i;
1322 int csz = 0;
1323
1324 /* XXX: hardware will not be ready until ath_open() being called */
1325 sc->sc_flags |= SC_OP_INVALID;
88b126af 1326
826d2680
S		 1327 if (ath9k_init_debug(sc) < 0)
1328 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S		 1329
1330 spin_lock_init(&sc->sc_resetlock);
aa33de09 1331 mutex_init(&sc->mutex);
ff37e337
S		 1332 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1333 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1334 (unsigned long)sc);
1335
1336 /*
1337 * Cache line size is used to size and align various
1338 * structures used to communicate with the hardware.
1339 */
1340 bus_read_cachesize(sc, &csz);
1341 /* XXX assert csz is non-zero */
1342 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1343
1344 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1345 if (ah == NULL) {
1346 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1347 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1348 error = -ENXIO;
1349 goto bad;
1350 }
1351 sc->sc_ah = ah;
1352
1353 /* Get the hardware key cache size. */
1354 sc->sc_keymax = ah->ah_caps.keycache_size;
1355 if (sc->sc_keymax > ATH_KEYMAX) {
1356 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638
S		 1357 "Warning, using only %u entries in %u key cache\n",
1358 ATH_KEYMAX, sc->sc_keymax);
ff37e337
S		 1359 sc->sc_keymax = ATH_KEYMAX;
1360 }
1361
1362 /*
1363 * Reset the key cache since some parts do not
1364 * reset the contents on initial power up.
1365 */
1366 for (i = 0; i < sc->sc_keymax; i++)
1367 ath9k_hw_keyreset(ah, (u16) i);
ff37e337
S		 1368
1369 /* Collect the channel list using the default country code */
1370
1371 error = ath_setup_channels(sc);
1372 if (error)
1373 goto bad;
1374
1375 /* default to MONITOR mode */
d97809db
CM		 1376 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1377
ff37e337
S		 1378
1379 /* Setup rate tables */
1380
1381 ath_rate_attach(sc);
1382 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1383 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1384
1385 /*
1386 * Allocate hardware transmit queues: one queue for
1387 * beacon frames and one data queue for each QoS
1388 * priority. Note that the hal handles reseting
1389 * these queues at the needed time.
1390 */
b77f483f
S		 1391 sc->beacon.beaconq = ath_beaconq_setup(ah);
1392 if (sc->beacon.beaconq == -1) {
ff37e337 1393 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1394 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1395 error = -EIO;
1396 goto bad2;
1397 }
b77f483f
S		 1398 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1399 if (sc->beacon.cabq == NULL) {
ff37e337 1400 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1401 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1402 error = -EIO;
1403 goto bad2;
1404 }
1405
1406 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1407 ath_cabq_update(sc);
1408
b77f483f
S		 1409 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1410 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1411
1412 /* Setup data queues */
1413 /* NB: ensure BK queue is the lowest priority h/w queue */
1414 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1415 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1416 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1417 error = -EIO;
1418 goto bad2;
1419 }
1420
1421 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1422 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1423 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1424 error = -EIO;
1425 goto bad2;
1426 }
1427 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1428 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1429 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1430 error = -EIO;
1431 goto bad2;
1432 }
1433 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1434 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1435 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1436 error = -EIO;
1437 goto bad2;
1438 }
1439
1440 /* Initializes the noise floor to a reasonable default value.
1441 * Later on this will be updated during ANI processing. */
1442
1443 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1444 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1445
1446 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1447 ATH9K_CIPHER_TKIP, NULL)) {
1448 /*
1449 * Whether we should enable h/w TKIP MIC.
1450 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1451 * report WMM capable, so it's always safe to turn on
1452 * TKIP MIC in this case.
1453 */
1454 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1455 0, 1, NULL);
1456 }
1457
1458 /*
1459 * Check whether the separate key cache entries
1460 * are required to handle both tx+rx MIC keys.
1461 * With split mic keys the number of stations is limited
1462 * to 27 otherwise 59.
1463 */
1464 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1465 ATH9K_CIPHER_TKIP, NULL)
1466 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1467 ATH9K_CIPHER_MIC, NULL)
1468 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1469 0, NULL))
1470 sc->sc_splitmic = 1;
1471
1472 /* turn on mcast key search if possible */
1473 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1474 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1475 1, NULL);
1476
1477 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1478 sc->sc_config.txpowlimit_override = 0;
1479
1480 /* 11n Capabilities */
1481 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1482 sc->sc_flags |= SC_OP_TXAGGR;
1483 sc->sc_flags |= SC_OP_RXAGGR;
1484 }
1485
1486 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1487 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1488
1489 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1490 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337
S		 1491
1492 ath9k_hw_getmac(ah, sc->sc_myaddr);
1493 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1494 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1495 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1496 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1497 }
1498
b77f483f 1499 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1500
1501 /* initialize beacon slots */
b77f483f
S		 1502 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1503 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
ff37e337
S		 1504
1505 /* save MISC configurations */
1506 sc->sc_config.swBeaconProcess = 1;
1507
ff37e337
S		 1508 /* setup channels and rates */
1509
1510 sc->sbands[IEEE80211_BAND_2GHZ].channels =
1511 sc->channels[IEEE80211_BAND_2GHZ];
1512 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1513 sc->rates[IEEE80211_BAND_2GHZ];
1514 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1515
1516 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1517 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1518 sc->channels[IEEE80211_BAND_5GHZ];
1519 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1520 sc->rates[IEEE80211_BAND_5GHZ];
1521 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1522 }
1523
c97c92d9
VT		 1524 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1525 ath9k_hw_btcoex_enable(sc->sc_ah);
1526
ff37e337
S		 1527 return 0;
1528bad2:
1529 /* cleanup tx queues */
1530 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1531 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1532 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1533bad:
1534 if (ah)
1535 ath9k_hw_detach(ah);
1536
1537 return error;
1538}
1539
9c84b797 1540static int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1541{
8feceb67
VT		 1542 struct ieee80211_hw *hw = sc->hw;
1543 int error = 0;
f078f209 1544
04bd4638 1545 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1546
8feceb67
VT		 1547 error = ath_init(devid, sc);
1548 if (error != 0)
1549 return error;
f078f209 1550
8feceb67 1551 /* get mac address from hardware and set in mac80211 */
f078f209 1552
8feceb67 1553 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
f078f209 1554
9c84b797
S		 1555 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1556 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1557 IEEE80211_HW_SIGNAL_DBM |
1558 IEEE80211_HW_AMPDU_AGGREGATION;
f078f209 1559
0ced0e17
JM		 1560 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1561 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1562
9c84b797
S		 1563 hw->wiphy->interface_modes =
1564 BIT(NL80211_IFTYPE_AP) |
1565 BIT(NL80211_IFTYPE_STATION) |
1566 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1567
8feceb67 1568 hw->queues = 4;
e63835b0
S		 1569 hw->max_rates = 4;
1570 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1571 hw->sta_data_size = sizeof(struct ath_node);
5640b08e 1572 hw->vif_data_size = sizeof(struct ath_vap);
f078f209 1573
8feceb67 1574 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1575
9c84b797
S		 1576 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1577 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1578 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1579 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1580 }
1581
1582 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1583 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1584 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1585 &sc->sbands[IEEE80211_BAND_5GHZ];
1586
db93e7b5
SB		 1587 /* initialize tx/rx engine */
1588 error = ath_tx_init(sc, ATH_TXBUF);
1589 if (error != 0)
1590 goto detach;
8feceb67 1591
db93e7b5
SB		 1592 error = ath_rx_init(sc, ATH_RXBUF);
1593 if (error != 0)
1594 goto detach;
8feceb67 1595
e97275cb 1596#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1597 /* Initialze h/w Rfkill */
1598 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1599 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1600
1601 /* Initialize s/w rfkill */
1602 if (ath_init_sw_rfkill(sc))
1603 goto detach;
1604#endif
1605
db93e7b5 1606 error = ieee80211_register_hw(hw);
8feceb67 1607
db93e7b5
SB		 1608 /* Initialize LED control */
1609 ath_init_leds(sc);
8feceb67
VT		 1610
1611 return 0;
1612detach:
1613 ath_detach(sc);
8feceb67 1614 return error;
f078f209
LR		 1615}
1616
ff37e337
S		 1617int ath_reset(struct ath_softc *sc, bool retry_tx)
1618{
1619 struct ath_hal *ah = sc->sc_ah;
030bb495 1620 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1621 int r;
ff37e337
S		 1622
1623 ath9k_hw_set_interrupts(ah, 0);
1624 ath_draintxq(sc, retry_tx);
1625 ath_stoprecv(sc);
1626 ath_flushrecv(sc);
1627
1628 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1629 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1630 if (r)
ff37e337 1631 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1632 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1633 spin_unlock_bh(&sc->sc_resetlock);
1634
1635 if (ath_startrecv(sc) != 0)
04bd4638 1636 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1637
1638 /*
1639 * We may be doing a reset in response to a request
1640 * that changes the channel so update any state that
1641 * might change as a result.
1642 */
ce111bad 1643 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1644
1645 ath_update_txpow(sc);
1646
1647 if (sc->sc_flags & SC_OP_BEACONS)
1648 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1649
1650 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1651
1652 if (retry_tx) {
1653 int i;
1654 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1655 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1656 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1657 ath_txq_schedule(sc, &sc->tx.txq[i]);
1658 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1659 }
1660 }
1661 }
1662
ae8d2858 1663 return r;
ff37e337
S		 1664}
1665
1666/*
1667 * This function will allocate both the DMA descriptor structure, and the
1668 * buffers it contains. These are used to contain the descriptors used
1669 * by the system.
1670*/
1671int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1672 struct list_head *head, const char *name,
1673 int nbuf, int ndesc)
1674{
1675#define DS2PHYS(_dd, _ds) \
1676 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1677#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1678#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1679
1680 struct ath_desc *ds;
1681 struct ath_buf *bf;
1682 int i, bsize, error;
1683
04bd4638
S		 1684 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1685 name, nbuf, ndesc);
ff37e337
S		 1686
1687 /* ath_desc must be a multiple of DWORDs */
1688 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1689 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1690 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1691 error = -ENOMEM;
1692 goto fail;
1693 }
1694
1695 dd->dd_name = name;
1696 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1697
1698 /*
1699 * Need additional DMA memory because we can't use
1700 * descriptors that cross the 4K page boundary. Assume
1701 * one skipped descriptor per 4K page.
1702 */
1703 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1704 u32 ndesc_skipped =
1705 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1706 u32 dma_len;
1707
1708 while (ndesc_skipped) {
1709 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1710 dd->dd_desc_len += dma_len;
1711
1712 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1713 };
1714 }
1715
1716 /* allocate descriptors */
1717 dd->dd_desc = pci_alloc_consistent(sc->pdev,
1718 dd->dd_desc_len,
1719 &dd->dd_desc_paddr);
1720 if (dd->dd_desc == NULL) {
1721 error = -ENOMEM;
1722 goto fail;
1723 }
1724 ds = dd->dd_desc;
04bd4638
S		 1725 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1726 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1727 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1728
1729 /* allocate buffers */
1730 bsize = sizeof(struct ath_buf) * nbuf;
1731 bf = kmalloc(bsize, GFP_KERNEL);
1732 if (bf == NULL) {
1733 error = -ENOMEM;
1734 goto fail2;
1735 }
1736 memset(bf, 0, bsize);
1737 dd->dd_bufptr = bf;
1738
1739 INIT_LIST_HEAD(head);
1740 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1741 bf->bf_desc = ds;
1742 bf->bf_daddr = DS2PHYS(dd, ds);
1743
1744 if (!(sc->sc_ah->ah_caps.hw_caps &
1745 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1746 /*
1747 * Skip descriptor addresses which can cause 4KB
1748 * boundary crossing (addr + length) with a 32 dword
1749 * descriptor fetch.
1750 */
1751 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1752 ASSERT((caddr_t) bf->bf_desc <
1753 ((caddr_t) dd->dd_desc +
1754 dd->dd_desc_len));
1755
1756 ds += ndesc;
1757 bf->bf_desc = ds;
1758 bf->bf_daddr = DS2PHYS(dd, ds);
1759 }
1760 }
1761 list_add_tail(&bf->list, head);
1762 }
1763 return 0;
1764fail2:
1765 pci_free_consistent(sc->pdev,
1766 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1767fail:
1768 memset(dd, 0, sizeof(*dd));
1769 return error;
1770#undef ATH_DESC_4KB_BOUND_CHECK
1771#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1772#undef DS2PHYS
1773}
1774
1775void ath_descdma_cleanup(struct ath_softc *sc,
1776 struct ath_descdma *dd,
1777 struct list_head *head)
1778{
1779 pci_free_consistent(sc->pdev,
1780 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1781
1782 INIT_LIST_HEAD(head);
1783 kfree(dd->dd_bufptr);
1784 memset(dd, 0, sizeof(*dd));
1785}
1786
1787int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1788{
1789 int qnum;
1790
1791 switch (queue) {
1792 case 0:
b77f483f 1793 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1794 break;
1795 case 1:
b77f483f 1796 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1797 break;
1798 case 2:
b77f483f 1799 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1800 break;
1801 case 3:
b77f483f 1802 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1803 break;
1804 default:
b77f483f 1805 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1806 break;
1807 }
1808
1809 return qnum;
1810}
1811
1812int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1813{
1814 int qnum;
1815
1816 switch (queue) {
1817 case ATH9K_WME_AC_VO:
1818 qnum = 0;
1819 break;
1820 case ATH9K_WME_AC_VI:
1821 qnum = 1;
1822 break;
1823 case ATH9K_WME_AC_BE:
1824 qnum = 2;
1825 break;
1826 case ATH9K_WME_AC_BK:
1827 qnum = 3;
1828 break;
1829 default:
1830 qnum = -1;
1831 break;
1832 }
1833
1834 return qnum;
1835}
1836
1837/**********************/
1838/* mac80211 callbacks */
1839/**********************/
1840
8feceb67 1841static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR		 1842{
1843 struct ath_softc *sc = hw->priv;
8feceb67 1844 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1845 struct ath9k_channel *init_channel;
ae8d2858 1846 int r, pos;
f078f209 1847
04bd4638
S		 1848 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1849 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1850
8feceb67 1851 /* setup initial channel */
f078f209 1852
8feceb67
VT		 1853 pos = ath_get_channel(sc, curchan);
1854 if (pos == -1) {
04bd4638 1855 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
ae8d2858 1856 return -EINVAL;
f078f209
LR		 1857 }
1858
99405f93 1859 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
8feceb67
VT		 1860 sc->sc_ah->ah_channels[pos].chanmode =
1861 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
ff37e337
S		 1862 init_channel = &sc->sc_ah->ah_channels[pos];
1863
1864 /* Reset SERDES registers */
1865 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1866
1867 /*
1868 * The basic interface to setting the hardware in a good
1869 * state is ``reset''. On return the hardware is known to
1870 * be powered up and with interrupts disabled. This must
1871 * be followed by initialization of the appropriate bits
1872 * and then setup of the interrupt mask.
1873 */
1874 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1875 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1876 if (r) {
ff37e337 1877 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1878 "Unable to reset hardware; reset status %u "
1879 "(freq %u MHz)\n", r,
1880 curchan->center_freq);
ff37e337 1881 spin_unlock_bh(&sc->sc_resetlock);
ae8d2858 1882 return r;
ff37e337
S		 1883 }
1884 spin_unlock_bh(&sc->sc_resetlock);
1885
1886 /*
1887 * This is needed only to setup initial state
1888 * but it's best done after a reset.
1889 */
1890 ath_update_txpow(sc);
8feceb67 1891
ff37e337
S		 1892 /*
1893 * Setup the hardware after reset:
1894 * The receive engine is set going.
1895 * Frame transmit is handled entirely
1896 * in the frame output path; there's nothing to do
1897 * here except setup the interrupt mask.
1898 */
1899 if (ath_startrecv(sc) != 0) {
8feceb67 1900 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1901 "Unable to start recv logic\n");
ae8d2858 1902 return -EIO;
f078f209 1903 }
8feceb67 1904
ff37e337
S		 1905 /* Setup our intr mask. */
1906 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1907 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1908 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1909
1910 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1911 sc->sc_imask |= ATH9K_INT_GTT;
1912
1913 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1914 sc->sc_imask |= ATH9K_INT_CST;
1915
1916 /*
1917 * Enable MIB interrupts when there are hardware phy counters.
1918 * Note we only do this (at the moment) for station mode.
1919 */
1920 if (ath9k_hw_phycounters(sc->sc_ah) &&
d97809db
CM		 1921 ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1922 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
ff37e337
S		 1923 sc->sc_imask |= ATH9K_INT_MIB;
1924 /*
1925 * Some hardware processes the TIM IE and fires an
1926 * interrupt when the TIM bit is set. For hardware
1927 * that does, if not overridden by configuration,
1928 * enable the TIM interrupt when operating as station.
1929 */
1930 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
d97809db 1931 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
ff37e337
S		 1932 !sc->sc_config.swBeaconProcess)
1933 sc->sc_imask |= ATH9K_INT_TIM;
1934
ce111bad 1935 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1936
1937 sc->sc_flags &= ~SC_OP_INVALID;
1938
1939 /* Disable BMISS interrupt when we're not associated */
1940 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1941 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1942
1943 ieee80211_wake_queues(sc->hw);
1944
e97275cb 1945#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 1946 r = ath_start_rfkill_poll(sc);
500c064d 1947#endif
ae8d2858 1948 return r;
f078f209
LR		 1949}
1950
8feceb67
VT		 1951static int ath9k_tx(struct ieee80211_hw *hw,
1952 struct sk_buff *skb)
f078f209 1953{
528f0c6b 1954 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 1955 struct ath_softc *sc = hw->priv;
528f0c6b 1956 struct ath_tx_control txctl;
8feceb67 1957 int hdrlen, padsize;
528f0c6b
S		 1958
1959 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 1960
8feceb67
VT		 1961 /*
1962 * As a temporary workaround, assign seq# here; this will likely need
1963 * to be cleaned up to work better with Beacon transmission and virtual
1964 * BSSes.
1965 */
1966 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1967 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1968 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 1969 sc->tx.seq_no += 0x10;
8feceb67 1970 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 1971 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 1972 }
f078f209 1973
8feceb67
VT		 1974 /* Add the padding after the header if this is not already done */
1975 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1976 if (hdrlen & 3) {
1977 padsize = hdrlen % 4;
1978 if (skb_headroom(skb) < padsize)
1979 return -1;
1980 skb_push(skb, padsize);
1981 memmove(skb->data, skb->data + padsize, hdrlen);
1982 }
1983
528f0c6b
S		 1984 /* Check if a tx queue is available */
1985
1986 txctl.txq = ath_test_get_txq(sc, skb);
1987 if (!txctl.txq)
1988 goto exit;
1989
04bd4638 1990 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1991
528f0c6b 1992 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 1993 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1994 goto exit;
8feceb67
VT		 1995 }
1996
528f0c6b
S		 1997 return 0;
1998exit:
1999 dev_kfree_skb_any(skb);
8feceb67 2000 return 0;
f078f209
LR		 2001}
2002
8feceb67 2003static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR		 2004{
2005 struct ath_softc *sc = hw->priv;
f078f209 2006
9c84b797 2007 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2008 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2009 return;
2010 }
8feceb67 2011
04bd4638 2012 DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
ff37e337
S		 2013
2014 ieee80211_stop_queues(sc->hw);
2015
2016 /* make sure h/w will not generate any interrupt
2017 * before setting the invalid flag. */
2018 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2019
2020 if (!(sc->sc_flags & SC_OP_INVALID)) {
2021 ath_draintxq(sc, false);
2022 ath_stoprecv(sc);
2023 ath9k_hw_phy_disable(sc->sc_ah);
2024 } else
b77f483f 2025 sc->rx.rxlink = NULL;
ff37e337
S		 2026
2027#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2028 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2029 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2030#endif
2031 /* disable HAL and put h/w to sleep */
2032 ath9k_hw_disable(sc->sc_ah);
2033 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2034
2035 sc->sc_flags |= SC_OP_INVALID;
500c064d 2036
04bd4638 2037 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2038}
2039
8feceb67
VT		 2040static int ath9k_add_interface(struct ieee80211_hw *hw,
2041 struct ieee80211_if_init_conf *conf)
f078f209
LR		 2042{
2043 struct ath_softc *sc = hw->priv;
5640b08e 2044 struct ath_vap *avp = (void *)conf->vif->drv_priv;
d97809db 2045 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
f078f209 2046
8feceb67
VT		 2047 /* Support only vap for now */
2048
2049 if (sc->sc_nvaps)
2050 return -ENOBUFS;
2051
2052 switch (conf->type) {
05c914fe 2053 case NL80211_IFTYPE_STATION:
d97809db 2054 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2055 break;
05c914fe 2056 case NL80211_IFTYPE_ADHOC:
d97809db 2057 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2058 break;
05c914fe 2059 case NL80211_IFTYPE_AP:
d97809db 2060 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR		 2061 break;
2062 default:
2063 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2064 "Interface type %d not yet supported\n", conf->type);
8feceb67 2065 return -EOPNOTSUPP;
f078f209
LR		 2066 }
2067
04bd4638 2068 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
8feceb67 2069
5640b08e
S		 2070 /* Set the VAP opmode */
2071 avp->av_opmode = ic_opmode;
2072 avp->av_bslot = -1;
2073
d97809db 2074 if (ic_opmode == NL80211_IFTYPE_AP)
5640b08e
S		 2075 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2076
2077 sc->sc_vaps[0] = conf->vif;
2078 sc->sc_nvaps++;
2079
2080 /* Set the device opmode */
2081 sc->sc_ah->ah_opmode = ic_opmode;
2082
6f255425
LR		 2083 if (conf->type == NL80211_IFTYPE_AP) {
2084 /* TODO: is this a suitable place to start ANI for AP mode? */
2085 /* Start ANI */
2086 mod_timer(&sc->sc_ani.timer,
2087 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2088 }
2089
8feceb67 2090 return 0;
f078f209
LR		 2091}
2092
8feceb67
VT		 2093static void ath9k_remove_interface(struct ieee80211_hw *hw,
2094 struct ieee80211_if_init_conf *conf)
f078f209 2095{
8feceb67 2096 struct ath_softc *sc = hw->priv;
5640b08e 2097 struct ath_vap *avp = (void *)conf->vif->drv_priv;
f078f209 2098
04bd4638 2099 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2100
6f255425
LR		 2101 /* Stop ANI */
2102 del_timer_sync(&sc->sc_ani.timer);
580f0b8a 2103
8feceb67 2104 /* Reclaim beacon resources */
d97809db
CM		 2105 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2106 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2107 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2108 ath_beacon_return(sc, avp);
580f0b8a 2109 }
f078f209 2110
8feceb67 2111 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2112
5640b08e
S		 2113 sc->sc_vaps[0] = NULL;
2114 sc->sc_nvaps--;
f078f209
LR		 2115}
2116
e8975581 2117static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2118{
8feceb67 2119 struct ath_softc *sc = hw->priv;
e8975581 2120 struct ieee80211_conf *conf = &hw->conf;
f078f209 2121
aa33de09 2122 mutex_lock(&sc->mutex);
4797938c 2123 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93
S		 2124 struct ieee80211_channel *curchan = hw->conf.channel;
2125 int pos;
ae5eb026 2126
04bd4638
S		 2127 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2128 curchan->center_freq);
f078f209 2129
99405f93
S		 2130 pos = ath_get_channel(sc, curchan);
2131 if (pos == -1) {
04bd4638
S		 2132 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2133 curchan->center_freq);
aa33de09 2134 mutex_unlock(&sc->mutex);
99405f93
S		 2135 return -EINVAL;
2136 }
f078f209 2137
99405f93 2138 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
8feceb67 2139 sc->sc_ah->ah_channels[pos].chanmode =
99405f93
S		 2140 (curchan->band == IEEE80211_BAND_2GHZ) ?
2141 CHANNEL_G : CHANNEL_A;
2142
ecf70441
LR		 2143 if (conf_is_ht(conf)) {
2144 if (conf_is_ht40(conf))
094d05dc 2145 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
e11602b7
S		 2146
2147 sc->sc_ah->ah_channels[pos].chanmode =
2148 ath_get_extchanmode(sc, curchan,
4797938c 2149 conf->channel_type);
e11602b7
S		 2150 }
2151
ecf70441 2152 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2153
e11602b7 2154 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
04bd4638 2155 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2156 mutex_unlock(&sc->mutex);
e11602b7
S		 2157 return -EINVAL;
2158 }
094d05dc 2159 }
f078f209 2160
5c020dc6
LR		 2161 if (changed & IEEE80211_CONF_CHANGE_POWER)
2162 sc->sc_config.txpowlimit = 2 * conf->power_level;
f078f209 2163
aa33de09 2164 mutex_unlock(&sc->mutex);
f078f209
LR		 2165 return 0;
2166}
2167
8feceb67
VT		 2168static int ath9k_config_interface(struct ieee80211_hw *hw,
2169 struct ieee80211_vif *vif,
2170 struct ieee80211_if_conf *conf)
c83be688 2171{
8feceb67
VT		 2172 struct ath_softc *sc = hw->priv;
2173 struct ath_hal *ah = sc->sc_ah;
5640b08e 2174 struct ath_vap *avp = (void *)vif->drv_priv;
8feceb67
VT		 2175 u32 rfilt = 0;
2176 int error, i;
c83be688 2177
8feceb67
VT		 2178 /* TODO: Need to decide which hw opmode to use for multi-interface
2179 * cases */
05c914fe 2180 if (vif->type == NL80211_IFTYPE_AP &&
d97809db
CM		 2181 ah->ah_opmode != NL80211_IFTYPE_AP) {
2182 ah->ah_opmode = NL80211_IFTYPE_STATION;
8feceb67
VT		 2183 ath9k_hw_setopmode(ah);
2184 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2185 /* Request full reset to get hw opmode changed properly */
2186 sc->sc_flags |= SC_OP_FULL_RESET;
2187 }
c83be688 2188
8feceb67
VT		 2189 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2190 !is_zero_ether_addr(conf->bssid)) {
2191 switch (vif->type) {
05c914fe
JB		 2192 case NL80211_IFTYPE_STATION:
2193 case NL80211_IFTYPE_ADHOC:
8feceb67
VT		 2194 /* Set BSSID */
2195 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2196 sc->sc_curaid = 0;
2197 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2198 sc->sc_curaid);
c83be688 2199
8feceb67
VT		 2200 /* Set aggregation protection mode parameters */
2201 sc->sc_config.ath_aggr_prot = 0;
c83be688 2202
8feceb67 2203 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638
S		 2204 "RX filter 0x%x bssid %pM aid 0x%x\n",
2205 rfilt, sc->sc_curbssid, sc->sc_curaid);
c83be688 2206
8feceb67
VT		 2207 /* need to reconfigure the beacon */
2208 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2209
8feceb67
VT		 2210 break;
2211 default:
2212 break;
2213 }
2214 }
c83be688 2215
8feceb67 2216 if ((conf->changed & IEEE80211_IFCC_BEACON) &&
05c914fe
JB		 2217 ((vif->type == NL80211_IFTYPE_ADHOC) ||
2218 (vif->type == NL80211_IFTYPE_AP))) {
8feceb67
VT		 2219 /*
2220 * Allocate and setup the beacon frame.
2221 *
2222 * Stop any previous beacon DMA. This may be
2223 * necessary, for example, when an ibss merge
2224 * causes reconfiguration; we may be called
2225 * with beacon transmission active.
2226 */
b77f483f 2227 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2228
8feceb67
VT		 2229 error = ath_beacon_alloc(sc, 0);
2230 if (error != 0)
2231 return error;
c83be688 2232
8feceb67
VT		 2233 ath_beacon_sync(sc, 0);
2234 }
c83be688 2235
8feceb67 2236 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2237 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2238 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2239 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2240 ath9k_hw_keysetmac(sc->sc_ah,
2241 (u16)i,
2242 sc->sc_curbssid);
2243 }
c83be688 2244
8feceb67 2245 /* Only legacy IBSS for now */
05c914fe 2246 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2247 ath_update_chainmask(sc, 0);
f078f209 2248
8feceb67
VT		 2249 return 0;
2250}
f078f209 2251
8feceb67
VT		 2252#define SUPPORTED_FILTERS \
2253 (FIF_PROMISC_IN_BSS | \
2254 FIF_ALLMULTI | \
2255 FIF_CONTROL | \
2256 FIF_OTHER_BSS | \
2257 FIF_BCN_PRBRESP_PROMISC | \
2258 FIF_FCSFAIL)
c83be688 2259
8feceb67
VT		 2260/* FIXME: sc->sc_full_reset ? */
2261static void ath9k_configure_filter(struct ieee80211_hw *hw,
2262 unsigned int changed_flags,
2263 unsigned int *total_flags,
2264 int mc_count,
2265 struct dev_mc_list *mclist)
2266{
2267 struct ath_softc *sc = hw->priv;
2268 u32 rfilt;
f078f209 2269
8feceb67
VT		 2270 changed_flags &= SUPPORTED_FILTERS;
2271 *total_flags &= SUPPORTED_FILTERS;
f078f209 2272
b77f483f 2273 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2274 rfilt = ath_calcrxfilter(sc);
2275 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2276
8feceb67
VT		 2277 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2278 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2279 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2280 }
f078f209 2281
b77f483f 2282 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2283}
f078f209 2284
8feceb67
VT		 2285static void ath9k_sta_notify(struct ieee80211_hw *hw,
2286 struct ieee80211_vif *vif,
2287 enum sta_notify_cmd cmd,
17741cdc 2288 struct ieee80211_sta *sta)
8feceb67
VT		 2289{
2290 struct ath_softc *sc = hw->priv;
f078f209 2291
8feceb67
VT		 2292 switch (cmd) {
2293 case STA_NOTIFY_ADD:
5640b08e 2294 ath_node_attach(sc, sta);
8feceb67
VT		 2295 break;
2296 case STA_NOTIFY_REMOVE:
b5aa9bf9 2297 ath_node_detach(sc, sta);
8feceb67
VT		 2298 break;
2299 default:
2300 break;
2301 }
f078f209
LR		 2302}
2303
8feceb67
VT		 2304static int ath9k_conf_tx(struct ieee80211_hw *hw,
2305 u16 queue,
2306 const struct ieee80211_tx_queue_params *params)
f078f209 2307{
8feceb67
VT		 2308 struct ath_softc *sc = hw->priv;
2309 struct ath9k_tx_queue_info qi;
2310 int ret = 0, qnum;
f078f209 2311
8feceb67
VT		 2312 if (queue >= WME_NUM_AC)
2313 return 0;
f078f209 2314
8feceb67
VT		 2315 qi.tqi_aifs = params->aifs;
2316 qi.tqi_cwmin = params->cw_min;
2317 qi.tqi_cwmax = params->cw_max;
2318 qi.tqi_burstTime = params->txop;
2319 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2320
8feceb67 2321 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2322 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2323 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2324 queue, qnum, params->aifs, params->cw_min,
2325 params->cw_max, params->txop);
f078f209 2326
8feceb67
VT		 2327 ret = ath_txq_update(sc, qnum, &qi);
2328 if (ret)
04bd4638 2329 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2330
8feceb67
VT		 2331 return ret;
2332}
f078f209 2333
8feceb67
VT		 2334static int ath9k_set_key(struct ieee80211_hw *hw,
2335 enum set_key_cmd cmd,
dc822b5d
JB		 2336 struct ieee80211_vif *vif,
2337 struct ieee80211_sta *sta,
8feceb67
VT		 2338 struct ieee80211_key_conf *key)
2339{
2340 struct ath_softc *sc = hw->priv;
2341 int ret = 0;
f078f209 2342
04bd4638 2343 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2344
8feceb67
VT		 2345 switch (cmd) {
2346 case SET_KEY:
dc822b5d 2347 ret = ath_key_config(sc, sta, key);
6ace2891
JM		 2348 if (ret >= 0) {
2349 key->hw_key_idx = ret;
8feceb67
VT		 2350 /* push IV and Michael MIC generation to stack */
2351 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2352 if (key->alg == ALG_TKIP)
2353 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2354 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2355 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2356 ret = 0;
8feceb67
VT		 2357 }
2358 break;
2359 case DISABLE_KEY:
2360 ath_key_delete(sc, key);
8feceb67
VT		 2361 break;
2362 default:
2363 ret = -EINVAL;
2364 }
f078f209 2365
8feceb67
VT		 2366 return ret;
2367}
f078f209 2368
8feceb67
VT		 2369static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2370 struct ieee80211_vif *vif,
2371 struct ieee80211_bss_conf *bss_conf,
2372 u32 changed)
2373{
2374 struct ath_softc *sc = hw->priv;
f078f209 2375
8feceb67 2376 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2377 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2378 bss_conf->use_short_preamble);
2379 if (bss_conf->use_short_preamble)
2380 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2381 else
2382 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2383 }
f078f209 2384
8feceb67 2385 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2386 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2387 bss_conf->use_cts_prot);
2388 if (bss_conf->use_cts_prot &&
2389 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2390 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2391 else
2392 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2393 }
f078f209 2394
8feceb67 2395 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2396 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2397 bss_conf->assoc);
5640b08e 2398 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67
VT		 2399 }
2400}
f078f209 2401
8feceb67
VT		 2402static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2403{
2404 u64 tsf;
2405 struct ath_softc *sc = hw->priv;
2406 struct ath_hal *ah = sc->sc_ah;
f078f209 2407
8feceb67 2408 tsf = ath9k_hw_gettsf64(ah);
f078f209 2409
8feceb67
VT		 2410 return tsf;
2411}
f078f209 2412
8feceb67
VT		 2413static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2414{
2415 struct ath_softc *sc = hw->priv;
2416 struct ath_hal *ah = sc->sc_ah;
c83be688 2417
8feceb67
VT		 2418 ath9k_hw_reset_tsf(ah);
2419}
f078f209 2420
8feceb67
VT		 2421static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2422 enum ieee80211_ampdu_mlme_action action,
17741cdc
JB		 2423 struct ieee80211_sta *sta,
2424 u16 tid, u16 *ssn)
8feceb67
VT		 2425{
2426 struct ath_softc *sc = hw->priv;
2427 int ret = 0;
f078f209 2428
8feceb67
VT		 2429 switch (action) {
2430 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2431 if (!(sc->sc_flags & SC_OP_RXAGGR))
2432 ret = -ENOTSUPP;
8feceb67
VT		 2433 break;
2434 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2435 break;
2436 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2437 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2438 if (ret < 0)
2439 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2440 "Unable to start TX aggregation\n");
8feceb67 2441 else
17741cdc 2442 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2443 break;
2444 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2445 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2446 if (ret < 0)
2447 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2448 "Unable to stop TX aggregation\n");
f078f209 2449
17741cdc 2450 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2451 break;
8469cdef
S		 2452 case IEEE80211_AMPDU_TX_RESUME:
2453 ath_tx_aggr_resume(sc, sta, tid);
2454 break;
8feceb67 2455 default:
04bd4638 2456 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2457 }
2458
2459 return ret;
f078f209
LR		 2460}
2461
8feceb67
VT		 2462static struct ieee80211_ops ath9k_ops = {
2463 .tx = ath9k_tx,
2464 .start = ath9k_start,
2465 .stop = ath9k_stop,
2466 .add_interface = ath9k_add_interface,
2467 .remove_interface = ath9k_remove_interface,
2468 .config = ath9k_config,
2469 .config_interface = ath9k_config_interface,
2470 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2471 .sta_notify = ath9k_sta_notify,
2472 .conf_tx = ath9k_conf_tx,
8feceb67 2473 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2474 .set_key = ath9k_set_key,
8feceb67
VT		 2475 .get_tsf = ath9k_get_tsf,
2476 .reset_tsf = ath9k_reset_tsf,
4233df6b 2477 .ampdu_action = ath9k_ampdu_action,
8feceb67
VT		 2478};
2479
392dff83
BP		 2480static struct {
2481 u32 version;
2482 const char * name;
2483} ath_mac_bb_names[] = {
2484 { AR_SREV_VERSION_5416_PCI, "5416" },
2485 { AR_SREV_VERSION_5416_PCIE, "5418" },
2486 { AR_SREV_VERSION_9100, "9100" },
2487 { AR_SREV_VERSION_9160, "9160" },
2488 { AR_SREV_VERSION_9280, "9280" },
2489 { AR_SREV_VERSION_9285, "9285" }
2490};
2491
2492static struct {
2493 u16 version;
2494 const char * name;
2495} ath_rf_names[] = {
2496 { 0, "5133" },
2497 { AR_RAD5133_SREV_MAJOR, "5133" },
2498 { AR_RAD5122_SREV_MAJOR, "5122" },
2499 { AR_RAD2133_SREV_MAJOR, "2133" },
2500 { AR_RAD2122_SREV_MAJOR, "2122" }
2501};
2502
2503/*
2504 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2505 */
392dff83
BP		 2506static const char *
2507ath_mac_bb_name(u32 mac_bb_version)
2508{
2509 int i;
2510
2511 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2512 if (ath_mac_bb_names[i].version == mac_bb_version) {
2513 return ath_mac_bb_names[i].name;
2514 }
2515 }
2516
2517 return "????";
2518}
2519
2520/*
2521 * Return the RF name. "????" is returned if the RF is unknown.
2522 */
392dff83
BP		 2523static const char *
2524ath_rf_name(u16 rf_version)
2525{
2526 int i;
2527
2528 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2529 if (ath_rf_names[i].version == rf_version) {
2530 return ath_rf_names[i].name;
2531 }
2532 }
2533
2534 return "????";
2535}
2536
f078f209
LR		 2537static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2538{
2539 void __iomem *mem;
2540 struct ath_softc *sc;
2541 struct ieee80211_hw *hw;
f078f209
LR		 2542 u8 csz;
2543 u32 val;
2544 int ret = 0;
392dff83 2545 struct ath_hal *ah;
f078f209
LR		 2546
2547 if (pci_enable_device(pdev))
2548 return -EIO;
2549
97b777db
LR		 2550 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2551
2552 if (ret) {
1d450cfc 2553 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
97b777db
LR		 2554 goto bad;
2555 }
2556
2557 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2558
2559 if (ret) {
2560 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
04bd4638 2561 "DMA enable failed\n");
f078f209
LR		 2562 goto bad;
2563 }
2564
2565 /*
2566 * Cache line size is used to size and align various
2567 * structures used to communicate with the hardware.
2568 */
2569 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2570 if (csz == 0) {
2571 /*
2572 * Linux 2.4.18 (at least) writes the cache line size
2573 * register as a 16-bit wide register which is wrong.
2574 * We must have this setup properly for rx buffer
2575 * DMA to work so force a reasonable value here if it
2576 * comes up zero.
2577 */
2578 csz = L1_CACHE_BYTES / sizeof(u32);
2579 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2580 }
2581 /*
2582 * The default setting of latency timer yields poor results,
2583 * set it to the value used by other systems. It may be worth
2584 * tweaking this setting more.
2585 */
2586 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2587
2588 pci_set_master(pdev);
2589
2590 /*
2591 * Disable the RETRY_TIMEOUT register (0x41) to keep
2592 * PCI Tx retries from interfering with C3 CPU state.
2593 */
2594 pci_read_config_dword(pdev, 0x40, &val);
2595 if ((val & 0x0000ff00) != 0)
2596 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2597
2598 ret = pci_request_region(pdev, 0, "ath9k");
2599 if (ret) {
2600 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2601 ret = -ENODEV;
2602 goto bad;
2603 }
2604
2605 mem = pci_iomap(pdev, 0, 0);
2606 if (!mem) {
2607 printk(KERN_ERR "PCI memory map error\n") ;
2608 ret = -EIO;
2609 goto bad1;
2610 }
2611
2612 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2613 if (hw == NULL) {
2614 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2615 goto bad2;
2616 }
2617
f078f209
LR		 2618 SET_IEEE80211_DEV(hw, &pdev->dev);
2619 pci_set_drvdata(pdev, hw);
2620
2621 sc = hw->priv;
2622 sc->hw = hw;
2623 sc->pdev = pdev;
2624 sc->mem = mem;
2625
2626 if (ath_attach(id->device, sc) != 0) {
2627 ret = -ENODEV;
2628 goto bad3;
2629 }
2630
2631 /* setup interrupt service routine */
2632
2633 if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2634 printk(KERN_ERR "%s: request_irq failed\n",
2635 wiphy_name(hw->wiphy));
2636 ret = -EIO;
2637 goto bad4;
2638 }
2639
392dff83
BP		 2640 ah = sc->sc_ah;
2641 printk(KERN_INFO
2642 "%s: Atheros AR%s MAC/BB Rev:%x "
2643 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
f078f209 2644 wiphy_name(hw->wiphy),
392dff83
BP		 2645 ath_mac_bb_name(ah->ah_macVersion),
2646 ah->ah_macRev,
2647 ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2648 ah->ah_phyRev,
f078f209
LR		 2649 (unsigned long)mem, pdev->irq);
2650
2651 return 0;
2652bad4:
2653 ath_detach(sc);
2654bad3:
2655 ieee80211_free_hw(hw);
2656bad2:
2657 pci_iounmap(pdev, mem);
2658bad1:
2659 pci_release_region(pdev, 0);
2660bad:
2661 pci_disable_device(pdev);
2662 return ret;
2663}
2664
2665static void ath_pci_remove(struct pci_dev *pdev)
2666{
2667 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2668 struct ath_softc *sc = hw->priv;
2669
f078f209 2670 ath_detach(sc);
9c84b797
S		 2671 if (pdev->irq)
2672 free_irq(pdev->irq, sc);
f078f209
LR		 2673 pci_iounmap(pdev, sc->mem);
2674 pci_release_region(pdev, 0);
2675 pci_disable_device(pdev);
2676 ieee80211_free_hw(hw);
2677}
2678
2679#ifdef CONFIG_PM
2680
2681static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2682{
c83be688
VT		 2683 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2684 struct ath_softc *sc = hw->priv;
2685
2686 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
500c064d 2687
e97275cb 2688#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 2689 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2690 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2691#endif
2692
f078f209
LR		 2693 pci_save_state(pdev);
2694 pci_disable_device(pdev);
07e74348 2695 pci_set_power_state(pdev, PCI_D3hot);
f078f209
LR		 2696
2697 return 0;
2698}
2699
2700static int ath_pci_resume(struct pci_dev *pdev)
2701{
c83be688
VT		 2702 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2703 struct ath_softc *sc = hw->priv;
f078f209
LR		 2704 u32 val;
2705 int err;
2706
2707 err = pci_enable_device(pdev);
2708 if (err)
2709 return err;
2710 pci_restore_state(pdev);
2711 /*
2712 * Suspend/Resume resets the PCI configuration space, so we have to
2713 * re-disable the RETRY_TIMEOUT register (0x41) to keep
2714 * PCI Tx retries from interfering with C3 CPU state
2715 */
2716 pci_read_config_dword(pdev, 0x40, &val);
2717 if ((val & 0x0000ff00) != 0)
2718 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2719
c83be688
VT		 2720 /* Enable LED */
2721 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2722 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2723 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2724
e97275cb 2725#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 2726 /*
2727 * check the h/w rfkill state on resume
2728 * and start the rfkill poll timer
2729 */
2730 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2731 queue_delayed_work(sc->hw->workqueue,
2732 &sc->rf_kill.rfkill_poll, 0);
2733#endif
2734
f078f209
LR		 2735 return 0;
2736}
2737
2738#endif /* CONFIG_PM */
2739
2740MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2741
2742static struct pci_driver ath_pci_driver = {
2743 .name = "ath9k",
2744 .id_table = ath_pci_id_table,
2745 .probe = ath_pci_probe,
2746 .remove = ath_pci_remove,
2747#ifdef CONFIG_PM
2748 .suspend = ath_pci_suspend,
2749 .resume = ath_pci_resume,
2750#endif /* CONFIG_PM */
2751};
2752
2753static int __init init_ath_pci(void)
2754{
ca8a8560
VT		 2755 int error;
2756
f078f209
LR		 2757 printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2758
ca8a8560
VT		 2759 /* Register rate control algorithm */
2760 error = ath_rate_control_register();
2761 if (error != 0) {
2762 printk(KERN_ERR
2763 "Unable to register rate control algorithm: %d\n",
2764 error);
2765 ath_rate_control_unregister();
2766 return error;
2767 }
2768
f078f209
LR		 2769 if (pci_register_driver(&ath_pci_driver) < 0) {
2770 printk(KERN_ERR
2771 "ath_pci: No devices found, driver not installed.\n");
ca8a8560 2772 ath_rate_control_unregister();
f078f209
LR		 2773 pci_unregister_driver(&ath_pci_driver);
2774 return -ENODEV;
2775 }
2776
2777 return 0;
2778}
2779module_init(init_ath_pci);
2780
2781static void __exit exit_ath_pci(void)
2782{
ca8a8560 2783 ath_rate_control_unregister();
f078f209 2784 pci_unregister_driver(&ath_pci_driver);
04bd4638 2785 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209
LR		 2786}
2787module_exit(exit_ath_pci);
Linux kernel - Deliverables
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