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nl80211: Optional IEs into scan request
[deliverable/linux.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
5f8e077c
LR		 29/* We use the hw_value as an index into our private channel structure */
30
31#define CHAN2G(_freq, _idx) { \
32 .center_freq = (_freq), \
33 .hw_value = (_idx), \
34 .max_power = 30, \
35}
36
37#define CHAN5G(_freq, _idx) { \
38 .band = IEEE80211_BAND_5GHZ, \
39 .center_freq = (_freq), \
40 .hw_value = (_idx), \
41 .max_power = 30, \
42}
43
44/* Some 2 GHz radios are actually tunable on 2312-2732
45 * on 5 MHz steps, we support the channels which we know
46 * we have calibration data for all cards though to make
47 * this static */
48static struct ieee80211_channel ath9k_2ghz_chantable[] = {
49 CHAN2G(2412, 0), /* Channel 1 */
50 CHAN2G(2417, 1), /* Channel 2 */
51 CHAN2G(2422, 2), /* Channel 3 */
52 CHAN2G(2427, 3), /* Channel 4 */
53 CHAN2G(2432, 4), /* Channel 5 */
54 CHAN2G(2437, 5), /* Channel 6 */
55 CHAN2G(2442, 6), /* Channel 7 */
56 CHAN2G(2447, 7), /* Channel 8 */
57 CHAN2G(2452, 8), /* Channel 9 */
58 CHAN2G(2457, 9), /* Channel 10 */
59 CHAN2G(2462, 10), /* Channel 11 */
60 CHAN2G(2467, 11), /* Channel 12 */
61 CHAN2G(2472, 12), /* Channel 13 */
62 CHAN2G(2484, 13), /* Channel 14 */
63};
64
65/* Some 5 GHz radios are actually tunable on XXXX-YYYY
66 * on 5 MHz steps, we support the channels which we know
67 * we have calibration data for all cards though to make
68 * this static */
69static struct ieee80211_channel ath9k_5ghz_chantable[] = {
70 /* _We_ call this UNII 1 */
71 CHAN5G(5180, 14), /* Channel 36 */
72 CHAN5G(5200, 15), /* Channel 40 */
73 CHAN5G(5220, 16), /* Channel 44 */
74 CHAN5G(5240, 17), /* Channel 48 */
75 /* _We_ call this UNII 2 */
76 CHAN5G(5260, 18), /* Channel 52 */
77 CHAN5G(5280, 19), /* Channel 56 */
78 CHAN5G(5300, 20), /* Channel 60 */
79 CHAN5G(5320, 21), /* Channel 64 */
80 /* _We_ call this "Middle band" */
81 CHAN5G(5500, 22), /* Channel 100 */
82 CHAN5G(5520, 23), /* Channel 104 */
83 CHAN5G(5540, 24), /* Channel 108 */
84 CHAN5G(5560, 25), /* Channel 112 */
85 CHAN5G(5580, 26), /* Channel 116 */
86 CHAN5G(5600, 27), /* Channel 120 */
87 CHAN5G(5620, 28), /* Channel 124 */
88 CHAN5G(5640, 29), /* Channel 128 */
89 CHAN5G(5660, 30), /* Channel 132 */
90 CHAN5G(5680, 31), /* Channel 136 */
91 CHAN5G(5700, 32), /* Channel 140 */
92 /* _We_ call this UNII 3 */
93 CHAN5G(5745, 33), /* Channel 149 */
94 CHAN5G(5765, 34), /* Channel 153 */
95 CHAN5G(5785, 35), /* Channel 157 */
96 CHAN5G(5805, 36), /* Channel 161 */
97 CHAN5G(5825, 37), /* Channel 165 */
98};
99
ce111bad
LR		 100static void ath_cache_conf_rate(struct ath_softc *sc,
101 struct ieee80211_conf *conf)
ff37e337 102{
030bb495
LR		 103 switch (conf->channel->band) {
104 case IEEE80211_BAND_2GHZ:
105 if (conf_is_ht20(conf))
106 sc->cur_rate_table =
107 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
108 else if (conf_is_ht40_minus(conf))
109 sc->cur_rate_table =
110 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
111 else if (conf_is_ht40_plus(conf))
112 sc->cur_rate_table =
113 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 114 else
030bb495
LR		 115 sc->cur_rate_table =
116 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 117 break;
118 case IEEE80211_BAND_5GHZ:
119 if (conf_is_ht20(conf))
120 sc->cur_rate_table =
121 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
122 else if (conf_is_ht40_minus(conf))
123 sc->cur_rate_table =
124 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
125 else if (conf_is_ht40_plus(conf))
126 sc->cur_rate_table =
127 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
128 else
96742256
LR		 129 sc->cur_rate_table =
130 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 131 break;
132 default:
ce111bad 133 BUG_ON(1);
030bb495
LR		 134 break;
135 }
ff37e337
S		 136}
137
138static void ath_update_txpow(struct ath_softc *sc)
139{
cbe61d8a 140 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 141 u32 txpow;
142
17d7904d
S		 143 if (sc->curtxpow != sc->config.txpowlimit) {
144 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 145 /* read back in case value is clamped */
146 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 147 sc->curtxpow = txpow;
ff37e337
S		 148 }
149}
150
151static u8 parse_mpdudensity(u8 mpdudensity)
152{
153 /*
154 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
155 * 0 for no restriction
156 * 1 for 1/4 us
157 * 2 for 1/2 us
158 * 3 for 1 us
159 * 4 for 2 us
160 * 5 for 4 us
161 * 6 for 8 us
162 * 7 for 16 us
163 */
164 switch (mpdudensity) {
165 case 0:
166 return 0;
167 case 1:
168 case 2:
169 case 3:
170 /* Our lower layer calculations limit our precision to
171 1 microsecond */
172 return 1;
173 case 4:
174 return 2;
175 case 5:
176 return 4;
177 case 6:
178 return 8;
179 case 7:
180 return 16;
181 default:
182 return 0;
183 }
184}
185
186static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
187{
188 struct ath_rate_table *rate_table = NULL;
189 struct ieee80211_supported_band *sband;
190 struct ieee80211_rate *rate;
191 int i, maxrates;
192
193 switch (band) {
194 case IEEE80211_BAND_2GHZ:
195 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
196 break;
197 case IEEE80211_BAND_5GHZ:
198 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
199 break;
200 default:
201 break;
202 }
203
204 if (rate_table == NULL)
205 return;
206
207 sband = &sc->sbands[band];
208 rate = sc->rates[band];
209
210 if (rate_table->rate_cnt > ATH_RATE_MAX)
211 maxrates = ATH_RATE_MAX;
212 else
213 maxrates = rate_table->rate_cnt;
214
215 for (i = 0; i < maxrates; i++) {
216 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
217 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 218 if (rate_table->info[i].short_preamble) {
219 rate[i].hw_value_short = rate_table->info[i].ratecode |
220 rate_table->info[i].short_preamble;
221 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
222 }
ff37e337 223 sband->n_bitrates++;
f46730d1 224
04bd4638
S		 225 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
226 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 227 }
228}
229
ff37e337
S		 230/*
231 * Set/change channels. If the channel is really being changed, it's done
232 * by reseting the chip. To accomplish this we must first cleanup any pending
233 * DMA, then restart stuff.
234*/
235static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
236{
cbe61d8a 237 struct ath_hw *ah = sc->sc_ah;
ff37e337 238 bool fastcc = true, stopped;
030bb495 239 struct ieee80211_hw *hw = sc->hw;
ae8d2858
LR		 240 struct ieee80211_channel *channel = hw->conf.channel;
241 int r;
ff37e337
S		 242
243 if (sc->sc_flags & SC_OP_INVALID)
244 return -EIO;
245
3cbb5dd7
VN		 246 ath9k_ps_wakeup(sc);
247
c0d7c7af
LR		 248 /*
249 * This is only performed if the channel settings have
250 * actually changed.
251 *
252 * To switch channels clear any pending DMA operations;
253 * wait long enough for the RX fifo to drain, reset the
254 * hardware at the new frequency, and then re-enable
255 * the relevant bits of the h/w.
256 */
257 ath9k_hw_set_interrupts(ah, 0);
043a0405 258 ath_drain_all_txq(sc, false);
c0d7c7af 259 stopped = ath_stoprecv(sc);
ff37e337 260
c0d7c7af
LR		 261 /* XXX: do not flush receive queue here. We don't want
262 * to flush data frames already in queue because of
263 * changing channel. */
ff37e337 264
c0d7c7af
LR		 265 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
266 fastcc = false;
267
268 DPRINTF(sc, ATH_DBG_CONFIG,
269 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 270 sc->sc_ah->curchan->channel,
c0d7c7af 271 channel->center_freq, sc->tx_chan_width);
ff37e337 272
c0d7c7af
LR		 273 spin_lock_bh(&sc->sc_resetlock);
274
275 r = ath9k_hw_reset(ah, hchan, fastcc);
276 if (r) {
277 DPRINTF(sc, ATH_DBG_FATAL,
278 "Unable to reset channel (%u Mhz) "
279 "reset status %u\n",
280 channel->center_freq, r);
281 spin_unlock_bh(&sc->sc_resetlock);
282 return r;
ff37e337 283 }
c0d7c7af
LR		 284 spin_unlock_bh(&sc->sc_resetlock);
285
286 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
287 sc->sc_flags &= ~SC_OP_FULL_RESET;
288
289 if (ath_startrecv(sc) != 0) {
290 DPRINTF(sc, ATH_DBG_FATAL,
291 "Unable to restart recv logic\n");
292 return -EIO;
293 }
294
295 ath_cache_conf_rate(sc, &hw->conf);
296 ath_update_txpow(sc);
17d7904d 297 ath9k_hw_set_interrupts(ah, sc->imask);
3cbb5dd7 298 ath9k_ps_restore(sc);
ff37e337
S		 299 return 0;
300}
301
302/*
303 * This routine performs the periodic noise floor calibration function
304 * that is used to adjust and optimize the chip performance. This
305 * takes environmental changes (location, temperature) into account.
306 * When the task is complete, it reschedules itself depending on the
307 * appropriate interval that was calculated.
308 */
309static void ath_ani_calibrate(unsigned long data)
310{
311 struct ath_softc *sc;
cbe61d8a 312 struct ath_hw *ah;
ff37e337
S		 313 bool longcal = false;
314 bool shortcal = false;
315 bool aniflag = false;
316 unsigned int timestamp = jiffies_to_msecs(jiffies);
317 u32 cal_interval;
318
319 sc = (struct ath_softc *)data;
320 ah = sc->sc_ah;
321
322 /*
323 * don't calibrate when we're scanning.
324 * we are most likely not on our home channel.
325 */
b77f483f 326 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
ff37e337
S		 327 return;
328
329 /* Long calibration runs independently of short calibration. */
17d7904d 330 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 331 longcal = true;
04bd4638 332 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 333 sc->ani.longcal_timer = timestamp;
ff37e337
S		 334 }
335
17d7904d
S		 336 /* Short calibration applies only while caldone is false */
337 if (!sc->ani.caldone) {
338 if ((timestamp - sc->ani.shortcal_timer) >=
ff37e337
S		 339 ATH_SHORT_CALINTERVAL) {
340 shortcal = true;
04bd4638 341 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 342 sc->ani.shortcal_timer = timestamp;
343 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 344 }
345 } else {
17d7904d 346 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 347 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 348 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
349 if (sc->ani.caldone)
350 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 351 }
352 }
353
354 /* Verify whether we must check ANI */
17d7904d 355 if ((timestamp - sc->ani.checkani_timer) >=
ff37e337
S		 356 ATH_ANI_POLLINTERVAL) {
357 aniflag = true;
17d7904d 358 sc->ani.checkani_timer = timestamp;
ff37e337
S		 359 }
360
361 /* Skip all processing if there's nothing to do. */
362 if (longcal || shortcal || aniflag) {
363 /* Call ANI routine if necessary */
364 if (aniflag)
17d7904d 365 ath9k_hw_ani_monitor(ah, &sc->nodestats,
2660b81a 366 ah->curchan);
ff37e337
S		 367
368 /* Perform calibration if necessary */
369 if (longcal || shortcal) {
370 bool iscaldone = false;
371
2660b81a 372 if (ath9k_hw_calibrate(ah, ah->curchan,
17d7904d 373 sc->rx_chainmask, longcal,
ff37e337
S		 374 &iscaldone)) {
375 if (longcal)
17d7904d 376 sc->ani.noise_floor =
ff37e337 377 ath9k_hw_getchan_noise(ah,
2660b81a 378 ah->curchan);
ff37e337
S		 379
380 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 381 "calibrate chan %u/%x nf: %d\n",
2660b81a
S		 382 ah->curchan->channel,
383 ah->curchan->channelFlags,
17d7904d 384 sc->ani.noise_floor);
ff37e337
S		 385 } else {
386 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 387 "calibrate chan %u/%x failed\n",
2660b81a
S		 388 ah->curchan->channel,
389 ah->curchan->channelFlags);
ff37e337 390 }
17d7904d 391 sc->ani.caldone = iscaldone;
ff37e337
S		 392 }
393 }
394
395 /*
396 * Set timer interval based on previous results.
397 * The interval must be the shortest necessary to satisfy ANI,
398 * short calibration and long calibration.
399 */
aac9207e 400 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 401 if (sc->sc_ah->config.enable_ani)
aac9207e 402 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 403 if (!sc->ani.caldone)
ff37e337
S		 404 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
405
17d7904d 406 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 407}
408
409/*
410 * Update tx/rx chainmask. For legacy association,
411 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 412 * the chainmask configuration, for bt coexistence, use
413 * the chainmask configuration even in legacy mode.
ff37e337
S		 414 */
415static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
416{
417 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
c97c92d9 418 if (is_ht ||
2660b81a
S		 419 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
420 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
421 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 422 } else {
17d7904d
S		 423 sc->tx_chainmask = 1;
424 sc->rx_chainmask = 1;
ff37e337
S		 425 }
426
04bd4638 427 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 428 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 429}
430
431static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
432{
433 struct ath_node *an;
434
435 an = (struct ath_node *)sta->drv_priv;
436
437 if (sc->sc_flags & SC_OP_TXAGGR)
438 ath_tx_node_init(sc, an);
439
440 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
441 sta->ht_cap.ampdu_factor);
442 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
443}
444
445static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
446{
447 struct ath_node *an = (struct ath_node *)sta->drv_priv;
448
449 if (sc->sc_flags & SC_OP_TXAGGR)
450 ath_tx_node_cleanup(sc, an);
451}
452
453static void ath9k_tasklet(unsigned long data)
454{
455 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 456 u32 status = sc->intrstatus;
ff37e337
S		 457
458 if (status & ATH9K_INT_FATAL) {
459 /* need a chip reset */
460 ath_reset(sc, false);
461 return;
462 } else {
463
464 if (status &
465 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 466 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 467 ath_rx_tasklet(sc, 0);
b77f483f 468 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 469 }
470 /* XXX: optimize this */
471 if (status & ATH9K_INT_TX)
472 ath_tx_tasklet(sc);
473 }
474
475 /* re-enable hardware interrupt */
17d7904d 476 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337
S		 477}
478
6baff7f9 479irqreturn_t ath_isr(int irq, void *dev)
ff37e337
S		 480{
481 struct ath_softc *sc = dev;
cbe61d8a 482 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 483 enum ath9k_int status;
484 bool sched = false;
485
486 do {
487 if (sc->sc_flags & SC_OP_INVALID) {
488 /*
489 * The hardware is not ready/present, don't
490 * touch anything. Note this can happen early
491 * on if the IRQ is shared.
492 */
493 return IRQ_NONE;
494 }
495 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
496 return IRQ_NONE;
497 }
498
499 /*
500 * Figure out the reason(s) for the interrupt. Note
501 * that the hal returns a pseudo-ISR that may include
502 * bits we haven't explicitly enabled so we mask the
503 * value to insure we only process bits we requested.
504 */
505 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
506
17d7904d 507 status &= sc->imask; /* discard unasked-for bits */
ff37e337
S		 508
509 /*
510 * If there are no status bits set, then this interrupt was not
511 * for me (should have been caught above).
512 */
513 if (!status)
514 return IRQ_NONE;
515
17d7904d 516 sc->intrstatus = status;
ff37e337
S		 517
518 if (status & ATH9K_INT_FATAL) {
519 /* need a chip reset */
520 sched = true;
521 } else if (status & ATH9K_INT_RXORN) {
522 /* need a chip reset */
523 sched = true;
524 } else {
525 if (status & ATH9K_INT_SWBA) {
526 /* schedule a tasklet for beacon handling */
527 tasklet_schedule(&sc->bcon_tasklet);
528 }
529 if (status & ATH9K_INT_RXEOL) {
530 /*
531 * NB: the hardware should re-read the link when
532 * RXE bit is written, but it doesn't work
533 * at least on older hardware revs.
534 */
535 sched = true;
536 }
537
538 if (status & ATH9K_INT_TXURN)
539 /* bump tx trigger level */
540 ath9k_hw_updatetxtriglevel(ah, true);
541 /* XXX: optimize this */
542 if (status & ATH9K_INT_RX)
543 sched = true;
544 if (status & ATH9K_INT_TX)
545 sched = true;
546 if (status & ATH9K_INT_BMISS)
547 sched = true;
548 /* carrier sense timeout */
549 if (status & ATH9K_INT_CST)
550 sched = true;
551 if (status & ATH9K_INT_MIB) {
552 /*
553 * Disable interrupts until we service the MIB
554 * interrupt; otherwise it will continue to
555 * fire.
556 */
557 ath9k_hw_set_interrupts(ah, 0);
558 /*
559 * Let the hal handle the event. We assume
560 * it will clear whatever condition caused
561 * the interrupt.
562 */
17d7904d
S		 563 ath9k_hw_procmibevent(ah, &sc->nodestats);
564 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 565 }
566 if (status & ATH9K_INT_TIM_TIMER) {
2660b81a 567 if (!(ah->caps.hw_caps &
ff37e337
S		 568 ATH9K_HW_CAP_AUTOSLEEP)) {
569 /* Clear RxAbort bit so that we can
570 * receive frames */
3cbb5dd7 571 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
ff37e337
S		 572 ath9k_hw_setrxabort(ah, 0);
573 sched = true;
3cbb5dd7 574 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337
S		 575 }
576 }
4af9cf4f
S		 577 if (status & ATH9K_INT_TSFOOR) {
578 /* FIXME: Handle this interrupt for power save */
579 sched = true;
580 }
ff37e337
S		 581 }
582 } while (0);
583
817e11de
S		 584 ath_debug_stat_interrupt(sc, status);
585
ff37e337
S		 586 if (sched) {
587 /* turn off every interrupt except SWBA */
17d7904d 588 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 589 tasklet_schedule(&sc->intr_tq);
590 }
591
592 return IRQ_HANDLED;
593}
594
f078f209 595static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 596 struct ieee80211_channel *chan,
094d05dc 597 enum nl80211_channel_type channel_type)
f078f209
LR		 598{
599 u32 chanmode = 0;
f078f209
LR		 600
601 switch (chan->band) {
602 case IEEE80211_BAND_2GHZ:
094d05dc
S		 603 switch(channel_type) {
604 case NL80211_CHAN_NO_HT:
605 case NL80211_CHAN_HT20:
f078f209 606 chanmode = CHANNEL_G_HT20;
094d05dc
S		 607 break;
608 case NL80211_CHAN_HT40PLUS:
f078f209 609 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 610 break;
611 case NL80211_CHAN_HT40MINUS:
f078f209 612 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 613 break;
614 }
f078f209
LR		 615 break;
616 case IEEE80211_BAND_5GHZ:
094d05dc
S		 617 switch(channel_type) {
618 case NL80211_CHAN_NO_HT:
619 case NL80211_CHAN_HT20:
f078f209 620 chanmode = CHANNEL_A_HT20;
094d05dc
S		 621 break;
622 case NL80211_CHAN_HT40PLUS:
f078f209 623 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 624 break;
625 case NL80211_CHAN_HT40MINUS:
f078f209 626 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 627 break;
628 }
f078f209
LR		 629 break;
630 default:
631 break;
632 }
633
634 return chanmode;
635}
636
ff37e337
S		 637static int ath_keyset(struct ath_softc *sc, u16 keyix,
638 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
639{
640 bool status;
641
642 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
643 keyix, hk, mac, false);
644
645 return status != false;
646}
f078f209 647
6ace2891 648static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
f078f209
LR		 649 struct ath9k_keyval *hk,
650 const u8 *addr)
651{
6ace2891
JM		 652 const u8 *key_rxmic;
653 const u8 *key_txmic;
f078f209 654
6ace2891
JM		 655 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
656 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 657
658 if (addr == NULL) {
659 /* Group key installation */
6ace2891
JM		 660 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
661 return ath_keyset(sc, keyix, hk, addr);
f078f209 662 }
17d7904d 663 if (!sc->splitmic) {
f078f209
LR		 664 /*
665 * data key goes at first index,
666 * the hal handles the MIC keys at index+64.
667 */
668 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
669 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
6ace2891 670 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 671 }
672 /*
673 * TX key goes at first index, RX key at +32.
674 * The hal handles the MIC keys at index+64.
675 */
676 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
6ace2891 677 if (!ath_keyset(sc, keyix, hk, NULL)) {
f078f209
LR		 678 /* Txmic entry failed. No need to proceed further */
679 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 680 "Setting TX MIC Key Failed\n");
f078f209
LR		 681 return 0;
682 }
683
684 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
685 /* XXX delete tx key on failure? */
6ace2891
JM		 686 return ath_keyset(sc, keyix + 32, hk, addr);
687}
688
689static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
690{
691 int i;
692
17d7904d
S		 693 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
694 if (test_bit(i, sc->keymap) ||
695 test_bit(i + 64, sc->keymap))
6ace2891 696 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 697 if (sc->splitmic &&
698 (test_bit(i + 32, sc->keymap) ||
699 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 700 continue; /* At least one part of TKIP key allocated */
701
702 /* Found a free slot for a TKIP key */
703 return i;
704 }
705 return -1;
706}
707
708static int ath_reserve_key_cache_slot(struct ath_softc *sc)
709{
710 int i;
711
712 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 713 if (sc->splitmic) {
714 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
715 if (!test_bit(i, sc->keymap) &&
716 (test_bit(i + 32, sc->keymap) ||
717 test_bit(i + 64, sc->keymap) ||
718 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 719 return i;
17d7904d
S		 720 if (!test_bit(i + 32, sc->keymap) &&
721 (test_bit(i, sc->keymap) ||
722 test_bit(i + 64, sc->keymap) ||
723 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 724 return i + 32;
17d7904d
S		 725 if (!test_bit(i + 64, sc->keymap) &&
726 (test_bit(i , sc->keymap) ||
727 test_bit(i + 32, sc->keymap) ||
728 test_bit(i + 64 + 32, sc->keymap)))
ea612132 729 return i + 64;
17d7904d
S		 730 if (!test_bit(i + 64 + 32, sc->keymap) &&
731 (test_bit(i, sc->keymap) ||
732 test_bit(i + 32, sc->keymap) ||
733 test_bit(i + 64, sc->keymap)))
ea612132 734 return i + 64 + 32;
6ace2891
JM		 735 }
736 } else {
17d7904d
S		 737 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
738 if (!test_bit(i, sc->keymap) &&
739 test_bit(i + 64, sc->keymap))
6ace2891 740 return i;
17d7904d
S		 741 if (test_bit(i, sc->keymap) &&
742 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 743 return i + 64;
744 }
745 }
746
747 /* No partially used TKIP slots, pick any available slot */
17d7904d 748 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 749 /* Do not allow slots that could be needed for TKIP group keys
750 * to be used. This limitation could be removed if we know that
751 * TKIP will not be used. */
752 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
753 continue;
17d7904d 754 if (sc->splitmic) {
be2864cf
JM		 755 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
756 continue;
757 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
758 continue;
759 }
760
17d7904d 761 if (!test_bit(i, sc->keymap))
6ace2891
JM		 762 return i; /* Found a free slot for a key */
763 }
764
765 /* No free slot found */
766 return -1;
f078f209
LR		 767}
768
769static int ath_key_config(struct ath_softc *sc,
dc822b5d 770 struct ieee80211_sta *sta,
f078f209
LR		 771 struct ieee80211_key_conf *key)
772{
f078f209
LR		 773 struct ath9k_keyval hk;
774 const u8 *mac = NULL;
775 int ret = 0;
6ace2891 776 int idx;
f078f209
LR		 777
778 memset(&hk, 0, sizeof(hk));
779
780 switch (key->alg) {
781 case ALG_WEP:
782 hk.kv_type = ATH9K_CIPHER_WEP;
783 break;
784 case ALG_TKIP:
785 hk.kv_type = ATH9K_CIPHER_TKIP;
786 break;
787 case ALG_CCMP:
788 hk.kv_type = ATH9K_CIPHER_AES_CCM;
789 break;
790 default:
ca470b29 791 return -EOPNOTSUPP;
f078f209
LR		 792 }
793
6ace2891 794 hk.kv_len = key->keylen;
f078f209
LR		 795 memcpy(hk.kv_val, key->key, key->keylen);
796
6ace2891
JM		 797 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
798 /* For now, use the default keys for broadcast keys. This may
799 * need to change with virtual interfaces. */
800 idx = key->keyidx;
801 } else if (key->keyidx) {
802 struct ieee80211_vif *vif;
f078f209 803
dc822b5d
JB		 804 if (WARN_ON(!sta))
805 return -EOPNOTSUPP;
806 mac = sta->addr;
807
17d7904d 808 vif = sc->vifs[0];
6ace2891
JM		 809 if (vif->type != NL80211_IFTYPE_AP) {
810 /* Only keyidx 0 should be used with unicast key, but
811 * allow this for client mode for now. */
812 idx = key->keyidx;
813 } else
814 return -EIO;
f078f209 815 } else {
dc822b5d
JB		 816 if (WARN_ON(!sta))
817 return -EOPNOTSUPP;
818 mac = sta->addr;
819
6ace2891
JM		 820 if (key->alg == ALG_TKIP)
821 idx = ath_reserve_key_cache_slot_tkip(sc);
822 else
823 idx = ath_reserve_key_cache_slot(sc);
824 if (idx < 0)
ca470b29 825 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 826 }
827
828 if (key->alg == ALG_TKIP)
6ace2891 829 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
f078f209 830 else
6ace2891 831 ret = ath_keyset(sc, idx, &hk, mac);
f078f209
LR		 832
833 if (!ret)
834 return -EIO;
835
17d7904d 836 set_bit(idx, sc->keymap);
6ace2891 837 if (key->alg == ALG_TKIP) {
17d7904d
S		 838 set_bit(idx + 64, sc->keymap);
839 if (sc->splitmic) {
840 set_bit(idx + 32, sc->keymap);
841 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 842 }
843 }
844
845 return idx;
f078f209
LR		 846}
847
848static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
849{
6ace2891
JM		 850 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
851 if (key->hw_key_idx < IEEE80211_WEP_NKID)
852 return;
853
17d7904d 854 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 855 if (key->alg != ALG_TKIP)
856 return;
f078f209 857
17d7904d
S		 858 clear_bit(key->hw_key_idx + 64, sc->keymap);
859 if (sc->splitmic) {
860 clear_bit(key->hw_key_idx + 32, sc->keymap);
861 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 862 }
f078f209
LR		 863}
864
eb2599ca
S		 865static void setup_ht_cap(struct ath_softc *sc,
866 struct ieee80211_sta_ht_cap *ht_info)
f078f209 867{
60653678
S		 868#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
869#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 870
d9fe60de
JB		 871 ht_info->ht_supported = true;
872 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
873 IEEE80211_HT_CAP_SM_PS |
874 IEEE80211_HT_CAP_SGI_40 |
875 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 876
60653678
S		 877 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
878 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 879
d9fe60de
JB		 880 /* set up supported mcs set */
881 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca 882
17d7904d 883 switch(sc->rx_chainmask) {
eb2599ca
S		 884 case 1:
885 ht_info->mcs.rx_mask[0] = 0xff;
886 break;
3c457265 887 case 3:
eb2599ca
S		 888 case 5:
889 case 7:
890 default:
891 ht_info->mcs.rx_mask[0] = 0xff;
892 ht_info->mcs.rx_mask[1] = 0xff;
893 break;
894 }
895
d9fe60de 896 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 897}
898
8feceb67 899static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 900 struct ieee80211_vif *vif,
8feceb67 901 struct ieee80211_bss_conf *bss_conf)
f078f209 902{
17d7904d 903 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 904
8feceb67 905 if (bss_conf->assoc) {
094d05dc 906 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 907 bss_conf->aid, sc->curbssid);
f078f209 908
8feceb67 909 /* New association, store aid */
d97809db 910 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
17d7904d 911 sc->curaid = bss_conf->aid;
ba52da58 912 ath9k_hw_write_associd(sc);
8feceb67 913 }
f078f209 914
8feceb67
VT		 915 /* Configure the beacon */
916 ath_beacon_config(sc, 0);
917 sc->sc_flags |= SC_OP_BEACONS;
f078f209 918
8feceb67 919 /* Reset rssi stats */
17d7904d
S		 920 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
921 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
922 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
923 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 924
6f255425 925 /* Start ANI */
17d7904d 926 mod_timer(&sc->ani.timer,
6f255425
LR		 927 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
928
8feceb67 929 } else {
04bd4638 930 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
17d7904d 931 sc->curaid = 0;
f078f209 932 }
8feceb67 933}
f078f209 934
8feceb67
VT		 935/********************************/
936/* LED functions */
937/********************************/
f078f209 938
f2bffa7e
VT		 939static void ath_led_blink_work(struct work_struct *work)
940{
941 struct ath_softc *sc = container_of(work, struct ath_softc,
942 ath_led_blink_work.work);
943
944 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
945 return;
946 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
947 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
948
949 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
950 (sc->sc_flags & SC_OP_LED_ON) ?
951 msecs_to_jiffies(sc->led_off_duration) :
952 msecs_to_jiffies(sc->led_on_duration));
953
954 sc->led_on_duration =
955 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
956 sc->led_off_duration =
957 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
958 sc->led_on_cnt = sc->led_off_cnt = 0;
959 if (sc->sc_flags & SC_OP_LED_ON)
960 sc->sc_flags &= ~SC_OP_LED_ON;
961 else
962 sc->sc_flags |= SC_OP_LED_ON;
963}
964
8feceb67
VT		 965static void ath_led_brightness(struct led_classdev *led_cdev,
966 enum led_brightness brightness)
967{
968 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
969 struct ath_softc *sc = led->sc;
f078f209 970
8feceb67
VT		 971 switch (brightness) {
972 case LED_OFF:
973 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 974 led->led_type == ATH_LED_RADIO) {
975 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
976 (led->led_type == ATH_LED_RADIO));
8feceb67 977 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 978 if (led->led_type == ATH_LED_RADIO)
979 sc->sc_flags &= ~SC_OP_LED_ON;
980 } else {
981 sc->led_off_cnt++;
982 }
8feceb67
VT		 983 break;
984 case LED_FULL:
f2bffa7e 985 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 986 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 987 queue_delayed_work(sc->hw->workqueue,
988 &sc->ath_led_blink_work, 0);
989 } else if (led->led_type == ATH_LED_RADIO) {
990 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
991 sc->sc_flags |= SC_OP_LED_ON;
992 } else {
993 sc->led_on_cnt++;
994 }
8feceb67
VT		 995 break;
996 default:
997 break;
f078f209 998 }
8feceb67 999}
f078f209 1000
8feceb67
VT		 1001static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1002 char *trigger)
1003{
1004 int ret;
f078f209 1005
8feceb67
VT		 1006 led->sc = sc;
1007 led->led_cdev.name = led->name;
1008 led->led_cdev.default_trigger = trigger;
1009 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1010
8feceb67
VT		 1011 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1012 if (ret)
1013 DPRINTF(sc, ATH_DBG_FATAL,
1014 "Failed to register led:%s", led->name);
1015 else
1016 led->registered = 1;
1017 return ret;
1018}
f078f209 1019
8feceb67
VT		 1020static void ath_unregister_led(struct ath_led *led)
1021{
1022 if (led->registered) {
1023 led_classdev_unregister(&led->led_cdev);
1024 led->registered = 0;
f078f209 1025 }
f078f209
LR		 1026}
1027
8feceb67 1028static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1029{
f2bffa7e 1030 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1031 ath_unregister_led(&sc->assoc_led);
1032 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1033 ath_unregister_led(&sc->tx_led);
1034 ath_unregister_led(&sc->rx_led);
1035 ath_unregister_led(&sc->radio_led);
1036 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1037}
f078f209 1038
8feceb67
VT		 1039static void ath_init_leds(struct ath_softc *sc)
1040{
1041 char *trigger;
1042 int ret;
f078f209 1043
8feceb67
VT		 1044 /* Configure gpio 1 for output */
1045 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1046 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1047 /* LED off, active low */
1048 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1049
f2bffa7e
VT		 1050 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1051
8feceb67
VT		 1052 trigger = ieee80211_get_radio_led_name(sc->hw);
1053 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1054 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1055 ret = ath_register_led(sc, &sc->radio_led, trigger);
1056 sc->radio_led.led_type = ATH_LED_RADIO;
1057 if (ret)
1058 goto fail;
7dcfdcd9 1059
8feceb67
VT		 1060 trigger = ieee80211_get_assoc_led_name(sc->hw);
1061 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1062 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1063 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1064 sc->assoc_led.led_type = ATH_LED_ASSOC;
1065 if (ret)
1066 goto fail;
f078f209 1067
8feceb67
VT		 1068 trigger = ieee80211_get_tx_led_name(sc->hw);
1069 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1070 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1071 ret = ath_register_led(sc, &sc->tx_led, trigger);
1072 sc->tx_led.led_type = ATH_LED_TX;
1073 if (ret)
1074 goto fail;
f078f209 1075
8feceb67
VT		 1076 trigger = ieee80211_get_rx_led_name(sc->hw);
1077 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1078 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1079 ret = ath_register_led(sc, &sc->rx_led, trigger);
1080 sc->rx_led.led_type = ATH_LED_RX;
1081 if (ret)
1082 goto fail;
f078f209 1083
8feceb67
VT		 1084 return;
1085
1086fail:
1087 ath_deinit_leds(sc);
f078f209
LR		 1088}
1089
e97275cb 1090#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1091
500c064d
VT		 1092/*******************/
1093/* Rfkill */
1094/*******************/
1095
1096static void ath_radio_enable(struct ath_softc *sc)
1097{
cbe61d8a 1098 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1099 struct ieee80211_channel *channel = sc->hw->conf.channel;
1100 int r;
500c064d 1101
3cbb5dd7 1102 ath9k_ps_wakeup(sc);
500c064d 1103 spin_lock_bh(&sc->sc_resetlock);
ae8d2858 1104
2660b81a 1105 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858
LR		 1106
1107 if (r) {
500c064d 1108 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1109 "Unable to reset channel %u (%uMhz) ",
1110 "reset status %u\n",
1111 channel->center_freq, r);
500c064d
VT		 1112 }
1113 spin_unlock_bh(&sc->sc_resetlock);
1114
1115 ath_update_txpow(sc);
1116 if (ath_startrecv(sc) != 0) {
1117 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1118 "Unable to restart recv logic\n");
500c064d
VT		 1119 return;
1120 }
1121
1122 if (sc->sc_flags & SC_OP_BEACONS)
1123 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1124
1125 /* Re-Enable interrupts */
17d7904d 1126 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1127
1128 /* Enable LED */
1129 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1130 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1131 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1132
1133 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1134 ath9k_ps_restore(sc);
500c064d
VT		 1135}
1136
1137static void ath_radio_disable(struct ath_softc *sc)
1138{
cbe61d8a 1139 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1140 struct ieee80211_channel *channel = sc->hw->conf.channel;
1141 int r;
500c064d 1142
3cbb5dd7 1143 ath9k_ps_wakeup(sc);
500c064d
VT		 1144 ieee80211_stop_queues(sc->hw);
1145
1146 /* Disable LED */
1147 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1148 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1149
1150 /* Disable interrupts */
1151 ath9k_hw_set_interrupts(ah, 0);
1152
043a0405 1153 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1154 ath_stoprecv(sc); /* turn off frame recv */
1155 ath_flushrecv(sc); /* flush recv queue */
1156
1157 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1158 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1159 if (r) {
500c064d 1160 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1161 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1162 "reset status %u\n",
1163 channel->center_freq, r);
500c064d
VT		 1164 }
1165 spin_unlock_bh(&sc->sc_resetlock);
1166
1167 ath9k_hw_phy_disable(ah);
1168 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1169 ath9k_ps_restore(sc);
500c064d
VT		 1170}
1171
1172static bool ath_is_rfkill_set(struct ath_softc *sc)
1173{
cbe61d8a 1174 struct ath_hw *ah = sc->sc_ah;
500c064d 1175
2660b81a
S		 1176 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1177 ah->rfkill_polarity;
500c064d
VT		 1178}
1179
1180/* h/w rfkill poll function */
1181static void ath_rfkill_poll(struct work_struct *work)
1182{
1183 struct ath_softc *sc = container_of(work, struct ath_softc,
1184 rf_kill.rfkill_poll.work);
1185 bool radio_on;
1186
1187 if (sc->sc_flags & SC_OP_INVALID)
1188 return;
1189
1190 radio_on = !ath_is_rfkill_set(sc);
1191
1192 /*
1193 * enable/disable radio only when there is a
1194 * state change in RF switch
1195 */
1196 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1197 enum rfkill_state state;
1198
1199 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1200 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1201 : RFKILL_STATE_HARD_BLOCKED;
1202 } else if (radio_on) {
1203 ath_radio_enable(sc);
1204 state = RFKILL_STATE_UNBLOCKED;
1205 } else {
1206 ath_radio_disable(sc);
1207 state = RFKILL_STATE_HARD_BLOCKED;
1208 }
1209
1210 if (state == RFKILL_STATE_HARD_BLOCKED)
1211 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1212 else
1213 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1214
1215 rfkill_force_state(sc->rf_kill.rfkill, state);
1216 }
1217
1218 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1219 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1220}
1221
1222/* s/w rfkill handler */
1223static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1224{
1225 struct ath_softc *sc = data;
1226
1227 switch (state) {
1228 case RFKILL_STATE_SOFT_BLOCKED:
1229 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1230 SC_OP_RFKILL_SW_BLOCKED)))
1231 ath_radio_disable(sc);
1232 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1233 return 0;
1234 case RFKILL_STATE_UNBLOCKED:
1235 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1236 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1237 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1238 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1239 "radio as it is disabled by h/w\n");
500c064d
VT		 1240 return -EPERM;
1241 }
1242 ath_radio_enable(sc);
1243 }
1244 return 0;
1245 default:
1246 return -EINVAL;
1247 }
1248}
1249
1250/* Init s/w rfkill */
1251static int ath_init_sw_rfkill(struct ath_softc *sc)
1252{
1253 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1254 RFKILL_TYPE_WLAN);
1255 if (!sc->rf_kill.rfkill) {
1256 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1257 return -ENOMEM;
1258 }
1259
1260 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
0818cb8a 1261 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
500c064d
VT		 1262 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1263 sc->rf_kill.rfkill->data = sc;
1264 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1265 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1266 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1267
1268 return 0;
1269}
1270
1271/* Deinitialize rfkill */
1272static void ath_deinit_rfkill(struct ath_softc *sc)
1273{
2660b81a 1274 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1275 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1276
1277 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1278 rfkill_unregister(sc->rf_kill.rfkill);
1279 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1280 sc->rf_kill.rfkill = NULL;
1281 }
1282}
9c84b797
S		 1283
1284static int ath_start_rfkill_poll(struct ath_softc *sc)
1285{
2660b81a 1286 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
9c84b797
S		 1287 queue_delayed_work(sc->hw->workqueue,
1288 &sc->rf_kill.rfkill_poll, 0);
1289
1290 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1291 if (rfkill_register(sc->rf_kill.rfkill)) {
1292 DPRINTF(sc, ATH_DBG_FATAL,
1293 "Unable to register rfkill\n");
1294 rfkill_free(sc->rf_kill.rfkill);
1295
1296 /* Deinitialize the device */
39c3c2f2 1297 ath_cleanup(sc);
9c84b797
S		 1298 return -EIO;
1299 } else {
1300 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1301 }
1302 }
1303
1304 return 0;
1305}
500c064d
VT		 1306#endif /* CONFIG_RFKILL */
1307
6baff7f9 1308void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1309{
1310 ath_detach(sc);
1311 free_irq(sc->irq, sc);
1312 ath_bus_cleanup(sc);
1313 ieee80211_free_hw(sc->hw);
1314}
1315
6baff7f9 1316void ath_detach(struct ath_softc *sc)
f078f209 1317{
8feceb67 1318 struct ieee80211_hw *hw = sc->hw;
9c84b797 1319 int i = 0;
f078f209 1320
3cbb5dd7
VN		 1321 ath9k_ps_wakeup(sc);
1322
04bd4638 1323 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1324
e97275cb 1325#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1326 ath_deinit_rfkill(sc);
1327#endif
3fcdfb4b
VT		 1328 ath_deinit_leds(sc);
1329
1330 ieee80211_unregister_hw(hw);
8feceb67
VT		 1331 ath_rx_cleanup(sc);
1332 ath_tx_cleanup(sc);
f078f209 1333
9c84b797
S		 1334 tasklet_kill(&sc->intr_tq);
1335 tasklet_kill(&sc->bcon_tasklet);
f078f209 1336
9c84b797
S		 1337 if (!(sc->sc_flags & SC_OP_INVALID))
1338 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1339
9c84b797
S		 1340 /* cleanup tx queues */
1341 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1342 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1343 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1344
1345 ath9k_hw_detach(sc->sc_ah);
826d2680 1346 ath9k_exit_debug(sc);
3cbb5dd7 1347 ath9k_ps_restore(sc);
f078f209
LR		 1348}
1349
ff37e337
S		 1350static int ath_init(u16 devid, struct ath_softc *sc)
1351{
cbe61d8a 1352 struct ath_hw *ah = NULL;
ff37e337
S		 1353 int status;
1354 int error = 0, i;
1355 int csz = 0;
1356
1357 /* XXX: hardware will not be ready until ath_open() being called */
1358 sc->sc_flags |= SC_OP_INVALID;
88b126af 1359
826d2680
S		 1360 if (ath9k_init_debug(sc) < 0)
1361 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S		 1362
1363 spin_lock_init(&sc->sc_resetlock);
aa33de09 1364 mutex_init(&sc->mutex);
ff37e337
S		 1365 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1366 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1367 (unsigned long)sc);
1368
1369 /*
1370 * Cache line size is used to size and align various
1371 * structures used to communicate with the hardware.
1372 */
88d15707 1373 ath_read_cachesize(sc, &csz);
ff37e337 1374 /* XXX assert csz is non-zero */
17d7904d 1375 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1376
cbe61d8a 1377 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1378 if (ah == NULL) {
1379 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1380 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1381 error = -ENXIO;
1382 goto bad;
1383 }
1384 sc->sc_ah = ah;
1385
1386 /* Get the hardware key cache size. */
2660b81a 1387 sc->keymax = ah->caps.keycache_size;
17d7904d 1388 if (sc->keymax > ATH_KEYMAX) {
ff37e337 1389 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 1390 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1391 ATH_KEYMAX, sc->keymax);
1392 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1393 }
1394
1395 /*
1396 * Reset the key cache since some parts do not
1397 * reset the contents on initial power up.
1398 */
17d7904d 1399 for (i = 0; i < sc->keymax; i++)
ff37e337 1400 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1401
5f8e077c 1402 if (ath9k_regd_init(sc->sc_ah))
ff37e337
S		 1403 goto bad;
1404
1405 /* default to MONITOR mode */
2660b81a 1406 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1407
ff37e337
S		 1408 /* Setup rate tables */
1409
1410 ath_rate_attach(sc);
1411 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1412 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1413
1414 /*
1415 * Allocate hardware transmit queues: one queue for
1416 * beacon frames and one data queue for each QoS
1417 * priority. Note that the hal handles reseting
1418 * these queues at the needed time.
1419 */
b77f483f
S		 1420 sc->beacon.beaconq = ath_beaconq_setup(ah);
1421 if (sc->beacon.beaconq == -1) {
ff37e337 1422 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1423 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1424 error = -EIO;
1425 goto bad2;
1426 }
b77f483f
S		 1427 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1428 if (sc->beacon.cabq == NULL) {
ff37e337 1429 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1430 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1431 error = -EIO;
1432 goto bad2;
1433 }
1434
17d7904d 1435 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1436 ath_cabq_update(sc);
1437
b77f483f
S		 1438 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1439 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1440
1441 /* Setup data queues */
1442 /* NB: ensure BK queue is the lowest priority h/w queue */
1443 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1444 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1445 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1446 error = -EIO;
1447 goto bad2;
1448 }
1449
1450 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1451 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1452 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1453 error = -EIO;
1454 goto bad2;
1455 }
1456 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1457 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1458 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1459 error = -EIO;
1460 goto bad2;
1461 }
1462 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1463 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1464 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1465 error = -EIO;
1466 goto bad2;
1467 }
1468
1469 /* Initializes the noise floor to a reasonable default value.
1470 * Later on this will be updated during ANI processing. */
1471
17d7904d
S		 1472 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1473 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1474
1475 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1476 ATH9K_CIPHER_TKIP, NULL)) {
1477 /*
1478 * Whether we should enable h/w TKIP MIC.
1479 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1480 * report WMM capable, so it's always safe to turn on
1481 * TKIP MIC in this case.
1482 */
1483 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1484 0, 1, NULL);
1485 }
1486
1487 /*
1488 * Check whether the separate key cache entries
1489 * are required to handle both tx+rx MIC keys.
1490 * With split mic keys the number of stations is limited
1491 * to 27 otherwise 59.
1492 */
1493 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1494 ATH9K_CIPHER_TKIP, NULL)
1495 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1496 ATH9K_CIPHER_MIC, NULL)
1497 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1498 0, NULL))
17d7904d 1499 sc->splitmic = 1;
ff37e337
S		 1500
1501 /* turn on mcast key search if possible */
1502 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1503 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1504 1, NULL);
1505
17d7904d 1506 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1507
1508 /* 11n Capabilities */
2660b81a 1509 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1510 sc->sc_flags |= SC_OP_TXAGGR;
1511 sc->sc_flags |= SC_OP_RXAGGR;
1512 }
1513
2660b81a
S		 1514 sc->tx_chainmask = ah->caps.tx_chainmask;
1515 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1516
1517 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1518 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1519
2660b81a 1520 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
ba52da58 1521 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
17d7904d 1522 ATH_SET_VIF_BSSID_MASK(sc->bssidmask);
ba52da58 1523 ath9k_hw_setbssidmask(sc);
ff37e337
S		 1524 }
1525
b77f483f 1526 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1527
1528 /* initialize beacon slots */
b77f483f
S		 1529 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1530 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
ff37e337
S		 1531
1532 /* save MISC configurations */
17d7904d 1533 sc->config.swBeaconProcess = 1;
ff37e337 1534
ff37e337
S		 1535 /* setup channels and rates */
1536
5f8e077c 1537 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1538 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1539 sc->rates[IEEE80211_BAND_2GHZ];
1540 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1541 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1542 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1543
2660b81a 1544 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1545 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1546 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1547 sc->rates[IEEE80211_BAND_5GHZ];
1548 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1549 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1550 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1551 }
1552
2660b81a 1553 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1554 ath9k_hw_btcoex_enable(sc->sc_ah);
1555
ff37e337
S		 1556 return 0;
1557bad2:
1558 /* cleanup tx queues */
1559 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1560 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1561 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1562bad:
1563 if (ah)
1564 ath9k_hw_detach(ah);
40b130a9 1565 ath9k_exit_debug(sc);
ff37e337
S		 1566
1567 return error;
1568}
1569
6baff7f9 1570int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1571{
8feceb67 1572 struct ieee80211_hw *hw = sc->hw;
191a99b7 1573 const struct ieee80211_regdomain *regd;
40b130a9 1574 int error = 0, i;
f078f209 1575
04bd4638 1576 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1577
8feceb67
VT		 1578 error = ath_init(devid, sc);
1579 if (error != 0)
1580 return error;
f078f209 1581
8feceb67 1582 /* get mac address from hardware and set in mac80211 */
f078f209 1583
ba52da58 1584 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
f078f209 1585
9c84b797
S		 1586 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1587 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1588 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1589 IEEE80211_HW_AMPDU_AGGREGATION |
1590 IEEE80211_HW_SUPPORTS_PS |
1591 IEEE80211_HW_PS_NULLFUNC_STACK;
f078f209 1592
0ced0e17
JM		 1593 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1594 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1595
9c84b797
S		 1596 hw->wiphy->interface_modes =
1597 BIT(NL80211_IFTYPE_AP) |
1598 BIT(NL80211_IFTYPE_STATION) |
1599 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1600
5f8e077c
LR		 1601 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1602 hw->wiphy->strict_regulatory = true;
1603
8feceb67 1604 hw->queues = 4;
e63835b0
S		 1605 hw->max_rates = 4;
1606 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1607 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1608 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1609
8feceb67 1610 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1611
2660b81a 1612 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1613 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1614 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1615 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1616 }
1617
1618 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
2660b81a 1619 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
9c84b797
S		 1620 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1621 &sc->sbands[IEEE80211_BAND_5GHZ];
1622
db93e7b5
SB		 1623 /* initialize tx/rx engine */
1624 error = ath_tx_init(sc, ATH_TXBUF);
1625 if (error != 0)
40b130a9 1626 goto error_attach;
8feceb67 1627
db93e7b5
SB		 1628 error = ath_rx_init(sc, ATH_RXBUF);
1629 if (error != 0)
40b130a9 1630 goto error_attach;
8feceb67 1631
e97275cb 1632#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d 1633 /* Initialze h/w Rfkill */
2660b81a 1634 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1635 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1636
1637 /* Initialize s/w rfkill */
40b130a9
VT		 1638 error = ath_init_sw_rfkill(sc);
1639 if (error)
1640 goto error_attach;
500c064d
VT		 1641#endif
1642
5f8e077c 1643 if (ath9k_is_world_regd(sc->sc_ah)) {
191a99b7 1644 /* Anything applied here (prior to wiphy registration) gets
5f8e077c 1645 * saved on the wiphy orig_* parameters */
191a99b7 1646 regd = ath9k_world_regdomain(sc->sc_ah);
5f8e077c
LR		 1647 hw->wiphy->custom_regulatory = true;
1648 hw->wiphy->strict_regulatory = false;
5f8e077c
LR		 1649 } else {
1650 /* This gets applied in the case of the absense of CRDA,
191a99b7 1651 * it's our own custom world regulatory domain, similar to
5f8e077c 1652 * cfg80211's but we enable passive scanning */
191a99b7 1653 regd = ath9k_default_world_regdomain();
5f8e077c 1654 }
191a99b7
BC		 1655 wiphy_apply_custom_regulatory(hw->wiphy, regd);
1656 ath9k_reg_apply_radar_flags(hw->wiphy);
1657 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
5f8e077c 1658
db93e7b5 1659 error = ieee80211_register_hw(hw);
8feceb67 1660
5f8e077c 1661 if (!ath9k_is_world_regd(sc->sc_ah))
d6bad496 1662 regulatory_hint(hw->wiphy, sc->sc_ah->regulatory.alpha2);
5f8e077c 1663
db93e7b5
SB		 1664 /* Initialize LED control */
1665 ath_init_leds(sc);
8feceb67 1666
5f8e077c 1667
8feceb67 1668 return 0;
40b130a9
VT		 1669
1670error_attach:
1671 /* cleanup tx queues */
1672 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1673 if (ATH_TXQ_SETUP(sc, i))
1674 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1675
1676 ath9k_hw_detach(sc->sc_ah);
1677 ath9k_exit_debug(sc);
1678
8feceb67 1679 return error;
f078f209
LR		 1680}
1681
ff37e337
S		 1682int ath_reset(struct ath_softc *sc, bool retry_tx)
1683{
cbe61d8a 1684 struct ath_hw *ah = sc->sc_ah;
030bb495 1685 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1686 int r;
ff37e337
S		 1687
1688 ath9k_hw_set_interrupts(ah, 0);
043a0405 1689 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1690 ath_stoprecv(sc);
1691 ath_flushrecv(sc);
1692
1693 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1694 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1695 if (r)
ff37e337 1696 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1697 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1698 spin_unlock_bh(&sc->sc_resetlock);
1699
1700 if (ath_startrecv(sc) != 0)
04bd4638 1701 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1702
1703 /*
1704 * We may be doing a reset in response to a request
1705 * that changes the channel so update any state that
1706 * might change as a result.
1707 */
ce111bad 1708 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1709
1710 ath_update_txpow(sc);
1711
1712 if (sc->sc_flags & SC_OP_BEACONS)
1713 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1714
17d7904d 1715 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1716
1717 if (retry_tx) {
1718 int i;
1719 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1720 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1721 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1722 ath_txq_schedule(sc, &sc->tx.txq[i]);
1723 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1724 }
1725 }
1726 }
1727
ae8d2858 1728 return r;
ff37e337
S		 1729}
1730
1731/*
1732 * This function will allocate both the DMA descriptor structure, and the
1733 * buffers it contains. These are used to contain the descriptors used
1734 * by the system.
1735*/
1736int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1737 struct list_head *head, const char *name,
1738 int nbuf, int ndesc)
1739{
1740#define DS2PHYS(_dd, _ds) \
1741 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1742#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1743#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1744
1745 struct ath_desc *ds;
1746 struct ath_buf *bf;
1747 int i, bsize, error;
1748
04bd4638
S		 1749 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1750 name, nbuf, ndesc);
ff37e337
S		 1751
1752 /* ath_desc must be a multiple of DWORDs */
1753 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1754 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1755 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1756 error = -ENOMEM;
1757 goto fail;
1758 }
1759
1760 dd->dd_name = name;
1761 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1762
1763 /*
1764 * Need additional DMA memory because we can't use
1765 * descriptors that cross the 4K page boundary. Assume
1766 * one skipped descriptor per 4K page.
1767 */
2660b81a 1768 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1769 u32 ndesc_skipped =
1770 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1771 u32 dma_len;
1772
1773 while (ndesc_skipped) {
1774 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1775 dd->dd_desc_len += dma_len;
1776
1777 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1778 };
1779 }
1780
1781 /* allocate descriptors */
7da3c55c
GJ		 1782 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1783 &dd->dd_desc_paddr, GFP_ATOMIC);
ff37e337
S		 1784 if (dd->dd_desc == NULL) {
1785 error = -ENOMEM;
1786 goto fail;
1787 }
1788 ds = dd->dd_desc;
04bd4638
S		 1789 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1790 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1791 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1792
1793 /* allocate buffers */
1794 bsize = sizeof(struct ath_buf) * nbuf;
1795 bf = kmalloc(bsize, GFP_KERNEL);
1796 if (bf == NULL) {
1797 error = -ENOMEM;
1798 goto fail2;
1799 }
1800 memset(bf, 0, bsize);
1801 dd->dd_bufptr = bf;
1802
1803 INIT_LIST_HEAD(head);
1804 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1805 bf->bf_desc = ds;
1806 bf->bf_daddr = DS2PHYS(dd, ds);
1807
2660b81a 1808 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1809 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1810 /*
1811 * Skip descriptor addresses which can cause 4KB
1812 * boundary crossing (addr + length) with a 32 dword
1813 * descriptor fetch.
1814 */
1815 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1816 ASSERT((caddr_t) bf->bf_desc <
1817 ((caddr_t) dd->dd_desc +
1818 dd->dd_desc_len));
1819
1820 ds += ndesc;
1821 bf->bf_desc = ds;
1822 bf->bf_daddr = DS2PHYS(dd, ds);
1823 }
1824 }
1825 list_add_tail(&bf->list, head);
1826 }
1827 return 0;
1828fail2:
7da3c55c
GJ		 1829 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1830 dd->dd_desc_paddr);
ff37e337
S		 1831fail:
1832 memset(dd, 0, sizeof(*dd));
1833 return error;
1834#undef ATH_DESC_4KB_BOUND_CHECK
1835#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1836#undef DS2PHYS
1837}
1838
1839void ath_descdma_cleanup(struct ath_softc *sc,
1840 struct ath_descdma *dd,
1841 struct list_head *head)
1842{
7da3c55c
GJ		 1843 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1844 dd->dd_desc_paddr);
ff37e337
S		 1845
1846 INIT_LIST_HEAD(head);
1847 kfree(dd->dd_bufptr);
1848 memset(dd, 0, sizeof(*dd));
1849}
1850
1851int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1852{
1853 int qnum;
1854
1855 switch (queue) {
1856 case 0:
b77f483f 1857 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1858 break;
1859 case 1:
b77f483f 1860 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1861 break;
1862 case 2:
b77f483f 1863 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1864 break;
1865 case 3:
b77f483f 1866 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1867 break;
1868 default:
b77f483f 1869 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1870 break;
1871 }
1872
1873 return qnum;
1874}
1875
1876int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1877{
1878 int qnum;
1879
1880 switch (queue) {
1881 case ATH9K_WME_AC_VO:
1882 qnum = 0;
1883 break;
1884 case ATH9K_WME_AC_VI:
1885 qnum = 1;
1886 break;
1887 case ATH9K_WME_AC_BE:
1888 qnum = 2;
1889 break;
1890 case ATH9K_WME_AC_BK:
1891 qnum = 3;
1892 break;
1893 default:
1894 qnum = -1;
1895 break;
1896 }
1897
1898 return qnum;
1899}
1900
5f8e077c
LR		 1901/* XXX: Remove me once we don't depend on ath9k_channel for all
1902 * this redundant data */
1903static void ath9k_update_ichannel(struct ath_softc *sc,
1904 struct ath9k_channel *ichan)
1905{
1906 struct ieee80211_hw *hw = sc->hw;
1907 struct ieee80211_channel *chan = hw->conf.channel;
1908 struct ieee80211_conf *conf = &hw->conf;
1909
1910 ichan->channel = chan->center_freq;
1911 ichan->chan = chan;
1912
1913 if (chan->band == IEEE80211_BAND_2GHZ) {
1914 ichan->chanmode = CHANNEL_G;
1915 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1916 } else {
1917 ichan->chanmode = CHANNEL_A;
1918 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1919 }
1920
1921 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1922
1923 if (conf_is_ht(conf)) {
1924 if (conf_is_ht40(conf))
1925 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1926
1927 ichan->chanmode = ath_get_extchanmode(sc, chan,
1928 conf->channel_type);
1929 }
1930}
1931
ff37e337
S		 1932/**********************/
1933/* mac80211 callbacks */
1934/**********************/
1935
8feceb67 1936static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR		 1937{
1938 struct ath_softc *sc = hw->priv;
8feceb67 1939 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1940 struct ath9k_channel *init_channel;
ae8d2858 1941 int r, pos;
f078f209 1942
04bd4638
S		 1943 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1944 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1945
141b38b6
S		 1946 mutex_lock(&sc->mutex);
1947
8feceb67 1948 /* setup initial channel */
f078f209 1949
5f8e077c 1950 pos = curchan->hw_value;
f078f209 1951
2660b81a 1952 init_channel = &sc->sc_ah->channels[pos];
5f8e077c 1953 ath9k_update_ichannel(sc, init_channel);
ff37e337
S		 1954
1955 /* Reset SERDES registers */
1956 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1957
1958 /*
1959 * The basic interface to setting the hardware in a good
1960 * state is ``reset''. On return the hardware is known to
1961 * be powered up and with interrupts disabled. This must
1962 * be followed by initialization of the appropriate bits
1963 * and then setup of the interrupt mask.
1964 */
1965 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1966 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1967 if (r) {
ff37e337 1968 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1969 "Unable to reset hardware; reset status %u "
1970 "(freq %u MHz)\n", r,
1971 curchan->center_freq);
ff37e337 1972 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1973 goto mutex_unlock;
ff37e337
S		 1974 }
1975 spin_unlock_bh(&sc->sc_resetlock);
1976
1977 /*
1978 * This is needed only to setup initial state
1979 * but it's best done after a reset.
1980 */
1981 ath_update_txpow(sc);
8feceb67 1982
ff37e337
S		 1983 /*
1984 * Setup the hardware after reset:
1985 * The receive engine is set going.
1986 * Frame transmit is handled entirely
1987 * in the frame output path; there's nothing to do
1988 * here except setup the interrupt mask.
1989 */
1990 if (ath_startrecv(sc) != 0) {
8feceb67 1991 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1992 "Unable to start recv logic\n");
141b38b6
S		 1993 r = -EIO;
1994 goto mutex_unlock;
f078f209 1995 }
8feceb67 1996
ff37e337 1997 /* Setup our intr mask. */
17d7904d 1998 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 1999 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2000 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2001
2660b81a 2002 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2003 sc->imask |= ATH9K_INT_GTT;
ff37e337 2004
2660b81a 2005 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2006 sc->imask |= ATH9K_INT_CST;
ff37e337 2007
ce111bad 2008 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2009
2010 sc->sc_flags &= ~SC_OP_INVALID;
2011
2012 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 2013 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2014 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337
S		 2015
2016 ieee80211_wake_queues(sc->hw);
2017
e97275cb 2018#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 2019 r = ath_start_rfkill_poll(sc);
500c064d 2020#endif
141b38b6
S		 2021
2022mutex_unlock:
2023 mutex_unlock(&sc->mutex);
2024
ae8d2858 2025 return r;
f078f209
LR		 2026}
2027
8feceb67
VT		 2028static int ath9k_tx(struct ieee80211_hw *hw,
2029 struct sk_buff *skb)
f078f209 2030{
528f0c6b 2031 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 2032 struct ath_softc *sc = hw->priv;
528f0c6b 2033 struct ath_tx_control txctl;
8feceb67 2034 int hdrlen, padsize;
528f0c6b
S		 2035
2036 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2037
8feceb67
VT		 2038 /*
2039 * As a temporary workaround, assign seq# here; this will likely need
2040 * to be cleaned up to work better with Beacon transmission and virtual
2041 * BSSes.
2042 */
2043 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2044 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2045 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2046 sc->tx.seq_no += 0x10;
8feceb67 2047 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2048 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2049 }
f078f209 2050
8feceb67
VT		 2051 /* Add the padding after the header if this is not already done */
2052 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2053 if (hdrlen & 3) {
2054 padsize = hdrlen % 4;
2055 if (skb_headroom(skb) < padsize)
2056 return -1;
2057 skb_push(skb, padsize);
2058 memmove(skb->data, skb->data + padsize, hdrlen);
2059 }
2060
528f0c6b
S		 2061 /* Check if a tx queue is available */
2062
2063 txctl.txq = ath_test_get_txq(sc, skb);
2064 if (!txctl.txq)
2065 goto exit;
2066
04bd4638 2067 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2068
528f0c6b 2069 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 2070 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2071 goto exit;
8feceb67
VT		 2072 }
2073
528f0c6b
S		 2074 return 0;
2075exit:
2076 dev_kfree_skb_any(skb);
8feceb67 2077 return 0;
f078f209
LR		 2078}
2079
8feceb67 2080static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR		 2081{
2082 struct ath_softc *sc = hw->priv;
f078f209 2083
9c84b797 2084 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2085 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2086 return;
2087 }
8feceb67 2088
141b38b6 2089 mutex_lock(&sc->mutex);
ff37e337
S		 2090
2091 ieee80211_stop_queues(sc->hw);
2092
2093 /* make sure h/w will not generate any interrupt
2094 * before setting the invalid flag. */
2095 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2096
2097 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2098 ath_drain_all_txq(sc, false);
ff37e337
S		 2099 ath_stoprecv(sc);
2100 ath9k_hw_phy_disable(sc->sc_ah);
2101 } else
b77f483f 2102 sc->rx.rxlink = NULL;
ff37e337
S		 2103
2104#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a 2105 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
ff37e337
S		 2106 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2107#endif
2108 /* disable HAL and put h/w to sleep */
2109 ath9k_hw_disable(sc->sc_ah);
2110 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2111
2112 sc->sc_flags |= SC_OP_INVALID;
500c064d 2113
141b38b6
S		 2114 mutex_unlock(&sc->mutex);
2115
04bd4638 2116 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2117}
2118
8feceb67
VT		 2119static int ath9k_add_interface(struct ieee80211_hw *hw,
2120 struct ieee80211_if_init_conf *conf)
f078f209
LR		 2121{
2122 struct ath_softc *sc = hw->priv;
17d7904d 2123 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2124 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
f078f209 2125
17d7904d 2126 /* Support only vif for now */
8feceb67 2127
17d7904d 2128 if (sc->nvifs)
8feceb67
VT		 2129 return -ENOBUFS;
2130
141b38b6
S		 2131 mutex_lock(&sc->mutex);
2132
8feceb67 2133 switch (conf->type) {
05c914fe 2134 case NL80211_IFTYPE_STATION:
d97809db 2135 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2136 break;
05c914fe 2137 case NL80211_IFTYPE_ADHOC:
d97809db 2138 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2139 break;
05c914fe 2140 case NL80211_IFTYPE_AP:
d97809db 2141 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR		 2142 break;
2143 default:
2144 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2145 "Interface type %d not yet supported\n", conf->type);
8feceb67 2146 return -EOPNOTSUPP;
f078f209
LR		 2147 }
2148
17d7904d 2149 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2150
17d7904d 2151 /* Set the VIF opmode */
5640b08e
S		 2152 avp->av_opmode = ic_opmode;
2153 avp->av_bslot = -1;
2154
d97809db 2155 if (ic_opmode == NL80211_IFTYPE_AP)
5640b08e
S		 2156 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2157
17d7904d
S		 2158 sc->vifs[0] = conf->vif;
2159 sc->nvifs++;
5640b08e
S		 2160
2161 /* Set the device opmode */
2660b81a 2162 sc->sc_ah->opmode = ic_opmode;
5640b08e 2163
4e30ffa2
VN		 2164 /*
2165 * Enable MIB interrupts when there are hardware phy counters.
2166 * Note we only do this (at the moment) for station mode.
2167 */
4af9cf4f
S		 2168 if ((conf->type == NL80211_IFTYPE_STATION) ||
2169 (conf->type == NL80211_IFTYPE_ADHOC)) {
2170 if (ath9k_hw_phycounters(sc->sc_ah))
2171 sc->imask |= ATH9K_INT_MIB;
2172 sc->imask |= ATH9K_INT_TSFOOR;
2173 }
2174
4e30ffa2
VN		 2175 /*
2176 * Some hardware processes the TIM IE and fires an
2177 * interrupt when the TIM bit is set. For hardware
2178 * that does, if not overridden by configuration,
2179 * enable the TIM interrupt when operating as station.
2180 */
2660b81a 2181 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
4e30ffa2 2182 (conf->type == NL80211_IFTYPE_STATION) &&
17d7904d
S		 2183 !sc->config.swBeaconProcess)
2184 sc->imask |= ATH9K_INT_TIM;
4e30ffa2 2185
17d7904d 2186 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2187
6f255425
LR		 2188 if (conf->type == NL80211_IFTYPE_AP) {
2189 /* TODO: is this a suitable place to start ANI for AP mode? */
2190 /* Start ANI */
17d7904d 2191 mod_timer(&sc->ani.timer,
6f255425
LR		 2192 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2193 }
2194
141b38b6
S		 2195 mutex_unlock(&sc->mutex);
2196
8feceb67 2197 return 0;
f078f209
LR		 2198}
2199
8feceb67
VT		 2200static void ath9k_remove_interface(struct ieee80211_hw *hw,
2201 struct ieee80211_if_init_conf *conf)
f078f209 2202{
8feceb67 2203 struct ath_softc *sc = hw->priv;
17d7904d 2204 struct ath_vif *avp = (void *)conf->vif->drv_priv;
f078f209 2205
04bd4638 2206 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2207
141b38b6
S		 2208 mutex_lock(&sc->mutex);
2209
6f255425 2210 /* Stop ANI */
17d7904d 2211 del_timer_sync(&sc->ani.timer);
580f0b8a 2212
8feceb67 2213 /* Reclaim beacon resources */
2660b81a
S		 2214 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
2215 sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2216 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2217 ath_beacon_return(sc, avp);
580f0b8a 2218 }
f078f209 2219
8feceb67 2220 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2221
17d7904d
S		 2222 sc->vifs[0] = NULL;
2223 sc->nvifs--;
141b38b6
S		 2224
2225 mutex_unlock(&sc->mutex);
f078f209
LR		 2226}
2227
e8975581 2228static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2229{
8feceb67 2230 struct ath_softc *sc = hw->priv;
e8975581 2231 struct ieee80211_conf *conf = &hw->conf;
f078f209 2232
aa33de09 2233 mutex_lock(&sc->mutex);
141b38b6 2234
3cbb5dd7
VN		 2235 if (changed & IEEE80211_CONF_CHANGE_PS) {
2236 if (conf->flags & IEEE80211_CONF_PS) {
17d7904d
S		 2237 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2238 sc->imask |= ATH9K_INT_TIM_TIMER;
3cbb5dd7 2239 ath9k_hw_set_interrupts(sc->sc_ah,
17d7904d 2240 sc->imask);
3cbb5dd7
VN		 2241 }
2242 ath9k_hw_setrxabort(sc->sc_ah, 1);
2243 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2244 } else {
2245 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2246 ath9k_hw_setrxabort(sc->sc_ah, 0);
2247 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
17d7904d
S		 2248 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2249 sc->imask &= ~ATH9K_INT_TIM_TIMER;
3cbb5dd7 2250 ath9k_hw_set_interrupts(sc->sc_ah,
17d7904d 2251 sc->imask);
3cbb5dd7
VN		 2252 }
2253 }
2254 }
2255
4797938c 2256 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2257 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2258 int pos = curchan->hw_value;
ae5eb026 2259
04bd4638
S		 2260 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2261 curchan->center_freq);
f078f209 2262
5f8e077c 2263 /* XXX: remove me eventualy */
2660b81a 2264 ath9k_update_ichannel(sc, &sc->sc_ah->channels[pos]);
e11602b7 2265
ecf70441 2266 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2267
2660b81a 2268 if (ath_set_channel(sc, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2269 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2270 mutex_unlock(&sc->mutex);
e11602b7
S		 2271 return -EINVAL;
2272 }
094d05dc 2273 }
f078f209 2274
5c020dc6 2275 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2276 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2277
aa33de09 2278 mutex_unlock(&sc->mutex);
141b38b6 2279
f078f209
LR		 2280 return 0;
2281}
2282
8feceb67
VT		 2283static int ath9k_config_interface(struct ieee80211_hw *hw,
2284 struct ieee80211_vif *vif,
2285 struct ieee80211_if_conf *conf)
c83be688 2286{
8feceb67 2287 struct ath_softc *sc = hw->priv;
cbe61d8a 2288 struct ath_hw *ah = sc->sc_ah;
17d7904d 2289 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67
VT		 2290 u32 rfilt = 0;
2291 int error, i;
c83be688 2292
8feceb67
VT		 2293 /* TODO: Need to decide which hw opmode to use for multi-interface
2294 * cases */
05c914fe 2295 if (vif->type == NL80211_IFTYPE_AP &&
2660b81a
S		 2296 ah->opmode != NL80211_IFTYPE_AP) {
2297 ah->opmode = NL80211_IFTYPE_STATION;
8feceb67 2298 ath9k_hw_setopmode(ah);
ba52da58
S		 2299 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2300 sc->curaid = 0;
2301 ath9k_hw_write_associd(sc);
8feceb67
VT		 2302 /* Request full reset to get hw opmode changed properly */
2303 sc->sc_flags |= SC_OP_FULL_RESET;
2304 }
c83be688 2305
8feceb67
VT		 2306 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2307 !is_zero_ether_addr(conf->bssid)) {
2308 switch (vif->type) {
05c914fe
JB		 2309 case NL80211_IFTYPE_STATION:
2310 case NL80211_IFTYPE_ADHOC:
8feceb67 2311 /* Set BSSID */
17d7904d
S		 2312 memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2313 sc->curaid = 0;
ba52da58 2314 ath9k_hw_write_associd(sc);
c83be688 2315
8feceb67 2316 /* Set aggregation protection mode parameters */
17d7904d 2317 sc->config.ath_aggr_prot = 0;
c83be688 2318
8feceb67 2319 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2320 "RX filter 0x%x bssid %pM aid 0x%x\n",
17d7904d 2321 rfilt, sc->curbssid, sc->curaid);
c83be688 2322
8feceb67
VT		 2323 /* need to reconfigure the beacon */
2324 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2325
8feceb67
VT		 2326 break;
2327 default:
2328 break;
2329 }
2330 }
c83be688 2331
1f7d6cbf
S		 2332 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2333 (vif->type == NL80211_IFTYPE_AP)) {
2334 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2335 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2336 conf->enable_beacon)) {
2337 /*
2338 * Allocate and setup the beacon frame.
2339 *
2340 * Stop any previous beacon DMA. This may be
2341 * necessary, for example, when an ibss merge
2342 * causes reconfiguration; we may be called
2343 * with beacon transmission active.
2344 */
2345 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2346
1f7d6cbf
S		 2347 error = ath_beacon_alloc(sc, 0);
2348 if (error != 0)
2349 return error;
c83be688 2350
1f7d6cbf
S		 2351 ath_beacon_sync(sc, 0);
2352 }
8feceb67 2353 }
c83be688 2354
8feceb67 2355 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2356 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2357 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2358 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2359 ath9k_hw_keysetmac(sc->sc_ah,
2360 (u16)i,
17d7904d 2361 sc->curbssid);
8feceb67 2362 }
c83be688 2363
8feceb67 2364 /* Only legacy IBSS for now */
05c914fe 2365 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2366 ath_update_chainmask(sc, 0);
f078f209 2367
8feceb67
VT		 2368 return 0;
2369}
f078f209 2370
8feceb67
VT		 2371#define SUPPORTED_FILTERS \
2372 (FIF_PROMISC_IN_BSS | \
2373 FIF_ALLMULTI | \
2374 FIF_CONTROL | \
2375 FIF_OTHER_BSS | \
2376 FIF_BCN_PRBRESP_PROMISC | \
2377 FIF_FCSFAIL)
c83be688 2378
8feceb67
VT		 2379/* FIXME: sc->sc_full_reset ? */
2380static void ath9k_configure_filter(struct ieee80211_hw *hw,
2381 unsigned int changed_flags,
2382 unsigned int *total_flags,
2383 int mc_count,
2384 struct dev_mc_list *mclist)
2385{
2386 struct ath_softc *sc = hw->priv;
2387 u32 rfilt;
f078f209 2388
8feceb67
VT		 2389 changed_flags &= SUPPORTED_FILTERS;
2390 *total_flags &= SUPPORTED_FILTERS;
f078f209 2391
b77f483f 2392 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2393 rfilt = ath_calcrxfilter(sc);
2394 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2395
8feceb67 2396 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
ba52da58
S		 2397 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2398 memcpy(sc->curbssid, ath_bcast_mac, ETH_ALEN);
2399 sc->curaid = 0;
2400 ath9k_hw_write_associd(sc);
2401 }
8feceb67 2402 }
f078f209 2403
b77f483f 2404 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2405}
f078f209 2406
8feceb67
VT		 2407static void ath9k_sta_notify(struct ieee80211_hw *hw,
2408 struct ieee80211_vif *vif,
2409 enum sta_notify_cmd cmd,
17741cdc 2410 struct ieee80211_sta *sta)
8feceb67
VT		 2411{
2412 struct ath_softc *sc = hw->priv;
f078f209 2413
8feceb67
VT		 2414 switch (cmd) {
2415 case STA_NOTIFY_ADD:
5640b08e 2416 ath_node_attach(sc, sta);
8feceb67
VT		 2417 break;
2418 case STA_NOTIFY_REMOVE:
b5aa9bf9 2419 ath_node_detach(sc, sta);
8feceb67
VT		 2420 break;
2421 default:
2422 break;
2423 }
f078f209
LR		 2424}
2425
141b38b6 2426static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2427 const struct ieee80211_tx_queue_params *params)
f078f209 2428{
8feceb67
VT		 2429 struct ath_softc *sc = hw->priv;
2430 struct ath9k_tx_queue_info qi;
2431 int ret = 0, qnum;
f078f209 2432
8feceb67
VT		 2433 if (queue >= WME_NUM_AC)
2434 return 0;
f078f209 2435
141b38b6
S		 2436 mutex_lock(&sc->mutex);
2437
8feceb67
VT		 2438 qi.tqi_aifs = params->aifs;
2439 qi.tqi_cwmin = params->cw_min;
2440 qi.tqi_cwmax = params->cw_max;
2441 qi.tqi_burstTime = params->txop;
2442 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2443
8feceb67 2444 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2445 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2446 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2447 queue, qnum, params->aifs, params->cw_min,
2448 params->cw_max, params->txop);
f078f209 2449
8feceb67
VT		 2450 ret = ath_txq_update(sc, qnum, &qi);
2451 if (ret)
04bd4638 2452 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2453
141b38b6
S		 2454 mutex_unlock(&sc->mutex);
2455
8feceb67
VT		 2456 return ret;
2457}
f078f209 2458
8feceb67
VT		 2459static int ath9k_set_key(struct ieee80211_hw *hw,
2460 enum set_key_cmd cmd,
dc822b5d
JB		 2461 struct ieee80211_vif *vif,
2462 struct ieee80211_sta *sta,
8feceb67
VT		 2463 struct ieee80211_key_conf *key)
2464{
2465 struct ath_softc *sc = hw->priv;
2466 int ret = 0;
f078f209 2467
141b38b6 2468 mutex_lock(&sc->mutex);
3cbb5dd7 2469 ath9k_ps_wakeup(sc);
04bd4638 2470 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2471
8feceb67
VT		 2472 switch (cmd) {
2473 case SET_KEY:
dc822b5d 2474 ret = ath_key_config(sc, sta, key);
6ace2891
JM		 2475 if (ret >= 0) {
2476 key->hw_key_idx = ret;
8feceb67
VT		 2477 /* push IV and Michael MIC generation to stack */
2478 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2479 if (key->alg == ALG_TKIP)
2480 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2481 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2482 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2483 ret = 0;
8feceb67
VT		 2484 }
2485 break;
2486 case DISABLE_KEY:
2487 ath_key_delete(sc, key);
8feceb67
VT		 2488 break;
2489 default:
2490 ret = -EINVAL;
2491 }
f078f209 2492
3cbb5dd7 2493 ath9k_ps_restore(sc);
141b38b6
S		 2494 mutex_unlock(&sc->mutex);
2495
8feceb67
VT		 2496 return ret;
2497}
f078f209 2498
8feceb67
VT		 2499static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2500 struct ieee80211_vif *vif,
2501 struct ieee80211_bss_conf *bss_conf,
2502 u32 changed)
2503{
2504 struct ath_softc *sc = hw->priv;
f078f209 2505
141b38b6
S		 2506 mutex_lock(&sc->mutex);
2507
8feceb67 2508 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2509 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2510 bss_conf->use_short_preamble);
2511 if (bss_conf->use_short_preamble)
2512 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2513 else
2514 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2515 }
f078f209 2516
8feceb67 2517 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2518 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2519 bss_conf->use_cts_prot);
2520 if (bss_conf->use_cts_prot &&
2521 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2522 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2523 else
2524 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2525 }
f078f209 2526
8feceb67 2527 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2528 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2529 bss_conf->assoc);
5640b08e 2530 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2531 }
141b38b6
S		 2532
2533 mutex_unlock(&sc->mutex);
8feceb67 2534}
f078f209 2535
8feceb67
VT		 2536static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2537{
2538 u64 tsf;
2539 struct ath_softc *sc = hw->priv;
f078f209 2540
141b38b6
S		 2541 mutex_lock(&sc->mutex);
2542 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2543 mutex_unlock(&sc->mutex);
f078f209 2544
8feceb67
VT		 2545 return tsf;
2546}
f078f209 2547
3b5d665b
AF		 2548static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2549{
2550 struct ath_softc *sc = hw->priv;
3b5d665b 2551
141b38b6
S		 2552 mutex_lock(&sc->mutex);
2553 ath9k_hw_settsf64(sc->sc_ah, tsf);
2554 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2555}
2556
8feceb67
VT		 2557static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2558{
2559 struct ath_softc *sc = hw->priv;
c83be688 2560
141b38b6
S		 2561 mutex_lock(&sc->mutex);
2562 ath9k_hw_reset_tsf(sc->sc_ah);
2563 mutex_unlock(&sc->mutex);
8feceb67 2564}
f078f209 2565
8feceb67 2566static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2567 enum ieee80211_ampdu_mlme_action action,
2568 struct ieee80211_sta *sta,
2569 u16 tid, u16 *ssn)
8feceb67
VT		 2570{
2571 struct ath_softc *sc = hw->priv;
2572 int ret = 0;
f078f209 2573
8feceb67
VT		 2574 switch (action) {
2575 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2576 if (!(sc->sc_flags & SC_OP_RXAGGR))
2577 ret = -ENOTSUPP;
8feceb67
VT		 2578 break;
2579 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2580 break;
2581 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2582 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2583 if (ret < 0)
2584 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2585 "Unable to start TX aggregation\n");
8feceb67 2586 else
17741cdc 2587 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2588 break;
2589 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2590 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2591 if (ret < 0)
2592 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2593 "Unable to stop TX aggregation\n");
f078f209 2594
17741cdc 2595 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2596 break;
8469cdef
S		 2597 case IEEE80211_AMPDU_TX_RESUME:
2598 ath_tx_aggr_resume(sc, sta, tid);
2599 break;
8feceb67 2600 default:
04bd4638 2601 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2602 }
2603
2604 return ret;
f078f209
LR		 2605}
2606
6baff7f9 2607struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2608 .tx = ath9k_tx,
2609 .start = ath9k_start,
2610 .stop = ath9k_stop,
2611 .add_interface = ath9k_add_interface,
2612 .remove_interface = ath9k_remove_interface,
2613 .config = ath9k_config,
2614 .config_interface = ath9k_config_interface,
2615 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2616 .sta_notify = ath9k_sta_notify,
2617 .conf_tx = ath9k_conf_tx,
8feceb67 2618 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2619 .set_key = ath9k_set_key,
8feceb67 2620 .get_tsf = ath9k_get_tsf,
3b5d665b 2621 .set_tsf = ath9k_set_tsf,
8feceb67 2622 .reset_tsf = ath9k_reset_tsf,
4233df6b 2623 .ampdu_action = ath9k_ampdu_action,
8feceb67
VT		 2624};
2625
392dff83
BP		 2626static struct {
2627 u32 version;
2628 const char * name;
2629} ath_mac_bb_names[] = {
2630 { AR_SREV_VERSION_5416_PCI, "5416" },
2631 { AR_SREV_VERSION_5416_PCIE, "5418" },
2632 { AR_SREV_VERSION_9100, "9100" },
2633 { AR_SREV_VERSION_9160, "9160" },
2634 { AR_SREV_VERSION_9280, "9280" },
2635 { AR_SREV_VERSION_9285, "9285" }
2636};
2637
2638static struct {
2639 u16 version;
2640 const char * name;
2641} ath_rf_names[] = {
2642 { 0, "5133" },
2643 { AR_RAD5133_SREV_MAJOR, "5133" },
2644 { AR_RAD5122_SREV_MAJOR, "5122" },
2645 { AR_RAD2133_SREV_MAJOR, "2133" },
2646 { AR_RAD2122_SREV_MAJOR, "2122" }
2647};
2648
2649/*
2650 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2651 */
6baff7f9 2652const char *
392dff83
BP		 2653ath_mac_bb_name(u32 mac_bb_version)
2654{
2655 int i;
2656
2657 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2658 if (ath_mac_bb_names[i].version == mac_bb_version) {
2659 return ath_mac_bb_names[i].name;
2660 }
2661 }
2662
2663 return "????";
2664}
2665
2666/*
2667 * Return the RF name. "????" is returned if the RF is unknown.
2668 */
6baff7f9 2669const char *
392dff83
BP		 2670ath_rf_name(u16 rf_version)
2671{
2672 int i;
2673
2674 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2675 if (ath_rf_names[i].version == rf_version) {
2676 return ath_rf_names[i].name;
2677 }
2678 }
2679
2680 return "????";
2681}
2682
6baff7f9 2683static int __init ath9k_init(void)
f078f209 2684{
ca8a8560
VT		 2685 int error;
2686
ca8a8560
VT		 2687 /* Register rate control algorithm */
2688 error = ath_rate_control_register();
2689 if (error != 0) {
2690 printk(KERN_ERR
b51bb3cd
LR		 2691 "ath9k: Unable to register rate control "
2692 "algorithm: %d\n",
ca8a8560 2693 error);
6baff7f9 2694 goto err_out;
ca8a8560
VT		 2695 }
2696
6baff7f9
GJ		 2697 error = ath_pci_init();
2698 if (error < 0) {
f078f209 2699 printk(KERN_ERR
b51bb3cd 2700 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9
GJ		 2701 error = -ENODEV;
2702 goto err_rate_unregister;
f078f209
LR		 2703 }
2704
09329d37
GJ		 2705 error = ath_ahb_init();
2706 if (error < 0) {
2707 error = -ENODEV;
2708 goto err_pci_exit;
2709 }
2710
f078f209 2711 return 0;
6baff7f9 2712
09329d37
GJ		 2713 err_pci_exit:
2714 ath_pci_exit();
2715
6baff7f9
GJ		 2716 err_rate_unregister:
2717 ath_rate_control_unregister();
2718 err_out:
2719 return error;
f078f209 2720}
6baff7f9 2721module_init(ath9k_init);
f078f209 2722
6baff7f9 2723static void __exit ath9k_exit(void)
f078f209 2724{
09329d37 2725 ath_ahb_exit();
6baff7f9 2726 ath_pci_exit();
ca8a8560 2727 ath_rate_control_unregister();
04bd4638 2728 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2729}
6baff7f9 2730module_exit(ath9k_exit);
Linux kernel - Deliverables
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