projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rt2x00: Export all register stats through debugfs
[deliverable/linux.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
b3bd89ce
JM		 29static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
5f8e077c
LR		 33/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 30, \
39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 30, \
46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
ce111bad
LR		 104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
ff37e337 106{
030bb495
LR		 107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 118 else
030bb495
LR		 119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
96742256
LR		 133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 135 break;
136 default:
ce111bad 137 BUG_ON(1);
030bb495
LR		 138 break;
139 }
ff37e337
S		 140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
cbe61d8a 144 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 145 u32 txpow;
146
17d7904d
S		 147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 151 sc->curtxpow = txpow;
ff37e337
S		 152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
192 struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
ff37e337 227 sband->n_bitrates++;
f46730d1 228
04bd4638
S		 229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
ff37e337
S		 234/*
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
238*/
239static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
240{
cbe61d8a 241 struct ath_hw *ah = sc->sc_ah;
ff37e337 242 bool fastcc = true, stopped;
030bb495 243 struct ieee80211_hw *hw = sc->hw;
ae8d2858
LR		 244 struct ieee80211_channel *channel = hw->conf.channel;
245 int r;
ff37e337
S		 246
247 if (sc->sc_flags & SC_OP_INVALID)
248 return -EIO;
249
3cbb5dd7
VN		 250 ath9k_ps_wakeup(sc);
251
c0d7c7af
LR		 252 /*
253 * This is only performed if the channel settings have
254 * actually changed.
255 *
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
260 */
261 ath9k_hw_set_interrupts(ah, 0);
043a0405 262 ath_drain_all_txq(sc, false);
c0d7c7af 263 stopped = ath_stoprecv(sc);
ff37e337 264
c0d7c7af
LR		 265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
ff37e337 268
c0d7c7af
LR		 269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
270 fastcc = false;
271
272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 274 sc->sc_ah->curchan->channel,
c0d7c7af 275 channel->center_freq, sc->tx_chan_width);
ff37e337 276
c0d7c7af
LR		 277 spin_lock_bh(&sc->sc_resetlock);
278
279 r = ath9k_hw_reset(ah, hchan, fastcc);
280 if (r) {
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
283 "reset status %u\n",
284 channel->center_freq, r);
285 spin_unlock_bh(&sc->sc_resetlock);
286 return r;
ff37e337 287 }
c0d7c7af
LR		 288 spin_unlock_bh(&sc->sc_resetlock);
289
290 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
291 sc->sc_flags &= ~SC_OP_FULL_RESET;
292
293 if (ath_startrecv(sc) != 0) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to restart recv logic\n");
296 return -EIO;
297 }
298
299 ath_cache_conf_rate(sc, &hw->conf);
300 ath_update_txpow(sc);
17d7904d 301 ath9k_hw_set_interrupts(ah, sc->imask);
3cbb5dd7 302 ath9k_ps_restore(sc);
ff37e337
S		 303 return 0;
304}
305
306/*
307 * This routine performs the periodic noise floor calibration function
308 * that is used to adjust and optimize the chip performance. This
309 * takes environmental changes (location, temperature) into account.
310 * When the task is complete, it reschedules itself depending on the
311 * appropriate interval that was calculated.
312 */
313static void ath_ani_calibrate(unsigned long data)
314{
20977d3e
S		 315 struct ath_softc *sc = (struct ath_softc *)data;
316 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 317 bool longcal = false;
318 bool shortcal = false;
319 bool aniflag = false;
320 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 321 u32 cal_interval, short_cal_interval;
ff37e337 322
20977d3e
S		 323 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
324 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 325
326 /*
327 * don't calibrate when we're scanning.
328 * we are most likely not on our home channel.
329 */
0c98de65 330 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 331 goto set_timer;
ff37e337
S		 332
333 /* Long calibration runs independently of short calibration. */
17d7904d 334 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 335 longcal = true;
04bd4638 336 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 337 sc->ani.longcal_timer = timestamp;
ff37e337
S		 338 }
339
17d7904d
S		 340 /* Short calibration applies only while caldone is false */
341 if (!sc->ani.caldone) {
20977d3e 342 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 343 shortcal = true;
04bd4638 344 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 345 sc->ani.shortcal_timer = timestamp;
346 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 347 }
348 } else {
17d7904d 349 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 350 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 351 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
352 if (sc->ani.caldone)
353 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 354 }
355 }
356
357 /* Verify whether we must check ANI */
20977d3e 358 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 359 aniflag = true;
17d7904d 360 sc->ani.checkani_timer = timestamp;
ff37e337
S		 361 }
362
363 /* Skip all processing if there's nothing to do. */
364 if (longcal || shortcal || aniflag) {
365 /* Call ANI routine if necessary */
366 if (aniflag)
20977d3e 367 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 368
369 /* Perform calibration if necessary */
370 if (longcal || shortcal) {
371 bool iscaldone = false;
372
2660b81a 373 if (ath9k_hw_calibrate(ah, ah->curchan,
17d7904d 374 sc->rx_chainmask, longcal,
ff37e337
S		 375 &iscaldone)) {
376 if (longcal)
17d7904d 377 sc->ani.noise_floor =
ff37e337 378 ath9k_hw_getchan_noise(ah,
2660b81a 379 ah->curchan);
ff37e337
S		 380
381 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 382 "calibrate chan %u/%x nf: %d\n",
2660b81a
S		 383 ah->curchan->channel,
384 ah->curchan->channelFlags,
17d7904d 385 sc->ani.noise_floor);
ff37e337
S		 386 } else {
387 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 388 "calibrate chan %u/%x failed\n",
2660b81a
S		 389 ah->curchan->channel,
390 ah->curchan->channelFlags);
ff37e337 391 }
17d7904d 392 sc->ani.caldone = iscaldone;
ff37e337
S		 393 }
394 }
395
20977d3e 396set_timer:
ff37e337
S		 397 /*
398 * Set timer interval based on previous results.
399 * The interval must be the shortest necessary to satisfy ANI,
400 * short calibration and long calibration.
401 */
aac9207e 402 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 403 if (sc->sc_ah->config.enable_ani)
aac9207e 404 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 405 if (!sc->ani.caldone)
20977d3e 406 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 407
17d7904d 408 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 409}
410
411/*
412 * Update tx/rx chainmask. For legacy association,
413 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 414 * the chainmask configuration, for bt coexistence, use
415 * the chainmask configuration even in legacy mode.
ff37e337
S		 416 */
417static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
418{
419 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
c97c92d9 420 if (is_ht ||
2660b81a
S		 421 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
422 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
423 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 424 } else {
17d7904d
S		 425 sc->tx_chainmask = 1;
426 sc->rx_chainmask = 1;
ff37e337
S		 427 }
428
04bd4638 429 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 430 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 431}
432
433static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
434{
435 struct ath_node *an;
436
437 an = (struct ath_node *)sta->drv_priv;
438
439 if (sc->sc_flags & SC_OP_TXAGGR)
440 ath_tx_node_init(sc, an);
441
442 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
443 sta->ht_cap.ampdu_factor);
444 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
445}
446
447static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
448{
449 struct ath_node *an = (struct ath_node *)sta->drv_priv;
450
451 if (sc->sc_flags & SC_OP_TXAGGR)
452 ath_tx_node_cleanup(sc, an);
453}
454
455static void ath9k_tasklet(unsigned long data)
456{
457 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 458 u32 status = sc->intrstatus;
ff37e337
S		 459
460 if (status & ATH9K_INT_FATAL) {
461 /* need a chip reset */
462 ath_reset(sc, false);
463 return;
464 } else {
465
466 if (status &
467 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 468 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 469 ath_rx_tasklet(sc, 0);
b77f483f 470 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 471 }
472 /* XXX: optimize this */
473 if (status & ATH9K_INT_TX)
474 ath_tx_tasklet(sc);
475 }
476
477 /* re-enable hardware interrupt */
17d7904d 478 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337
S		 479}
480
6baff7f9 481irqreturn_t ath_isr(int irq, void *dev)
ff37e337
S		 482{
483 struct ath_softc *sc = dev;
cbe61d8a 484 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 485 enum ath9k_int status;
486 bool sched = false;
487
488 do {
489 if (sc->sc_flags & SC_OP_INVALID) {
490 /*
491 * The hardware is not ready/present, don't
492 * touch anything. Note this can happen early
493 * on if the IRQ is shared.
494 */
495 return IRQ_NONE;
496 }
497 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
498 return IRQ_NONE;
499 }
500
501 /*
502 * Figure out the reason(s) for the interrupt. Note
503 * that the hal returns a pseudo-ISR that may include
504 * bits we haven't explicitly enabled so we mask the
505 * value to insure we only process bits we requested.
506 */
507 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
508
17d7904d 509 status &= sc->imask; /* discard unasked-for bits */
ff37e337
S		 510
511 /*
512 * If there are no status bits set, then this interrupt was not
513 * for me (should have been caught above).
514 */
515 if (!status)
516 return IRQ_NONE;
517
17d7904d 518 sc->intrstatus = status;
541d8dd5 519 ath9k_ps_wakeup(sc);
ff37e337
S		 520
521 if (status & ATH9K_INT_FATAL) {
522 /* need a chip reset */
523 sched = true;
524 } else if (status & ATH9K_INT_RXORN) {
525 /* need a chip reset */
526 sched = true;
527 } else {
528 if (status & ATH9K_INT_SWBA) {
529 /* schedule a tasklet for beacon handling */
530 tasklet_schedule(&sc->bcon_tasklet);
531 }
532 if (status & ATH9K_INT_RXEOL) {
533 /*
534 * NB: the hardware should re-read the link when
535 * RXE bit is written, but it doesn't work
536 * at least on older hardware revs.
537 */
538 sched = true;
539 }
540
541 if (status & ATH9K_INT_TXURN)
542 /* bump tx trigger level */
543 ath9k_hw_updatetxtriglevel(ah, true);
544 /* XXX: optimize this */
545 if (status & ATH9K_INT_RX)
546 sched = true;
547 if (status & ATH9K_INT_TX)
548 sched = true;
549 if (status & ATH9K_INT_BMISS)
550 sched = true;
551 /* carrier sense timeout */
552 if (status & ATH9K_INT_CST)
553 sched = true;
554 if (status & ATH9K_INT_MIB) {
555 /*
556 * Disable interrupts until we service the MIB
557 * interrupt; otherwise it will continue to
558 * fire.
559 */
560 ath9k_hw_set_interrupts(ah, 0);
561 /*
562 * Let the hal handle the event. We assume
563 * it will clear whatever condition caused
564 * the interrupt.
565 */
17d7904d
S		 566 ath9k_hw_procmibevent(ah, &sc->nodestats);
567 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 568 }
569 if (status & ATH9K_INT_TIM_TIMER) {
2660b81a 570 if (!(ah->caps.hw_caps &
ff37e337
S		 571 ATH9K_HW_CAP_AUTOSLEEP)) {
572 /* Clear RxAbort bit so that we can
573 * receive frames */
3cbb5dd7 574 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
ff37e337
S		 575 ath9k_hw_setrxabort(ah, 0);
576 sched = true;
3cbb5dd7 577 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337
S		 578 }
579 }
4af9cf4f
S		 580 if (status & ATH9K_INT_TSFOOR) {
581 /* FIXME: Handle this interrupt for power save */
582 sched = true;
583 }
ff37e337 584 }
541d8dd5 585 ath9k_ps_restore(sc);
ff37e337
S		 586 } while (0);
587
817e11de
S		 588 ath_debug_stat_interrupt(sc, status);
589
ff37e337
S		 590 if (sched) {
591 /* turn off every interrupt except SWBA */
17d7904d 592 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 593 tasklet_schedule(&sc->intr_tq);
594 }
595
596 return IRQ_HANDLED;
597}
598
f078f209 599static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 600 struct ieee80211_channel *chan,
094d05dc 601 enum nl80211_channel_type channel_type)
f078f209
LR		 602{
603 u32 chanmode = 0;
f078f209
LR		 604
605 switch (chan->band) {
606 case IEEE80211_BAND_2GHZ:
094d05dc
S		 607 switch(channel_type) {
608 case NL80211_CHAN_NO_HT:
609 case NL80211_CHAN_HT20:
f078f209 610 chanmode = CHANNEL_G_HT20;
094d05dc
S		 611 break;
612 case NL80211_CHAN_HT40PLUS:
f078f209 613 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 614 break;
615 case NL80211_CHAN_HT40MINUS:
f078f209 616 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 617 break;
618 }
f078f209
LR		 619 break;
620 case IEEE80211_BAND_5GHZ:
094d05dc
S		 621 switch(channel_type) {
622 case NL80211_CHAN_NO_HT:
623 case NL80211_CHAN_HT20:
f078f209 624 chanmode = CHANNEL_A_HT20;
094d05dc
S		 625 break;
626 case NL80211_CHAN_HT40PLUS:
f078f209 627 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 628 break;
629 case NL80211_CHAN_HT40MINUS:
f078f209 630 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 631 break;
632 }
f078f209
LR		 633 break;
634 default:
635 break;
636 }
637
638 return chanmode;
639}
640
6ace2891 641static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 642 struct ath9k_keyval *hk, const u8 *addr,
643 bool authenticator)
f078f209 644{
6ace2891
JM		 645 const u8 *key_rxmic;
646 const u8 *key_txmic;
f078f209 647
6ace2891
JM		 648 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
649 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 650
651 if (addr == NULL) {
d216aaa6
JM		 652 /*
653 * Group key installation - only two key cache entries are used
654 * regardless of splitmic capability since group key is only
655 * used either for TX or RX.
656 */
3f53dd64
JM		 657 if (authenticator) {
658 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
659 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
660 } else {
661 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
662 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
663 }
d216aaa6 664 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 665 }
17d7904d 666 if (!sc->splitmic) {
d216aaa6 667 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 668 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
669 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 670 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 671 }
d216aaa6
JM		 672
673 /* Separate key cache entries for TX and RX */
674
675 /* TX key goes at first index, RX key at +32. */
f078f209 676 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 677 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
678 /* TX MIC entry failed. No need to proceed further */
f078f209 679 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 680 "Setting TX MIC Key Failed\n");
f078f209
LR		 681 return 0;
682 }
683
684 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
685 /* XXX delete tx key on failure? */
d216aaa6 686 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 687}
688
689static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
690{
691 int i;
692
17d7904d
S		 693 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
694 if (test_bit(i, sc->keymap) ||
695 test_bit(i + 64, sc->keymap))
6ace2891 696 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 697 if (sc->splitmic &&
698 (test_bit(i + 32, sc->keymap) ||
699 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 700 continue; /* At least one part of TKIP key allocated */
701
702 /* Found a free slot for a TKIP key */
703 return i;
704 }
705 return -1;
706}
707
708static int ath_reserve_key_cache_slot(struct ath_softc *sc)
709{
710 int i;
711
712 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 713 if (sc->splitmic) {
714 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
715 if (!test_bit(i, sc->keymap) &&
716 (test_bit(i + 32, sc->keymap) ||
717 test_bit(i + 64, sc->keymap) ||
718 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 719 return i;
17d7904d
S		 720 if (!test_bit(i + 32, sc->keymap) &&
721 (test_bit(i, sc->keymap) ||
722 test_bit(i + 64, sc->keymap) ||
723 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 724 return i + 32;
17d7904d
S		 725 if (!test_bit(i + 64, sc->keymap) &&
726 (test_bit(i , sc->keymap) ||
727 test_bit(i + 32, sc->keymap) ||
728 test_bit(i + 64 + 32, sc->keymap)))
ea612132 729 return i + 64;
17d7904d
S		 730 if (!test_bit(i + 64 + 32, sc->keymap) &&
731 (test_bit(i, sc->keymap) ||
732 test_bit(i + 32, sc->keymap) ||
733 test_bit(i + 64, sc->keymap)))
ea612132 734 return i + 64 + 32;
6ace2891
JM		 735 }
736 } else {
17d7904d
S		 737 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
738 if (!test_bit(i, sc->keymap) &&
739 test_bit(i + 64, sc->keymap))
6ace2891 740 return i;
17d7904d
S		 741 if (test_bit(i, sc->keymap) &&
742 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 743 return i + 64;
744 }
745 }
746
747 /* No partially used TKIP slots, pick any available slot */
17d7904d 748 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 749 /* Do not allow slots that could be needed for TKIP group keys
750 * to be used. This limitation could be removed if we know that
751 * TKIP will not be used. */
752 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
753 continue;
17d7904d 754 if (sc->splitmic) {
be2864cf
JM		 755 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
756 continue;
757 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
758 continue;
759 }
760
17d7904d 761 if (!test_bit(i, sc->keymap))
6ace2891
JM		 762 return i; /* Found a free slot for a key */
763 }
764
765 /* No free slot found */
766 return -1;
f078f209
LR		 767}
768
769static int ath_key_config(struct ath_softc *sc,
3f53dd64 770 struct ieee80211_vif *vif,
dc822b5d 771 struct ieee80211_sta *sta,
f078f209
LR		 772 struct ieee80211_key_conf *key)
773{
f078f209
LR		 774 struct ath9k_keyval hk;
775 const u8 *mac = NULL;
776 int ret = 0;
6ace2891 777 int idx;
f078f209
LR		 778
779 memset(&hk, 0, sizeof(hk));
780
781 switch (key->alg) {
782 case ALG_WEP:
783 hk.kv_type = ATH9K_CIPHER_WEP;
784 break;
785 case ALG_TKIP:
786 hk.kv_type = ATH9K_CIPHER_TKIP;
787 break;
788 case ALG_CCMP:
789 hk.kv_type = ATH9K_CIPHER_AES_CCM;
790 break;
791 default:
ca470b29 792 return -EOPNOTSUPP;
f078f209
LR		 793 }
794
6ace2891 795 hk.kv_len = key->keylen;
f078f209
LR		 796 memcpy(hk.kv_val, key->key, key->keylen);
797
6ace2891
JM		 798 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
799 /* For now, use the default keys for broadcast keys. This may
800 * need to change with virtual interfaces. */
801 idx = key->keyidx;
802 } else if (key->keyidx) {
803 struct ieee80211_vif *vif;
f078f209 804
dc822b5d
JB		 805 if (WARN_ON(!sta))
806 return -EOPNOTSUPP;
807 mac = sta->addr;
808
17d7904d 809 vif = sc->vifs[0];
6ace2891
JM		 810 if (vif->type != NL80211_IFTYPE_AP) {
811 /* Only keyidx 0 should be used with unicast key, but
812 * allow this for client mode for now. */
813 idx = key->keyidx;
814 } else
815 return -EIO;
f078f209 816 } else {
dc822b5d
JB		 817 if (WARN_ON(!sta))
818 return -EOPNOTSUPP;
819 mac = sta->addr;
820
6ace2891
JM		 821 if (key->alg == ALG_TKIP)
822 idx = ath_reserve_key_cache_slot_tkip(sc);
823 else
824 idx = ath_reserve_key_cache_slot(sc);
825 if (idx < 0)
ca470b29 826 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 827 }
828
829 if (key->alg == ALG_TKIP)
3f53dd64
JM		 830 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
831 vif->type == NL80211_IFTYPE_AP);
f078f209 832 else
d216aaa6 833 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 834
835 if (!ret)
836 return -EIO;
837
17d7904d 838 set_bit(idx, sc->keymap);
6ace2891 839 if (key->alg == ALG_TKIP) {
17d7904d
S		 840 set_bit(idx + 64, sc->keymap);
841 if (sc->splitmic) {
842 set_bit(idx + 32, sc->keymap);
843 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 844 }
845 }
846
847 return idx;
f078f209
LR		 848}
849
850static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
851{
6ace2891
JM		 852 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
853 if (key->hw_key_idx < IEEE80211_WEP_NKID)
854 return;
855
17d7904d 856 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 857 if (key->alg != ALG_TKIP)
858 return;
f078f209 859
17d7904d
S		 860 clear_bit(key->hw_key_idx + 64, sc->keymap);
861 if (sc->splitmic) {
862 clear_bit(key->hw_key_idx + 32, sc->keymap);
863 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 864 }
f078f209
LR		 865}
866
eb2599ca
S		 867static void setup_ht_cap(struct ath_softc *sc,
868 struct ieee80211_sta_ht_cap *ht_info)
f078f209 869{
60653678
S		 870#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
871#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 872
d9fe60de
JB		 873 ht_info->ht_supported = true;
874 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
875 IEEE80211_HT_CAP_SM_PS |
876 IEEE80211_HT_CAP_SGI_40 |
877 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 878
60653678
S		 879 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
880 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 881
d9fe60de
JB		 882 /* set up supported mcs set */
883 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca 884
17d7904d 885 switch(sc->rx_chainmask) {
eb2599ca
S		 886 case 1:
887 ht_info->mcs.rx_mask[0] = 0xff;
888 break;
3c457265 889 case 3:
eb2599ca
S		 890 case 5:
891 case 7:
892 default:
893 ht_info->mcs.rx_mask[0] = 0xff;
894 ht_info->mcs.rx_mask[1] = 0xff;
895 break;
896 }
897
d9fe60de 898 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 899}
900
8feceb67 901static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 902 struct ieee80211_vif *vif,
8feceb67 903 struct ieee80211_bss_conf *bss_conf)
f078f209 904{
17d7904d 905 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 906
8feceb67 907 if (bss_conf->assoc) {
094d05dc 908 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 909 bss_conf->aid, sc->curbssid);
f078f209 910
8feceb67 911 /* New association, store aid */
d97809db 912 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
17d7904d 913 sc->curaid = bss_conf->aid;
ba52da58 914 ath9k_hw_write_associd(sc);
8feceb67 915 }
f078f209 916
8feceb67
VT		 917 /* Configure the beacon */
918 ath_beacon_config(sc, 0);
f078f209 919
8feceb67 920 /* Reset rssi stats */
17d7904d
S		 921 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
922 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
923 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
924 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 925
6f255425 926 /* Start ANI */
17d7904d 927 mod_timer(&sc->ani.timer,
20977d3e 928 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
8feceb67 929 } else {
04bd4638 930 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
17d7904d 931 sc->curaid = 0;
f078f209 932 }
8feceb67 933}
f078f209 934
8feceb67
VT		 935/********************************/
936/* LED functions */
937/********************************/
f078f209 938
f2bffa7e
VT		 939static void ath_led_blink_work(struct work_struct *work)
940{
941 struct ath_softc *sc = container_of(work, struct ath_softc,
942 ath_led_blink_work.work);
943
944 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
945 return;
946 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
947 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
948
949 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
950 (sc->sc_flags & SC_OP_LED_ON) ?
951 msecs_to_jiffies(sc->led_off_duration) :
952 msecs_to_jiffies(sc->led_on_duration));
953
954 sc->led_on_duration =
955 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
956 sc->led_off_duration =
957 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
958 sc->led_on_cnt = sc->led_off_cnt = 0;
959 if (sc->sc_flags & SC_OP_LED_ON)
960 sc->sc_flags &= ~SC_OP_LED_ON;
961 else
962 sc->sc_flags |= SC_OP_LED_ON;
963}
964
8feceb67
VT		 965static void ath_led_brightness(struct led_classdev *led_cdev,
966 enum led_brightness brightness)
967{
968 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
969 struct ath_softc *sc = led->sc;
f078f209 970
8feceb67
VT		 971 switch (brightness) {
972 case LED_OFF:
973 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 974 led->led_type == ATH_LED_RADIO) {
975 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
976 (led->led_type == ATH_LED_RADIO));
8feceb67 977 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 978 if (led->led_type == ATH_LED_RADIO)
979 sc->sc_flags &= ~SC_OP_LED_ON;
980 } else {
981 sc->led_off_cnt++;
982 }
8feceb67
VT		 983 break;
984 case LED_FULL:
f2bffa7e 985 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 986 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 987 queue_delayed_work(sc->hw->workqueue,
988 &sc->ath_led_blink_work, 0);
989 } else if (led->led_type == ATH_LED_RADIO) {
990 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
991 sc->sc_flags |= SC_OP_LED_ON;
992 } else {
993 sc->led_on_cnt++;
994 }
8feceb67
VT		 995 break;
996 default:
997 break;
f078f209 998 }
8feceb67 999}
f078f209 1000
8feceb67
VT		 1001static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1002 char *trigger)
1003{
1004 int ret;
f078f209 1005
8feceb67
VT		 1006 led->sc = sc;
1007 led->led_cdev.name = led->name;
1008 led->led_cdev.default_trigger = trigger;
1009 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1010
8feceb67
VT		 1011 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1012 if (ret)
1013 DPRINTF(sc, ATH_DBG_FATAL,
1014 "Failed to register led:%s", led->name);
1015 else
1016 led->registered = 1;
1017 return ret;
1018}
f078f209 1019
8feceb67
VT		 1020static void ath_unregister_led(struct ath_led *led)
1021{
1022 if (led->registered) {
1023 led_classdev_unregister(&led->led_cdev);
1024 led->registered = 0;
f078f209 1025 }
f078f209
LR		 1026}
1027
8feceb67 1028static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1029{
f2bffa7e 1030 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1031 ath_unregister_led(&sc->assoc_led);
1032 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1033 ath_unregister_led(&sc->tx_led);
1034 ath_unregister_led(&sc->rx_led);
1035 ath_unregister_led(&sc->radio_led);
1036 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1037}
f078f209 1038
8feceb67
VT		 1039static void ath_init_leds(struct ath_softc *sc)
1040{
1041 char *trigger;
1042 int ret;
f078f209 1043
8feceb67
VT		 1044 /* Configure gpio 1 for output */
1045 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1046 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1047 /* LED off, active low */
1048 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1049
f2bffa7e
VT		 1050 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1051
8feceb67
VT		 1052 trigger = ieee80211_get_radio_led_name(sc->hw);
1053 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1054 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1055 ret = ath_register_led(sc, &sc->radio_led, trigger);
1056 sc->radio_led.led_type = ATH_LED_RADIO;
1057 if (ret)
1058 goto fail;
7dcfdcd9 1059
8feceb67
VT		 1060 trigger = ieee80211_get_assoc_led_name(sc->hw);
1061 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1062 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1063 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1064 sc->assoc_led.led_type = ATH_LED_ASSOC;
1065 if (ret)
1066 goto fail;
f078f209 1067
8feceb67
VT		 1068 trigger = ieee80211_get_tx_led_name(sc->hw);
1069 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1070 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1071 ret = ath_register_led(sc, &sc->tx_led, trigger);
1072 sc->tx_led.led_type = ATH_LED_TX;
1073 if (ret)
1074 goto fail;
f078f209 1075
8feceb67
VT		 1076 trigger = ieee80211_get_rx_led_name(sc->hw);
1077 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1078 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1079 ret = ath_register_led(sc, &sc->rx_led, trigger);
1080 sc->rx_led.led_type = ATH_LED_RX;
1081 if (ret)
1082 goto fail;
f078f209 1083
8feceb67
VT		 1084 return;
1085
1086fail:
1087 ath_deinit_leds(sc);
f078f209
LR		 1088}
1089
e97275cb 1090#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1091
500c064d
VT		 1092/*******************/
1093/* Rfkill */
1094/*******************/
1095
1096static void ath_radio_enable(struct ath_softc *sc)
1097{
cbe61d8a 1098 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1099 struct ieee80211_channel *channel = sc->hw->conf.channel;
1100 int r;
500c064d 1101
3cbb5dd7 1102 ath9k_ps_wakeup(sc);
500c064d 1103 spin_lock_bh(&sc->sc_resetlock);
ae8d2858 1104
2660b81a 1105 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858
LR		 1106
1107 if (r) {
500c064d 1108 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1109 "Unable to reset channel %u (%uMhz) ",
1110 "reset status %u\n",
1111 channel->center_freq, r);
500c064d
VT		 1112 }
1113 spin_unlock_bh(&sc->sc_resetlock);
1114
1115 ath_update_txpow(sc);
1116 if (ath_startrecv(sc) != 0) {
1117 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1118 "Unable to restart recv logic\n");
500c064d
VT		 1119 return;
1120 }
1121
1122 if (sc->sc_flags & SC_OP_BEACONS)
1123 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1124
1125 /* Re-Enable interrupts */
17d7904d 1126 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1127
1128 /* Enable LED */
1129 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1130 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1131 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1132
1133 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1134 ath9k_ps_restore(sc);
500c064d
VT		 1135}
1136
1137static void ath_radio_disable(struct ath_softc *sc)
1138{
cbe61d8a 1139 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1140 struct ieee80211_channel *channel = sc->hw->conf.channel;
1141 int r;
500c064d 1142
3cbb5dd7 1143 ath9k_ps_wakeup(sc);
500c064d
VT		 1144 ieee80211_stop_queues(sc->hw);
1145
1146 /* Disable LED */
1147 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1148 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1149
1150 /* Disable interrupts */
1151 ath9k_hw_set_interrupts(ah, 0);
1152
043a0405 1153 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1154 ath_stoprecv(sc); /* turn off frame recv */
1155 ath_flushrecv(sc); /* flush recv queue */
1156
1157 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1158 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1159 if (r) {
500c064d 1160 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1161 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1162 "reset status %u\n",
1163 channel->center_freq, r);
500c064d
VT		 1164 }
1165 spin_unlock_bh(&sc->sc_resetlock);
1166
1167 ath9k_hw_phy_disable(ah);
1168 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1169 ath9k_ps_restore(sc);
500c064d
VT		 1170}
1171
1172static bool ath_is_rfkill_set(struct ath_softc *sc)
1173{
cbe61d8a 1174 struct ath_hw *ah = sc->sc_ah;
500c064d 1175
2660b81a
S		 1176 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1177 ah->rfkill_polarity;
500c064d
VT		 1178}
1179
1180/* h/w rfkill poll function */
1181static void ath_rfkill_poll(struct work_struct *work)
1182{
1183 struct ath_softc *sc = container_of(work, struct ath_softc,
1184 rf_kill.rfkill_poll.work);
1185 bool radio_on;
1186
1187 if (sc->sc_flags & SC_OP_INVALID)
1188 return;
1189
1190 radio_on = !ath_is_rfkill_set(sc);
1191
1192 /*
1193 * enable/disable radio only when there is a
1194 * state change in RF switch
1195 */
1196 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1197 enum rfkill_state state;
1198
1199 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1200 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1201 : RFKILL_STATE_HARD_BLOCKED;
1202 } else if (radio_on) {
1203 ath_radio_enable(sc);
1204 state = RFKILL_STATE_UNBLOCKED;
1205 } else {
1206 ath_radio_disable(sc);
1207 state = RFKILL_STATE_HARD_BLOCKED;
1208 }
1209
1210 if (state == RFKILL_STATE_HARD_BLOCKED)
1211 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1212 else
1213 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1214
1215 rfkill_force_state(sc->rf_kill.rfkill, state);
1216 }
1217
1218 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1219 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1220}
1221
1222/* s/w rfkill handler */
1223static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1224{
1225 struct ath_softc *sc = data;
1226
1227 switch (state) {
1228 case RFKILL_STATE_SOFT_BLOCKED:
1229 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1230 SC_OP_RFKILL_SW_BLOCKED)))
1231 ath_radio_disable(sc);
1232 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1233 return 0;
1234 case RFKILL_STATE_UNBLOCKED:
1235 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1236 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1237 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1238 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1239 "radio as it is disabled by h/w\n");
500c064d
VT		 1240 return -EPERM;
1241 }
1242 ath_radio_enable(sc);
1243 }
1244 return 0;
1245 default:
1246 return -EINVAL;
1247 }
1248}
1249
1250/* Init s/w rfkill */
1251static int ath_init_sw_rfkill(struct ath_softc *sc)
1252{
1253 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1254 RFKILL_TYPE_WLAN);
1255 if (!sc->rf_kill.rfkill) {
1256 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1257 return -ENOMEM;
1258 }
1259
1260 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
0818cb8a 1261 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
500c064d
VT		 1262 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1263 sc->rf_kill.rfkill->data = sc;
1264 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1265 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1266 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1267
1268 return 0;
1269}
1270
1271/* Deinitialize rfkill */
1272static void ath_deinit_rfkill(struct ath_softc *sc)
1273{
2660b81a 1274 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1275 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1276
1277 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1278 rfkill_unregister(sc->rf_kill.rfkill);
1279 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1280 sc->rf_kill.rfkill = NULL;
1281 }
1282}
9c84b797
S		 1283
1284static int ath_start_rfkill_poll(struct ath_softc *sc)
1285{
2660b81a 1286 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
9c84b797
S		 1287 queue_delayed_work(sc->hw->workqueue,
1288 &sc->rf_kill.rfkill_poll, 0);
1289
1290 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1291 if (rfkill_register(sc->rf_kill.rfkill)) {
1292 DPRINTF(sc, ATH_DBG_FATAL,
1293 "Unable to register rfkill\n");
1294 rfkill_free(sc->rf_kill.rfkill);
1295
1296 /* Deinitialize the device */
39c3c2f2 1297 ath_cleanup(sc);
9c84b797
S		 1298 return -EIO;
1299 } else {
1300 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1301 }
1302 }
1303
1304 return 0;
1305}
500c064d
VT		 1306#endif /* CONFIG_RFKILL */
1307
6baff7f9 1308void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1309{
1310 ath_detach(sc);
1311 free_irq(sc->irq, sc);
1312 ath_bus_cleanup(sc);
1313 ieee80211_free_hw(sc->hw);
1314}
1315
6baff7f9 1316void ath_detach(struct ath_softc *sc)
f078f209 1317{
8feceb67 1318 struct ieee80211_hw *hw = sc->hw;
9c84b797 1319 int i = 0;
f078f209 1320
3cbb5dd7
VN		 1321 ath9k_ps_wakeup(sc);
1322
04bd4638 1323 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1324
e97275cb 1325#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1326 ath_deinit_rfkill(sc);
1327#endif
3fcdfb4b
VT		 1328 ath_deinit_leds(sc);
1329
1330 ieee80211_unregister_hw(hw);
8feceb67
VT		 1331 ath_rx_cleanup(sc);
1332 ath_tx_cleanup(sc);
f078f209 1333
9c84b797
S		 1334 tasklet_kill(&sc->intr_tq);
1335 tasklet_kill(&sc->bcon_tasklet);
f078f209 1336
9c84b797
S		 1337 if (!(sc->sc_flags & SC_OP_INVALID))
1338 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1339
9c84b797
S		 1340 /* cleanup tx queues */
1341 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1342 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1343 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1344
1345 ath9k_hw_detach(sc->sc_ah);
826d2680 1346 ath9k_exit_debug(sc);
3cbb5dd7 1347 ath9k_ps_restore(sc);
f078f209
LR		 1348}
1349
ff37e337
S		 1350static int ath_init(u16 devid, struct ath_softc *sc)
1351{
cbe61d8a 1352 struct ath_hw *ah = NULL;
ff37e337
S		 1353 int status;
1354 int error = 0, i;
1355 int csz = 0;
1356
1357 /* XXX: hardware will not be ready until ath_open() being called */
1358 sc->sc_flags |= SC_OP_INVALID;
88b126af 1359
826d2680
S		 1360 if (ath9k_init_debug(sc) < 0)
1361 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S		 1362
1363 spin_lock_init(&sc->sc_resetlock);
aa33de09 1364 mutex_init(&sc->mutex);
ff37e337 1365 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1366 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1367 (unsigned long)sc);
1368
1369 /*
1370 * Cache line size is used to size and align various
1371 * structures used to communicate with the hardware.
1372 */
88d15707 1373 ath_read_cachesize(sc, &csz);
ff37e337 1374 /* XXX assert csz is non-zero */
17d7904d 1375 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1376
cbe61d8a 1377 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1378 if (ah == NULL) {
1379 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1380 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1381 error = -ENXIO;
1382 goto bad;
1383 }
1384 sc->sc_ah = ah;
1385
1386 /* Get the hardware key cache size. */
2660b81a 1387 sc->keymax = ah->caps.keycache_size;
17d7904d 1388 if (sc->keymax > ATH_KEYMAX) {
ff37e337 1389 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 1390 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1391 ATH_KEYMAX, sc->keymax);
1392 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1393 }
1394
1395 /*
1396 * Reset the key cache since some parts do not
1397 * reset the contents on initial power up.
1398 */
17d7904d 1399 for (i = 0; i < sc->keymax; i++)
ff37e337 1400 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1401
5f8e077c 1402 if (ath9k_regd_init(sc->sc_ah))
ff37e337
S		 1403 goto bad;
1404
1405 /* default to MONITOR mode */
2660b81a 1406 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1407
ff37e337
S		 1408 /* Setup rate tables */
1409
1410 ath_rate_attach(sc);
1411 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1412 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1413
1414 /*
1415 * Allocate hardware transmit queues: one queue for
1416 * beacon frames and one data queue for each QoS
1417 * priority. Note that the hal handles reseting
1418 * these queues at the needed time.
1419 */
b77f483f
S		 1420 sc->beacon.beaconq = ath_beaconq_setup(ah);
1421 if (sc->beacon.beaconq == -1) {
ff37e337 1422 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1423 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1424 error = -EIO;
1425 goto bad2;
1426 }
b77f483f
S		 1427 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1428 if (sc->beacon.cabq == NULL) {
ff37e337 1429 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1430 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1431 error = -EIO;
1432 goto bad2;
1433 }
1434
17d7904d 1435 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1436 ath_cabq_update(sc);
1437
b77f483f
S		 1438 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1439 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1440
1441 /* Setup data queues */
1442 /* NB: ensure BK queue is the lowest priority h/w queue */
1443 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1444 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1445 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1446 error = -EIO;
1447 goto bad2;
1448 }
1449
1450 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1451 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1452 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1453 error = -EIO;
1454 goto bad2;
1455 }
1456 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1457 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1458 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1459 error = -EIO;
1460 goto bad2;
1461 }
1462 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1463 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1464 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1465 error = -EIO;
1466 goto bad2;
1467 }
1468
1469 /* Initializes the noise floor to a reasonable default value.
1470 * Later on this will be updated during ANI processing. */
1471
17d7904d
S		 1472 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1473 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1474
1475 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1476 ATH9K_CIPHER_TKIP, NULL)) {
1477 /*
1478 * Whether we should enable h/w TKIP MIC.
1479 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1480 * report WMM capable, so it's always safe to turn on
1481 * TKIP MIC in this case.
1482 */
1483 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1484 0, 1, NULL);
1485 }
1486
1487 /*
1488 * Check whether the separate key cache entries
1489 * are required to handle both tx+rx MIC keys.
1490 * With split mic keys the number of stations is limited
1491 * to 27 otherwise 59.
1492 */
1493 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1494 ATH9K_CIPHER_TKIP, NULL)
1495 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1496 ATH9K_CIPHER_MIC, NULL)
1497 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1498 0, NULL))
17d7904d 1499 sc->splitmic = 1;
ff37e337
S		 1500
1501 /* turn on mcast key search if possible */
1502 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1503 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1504 1, NULL);
1505
17d7904d 1506 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1507
1508 /* 11n Capabilities */
2660b81a 1509 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1510 sc->sc_flags |= SC_OP_TXAGGR;
1511 sc->sc_flags |= SC_OP_RXAGGR;
1512 }
1513
2660b81a
S		 1514 sc->tx_chainmask = ah->caps.tx_chainmask;
1515 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1516
1517 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1518 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1519
2660b81a 1520 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
ba52da58 1521 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
17d7904d 1522 ATH_SET_VIF_BSSID_MASK(sc->bssidmask);
ba52da58 1523 ath9k_hw_setbssidmask(sc);
ff37e337
S		 1524 }
1525
b77f483f 1526 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1527
1528 /* initialize beacon slots */
b77f483f
S		 1529 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1530 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
ff37e337
S		 1531
1532 /* save MISC configurations */
17d7904d 1533 sc->config.swBeaconProcess = 1;
ff37e337 1534
ff37e337
S		 1535 /* setup channels and rates */
1536
5f8e077c 1537 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1538 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1539 sc->rates[IEEE80211_BAND_2GHZ];
1540 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1541 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1542 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1543
2660b81a 1544 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1545 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1546 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1547 sc->rates[IEEE80211_BAND_5GHZ];
1548 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1549 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1550 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1551 }
1552
2660b81a 1553 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1554 ath9k_hw_btcoex_enable(sc->sc_ah);
1555
ff37e337
S		 1556 return 0;
1557bad2:
1558 /* cleanup tx queues */
1559 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1560 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1561 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1562bad:
1563 if (ah)
1564 ath9k_hw_detach(ah);
40b130a9 1565 ath9k_exit_debug(sc);
ff37e337
S		 1566
1567 return error;
1568}
1569
6baff7f9 1570int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1571{
8feceb67 1572 struct ieee80211_hw *hw = sc->hw;
191a99b7 1573 const struct ieee80211_regdomain *regd;
40b130a9 1574 int error = 0, i;
f078f209 1575
04bd4638 1576 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1577
8feceb67
VT		 1578 error = ath_init(devid, sc);
1579 if (error != 0)
1580 return error;
f078f209 1581
8feceb67 1582 /* get mac address from hardware and set in mac80211 */
f078f209 1583
ba52da58 1584 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
f078f209 1585
9c84b797
S		 1586 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1587 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1588 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1589 IEEE80211_HW_AMPDU_AGGREGATION |
1590 IEEE80211_HW_SUPPORTS_PS |
1591 IEEE80211_HW_PS_NULLFUNC_STACK;
f078f209 1592
b3bd89ce 1593 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1594 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1595
9c84b797
S		 1596 hw->wiphy->interface_modes =
1597 BIT(NL80211_IFTYPE_AP) |
1598 BIT(NL80211_IFTYPE_STATION) |
1599 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1600
5f8e077c
LR		 1601 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1602 hw->wiphy->strict_regulatory = true;
1603
8feceb67 1604 hw->queues = 4;
e63835b0 1605 hw->max_rates = 4;
171387ef 1606 hw->channel_change_time = 5000;
e63835b0 1607 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1608 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1609 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1610
8feceb67 1611 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1612
2660b81a 1613 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1614 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1615 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1616 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1617 }
1618
1619 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
2660b81a 1620 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
9c84b797
S		 1621 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1622 &sc->sbands[IEEE80211_BAND_5GHZ];
1623
db93e7b5
SB		 1624 /* initialize tx/rx engine */
1625 error = ath_tx_init(sc, ATH_TXBUF);
1626 if (error != 0)
40b130a9 1627 goto error_attach;
8feceb67 1628
db93e7b5
SB		 1629 error = ath_rx_init(sc, ATH_RXBUF);
1630 if (error != 0)
40b130a9 1631 goto error_attach;
8feceb67 1632
e97275cb 1633#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d 1634 /* Initialze h/w Rfkill */
2660b81a 1635 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1636 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1637
1638 /* Initialize s/w rfkill */
40b130a9
VT		 1639 error = ath_init_sw_rfkill(sc);
1640 if (error)
1641 goto error_attach;
500c064d
VT		 1642#endif
1643
5f8e077c 1644 if (ath9k_is_world_regd(sc->sc_ah)) {
191a99b7 1645 /* Anything applied here (prior to wiphy registration) gets
5f8e077c 1646 * saved on the wiphy orig_* parameters */
191a99b7 1647 regd = ath9k_world_regdomain(sc->sc_ah);
5f8e077c
LR		 1648 hw->wiphy->custom_regulatory = true;
1649 hw->wiphy->strict_regulatory = false;
5f8e077c
LR		 1650 } else {
1651 /* This gets applied in the case of the absense of CRDA,
191a99b7 1652 * it's our own custom world regulatory domain, similar to
5f8e077c 1653 * cfg80211's but we enable passive scanning */
191a99b7 1654 regd = ath9k_default_world_regdomain();
5f8e077c 1655 }
191a99b7
BC		 1656 wiphy_apply_custom_regulatory(hw->wiphy, regd);
1657 ath9k_reg_apply_radar_flags(hw->wiphy);
1658 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
5f8e077c 1659
db93e7b5 1660 error = ieee80211_register_hw(hw);
8feceb67 1661
fe33eb39
LR		 1662 if (!ath9k_is_world_regd(sc->sc_ah)) {
1663 error = regulatory_hint(hw->wiphy,
1664 sc->sc_ah->regulatory.alpha2);
1665 if (error)
1666 goto error_attach;
1667 }
5f8e077c 1668
db93e7b5
SB		 1669 /* Initialize LED control */
1670 ath_init_leds(sc);
8feceb67 1671
5f8e077c 1672
8feceb67 1673 return 0;
40b130a9
VT		 1674
1675error_attach:
1676 /* cleanup tx queues */
1677 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1678 if (ATH_TXQ_SETUP(sc, i))
1679 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1680
1681 ath9k_hw_detach(sc->sc_ah);
1682 ath9k_exit_debug(sc);
1683
8feceb67 1684 return error;
f078f209
LR		 1685}
1686
ff37e337
S		 1687int ath_reset(struct ath_softc *sc, bool retry_tx)
1688{
cbe61d8a 1689 struct ath_hw *ah = sc->sc_ah;
030bb495 1690 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1691 int r;
ff37e337
S		 1692
1693 ath9k_hw_set_interrupts(ah, 0);
043a0405 1694 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1695 ath_stoprecv(sc);
1696 ath_flushrecv(sc);
1697
1698 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1699 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1700 if (r)
ff37e337 1701 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1702 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1703 spin_unlock_bh(&sc->sc_resetlock);
1704
1705 if (ath_startrecv(sc) != 0)
04bd4638 1706 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1707
1708 /*
1709 * We may be doing a reset in response to a request
1710 * that changes the channel so update any state that
1711 * might change as a result.
1712 */
ce111bad 1713 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1714
1715 ath_update_txpow(sc);
1716
1717 if (sc->sc_flags & SC_OP_BEACONS)
1718 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1719
17d7904d 1720 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1721
1722 if (retry_tx) {
1723 int i;
1724 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1725 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1726 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1727 ath_txq_schedule(sc, &sc->tx.txq[i]);
1728 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1729 }
1730 }
1731 }
1732
ae8d2858 1733 return r;
ff37e337
S		 1734}
1735
1736/*
1737 * This function will allocate both the DMA descriptor structure, and the
1738 * buffers it contains. These are used to contain the descriptors used
1739 * by the system.
1740*/
1741int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1742 struct list_head *head, const char *name,
1743 int nbuf, int ndesc)
1744{
1745#define DS2PHYS(_dd, _ds) \
1746 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1747#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1748#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1749
1750 struct ath_desc *ds;
1751 struct ath_buf *bf;
1752 int i, bsize, error;
1753
04bd4638
S		 1754 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1755 name, nbuf, ndesc);
ff37e337
S		 1756
1757 /* ath_desc must be a multiple of DWORDs */
1758 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1759 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1760 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1761 error = -ENOMEM;
1762 goto fail;
1763 }
1764
1765 dd->dd_name = name;
1766 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1767
1768 /*
1769 * Need additional DMA memory because we can't use
1770 * descriptors that cross the 4K page boundary. Assume
1771 * one skipped descriptor per 4K page.
1772 */
2660b81a 1773 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1774 u32 ndesc_skipped =
1775 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1776 u32 dma_len;
1777
1778 while (ndesc_skipped) {
1779 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1780 dd->dd_desc_len += dma_len;
1781
1782 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1783 };
1784 }
1785
1786 /* allocate descriptors */
7da3c55c
GJ		 1787 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1788 &dd->dd_desc_paddr, GFP_ATOMIC);
ff37e337
S		 1789 if (dd->dd_desc == NULL) {
1790 error = -ENOMEM;
1791 goto fail;
1792 }
1793 ds = dd->dd_desc;
04bd4638
S		 1794 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1795 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1796 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1797
1798 /* allocate buffers */
1799 bsize = sizeof(struct ath_buf) * nbuf;
1800 bf = kmalloc(bsize, GFP_KERNEL);
1801 if (bf == NULL) {
1802 error = -ENOMEM;
1803 goto fail2;
1804 }
1805 memset(bf, 0, bsize);
1806 dd->dd_bufptr = bf;
1807
1808 INIT_LIST_HEAD(head);
1809 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1810 bf->bf_desc = ds;
1811 bf->bf_daddr = DS2PHYS(dd, ds);
1812
2660b81a 1813 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1814 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1815 /*
1816 * Skip descriptor addresses which can cause 4KB
1817 * boundary crossing (addr + length) with a 32 dword
1818 * descriptor fetch.
1819 */
1820 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1821 ASSERT((caddr_t) bf->bf_desc <
1822 ((caddr_t) dd->dd_desc +
1823 dd->dd_desc_len));
1824
1825 ds += ndesc;
1826 bf->bf_desc = ds;
1827 bf->bf_daddr = DS2PHYS(dd, ds);
1828 }
1829 }
1830 list_add_tail(&bf->list, head);
1831 }
1832 return 0;
1833fail2:
7da3c55c
GJ		 1834 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1835 dd->dd_desc_paddr);
ff37e337
S		 1836fail:
1837 memset(dd, 0, sizeof(*dd));
1838 return error;
1839#undef ATH_DESC_4KB_BOUND_CHECK
1840#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1841#undef DS2PHYS
1842}
1843
1844void ath_descdma_cleanup(struct ath_softc *sc,
1845 struct ath_descdma *dd,
1846 struct list_head *head)
1847{
7da3c55c
GJ		 1848 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1849 dd->dd_desc_paddr);
ff37e337
S		 1850
1851 INIT_LIST_HEAD(head);
1852 kfree(dd->dd_bufptr);
1853 memset(dd, 0, sizeof(*dd));
1854}
1855
1856int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1857{
1858 int qnum;
1859
1860 switch (queue) {
1861 case 0:
b77f483f 1862 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1863 break;
1864 case 1:
b77f483f 1865 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1866 break;
1867 case 2:
b77f483f 1868 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1869 break;
1870 case 3:
b77f483f 1871 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1872 break;
1873 default:
b77f483f 1874 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1875 break;
1876 }
1877
1878 return qnum;
1879}
1880
1881int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1882{
1883 int qnum;
1884
1885 switch (queue) {
1886 case ATH9K_WME_AC_VO:
1887 qnum = 0;
1888 break;
1889 case ATH9K_WME_AC_VI:
1890 qnum = 1;
1891 break;
1892 case ATH9K_WME_AC_BE:
1893 qnum = 2;
1894 break;
1895 case ATH9K_WME_AC_BK:
1896 qnum = 3;
1897 break;
1898 default:
1899 qnum = -1;
1900 break;
1901 }
1902
1903 return qnum;
1904}
1905
5f8e077c
LR		 1906/* XXX: Remove me once we don't depend on ath9k_channel for all
1907 * this redundant data */
1908static void ath9k_update_ichannel(struct ath_softc *sc,
1909 struct ath9k_channel *ichan)
1910{
1911 struct ieee80211_hw *hw = sc->hw;
1912 struct ieee80211_channel *chan = hw->conf.channel;
1913 struct ieee80211_conf *conf = &hw->conf;
1914
1915 ichan->channel = chan->center_freq;
1916 ichan->chan = chan;
1917
1918 if (chan->band == IEEE80211_BAND_2GHZ) {
1919 ichan->chanmode = CHANNEL_G;
1920 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1921 } else {
1922 ichan->chanmode = CHANNEL_A;
1923 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1924 }
1925
1926 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1927
1928 if (conf_is_ht(conf)) {
1929 if (conf_is_ht40(conf))
1930 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1931
1932 ichan->chanmode = ath_get_extchanmode(sc, chan,
1933 conf->channel_type);
1934 }
1935}
1936
ff37e337
S		 1937/**********************/
1938/* mac80211 callbacks */
1939/**********************/
1940
8feceb67 1941static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR		 1942{
1943 struct ath_softc *sc = hw->priv;
8feceb67 1944 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1945 struct ath9k_channel *init_channel;
ae8d2858 1946 int r, pos;
f078f209 1947
04bd4638
S		 1948 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1949 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1950
141b38b6
S		 1951 mutex_lock(&sc->mutex);
1952
8feceb67 1953 /* setup initial channel */
f078f209 1954
5f8e077c 1955 pos = curchan->hw_value;
f078f209 1956
2660b81a 1957 init_channel = &sc->sc_ah->channels[pos];
5f8e077c 1958 ath9k_update_ichannel(sc, init_channel);
ff37e337
S		 1959
1960 /* Reset SERDES registers */
1961 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1962
1963 /*
1964 * The basic interface to setting the hardware in a good
1965 * state is ``reset''. On return the hardware is known to
1966 * be powered up and with interrupts disabled. This must
1967 * be followed by initialization of the appropriate bits
1968 * and then setup of the interrupt mask.
1969 */
1970 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1971 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1972 if (r) {
ff37e337 1973 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1974 "Unable to reset hardware; reset status %u "
1975 "(freq %u MHz)\n", r,
1976 curchan->center_freq);
ff37e337 1977 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1978 goto mutex_unlock;
ff37e337
S		 1979 }
1980 spin_unlock_bh(&sc->sc_resetlock);
1981
1982 /*
1983 * This is needed only to setup initial state
1984 * but it's best done after a reset.
1985 */
1986 ath_update_txpow(sc);
8feceb67 1987
ff37e337
S		 1988 /*
1989 * Setup the hardware after reset:
1990 * The receive engine is set going.
1991 * Frame transmit is handled entirely
1992 * in the frame output path; there's nothing to do
1993 * here except setup the interrupt mask.
1994 */
1995 if (ath_startrecv(sc) != 0) {
8feceb67 1996 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1997 "Unable to start recv logic\n");
141b38b6
S		 1998 r = -EIO;
1999 goto mutex_unlock;
f078f209 2000 }
8feceb67 2001
ff37e337 2002 /* Setup our intr mask. */
17d7904d 2003 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2004 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2005 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2006
2660b81a 2007 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2008 sc->imask |= ATH9K_INT_GTT;
ff37e337 2009
2660b81a 2010 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2011 sc->imask |= ATH9K_INT_CST;
ff37e337 2012
ce111bad 2013 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2014
2015 sc->sc_flags &= ~SC_OP_INVALID;
2016
2017 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 2018 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2019 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337
S		 2020
2021 ieee80211_wake_queues(sc->hw);
2022
e97275cb 2023#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 2024 r = ath_start_rfkill_poll(sc);
500c064d 2025#endif
141b38b6
S		 2026
2027mutex_unlock:
2028 mutex_unlock(&sc->mutex);
2029
ae8d2858 2030 return r;
f078f209
LR		 2031}
2032
8feceb67
VT		 2033static int ath9k_tx(struct ieee80211_hw *hw,
2034 struct sk_buff *skb)
f078f209 2035{
528f0c6b 2036 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 2037 struct ath_softc *sc = hw->priv;
528f0c6b 2038 struct ath_tx_control txctl;
8feceb67 2039 int hdrlen, padsize;
528f0c6b
S		 2040
2041 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2042
8feceb67
VT		 2043 /*
2044 * As a temporary workaround, assign seq# here; this will likely need
2045 * to be cleaned up to work better with Beacon transmission and virtual
2046 * BSSes.
2047 */
2048 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2049 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2050 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2051 sc->tx.seq_no += 0x10;
8feceb67 2052 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2053 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2054 }
f078f209 2055
8feceb67
VT		 2056 /* Add the padding after the header if this is not already done */
2057 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2058 if (hdrlen & 3) {
2059 padsize = hdrlen % 4;
2060 if (skb_headroom(skb) < padsize)
2061 return -1;
2062 skb_push(skb, padsize);
2063 memmove(skb->data, skb->data + padsize, hdrlen);
2064 }
2065
528f0c6b
S		 2066 /* Check if a tx queue is available */
2067
2068 txctl.txq = ath_test_get_txq(sc, skb);
2069 if (!txctl.txq)
2070 goto exit;
2071
04bd4638 2072 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2073
528f0c6b 2074 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 2075 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2076 goto exit;
8feceb67
VT		 2077 }
2078
528f0c6b
S		 2079 return 0;
2080exit:
2081 dev_kfree_skb_any(skb);
8feceb67 2082 return 0;
f078f209
LR		 2083}
2084
8feceb67 2085static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR		 2086{
2087 struct ath_softc *sc = hw->priv;
f078f209 2088
9c84b797 2089 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2090 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2091 return;
2092 }
8feceb67 2093
141b38b6 2094 mutex_lock(&sc->mutex);
ff37e337
S		 2095
2096 ieee80211_stop_queues(sc->hw);
2097
2098 /* make sure h/w will not generate any interrupt
2099 * before setting the invalid flag. */
2100 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2101
2102 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2103 ath_drain_all_txq(sc, false);
ff37e337
S		 2104 ath_stoprecv(sc);
2105 ath9k_hw_phy_disable(sc->sc_ah);
2106 } else
b77f483f 2107 sc->rx.rxlink = NULL;
ff37e337
S		 2108
2109#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a 2110 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
ff37e337
S		 2111 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2112#endif
2113 /* disable HAL and put h/w to sleep */
2114 ath9k_hw_disable(sc->sc_ah);
2115 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2116
2117 sc->sc_flags |= SC_OP_INVALID;
500c064d 2118
141b38b6
S		 2119 mutex_unlock(&sc->mutex);
2120
04bd4638 2121 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2122}
2123
8feceb67
VT		 2124static int ath9k_add_interface(struct ieee80211_hw *hw,
2125 struct ieee80211_if_init_conf *conf)
f078f209
LR		 2126{
2127 struct ath_softc *sc = hw->priv;
17d7904d 2128 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2129 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
f078f209 2130
17d7904d 2131 /* Support only vif for now */
8feceb67 2132
17d7904d 2133 if (sc->nvifs)
8feceb67
VT		 2134 return -ENOBUFS;
2135
141b38b6
S		 2136 mutex_lock(&sc->mutex);
2137
8feceb67 2138 switch (conf->type) {
05c914fe 2139 case NL80211_IFTYPE_STATION:
d97809db 2140 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2141 break;
05c914fe 2142 case NL80211_IFTYPE_ADHOC:
d97809db 2143 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2144 break;
05c914fe 2145 case NL80211_IFTYPE_AP:
d97809db 2146 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR		 2147 break;
2148 default:
2149 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2150 "Interface type %d not yet supported\n", conf->type);
222d0b33 2151 mutex_unlock(&sc->mutex);
8feceb67 2152 return -EOPNOTSUPP;
f078f209
LR		 2153 }
2154
17d7904d 2155 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2156
17d7904d 2157 /* Set the VIF opmode */
5640b08e
S		 2158 avp->av_opmode = ic_opmode;
2159 avp->av_bslot = -1;
2160
b238e90e 2161 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2162 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2163 sc->sc_flags |= SC_OP_TSF_RESET;
2164 }
5640b08e 2165
17d7904d
S		 2166 sc->vifs[0] = conf->vif;
2167 sc->nvifs++;
5640b08e
S		 2168
2169 /* Set the device opmode */
2660b81a 2170 sc->sc_ah->opmode = ic_opmode;
5640b08e 2171
4e30ffa2
VN		 2172 /*
2173 * Enable MIB interrupts when there are hardware phy counters.
2174 * Note we only do this (at the moment) for station mode.
2175 */
4af9cf4f
S		 2176 if ((conf->type == NL80211_IFTYPE_STATION) ||
2177 (conf->type == NL80211_IFTYPE_ADHOC)) {
2178 if (ath9k_hw_phycounters(sc->sc_ah))
2179 sc->imask |= ATH9K_INT_MIB;
2180 sc->imask |= ATH9K_INT_TSFOOR;
2181 }
2182
4e30ffa2
VN		 2183 /*
2184 * Some hardware processes the TIM IE and fires an
2185 * interrupt when the TIM bit is set. For hardware
2186 * that does, if not overridden by configuration,
2187 * enable the TIM interrupt when operating as station.
2188 */
2660b81a 2189 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
4e30ffa2 2190 (conf->type == NL80211_IFTYPE_STATION) &&
17d7904d
S		 2191 !sc->config.swBeaconProcess)
2192 sc->imask |= ATH9K_INT_TIM;
4e30ffa2 2193
17d7904d 2194 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2195
6f255425
LR		 2196 if (conf->type == NL80211_IFTYPE_AP) {
2197 /* TODO: is this a suitable place to start ANI for AP mode? */
2198 /* Start ANI */
17d7904d 2199 mod_timer(&sc->ani.timer,
6f255425
LR		 2200 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2201 }
2202
141b38b6
S		 2203 mutex_unlock(&sc->mutex);
2204
8feceb67 2205 return 0;
f078f209
LR		 2206}
2207
8feceb67
VT		 2208static void ath9k_remove_interface(struct ieee80211_hw *hw,
2209 struct ieee80211_if_init_conf *conf)
f078f209 2210{
8feceb67 2211 struct ath_softc *sc = hw->priv;
17d7904d 2212 struct ath_vif *avp = (void *)conf->vif->drv_priv;
f078f209 2213
04bd4638 2214 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2215
141b38b6
S		 2216 mutex_lock(&sc->mutex);
2217
6f255425 2218 /* Stop ANI */
17d7904d 2219 del_timer_sync(&sc->ani.timer);
580f0b8a 2220
8feceb67 2221 /* Reclaim beacon resources */
2660b81a
S		 2222 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
2223 sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2224 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2225 ath_beacon_return(sc, avp);
580f0b8a 2226 }
f078f209 2227
8feceb67 2228 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2229
17d7904d
S		 2230 sc->vifs[0] = NULL;
2231 sc->nvifs--;
141b38b6
S		 2232
2233 mutex_unlock(&sc->mutex);
f078f209
LR		 2234}
2235
e8975581 2236static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2237{
8feceb67 2238 struct ath_softc *sc = hw->priv;
e8975581 2239 struct ieee80211_conf *conf = &hw->conf;
f078f209 2240
aa33de09 2241 mutex_lock(&sc->mutex);
141b38b6 2242
3cbb5dd7
VN		 2243 if (changed & IEEE80211_CONF_CHANGE_PS) {
2244 if (conf->flags & IEEE80211_CONF_PS) {
17d7904d
S		 2245 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2246 sc->imask |= ATH9K_INT_TIM_TIMER;
3cbb5dd7 2247 ath9k_hw_set_interrupts(sc->sc_ah,
17d7904d 2248 sc->imask);
3cbb5dd7
VN		 2249 }
2250 ath9k_hw_setrxabort(sc->sc_ah, 1);
2251 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2252 } else {
2253 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2254 ath9k_hw_setrxabort(sc->sc_ah, 0);
2255 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
17d7904d
S		 2256 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2257 sc->imask &= ~ATH9K_INT_TIM_TIMER;
3cbb5dd7 2258 ath9k_hw_set_interrupts(sc->sc_ah,
17d7904d 2259 sc->imask);
3cbb5dd7
VN		 2260 }
2261 }
2262 }
2263
4797938c 2264 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2265 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2266 int pos = curchan->hw_value;
ae5eb026 2267
04bd4638
S		 2268 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2269 curchan->center_freq);
f078f209 2270
5f8e077c 2271 /* XXX: remove me eventualy */
2660b81a 2272 ath9k_update_ichannel(sc, &sc->sc_ah->channels[pos]);
e11602b7 2273
ecf70441 2274 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2275
2660b81a 2276 if (ath_set_channel(sc, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2277 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2278 mutex_unlock(&sc->mutex);
e11602b7
S		 2279 return -EINVAL;
2280 }
094d05dc 2281 }
f078f209 2282
5c020dc6 2283 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2284 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2285
b238e90e
S		 2286 /*
2287 * The HW TSF has to be reset when the beacon interval changes.
2288 * We set the flag here, and ath_beacon_config_ap() would take this
2289 * into account when it gets called through the subsequent
2290 * config_interface() call - with IFCC_BEACON in the changed field.
2291 */
2292
2293 if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2294 sc->sc_flags |= SC_OP_TSF_RESET;
2295
aa33de09 2296 mutex_unlock(&sc->mutex);
141b38b6 2297
f078f209
LR		 2298 return 0;
2299}
2300
8feceb67
VT		 2301static int ath9k_config_interface(struct ieee80211_hw *hw,
2302 struct ieee80211_vif *vif,
2303 struct ieee80211_if_conf *conf)
c83be688 2304{
8feceb67 2305 struct ath_softc *sc = hw->priv;
cbe61d8a 2306 struct ath_hw *ah = sc->sc_ah;
17d7904d 2307 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67
VT		 2308 u32 rfilt = 0;
2309 int error, i;
c83be688 2310
2554935b
S		 2311 mutex_lock(&sc->mutex);
2312
8feceb67
VT		 2313 /* TODO: Need to decide which hw opmode to use for multi-interface
2314 * cases */
05c914fe 2315 if (vif->type == NL80211_IFTYPE_AP &&
2660b81a
S		 2316 ah->opmode != NL80211_IFTYPE_AP) {
2317 ah->opmode = NL80211_IFTYPE_STATION;
8feceb67 2318 ath9k_hw_setopmode(ah);
ba52da58
S		 2319 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2320 sc->curaid = 0;
2321 ath9k_hw_write_associd(sc);
8feceb67
VT		 2322 /* Request full reset to get hw opmode changed properly */
2323 sc->sc_flags |= SC_OP_FULL_RESET;
2324 }
c83be688 2325
8feceb67
VT		 2326 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2327 !is_zero_ether_addr(conf->bssid)) {
2328 switch (vif->type) {
05c914fe
JB		 2329 case NL80211_IFTYPE_STATION:
2330 case NL80211_IFTYPE_ADHOC:
8feceb67 2331 /* Set BSSID */
17d7904d
S		 2332 memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2333 sc->curaid = 0;
ba52da58 2334 ath9k_hw_write_associd(sc);
c83be688 2335
8feceb67 2336 /* Set aggregation protection mode parameters */
17d7904d 2337 sc->config.ath_aggr_prot = 0;
c83be688 2338
8feceb67 2339 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2340 "RX filter 0x%x bssid %pM aid 0x%x\n",
17d7904d 2341 rfilt, sc->curbssid, sc->curaid);
c83be688 2342
8feceb67
VT		 2343 /* need to reconfigure the beacon */
2344 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2345
8feceb67
VT		 2346 break;
2347 default:
2348 break;
2349 }
2350 }
c83be688 2351
1f7d6cbf
S		 2352 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2353 (vif->type == NL80211_IFTYPE_AP)) {
2354 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2355 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2356 conf->enable_beacon)) {
2357 /*
2358 * Allocate and setup the beacon frame.
2359 *
2360 * Stop any previous beacon DMA. This may be
2361 * necessary, for example, when an ibss merge
2362 * causes reconfiguration; we may be called
2363 * with beacon transmission active.
2364 */
2365 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2366
1f7d6cbf 2367 error = ath_beacon_alloc(sc, 0);
2554935b
S		 2368 if (error != 0) {
2369 mutex_unlock(&sc->mutex);
1f7d6cbf 2370 return error;
2554935b 2371 }
c83be688 2372
5379c8a2 2373 ath_beacon_config(sc, 0);
1f7d6cbf 2374 }
8feceb67 2375 }
c83be688 2376
8feceb67 2377 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2378 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2379 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2380 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2381 ath9k_hw_keysetmac(sc->sc_ah,
2382 (u16)i,
17d7904d 2383 sc->curbssid);
8feceb67 2384 }
c83be688 2385
8feceb67 2386 /* Only legacy IBSS for now */
05c914fe 2387 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2388 ath_update_chainmask(sc, 0);
f078f209 2389
2554935b
S		 2390 mutex_unlock(&sc->mutex);
2391
8feceb67
VT		 2392 return 0;
2393}
f078f209 2394
8feceb67
VT		 2395#define SUPPORTED_FILTERS \
2396 (FIF_PROMISC_IN_BSS | \
2397 FIF_ALLMULTI | \
2398 FIF_CONTROL | \
2399 FIF_OTHER_BSS | \
2400 FIF_BCN_PRBRESP_PROMISC | \
2401 FIF_FCSFAIL)
c83be688 2402
8feceb67
VT		 2403/* FIXME: sc->sc_full_reset ? */
2404static void ath9k_configure_filter(struct ieee80211_hw *hw,
2405 unsigned int changed_flags,
2406 unsigned int *total_flags,
2407 int mc_count,
2408 struct dev_mc_list *mclist)
2409{
2410 struct ath_softc *sc = hw->priv;
2411 u32 rfilt;
f078f209 2412
8feceb67
VT		 2413 changed_flags &= SUPPORTED_FILTERS;
2414 *total_flags &= SUPPORTED_FILTERS;
f078f209 2415
b77f483f 2416 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2417 rfilt = ath_calcrxfilter(sc);
2418 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2419
b77f483f 2420 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2421}
f078f209 2422
8feceb67
VT		 2423static void ath9k_sta_notify(struct ieee80211_hw *hw,
2424 struct ieee80211_vif *vif,
2425 enum sta_notify_cmd cmd,
17741cdc 2426 struct ieee80211_sta *sta)
8feceb67
VT		 2427{
2428 struct ath_softc *sc = hw->priv;
f078f209 2429
8feceb67
VT		 2430 switch (cmd) {
2431 case STA_NOTIFY_ADD:
5640b08e 2432 ath_node_attach(sc, sta);
8feceb67
VT		 2433 break;
2434 case STA_NOTIFY_REMOVE:
b5aa9bf9 2435 ath_node_detach(sc, sta);
8feceb67
VT		 2436 break;
2437 default:
2438 break;
2439 }
f078f209
LR		 2440}
2441
141b38b6 2442static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2443 const struct ieee80211_tx_queue_params *params)
f078f209 2444{
8feceb67
VT		 2445 struct ath_softc *sc = hw->priv;
2446 struct ath9k_tx_queue_info qi;
2447 int ret = 0, qnum;
f078f209 2448
8feceb67
VT		 2449 if (queue >= WME_NUM_AC)
2450 return 0;
f078f209 2451
141b38b6
S		 2452 mutex_lock(&sc->mutex);
2453
8feceb67
VT		 2454 qi.tqi_aifs = params->aifs;
2455 qi.tqi_cwmin = params->cw_min;
2456 qi.tqi_cwmax = params->cw_max;
2457 qi.tqi_burstTime = params->txop;
2458 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2459
8feceb67 2460 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2461 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2462 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2463 queue, qnum, params->aifs, params->cw_min,
2464 params->cw_max, params->txop);
f078f209 2465
8feceb67
VT		 2466 ret = ath_txq_update(sc, qnum, &qi);
2467 if (ret)
04bd4638 2468 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2469
141b38b6
S		 2470 mutex_unlock(&sc->mutex);
2471
8feceb67
VT		 2472 return ret;
2473}
f078f209 2474
8feceb67
VT		 2475static int ath9k_set_key(struct ieee80211_hw *hw,
2476 enum set_key_cmd cmd,
dc822b5d
JB		 2477 struct ieee80211_vif *vif,
2478 struct ieee80211_sta *sta,
8feceb67
VT		 2479 struct ieee80211_key_conf *key)
2480{
2481 struct ath_softc *sc = hw->priv;
2482 int ret = 0;
f078f209 2483
b3bd89ce
JM		 2484 if (modparam_nohwcrypt)
2485 return -ENOSPC;
2486
141b38b6 2487 mutex_lock(&sc->mutex);
3cbb5dd7 2488 ath9k_ps_wakeup(sc);
04bd4638 2489 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2490
8feceb67
VT		 2491 switch (cmd) {
2492 case SET_KEY:
3f53dd64 2493 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2494 if (ret >= 0) {
2495 key->hw_key_idx = ret;
8feceb67
VT		 2496 /* push IV and Michael MIC generation to stack */
2497 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2498 if (key->alg == ALG_TKIP)
2499 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2500 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2501 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2502 ret = 0;
8feceb67
VT		 2503 }
2504 break;
2505 case DISABLE_KEY:
2506 ath_key_delete(sc, key);
8feceb67
VT		 2507 break;
2508 default:
2509 ret = -EINVAL;
2510 }
f078f209 2511
3cbb5dd7 2512 ath9k_ps_restore(sc);
141b38b6
S		 2513 mutex_unlock(&sc->mutex);
2514
8feceb67
VT		 2515 return ret;
2516}
f078f209 2517
8feceb67
VT		 2518static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2519 struct ieee80211_vif *vif,
2520 struct ieee80211_bss_conf *bss_conf,
2521 u32 changed)
2522{
2523 struct ath_softc *sc = hw->priv;
f078f209 2524
141b38b6
S		 2525 mutex_lock(&sc->mutex);
2526
8feceb67 2527 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2528 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2529 bss_conf->use_short_preamble);
2530 if (bss_conf->use_short_preamble)
2531 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2532 else
2533 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2534 }
f078f209 2535
8feceb67 2536 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2537 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2538 bss_conf->use_cts_prot);
2539 if (bss_conf->use_cts_prot &&
2540 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2541 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2542 else
2543 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2544 }
f078f209 2545
8feceb67 2546 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2547 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2548 bss_conf->assoc);
5640b08e 2549 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2550 }
141b38b6
S		 2551
2552 mutex_unlock(&sc->mutex);
8feceb67 2553}
f078f209 2554
8feceb67
VT		 2555static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2556{
2557 u64 tsf;
2558 struct ath_softc *sc = hw->priv;
f078f209 2559
141b38b6
S		 2560 mutex_lock(&sc->mutex);
2561 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2562 mutex_unlock(&sc->mutex);
f078f209 2563
8feceb67
VT		 2564 return tsf;
2565}
f078f209 2566
3b5d665b
AF		 2567static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2568{
2569 struct ath_softc *sc = hw->priv;
3b5d665b 2570
141b38b6
S		 2571 mutex_lock(&sc->mutex);
2572 ath9k_hw_settsf64(sc->sc_ah, tsf);
2573 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2574}
2575
8feceb67
VT		 2576static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2577{
2578 struct ath_softc *sc = hw->priv;
c83be688 2579
141b38b6
S		 2580 mutex_lock(&sc->mutex);
2581 ath9k_hw_reset_tsf(sc->sc_ah);
2582 mutex_unlock(&sc->mutex);
8feceb67 2583}
f078f209 2584
8feceb67 2585static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2586 enum ieee80211_ampdu_mlme_action action,
2587 struct ieee80211_sta *sta,
2588 u16 tid, u16 *ssn)
8feceb67
VT		 2589{
2590 struct ath_softc *sc = hw->priv;
2591 int ret = 0;
f078f209 2592
8feceb67
VT		 2593 switch (action) {
2594 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2595 if (!(sc->sc_flags & SC_OP_RXAGGR))
2596 ret = -ENOTSUPP;
8feceb67
VT		 2597 break;
2598 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2599 break;
2600 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2601 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2602 if (ret < 0)
2603 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2604 "Unable to start TX aggregation\n");
8feceb67 2605 else
17741cdc 2606 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2607 break;
2608 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2609 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2610 if (ret < 0)
2611 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2612 "Unable to stop TX aggregation\n");
f078f209 2613
17741cdc 2614 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2615 break;
8469cdef
S		 2616 case IEEE80211_AMPDU_TX_RESUME:
2617 ath_tx_aggr_resume(sc, sta, tid);
2618 break;
8feceb67 2619 default:
04bd4638 2620 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2621 }
2622
2623 return ret;
f078f209
LR		 2624}
2625
0c98de65
S		 2626static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2627{
2628 struct ath_softc *sc = hw->priv;
2629
2630 mutex_lock(&sc->mutex);
2631 sc->sc_flags |= SC_OP_SCANNING;
2632 mutex_unlock(&sc->mutex);
2633}
2634
2635static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2636{
2637 struct ath_softc *sc = hw->priv;
2638
2639 mutex_lock(&sc->mutex);
2640 sc->sc_flags &= ~SC_OP_SCANNING;
2641 mutex_unlock(&sc->mutex);
2642}
2643
6baff7f9 2644struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2645 .tx = ath9k_tx,
2646 .start = ath9k_start,
2647 .stop = ath9k_stop,
2648 .add_interface = ath9k_add_interface,
2649 .remove_interface = ath9k_remove_interface,
2650 .config = ath9k_config,
2651 .config_interface = ath9k_config_interface,
2652 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2653 .sta_notify = ath9k_sta_notify,
2654 .conf_tx = ath9k_conf_tx,
8feceb67 2655 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2656 .set_key = ath9k_set_key,
8feceb67 2657 .get_tsf = ath9k_get_tsf,
3b5d665b 2658 .set_tsf = ath9k_set_tsf,
8feceb67 2659 .reset_tsf = ath9k_reset_tsf,
4233df6b 2660 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2661 .sw_scan_start = ath9k_sw_scan_start,
2662 .sw_scan_complete = ath9k_sw_scan_complete,
8feceb67
VT		 2663};
2664
392dff83
BP		 2665static struct {
2666 u32 version;
2667 const char * name;
2668} ath_mac_bb_names[] = {
2669 { AR_SREV_VERSION_5416_PCI, "5416" },
2670 { AR_SREV_VERSION_5416_PCIE, "5418" },
2671 { AR_SREV_VERSION_9100, "9100" },
2672 { AR_SREV_VERSION_9160, "9160" },
2673 { AR_SREV_VERSION_9280, "9280" },
2674 { AR_SREV_VERSION_9285, "9285" }
2675};
2676
2677static struct {
2678 u16 version;
2679 const char * name;
2680} ath_rf_names[] = {
2681 { 0, "5133" },
2682 { AR_RAD5133_SREV_MAJOR, "5133" },
2683 { AR_RAD5122_SREV_MAJOR, "5122" },
2684 { AR_RAD2133_SREV_MAJOR, "2133" },
2685 { AR_RAD2122_SREV_MAJOR, "2122" }
2686};
2687
2688/*
2689 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2690 */
6baff7f9 2691const char *
392dff83
BP		 2692ath_mac_bb_name(u32 mac_bb_version)
2693{
2694 int i;
2695
2696 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2697 if (ath_mac_bb_names[i].version == mac_bb_version) {
2698 return ath_mac_bb_names[i].name;
2699 }
2700 }
2701
2702 return "????";
2703}
2704
2705/*
2706 * Return the RF name. "????" is returned if the RF is unknown.
2707 */
6baff7f9 2708const char *
392dff83
BP		 2709ath_rf_name(u16 rf_version)
2710{
2711 int i;
2712
2713 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2714 if (ath_rf_names[i].version == rf_version) {
2715 return ath_rf_names[i].name;
2716 }
2717 }
2718
2719 return "????";
2720}
2721
6baff7f9 2722static int __init ath9k_init(void)
f078f209 2723{
ca8a8560
VT		 2724 int error;
2725
ca8a8560
VT		 2726 /* Register rate control algorithm */
2727 error = ath_rate_control_register();
2728 if (error != 0) {
2729 printk(KERN_ERR
b51bb3cd
LR		 2730 "ath9k: Unable to register rate control "
2731 "algorithm: %d\n",
ca8a8560 2732 error);
6baff7f9 2733 goto err_out;
ca8a8560
VT		 2734 }
2735
6baff7f9
GJ		 2736 error = ath_pci_init();
2737 if (error < 0) {
f078f209 2738 printk(KERN_ERR
b51bb3cd 2739 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9
GJ		 2740 error = -ENODEV;
2741 goto err_rate_unregister;
f078f209
LR		 2742 }
2743
09329d37
GJ		 2744 error = ath_ahb_init();
2745 if (error < 0) {
2746 error = -ENODEV;
2747 goto err_pci_exit;
2748 }
2749
f078f209 2750 return 0;
6baff7f9 2751
09329d37
GJ		 2752 err_pci_exit:
2753 ath_pci_exit();
2754
6baff7f9
GJ		 2755 err_rate_unregister:
2756 ath_rate_control_unregister();
2757 err_out:
2758 return error;
f078f209 2759}
6baff7f9 2760module_init(ath9k_init);
f078f209 2761
6baff7f9 2762static void __exit ath9k_exit(void)
f078f209 2763{
09329d37 2764 ath_ahb_exit();
6baff7f9 2765 ath_pci_exit();
ca8a8560 2766 ath_rate_control_unregister();
04bd4638 2767 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2768}
6baff7f9 2769module_exit(ath9k_exit);
Linux kernel - Deliverables
This page took 0.305814 seconds and 5 git commands to generate.