802.11: clean up/fix HT support
[deliverable/linux.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
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1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/* mac80211 and PCI callbacks */
18
19#include <linux/nl80211.h>
20#include "core.h"
21
22#define ATH_PCI_VERSION "0.1"
23
24#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
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25
26static char *dev_info = "ath9k";
27
28MODULE_AUTHOR("Atheros Communications");
29MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31MODULE_LICENSE("Dual BSD/GPL");
32
33static struct pci_device_id ath_pci_id_table[] __devinitdata = {
34 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
35 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
36 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
37 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
38 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
39 { 0 }
40};
41
42static int ath_get_channel(struct ath_softc *sc,
43 struct ieee80211_channel *chan)
44{
45 int i;
46
47 for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
48 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
49 return i;
50 }
51
52 return -1;
53}
54
55static u32 ath_get_extchanmode(struct ath_softc *sc,
56 struct ieee80211_channel *chan)
57{
58 u32 chanmode = 0;
59 u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset;
60 enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width;
61
62 switch (chan->band) {
63 case IEEE80211_BAND_2GHZ:
d9fe60de 64 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
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65 (tx_chan_width == ATH9K_HT_MACMODE_20))
66 chanmode = CHANNEL_G_HT20;
d9fe60de 67 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
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68 (tx_chan_width == ATH9K_HT_MACMODE_2040))
69 chanmode = CHANNEL_G_HT40PLUS;
d9fe60de 70 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
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71 (tx_chan_width == ATH9K_HT_MACMODE_2040))
72 chanmode = CHANNEL_G_HT40MINUS;
73 break;
74 case IEEE80211_BAND_5GHZ:
d9fe60de 75 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
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76 (tx_chan_width == ATH9K_HT_MACMODE_20))
77 chanmode = CHANNEL_A_HT20;
d9fe60de 78 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
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79 (tx_chan_width == ATH9K_HT_MACMODE_2040))
80 chanmode = CHANNEL_A_HT40PLUS;
d9fe60de 81 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
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82 (tx_chan_width == ATH9K_HT_MACMODE_2040))
83 chanmode = CHANNEL_A_HT40MINUS;
84 break;
85 default:
86 break;
87 }
88
89 return chanmode;
90}
91
92
93static int ath_setkey_tkip(struct ath_softc *sc,
94 struct ieee80211_key_conf *key,
95 struct ath9k_keyval *hk,
96 const u8 *addr)
97{
98 u8 *key_rxmic = NULL;
99 u8 *key_txmic = NULL;
100
101 key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
102 key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
103
104 if (addr == NULL) {
105 /* Group key installation */
106 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
107 return ath_keyset(sc, key->keyidx, hk, addr);
108 }
109 if (!sc->sc_splitmic) {
110 /*
111 * data key goes at first index,
112 * the hal handles the MIC keys at index+64.
113 */
114 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
115 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
116 return ath_keyset(sc, key->keyidx, hk, addr);
117 }
118 /*
119 * TX key goes at first index, RX key at +32.
120 * The hal handles the MIC keys at index+64.
121 */
122 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
123 if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
124 /* Txmic entry failed. No need to proceed further */
125 DPRINTF(sc, ATH_DBG_KEYCACHE,
126 "%s Setting TX MIC Key Failed\n", __func__);
127 return 0;
128 }
129
130 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
131 /* XXX delete tx key on failure? */
132 return ath_keyset(sc, key->keyidx+32, hk, addr);
133}
134
135static int ath_key_config(struct ath_softc *sc,
136 const u8 *addr,
137 struct ieee80211_key_conf *key)
138{
139 struct ieee80211_vif *vif;
140 struct ath9k_keyval hk;
141 const u8 *mac = NULL;
142 int ret = 0;
05c914fe 143 enum nl80211_iftype opmode;
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144
145 memset(&hk, 0, sizeof(hk));
146
147 switch (key->alg) {
148 case ALG_WEP:
149 hk.kv_type = ATH9K_CIPHER_WEP;
150 break;
151 case ALG_TKIP:
152 hk.kv_type = ATH9K_CIPHER_TKIP;
153 break;
154 case ALG_CCMP:
155 hk.kv_type = ATH9K_CIPHER_AES_CCM;
156 break;
157 default:
158 return -EINVAL;
159 }
160
161 hk.kv_len = key->keylen;
162 memcpy(hk.kv_val, key->key, key->keylen);
163
164 if (!sc->sc_vaps[0])
165 return -EIO;
166
167 vif = sc->sc_vaps[0]->av_if_data;
168 opmode = vif->type;
169
170 /*
171 * Strategy:
172 * For _M_STA mc tx, we will not setup a key at all since we never
173 * tx mc.
174 * _M_STA mc rx, we will use the keyID.
175 * for _M_IBSS mc tx, we will use the keyID, and no macaddr.
176 * for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
177 * peer node. BUT we will plumb a cleartext key so that we can do
178 * perSta default key table lookup in software.
179 */
180 if (is_broadcast_ether_addr(addr)) {
181 switch (opmode) {
05c914fe 182 case NL80211_IFTYPE_STATION:
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183 /* default key: could be group WPA key
184 * or could be static WEP key */
185 mac = NULL;
186 break;
05c914fe 187 case NL80211_IFTYPE_ADHOC:
f078f209 188 break;
05c914fe 189 case NL80211_IFTYPE_AP:
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190 break;
191 default:
192 ASSERT(0);
193 break;
194 }
195 } else {
196 mac = addr;
197 }
198
199 if (key->alg == ALG_TKIP)
200 ret = ath_setkey_tkip(sc, key, &hk, mac);
201 else
202 ret = ath_keyset(sc, key->keyidx, &hk, mac);
203
204 if (!ret)
205 return -EIO;
206
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207 return 0;
208}
209
210static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
211{
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212 int freeslot;
213
ff9b662d 214 freeslot = (key->keyidx >= 4) ? 1 : 0;
f078f209 215 ath_key_reset(sc, key->keyidx, freeslot);
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216}
217
d9fe60de 218static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
f078f209 219{
60653678
S
220#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
221#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 222
d9fe60de
JB
223 ht_info->ht_supported = true;
224 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
225 IEEE80211_HT_CAP_SM_PS |
226 IEEE80211_HT_CAP_SGI_40 |
227 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 228
60653678
S
229 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
230 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
d9fe60de
JB
231 /* set up supported mcs set */
232 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
233 ht_info->mcs.rx_mask[0] = 0xff;
234 ht_info->mcs.rx_mask[1] = 0xff;
235 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
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236}
237
238static int ath_rate2idx(struct ath_softc *sc, int rate)
239{
240 int i = 0, cur_band, n_rates;
241 struct ieee80211_hw *hw = sc->hw;
242
243 cur_band = hw->conf.channel->band;
244 n_rates = sc->sbands[cur_band].n_bitrates;
245
246 for (i = 0; i < n_rates; i++) {
247 if (sc->sbands[cur_band].bitrates[i].bitrate == rate)
248 break;
249 }
250
251 /*
252 * NB:mac80211 validates rx rate index against the supported legacy rate
253 * index only (should be done against ht rates also), return the highest
254 * legacy rate index for rx rate which does not match any one of the
255 * supported basic and extended rates to make mac80211 happy.
256 * The following hack will be cleaned up once the issue with
257 * the rx rate index validation in mac80211 is fixed.
258 */
259 if (i == n_rates)
260 return n_rates - 1;
261 return i;
262}
263
264static void ath9k_rx_prepare(struct ath_softc *sc,
265 struct sk_buff *skb,
266 struct ath_recv_status *status,
267 struct ieee80211_rx_status *rx_status)
268{
269 struct ieee80211_hw *hw = sc->hw;
270 struct ieee80211_channel *curchan = hw->conf.channel;
271
272 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
273
274 rx_status->mactime = status->tsf;
275 rx_status->band = curchan->band;
276 rx_status->freq = curchan->center_freq;
6f255425 277 rx_status->noise = sc->sc_ani.sc_noise_floor;
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278 rx_status->signal = rx_status->noise + status->rssi;
279 rx_status->rate_idx = ath_rate2idx(sc, (status->rateKbps / 100));
280 rx_status->antenna = status->antenna;
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281
282 /* XXX Fix me, 64 cannot be the max rssi value, rigure it out */
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283 rx_status->qual = status->rssi * 100 / 64;
284
285 if (status->flags & ATH_RX_MIC_ERROR)
286 rx_status->flag |= RX_FLAG_MMIC_ERROR;
287 if (status->flags & ATH_RX_FCS_ERROR)
288 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
289
290 rx_status->flag |= RX_FLAG_TSFT;
291}
292
293static u8 parse_mpdudensity(u8 mpdudensity)
294{
295 /*
296 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
297 * 0 for no restriction
298 * 1 for 1/4 us
299 * 2 for 1/2 us
300 * 3 for 1 us
301 * 4 for 2 us
302 * 5 for 4 us
303 * 6 for 8 us
304 * 7 for 16 us
305 */
306 switch (mpdudensity) {
307 case 0:
308 return 0;
309 case 1:
310 case 2:
311 case 3:
312 /* Our lower layer calculations limit our precision to
313 1 microsecond */
314 return 1;
315 case 4:
316 return 2;
317 case 5:
318 return 4;
319 case 6:
320 return 8;
321 case 7:
322 return 16;
323 default:
324 return 0;
325 }
326}
327
8feceb67
VT
328static void ath9k_ht_conf(struct ath_softc *sc,
329 struct ieee80211_bss_conf *bss_conf)
f078f209 330{
8feceb67 331 struct ath_ht_info *ht_info = &sc->sc_ht_info;
f078f209 332
8feceb67
VT
333 if (bss_conf->assoc_ht) {
334 ht_info->ext_chan_offset =
335 bss_conf->ht_bss_conf->bss_cap &
d9fe60de 336 IEEE80211_HT_PARAM_CHA_SEC_OFFSET;
f078f209 337
d9fe60de 338 if (!(bss_conf->ht_cap->cap &
8feceb67
VT
339 IEEE80211_HT_CAP_40MHZ_INTOLERANT) &&
340 (bss_conf->ht_bss_conf->bss_cap &
d9fe60de 341 IEEE80211_HT_PARAM_CHAN_WIDTH_ANY))
8feceb67
VT
342 ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040;
343 else
344 ht_info->tx_chan_width = ATH9K_HT_MACMODE_20;
f078f209 345
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VT
346 ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
347 ht_info->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
d9fe60de 348 bss_conf->ht_cap->ampdu_factor);
8feceb67 349 ht_info->mpdudensity =
d9fe60de 350 parse_mpdudensity(bss_conf->ht_cap->ampdu_density);
f078f209 351
f078f209 352 }
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353}
354
8feceb67
VT
355static void ath9k_bss_assoc_info(struct ath_softc *sc,
356 struct ieee80211_bss_conf *bss_conf)
f078f209 357{
8feceb67
VT
358 struct ieee80211_hw *hw = sc->hw;
359 struct ieee80211_channel *curchan = hw->conf.channel;
360 struct ath_vap *avp;
361 int pos;
f078f209 362
8feceb67
VT
363 if (bss_conf->assoc) {
364 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
365 __func__,
366 bss_conf->aid);
f078f209 367
8feceb67
VT
368 avp = sc->sc_vaps[0];
369 if (avp == NULL) {
370 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
371 __func__);
372 return;
373 }
f078f209 374
8feceb67
VT
375 /* New association, store aid */
376 if (avp->av_opmode == ATH9K_M_STA) {
377 sc->sc_curaid = bss_conf->aid;
378 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
379 sc->sc_curaid);
380 }
f078f209 381
8feceb67
VT
382 /* Configure the beacon */
383 ath_beacon_config(sc, 0);
384 sc->sc_flags |= SC_OP_BEACONS;
f078f209 385
8feceb67
VT
386 /* Reset rssi stats */
387 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
388 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
389 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
390 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 391
8feceb67
VT
392 /* Update chainmask */
393 ath_update_chainmask(sc, bss_conf->assoc_ht);
f078f209 394
f078f209 395 DPRINTF(sc, ATH_DBG_CONFIG,
e174961c 396 "%s: bssid %pM aid 0x%x\n",
8feceb67 397 __func__,
e174961c 398 sc->sc_curbssid, sc->sc_curaid);
f078f209 399
8feceb67
VT
400 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
401 __func__,
402 curchan->center_freq);
f078f209 403
8feceb67
VT
404 pos = ath_get_channel(sc, curchan);
405 if (pos == -1) {
406 DPRINTF(sc, ATH_DBG_FATAL,
407 "%s: Invalid channel\n", __func__);
408 return;
409 }
f078f209 410
d9fe60de 411 if (hw->conf.ht_cap.ht_supported)
8feceb67
VT
412 sc->sc_ah->ah_channels[pos].chanmode =
413 ath_get_extchanmode(sc, curchan);
414 else
415 sc->sc_ah->ah_channels[pos].chanmode =
416 (curchan->band == IEEE80211_BAND_2GHZ) ?
417 CHANNEL_G : CHANNEL_A;
f078f209 418
8feceb67
VT
419 /* set h/w channel */
420 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
421 DPRINTF(sc, ATH_DBG_FATAL,
422 "%s: Unable to set channel\n",
423 __func__);
f078f209 424
8feceb67
VT
425 ath_rate_newstate(sc, avp);
426 /* Update ratectrl about the new state */
427 ath_rc_node_update(hw, avp->rc_node);
6f255425
LR
428
429 /* Start ANI */
430 mod_timer(&sc->sc_ani.timer,
431 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
432
8feceb67
VT
433 } else {
434 DPRINTF(sc, ATH_DBG_CONFIG,
435 "%s: Bss Info DISSOC\n", __func__);
436 sc->sc_curaid = 0;
f078f209 437 }
8feceb67 438}
f078f209 439
8feceb67
VT
440void ath_get_beaconconfig(struct ath_softc *sc,
441 int if_id,
442 struct ath_beacon_config *conf)
443{
444 struct ieee80211_hw *hw = sc->hw;
f078f209 445
8feceb67 446 /* fill in beacon config data */
f078f209 447
8feceb67
VT
448 conf->beacon_interval = hw->conf.beacon_int;
449 conf->listen_interval = 100;
450 conf->dtim_count = 1;
451 conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
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LR
452}
453
8feceb67
VT
454void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
455 struct ath_xmit_status *tx_status, struct ath_node *an)
f078f209 456{
8feceb67
VT
457 struct ieee80211_hw *hw = sc->hw;
458 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
f078f209 459
8feceb67
VT
460 DPRINTF(sc, ATH_DBG_XMIT,
461 "%s: TX complete: skb: %p\n", __func__, skb);
f078f209 462
8feceb67
VT
463 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
464 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
465 /* free driver's private data area of tx_info */
466 if (tx_info->driver_data[0] != NULL)
467 kfree(tx_info->driver_data[0]);
468 tx_info->driver_data[0] = NULL;
f078f209
LR
469 }
470
8feceb67
VT
471 if (tx_status->flags & ATH_TX_BAR) {
472 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
473 tx_status->flags &= ~ATH_TX_BAR;
474 }
f078f209 475
8feceb67
VT
476 if (tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY)) {
477 if (!(tx_info->flags & IEEE80211_TX_CTL_NO_ACK)) {
478 /* Frame was not ACKed, but an ACK was expected */
479 tx_info->status.excessive_retries = 1;
480 }
481 } else {
482 /* Frame was ACKed */
483 tx_info->flags |= IEEE80211_TX_STAT_ACK;
f078f209
LR
484 }
485
8feceb67 486 tx_info->status.retry_count = tx_status->retries;
f078f209 487
8feceb67
VT
488 ieee80211_tx_status(hw, skb);
489 if (an)
490 ath_node_put(sc, an, ATH9K_BH_STATUS_CHANGE);
f078f209
LR
491}
492
8feceb67
VT
493int _ath_rx_indicate(struct ath_softc *sc,
494 struct sk_buff *skb,
495 struct ath_recv_status *status,
496 u16 keyix)
f078f209 497{
8feceb67
VT
498 struct ieee80211_hw *hw = sc->hw;
499 struct ath_node *an = NULL;
500 struct ieee80211_rx_status rx_status;
501 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
502 int hdrlen = ieee80211_get_hdrlen_from_skb(skb);
503 int padsize;
504 enum ATH_RX_TYPE st;
f078f209 505
8feceb67
VT
506 /* see if any padding is done by the hw and remove it */
507 if (hdrlen & 3) {
508 padsize = hdrlen % 4;
509 memmove(skb->data + padsize, skb->data, hdrlen);
510 skb_pull(skb, padsize);
f078f209
LR
511 }
512
8feceb67
VT
513 /* Prepare rx status */
514 ath9k_rx_prepare(sc, skb, status, &rx_status);
86b89eed 515
8feceb67
VT
516 if (!(keyix == ATH9K_RXKEYIX_INVALID) &&
517 !(status->flags & ATH_RX_DECRYPT_ERROR)) {
518 rx_status.flag |= RX_FLAG_DECRYPTED;
519 } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED)
520 && !(status->flags & ATH_RX_DECRYPT_ERROR)
521 && skb->len >= hdrlen + 4) {
522 keyix = skb->data[hdrlen + 3] >> 6;
86b89eed 523
8feceb67
VT
524 if (test_bit(keyix, sc->sc_keymap))
525 rx_status.flag |= RX_FLAG_DECRYPTED;
526 }
f078f209 527
8feceb67
VT
528 spin_lock_bh(&sc->node_lock);
529 an = ath_node_find(sc, hdr->addr2);
530 spin_unlock_bh(&sc->node_lock);
531
532 if (an) {
533 ath_rx_input(sc, an,
d9fe60de 534 hw->conf.ht_cap.ht_supported,
8feceb67
VT
535 skb, status, &st);
536 }
537 if (!an || (st != ATH_RX_CONSUMED))
538 __ieee80211_rx(hw, skb, &rx_status);
f078f209
LR
539
540 return 0;
541}
542
8feceb67
VT
543int ath_rx_subframe(struct ath_node *an,
544 struct sk_buff *skb,
545 struct ath_recv_status *status)
f078f209 546{
8feceb67
VT
547 struct ath_softc *sc = an->an_sc;
548 struct ieee80211_hw *hw = sc->hw;
549 struct ieee80211_rx_status rx_status;
f078f209 550
8feceb67
VT
551 /* Prepare rx status */
552 ath9k_rx_prepare(sc, skb, status, &rx_status);
553 if (!(status->flags & ATH_RX_DECRYPT_ERROR))
554 rx_status.flag |= RX_FLAG_DECRYPTED;
f078f209 555
8feceb67 556 __ieee80211_rx(hw, skb, &rx_status);
f078f209 557
8feceb67
VT
558 return 0;
559}
f078f209 560
8feceb67
VT
561/********************************/
562/* LED functions */
563/********************************/
f078f209 564
8feceb67
VT
565static void ath_led_brightness(struct led_classdev *led_cdev,
566 enum led_brightness brightness)
567{
568 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
569 struct ath_softc *sc = led->sc;
f078f209 570
8feceb67
VT
571 switch (brightness) {
572 case LED_OFF:
573 if (led->led_type == ATH_LED_ASSOC ||
574 led->led_type == ATH_LED_RADIO)
575 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
576 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
577 (led->led_type == ATH_LED_RADIO) ? 1 :
578 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
579 break;
580 case LED_FULL:
581 if (led->led_type == ATH_LED_ASSOC)
582 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
583 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
584 break;
585 default:
586 break;
f078f209 587 }
8feceb67 588}
f078f209 589
8feceb67
VT
590static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
591 char *trigger)
592{
593 int ret;
f078f209 594
8feceb67
VT
595 led->sc = sc;
596 led->led_cdev.name = led->name;
597 led->led_cdev.default_trigger = trigger;
598 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 599
8feceb67
VT
600 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
601 if (ret)
602 DPRINTF(sc, ATH_DBG_FATAL,
603 "Failed to register led:%s", led->name);
604 else
605 led->registered = 1;
606 return ret;
607}
f078f209 608
8feceb67
VT
609static void ath_unregister_led(struct ath_led *led)
610{
611 if (led->registered) {
612 led_classdev_unregister(&led->led_cdev);
613 led->registered = 0;
f078f209 614 }
f078f209
LR
615}
616
8feceb67 617static void ath_deinit_leds(struct ath_softc *sc)
f078f209 618{
8feceb67
VT
619 ath_unregister_led(&sc->assoc_led);
620 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
621 ath_unregister_led(&sc->tx_led);
622 ath_unregister_led(&sc->rx_led);
623 ath_unregister_led(&sc->radio_led);
624 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
625}
f078f209 626
8feceb67
VT
627static void ath_init_leds(struct ath_softc *sc)
628{
629 char *trigger;
630 int ret;
f078f209 631
8feceb67
VT
632 /* Configure gpio 1 for output */
633 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
634 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
635 /* LED off, active low */
636 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 637
8feceb67
VT
638 trigger = ieee80211_get_radio_led_name(sc->hw);
639 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
640 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
641 ret = ath_register_led(sc, &sc->radio_led, trigger);
642 sc->radio_led.led_type = ATH_LED_RADIO;
643 if (ret)
644 goto fail;
7dcfdcd9 645
8feceb67
VT
646 trigger = ieee80211_get_assoc_led_name(sc->hw);
647 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
648 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
649 ret = ath_register_led(sc, &sc->assoc_led, trigger);
650 sc->assoc_led.led_type = ATH_LED_ASSOC;
651 if (ret)
652 goto fail;
f078f209 653
8feceb67
VT
654 trigger = ieee80211_get_tx_led_name(sc->hw);
655 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
656 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
657 ret = ath_register_led(sc, &sc->tx_led, trigger);
658 sc->tx_led.led_type = ATH_LED_TX;
659 if (ret)
660 goto fail;
f078f209 661
8feceb67
VT
662 trigger = ieee80211_get_rx_led_name(sc->hw);
663 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
664 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
665 ret = ath_register_led(sc, &sc->rx_led, trigger);
666 sc->rx_led.led_type = ATH_LED_RX;
667 if (ret)
668 goto fail;
f078f209 669
8feceb67
VT
670 return;
671
672fail:
673 ath_deinit_leds(sc);
f078f209
LR
674}
675
500c064d
VT
676#ifdef CONFIG_RFKILL
677/*******************/
678/* Rfkill */
679/*******************/
680
681static void ath_radio_enable(struct ath_softc *sc)
682{
683 struct ath_hal *ah = sc->sc_ah;
684 int status;
685
686 spin_lock_bh(&sc->sc_resetlock);
687 if (!ath9k_hw_reset(ah, ah->ah_curchan,
688 sc->sc_ht_info.tx_chan_width,
689 sc->sc_tx_chainmask,
690 sc->sc_rx_chainmask,
691 sc->sc_ht_extprotspacing,
692 false, &status)) {
693 DPRINTF(sc, ATH_DBG_FATAL,
694 "%s: unable to reset channel %u (%uMhz) "
695 "flags 0x%x hal status %u\n", __func__,
696 ath9k_hw_mhz2ieee(ah,
697 ah->ah_curchan->channel,
698 ah->ah_curchan->channelFlags),
699 ah->ah_curchan->channel,
700 ah->ah_curchan->channelFlags, status);
701 }
702 spin_unlock_bh(&sc->sc_resetlock);
703
704 ath_update_txpow(sc);
705 if (ath_startrecv(sc) != 0) {
706 DPRINTF(sc, ATH_DBG_FATAL,
707 "%s: unable to restart recv logic\n", __func__);
708 return;
709 }
710
711 if (sc->sc_flags & SC_OP_BEACONS)
712 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
713
714 /* Re-Enable interrupts */
715 ath9k_hw_set_interrupts(ah, sc->sc_imask);
716
717 /* Enable LED */
718 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
719 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
720 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
721
722 ieee80211_wake_queues(sc->hw);
723}
724
725static void ath_radio_disable(struct ath_softc *sc)
726{
727 struct ath_hal *ah = sc->sc_ah;
728 int status;
729
730
731 ieee80211_stop_queues(sc->hw);
732
733 /* Disable LED */
734 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
735 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
736
737 /* Disable interrupts */
738 ath9k_hw_set_interrupts(ah, 0);
739
740 ath_draintxq(sc, false); /* clear pending tx frames */
741 ath_stoprecv(sc); /* turn off frame recv */
742 ath_flushrecv(sc); /* flush recv queue */
743
744 spin_lock_bh(&sc->sc_resetlock);
745 if (!ath9k_hw_reset(ah, ah->ah_curchan,
746 sc->sc_ht_info.tx_chan_width,
747 sc->sc_tx_chainmask,
748 sc->sc_rx_chainmask,
749 sc->sc_ht_extprotspacing,
750 false, &status)) {
751 DPRINTF(sc, ATH_DBG_FATAL,
752 "%s: unable to reset channel %u (%uMhz) "
753 "flags 0x%x hal status %u\n", __func__,
754 ath9k_hw_mhz2ieee(ah,
755 ah->ah_curchan->channel,
756 ah->ah_curchan->channelFlags),
757 ah->ah_curchan->channel,
758 ah->ah_curchan->channelFlags, status);
759 }
760 spin_unlock_bh(&sc->sc_resetlock);
761
762 ath9k_hw_phy_disable(ah);
763 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
764}
765
766static bool ath_is_rfkill_set(struct ath_softc *sc)
767{
768 struct ath_hal *ah = sc->sc_ah;
769
770 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
771 ah->ah_rfkill_polarity;
772}
773
774/* h/w rfkill poll function */
775static void ath_rfkill_poll(struct work_struct *work)
776{
777 struct ath_softc *sc = container_of(work, struct ath_softc,
778 rf_kill.rfkill_poll.work);
779 bool radio_on;
780
781 if (sc->sc_flags & SC_OP_INVALID)
782 return;
783
784 radio_on = !ath_is_rfkill_set(sc);
785
786 /*
787 * enable/disable radio only when there is a
788 * state change in RF switch
789 */
790 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
791 enum rfkill_state state;
792
793 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
794 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
795 : RFKILL_STATE_HARD_BLOCKED;
796 } else if (radio_on) {
797 ath_radio_enable(sc);
798 state = RFKILL_STATE_UNBLOCKED;
799 } else {
800 ath_radio_disable(sc);
801 state = RFKILL_STATE_HARD_BLOCKED;
802 }
803
804 if (state == RFKILL_STATE_HARD_BLOCKED)
805 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
806 else
807 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
808
809 rfkill_force_state(sc->rf_kill.rfkill, state);
810 }
811
812 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
813 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
814}
815
816/* s/w rfkill handler */
817static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
818{
819 struct ath_softc *sc = data;
820
821 switch (state) {
822 case RFKILL_STATE_SOFT_BLOCKED:
823 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
824 SC_OP_RFKILL_SW_BLOCKED)))
825 ath_radio_disable(sc);
826 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
827 return 0;
828 case RFKILL_STATE_UNBLOCKED:
829 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
830 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
831 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
832 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
833 "radio as it is disabled by h/w \n");
834 return -EPERM;
835 }
836 ath_radio_enable(sc);
837 }
838 return 0;
839 default:
840 return -EINVAL;
841 }
842}
843
844/* Init s/w rfkill */
845static int ath_init_sw_rfkill(struct ath_softc *sc)
846{
847 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
848 RFKILL_TYPE_WLAN);
849 if (!sc->rf_kill.rfkill) {
850 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
851 return -ENOMEM;
852 }
853
854 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
855 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
856 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
857 sc->rf_kill.rfkill->data = sc;
858 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
859 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
860 sc->rf_kill.rfkill->user_claim_unsupported = 1;
861
862 return 0;
863}
864
865/* Deinitialize rfkill */
866static void ath_deinit_rfkill(struct ath_softc *sc)
867{
868 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
869 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
870
871 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
872 rfkill_unregister(sc->rf_kill.rfkill);
873 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
874 sc->rf_kill.rfkill = NULL;
875 }
876}
877#endif /* CONFIG_RFKILL */
878
8feceb67 879static int ath_detach(struct ath_softc *sc)
f078f209 880{
8feceb67 881 struct ieee80211_hw *hw = sc->hw;
f078f209 882
8feceb67 883 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
f078f209 884
8feceb67
VT
885 /* Deinit LED control */
886 ath_deinit_leds(sc);
f078f209 887
500c064d
VT
888#ifdef CONFIG_RFKILL
889 /* deinit rfkill */
890 ath_deinit_rfkill(sc);
891#endif
892
8feceb67 893 /* Unregister hw */
f078f209 894
8feceb67 895 ieee80211_unregister_hw(hw);
f078f209 896
8feceb67
VT
897 /* unregister Rate control */
898 ath_rate_control_unregister();
f078f209 899
8feceb67 900 /* tx/rx cleanup */
f078f209 901
8feceb67
VT
902 ath_rx_cleanup(sc);
903 ath_tx_cleanup(sc);
f078f209 904
8feceb67 905 /* Deinit */
f078f209 906
8feceb67
VT
907 ath_deinit(sc);
908
909 return 0;
f078f209
LR
910}
911
8feceb67
VT
912static int ath_attach(u16 devid,
913 struct ath_softc *sc)
f078f209 914{
8feceb67
VT
915 struct ieee80211_hw *hw = sc->hw;
916 int error = 0;
f078f209 917
8feceb67 918 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
f078f209 919
8feceb67
VT
920 error = ath_init(devid, sc);
921 if (error != 0)
922 return error;
f078f209 923
8feceb67 924 /* Init nodes */
f078f209 925
8feceb67
VT
926 INIT_LIST_HEAD(&sc->node_list);
927 spin_lock_init(&sc->node_lock);
f078f209 928
8feceb67 929 /* get mac address from hardware and set in mac80211 */
f078f209 930
8feceb67 931 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
f078f209 932
8feceb67 933 /* setup channels and rates */
f078f209 934
8feceb67
VT
935 sc->sbands[IEEE80211_BAND_2GHZ].channels =
936 sc->channels[IEEE80211_BAND_2GHZ];
937 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
938 sc->rates[IEEE80211_BAND_2GHZ];
939 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
f078f209 940
8feceb67
VT
941 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
942 /* Setup HT capabilities for 2.4Ghz*/
d9fe60de 943 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
f078f209 944
8feceb67
VT
945 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
946 &sc->sbands[IEEE80211_BAND_2GHZ];
f078f209 947
8feceb67
VT
948 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
949 sc->sbands[IEEE80211_BAND_5GHZ].channels =
950 sc->channels[IEEE80211_BAND_5GHZ];
951 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
952 sc->rates[IEEE80211_BAND_5GHZ];
953 sc->sbands[IEEE80211_BAND_5GHZ].band =
954 IEEE80211_BAND_5GHZ;
f078f209 955
8feceb67
VT
956 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
957 /* Setup HT capabilities for 5Ghz*/
d9fe60de 958 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
f078f209 959
8feceb67
VT
960 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
961 &sc->sbands[IEEE80211_BAND_5GHZ];
962 }
f078f209 963
8feceb67 964 /* FIXME: Have to figure out proper hw init values later */
f078f209 965
8feceb67
VT
966 hw->queues = 4;
967 hw->ampdu_queues = 1;
f078f209 968
8feceb67
VT
969 /* Register rate control */
970 hw->rate_control_algorithm = "ath9k_rate_control";
971 error = ath_rate_control_register();
972 if (error != 0) {
973 DPRINTF(sc, ATH_DBG_FATAL,
974 "%s: Unable to register rate control "
975 "algorithm:%d\n", __func__, error);
976 ath_rate_control_unregister();
977 goto bad;
978 }
f078f209 979
8feceb67
VT
980 error = ieee80211_register_hw(hw);
981 if (error != 0) {
982 ath_rate_control_unregister();
983 goto bad;
f078f209 984 }
8feceb67
VT
985
986 /* Initialize LED control */
987 ath_init_leds(sc);
988
500c064d
VT
989#ifdef CONFIG_RFKILL
990 /* Initialze h/w Rfkill */
991 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
992 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
993
994 /* Initialize s/w rfkill */
995 if (ath_init_sw_rfkill(sc))
996 goto detach;
997#endif
998
8feceb67
VT
999 /* initialize tx/rx engine */
1000
1001 error = ath_tx_init(sc, ATH_TXBUF);
1002 if (error != 0)
1003 goto detach;
1004
1005 error = ath_rx_init(sc, ATH_RXBUF);
1006 if (error != 0)
1007 goto detach;
1008
1009 return 0;
1010detach:
1011 ath_detach(sc);
1012bad:
1013 return error;
f078f209
LR
1014}
1015
8feceb67 1016static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR
1017{
1018 struct ath_softc *sc = hw->priv;
8feceb67
VT
1019 struct ieee80211_channel *curchan = hw->conf.channel;
1020 int error = 0, pos;
f078f209 1021
8feceb67
VT
1022 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
1023 "initial channel: %d MHz\n", __func__, curchan->center_freq);
f078f209 1024
8feceb67 1025 /* setup initial channel */
f078f209 1026
8feceb67
VT
1027 pos = ath_get_channel(sc, curchan);
1028 if (pos == -1) {
1029 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
1030 return -EINVAL;
f078f209
LR
1031 }
1032
8feceb67
VT
1033 sc->sc_ah->ah_channels[pos].chanmode =
1034 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1035
1036 /* open ath_dev */
1037 error = ath_open(sc, &sc->sc_ah->ah_channels[pos]);
1038 if (error) {
1039 DPRINTF(sc, ATH_DBG_FATAL,
1040 "%s: Unable to complete ath_open\n", __func__);
1041 return error;
f078f209 1042 }
8feceb67 1043
500c064d
VT
1044#ifdef CONFIG_RFKILL
1045 /* Start rfkill polling */
1046 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1047 queue_delayed_work(sc->hw->workqueue,
1048 &sc->rf_kill.rfkill_poll, 0);
1049
1050 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1051 if (rfkill_register(sc->rf_kill.rfkill)) {
1052 DPRINTF(sc, ATH_DBG_FATAL,
1053 "Unable to register rfkill\n");
1054 rfkill_free(sc->rf_kill.rfkill);
1055
1056 /* Deinitialize the device */
1057 if (sc->pdev->irq)
1058 free_irq(sc->pdev->irq, sc);
1059 ath_detach(sc);
1060 pci_iounmap(sc->pdev, sc->mem);
1061 pci_release_region(sc->pdev, 0);
1062 pci_disable_device(sc->pdev);
1063 ieee80211_free_hw(hw);
1064 return -EIO;
1065 } else {
1066 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1067 }
1068 }
1069#endif
1070
8feceb67
VT
1071 ieee80211_wake_queues(hw);
1072 return 0;
f078f209
LR
1073}
1074
8feceb67
VT
1075static int ath9k_tx(struct ieee80211_hw *hw,
1076 struct sk_buff *skb)
f078f209 1077{
f078f209 1078 struct ath_softc *sc = hw->priv;
8feceb67
VT
1079 int hdrlen, padsize;
1080 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 1081
8feceb67
VT
1082 /*
1083 * As a temporary workaround, assign seq# here; this will likely need
1084 * to be cleaned up to work better with Beacon transmission and virtual
1085 * BSSes.
1086 */
1087 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1088 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1089 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1090 sc->seq_no += 0x10;
1091 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1092 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
1093 }
f078f209 1094
8feceb67
VT
1095 /* Add the padding after the header if this is not already done */
1096 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1097 if (hdrlen & 3) {
1098 padsize = hdrlen % 4;
1099 if (skb_headroom(skb) < padsize)
1100 return -1;
1101 skb_push(skb, padsize);
1102 memmove(skb->data, skb->data + padsize, hdrlen);
1103 }
1104
1105 DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
1106 __func__,
1107 skb);
1108
1109 if (ath_tx_start(sc, skb) != 0) {
1110 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
1111 dev_kfree_skb_any(skb);
1112 /* FIXME: Check for proper return value from ATH_DEV */
1113 return 0;
1114 }
1115
1116 return 0;
f078f209
LR
1117}
1118
8feceb67 1119static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR
1120{
1121 struct ath_softc *sc = hw->priv;
8feceb67 1122 int error;
f078f209 1123
8feceb67
VT
1124 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
1125
1126 error = ath_suspend(sc);
1127 if (error)
1128 DPRINTF(sc, ATH_DBG_CONFIG,
1129 "%s: Device is no longer present\n", __func__);
1130
1131 ieee80211_stop_queues(hw);
500c064d
VT
1132
1133#ifdef CONFIG_RFKILL
1134 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1135 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1136#endif
f078f209
LR
1137}
1138
8feceb67
VT
1139static int ath9k_add_interface(struct ieee80211_hw *hw,
1140 struct ieee80211_if_init_conf *conf)
f078f209
LR
1141{
1142 struct ath_softc *sc = hw->priv;
8feceb67 1143 int error, ic_opmode = 0;
f078f209 1144
8feceb67
VT
1145 /* Support only vap for now */
1146
1147 if (sc->sc_nvaps)
1148 return -ENOBUFS;
1149
1150 switch (conf->type) {
05c914fe 1151 case NL80211_IFTYPE_STATION:
8feceb67 1152 ic_opmode = ATH9K_M_STA;
f078f209 1153 break;
05c914fe 1154 case NL80211_IFTYPE_ADHOC:
8feceb67 1155 ic_opmode = ATH9K_M_IBSS;
f078f209 1156 break;
05c914fe 1157 case NL80211_IFTYPE_AP:
8feceb67 1158 ic_opmode = ATH9K_M_HOSTAP;
f078f209
LR
1159 break;
1160 default:
1161 DPRINTF(sc, ATH_DBG_FATAL,
8feceb67
VT
1162 "%s: Interface type %d not yet supported\n",
1163 __func__, conf->type);
1164 return -EOPNOTSUPP;
f078f209
LR
1165 }
1166
8feceb67
VT
1167 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
1168 __func__,
1169 ic_opmode);
1170
1171 error = ath_vap_attach(sc, 0, conf->vif, ic_opmode);
1172 if (error) {
1173 DPRINTF(sc, ATH_DBG_FATAL,
1174 "%s: Unable to attach vap, error: %d\n",
1175 __func__, error);
1176 return error;
1177 }
1178
6f255425
LR
1179 if (conf->type == NL80211_IFTYPE_AP) {
1180 /* TODO: is this a suitable place to start ANI for AP mode? */
1181 /* Start ANI */
1182 mod_timer(&sc->sc_ani.timer,
1183 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
1184 }
1185
8feceb67 1186 return 0;
f078f209
LR
1187}
1188
8feceb67
VT
1189static void ath9k_remove_interface(struct ieee80211_hw *hw,
1190 struct ieee80211_if_init_conf *conf)
f078f209 1191{
8feceb67
VT
1192 struct ath_softc *sc = hw->priv;
1193 struct ath_vap *avp;
1194 int error;
f078f209 1195
8feceb67 1196 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
f078f209 1197
8feceb67
VT
1198 avp = sc->sc_vaps[0];
1199 if (avp == NULL) {
1200 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
1201 __func__);
1202 return;
f078f209
LR
1203 }
1204
8feceb67
VT
1205#ifdef CONFIG_SLOW_ANT_DIV
1206 ath_slow_ant_div_stop(&sc->sc_antdiv);
1207#endif
6f255425
LR
1208 /* Stop ANI */
1209 del_timer_sync(&sc->sc_ani.timer);
580f0b8a 1210
8feceb67
VT
1211 /* Update ratectrl */
1212 ath_rate_newstate(sc, avp);
1213
1214 /* Reclaim beacon resources */
1215 if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||
1216 sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
1217 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
1218 ath_beacon_return(sc, avp);
580f0b8a 1219 }
f078f209 1220
8feceb67
VT
1221 /* Set interrupt mask */
1222 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1223 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask & ~ATH9K_INT_GLOBAL);
1224 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 1225
8feceb67
VT
1226 error = ath_vap_detach(sc, 0);
1227 if (error)
1228 DPRINTF(sc, ATH_DBG_FATAL,
1229 "%s: Unable to detach vap, error: %d\n",
1230 __func__, error);
f078f209
LR
1231}
1232
8feceb67
VT
1233static int ath9k_config(struct ieee80211_hw *hw,
1234 struct ieee80211_conf *conf)
f078f209 1235{
8feceb67
VT
1236 struct ath_softc *sc = hw->priv;
1237 struct ieee80211_channel *curchan = hw->conf.channel;
1238 int pos;
f078f209 1239
8feceb67
VT
1240 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
1241 __func__,
1242 curchan->center_freq);
f078f209 1243
8feceb67
VT
1244 pos = ath_get_channel(sc, curchan);
1245 if (pos == -1) {
1246 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
1247 return -EINVAL;
f078f209 1248 }
f078f209 1249
8feceb67
VT
1250 sc->sc_ah->ah_channels[pos].chanmode =
1251 (curchan->band == IEEE80211_BAND_2GHZ) ?
1252 CHANNEL_G : CHANNEL_A;
f078f209 1253
d9fe60de 1254 if (sc->sc_curaid && hw->conf.ht_cap.ht_supported)
8feceb67
VT
1255 sc->sc_ah->ah_channels[pos].chanmode =
1256 ath_get_extchanmode(sc, curchan);
f078f209 1257
8feceb67 1258 sc->sc_config.txpowlimit = 2 * conf->power_level;
f078f209 1259
8feceb67
VT
1260 /* set h/w channel */
1261 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
1262 DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
1263 __func__);
f078f209
LR
1264
1265 return 0;
1266}
1267
8feceb67
VT
1268static int ath9k_config_interface(struct ieee80211_hw *hw,
1269 struct ieee80211_vif *vif,
1270 struct ieee80211_if_conf *conf)
c83be688 1271{
8feceb67
VT
1272 struct ath_softc *sc = hw->priv;
1273 struct ath_hal *ah = sc->sc_ah;
1274 struct ath_vap *avp;
1275 u32 rfilt = 0;
1276 int error, i;
c83be688 1277
8feceb67
VT
1278 avp = sc->sc_vaps[0];
1279 if (avp == NULL) {
1280 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid interface\n",
1281 __func__);
1282 return -EINVAL;
c83be688 1283 }
c83be688 1284
8feceb67
VT
1285 /* TODO: Need to decide which hw opmode to use for multi-interface
1286 * cases */
05c914fe 1287 if (vif->type == NL80211_IFTYPE_AP &&
8feceb67
VT
1288 ah->ah_opmode != ATH9K_M_HOSTAP) {
1289 ah->ah_opmode = ATH9K_M_HOSTAP;
1290 ath9k_hw_setopmode(ah);
1291 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
1292 /* Request full reset to get hw opmode changed properly */
1293 sc->sc_flags |= SC_OP_FULL_RESET;
1294 }
c83be688 1295
8feceb67
VT
1296 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
1297 !is_zero_ether_addr(conf->bssid)) {
1298 switch (vif->type) {
05c914fe
JB
1299 case NL80211_IFTYPE_STATION:
1300 case NL80211_IFTYPE_ADHOC:
8feceb67
VT
1301 /* Update ratectrl about the new state */
1302 ath_rate_newstate(sc, avp);
c83be688 1303
8feceb67
VT
1304 /* Set BSSID */
1305 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
1306 sc->sc_curaid = 0;
1307 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
1308 sc->sc_curaid);
c83be688 1309
8feceb67
VT
1310 /* Set aggregation protection mode parameters */
1311 sc->sc_config.ath_aggr_prot = 0;
c83be688 1312
8feceb67
VT
1313 /*
1314 * Reset our TSF so that its value is lower than the
1315 * beacon that we are trying to catch.
1316 * Only then hw will update its TSF register with the
1317 * new beacon. Reset the TSF before setting the BSSID
1318 * to avoid allowing in any frames that would update
1319 * our TSF only to have us clear it
1320 * immediately thereafter.
1321 */
1322 ath9k_hw_reset_tsf(sc->sc_ah);
c83be688 1323
8feceb67
VT
1324 /* Disable BMISS interrupt when we're not associated */
1325 ath9k_hw_set_interrupts(sc->sc_ah,
1326 sc->sc_imask &
1327 ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
1328 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
c83be688 1329
8feceb67 1330 DPRINTF(sc, ATH_DBG_CONFIG,
e174961c 1331 "%s: RX filter 0x%x bssid %pM aid 0x%x\n",
8feceb67 1332 __func__, rfilt,
e174961c 1333 sc->sc_curbssid, sc->sc_curaid);
c83be688 1334
8feceb67
VT
1335 /* need to reconfigure the beacon */
1336 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 1337
8feceb67
VT
1338 break;
1339 default:
1340 break;
1341 }
1342 }
c83be688 1343
8feceb67 1344 if ((conf->changed & IEEE80211_IFCC_BEACON) &&
05c914fe
JB
1345 ((vif->type == NL80211_IFTYPE_ADHOC) ||
1346 (vif->type == NL80211_IFTYPE_AP))) {
8feceb67
VT
1347 /*
1348 * Allocate and setup the beacon frame.
1349 *
1350 * Stop any previous beacon DMA. This may be
1351 * necessary, for example, when an ibss merge
1352 * causes reconfiguration; we may be called
1353 * with beacon transmission active.
1354 */
1355 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
c83be688 1356
8feceb67
VT
1357 error = ath_beacon_alloc(sc, 0);
1358 if (error != 0)
1359 return error;
c83be688 1360
8feceb67
VT
1361 ath_beacon_sync(sc, 0);
1362 }
c83be688 1363
8feceb67 1364 /* Check for WLAN_CAPABILITY_PRIVACY ? */
05c914fe 1365 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT
1366 for (i = 0; i < IEEE80211_WEP_NKID; i++)
1367 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
1368 ath9k_hw_keysetmac(sc->sc_ah,
1369 (u16)i,
1370 sc->sc_curbssid);
1371 }
c83be688 1372
8feceb67 1373 /* Only legacy IBSS for now */
05c914fe 1374 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 1375 ath_update_chainmask(sc, 0);
f078f209 1376
8feceb67
VT
1377 return 0;
1378}
f078f209 1379
8feceb67
VT
1380#define SUPPORTED_FILTERS \
1381 (FIF_PROMISC_IN_BSS | \
1382 FIF_ALLMULTI | \
1383 FIF_CONTROL | \
1384 FIF_OTHER_BSS | \
1385 FIF_BCN_PRBRESP_PROMISC | \
1386 FIF_FCSFAIL)
c83be688 1387
8feceb67
VT
1388/* FIXME: sc->sc_full_reset ? */
1389static void ath9k_configure_filter(struct ieee80211_hw *hw,
1390 unsigned int changed_flags,
1391 unsigned int *total_flags,
1392 int mc_count,
1393 struct dev_mc_list *mclist)
1394{
1395 struct ath_softc *sc = hw->priv;
1396 u32 rfilt;
f078f209 1397
8feceb67
VT
1398 changed_flags &= SUPPORTED_FILTERS;
1399 *total_flags &= SUPPORTED_FILTERS;
f078f209 1400
8feceb67
VT
1401 sc->rx_filter = *total_flags;
1402 rfilt = ath_calcrxfilter(sc);
1403 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 1404
8feceb67
VT
1405 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
1406 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1407 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
1408 }
f078f209 1409
8feceb67
VT
1410 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set HW RX filter: 0x%x\n",
1411 __func__, sc->rx_filter);
1412}
f078f209 1413
8feceb67
VT
1414static void ath9k_sta_notify(struct ieee80211_hw *hw,
1415 struct ieee80211_vif *vif,
1416 enum sta_notify_cmd cmd,
17741cdc 1417 struct ieee80211_sta *sta)
8feceb67
VT
1418{
1419 struct ath_softc *sc = hw->priv;
1420 struct ath_node *an;
1421 unsigned long flags;
f078f209 1422
8feceb67 1423 spin_lock_irqsave(&sc->node_lock, flags);
17741cdc 1424 an = ath_node_find(sc, sta->addr);
8feceb67 1425 spin_unlock_irqrestore(&sc->node_lock, flags);
f078f209 1426
8feceb67
VT
1427 switch (cmd) {
1428 case STA_NOTIFY_ADD:
1429 spin_lock_irqsave(&sc->node_lock, flags);
1430 if (!an) {
17741cdc 1431 ath_node_attach(sc, sta->addr, 0);
e174961c
JB
1432 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a node: %pM\n",
1433 __func__, sta->addr);
8feceb67 1434 } else {
17741cdc 1435 ath_node_get(sc, sta->addr);
8feceb67
VT
1436 }
1437 spin_unlock_irqrestore(&sc->node_lock, flags);
1438 break;
1439 case STA_NOTIFY_REMOVE:
1440 if (!an)
1441 DPRINTF(sc, ATH_DBG_FATAL,
1442 "%s: Removal of a non-existent node\n",
1443 __func__);
1444 else {
1445 ath_node_put(sc, an, ATH9K_BH_STATUS_INTACT);
e174961c 1446 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Put a node: %pM\n",
8feceb67 1447 __func__,
e174961c 1448 sta->addr);
8feceb67
VT
1449 }
1450 break;
1451 default:
1452 break;
1453 }
f078f209
LR
1454}
1455
8feceb67
VT
1456static int ath9k_conf_tx(struct ieee80211_hw *hw,
1457 u16 queue,
1458 const struct ieee80211_tx_queue_params *params)
f078f209 1459{
8feceb67
VT
1460 struct ath_softc *sc = hw->priv;
1461 struct ath9k_tx_queue_info qi;
1462 int ret = 0, qnum;
f078f209 1463
8feceb67
VT
1464 if (queue >= WME_NUM_AC)
1465 return 0;
f078f209 1466
8feceb67
VT
1467 qi.tqi_aifs = params->aifs;
1468 qi.tqi_cwmin = params->cw_min;
1469 qi.tqi_cwmax = params->cw_max;
1470 qi.tqi_burstTime = params->txop;
1471 qnum = ath_get_hal_qnum(queue, sc);
f078f209 1472
8feceb67
VT
1473 DPRINTF(sc, ATH_DBG_CONFIG,
1474 "%s: Configure tx [queue/halq] [%d/%d], "
1475 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1476 __func__,
1477 queue,
1478 qnum,
1479 params->aifs,
1480 params->cw_min,
1481 params->cw_max,
1482 params->txop);
f078f209 1483
8feceb67
VT
1484 ret = ath_txq_update(sc, qnum, &qi);
1485 if (ret)
1486 DPRINTF(sc, ATH_DBG_FATAL,
1487 "%s: TXQ Update failed\n", __func__);
f078f209 1488
8feceb67
VT
1489 return ret;
1490}
f078f209 1491
8feceb67
VT
1492static int ath9k_set_key(struct ieee80211_hw *hw,
1493 enum set_key_cmd cmd,
1494 const u8 *local_addr,
1495 const u8 *addr,
1496 struct ieee80211_key_conf *key)
1497{
1498 struct ath_softc *sc = hw->priv;
1499 int ret = 0;
f078f209 1500
8feceb67 1501 DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
f078f209 1502
8feceb67
VT
1503 switch (cmd) {
1504 case SET_KEY:
1505 ret = ath_key_config(sc, addr, key);
1506 if (!ret) {
1507 set_bit(key->keyidx, sc->sc_keymap);
1508 key->hw_key_idx = key->keyidx;
1509 /* push IV and Michael MIC generation to stack */
1510 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1511 if (key->alg == ALG_TKIP)
1512 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1513 }
1514 break;
1515 case DISABLE_KEY:
1516 ath_key_delete(sc, key);
1517 clear_bit(key->keyidx, sc->sc_keymap);
8feceb67
VT
1518 break;
1519 default:
1520 ret = -EINVAL;
1521 }
f078f209 1522
8feceb67
VT
1523 return ret;
1524}
f078f209 1525
8feceb67
VT
1526static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1527 struct ieee80211_vif *vif,
1528 struct ieee80211_bss_conf *bss_conf,
1529 u32 changed)
1530{
1531 struct ath_softc *sc = hw->priv;
f078f209 1532
8feceb67
VT
1533 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1534 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
1535 __func__,
1536 bss_conf->use_short_preamble);
1537 if (bss_conf->use_short_preamble)
1538 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
1539 else
1540 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
1541 }
f078f209 1542
8feceb67
VT
1543 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1544 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
1545 __func__,
1546 bss_conf->use_cts_prot);
1547 if (bss_conf->use_cts_prot &&
1548 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
1549 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
1550 else
1551 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
1552 }
f078f209 1553
8feceb67
VT
1554 if (changed & BSS_CHANGED_HT) {
1555 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT %d\n",
1556 __func__,
1557 bss_conf->assoc_ht);
1558 ath9k_ht_conf(sc, bss_conf);
f078f209
LR
1559 }
1560
8feceb67
VT
1561 if (changed & BSS_CHANGED_ASSOC) {
1562 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
1563 __func__,
1564 bss_conf->assoc);
1565 ath9k_bss_assoc_info(sc, bss_conf);
1566 }
1567}
f078f209 1568
8feceb67
VT
1569static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
1570{
1571 u64 tsf;
1572 struct ath_softc *sc = hw->priv;
1573 struct ath_hal *ah = sc->sc_ah;
f078f209 1574
8feceb67 1575 tsf = ath9k_hw_gettsf64(ah);
f078f209 1576
8feceb67
VT
1577 return tsf;
1578}
f078f209 1579
8feceb67
VT
1580static void ath9k_reset_tsf(struct ieee80211_hw *hw)
1581{
1582 struct ath_softc *sc = hw->priv;
1583 struct ath_hal *ah = sc->sc_ah;
c83be688 1584
8feceb67
VT
1585 ath9k_hw_reset_tsf(ah);
1586}
f078f209 1587
8feceb67
VT
1588static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1589 enum ieee80211_ampdu_mlme_action action,
17741cdc
JB
1590 struct ieee80211_sta *sta,
1591 u16 tid, u16 *ssn)
8feceb67
VT
1592{
1593 struct ath_softc *sc = hw->priv;
1594 int ret = 0;
f078f209 1595
8feceb67
VT
1596 switch (action) {
1597 case IEEE80211_AMPDU_RX_START:
17741cdc 1598 ret = ath_rx_aggr_start(sc, sta->addr, tid, ssn);
8feceb67
VT
1599 if (ret < 0)
1600 DPRINTF(sc, ATH_DBG_FATAL,
1601 "%s: Unable to start RX aggregation\n",
1602 __func__);
1603 break;
1604 case IEEE80211_AMPDU_RX_STOP:
17741cdc 1605 ret = ath_rx_aggr_stop(sc, sta->addr, tid);
8feceb67
VT
1606 if (ret < 0)
1607 DPRINTF(sc, ATH_DBG_FATAL,
1608 "%s: Unable to stop RX aggregation\n",
1609 __func__);
1610 break;
1611 case IEEE80211_AMPDU_TX_START:
17741cdc 1612 ret = ath_tx_aggr_start(sc, sta->addr, tid, ssn);
8feceb67
VT
1613 if (ret < 0)
1614 DPRINTF(sc, ATH_DBG_FATAL,
1615 "%s: Unable to start TX aggregation\n",
1616 __func__);
1617 else
17741cdc 1618 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT
1619 break;
1620 case IEEE80211_AMPDU_TX_STOP:
17741cdc 1621 ret = ath_tx_aggr_stop(sc, sta->addr, tid);
8feceb67
VT
1622 if (ret < 0)
1623 DPRINTF(sc, ATH_DBG_FATAL,
1624 "%s: Unable to stop TX aggregation\n",
1625 __func__);
f078f209 1626
17741cdc 1627 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT
1628 break;
1629 default:
1630 DPRINTF(sc, ATH_DBG_FATAL,
1631 "%s: Unknown AMPDU action\n", __func__);
1632 }
1633
1634 return ret;
f078f209
LR
1635}
1636
4233df6b
JB
1637static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
1638{
1639 return -EOPNOTSUPP;
1640}
1641
8feceb67
VT
1642static struct ieee80211_ops ath9k_ops = {
1643 .tx = ath9k_tx,
1644 .start = ath9k_start,
1645 .stop = ath9k_stop,
1646 .add_interface = ath9k_add_interface,
1647 .remove_interface = ath9k_remove_interface,
1648 .config = ath9k_config,
1649 .config_interface = ath9k_config_interface,
1650 .configure_filter = ath9k_configure_filter,
1651 .get_stats = NULL,
1652 .sta_notify = ath9k_sta_notify,
1653 .conf_tx = ath9k_conf_tx,
1654 .get_tx_stats = NULL,
1655 .bss_info_changed = ath9k_bss_info_changed,
1656 .set_tim = NULL,
1657 .set_key = ath9k_set_key,
1658 .hw_scan = NULL,
1659 .get_tkip_seq = NULL,
1660 .set_rts_threshold = NULL,
1661 .set_frag_threshold = NULL,
1662 .set_retry_limit = NULL,
1663 .get_tsf = ath9k_get_tsf,
1664 .reset_tsf = ath9k_reset_tsf,
1665 .tx_last_beacon = NULL,
4233df6b
JB
1666 .ampdu_action = ath9k_ampdu_action,
1667 .set_frag_threshold = ath9k_no_fragmentation,
8feceb67
VT
1668};
1669
f078f209
LR
1670static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1671{
1672 void __iomem *mem;
1673 struct ath_softc *sc;
1674 struct ieee80211_hw *hw;
1675 const char *athname;
1676 u8 csz;
1677 u32 val;
1678 int ret = 0;
1679
1680 if (pci_enable_device(pdev))
1681 return -EIO;
1682
1683 /* XXX 32-bit addressing only */
1684 if (pci_set_dma_mask(pdev, 0xffffffff)) {
1685 printk(KERN_ERR "ath_pci: 32-bit DMA not available\n");
1686 ret = -ENODEV;
1687 goto bad;
1688 }
1689
1690 /*
1691 * Cache line size is used to size and align various
1692 * structures used to communicate with the hardware.
1693 */
1694 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
1695 if (csz == 0) {
1696 /*
1697 * Linux 2.4.18 (at least) writes the cache line size
1698 * register as a 16-bit wide register which is wrong.
1699 * We must have this setup properly for rx buffer
1700 * DMA to work so force a reasonable value here if it
1701 * comes up zero.
1702 */
1703 csz = L1_CACHE_BYTES / sizeof(u32);
1704 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
1705 }
1706 /*
1707 * The default setting of latency timer yields poor results,
1708 * set it to the value used by other systems. It may be worth
1709 * tweaking this setting more.
1710 */
1711 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
1712
1713 pci_set_master(pdev);
1714
1715 /*
1716 * Disable the RETRY_TIMEOUT register (0x41) to keep
1717 * PCI Tx retries from interfering with C3 CPU state.
1718 */
1719 pci_read_config_dword(pdev, 0x40, &val);
1720 if ((val & 0x0000ff00) != 0)
1721 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1722
1723 ret = pci_request_region(pdev, 0, "ath9k");
1724 if (ret) {
1725 dev_err(&pdev->dev, "PCI memory region reserve error\n");
1726 ret = -ENODEV;
1727 goto bad;
1728 }
1729
1730 mem = pci_iomap(pdev, 0, 0);
1731 if (!mem) {
1732 printk(KERN_ERR "PCI memory map error\n") ;
1733 ret = -EIO;
1734 goto bad1;
1735 }
1736
1737 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
1738 if (hw == NULL) {
1739 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
1740 goto bad2;
1741 }
1742
19b73c7f 1743 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
e022edbd 1744 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
19b73c7f 1745 IEEE80211_HW_SIGNAL_DBM |
f078f209
LR
1746 IEEE80211_HW_NOISE_DBM;
1747
f59ac048
LR
1748 hw->wiphy->interface_modes =
1749 BIT(NL80211_IFTYPE_AP) |
1750 BIT(NL80211_IFTYPE_STATION) |
1751 BIT(NL80211_IFTYPE_ADHOC);
1752
f078f209
LR
1753 SET_IEEE80211_DEV(hw, &pdev->dev);
1754 pci_set_drvdata(pdev, hw);
1755
1756 sc = hw->priv;
1757 sc->hw = hw;
1758 sc->pdev = pdev;
1759 sc->mem = mem;
1760
1761 if (ath_attach(id->device, sc) != 0) {
1762 ret = -ENODEV;
1763 goto bad3;
1764 }
1765
1766 /* setup interrupt service routine */
1767
1768 if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
1769 printk(KERN_ERR "%s: request_irq failed\n",
1770 wiphy_name(hw->wiphy));
1771 ret = -EIO;
1772 goto bad4;
1773 }
1774
1775 athname = ath9k_hw_probe(id->vendor, id->device);
1776
1777 printk(KERN_INFO "%s: %s: mem=0x%lx, irq=%d\n",
1778 wiphy_name(hw->wiphy),
1779 athname ? athname : "Atheros ???",
1780 (unsigned long)mem, pdev->irq);
1781
1782 return 0;
1783bad4:
1784 ath_detach(sc);
1785bad3:
1786 ieee80211_free_hw(hw);
1787bad2:
1788 pci_iounmap(pdev, mem);
1789bad1:
1790 pci_release_region(pdev, 0);
1791bad:
1792 pci_disable_device(pdev);
1793 return ret;
1794}
1795
1796static void ath_pci_remove(struct pci_dev *pdev)
1797{
1798 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1799 struct ath_softc *sc = hw->priv;
6115e855 1800 enum ath9k_int status;
f078f209 1801
6115e855
SB
1802 if (pdev->irq) {
1803 ath9k_hw_set_interrupts(sc->sc_ah, 0);
1804 /* clear the ISR */
1805 ath9k_hw_getisr(sc->sc_ah, &status);
b262e603 1806 sc->sc_flags |= SC_OP_INVALID;
f078f209 1807 free_irq(pdev->irq, sc);
6115e855 1808 }
f078f209 1809 ath_detach(sc);
6115e855 1810
f078f209
LR
1811 pci_iounmap(pdev, sc->mem);
1812 pci_release_region(pdev, 0);
1813 pci_disable_device(pdev);
1814 ieee80211_free_hw(hw);
1815}
1816
1817#ifdef CONFIG_PM
1818
1819static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1820{
c83be688
VT
1821 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1822 struct ath_softc *sc = hw->priv;
1823
1824 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
500c064d
VT
1825
1826#ifdef CONFIG_RFKILL
1827 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1828 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1829#endif
1830
f078f209
LR
1831 pci_save_state(pdev);
1832 pci_disable_device(pdev);
1833 pci_set_power_state(pdev, 3);
1834
1835 return 0;
1836}
1837
1838static int ath_pci_resume(struct pci_dev *pdev)
1839{
c83be688
VT
1840 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
1841 struct ath_softc *sc = hw->priv;
f078f209
LR
1842 u32 val;
1843 int err;
1844
1845 err = pci_enable_device(pdev);
1846 if (err)
1847 return err;
1848 pci_restore_state(pdev);
1849 /*
1850 * Suspend/Resume resets the PCI configuration space, so we have to
1851 * re-disable the RETRY_TIMEOUT register (0x41) to keep
1852 * PCI Tx retries from interfering with C3 CPU state
1853 */
1854 pci_read_config_dword(pdev, 0x40, &val);
1855 if ((val & 0x0000ff00) != 0)
1856 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1857
c83be688
VT
1858 /* Enable LED */
1859 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1860 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1861 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1862
500c064d
VT
1863#ifdef CONFIG_RFKILL
1864 /*
1865 * check the h/w rfkill state on resume
1866 * and start the rfkill poll timer
1867 */
1868 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1869 queue_delayed_work(sc->hw->workqueue,
1870 &sc->rf_kill.rfkill_poll, 0);
1871#endif
1872
f078f209
LR
1873 return 0;
1874}
1875
1876#endif /* CONFIG_PM */
1877
1878MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
1879
1880static struct pci_driver ath_pci_driver = {
1881 .name = "ath9k",
1882 .id_table = ath_pci_id_table,
1883 .probe = ath_pci_probe,
1884 .remove = ath_pci_remove,
1885#ifdef CONFIG_PM
1886 .suspend = ath_pci_suspend,
1887 .resume = ath_pci_resume,
1888#endif /* CONFIG_PM */
1889};
1890
1891static int __init init_ath_pci(void)
1892{
1893 printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
1894
1895 if (pci_register_driver(&ath_pci_driver) < 0) {
1896 printk(KERN_ERR
1897 "ath_pci: No devices found, driver not installed.\n");
1898 pci_unregister_driver(&ath_pci_driver);
1899 return -ENODEV;
1900 }
1901
1902 return 0;
1903}
1904module_init(init_ath_pci);
1905
1906static void __exit exit_ath_pci(void)
1907{
1908 pci_unregister_driver(&ath_pci_driver);
1909 printk(KERN_INFO "%s: driver unloaded\n", dev_info);
1910}
1911module_exit(exit_ath_pci);
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