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ath9k: convert to struct device
[deliverable/linux.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209
LR		 17#include <linux/nl80211.h>
18#include "core.h"
392dff83 19#include "reg.h"
2a163c6d 20#include "hw.h"
f078f209
LR		 21
22#define ATH_PCI_VERSION "0.1"
23
f078f209
LR		 24static char *dev_info = "ath9k";
25
26MODULE_AUTHOR("Atheros Communications");
27MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29MODULE_LICENSE("Dual BSD/GPL");
30
31static struct pci_device_id ath_pci_id_table[] __devinitdata = {
32 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
33 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
34 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
35 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
36 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
e7594072 37 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
f078f209
LR		 38 { 0 }
39};
40
9757d556
S		 41static void ath_detach(struct ath_softc *sc);
42
ff37e337
S		 43/* return bus cachesize in 4B word units */
44
45static void bus_read_cachesize(struct ath_softc *sc, int *csz)
46{
47 u8 u8tmp;
48
f5870acb
GJ		 49 pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
50 (u8 *)&u8tmp);
ff37e337
S		 51 *csz = (int)u8tmp;
52
53 /*
54 * This check was put in to avoid "unplesant" consequences if
55 * the bootrom has not fully initialized all PCI devices.
56 * Sometimes the cache line size register is not set
57 */
58
59 if (*csz == 0)
60 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
61}
62
ce111bad
LR		 63static void ath_cache_conf_rate(struct ath_softc *sc,
64 struct ieee80211_conf *conf)
ff37e337 65{
030bb495
LR		 66 switch (conf->channel->band) {
67 case IEEE80211_BAND_2GHZ:
68 if (conf_is_ht20(conf))
69 sc->cur_rate_table =
70 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
71 else if (conf_is_ht40_minus(conf))
72 sc->cur_rate_table =
73 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
74 else if (conf_is_ht40_plus(conf))
75 sc->cur_rate_table =
76 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 77 else
030bb495
LR		 78 sc->cur_rate_table =
79 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 80 break;
81 case IEEE80211_BAND_5GHZ:
82 if (conf_is_ht20(conf))
83 sc->cur_rate_table =
84 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
85 else if (conf_is_ht40_minus(conf))
86 sc->cur_rate_table =
87 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
88 else if (conf_is_ht40_plus(conf))
89 sc->cur_rate_table =
90 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
91 else
96742256
LR		 92 sc->cur_rate_table =
93 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 94 break;
95 default:
ce111bad 96 BUG_ON(1);
030bb495
LR		 97 break;
98 }
ff37e337
S		 99}
100
101static void ath_update_txpow(struct ath_softc *sc)
102{
103 struct ath_hal *ah = sc->sc_ah;
104 u32 txpow;
105
106 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
107 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
108 /* read back in case value is clamped */
109 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
110 sc->sc_curtxpow = txpow;
111 }
112}
113
114static u8 parse_mpdudensity(u8 mpdudensity)
115{
116 /*
117 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
118 * 0 for no restriction
119 * 1 for 1/4 us
120 * 2 for 1/2 us
121 * 3 for 1 us
122 * 4 for 2 us
123 * 5 for 4 us
124 * 6 for 8 us
125 * 7 for 16 us
126 */
127 switch (mpdudensity) {
128 case 0:
129 return 0;
130 case 1:
131 case 2:
132 case 3:
133 /* Our lower layer calculations limit our precision to
134 1 microsecond */
135 return 1;
136 case 4:
137 return 2;
138 case 5:
139 return 4;
140 case 6:
141 return 8;
142 case 7:
143 return 16;
144 default:
145 return 0;
146 }
147}
148
149static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
150{
151 struct ath_rate_table *rate_table = NULL;
152 struct ieee80211_supported_band *sband;
153 struct ieee80211_rate *rate;
154 int i, maxrates;
155
156 switch (band) {
157 case IEEE80211_BAND_2GHZ:
158 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
159 break;
160 case IEEE80211_BAND_5GHZ:
161 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
162 break;
163 default:
164 break;
165 }
166
167 if (rate_table == NULL)
168 return;
169
170 sband = &sc->sbands[band];
171 rate = sc->rates[band];
172
173 if (rate_table->rate_cnt > ATH_RATE_MAX)
174 maxrates = ATH_RATE_MAX;
175 else
176 maxrates = rate_table->rate_cnt;
177
178 for (i = 0; i < maxrates; i++) {
179 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
180 rate[i].hw_value = rate_table->info[i].ratecode;
181 sband->n_bitrates++;
04bd4638
S		 182 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
183 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 184 }
185}
186
187static int ath_setup_channels(struct ath_softc *sc)
188{
189 struct ath_hal *ah = sc->sc_ah;
190 int nchan, i, a = 0, b = 0;
191 u8 regclassids[ATH_REGCLASSIDS_MAX];
192 u32 nregclass = 0;
193 struct ieee80211_supported_band *band_2ghz;
194 struct ieee80211_supported_band *band_5ghz;
195 struct ieee80211_channel *chan_2ghz;
196 struct ieee80211_channel *chan_5ghz;
197 struct ath9k_channel *c;
198
199 /* Fill in ah->ah_channels */
200 if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
201 regclassids, ATH_REGCLASSIDS_MAX,
202 &nregclass, CTRY_DEFAULT, false, 1)) {
203 u32 rd = ah->ah_currentRD;
204 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 205 "Unable to collect channel list; "
ff37e337 206 "regdomain likely %u country code %u\n",
04bd4638 207 rd, CTRY_DEFAULT);
ff37e337
S		 208 return -EINVAL;
209 }
210
211 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
212 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
213 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
214 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
215
216 for (i = 0; i < nchan; i++) {
217 c = &ah->ah_channels[i];
218 if (IS_CHAN_2GHZ(c)) {
219 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
220 chan_2ghz[a].center_freq = c->channel;
221 chan_2ghz[a].max_power = c->maxTxPower;
76061abb 222 c->chan = &chan_2ghz[a];
ff37e337
S		 223
224 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
225 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
226 if (c->channelFlags & CHANNEL_PASSIVE)
227 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
228
229 band_2ghz->n_channels = ++a;
230
04bd4638 231 DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
ff37e337 232 "channelFlags: 0x%x\n",
04bd4638 233 c->channel, c->channelFlags);
ff37e337
S		 234 } else if (IS_CHAN_5GHZ(c)) {
235 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
236 chan_5ghz[b].center_freq = c->channel;
237 chan_5ghz[b].max_power = c->maxTxPower;
76061abb 238 c->chan = &chan_5ghz[a];
ff37e337
S		 239
240 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
241 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
242 if (c->channelFlags & CHANNEL_PASSIVE)
243 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
244
245 band_5ghz->n_channels = ++b;
246
04bd4638 247 DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
ff37e337 248 "channelFlags: 0x%x\n",
04bd4638 249 c->channel, c->channelFlags);
ff37e337
S		 250 }
251 }
252
253 return 0;
254}
255
256/*
257 * Set/change channels. If the channel is really being changed, it's done
258 * by reseting the chip. To accomplish this we must first cleanup any pending
259 * DMA, then restart stuff.
260*/
261static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
262{
263 struct ath_hal *ah = sc->sc_ah;
264 bool fastcc = true, stopped;
030bb495 265 struct ieee80211_hw *hw = sc->hw;
ae8d2858
LR		 266 struct ieee80211_channel *channel = hw->conf.channel;
267 int r;
ff37e337
S		 268
269 if (sc->sc_flags & SC_OP_INVALID)
270 return -EIO;
271
c0d7c7af
LR		 272 /*
273 * This is only performed if the channel settings have
274 * actually changed.
275 *
276 * To switch channels clear any pending DMA operations;
277 * wait long enough for the RX fifo to drain, reset the
278 * hardware at the new frequency, and then re-enable
279 * the relevant bits of the h/w.
280 */
281 ath9k_hw_set_interrupts(ah, 0);
282 ath_draintxq(sc, false);
283 stopped = ath_stoprecv(sc);
ff37e337 284
c0d7c7af
LR		 285 /* XXX: do not flush receive queue here. We don't want
286 * to flush data frames already in queue because of
287 * changing channel. */
ff37e337 288
c0d7c7af
LR		 289 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
290 fastcc = false;
291
292 DPRINTF(sc, ATH_DBG_CONFIG,
293 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
294 sc->sc_ah->ah_curchan->channel,
295 channel->center_freq, sc->tx_chan_width);
ff37e337 296
c0d7c7af
LR		 297 spin_lock_bh(&sc->sc_resetlock);
298
299 r = ath9k_hw_reset(ah, hchan, fastcc);
300 if (r) {
301 DPRINTF(sc, ATH_DBG_FATAL,
302 "Unable to reset channel (%u Mhz) "
303 "reset status %u\n",
304 channel->center_freq, r);
305 spin_unlock_bh(&sc->sc_resetlock);
306 return r;
ff37e337 307 }
c0d7c7af
LR		 308 spin_unlock_bh(&sc->sc_resetlock);
309
310 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
311 sc->sc_flags &= ~SC_OP_FULL_RESET;
312
313 if (ath_startrecv(sc) != 0) {
314 DPRINTF(sc, ATH_DBG_FATAL,
315 "Unable to restart recv logic\n");
316 return -EIO;
317 }
318
319 ath_cache_conf_rate(sc, &hw->conf);
320 ath_update_txpow(sc);
321 ath9k_hw_set_interrupts(ah, sc->sc_imask);
ff37e337
S		 322 return 0;
323}
324
325/*
326 * This routine performs the periodic noise floor calibration function
327 * that is used to adjust and optimize the chip performance. This
328 * takes environmental changes (location, temperature) into account.
329 * When the task is complete, it reschedules itself depending on the
330 * appropriate interval that was calculated.
331 */
332static void ath_ani_calibrate(unsigned long data)
333{
334 struct ath_softc *sc;
335 struct ath_hal *ah;
336 bool longcal = false;
337 bool shortcal = false;
338 bool aniflag = false;
339 unsigned int timestamp = jiffies_to_msecs(jiffies);
340 u32 cal_interval;
341
342 sc = (struct ath_softc *)data;
343 ah = sc->sc_ah;
344
345 /*
346 * don't calibrate when we're scanning.
347 * we are most likely not on our home channel.
348 */
b77f483f 349 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
ff37e337
S		 350 return;
351
352 /* Long calibration runs independently of short calibration. */
353 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
354 longcal = true;
04bd4638 355 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
ff37e337
S		 356 sc->sc_ani.sc_longcal_timer = timestamp;
357 }
358
359 /* Short calibration applies only while sc_caldone is false */
360 if (!sc->sc_ani.sc_caldone) {
361 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
362 ATH_SHORT_CALINTERVAL) {
363 shortcal = true;
04bd4638 364 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
ff37e337
S		 365 sc->sc_ani.sc_shortcal_timer = timestamp;
366 sc->sc_ani.sc_resetcal_timer = timestamp;
367 }
368 } else {
369 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
370 ATH_RESTART_CALINTERVAL) {
c9e27d94 371 sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
ff37e337
S		 372 if (sc->sc_ani.sc_caldone)
373 sc->sc_ani.sc_resetcal_timer = timestamp;
374 }
375 }
376
377 /* Verify whether we must check ANI */
378 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
379 ATH_ANI_POLLINTERVAL) {
380 aniflag = true;
381 sc->sc_ani.sc_checkani_timer = timestamp;
382 }
383
384 /* Skip all processing if there's nothing to do. */
385 if (longcal || shortcal || aniflag) {
386 /* Call ANI routine if necessary */
387 if (aniflag)
388 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
389 ah->ah_curchan);
390
391 /* Perform calibration if necessary */
392 if (longcal || shortcal) {
393 bool iscaldone = false;
394
395 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
396 sc->sc_rx_chainmask, longcal,
397 &iscaldone)) {
398 if (longcal)
399 sc->sc_ani.sc_noise_floor =
400 ath9k_hw_getchan_noise(ah,
401 ah->ah_curchan);
402
403 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 404 "calibrate chan %u/%x nf: %d\n",
ff37e337
S		 405 ah->ah_curchan->channel,
406 ah->ah_curchan->channelFlags,
407 sc->sc_ani.sc_noise_floor);
408 } else {
409 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 410 "calibrate chan %u/%x failed\n",
ff37e337
S		 411 ah->ah_curchan->channel,
412 ah->ah_curchan->channelFlags);
413 }
414 sc->sc_ani.sc_caldone = iscaldone;
415 }
416 }
417
418 /*
419 * Set timer interval based on previous results.
420 * The interval must be the shortest necessary to satisfy ANI,
421 * short calibration and long calibration.
422 */
aac9207e
S		 423 cal_interval = ATH_LONG_CALINTERVAL;
424 if (sc->sc_ah->ah_config.enable_ani)
425 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
ff37e337
S		 426 if (!sc->sc_ani.sc_caldone)
427 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
428
429 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
430}
431
432/*
433 * Update tx/rx chainmask. For legacy association,
434 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 435 * the chainmask configuration, for bt coexistence, use
436 * the chainmask configuration even in legacy mode.
ff37e337
S		 437 */
438static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
439{
440 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
c97c92d9
VT		 441 if (is_ht ||
442 (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
ff37e337
S		 443 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
444 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
445 } else {
446 sc->sc_tx_chainmask = 1;
447 sc->sc_rx_chainmask = 1;
448 }
449
04bd4638
S		 450 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
451 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
ff37e337
S		 452}
453
454static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
455{
456 struct ath_node *an;
457
458 an = (struct ath_node *)sta->drv_priv;
459
460 if (sc->sc_flags & SC_OP_TXAGGR)
461 ath_tx_node_init(sc, an);
462
463 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
464 sta->ht_cap.ampdu_factor);
465 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
466}
467
468static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
469{
470 struct ath_node *an = (struct ath_node *)sta->drv_priv;
471
472 if (sc->sc_flags & SC_OP_TXAGGR)
473 ath_tx_node_cleanup(sc, an);
474}
475
476static void ath9k_tasklet(unsigned long data)
477{
478 struct ath_softc *sc = (struct ath_softc *)data;
479 u32 status = sc->sc_intrstatus;
480
481 if (status & ATH9K_INT_FATAL) {
482 /* need a chip reset */
483 ath_reset(sc, false);
484 return;
485 } else {
486
487 if (status &
488 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 489 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 490 ath_rx_tasklet(sc, 0);
b77f483f 491 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 492 }
493 /* XXX: optimize this */
494 if (status & ATH9K_INT_TX)
495 ath_tx_tasklet(sc);
496 }
497
498 /* re-enable hardware interrupt */
499 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
500}
501
502static irqreturn_t ath_isr(int irq, void *dev)
503{
504 struct ath_softc *sc = dev;
505 struct ath_hal *ah = sc->sc_ah;
506 enum ath9k_int status;
507 bool sched = false;
508
509 do {
510 if (sc->sc_flags & SC_OP_INVALID) {
511 /*
512 * The hardware is not ready/present, don't
513 * touch anything. Note this can happen early
514 * on if the IRQ is shared.
515 */
516 return IRQ_NONE;
517 }
518 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
519 return IRQ_NONE;
520 }
521
522 /*
523 * Figure out the reason(s) for the interrupt. Note
524 * that the hal returns a pseudo-ISR that may include
525 * bits we haven't explicitly enabled so we mask the
526 * value to insure we only process bits we requested.
527 */
528 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
529
530 status &= sc->sc_imask; /* discard unasked-for bits */
531
532 /*
533 * If there are no status bits set, then this interrupt was not
534 * for me (should have been caught above).
535 */
536 if (!status)
537 return IRQ_NONE;
538
539 sc->sc_intrstatus = status;
540
541 if (status & ATH9K_INT_FATAL) {
542 /* need a chip reset */
543 sched = true;
544 } else if (status & ATH9K_INT_RXORN) {
545 /* need a chip reset */
546 sched = true;
547 } else {
548 if (status & ATH9K_INT_SWBA) {
549 /* schedule a tasklet for beacon handling */
550 tasklet_schedule(&sc->bcon_tasklet);
551 }
552 if (status & ATH9K_INT_RXEOL) {
553 /*
554 * NB: the hardware should re-read the link when
555 * RXE bit is written, but it doesn't work
556 * at least on older hardware revs.
557 */
558 sched = true;
559 }
560
561 if (status & ATH9K_INT_TXURN)
562 /* bump tx trigger level */
563 ath9k_hw_updatetxtriglevel(ah, true);
564 /* XXX: optimize this */
565 if (status & ATH9K_INT_RX)
566 sched = true;
567 if (status & ATH9K_INT_TX)
568 sched = true;
569 if (status & ATH9K_INT_BMISS)
570 sched = true;
571 /* carrier sense timeout */
572 if (status & ATH9K_INT_CST)
573 sched = true;
574 if (status & ATH9K_INT_MIB) {
575 /*
576 * Disable interrupts until we service the MIB
577 * interrupt; otherwise it will continue to
578 * fire.
579 */
580 ath9k_hw_set_interrupts(ah, 0);
581 /*
582 * Let the hal handle the event. We assume
583 * it will clear whatever condition caused
584 * the interrupt.
585 */
586 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
587 ath9k_hw_set_interrupts(ah, sc->sc_imask);
588 }
589 if (status & ATH9K_INT_TIM_TIMER) {
590 if (!(ah->ah_caps.hw_caps &
591 ATH9K_HW_CAP_AUTOSLEEP)) {
592 /* Clear RxAbort bit so that we can
593 * receive frames */
594 ath9k_hw_setrxabort(ah, 0);
595 sched = true;
596 }
597 }
598 }
599 } while (0);
600
817e11de
S		 601 ath_debug_stat_interrupt(sc, status);
602
ff37e337
S		 603 if (sched) {
604 /* turn off every interrupt except SWBA */
605 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
606 tasklet_schedule(&sc->intr_tq);
607 }
608
609 return IRQ_HANDLED;
610}
611
f078f209
LR		 612static int ath_get_channel(struct ath_softc *sc,
613 struct ieee80211_channel *chan)
614{
615 int i;
616
617 for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
618 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
619 return i;
620 }
621
622 return -1;
623}
624
625static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 626 struct ieee80211_channel *chan,
094d05dc 627 enum nl80211_channel_type channel_type)
f078f209
LR		 628{
629 u32 chanmode = 0;
f078f209
LR		 630
631 switch (chan->band) {
632 case IEEE80211_BAND_2GHZ:
094d05dc
S		 633 switch(channel_type) {
634 case NL80211_CHAN_NO_HT:
635 case NL80211_CHAN_HT20:
f078f209 636 chanmode = CHANNEL_G_HT20;
094d05dc
S		 637 break;
638 case NL80211_CHAN_HT40PLUS:
f078f209 639 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 640 break;
641 case NL80211_CHAN_HT40MINUS:
f078f209 642 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 643 break;
644 }
f078f209
LR		 645 break;
646 case IEEE80211_BAND_5GHZ:
094d05dc
S		 647 switch(channel_type) {
648 case NL80211_CHAN_NO_HT:
649 case NL80211_CHAN_HT20:
f078f209 650 chanmode = CHANNEL_A_HT20;
094d05dc
S		 651 break;
652 case NL80211_CHAN_HT40PLUS:
f078f209 653 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 654 break;
655 case NL80211_CHAN_HT40MINUS:
f078f209 656 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 657 break;
658 }
f078f209
LR		 659 break;
660 default:
661 break;
662 }
663
664 return chanmode;
665}
666
ff37e337
S		 667static int ath_keyset(struct ath_softc *sc, u16 keyix,
668 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
669{
670 bool status;
671
672 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
673 keyix, hk, mac, false);
674
675 return status != false;
676}
f078f209 677
6ace2891 678static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
f078f209
LR		 679 struct ath9k_keyval *hk,
680 const u8 *addr)
681{
6ace2891
JM		 682 const u8 *key_rxmic;
683 const u8 *key_txmic;
f078f209 684
6ace2891
JM		 685 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
686 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 687
688 if (addr == NULL) {
689 /* Group key installation */
6ace2891
JM		 690 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
691 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 692 }
693 if (!sc->sc_splitmic) {
694 /*
695 * data key goes at first index,
696 * the hal handles the MIC keys at index+64.
697 */
698 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
699 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
6ace2891 700 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 701 }
702 /*
703 * TX key goes at first index, RX key at +32.
704 * The hal handles the MIC keys at index+64.
705 */
706 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
6ace2891 707 if (!ath_keyset(sc, keyix, hk, NULL)) {
f078f209
LR		 708 /* Txmic entry failed. No need to proceed further */
709 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 710 "Setting TX MIC Key Failed\n");
f078f209
LR		 711 return 0;
712 }
713
714 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
715 /* XXX delete tx key on failure? */
6ace2891
JM		 716 return ath_keyset(sc, keyix + 32, hk, addr);
717}
718
719static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
720{
721 int i;
722
723 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
724 if (test_bit(i, sc->sc_keymap) ||
725 test_bit(i + 64, sc->sc_keymap))
726 continue; /* At least one part of TKIP key allocated */
727 if (sc->sc_splitmic &&
728 (test_bit(i + 32, sc->sc_keymap) ||
729 test_bit(i + 64 + 32, sc->sc_keymap)))
730 continue; /* At least one part of TKIP key allocated */
731
732 /* Found a free slot for a TKIP key */
733 return i;
734 }
735 return -1;
736}
737
738static int ath_reserve_key_cache_slot(struct ath_softc *sc)
739{
740 int i;
741
742 /* First, try to find slots that would not be available for TKIP. */
743 if (sc->sc_splitmic) {
744 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
745 if (!test_bit(i, sc->sc_keymap) &&
746 (test_bit(i + 32, sc->sc_keymap) ||
747 test_bit(i + 64, sc->sc_keymap) ||
748 test_bit(i + 64 + 32, sc->sc_keymap)))
749 return i;
750 if (!test_bit(i + 32, sc->sc_keymap) &&
751 (test_bit(i, sc->sc_keymap) ||
752 test_bit(i + 64, sc->sc_keymap) ||
753 test_bit(i + 64 + 32, sc->sc_keymap)))
754 return i + 32;
755 if (!test_bit(i + 64, sc->sc_keymap) &&
756 (test_bit(i , sc->sc_keymap) ||
757 test_bit(i + 32, sc->sc_keymap) ||
758 test_bit(i + 64 + 32, sc->sc_keymap)))
ea612132 759 return i + 64;
6ace2891
JM		 760 if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
761 (test_bit(i, sc->sc_keymap) ||
762 test_bit(i + 32, sc->sc_keymap) ||
763 test_bit(i + 64, sc->sc_keymap)))
ea612132 764 return i + 64 + 32;
6ace2891
JM		 765 }
766 } else {
767 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
768 if (!test_bit(i, sc->sc_keymap) &&
769 test_bit(i + 64, sc->sc_keymap))
770 return i;
771 if (test_bit(i, sc->sc_keymap) &&
772 !test_bit(i + 64, sc->sc_keymap))
773 return i + 64;
774 }
775 }
776
777 /* No partially used TKIP slots, pick any available slot */
778 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
be2864cf
JM		 779 /* Do not allow slots that could be needed for TKIP group keys
780 * to be used. This limitation could be removed if we know that
781 * TKIP will not be used. */
782 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
783 continue;
784 if (sc->sc_splitmic) {
785 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
786 continue;
787 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
788 continue;
789 }
790
6ace2891
JM		 791 if (!test_bit(i, sc->sc_keymap))
792 return i; /* Found a free slot for a key */
793 }
794
795 /* No free slot found */
796 return -1;
f078f209
LR		 797}
798
799static int ath_key_config(struct ath_softc *sc,
dc822b5d 800 struct ieee80211_sta *sta,
f078f209
LR		 801 struct ieee80211_key_conf *key)
802{
f078f209
LR		 803 struct ath9k_keyval hk;
804 const u8 *mac = NULL;
805 int ret = 0;
6ace2891 806 int idx;
f078f209
LR		 807
808 memset(&hk, 0, sizeof(hk));
809
810 switch (key->alg) {
811 case ALG_WEP:
812 hk.kv_type = ATH9K_CIPHER_WEP;
813 break;
814 case ALG_TKIP:
815 hk.kv_type = ATH9K_CIPHER_TKIP;
816 break;
817 case ALG_CCMP:
818 hk.kv_type = ATH9K_CIPHER_AES_CCM;
819 break;
820 default:
ca470b29 821 return -EOPNOTSUPP;
f078f209
LR		 822 }
823
6ace2891 824 hk.kv_len = key->keylen;
f078f209
LR		 825 memcpy(hk.kv_val, key->key, key->keylen);
826
6ace2891
JM		 827 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
828 /* For now, use the default keys for broadcast keys. This may
829 * need to change with virtual interfaces. */
830 idx = key->keyidx;
831 } else if (key->keyidx) {
832 struct ieee80211_vif *vif;
f078f209 833
dc822b5d
JB		 834 if (WARN_ON(!sta))
835 return -EOPNOTSUPP;
836 mac = sta->addr;
837
6ace2891
JM		 838 vif = sc->sc_vaps[0];
839 if (vif->type != NL80211_IFTYPE_AP) {
840 /* Only keyidx 0 should be used with unicast key, but
841 * allow this for client mode for now. */
842 idx = key->keyidx;
843 } else
844 return -EIO;
f078f209 845 } else {
dc822b5d
JB		 846 if (WARN_ON(!sta))
847 return -EOPNOTSUPP;
848 mac = sta->addr;
849
6ace2891
JM		 850 if (key->alg == ALG_TKIP)
851 idx = ath_reserve_key_cache_slot_tkip(sc);
852 else
853 idx = ath_reserve_key_cache_slot(sc);
854 if (idx < 0)
ca470b29 855 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 856 }
857
858 if (key->alg == ALG_TKIP)
6ace2891 859 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
f078f209 860 else
6ace2891 861 ret = ath_keyset(sc, idx, &hk, mac);
f078f209
LR		 862
863 if (!ret)
864 return -EIO;
865
6ace2891
JM		 866 set_bit(idx, sc->sc_keymap);
867 if (key->alg == ALG_TKIP) {
868 set_bit(idx + 64, sc->sc_keymap);
869 if (sc->sc_splitmic) {
870 set_bit(idx + 32, sc->sc_keymap);
871 set_bit(idx + 64 + 32, sc->sc_keymap);
872 }
873 }
874
875 return idx;
f078f209
LR		 876}
877
878static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
879{
6ace2891
JM		 880 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
881 if (key->hw_key_idx < IEEE80211_WEP_NKID)
882 return;
883
884 clear_bit(key->hw_key_idx, sc->sc_keymap);
885 if (key->alg != ALG_TKIP)
886 return;
f078f209 887
6ace2891
JM		 888 clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
889 if (sc->sc_splitmic) {
890 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
891 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
892 }
f078f209
LR		 893}
894
d9fe60de 895static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
f078f209 896{
60653678
S		 897#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
898#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 899
d9fe60de
JB		 900 ht_info->ht_supported = true;
901 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
902 IEEE80211_HT_CAP_SM_PS |
903 IEEE80211_HT_CAP_SGI_40 |
904 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 905
60653678
S		 906 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
907 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
d9fe60de
JB		 908 /* set up supported mcs set */
909 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
910 ht_info->mcs.rx_mask[0] = 0xff;
911 ht_info->mcs.rx_mask[1] = 0xff;
912 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 913}
914
8feceb67 915static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 916 struct ieee80211_vif *vif,
8feceb67 917 struct ieee80211_bss_conf *bss_conf)
f078f209 918{
5640b08e 919 struct ath_vap *avp = (void *)vif->drv_priv;
f078f209 920
8feceb67 921 if (bss_conf->assoc) {
094d05dc
S		 922 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
923 bss_conf->aid, sc->sc_curbssid);
f078f209 924
8feceb67 925 /* New association, store aid */
d97809db 926 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
8feceb67
VT		 927 sc->sc_curaid = bss_conf->aid;
928 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
929 sc->sc_curaid);
930 }
f078f209 931
8feceb67
VT		 932 /* Configure the beacon */
933 ath_beacon_config(sc, 0);
934 sc->sc_flags |= SC_OP_BEACONS;
f078f209 935
8feceb67
VT		 936 /* Reset rssi stats */
937 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
938 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
939 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
940 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 941
6f255425
LR		 942 /* Start ANI */
943 mod_timer(&sc->sc_ani.timer,
944 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
945
8feceb67 946 } else {
04bd4638 947 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
8feceb67 948 sc->sc_curaid = 0;
f078f209 949 }
8feceb67 950}
f078f209 951
8feceb67
VT		 952/********************************/
953/* LED functions */
954/********************************/
f078f209 955
8feceb67
VT		 956static void ath_led_brightness(struct led_classdev *led_cdev,
957 enum led_brightness brightness)
958{
959 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
960 struct ath_softc *sc = led->sc;
f078f209 961
8feceb67
VT		 962 switch (brightness) {
963 case LED_OFF:
964 if (led->led_type == ATH_LED_ASSOC ||
965 led->led_type == ATH_LED_RADIO)
966 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
967 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
968 (led->led_type == ATH_LED_RADIO) ? 1 :
969 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
970 break;
971 case LED_FULL:
972 if (led->led_type == ATH_LED_ASSOC)
973 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
974 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
975 break;
976 default:
977 break;
f078f209 978 }
8feceb67 979}
f078f209 980
8feceb67
VT		 981static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
982 char *trigger)
983{
984 int ret;
f078f209 985
8feceb67
VT		 986 led->sc = sc;
987 led->led_cdev.name = led->name;
988 led->led_cdev.default_trigger = trigger;
989 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 990
8feceb67
VT		 991 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
992 if (ret)
993 DPRINTF(sc, ATH_DBG_FATAL,
994 "Failed to register led:%s", led->name);
995 else
996 led->registered = 1;
997 return ret;
998}
f078f209 999
8feceb67
VT		 1000static void ath_unregister_led(struct ath_led *led)
1001{
1002 if (led->registered) {
1003 led_classdev_unregister(&led->led_cdev);
1004 led->registered = 0;
f078f209 1005 }
f078f209
LR		 1006}
1007
8feceb67 1008static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1009{
8feceb67
VT		 1010 ath_unregister_led(&sc->assoc_led);
1011 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1012 ath_unregister_led(&sc->tx_led);
1013 ath_unregister_led(&sc->rx_led);
1014 ath_unregister_led(&sc->radio_led);
1015 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1016}
f078f209 1017
8feceb67
VT		 1018static void ath_init_leds(struct ath_softc *sc)
1019{
1020 char *trigger;
1021 int ret;
f078f209 1022
8feceb67
VT		 1023 /* Configure gpio 1 for output */
1024 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1025 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1026 /* LED off, active low */
1027 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1028
8feceb67
VT		 1029 trigger = ieee80211_get_radio_led_name(sc->hw);
1030 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1031 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1032 ret = ath_register_led(sc, &sc->radio_led, trigger);
1033 sc->radio_led.led_type = ATH_LED_RADIO;
1034 if (ret)
1035 goto fail;
7dcfdcd9 1036
8feceb67
VT		 1037 trigger = ieee80211_get_assoc_led_name(sc->hw);
1038 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1039 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1040 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1041 sc->assoc_led.led_type = ATH_LED_ASSOC;
1042 if (ret)
1043 goto fail;
f078f209 1044
8feceb67
VT		 1045 trigger = ieee80211_get_tx_led_name(sc->hw);
1046 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1047 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1048 ret = ath_register_led(sc, &sc->tx_led, trigger);
1049 sc->tx_led.led_type = ATH_LED_TX;
1050 if (ret)
1051 goto fail;
f078f209 1052
8feceb67
VT		 1053 trigger = ieee80211_get_rx_led_name(sc->hw);
1054 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1055 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1056 ret = ath_register_led(sc, &sc->rx_led, trigger);
1057 sc->rx_led.led_type = ATH_LED_RX;
1058 if (ret)
1059 goto fail;
f078f209 1060
8feceb67
VT		 1061 return;
1062
1063fail:
1064 ath_deinit_leds(sc);
f078f209
LR		 1065}
1066
e97275cb 1067#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1068
500c064d
VT		 1069/*******************/
1070/* Rfkill */
1071/*******************/
1072
1073static void ath_radio_enable(struct ath_softc *sc)
1074{
1075 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1076 struct ieee80211_channel *channel = sc->hw->conf.channel;
1077 int r;
500c064d
VT		 1078
1079 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1080
1081 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1082
1083 if (r) {
500c064d 1084 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1085 "Unable to reset channel %u (%uMhz) ",
1086 "reset status %u\n",
1087 channel->center_freq, r);
500c064d
VT		 1088 }
1089 spin_unlock_bh(&sc->sc_resetlock);
1090
1091 ath_update_txpow(sc);
1092 if (ath_startrecv(sc) != 0) {
1093 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1094 "Unable to restart recv logic\n");
500c064d
VT		 1095 return;
1096 }
1097
1098 if (sc->sc_flags & SC_OP_BEACONS)
1099 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1100
1101 /* Re-Enable interrupts */
1102 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1103
1104 /* Enable LED */
1105 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1106 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1107 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1108
1109 ieee80211_wake_queues(sc->hw);
1110}
1111
1112static void ath_radio_disable(struct ath_softc *sc)
1113{
1114 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1115 struct ieee80211_channel *channel = sc->hw->conf.channel;
1116 int r;
500c064d
VT		 1117
1118 ieee80211_stop_queues(sc->hw);
1119
1120 /* Disable LED */
1121 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1122 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1123
1124 /* Disable interrupts */
1125 ath9k_hw_set_interrupts(ah, 0);
1126
1127 ath_draintxq(sc, false); /* clear pending tx frames */
1128 ath_stoprecv(sc); /* turn off frame recv */
1129 ath_flushrecv(sc); /* flush recv queue */
1130
1131 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1132 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1133 if (r) {
500c064d 1134 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1135 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1136 "reset status %u\n",
1137 channel->center_freq, r);
500c064d
VT		 1138 }
1139 spin_unlock_bh(&sc->sc_resetlock);
1140
1141 ath9k_hw_phy_disable(ah);
1142 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1143}
1144
1145static bool ath_is_rfkill_set(struct ath_softc *sc)
1146{
1147 struct ath_hal *ah = sc->sc_ah;
1148
1149 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1150 ah->ah_rfkill_polarity;
1151}
1152
1153/* h/w rfkill poll function */
1154static void ath_rfkill_poll(struct work_struct *work)
1155{
1156 struct ath_softc *sc = container_of(work, struct ath_softc,
1157 rf_kill.rfkill_poll.work);
1158 bool radio_on;
1159
1160 if (sc->sc_flags & SC_OP_INVALID)
1161 return;
1162
1163 radio_on = !ath_is_rfkill_set(sc);
1164
1165 /*
1166 * enable/disable radio only when there is a
1167 * state change in RF switch
1168 */
1169 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1170 enum rfkill_state state;
1171
1172 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1173 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1174 : RFKILL_STATE_HARD_BLOCKED;
1175 } else if (radio_on) {
1176 ath_radio_enable(sc);
1177 state = RFKILL_STATE_UNBLOCKED;
1178 } else {
1179 ath_radio_disable(sc);
1180 state = RFKILL_STATE_HARD_BLOCKED;
1181 }
1182
1183 if (state == RFKILL_STATE_HARD_BLOCKED)
1184 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1185 else
1186 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1187
1188 rfkill_force_state(sc->rf_kill.rfkill, state);
1189 }
1190
1191 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1192 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1193}
1194
1195/* s/w rfkill handler */
1196static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1197{
1198 struct ath_softc *sc = data;
1199
1200 switch (state) {
1201 case RFKILL_STATE_SOFT_BLOCKED:
1202 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1203 SC_OP_RFKILL_SW_BLOCKED)))
1204 ath_radio_disable(sc);
1205 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1206 return 0;
1207 case RFKILL_STATE_UNBLOCKED:
1208 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1209 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1210 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1211 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1212 "radio as it is disabled by h/w\n");
500c064d
VT		 1213 return -EPERM;
1214 }
1215 ath_radio_enable(sc);
1216 }
1217 return 0;
1218 default:
1219 return -EINVAL;
1220 }
1221}
1222
1223/* Init s/w rfkill */
1224static int ath_init_sw_rfkill(struct ath_softc *sc)
1225{
1226 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1227 RFKILL_TYPE_WLAN);
1228 if (!sc->rf_kill.rfkill) {
1229 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1230 return -ENOMEM;
1231 }
1232
1233 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1234 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1235 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1236 sc->rf_kill.rfkill->data = sc;
1237 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1238 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1239 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1240
1241 return 0;
1242}
1243
1244/* Deinitialize rfkill */
1245static void ath_deinit_rfkill(struct ath_softc *sc)
1246{
1247 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1248 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1249
1250 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1251 rfkill_unregister(sc->rf_kill.rfkill);
1252 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1253 sc->rf_kill.rfkill = NULL;
1254 }
1255}
9c84b797
S		 1256
1257static int ath_start_rfkill_poll(struct ath_softc *sc)
1258{
1259 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1260 queue_delayed_work(sc->hw->workqueue,
1261 &sc->rf_kill.rfkill_poll, 0);
1262
1263 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1264 if (rfkill_register(sc->rf_kill.rfkill)) {
1265 DPRINTF(sc, ATH_DBG_FATAL,
1266 "Unable to register rfkill\n");
1267 rfkill_free(sc->rf_kill.rfkill);
1268
1269 /* Deinitialize the device */
306efdd1 1270 ath_detach(sc);
f5870acb
GJ		 1271 if (to_pci_dev(sc->dev)->irq)
1272 free_irq(to_pci_dev(sc->dev)->irq, sc);
1273 pci_iounmap(to_pci_dev(sc->dev), sc->mem);
1274 pci_release_region(to_pci_dev(sc->dev), 0);
1275 pci_disable_device(to_pci_dev(sc->dev));
9757d556 1276 ieee80211_free_hw(sc->hw);
9c84b797
S		 1277 return -EIO;
1278 } else {
1279 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1280 }
1281 }
1282
1283 return 0;
1284}
500c064d
VT		 1285#endif /* CONFIG_RFKILL */
1286
9c84b797 1287static void ath_detach(struct ath_softc *sc)
f078f209 1288{
8feceb67 1289 struct ieee80211_hw *hw = sc->hw;
9c84b797 1290 int i = 0;
f078f209 1291
04bd4638 1292 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1293
e97275cb 1294#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1295 ath_deinit_rfkill(sc);
1296#endif
3fcdfb4b
VT		 1297 ath_deinit_leds(sc);
1298
1299 ieee80211_unregister_hw(hw);
8feceb67
VT		 1300 ath_rx_cleanup(sc);
1301 ath_tx_cleanup(sc);
f078f209 1302
9c84b797
S		 1303 tasklet_kill(&sc->intr_tq);
1304 tasklet_kill(&sc->bcon_tasklet);
f078f209 1305
9c84b797
S		 1306 if (!(sc->sc_flags & SC_OP_INVALID))
1307 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1308
9c84b797
S		 1309 /* cleanup tx queues */
1310 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1311 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1312 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1313
1314 ath9k_hw_detach(sc->sc_ah);
826d2680 1315 ath9k_exit_debug(sc);
f078f209
LR		 1316}
1317
ff37e337
S		 1318static int ath_init(u16 devid, struct ath_softc *sc)
1319{
1320 struct ath_hal *ah = NULL;
1321 int status;
1322 int error = 0, i;
1323 int csz = 0;
1324
1325 /* XXX: hardware will not be ready until ath_open() being called */
1326 sc->sc_flags |= SC_OP_INVALID;
88b126af 1327
826d2680
S		 1328 if (ath9k_init_debug(sc) < 0)
1329 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S		 1330
1331 spin_lock_init(&sc->sc_resetlock);
aa33de09 1332 mutex_init(&sc->mutex);
ff37e337
S		 1333 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1334 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1335 (unsigned long)sc);
1336
1337 /*
1338 * Cache line size is used to size and align various
1339 * structures used to communicate with the hardware.
1340 */
1341 bus_read_cachesize(sc, &csz);
1342 /* XXX assert csz is non-zero */
1343 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1344
1345 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1346 if (ah == NULL) {
1347 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1348 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1349 error = -ENXIO;
1350 goto bad;
1351 }
1352 sc->sc_ah = ah;
1353
1354 /* Get the hardware key cache size. */
1355 sc->sc_keymax = ah->ah_caps.keycache_size;
1356 if (sc->sc_keymax > ATH_KEYMAX) {
1357 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638
S		 1358 "Warning, using only %u entries in %u key cache\n",
1359 ATH_KEYMAX, sc->sc_keymax);
ff37e337
S		 1360 sc->sc_keymax = ATH_KEYMAX;
1361 }
1362
1363 /*
1364 * Reset the key cache since some parts do not
1365 * reset the contents on initial power up.
1366 */
1367 for (i = 0; i < sc->sc_keymax; i++)
1368 ath9k_hw_keyreset(ah, (u16) i);
ff37e337
S		 1369
1370 /* Collect the channel list using the default country code */
1371
1372 error = ath_setup_channels(sc);
1373 if (error)
1374 goto bad;
1375
1376 /* default to MONITOR mode */
d97809db
CM		 1377 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1378
ff37e337
S		 1379
1380 /* Setup rate tables */
1381
1382 ath_rate_attach(sc);
1383 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1384 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1385
1386 /*
1387 * Allocate hardware transmit queues: one queue for
1388 * beacon frames and one data queue for each QoS
1389 * priority. Note that the hal handles reseting
1390 * these queues at the needed time.
1391 */
b77f483f
S		 1392 sc->beacon.beaconq = ath_beaconq_setup(ah);
1393 if (sc->beacon.beaconq == -1) {
ff37e337 1394 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1395 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1396 error = -EIO;
1397 goto bad2;
1398 }
b77f483f
S		 1399 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1400 if (sc->beacon.cabq == NULL) {
ff37e337 1401 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1402 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1403 error = -EIO;
1404 goto bad2;
1405 }
1406
1407 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1408 ath_cabq_update(sc);
1409
b77f483f
S		 1410 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1411 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1412
1413 /* Setup data queues */
1414 /* NB: ensure BK queue is the lowest priority h/w queue */
1415 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1416 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1417 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1418 error = -EIO;
1419 goto bad2;
1420 }
1421
1422 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1423 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1424 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1425 error = -EIO;
1426 goto bad2;
1427 }
1428 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1429 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1430 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1431 error = -EIO;
1432 goto bad2;
1433 }
1434 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1435 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1436 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1437 error = -EIO;
1438 goto bad2;
1439 }
1440
1441 /* Initializes the noise floor to a reasonable default value.
1442 * Later on this will be updated during ANI processing. */
1443
1444 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1445 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1446
1447 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1448 ATH9K_CIPHER_TKIP, NULL)) {
1449 /*
1450 * Whether we should enable h/w TKIP MIC.
1451 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1452 * report WMM capable, so it's always safe to turn on
1453 * TKIP MIC in this case.
1454 */
1455 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1456 0, 1, NULL);
1457 }
1458
1459 /*
1460 * Check whether the separate key cache entries
1461 * are required to handle both tx+rx MIC keys.
1462 * With split mic keys the number of stations is limited
1463 * to 27 otherwise 59.
1464 */
1465 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1466 ATH9K_CIPHER_TKIP, NULL)
1467 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1468 ATH9K_CIPHER_MIC, NULL)
1469 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1470 0, NULL))
1471 sc->sc_splitmic = 1;
1472
1473 /* turn on mcast key search if possible */
1474 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1475 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1476 1, NULL);
1477
1478 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1479 sc->sc_config.txpowlimit_override = 0;
1480
1481 /* 11n Capabilities */
1482 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1483 sc->sc_flags |= SC_OP_TXAGGR;
1484 sc->sc_flags |= SC_OP_RXAGGR;
1485 }
1486
1487 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1488 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1489
1490 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1491 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337
S		 1492
1493 ath9k_hw_getmac(ah, sc->sc_myaddr);
1494 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1495 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1496 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1497 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1498 }
1499
b77f483f 1500 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1501
1502 /* initialize beacon slots */
b77f483f
S		 1503 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1504 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
ff37e337
S		 1505
1506 /* save MISC configurations */
1507 sc->sc_config.swBeaconProcess = 1;
1508
ff37e337
S		 1509 /* setup channels and rates */
1510
1511 sc->sbands[IEEE80211_BAND_2GHZ].channels =
1512 sc->channels[IEEE80211_BAND_2GHZ];
1513 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1514 sc->rates[IEEE80211_BAND_2GHZ];
1515 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1516
1517 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1518 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1519 sc->channels[IEEE80211_BAND_5GHZ];
1520 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1521 sc->rates[IEEE80211_BAND_5GHZ];
1522 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1523 }
1524
c97c92d9
VT		 1525 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1526 ath9k_hw_btcoex_enable(sc->sc_ah);
1527
ff37e337
S		 1528 return 0;
1529bad2:
1530 /* cleanup tx queues */
1531 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1532 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1533 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1534bad:
1535 if (ah)
1536 ath9k_hw_detach(ah);
1537
1538 return error;
1539}
1540
9c84b797 1541static int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1542{
8feceb67
VT		 1543 struct ieee80211_hw *hw = sc->hw;
1544 int error = 0;
f078f209 1545
04bd4638 1546 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1547
8feceb67
VT		 1548 error = ath_init(devid, sc);
1549 if (error != 0)
1550 return error;
f078f209 1551
8feceb67 1552 /* get mac address from hardware and set in mac80211 */
f078f209 1553
8feceb67 1554 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
f078f209 1555
9c84b797
S		 1556 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1557 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1558 IEEE80211_HW_SIGNAL_DBM |
1559 IEEE80211_HW_AMPDU_AGGREGATION;
f078f209 1560
0ced0e17
JM		 1561 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1562 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1563
9c84b797
S		 1564 hw->wiphy->interface_modes =
1565 BIT(NL80211_IFTYPE_AP) |
1566 BIT(NL80211_IFTYPE_STATION) |
1567 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1568
8feceb67 1569 hw->queues = 4;
e63835b0
S		 1570 hw->max_rates = 4;
1571 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1572 hw->sta_data_size = sizeof(struct ath_node);
5640b08e 1573 hw->vif_data_size = sizeof(struct ath_vap);
f078f209 1574
8feceb67 1575 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1576
9c84b797
S		 1577 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1578 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1579 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1580 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1581 }
1582
1583 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1584 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1585 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1586 &sc->sbands[IEEE80211_BAND_5GHZ];
1587
db93e7b5
SB		 1588 /* initialize tx/rx engine */
1589 error = ath_tx_init(sc, ATH_TXBUF);
1590 if (error != 0)
1591 goto detach;
8feceb67 1592
db93e7b5
SB		 1593 error = ath_rx_init(sc, ATH_RXBUF);
1594 if (error != 0)
1595 goto detach;
8feceb67 1596
e97275cb 1597#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1598 /* Initialze h/w Rfkill */
1599 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1600 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1601
1602 /* Initialize s/w rfkill */
1603 if (ath_init_sw_rfkill(sc))
1604 goto detach;
1605#endif
1606
db93e7b5 1607 error = ieee80211_register_hw(hw);
8feceb67 1608
db93e7b5
SB		 1609 /* Initialize LED control */
1610 ath_init_leds(sc);
8feceb67
VT		 1611
1612 return 0;
1613detach:
1614 ath_detach(sc);
8feceb67 1615 return error;
f078f209
LR		 1616}
1617
ff37e337
S		 1618int ath_reset(struct ath_softc *sc, bool retry_tx)
1619{
1620 struct ath_hal *ah = sc->sc_ah;
030bb495 1621 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1622 int r;
ff37e337
S		 1623
1624 ath9k_hw_set_interrupts(ah, 0);
1625 ath_draintxq(sc, retry_tx);
1626 ath_stoprecv(sc);
1627 ath_flushrecv(sc);
1628
1629 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1630 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1631 if (r)
ff37e337 1632 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1633 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1634 spin_unlock_bh(&sc->sc_resetlock);
1635
1636 if (ath_startrecv(sc) != 0)
04bd4638 1637 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1638
1639 /*
1640 * We may be doing a reset in response to a request
1641 * that changes the channel so update any state that
1642 * might change as a result.
1643 */
ce111bad 1644 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1645
1646 ath_update_txpow(sc);
1647
1648 if (sc->sc_flags & SC_OP_BEACONS)
1649 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1650
1651 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1652
1653 if (retry_tx) {
1654 int i;
1655 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1656 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1657 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1658 ath_txq_schedule(sc, &sc->tx.txq[i]);
1659 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1660 }
1661 }
1662 }
1663
ae8d2858 1664 return r;
ff37e337
S		 1665}
1666
1667/*
1668 * This function will allocate both the DMA descriptor structure, and the
1669 * buffers it contains. These are used to contain the descriptors used
1670 * by the system.
1671*/
1672int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1673 struct list_head *head, const char *name,
1674 int nbuf, int ndesc)
1675{
1676#define DS2PHYS(_dd, _ds) \
1677 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1678#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1679#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1680
1681 struct ath_desc *ds;
1682 struct ath_buf *bf;
1683 int i, bsize, error;
1684
04bd4638
S		 1685 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1686 name, nbuf, ndesc);
ff37e337
S		 1687
1688 /* ath_desc must be a multiple of DWORDs */
1689 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1690 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1691 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1692 error = -ENOMEM;
1693 goto fail;
1694 }
1695
1696 dd->dd_name = name;
1697 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1698
1699 /*
1700 * Need additional DMA memory because we can't use
1701 * descriptors that cross the 4K page boundary. Assume
1702 * one skipped descriptor per 4K page.
1703 */
1704 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1705 u32 ndesc_skipped =
1706 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1707 u32 dma_len;
1708
1709 while (ndesc_skipped) {
1710 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1711 dd->dd_desc_len += dma_len;
1712
1713 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1714 };
1715 }
1716
1717 /* allocate descriptors */
f5870acb 1718 dd->dd_desc = pci_alloc_consistent(to_pci_dev(sc->dev),
ff37e337
S		 1719 dd->dd_desc_len,
1720 &dd->dd_desc_paddr);
1721 if (dd->dd_desc == NULL) {
1722 error = -ENOMEM;
1723 goto fail;
1724 }
1725 ds = dd->dd_desc;
04bd4638
S		 1726 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1727 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1728 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1729
1730 /* allocate buffers */
1731 bsize = sizeof(struct ath_buf) * nbuf;
1732 bf = kmalloc(bsize, GFP_KERNEL);
1733 if (bf == NULL) {
1734 error = -ENOMEM;
1735 goto fail2;
1736 }
1737 memset(bf, 0, bsize);
1738 dd->dd_bufptr = bf;
1739
1740 INIT_LIST_HEAD(head);
1741 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1742 bf->bf_desc = ds;
1743 bf->bf_daddr = DS2PHYS(dd, ds);
1744
1745 if (!(sc->sc_ah->ah_caps.hw_caps &
1746 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1747 /*
1748 * Skip descriptor addresses which can cause 4KB
1749 * boundary crossing (addr + length) with a 32 dword
1750 * descriptor fetch.
1751 */
1752 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1753 ASSERT((caddr_t) bf->bf_desc <
1754 ((caddr_t) dd->dd_desc +
1755 dd->dd_desc_len));
1756
1757 ds += ndesc;
1758 bf->bf_desc = ds;
1759 bf->bf_daddr = DS2PHYS(dd, ds);
1760 }
1761 }
1762 list_add_tail(&bf->list, head);
1763 }
1764 return 0;
1765fail2:
f5870acb 1766 pci_free_consistent(to_pci_dev(sc->dev),
ff37e337
S		 1767 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1768fail:
1769 memset(dd, 0, sizeof(*dd));
1770 return error;
1771#undef ATH_DESC_4KB_BOUND_CHECK
1772#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1773#undef DS2PHYS
1774}
1775
1776void ath_descdma_cleanup(struct ath_softc *sc,
1777 struct ath_descdma *dd,
1778 struct list_head *head)
1779{
f5870acb 1780 pci_free_consistent(to_pci_dev(sc->dev),
ff37e337
S		 1781 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1782
1783 INIT_LIST_HEAD(head);
1784 kfree(dd->dd_bufptr);
1785 memset(dd, 0, sizeof(*dd));
1786}
1787
1788int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1789{
1790 int qnum;
1791
1792 switch (queue) {
1793 case 0:
b77f483f 1794 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1795 break;
1796 case 1:
b77f483f 1797 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1798 break;
1799 case 2:
b77f483f 1800 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1801 break;
1802 case 3:
b77f483f 1803 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1804 break;
1805 default:
b77f483f 1806 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1807 break;
1808 }
1809
1810 return qnum;
1811}
1812
1813int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1814{
1815 int qnum;
1816
1817 switch (queue) {
1818 case ATH9K_WME_AC_VO:
1819 qnum = 0;
1820 break;
1821 case ATH9K_WME_AC_VI:
1822 qnum = 1;
1823 break;
1824 case ATH9K_WME_AC_BE:
1825 qnum = 2;
1826 break;
1827 case ATH9K_WME_AC_BK:
1828 qnum = 3;
1829 break;
1830 default:
1831 qnum = -1;
1832 break;
1833 }
1834
1835 return qnum;
1836}
1837
1838/**********************/
1839/* mac80211 callbacks */
1840/**********************/
1841
8feceb67 1842static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR		 1843{
1844 struct ath_softc *sc = hw->priv;
8feceb67 1845 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1846 struct ath9k_channel *init_channel;
ae8d2858 1847 int r, pos;
f078f209 1848
04bd4638
S		 1849 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1850 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1851
8feceb67 1852 /* setup initial channel */
f078f209 1853
8feceb67
VT		 1854 pos = ath_get_channel(sc, curchan);
1855 if (pos == -1) {
04bd4638 1856 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
ae8d2858 1857 return -EINVAL;
f078f209
LR		 1858 }
1859
99405f93 1860 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
8feceb67
VT		 1861 sc->sc_ah->ah_channels[pos].chanmode =
1862 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
ff37e337
S		 1863 init_channel = &sc->sc_ah->ah_channels[pos];
1864
1865 /* Reset SERDES registers */
1866 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1867
1868 /*
1869 * The basic interface to setting the hardware in a good
1870 * state is ``reset''. On return the hardware is known to
1871 * be powered up and with interrupts disabled. This must
1872 * be followed by initialization of the appropriate bits
1873 * and then setup of the interrupt mask.
1874 */
1875 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1876 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1877 if (r) {
ff37e337 1878 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1879 "Unable to reset hardware; reset status %u "
1880 "(freq %u MHz)\n", r,
1881 curchan->center_freq);
ff37e337 1882 spin_unlock_bh(&sc->sc_resetlock);
ae8d2858 1883 return r;
ff37e337
S		 1884 }
1885 spin_unlock_bh(&sc->sc_resetlock);
1886
1887 /*
1888 * This is needed only to setup initial state
1889 * but it's best done after a reset.
1890 */
1891 ath_update_txpow(sc);
8feceb67 1892
ff37e337
S		 1893 /*
1894 * Setup the hardware after reset:
1895 * The receive engine is set going.
1896 * Frame transmit is handled entirely
1897 * in the frame output path; there's nothing to do
1898 * here except setup the interrupt mask.
1899 */
1900 if (ath_startrecv(sc) != 0) {
8feceb67 1901 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1902 "Unable to start recv logic\n");
ae8d2858 1903 return -EIO;
f078f209 1904 }
8feceb67 1905
ff37e337
S		 1906 /* Setup our intr mask. */
1907 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1908 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1909 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1910
1911 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1912 sc->sc_imask |= ATH9K_INT_GTT;
1913
1914 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1915 sc->sc_imask |= ATH9K_INT_CST;
1916
1917 /*
1918 * Enable MIB interrupts when there are hardware phy counters.
1919 * Note we only do this (at the moment) for station mode.
1920 */
1921 if (ath9k_hw_phycounters(sc->sc_ah) &&
d97809db
CM		 1922 ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1923 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
ff37e337
S		 1924 sc->sc_imask |= ATH9K_INT_MIB;
1925 /*
1926 * Some hardware processes the TIM IE and fires an
1927 * interrupt when the TIM bit is set. For hardware
1928 * that does, if not overridden by configuration,
1929 * enable the TIM interrupt when operating as station.
1930 */
1931 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
d97809db 1932 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
ff37e337
S		 1933 !sc->sc_config.swBeaconProcess)
1934 sc->sc_imask |= ATH9K_INT_TIM;
1935
ce111bad 1936 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1937
1938 sc->sc_flags &= ~SC_OP_INVALID;
1939
1940 /* Disable BMISS interrupt when we're not associated */
1941 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1942 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1943
1944 ieee80211_wake_queues(sc->hw);
1945
e97275cb 1946#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 1947 r = ath_start_rfkill_poll(sc);
500c064d 1948#endif
ae8d2858 1949 return r;
f078f209
LR		 1950}
1951
8feceb67
VT		 1952static int ath9k_tx(struct ieee80211_hw *hw,
1953 struct sk_buff *skb)
f078f209 1954{
528f0c6b 1955 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 1956 struct ath_softc *sc = hw->priv;
528f0c6b 1957 struct ath_tx_control txctl;
8feceb67 1958 int hdrlen, padsize;
528f0c6b
S		 1959
1960 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 1961
8feceb67
VT		 1962 /*
1963 * As a temporary workaround, assign seq# here; this will likely need
1964 * to be cleaned up to work better with Beacon transmission and virtual
1965 * BSSes.
1966 */
1967 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1968 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1969 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 1970 sc->tx.seq_no += 0x10;
8feceb67 1971 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 1972 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 1973 }
f078f209 1974
8feceb67
VT		 1975 /* Add the padding after the header if this is not already done */
1976 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1977 if (hdrlen & 3) {
1978 padsize = hdrlen % 4;
1979 if (skb_headroom(skb) < padsize)
1980 return -1;
1981 skb_push(skb, padsize);
1982 memmove(skb->data, skb->data + padsize, hdrlen);
1983 }
1984
528f0c6b
S		 1985 /* Check if a tx queue is available */
1986
1987 txctl.txq = ath_test_get_txq(sc, skb);
1988 if (!txctl.txq)
1989 goto exit;
1990
04bd4638 1991 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1992
528f0c6b 1993 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 1994 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1995 goto exit;
8feceb67
VT		 1996 }
1997
528f0c6b
S		 1998 return 0;
1999exit:
2000 dev_kfree_skb_any(skb);
8feceb67 2001 return 0;
f078f209
LR		 2002}
2003
8feceb67 2004static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR		 2005{
2006 struct ath_softc *sc = hw->priv;
f078f209 2007
9c84b797 2008 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2009 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2010 return;
2011 }
8feceb67 2012
04bd4638 2013 DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
ff37e337
S		 2014
2015 ieee80211_stop_queues(sc->hw);
2016
2017 /* make sure h/w will not generate any interrupt
2018 * before setting the invalid flag. */
2019 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2020
2021 if (!(sc->sc_flags & SC_OP_INVALID)) {
2022 ath_draintxq(sc, false);
2023 ath_stoprecv(sc);
2024 ath9k_hw_phy_disable(sc->sc_ah);
2025 } else
b77f483f 2026 sc->rx.rxlink = NULL;
ff37e337
S		 2027
2028#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2029 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2030 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2031#endif
2032 /* disable HAL and put h/w to sleep */
2033 ath9k_hw_disable(sc->sc_ah);
2034 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2035
2036 sc->sc_flags |= SC_OP_INVALID;
500c064d 2037
04bd4638 2038 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2039}
2040
8feceb67
VT		 2041static int ath9k_add_interface(struct ieee80211_hw *hw,
2042 struct ieee80211_if_init_conf *conf)
f078f209
LR		 2043{
2044 struct ath_softc *sc = hw->priv;
5640b08e 2045 struct ath_vap *avp = (void *)conf->vif->drv_priv;
d97809db 2046 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
f078f209 2047
8feceb67
VT		 2048 /* Support only vap for now */
2049
2050 if (sc->sc_nvaps)
2051 return -ENOBUFS;
2052
2053 switch (conf->type) {
05c914fe 2054 case NL80211_IFTYPE_STATION:
d97809db 2055 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2056 break;
05c914fe 2057 case NL80211_IFTYPE_ADHOC:
d97809db 2058 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2059 break;
05c914fe 2060 case NL80211_IFTYPE_AP:
d97809db 2061 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR		 2062 break;
2063 default:
2064 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2065 "Interface type %d not yet supported\n", conf->type);
8feceb67 2066 return -EOPNOTSUPP;
f078f209
LR		 2067 }
2068
04bd4638 2069 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
8feceb67 2070
5640b08e
S		 2071 /* Set the VAP opmode */
2072 avp->av_opmode = ic_opmode;
2073 avp->av_bslot = -1;
2074
d97809db 2075 if (ic_opmode == NL80211_IFTYPE_AP)
5640b08e
S		 2076 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2077
2078 sc->sc_vaps[0] = conf->vif;
2079 sc->sc_nvaps++;
2080
2081 /* Set the device opmode */
2082 sc->sc_ah->ah_opmode = ic_opmode;
2083
6f255425
LR		 2084 if (conf->type == NL80211_IFTYPE_AP) {
2085 /* TODO: is this a suitable place to start ANI for AP mode? */
2086 /* Start ANI */
2087 mod_timer(&sc->sc_ani.timer,
2088 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2089 }
2090
8feceb67 2091 return 0;
f078f209
LR		 2092}
2093
8feceb67
VT		 2094static void ath9k_remove_interface(struct ieee80211_hw *hw,
2095 struct ieee80211_if_init_conf *conf)
f078f209 2096{
8feceb67 2097 struct ath_softc *sc = hw->priv;
5640b08e 2098 struct ath_vap *avp = (void *)conf->vif->drv_priv;
f078f209 2099
04bd4638 2100 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2101
6f255425
LR		 2102 /* Stop ANI */
2103 del_timer_sync(&sc->sc_ani.timer);
580f0b8a 2104
8feceb67 2105 /* Reclaim beacon resources */
d97809db
CM		 2106 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2107 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2108 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2109 ath_beacon_return(sc, avp);
580f0b8a 2110 }
f078f209 2111
8feceb67 2112 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2113
5640b08e
S		 2114 sc->sc_vaps[0] = NULL;
2115 sc->sc_nvaps--;
f078f209
LR		 2116}
2117
e8975581 2118static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2119{
8feceb67 2120 struct ath_softc *sc = hw->priv;
e8975581 2121 struct ieee80211_conf *conf = &hw->conf;
f078f209 2122
aa33de09 2123 mutex_lock(&sc->mutex);
4797938c 2124 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93
S		 2125 struct ieee80211_channel *curchan = hw->conf.channel;
2126 int pos;
ae5eb026 2127
04bd4638
S		 2128 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2129 curchan->center_freq);
f078f209 2130
99405f93
S		 2131 pos = ath_get_channel(sc, curchan);
2132 if (pos == -1) {
04bd4638
S		 2133 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2134 curchan->center_freq);
aa33de09 2135 mutex_unlock(&sc->mutex);
99405f93
S		 2136 return -EINVAL;
2137 }
f078f209 2138
99405f93 2139 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
8feceb67 2140 sc->sc_ah->ah_channels[pos].chanmode =
99405f93
S		 2141 (curchan->band == IEEE80211_BAND_2GHZ) ?
2142 CHANNEL_G : CHANNEL_A;
2143
ecf70441
LR		 2144 if (conf_is_ht(conf)) {
2145 if (conf_is_ht40(conf))
094d05dc 2146 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
e11602b7
S		 2147
2148 sc->sc_ah->ah_channels[pos].chanmode =
2149 ath_get_extchanmode(sc, curchan,
4797938c 2150 conf->channel_type);
e11602b7
S		 2151 }
2152
ecf70441 2153 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2154
e11602b7 2155 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
04bd4638 2156 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2157 mutex_unlock(&sc->mutex);
e11602b7
S		 2158 return -EINVAL;
2159 }
094d05dc 2160 }
f078f209 2161
5c020dc6
LR		 2162 if (changed & IEEE80211_CONF_CHANGE_POWER)
2163 sc->sc_config.txpowlimit = 2 * conf->power_level;
f078f209 2164
aa33de09 2165 mutex_unlock(&sc->mutex);
f078f209
LR		 2166 return 0;
2167}
2168
8feceb67
VT		 2169static int ath9k_config_interface(struct ieee80211_hw *hw,
2170 struct ieee80211_vif *vif,
2171 struct ieee80211_if_conf *conf)
c83be688 2172{
8feceb67
VT		 2173 struct ath_softc *sc = hw->priv;
2174 struct ath_hal *ah = sc->sc_ah;
5640b08e 2175 struct ath_vap *avp = (void *)vif->drv_priv;
8feceb67
VT		 2176 u32 rfilt = 0;
2177 int error, i;
c83be688 2178
8feceb67
VT		 2179 /* TODO: Need to decide which hw opmode to use for multi-interface
2180 * cases */
05c914fe 2181 if (vif->type == NL80211_IFTYPE_AP &&
d97809db
CM		 2182 ah->ah_opmode != NL80211_IFTYPE_AP) {
2183 ah->ah_opmode = NL80211_IFTYPE_STATION;
8feceb67
VT		 2184 ath9k_hw_setopmode(ah);
2185 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2186 /* Request full reset to get hw opmode changed properly */
2187 sc->sc_flags |= SC_OP_FULL_RESET;
2188 }
c83be688 2189
8feceb67
VT		 2190 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2191 !is_zero_ether_addr(conf->bssid)) {
2192 switch (vif->type) {
05c914fe
JB		 2193 case NL80211_IFTYPE_STATION:
2194 case NL80211_IFTYPE_ADHOC:
8feceb67
VT		 2195 /* Set BSSID */
2196 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2197 sc->sc_curaid = 0;
2198 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2199 sc->sc_curaid);
c83be688 2200
8feceb67
VT		 2201 /* Set aggregation protection mode parameters */
2202 sc->sc_config.ath_aggr_prot = 0;
c83be688 2203
8feceb67 2204 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638
S		 2205 "RX filter 0x%x bssid %pM aid 0x%x\n",
2206 rfilt, sc->sc_curbssid, sc->sc_curaid);
c83be688 2207
8feceb67
VT		 2208 /* need to reconfigure the beacon */
2209 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2210
8feceb67
VT		 2211 break;
2212 default:
2213 break;
2214 }
2215 }
c83be688 2216
8feceb67 2217 if ((conf->changed & IEEE80211_IFCC_BEACON) &&
05c914fe
JB		 2218 ((vif->type == NL80211_IFTYPE_ADHOC) ||
2219 (vif->type == NL80211_IFTYPE_AP))) {
8feceb67
VT		 2220 /*
2221 * Allocate and setup the beacon frame.
2222 *
2223 * Stop any previous beacon DMA. This may be
2224 * necessary, for example, when an ibss merge
2225 * causes reconfiguration; we may be called
2226 * with beacon transmission active.
2227 */
b77f483f 2228 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2229
8feceb67
VT		 2230 error = ath_beacon_alloc(sc, 0);
2231 if (error != 0)
2232 return error;
c83be688 2233
8feceb67
VT		 2234 ath_beacon_sync(sc, 0);
2235 }
c83be688 2236
8feceb67 2237 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2238 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2239 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2240 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2241 ath9k_hw_keysetmac(sc->sc_ah,
2242 (u16)i,
2243 sc->sc_curbssid);
2244 }
c83be688 2245
8feceb67 2246 /* Only legacy IBSS for now */
05c914fe 2247 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2248 ath_update_chainmask(sc, 0);
f078f209 2249
8feceb67
VT		 2250 return 0;
2251}
f078f209 2252
8feceb67
VT		 2253#define SUPPORTED_FILTERS \
2254 (FIF_PROMISC_IN_BSS | \
2255 FIF_ALLMULTI | \
2256 FIF_CONTROL | \
2257 FIF_OTHER_BSS | \
2258 FIF_BCN_PRBRESP_PROMISC | \
2259 FIF_FCSFAIL)
c83be688 2260
8feceb67
VT		 2261/* FIXME: sc->sc_full_reset ? */
2262static void ath9k_configure_filter(struct ieee80211_hw *hw,
2263 unsigned int changed_flags,
2264 unsigned int *total_flags,
2265 int mc_count,
2266 struct dev_mc_list *mclist)
2267{
2268 struct ath_softc *sc = hw->priv;
2269 u32 rfilt;
f078f209 2270
8feceb67
VT		 2271 changed_flags &= SUPPORTED_FILTERS;
2272 *total_flags &= SUPPORTED_FILTERS;
f078f209 2273
b77f483f 2274 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2275 rfilt = ath_calcrxfilter(sc);
2276 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2277
8feceb67
VT		 2278 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2279 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2280 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2281 }
f078f209 2282
b77f483f 2283 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2284}
f078f209 2285
8feceb67
VT		 2286static void ath9k_sta_notify(struct ieee80211_hw *hw,
2287 struct ieee80211_vif *vif,
2288 enum sta_notify_cmd cmd,
17741cdc 2289 struct ieee80211_sta *sta)
8feceb67
VT		 2290{
2291 struct ath_softc *sc = hw->priv;
f078f209 2292
8feceb67
VT		 2293 switch (cmd) {
2294 case STA_NOTIFY_ADD:
5640b08e 2295 ath_node_attach(sc, sta);
8feceb67
VT		 2296 break;
2297 case STA_NOTIFY_REMOVE:
b5aa9bf9 2298 ath_node_detach(sc, sta);
8feceb67
VT		 2299 break;
2300 default:
2301 break;
2302 }
f078f209
LR		 2303}
2304
8feceb67
VT		 2305static int ath9k_conf_tx(struct ieee80211_hw *hw,
2306 u16 queue,
2307 const struct ieee80211_tx_queue_params *params)
f078f209 2308{
8feceb67
VT		 2309 struct ath_softc *sc = hw->priv;
2310 struct ath9k_tx_queue_info qi;
2311 int ret = 0, qnum;
f078f209 2312
8feceb67
VT		 2313 if (queue >= WME_NUM_AC)
2314 return 0;
f078f209 2315
8feceb67
VT		 2316 qi.tqi_aifs = params->aifs;
2317 qi.tqi_cwmin = params->cw_min;
2318 qi.tqi_cwmax = params->cw_max;
2319 qi.tqi_burstTime = params->txop;
2320 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2321
8feceb67 2322 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2323 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2324 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2325 queue, qnum, params->aifs, params->cw_min,
2326 params->cw_max, params->txop);
f078f209 2327
8feceb67
VT		 2328 ret = ath_txq_update(sc, qnum, &qi);
2329 if (ret)
04bd4638 2330 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2331
8feceb67
VT		 2332 return ret;
2333}
f078f209 2334
8feceb67
VT		 2335static int ath9k_set_key(struct ieee80211_hw *hw,
2336 enum set_key_cmd cmd,
dc822b5d
JB		 2337 struct ieee80211_vif *vif,
2338 struct ieee80211_sta *sta,
8feceb67
VT		 2339 struct ieee80211_key_conf *key)
2340{
2341 struct ath_softc *sc = hw->priv;
2342 int ret = 0;
f078f209 2343
04bd4638 2344 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2345
8feceb67
VT		 2346 switch (cmd) {
2347 case SET_KEY:
dc822b5d 2348 ret = ath_key_config(sc, sta, key);
6ace2891
JM		 2349 if (ret >= 0) {
2350 key->hw_key_idx = ret;
8feceb67
VT		 2351 /* push IV and Michael MIC generation to stack */
2352 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2353 if (key->alg == ALG_TKIP)
2354 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2355 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2356 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2357 ret = 0;
8feceb67
VT		 2358 }
2359 break;
2360 case DISABLE_KEY:
2361 ath_key_delete(sc, key);
8feceb67
VT		 2362 break;
2363 default:
2364 ret = -EINVAL;
2365 }
f078f209 2366
8feceb67
VT		 2367 return ret;
2368}
f078f209 2369
8feceb67
VT		 2370static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2371 struct ieee80211_vif *vif,
2372 struct ieee80211_bss_conf *bss_conf,
2373 u32 changed)
2374{
2375 struct ath_softc *sc = hw->priv;
f078f209 2376
8feceb67 2377 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2378 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2379 bss_conf->use_short_preamble);
2380 if (bss_conf->use_short_preamble)
2381 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2382 else
2383 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2384 }
f078f209 2385
8feceb67 2386 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2387 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2388 bss_conf->use_cts_prot);
2389 if (bss_conf->use_cts_prot &&
2390 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2391 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2392 else
2393 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2394 }
f078f209 2395
8feceb67 2396 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2397 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2398 bss_conf->assoc);
5640b08e 2399 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67
VT		 2400 }
2401}
f078f209 2402
8feceb67
VT		 2403static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2404{
2405 u64 tsf;
2406 struct ath_softc *sc = hw->priv;
2407 struct ath_hal *ah = sc->sc_ah;
f078f209 2408
8feceb67 2409 tsf = ath9k_hw_gettsf64(ah);
f078f209 2410
8feceb67
VT		 2411 return tsf;
2412}
f078f209 2413
8feceb67
VT		 2414static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2415{
2416 struct ath_softc *sc = hw->priv;
2417 struct ath_hal *ah = sc->sc_ah;
c83be688 2418
8feceb67
VT		 2419 ath9k_hw_reset_tsf(ah);
2420}
f078f209 2421
8feceb67
VT		 2422static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2423 enum ieee80211_ampdu_mlme_action action,
17741cdc
JB		 2424 struct ieee80211_sta *sta,
2425 u16 tid, u16 *ssn)
8feceb67
VT		 2426{
2427 struct ath_softc *sc = hw->priv;
2428 int ret = 0;
f078f209 2429
8feceb67
VT		 2430 switch (action) {
2431 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2432 if (!(sc->sc_flags & SC_OP_RXAGGR))
2433 ret = -ENOTSUPP;
8feceb67
VT		 2434 break;
2435 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2436 break;
2437 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2438 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2439 if (ret < 0)
2440 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2441 "Unable to start TX aggregation\n");
8feceb67 2442 else
17741cdc 2443 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2444 break;
2445 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2446 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2447 if (ret < 0)
2448 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2449 "Unable to stop TX aggregation\n");
f078f209 2450
17741cdc 2451 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2452 break;
8469cdef
S		 2453 case IEEE80211_AMPDU_TX_RESUME:
2454 ath_tx_aggr_resume(sc, sta, tid);
2455 break;
8feceb67 2456 default:
04bd4638 2457 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2458 }
2459
2460 return ret;
f078f209
LR		 2461}
2462
8feceb67
VT		 2463static struct ieee80211_ops ath9k_ops = {
2464 .tx = ath9k_tx,
2465 .start = ath9k_start,
2466 .stop = ath9k_stop,
2467 .add_interface = ath9k_add_interface,
2468 .remove_interface = ath9k_remove_interface,
2469 .config = ath9k_config,
2470 .config_interface = ath9k_config_interface,
2471 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2472 .sta_notify = ath9k_sta_notify,
2473 .conf_tx = ath9k_conf_tx,
8feceb67 2474 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2475 .set_key = ath9k_set_key,
8feceb67
VT		 2476 .get_tsf = ath9k_get_tsf,
2477 .reset_tsf = ath9k_reset_tsf,
4233df6b 2478 .ampdu_action = ath9k_ampdu_action,
8feceb67
VT		 2479};
2480
392dff83
BP		 2481static struct {
2482 u32 version;
2483 const char * name;
2484} ath_mac_bb_names[] = {
2485 { AR_SREV_VERSION_5416_PCI, "5416" },
2486 { AR_SREV_VERSION_5416_PCIE, "5418" },
2487 { AR_SREV_VERSION_9100, "9100" },
2488 { AR_SREV_VERSION_9160, "9160" },
2489 { AR_SREV_VERSION_9280, "9280" },
2490 { AR_SREV_VERSION_9285, "9285" }
2491};
2492
2493static struct {
2494 u16 version;
2495 const char * name;
2496} ath_rf_names[] = {
2497 { 0, "5133" },
2498 { AR_RAD5133_SREV_MAJOR, "5133" },
2499 { AR_RAD5122_SREV_MAJOR, "5122" },
2500 { AR_RAD2133_SREV_MAJOR, "2133" },
2501 { AR_RAD2122_SREV_MAJOR, "2122" }
2502};
2503
2504/*
2505 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2506 */
392dff83
BP		 2507static const char *
2508ath_mac_bb_name(u32 mac_bb_version)
2509{
2510 int i;
2511
2512 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2513 if (ath_mac_bb_names[i].version == mac_bb_version) {
2514 return ath_mac_bb_names[i].name;
2515 }
2516 }
2517
2518 return "????";
2519}
2520
2521/*
2522 * Return the RF name. "????" is returned if the RF is unknown.
2523 */
392dff83
BP		 2524static const char *
2525ath_rf_name(u16 rf_version)
2526{
2527 int i;
2528
2529 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2530 if (ath_rf_names[i].version == rf_version) {
2531 return ath_rf_names[i].name;
2532 }
2533 }
2534
2535 return "????";
2536}
2537
f078f209
LR		 2538static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2539{
2540 void __iomem *mem;
2541 struct ath_softc *sc;
2542 struct ieee80211_hw *hw;
f078f209
LR		 2543 u8 csz;
2544 u32 val;
2545 int ret = 0;
392dff83 2546 struct ath_hal *ah;
f078f209
LR		 2547
2548 if (pci_enable_device(pdev))
2549 return -EIO;
2550
97b777db
LR		 2551 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2552
2553 if (ret) {
1d450cfc 2554 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
97b777db
LR		 2555 goto bad;
2556 }
2557
2558 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2559
2560 if (ret) {
2561 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
04bd4638 2562 "DMA enable failed\n");
f078f209
LR		 2563 goto bad;
2564 }
2565
2566 /*
2567 * Cache line size is used to size and align various
2568 * structures used to communicate with the hardware.
2569 */
2570 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2571 if (csz == 0) {
2572 /*
2573 * Linux 2.4.18 (at least) writes the cache line size
2574 * register as a 16-bit wide register which is wrong.
2575 * We must have this setup properly for rx buffer
2576 * DMA to work so force a reasonable value here if it
2577 * comes up zero.
2578 */
2579 csz = L1_CACHE_BYTES / sizeof(u32);
2580 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2581 }
2582 /*
2583 * The default setting of latency timer yields poor results,
2584 * set it to the value used by other systems. It may be worth
2585 * tweaking this setting more.
2586 */
2587 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2588
2589 pci_set_master(pdev);
2590
2591 /*
2592 * Disable the RETRY_TIMEOUT register (0x41) to keep
2593 * PCI Tx retries from interfering with C3 CPU state.
2594 */
2595 pci_read_config_dword(pdev, 0x40, &val);
2596 if ((val & 0x0000ff00) != 0)
2597 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2598
2599 ret = pci_request_region(pdev, 0, "ath9k");
2600 if (ret) {
2601 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2602 ret = -ENODEV;
2603 goto bad;
2604 }
2605
2606 mem = pci_iomap(pdev, 0, 0);
2607 if (!mem) {
2608 printk(KERN_ERR "PCI memory map error\n") ;
2609 ret = -EIO;
2610 goto bad1;
2611 }
2612
2613 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2614 if (hw == NULL) {
2615 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2616 goto bad2;
2617 }
2618
f078f209
LR		 2619 SET_IEEE80211_DEV(hw, &pdev->dev);
2620 pci_set_drvdata(pdev, hw);
2621
2622 sc = hw->priv;
2623 sc->hw = hw;
f5870acb 2624 sc->dev = &pdev->dev;
f078f209
LR		 2625 sc->mem = mem;
2626
2627 if (ath_attach(id->device, sc) != 0) {
2628 ret = -ENODEV;
2629 goto bad3;
2630 }
2631
2632 /* setup interrupt service routine */
2633
2634 if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2635 printk(KERN_ERR "%s: request_irq failed\n",
2636 wiphy_name(hw->wiphy));
2637 ret = -EIO;
2638 goto bad4;
2639 }
2640
392dff83
BP		 2641 ah = sc->sc_ah;
2642 printk(KERN_INFO
2643 "%s: Atheros AR%s MAC/BB Rev:%x "
2644 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
f078f209 2645 wiphy_name(hw->wiphy),
392dff83
BP		 2646 ath_mac_bb_name(ah->ah_macVersion),
2647 ah->ah_macRev,
2648 ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2649 ah->ah_phyRev,
f078f209
LR		 2650 (unsigned long)mem, pdev->irq);
2651
2652 return 0;
2653bad4:
2654 ath_detach(sc);
2655bad3:
2656 ieee80211_free_hw(hw);
2657bad2:
2658 pci_iounmap(pdev, mem);
2659bad1:
2660 pci_release_region(pdev, 0);
2661bad:
2662 pci_disable_device(pdev);
2663 return ret;
2664}
2665
2666static void ath_pci_remove(struct pci_dev *pdev)
2667{
2668 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2669 struct ath_softc *sc = hw->priv;
2670
f078f209 2671 ath_detach(sc);
9c84b797
S		 2672 if (pdev->irq)
2673 free_irq(pdev->irq, sc);
f078f209
LR		 2674 pci_iounmap(pdev, sc->mem);
2675 pci_release_region(pdev, 0);
2676 pci_disable_device(pdev);
2677 ieee80211_free_hw(hw);
2678}
2679
2680#ifdef CONFIG_PM
2681
2682static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2683{
c83be688
VT		 2684 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2685 struct ath_softc *sc = hw->priv;
2686
2687 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
500c064d 2688
e97275cb 2689#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 2690 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2691 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2692#endif
2693
f078f209
LR		 2694 pci_save_state(pdev);
2695 pci_disable_device(pdev);
07e74348 2696 pci_set_power_state(pdev, PCI_D3hot);
f078f209
LR		 2697
2698 return 0;
2699}
2700
2701static int ath_pci_resume(struct pci_dev *pdev)
2702{
c83be688
VT		 2703 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2704 struct ath_softc *sc = hw->priv;
f078f209
LR		 2705 u32 val;
2706 int err;
2707
2708 err = pci_enable_device(pdev);
2709 if (err)
2710 return err;
2711 pci_restore_state(pdev);
2712 /*
2713 * Suspend/Resume resets the PCI configuration space, so we have to
2714 * re-disable the RETRY_TIMEOUT register (0x41) to keep
2715 * PCI Tx retries from interfering with C3 CPU state
2716 */
2717 pci_read_config_dword(pdev, 0x40, &val);
2718 if ((val & 0x0000ff00) != 0)
2719 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2720
c83be688
VT		 2721 /* Enable LED */
2722 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2723 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2724 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2725
e97275cb 2726#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 2727 /*
2728 * check the h/w rfkill state on resume
2729 * and start the rfkill poll timer
2730 */
2731 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2732 queue_delayed_work(sc->hw->workqueue,
2733 &sc->rf_kill.rfkill_poll, 0);
2734#endif
2735
f078f209
LR		 2736 return 0;
2737}
2738
2739#endif /* CONFIG_PM */
2740
2741MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2742
2743static struct pci_driver ath_pci_driver = {
2744 .name = "ath9k",
2745 .id_table = ath_pci_id_table,
2746 .probe = ath_pci_probe,
2747 .remove = ath_pci_remove,
2748#ifdef CONFIG_PM
2749 .suspend = ath_pci_suspend,
2750 .resume = ath_pci_resume,
2751#endif /* CONFIG_PM */
2752};
2753
2754static int __init init_ath_pci(void)
2755{
ca8a8560
VT		 2756 int error;
2757
f078f209
LR		 2758 printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2759
ca8a8560
VT		 2760 /* Register rate control algorithm */
2761 error = ath_rate_control_register();
2762 if (error != 0) {
2763 printk(KERN_ERR
2764 "Unable to register rate control algorithm: %d\n",
2765 error);
2766 ath_rate_control_unregister();
2767 return error;
2768 }
2769
f078f209
LR		 2770 if (pci_register_driver(&ath_pci_driver) < 0) {
2771 printk(KERN_ERR
2772 "ath_pci: No devices found, driver not installed.\n");
ca8a8560 2773 ath_rate_control_unregister();
f078f209
LR		 2774 pci_unregister_driver(&ath_pci_driver);
2775 return -ENODEV;
2776 }
2777
2778 return 0;
2779}
2780module_init(init_ath_pci);
2781
2782static void __exit exit_ath_pci(void)
2783{
ca8a8560 2784 ath_rate_control_unregister();
f078f209 2785 pci_unregister_driver(&ath_pci_driver);
04bd4638 2786 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209
LR		 2787}
2788module_exit(exit_ath_pci);
Linux kernel - Deliverables
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