Commit | Line | Data |
---|---|---|
6baff7f9 GJ |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/nl80211.h> | |
18 | #include <linux/pci.h> | |
19 | #include "core.h" | |
20 | #include "reg.h" | |
21 | #include "hw.h" | |
22 | ||
23 | static struct pci_device_id ath_pci_id_table[] __devinitdata = { | |
24 | { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ | |
25 | { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ | |
26 | { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ | |
27 | { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ | |
28 | { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ | |
29 | { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */ | |
30 | { 0 } | |
31 | }; | |
32 | ||
33 | /* return bus cachesize in 4B word units */ | |
34 | static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz) | |
35 | { | |
36 | u8 u8tmp; | |
37 | ||
38 | pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, | |
39 | (u8 *)&u8tmp); | |
40 | *csz = (int)u8tmp; | |
41 | ||
42 | /* | |
43 | * This check was put in to avoid "unplesant" consequences if | |
44 | * the bootrom has not fully initialized all PCI devices. | |
45 | * Sometimes the cache line size register is not set | |
46 | */ | |
47 | ||
48 | if (*csz == 0) | |
49 | *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ | |
50 | } | |
51 | ||
52 | static void ath_pci_cleanup(struct ath_softc *sc) | |
53 | { | |
54 | struct pci_dev *pdev = to_pci_dev(sc->dev); | |
55 | ||
56 | pci_iounmap(pdev, sc->mem); | |
57 | pci_release_region(pdev, 0); | |
58 | pci_disable_device(pdev); | |
59 | } | |
60 | ||
61 | static struct ath_bus_ops ath_pci_bus_ops = { | |
62 | .read_cachesize = ath_pci_read_cachesize, | |
63 | .cleanup = ath_pci_cleanup, | |
64 | }; | |
65 | ||
66 | static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
67 | { | |
68 | void __iomem *mem; | |
69 | struct ath_softc *sc; | |
70 | struct ieee80211_hw *hw; | |
71 | u8 csz; | |
72 | u32 val; | |
73 | int ret = 0; | |
74 | struct ath_hal *ah; | |
75 | ||
76 | if (pci_enable_device(pdev)) | |
77 | return -EIO; | |
78 | ||
79 | ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
80 | ||
81 | if (ret) { | |
82 | printk(KERN_ERR "ath9k: 32-bit DMA not available\n"); | |
83 | goto bad; | |
84 | } | |
85 | ||
86 | ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
87 | ||
88 | if (ret) { | |
89 | printk(KERN_ERR "ath9k: 32-bit DMA consistent " | |
90 | "DMA enable failed\n"); | |
91 | goto bad; | |
92 | } | |
93 | ||
94 | /* | |
95 | * Cache line size is used to size and align various | |
96 | * structures used to communicate with the hardware. | |
97 | */ | |
98 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); | |
99 | if (csz == 0) { | |
100 | /* | |
101 | * Linux 2.4.18 (at least) writes the cache line size | |
102 | * register as a 16-bit wide register which is wrong. | |
103 | * We must have this setup properly for rx buffer | |
104 | * DMA to work so force a reasonable value here if it | |
105 | * comes up zero. | |
106 | */ | |
107 | csz = L1_CACHE_BYTES / sizeof(u32); | |
108 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); | |
109 | } | |
110 | /* | |
111 | * The default setting of latency timer yields poor results, | |
112 | * set it to the value used by other systems. It may be worth | |
113 | * tweaking this setting more. | |
114 | */ | |
115 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); | |
116 | ||
117 | pci_set_master(pdev); | |
118 | ||
119 | /* | |
120 | * Disable the RETRY_TIMEOUT register (0x41) to keep | |
121 | * PCI Tx retries from interfering with C3 CPU state. | |
122 | */ | |
123 | pci_read_config_dword(pdev, 0x40, &val); | |
124 | if ((val & 0x0000ff00) != 0) | |
125 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | |
126 | ||
127 | ret = pci_request_region(pdev, 0, "ath9k"); | |
128 | if (ret) { | |
129 | dev_err(&pdev->dev, "PCI memory region reserve error\n"); | |
130 | ret = -ENODEV; | |
131 | goto bad; | |
132 | } | |
133 | ||
134 | mem = pci_iomap(pdev, 0, 0); | |
135 | if (!mem) { | |
136 | printk(KERN_ERR "PCI memory map error\n") ; | |
137 | ret = -EIO; | |
138 | goto bad1; | |
139 | } | |
140 | ||
141 | hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops); | |
142 | if (hw == NULL) { | |
143 | printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n"); | |
144 | goto bad2; | |
145 | } | |
146 | ||
147 | SET_IEEE80211_DEV(hw, &pdev->dev); | |
148 | pci_set_drvdata(pdev, hw); | |
149 | ||
150 | sc = hw->priv; | |
151 | sc->hw = hw; | |
152 | sc->dev = &pdev->dev; | |
153 | sc->mem = mem; | |
154 | sc->bus_ops = &ath_pci_bus_ops; | |
155 | ||
156 | if (ath_attach(id->device, sc) != 0) { | |
157 | ret = -ENODEV; | |
158 | goto bad3; | |
159 | } | |
160 | ||
161 | /* setup interrupt service routine */ | |
162 | ||
163 | if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) { | |
164 | printk(KERN_ERR "%s: request_irq failed\n", | |
165 | wiphy_name(hw->wiphy)); | |
166 | ret = -EIO; | |
167 | goto bad4; | |
168 | } | |
169 | ||
170 | sc->irq = pdev->irq; | |
171 | ||
172 | ah = sc->sc_ah; | |
173 | printk(KERN_INFO | |
174 | "%s: Atheros AR%s MAC/BB Rev:%x " | |
175 | "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n", | |
176 | wiphy_name(hw->wiphy), | |
177 | ath_mac_bb_name(ah->ah_macVersion), | |
178 | ah->ah_macRev, | |
179 | ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)), | |
180 | ah->ah_phyRev, | |
181 | (unsigned long)mem, pdev->irq); | |
182 | ||
183 | return 0; | |
184 | bad4: | |
185 | ath_detach(sc); | |
186 | bad3: | |
187 | ieee80211_free_hw(hw); | |
188 | bad2: | |
189 | pci_iounmap(pdev, mem); | |
190 | bad1: | |
191 | pci_release_region(pdev, 0); | |
192 | bad: | |
193 | pci_disable_device(pdev); | |
194 | return ret; | |
195 | } | |
196 | ||
197 | static void ath_pci_remove(struct pci_dev *pdev) | |
198 | { | |
199 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
200 | struct ath_softc *sc = hw->priv; | |
201 | ||
202 | ath_cleanup(sc); | |
203 | } | |
204 | ||
205 | #ifdef CONFIG_PM | |
206 | ||
207 | static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
208 | { | |
209 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
210 | struct ath_softc *sc = hw->priv; | |
211 | ||
212 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); | |
213 | ||
214 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) | |
215 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) | |
216 | cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); | |
217 | #endif | |
218 | ||
219 | pci_save_state(pdev); | |
220 | pci_disable_device(pdev); | |
221 | pci_set_power_state(pdev, PCI_D3hot); | |
222 | ||
223 | return 0; | |
224 | } | |
225 | ||
226 | static int ath_pci_resume(struct pci_dev *pdev) | |
227 | { | |
228 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
229 | struct ath_softc *sc = hw->priv; | |
230 | u32 val; | |
231 | int err; | |
232 | ||
233 | err = pci_enable_device(pdev); | |
234 | if (err) | |
235 | return err; | |
236 | pci_restore_state(pdev); | |
237 | /* | |
238 | * Suspend/Resume resets the PCI configuration space, so we have to | |
239 | * re-disable the RETRY_TIMEOUT register (0x41) to keep | |
240 | * PCI Tx retries from interfering with C3 CPU state | |
241 | */ | |
242 | pci_read_config_dword(pdev, 0x40, &val); | |
243 | if ((val & 0x0000ff00) != 0) | |
244 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | |
245 | ||
246 | /* Enable LED */ | |
247 | ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN, | |
248 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
249 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); | |
250 | ||
251 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) | |
252 | /* | |
253 | * check the h/w rfkill state on resume | |
254 | * and start the rfkill poll timer | |
255 | */ | |
256 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) | |
257 | queue_delayed_work(sc->hw->workqueue, | |
258 | &sc->rf_kill.rfkill_poll, 0); | |
259 | #endif | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
264 | #endif /* CONFIG_PM */ | |
265 | ||
266 | MODULE_DEVICE_TABLE(pci, ath_pci_id_table); | |
267 | ||
268 | static struct pci_driver ath_pci_driver = { | |
269 | .name = "ath9k", | |
270 | .id_table = ath_pci_id_table, | |
271 | .probe = ath_pci_probe, | |
272 | .remove = ath_pci_remove, | |
273 | #ifdef CONFIG_PM | |
274 | .suspend = ath_pci_suspend, | |
275 | .resume = ath_pci_resume, | |
276 | #endif /* CONFIG_PM */ | |
277 | }; | |
278 | ||
279 | int __init ath_pci_init(void) | |
280 | { | |
281 | return pci_register_driver(&ath_pci_driver); | |
282 | } | |
283 | ||
284 | void ath_pci_exit(void) | |
285 | { | |
286 | pci_unregister_driver(&ath_pci_driver); | |
287 | } |