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[deliverable/linux.git] / drivers / net / wireless / ath9k / xmit.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/*
18 * Implementation of transmit path.
19 */
20
21#include "core.h"
22
23#define BITS_PER_BYTE 8
24#define OFDM_PLCP_BITS 22
25#define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
26#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
27#define L_STF 8
28#define L_LTF 8
29#define L_SIG 4
30#define HT_SIG 8
31#define HT_STF 4
32#define HT_LTF(_ns) (4 * (_ns))
33#define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
34#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
35#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
36#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
37
38#define OFDM_SIFS_TIME 16
39
40static u32 bits_per_symbol[][2] = {
41 /* 20MHz 40MHz */
42 { 26, 54 }, /* 0: BPSK */
43 { 52, 108 }, /* 1: QPSK 1/2 */
44 { 78, 162 }, /* 2: QPSK 3/4 */
45 { 104, 216 }, /* 3: 16-QAM 1/2 */
46 { 156, 324 }, /* 4: 16-QAM 3/4 */
47 { 208, 432 }, /* 5: 64-QAM 2/3 */
48 { 234, 486 }, /* 6: 64-QAM 3/4 */
49 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 { 52, 108 }, /* 8: BPSK */
51 { 104, 216 }, /* 9: QPSK 1/2 */
52 { 156, 324 }, /* 10: QPSK 3/4 */
53 { 208, 432 }, /* 11: 16-QAM 1/2 */
54 { 312, 648 }, /* 12: 16-QAM 3/4 */
55 { 416, 864 }, /* 13: 64-QAM 2/3 */
56 { 468, 972 }, /* 14: 64-QAM 3/4 */
57 { 520, 1080 }, /* 15: 64-QAM 5/6 */
58};
59
60#define IS_HT_RATE(_rate) ((_rate) & 0x80)
61
f078f209
LR		 62/*
63 * Insert a chain of ath_buf (descriptors) on a txq and
64 * assume the descriptors are already chained together by caller.
65 * NB: must be called with txq lock held
66 */
67
68static void ath_tx_txqaddbuf(struct ath_softc *sc,
69 struct ath_txq *txq, struct list_head *head)
70{
71 struct ath_hal *ah = sc->sc_ah;
72 struct ath_buf *bf;
73 /*
74 * Insert the frame on the outbound list and
75 * pass it on to the hardware.
76 */
77
78 if (list_empty(head))
79 return;
80
81 bf = list_first_entry(head, struct ath_buf, list);
82
83 list_splice_tail_init(head, &txq->axq_q);
84 txq->axq_depth++;
85 txq->axq_totalqueued++;
86 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
87
88 DPRINTF(sc, ATH_DBG_QUEUE,
89 "%s: txq depth = %d\n", __func__, txq->axq_depth);
90
91 if (txq->axq_link == NULL) {
92 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
93 DPRINTF(sc, ATH_DBG_XMIT,
94 "%s: TXDP[%u] = %llx (%p)\n",
95 __func__, txq->axq_qnum,
96 ito64(bf->bf_daddr), bf->bf_desc);
97 } else {
98 *txq->axq_link = bf->bf_daddr;
99 DPRINTF(sc, ATH_DBG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
100 __func__,
101 txq->axq_qnum, txq->axq_link,
102 ito64(bf->bf_daddr), bf->bf_desc);
103 }
104 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
105 ath9k_hw_txstart(ah, txq->axq_qnum);
106}
107
108/* Get transmit rate index using rate in Kbps */
109
110static int ath_tx_findindex(const struct ath9k_rate_table *rt, int rate)
111{
112 int i;
113 int ndx = 0;
114
115 for (i = 0; i < rt->rateCount; i++) {
116 if (rt->info[i].rateKbps == rate) {
117 ndx = i;
118 break;
119 }
120 }
121
122 return ndx;
123}
124
125/* Check if it's okay to send out aggregates */
126
127static int ath_aggr_query(struct ath_softc *sc,
128 struct ath_node *an, u8 tidno)
129{
130 struct ath_atx_tid *tid;
131 tid = ATH_AN_2_TID(an, tidno);
132
133 if (tid->addba_exchangecomplete || tid->addba_exchangeinprogress)
134 return 1;
135 else
136 return 0;
137}
138
139static enum ath9k_pkt_type get_hal_packet_type(struct ieee80211_hdr *hdr)
140{
141 enum ath9k_pkt_type htype;
142 __le16 fc;
143
144 fc = hdr->frame_control;
145
146 /* Calculate Atheros packet type from IEEE80211 packet header */
147
148 if (ieee80211_is_beacon(fc))
149 htype = ATH9K_PKT_TYPE_BEACON;
150 else if (ieee80211_is_probe_resp(fc))
151 htype = ATH9K_PKT_TYPE_PROBE_RESP;
152 else if (ieee80211_is_atim(fc))
153 htype = ATH9K_PKT_TYPE_ATIM;
154 else if (ieee80211_is_pspoll(fc))
155 htype = ATH9K_PKT_TYPE_PSPOLL;
156 else
157 htype = ATH9K_PKT_TYPE_NORMAL;
158
159 return htype;
160}
161
162static void fill_min_rates(struct sk_buff *skb, struct ath_tx_control *txctl)
163{
164 struct ieee80211_hdr *hdr;
165 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
166 struct ath_tx_info_priv *tx_info_priv;
167 __le16 fc;
168
169 hdr = (struct ieee80211_hdr *)skb->data;
170 fc = hdr->frame_control;
171 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
172
173 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) {
174 txctl->use_minrate = 1;
175 txctl->min_rate = tx_info_priv->min_rate;
176 } else if (ieee80211_is_data(fc)) {
177 if (ieee80211_is_nullfunc(fc) ||
178 /* Port Access Entity (IEEE 802.1X) */
179 (skb->protocol == cpu_to_be16(0x888E))) {
180 txctl->use_minrate = 1;
181 txctl->min_rate = tx_info_priv->min_rate;
182 }
183 if (is_multicast_ether_addr(hdr->addr1))
184 txctl->mcast_rate = tx_info_priv->min_rate;
185 }
186
187}
188
189/* This function will setup additional txctl information, mostly rate stuff */
190/* FIXME: seqno, ps */
191static int ath_tx_prepare(struct ath_softc *sc,
192 struct sk_buff *skb,
193 struct ath_tx_control *txctl)
194{
195 struct ieee80211_hw *hw = sc->hw;
196 struct ieee80211_hdr *hdr;
197 struct ath_rc_series *rcs;
198 struct ath_txq *txq = NULL;
199 const struct ath9k_rate_table *rt;
200 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
201 struct ath_tx_info_priv *tx_info_priv;
202 int hdrlen;
203 u8 rix, antenna;
204 __le16 fc;
205 u8 *qc;
206
f078f209
LR		 207 txctl->dev = sc;
208 hdr = (struct ieee80211_hdr *)skb->data;
209 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
210 fc = hdr->frame_control;
211
212 rt = sc->sc_currates;
213 BUG_ON(!rt);
214
215 /* Fill misc fields */
216
217 spin_lock_bh(&sc->node_lock);
218 txctl->an = ath_node_get(sc, hdr->addr1);
219 /* create a temp node, if the node is not there already */
220 if (!txctl->an)
221 txctl->an = ath_node_attach(sc, hdr->addr1, 0);
222 spin_unlock_bh(&sc->node_lock);
223
224 if (ieee80211_is_data_qos(fc)) {
225 qc = ieee80211_get_qos_ctl(hdr);
226 txctl->tidno = qc[0] & 0xf;
227 }
228
229 txctl->if_id = 0;
f078f209
LR		 230 txctl->frmlen = skb->len + FCS_LEN - (hdrlen & 3);
231 txctl->txpower = MAX_RATE_POWER; /* FIXME */
232
233 /* Fill Key related fields */
234
235 txctl->keytype = ATH9K_KEY_TYPE_CLEAR;
236 txctl->keyix = ATH9K_TXKEYIX_INVALID;
237
238 if (tx_info->control.hw_key) {
239 txctl->keyix = tx_info->control.hw_key->hw_key_idx;
76708dee 240 txctl->frmlen += tx_info->control.hw_key->icv_len;
f078f209 241
d0be7cc7 242 if (tx_info->control.hw_key->alg == ALG_WEP)
f078f209 243 txctl->keytype = ATH9K_KEY_TYPE_WEP;
d0be7cc7 244 else if (tx_info->control.hw_key->alg == ALG_TKIP)
f078f209 245 txctl->keytype = ATH9K_KEY_TYPE_TKIP;
d0be7cc7 246 else if (tx_info->control.hw_key->alg == ALG_CCMP)
f078f209
LR		 247 txctl->keytype = ATH9K_KEY_TYPE_AES;
248 }
249
250 /* Fill packet type */
251
252 txctl->atype = get_hal_packet_type(hdr);
253
254 /* Fill qnum */
255
e022edbd
JM		 256 if (unlikely(txctl->flags & ATH9K_TXDESC_CAB)) {
257 txctl->qnum = 0;
258 txq = sc->sc_cabq;
259 } else {
260 txctl->qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
261 txq = &sc->sc_txq[txctl->qnum];
262 }
f078f209
LR		 263 spin_lock_bh(&txq->axq_lock);
264
265 /* Try to avoid running out of descriptors */
e022edbd
JM		 266 if (txq->axq_depth >= (ATH_TXBUF - 20) &&
267 !(txctl->flags & ATH9K_TXDESC_CAB)) {
f078f209
LR		 268 DPRINTF(sc, ATH_DBG_FATAL,
269 "%s: TX queue: %d is full, depth: %d\n",
270 __func__,
271 txctl->qnum,
272 txq->axq_depth);
273 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
274 txq->stopped = 1;
275 spin_unlock_bh(&txq->axq_lock);
276 return -1;
277 }
278
279 spin_unlock_bh(&txq->axq_lock);
280
281 /* Fill rate */
282
283 fill_min_rates(skb, txctl);
284
285 /* Fill flags */
286
e022edbd 287 txctl->flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
f078f209
LR		 288
289 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
b14ecdd0 290 txctl->flags |= ATH9K_TXDESC_NOACK;
f078f209 291 if (tx_info->flags & IEEE80211_TX_CTL_USE_RTS_CTS)
b14ecdd0 292 txctl->flags |= ATH9K_TXDESC_RTSENA;
f078f209
LR		 293
294 /*
295 * Setup for rate calculations.
296 */
297 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
298 rcs = tx_info_priv->rcs;
299
300 if (ieee80211_is_data(fc) && !txctl->use_minrate) {
301
302 /* Enable HT only for DATA frames and not for EAPOL */
303 txctl->ht = (hw->conf.ht_conf.ht_supported &&
304 (tx_info->flags & IEEE80211_TX_CTL_AMPDU));
305
306 if (is_multicast_ether_addr(hdr->addr1)) {
307 rcs[0].rix = (u8)
308 ath_tx_findindex(rt, txctl->mcast_rate);
309
310 /*
311 * mcast packets are not re-tried.
312 */
313 rcs[0].tries = 1;
314 }
315 /* For HT capable stations, we save tidno for later use.
316 * We also override seqno set by upper layer with the one
317 * in tx aggregation state.
318 *
319 * First, the fragmentation stat is determined.
320 * If fragmentation is on, the sequence number is
321 * not overridden, since it has been
322 * incremented by the fragmentation routine.
323 */
324 if (likely(!(txctl->flags & ATH9K_TXDESC_FRAG_IS_ON)) &&
672840ac 325 txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) {
f078f209
LR		 326 struct ath_atx_tid *tid;
327
328 tid = ATH_AN_2_TID(txctl->an, txctl->tidno);
329
330 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
331 IEEE80211_SEQ_SEQ_SHIFT);
332 txctl->seqno = tid->seq_next;
333 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
334 }
335 } else {
336 /* for management and control frames,
337 * or for NULL and EAPOL frames */
338 if (txctl->min_rate)
339 rcs[0].rix = ath_rate_findrateix(sc, txctl->min_rate);
340 else
86b89eed 341 rcs[0].rix = 0;
f078f209
LR		 342 rcs[0].tries = ATH_MGT_TXMAXTRY;
343 }
344 rix = rcs[0].rix;
345
14cc709f
S		 346 if (ieee80211_has_morefrags(fc) ||
347 (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)) {
f078f209 348 /*
14cc709f
S		 349 ** Force hardware to use computed duration for next
350 ** fragment by disabling multi-rate retry, which
351 ** updates duration based on the multi-rate
352 ** duration table.
353 */
354 rcs[1].tries = rcs[2].tries = rcs[3].tries = 0;
355 rcs[1].rix = rcs[2].rix = rcs[3].rix = 0;
356 /* reset tries but keep rate index */
357 rcs[0].tries = ATH_TXMAXTRY;
f078f209
LR		 358 }
359
360 /*
361 * Determine if a tx interrupt should be generated for
362 * this descriptor. We take a tx interrupt to reap
363 * descriptors when the h/w hits an EOL condition or
364 * when the descriptor is specifically marked to generate
365 * an interrupt. We periodically mark descriptors in this
366 * way to insure timely replenishing of the supply needed
367 * for sending frames. Defering interrupts reduces system
368 * load and potentially allows more concurrent work to be
369 * done but if done to aggressively can cause senders to
370 * backup.
371 *
372 * NB: use >= to deal with sc_txintrperiod changing
373 * dynamically through sysctl.
374 */
375 spin_lock_bh(&txq->axq_lock);
376 if ((++txq->axq_intrcnt >= sc->sc_txintrperiod)) {
377 txctl->flags |= ATH9K_TXDESC_INTREQ;
378 txq->axq_intrcnt = 0;
379 }
380 spin_unlock_bh(&txq->axq_lock);
381
382 if (is_multicast_ether_addr(hdr->addr1)) {
383 antenna = sc->sc_mcastantenna + 1;
384 sc->sc_mcastantenna = (sc->sc_mcastantenna + 1) & 0x1;
98deeea0 385 }
f078f209 386
f078f209
LR		 387 return 0;
388}
389
390/* To complete a chain of buffers associated a frame */
391
392static void ath_tx_complete_buf(struct ath_softc *sc,
393 struct ath_buf *bf,
394 struct list_head *bf_q,
395 int txok, int sendbar)
396{
397 struct sk_buff *skb = bf->bf_mpdu;
398 struct ath_xmit_status tx_status;
f078f209
LR		 399
400 /*
401 * Set retry information.
402 * NB: Don't use the information in the descriptor, because the frame
403 * could be software retried.
404 */
405 tx_status.retries = bf->bf_retries;
406 tx_status.flags = 0;
407
408 if (sendbar)
409 tx_status.flags = ATH_TX_BAR;
410
411 if (!txok) {
412 tx_status.flags |= ATH_TX_ERROR;
413
cd3d39a6 414 if (bf_isxretried(bf))
f078f209
LR		 415 tx_status.flags |= ATH_TX_XRETRY;
416 }
417 /* Unmap this frame */
f078f209 418 pci_unmap_single(sc->pdev,
ff9b662d 419 bf->bf_dmacontext,
f078f209
LR		 420 skb->len,
421 PCI_DMA_TODEVICE);
422 /* complete this frame */
423 ath_tx_complete(sc, skb, &tx_status, bf->bf_node);
424
425 /*
426 * Return the list of ath_buf of this mpdu to free queue
427 */
428 spin_lock_bh(&sc->sc_txbuflock);
429 list_splice_tail_init(bf_q, &sc->sc_txbuf);
430 spin_unlock_bh(&sc->sc_txbuflock);
431}
432
433/*
434 * queue up a dest/ac pair for tx scheduling
435 * NB: must be called with txq lock held
436 */
437
438static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
439{
440 struct ath_atx_ac *ac = tid->ac;
441
442 /*
443 * if tid is paused, hold off
444 */
445 if (tid->paused)
446 return;
447
448 /*
449 * add tid to ac atmost once
450 */
451 if (tid->sched)
452 return;
453
454 tid->sched = true;
455 list_add_tail(&tid->list, &ac->tid_q);
456
457 /*
458 * add node ac to txq atmost once
459 */
460 if (ac->sched)
461 return;
462
463 ac->sched = true;
464 list_add_tail(&ac->list, &txq->axq_acq);
465}
466
467/* pause a tid */
468
469static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
470{
471 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
472
473 spin_lock_bh(&txq->axq_lock);
474
475 tid->paused++;
476
477 spin_unlock_bh(&txq->axq_lock);
478}
479
480/* resume a tid and schedule aggregate */
481
482void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
483{
484 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
485
486 ASSERT(tid->paused > 0);
487 spin_lock_bh(&txq->axq_lock);
488
489 tid->paused--;
490
491 if (tid->paused > 0)
492 goto unlock;
493
494 if (list_empty(&tid->buf_q))
495 goto unlock;
496
497 /*
498 * Add this TID to scheduler and try to send out aggregates
499 */
500 ath_tx_queue_tid(txq, tid);
501 ath_txq_schedule(sc, txq);
502unlock:
503 spin_unlock_bh(&txq->axq_lock);
504}
505
506/* Compute the number of bad frames */
507
508static int ath_tx_num_badfrms(struct ath_softc *sc,
509 struct ath_buf *bf, int txok)
510{
511 struct ath_node *an = bf->bf_node;
512 int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
513 struct ath_buf *bf_last = bf->bf_lastbf;
514 struct ath_desc *ds = bf_last->bf_desc;
515 u16 seq_st = 0;
516 u32 ba[WME_BA_BMP_SIZE >> 5];
517 int ba_index;
518 int nbad = 0;
519 int isaggr = 0;
520
521 if (isnodegone || ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
522 return 0;
523
cd3d39a6 524 isaggr = bf_isaggr(bf);
f078f209
LR		 525 if (isaggr) {
526 seq_st = ATH_DS_BA_SEQ(ds);
527 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
528 }
529
530 while (bf) {
531 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
532 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
533 nbad++;
534
535 bf = bf->bf_next;
536 }
537
538 return nbad;
539}
540
541static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
542{
543 struct sk_buff *skb;
544 struct ieee80211_hdr *hdr;
545
cd3d39a6 546 bf->bf_state.bf_type |= BUF_RETRY;
f078f209
LR		 547 bf->bf_retries++;
548
549 skb = bf->bf_mpdu;
550 hdr = (struct ieee80211_hdr *)skb->data;
551 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
552}
553
554/* Update block ack window */
555
556static void ath_tx_update_baw(struct ath_softc *sc,
557 struct ath_atx_tid *tid, int seqno)
558{
559 int index, cindex;
560
561 index = ATH_BA_INDEX(tid->seq_start, seqno);
562 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
563
564 tid->tx_buf[cindex] = NULL;
565
566 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
567 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
568 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
569 }
570}
571
572/*
573 * ath_pkt_dur - compute packet duration (NB: not NAV)
574 *
575 * rix - rate index
576 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
577 * width - 0 for 20 MHz, 1 for 40 MHz
578 * half_gi - to use 4us v/s 3.6 us for symbol time
579 */
580
581static u32 ath_pkt_duration(struct ath_softc *sc,
582 u8 rix,
583 struct ath_buf *bf,
584 int width,
585 int half_gi,
586 bool shortPreamble)
587{
588 const struct ath9k_rate_table *rt = sc->sc_currates;
589 u32 nbits, nsymbits, duration, nsymbols;
590 u8 rc;
591 int streams, pktlen;
592
cd3d39a6 593 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
f078f209
LR		 594 rc = rt->info[rix].rateCode;
595
596 /*
597 * for legacy rates, use old function to compute packet duration
598 */
599 if (!IS_HT_RATE(rc))
600 return ath9k_hw_computetxtime(sc->sc_ah,
601 rt,
602 pktlen,
603 rix,
604 shortPreamble);
605 /*
606 * find number of symbols: PLCP + data
607 */
608 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
609 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
610 nsymbols = (nbits + nsymbits - 1) / nsymbits;
611
612 if (!half_gi)
613 duration = SYMBOL_TIME(nsymbols);
614 else
615 duration = SYMBOL_TIME_HALFGI(nsymbols);
616
617 /*
618 * addup duration for legacy/ht training and signal fields
619 */
620 streams = HT_RC_2_STREAMS(rc);
621 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
622 return duration;
623}
624
625/* Rate module function to set rate related fields in tx descriptor */
626
627static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
628{
629 struct ath_hal *ah = sc->sc_ah;
630 const struct ath9k_rate_table *rt;
631 struct ath_desc *ds = bf->bf_desc;
632 struct ath_desc *lastds = bf->bf_lastbf->bf_desc;
633 struct ath9k_11n_rate_series series[4];
634 int i, flags, rtsctsena = 0, dynamic_mimops = 0;
635 u32 ctsduration = 0;
636 u8 rix = 0, cix, ctsrate = 0;
98deeea0 637 u32 aggr_limit_with_rts = ah->ah_caps.rts_aggr_limit;
f078f209
LR		 638 struct ath_node *an = (struct ath_node *) bf->bf_node;
639
640 /*
641 * get the cix for the lowest valid rix.
642 */
643 rt = sc->sc_currates;
644 for (i = 4; i--;) {
645 if (bf->bf_rcs[i].tries) {
646 rix = bf->bf_rcs[i].rix;
647 break;
648 }
649 }
650 flags = (bf->bf_flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA));
651 cix = rt->info[rix].controlRate;
652
653 /*
654 * If 802.11g protection is enabled, determine whether
655 * to use RTS/CTS or just CTS. Note that this is only
656 * done for OFDM/HT unicast frames.
657 */
658 if (sc->sc_protmode != PROT_M_NONE &&
659 (rt->info[rix].phy == PHY_OFDM ||
660 rt->info[rix].phy == PHY_HT) &&
661 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
662 if (sc->sc_protmode == PROT_M_RTSCTS)
663 flags = ATH9K_TXDESC_RTSENA;
664 else if (sc->sc_protmode == PROT_M_CTSONLY)
665 flags = ATH9K_TXDESC_CTSENA;
666
667 cix = rt->info[sc->sc_protrix].controlRate;
668 rtsctsena = 1;
669 }
670
671 /* For 11n, the default behavior is to enable RTS for
672 * hw retried frames. We enable the global flag here and
673 * let rate series flags determine which rates will actually
674 * use RTS.
675 */
cd3d39a6 676 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf_isdata(bf)) {
f078f209
LR		 677 BUG_ON(!an);
678 /*
679 * 802.11g protection not needed, use our default behavior
680 */
681 if (!rtsctsena)
682 flags = ATH9K_TXDESC_RTSENA;
683 /*
684 * For dynamic MIMO PS, RTS needs to precede the first aggregate
685 * and the second aggregate should have any protection at all.
686 */
687 if (an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) {
cd3d39a6 688 if (!bf_isaggrburst(bf)) {
f078f209
LR		 689 flags = ATH9K_TXDESC_RTSENA;
690 dynamic_mimops = 1;
691 } else {
692 flags = 0;
693 }
694 }
695 }
696
697 /*
698 * Set protection if aggregate protection on
699 */
700 if (sc->sc_config.ath_aggr_prot &&
cd3d39a6 701 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
f078f209
LR		 702 flags = ATH9K_TXDESC_RTSENA;
703 cix = rt->info[sc->sc_protrix].controlRate;
704 rtsctsena = 1;
705 }
706
707 /*
708 * For AR5416 - RTS cannot be followed by a frame larger than 8K.
709 */
cd3d39a6 710 if (bf_isaggr(bf) && (bf->bf_al > aggr_limit_with_rts)) {
f078f209
LR		 711 /*
712 * Ensure that in the case of SM Dynamic power save
713 * while we are bursting the second aggregate the
714 * RTS is cleared.
715 */
716 flags &= ~(ATH9K_TXDESC_RTSENA);
717 }
718
719 /*
720 * CTS transmit rate is derived from the transmit rate
721 * by looking in the h/w rate table. We must also factor
722 * in whether or not a short preamble is to be used.
723 */
724 /* NB: cix is set above where RTS/CTS is enabled */
725 BUG_ON(cix == 0xff);
726 ctsrate = rt->info[cix].rateCode |
cd3d39a6 727 (bf_isshpreamble(bf) ? rt->info[cix].shortPreamble : 0);
f078f209
LR		 728
729 /*
730 * Setup HAL rate series
731 */
0345f37b 732 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
f078f209
LR		 733
734 for (i = 0; i < 4; i++) {
735 if (!bf->bf_rcs[i].tries)
736 continue;
737
738 rix = bf->bf_rcs[i].rix;
739
740 series[i].Rate = rt->info[rix].rateCode |
cd3d39a6 741 (bf_isshpreamble(bf) ? rt->info[rix].shortPreamble : 0);
f078f209
LR		 742
743 series[i].Tries = bf->bf_rcs[i].tries;
744
745 series[i].RateFlags = (
746 (bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
747 ATH9K_RATESERIES_RTS_CTS : 0) |
748 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
749 ATH9K_RATESERIES_2040 : 0) |
750 ((bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG) ?
751 ATH9K_RATESERIES_HALFGI : 0);
752
753 series[i].PktDuration = ath_pkt_duration(
754 sc, rix, bf,
755 (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0,
756 (bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG),
cd3d39a6 757 bf_isshpreamble(bf));
f078f209
LR		 758
759 if ((an->an_smmode == ATH_SM_PWRSAV_STATIC) &&
760 (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG) == 0) {
761 /*
762 * When sending to an HT node that has enabled static
763 * SM/MIMO power save, send at single stream rates but
764 * use maximum allowed transmit chains per user,
765 * hardware, regulatory, or country limits for
766 * better range.
767 */
768 series[i].ChSel = sc->sc_tx_chainmask;
769 } else {
cd3d39a6 770 if (bf_isht(bf))
f078f209
LR		 771 series[i].ChSel =
772 ath_chainmask_sel_logic(sc, an);
773 else
774 series[i].ChSel = sc->sc_tx_chainmask;
775 }
776
777 if (rtsctsena)
778 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
779
780 /*
781 * Set RTS for all rates if node is in dynamic powersave
782 * mode and we are using dual stream rates.
783 */
784 if (dynamic_mimops && (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG))
785 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
786 }
787
788 /*
789 * For non-HT devices, calculate RTS/CTS duration in software
790 * and disable multi-rate retry.
791 */
60b67f51 792 if (flags && !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)) {
f078f209
LR		 793 /*
794 * Compute the transmit duration based on the frame
795 * size and the size of an ACK frame. We call into the
796 * HAL to do the computation since it depends on the
797 * characteristics of the actual PHY being used.
798 *
799 * NB: CTS is assumed the same size as an ACK so we can
800 * use the precalculated ACK durations.
801 */
802 if (flags & ATH9K_TXDESC_RTSENA) { /* SIFS + CTS */
cd3d39a6 803 ctsduration += bf_isshpreamble(bf) ?
f078f209
LR		 804 rt->info[cix].spAckDuration :
805 rt->info[cix].lpAckDuration;
806 }
807
808 ctsduration += series[0].PktDuration;
809
810 if ((bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { /* SIFS + ACK */
cd3d39a6 811 ctsduration += bf_isshpreamble(bf) ?
f078f209
LR		 812 rt->info[rix].spAckDuration :
813 rt->info[rix].lpAckDuration;
814 }
815
816 /*
817 * Disable multi-rate retry when using RTS/CTS by clearing
818 * series 1, 2 and 3.
819 */
0345f37b 820 memset(&series[1], 0, sizeof(struct ath9k_11n_rate_series) * 3);
f078f209
LR		 821 }
822
823 /*
824 * set dur_update_en for l-sig computation except for PS-Poll frames
825 */
826 ath9k_hw_set11n_ratescenario(ah, ds, lastds,
cd3d39a6
S		 827 !bf_ispspoll(bf),
828 ctsrate,
829 ctsduration,
830 series, 4, flags);
f078f209
LR		 831 if (sc->sc_config.ath_aggr_prot && flags)
832 ath9k_hw_set11n_burstduration(ah, ds, 8192);
833}
834
835/*
836 * Function to send a normal HT (non-AMPDU) frame
837 * NB: must be called with txq lock held
838 */
839
840static int ath_tx_send_normal(struct ath_softc *sc,
841 struct ath_txq *txq,
842 struct ath_atx_tid *tid,
843 struct list_head *bf_head)
844{
845 struct ath_buf *bf;
846 struct sk_buff *skb;
847 struct ieee80211_tx_info *tx_info;
848 struct ath_tx_info_priv *tx_info_priv;
849
850 BUG_ON(list_empty(bf_head));
851
852 bf = list_first_entry(bf_head, struct ath_buf, list);
cd3d39a6 853 bf->bf_state.bf_type &= ~BUF_AMPDU; /* regular HT frame */
f078f209
LR		 854
855 skb = (struct sk_buff *)bf->bf_mpdu;
856 tx_info = IEEE80211_SKB_CB(skb);
857 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
858 memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
859
860 /* update starting sequence number for subsequent ADDBA request */
861 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
862
863 /* Queue to h/w without aggregation */
864 bf->bf_nframes = 1;
865 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
866 ath_buf_set_rate(sc, bf);
867 ath_tx_txqaddbuf(sc, txq, bf_head);
868
869 return 0;
870}
871
872/* flush tid's software queue and send frames as non-ampdu's */
873
874static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
875{
876 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
877 struct ath_buf *bf;
878 struct list_head bf_head;
879 INIT_LIST_HEAD(&bf_head);
880
881 ASSERT(tid->paused > 0);
882 spin_lock_bh(&txq->axq_lock);
883
884 tid->paused--;
885
886 if (tid->paused > 0) {
887 spin_unlock_bh(&txq->axq_lock);
888 return;
889 }
890
891 while (!list_empty(&tid->buf_q)) {
892 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
cd3d39a6 893 ASSERT(!bf_isretried(bf));
f078f209
LR		 894 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
895 ath_tx_send_normal(sc, txq, tid, &bf_head);
896 }
897
898 spin_unlock_bh(&txq->axq_lock);
899}
900
901/* Completion routine of an aggregate */
902
903static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
904 struct ath_txq *txq,
905 struct ath_buf *bf,
906 struct list_head *bf_q,
907 int txok)
908{
909 struct ath_node *an = bf->bf_node;
910 struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno);
911 struct ath_buf *bf_last = bf->bf_lastbf;
912 struct ath_desc *ds = bf_last->bf_desc;
913 struct ath_buf *bf_next, *bf_lastq = NULL;
914 struct list_head bf_head, bf_pending;
915 u16 seq_st = 0;
916 u32 ba[WME_BA_BMP_SIZE >> 5];
917 int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
918 int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
919
cd3d39a6 920 isaggr = bf_isaggr(bf);
f078f209
LR		 921 if (isaggr) {
922 if (txok) {
923 if (ATH_DS_TX_BA(ds)) {
924 /*
925 * extract starting sequence and
926 * block-ack bitmap
927 */
928 seq_st = ATH_DS_BA_SEQ(ds);
929 memcpy(ba,
930 ATH_DS_BA_BITMAP(ds),
931 WME_BA_BMP_SIZE >> 3);
932 } else {
0345f37b 933 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
f078f209
LR		 934
935 /*
936 * AR5416 can become deaf/mute when BA
937 * issue happens. Chip needs to be reset.
938 * But AP code may have sychronization issues
939 * when perform internal reset in this routine.
940 * Only enable reset in STA mode for now.
941 */
b4696c8b 942 if (sc->sc_ah->ah_opmode == ATH9K_M_STA)
f078f209
LR		 943 needreset = 1;
944 }
945 } else {
0345f37b 946 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
f078f209
LR		 947 }
948 }
949
950 INIT_LIST_HEAD(&bf_pending);
951 INIT_LIST_HEAD(&bf_head);
952
953 while (bf) {
954 txfail = txpending = 0;
955 bf_next = bf->bf_next;
956
957 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
958 /* transmit completion, subframe is
959 * acked by block ack */
960 } else if (!isaggr && txok) {
961 /* transmit completion */
962 } else {
963
964 if (!tid->cleanup_inprogress && !isnodegone &&
965 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
966 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
967 ath_tx_set_retry(sc, bf);
968 txpending = 1;
969 } else {
cd3d39a6 970 bf->bf_state.bf_type |= BUF_XRETRY;
f078f209
LR		 971 txfail = 1;
972 sendbar = 1;
973 }
974 } else {
975 /*
976 * cleanup in progress, just fail
977 * the un-acked sub-frames
978 */
979 txfail = 1;
980 }
981 }
982 /*
983 * Remove ath_buf's of this sub-frame from aggregate queue.
984 */
985 if (bf_next == NULL) { /* last subframe in the aggregate */
986 ASSERT(bf->bf_lastfrm == bf_last);
987
988 /*
989 * The last descriptor of the last sub frame could be
990 * a holding descriptor for h/w. If that's the case,
991 * bf->bf_lastfrm won't be in the bf_q.
992 * Make sure we handle bf_q properly here.
993 */
994
995 if (!list_empty(bf_q)) {
996 bf_lastq = list_entry(bf_q->prev,
997 struct ath_buf, list);
998 list_cut_position(&bf_head,
999 bf_q, &bf_lastq->list);
1000 } else {
1001 /*
1002 * XXX: if the last subframe only has one
1003 * descriptor which is also being used as
1004 * a holding descriptor. Then the ath_buf
1005 * is not in the bf_q at all.
1006 */
1007 INIT_LIST_HEAD(&bf_head);
1008 }
1009 } else {
1010 ASSERT(!list_empty(bf_q));
1011 list_cut_position(&bf_head,
1012 bf_q, &bf->bf_lastfrm->list);
1013 }
1014
1015 if (!txpending) {
1016 /*
1017 * complete the acked-ones/xretried ones; update
1018 * block-ack window
1019 */
1020 spin_lock_bh(&txq->axq_lock);
1021 ath_tx_update_baw(sc, tid, bf->bf_seqno);
1022 spin_unlock_bh(&txq->axq_lock);
1023
1024 /* complete this sub-frame */
1025 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
1026 } else {
1027 /*
1028 * retry the un-acked ones
1029 */
1030 /*
1031 * XXX: if the last descriptor is holding descriptor,
1032 * in order to requeue the frame to software queue, we
1033 * need to allocate a new descriptor and
1034 * copy the content of holding descriptor to it.
1035 */
1036 if (bf->bf_next == NULL &&
1037 bf_last->bf_status & ATH_BUFSTATUS_STALE) {
1038 struct ath_buf *tbf;
1039
1040 /* allocate new descriptor */
1041 spin_lock_bh(&sc->sc_txbuflock);
1042 ASSERT(!list_empty((&sc->sc_txbuf)));
1043 tbf = list_first_entry(&sc->sc_txbuf,
1044 struct ath_buf, list);
1045 list_del(&tbf->list);
1046 spin_unlock_bh(&sc->sc_txbuflock);
1047
1048 ATH_TXBUF_RESET(tbf);
1049
1050 /* copy descriptor content */
1051 tbf->bf_mpdu = bf_last->bf_mpdu;
1052 tbf->bf_node = bf_last->bf_node;
1053 tbf->bf_buf_addr = bf_last->bf_buf_addr;
1054 *(tbf->bf_desc) = *(bf_last->bf_desc);
1055
1056 /* link it to the frame */
1057 if (bf_lastq) {
1058 bf_lastq->bf_desc->ds_link =
1059 tbf->bf_daddr;
1060 bf->bf_lastfrm = tbf;
1061 ath9k_hw_cleartxdesc(sc->sc_ah,
1062 bf->bf_lastfrm->bf_desc);
1063 } else {
1064 tbf->bf_state = bf_last->bf_state;
1065 tbf->bf_lastfrm = tbf;
1066 ath9k_hw_cleartxdesc(sc->sc_ah,
1067 tbf->bf_lastfrm->bf_desc);
1068
1069 /* copy the DMA context */
ff9b662d
S		 1070 tbf->bf_dmacontext =
1071 bf_last->bf_dmacontext;
f078f209
LR		 1072 }
1073 list_add_tail(&tbf->list, &bf_head);
1074 } else {
1075 /*
1076 * Clear descriptor status words for
1077 * software retry
1078 */
1079 ath9k_hw_cleartxdesc(sc->sc_ah,
ff9b662d 1080 bf->bf_lastfrm->bf_desc);
f078f209
LR		 1081 }
1082
1083 /*
1084 * Put this buffer to the temporary pending
1085 * queue to retain ordering
1086 */
1087 list_splice_tail_init(&bf_head, &bf_pending);
1088 }
1089
1090 bf = bf_next;
1091 }
1092
1093 /*
1094 * node is already gone. no more assocication
1095 * with the node. the node might have been freed
1096 * any node acces can result in panic.note tid
1097 * is part of the node.
1098 */
1099 if (isnodegone)
1100 return;
1101
1102 if (tid->cleanup_inprogress) {
1103 /* check to see if we're done with cleaning the h/w queue */
1104 spin_lock_bh(&txq->axq_lock);
1105
1106 if (tid->baw_head == tid->baw_tail) {
1107 tid->addba_exchangecomplete = 0;
1108 tid->addba_exchangeattempts = 0;
1109 spin_unlock_bh(&txq->axq_lock);
1110
1111 tid->cleanup_inprogress = false;
1112
1113 /* send buffered frames as singles */
1114 ath_tx_flush_tid(sc, tid);
1115 } else
1116 spin_unlock_bh(&txq->axq_lock);
1117
1118 return;
1119 }
1120
1121 /*
1122 * prepend un-acked frames to the beginning of the pending frame queue
1123 */
1124 if (!list_empty(&bf_pending)) {
1125 spin_lock_bh(&txq->axq_lock);
1126 /* Note: we _prepend_, we _do_not_ at to
1127 * the end of the queue ! */
1128 list_splice(&bf_pending, &tid->buf_q);
1129 ath_tx_queue_tid(txq, tid);
1130 spin_unlock_bh(&txq->axq_lock);
1131 }
1132
1133 if (needreset)
f45144ef 1134 ath_reset(sc, false);
f078f209
LR		 1135
1136 return;
1137}
1138
1139/* Process completed xmit descriptors from the specified queue */
1140
1141static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1142{
1143 struct ath_hal *ah = sc->sc_ah;
1144 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1145 struct list_head bf_head;
1146 struct ath_desc *ds, *tmp_ds;
1147 struct sk_buff *skb;
1148 struct ieee80211_tx_info *tx_info;
1149 struct ath_tx_info_priv *tx_info_priv;
1150 int nacked, txok, nbad = 0, isrifs = 0;
1151 int status;
1152
1153 DPRINTF(sc, ATH_DBG_QUEUE,
1154 "%s: tx queue %d (%x), link %p\n", __func__,
1155 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1156 txq->axq_link);
1157
1158 nacked = 0;
1159 for (;;) {
1160 spin_lock_bh(&txq->axq_lock);
1161 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
1162 if (list_empty(&txq->axq_q)) {
1163 txq->axq_link = NULL;
1164 txq->axq_linkbuf = NULL;
1165 spin_unlock_bh(&txq->axq_lock);
1166 break;
1167 }
1168 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1169
1170 /*
1171 * There is a race condition that a BH gets scheduled
1172 * after sw writes TxE and before hw re-load the last
1173 * descriptor to get the newly chained one.
1174 * Software must keep the last DONE descriptor as a
1175 * holding descriptor - software does so by marking
1176 * it with the STALE flag.
1177 */
1178 bf_held = NULL;
1179 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1180 bf_held = bf;
1181 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1182 /* FIXME:
1183 * The holding descriptor is the last
1184 * descriptor in queue. It's safe to remove
1185 * the last holding descriptor in BH context.
1186 */
1187 spin_unlock_bh(&txq->axq_lock);
1188 break;
1189 } else {
1190 /* Lets work with the next buffer now */
1191 bf = list_entry(bf_held->list.next,
1192 struct ath_buf, list);
1193 }
1194 }
1195
1196 lastbf = bf->bf_lastbf;
1197 ds = lastbf->bf_desc; /* NB: last decriptor */
1198
1199 status = ath9k_hw_txprocdesc(ah, ds);
1200 if (status == -EINPROGRESS) {
1201 spin_unlock_bh(&txq->axq_lock);
1202 break;
1203 }
1204 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1205 txq->axq_lastdsWithCTS = NULL;
1206 if (ds == txq->axq_gatingds)
1207 txq->axq_gatingds = NULL;
1208
1209 /*
1210 * Remove ath_buf's of the same transmit unit from txq,
1211 * however leave the last descriptor back as the holding
1212 * descriptor for hw.
1213 */
1214 lastbf->bf_status |= ATH_BUFSTATUS_STALE;
1215 INIT_LIST_HEAD(&bf_head);
1216
1217 if (!list_is_singular(&lastbf->list))
1218 list_cut_position(&bf_head,
1219 &txq->axq_q, lastbf->list.prev);
1220
1221 txq->axq_depth--;
1222
cd3d39a6 1223 if (bf_isaggr(bf))
f078f209
LR		 1224 txq->axq_aggr_depth--;
1225
1226 txok = (ds->ds_txstat.ts_status == 0);
1227
1228 spin_unlock_bh(&txq->axq_lock);
1229
1230 if (bf_held) {
1231 list_del(&bf_held->list);
1232 spin_lock_bh(&sc->sc_txbuflock);
1233 list_add_tail(&bf_held->list, &sc->sc_txbuf);
1234 spin_unlock_bh(&sc->sc_txbuflock);
1235 }
1236
cd3d39a6 1237 if (!bf_isampdu(bf)) {
f078f209
LR		 1238 /*
1239 * This frame is sent out as a single frame.
1240 * Use hardware retry status for this frame.
1241 */
1242 bf->bf_retries = ds->ds_txstat.ts_longretry;
1243 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
cd3d39a6 1244 bf->bf_state.bf_type |= BUF_XRETRY;
f078f209
LR		 1245 nbad = 0;
1246 } else {
1247 nbad = ath_tx_num_badfrms(sc, bf, txok);
1248 }
1249 skb = bf->bf_mpdu;
1250 tx_info = IEEE80211_SKB_CB(skb);
1251 tx_info_priv = (struct ath_tx_info_priv *)
1252 tx_info->driver_data[0];
1253 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1254 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1255 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1256 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
1257 if (ds->ds_txstat.ts_status == 0)
1258 nacked++;
1259
cd3d39a6 1260 if (bf_isdata(bf)) {
f078f209
LR		 1261 if (isrifs)
1262 tmp_ds = bf->bf_rifslast->bf_desc;
1263 else
1264 tmp_ds = ds;
1265 memcpy(&tx_info_priv->tx,
1266 &tmp_ds->ds_txstat,
1267 sizeof(tx_info_priv->tx));
1268 tx_info_priv->n_frames = bf->bf_nframes;
1269 tx_info_priv->n_bad_frames = nbad;
1270 }
1271 }
1272
1273 /*
1274 * Complete this transmit unit
1275 */
cd3d39a6 1276 if (bf_isampdu(bf))
f078f209
LR		 1277 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, txok);
1278 else
1279 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
1280
1281 /* Wake up mac80211 queue */
1282
1283 spin_lock_bh(&txq->axq_lock);
1284 if (txq->stopped && ath_txq_depth(sc, txq->axq_qnum) <=
1285 (ATH_TXBUF - 20)) {
1286 int qnum;
1287 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1288 if (qnum != -1) {
1289 ieee80211_wake_queue(sc->hw, qnum);
1290 txq->stopped = 0;
1291 }
1292
1293 }
1294
1295 /*
1296 * schedule any pending packets if aggregation is enabled
1297 */
672840ac 1298 if (sc->sc_flags & SC_OP_TXAGGR)
f078f209
LR		 1299 ath_txq_schedule(sc, txq);
1300 spin_unlock_bh(&txq->axq_lock);
1301 }
1302 return nacked;
1303}
1304
1305static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
1306{
1307 struct ath_hal *ah = sc->sc_ah;
1308
1309 (void) ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1310 DPRINTF(sc, ATH_DBG_XMIT, "%s: tx queue [%u] %x, link %p\n",
1311 __func__, txq->axq_qnum,
1312 ath9k_hw_gettxbuf(ah, txq->axq_qnum), txq->axq_link);
1313}
1314
1315/* Drain only the data queues */
1316
1317static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
1318{
1319 struct ath_hal *ah = sc->sc_ah;
1320 int i;
1321 int npend = 0;
f078f209
LR		 1322
1323 /* XXX return value */
672840ac 1324 if (!(sc->sc_flags & SC_OP_INVALID)) {
f078f209
LR		 1325 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1326 if (ATH_TXQ_SETUP(sc, i)) {
1327 ath_tx_stopdma(sc, &sc->sc_txq[i]);
1328
1329 /* The TxDMA may not really be stopped.
1330 * Double check the hal tx pending count */
1331 npend += ath9k_hw_numtxpending(ah,
1332 sc->sc_txq[i].axq_qnum);
1333 }
1334 }
1335 }
1336
1337 if (npend) {
1338 int status;
1339
1340 /* TxDMA not stopped, reset the hal */
1341 DPRINTF(sc, ATH_DBG_XMIT,
1342 "%s: Unable to stop TxDMA. Reset HAL!\n", __func__);
1343
1344 spin_lock_bh(&sc->sc_resetlock);
b4696c8b 1345 if (!ath9k_hw_reset(ah,
927e70e9
S		 1346 sc->sc_ah->ah_curchan,
1347 sc->sc_ht_info.tx_chan_width,
1348 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1349 sc->sc_ht_extprotspacing, true, &status)) {
f078f209
LR		 1350
1351 DPRINTF(sc, ATH_DBG_FATAL,
1352 "%s: unable to reset hardware; hal status %u\n",
1353 __func__,
1354 status);
1355 }
1356 spin_unlock_bh(&sc->sc_resetlock);
1357 }
1358
1359 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1360 if (ATH_TXQ_SETUP(sc, i))
1361 ath_tx_draintxq(sc, &sc->sc_txq[i], retry_tx);
1362 }
1363}
1364
1365/* Add a sub-frame to block ack window */
1366
1367static void ath_tx_addto_baw(struct ath_softc *sc,
1368 struct ath_atx_tid *tid,
1369 struct ath_buf *bf)
1370{
1371 int index, cindex;
1372
cd3d39a6 1373 if (bf_isretried(bf))
f078f209
LR		 1374 return;
1375
1376 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
1377 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1378
1379 ASSERT(tid->tx_buf[cindex] == NULL);
1380 tid->tx_buf[cindex] = bf;
1381
1382 if (index >= ((tid->baw_tail - tid->baw_head) &
1383 (ATH_TID_MAX_BUFS - 1))) {
1384 tid->baw_tail = cindex;
1385 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1386 }
1387}
1388
1389/*
1390 * Function to send an A-MPDU
1391 * NB: must be called with txq lock held
1392 */
1393
1394static int ath_tx_send_ampdu(struct ath_softc *sc,
1395 struct ath_txq *txq,
1396 struct ath_atx_tid *tid,
1397 struct list_head *bf_head,
1398 struct ath_tx_control *txctl)
1399{
1400 struct ath_buf *bf;
1401 struct sk_buff *skb;
1402 struct ieee80211_tx_info *tx_info;
1403 struct ath_tx_info_priv *tx_info_priv;
1404
1405 BUG_ON(list_empty(bf_head));
1406
1407 bf = list_first_entry(bf_head, struct ath_buf, list);
cd3d39a6 1408 bf->bf_state.bf_type |= BUF_AMPDU;
f078f209
LR		 1409 bf->bf_seqno = txctl->seqno; /* save seqno and tidno in buffer */
1410 bf->bf_tidno = txctl->tidno;
1411
1412 /*
1413 * Do not queue to h/w when any of the following conditions is true:
1414 * - there are pending frames in software queue
1415 * - the TID is currently paused for ADDBA/BAR request
1416 * - seqno is not within block-ack window
1417 * - h/w queue depth exceeds low water mark
1418 */
1419 if (!list_empty(&tid->buf_q) || tid->paused ||
1420 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1421 txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1422 /*
1423 * Add this frame to software queue for scheduling later
1424 * for aggregation.
1425 */
1426 list_splice_tail_init(bf_head, &tid->buf_q);
1427 ath_tx_queue_tid(txq, tid);
1428 return 0;
1429 }
1430
1431 skb = (struct sk_buff *)bf->bf_mpdu;
1432 tx_info = IEEE80211_SKB_CB(skb);
1433 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
1434 memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
1435
1436 /* Add sub-frame to BAW */
1437 ath_tx_addto_baw(sc, tid, bf);
1438
1439 /* Queue to h/w without aggregation */
1440 bf->bf_nframes = 1;
1441 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
1442 ath_buf_set_rate(sc, bf);
1443 ath_tx_txqaddbuf(sc, txq, bf_head);
1444 return 0;
1445}
1446
1447/*
1448 * looks up the rate
1449 * returns aggr limit based on lowest of the rates
1450 */
1451
1452static u32 ath_lookup_rate(struct ath_softc *sc,
1453 struct ath_buf *bf)
1454{
1455 const struct ath9k_rate_table *rt = sc->sc_currates;
1456 struct sk_buff *skb;
1457 struct ieee80211_tx_info *tx_info;
1458 struct ath_tx_info_priv *tx_info_priv;
1459 u32 max_4ms_framelen, frame_length;
1460 u16 aggr_limit, legacy = 0, maxampdu;
1461 int i;
1462
1463
1464 skb = (struct sk_buff *)bf->bf_mpdu;
1465 tx_info = IEEE80211_SKB_CB(skb);
1466 tx_info_priv = (struct ath_tx_info_priv *)
1467 tx_info->driver_data[0];
1468 memcpy(bf->bf_rcs,
1469 tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
1470
1471 /*
1472 * Find the lowest frame length among the rate series that will have a
1473 * 4ms transmit duration.
1474 * TODO - TXOP limit needs to be considered.
1475 */
1476 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
1477
1478 for (i = 0; i < 4; i++) {
1479 if (bf->bf_rcs[i].tries) {
1480 frame_length = bf->bf_rcs[i].max_4ms_framelen;
1481
1482 if (rt->info[bf->bf_rcs[i].rix].phy != PHY_HT) {
1483 legacy = 1;
1484 break;
1485 }
1486
1487 max_4ms_framelen = min(max_4ms_framelen, frame_length);
1488 }
1489 }
1490
1491 /*
1492 * limit aggregate size by the minimum rate if rate selected is
1493 * not a probe rate, if rate selected is a probe rate then
1494 * avoid aggregation of this packet.
1495 */
1496 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
1497 return 0;
1498
1499 aggr_limit = min(max_4ms_framelen,
1500 (u32)ATH_AMPDU_LIMIT_DEFAULT);
1501
1502 /*
1503 * h/w can accept aggregates upto 16 bit lengths (65535).
1504 * The IE, however can hold upto 65536, which shows up here
1505 * as zero. Ignore 65536 since we are constrained by hw.
1506 */
1507 maxampdu = sc->sc_ht_info.maxampdu;
1508 if (maxampdu)
1509 aggr_limit = min(aggr_limit, maxampdu);
1510
1511 return aggr_limit;
1512}
1513
1514/*
1515 * returns the number of delimiters to be added to
1516 * meet the minimum required mpdudensity.
1517 * caller should make sure that the rate is HT rate .
1518 */
1519
1520static int ath_compute_num_delims(struct ath_softc *sc,
1521 struct ath_buf *bf,
1522 u16 frmlen)
1523{
1524 const struct ath9k_rate_table *rt = sc->sc_currates;
1525 u32 nsymbits, nsymbols, mpdudensity;
1526 u16 minlen;
1527 u8 rc, flags, rix;
1528 int width, half_gi, ndelim, mindelim;
1529
1530 /* Select standard number of delimiters based on frame length alone */
1531 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
1532
1533 /*
1534 * If encryption enabled, hardware requires some more padding between
1535 * subframes.
1536 * TODO - this could be improved to be dependent on the rate.
1537 * The hardware can keep up at lower rates, but not higher rates
1538 */
1539 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
1540 ndelim += ATH_AGGR_ENCRYPTDELIM;
1541
1542 /*
1543 * Convert desired mpdu density from microeconds to bytes based
1544 * on highest rate in rate series (i.e. first rate) to determine
1545 * required minimum length for subframe. Take into account
1546 * whether high rate is 20 or 40Mhz and half or full GI.
1547 */
1548 mpdudensity = sc->sc_ht_info.mpdudensity;
1549
1550 /*
1551 * If there is no mpdu density restriction, no further calculation
1552 * is needed.
1553 */
1554 if (mpdudensity == 0)
1555 return ndelim;
1556
1557 rix = bf->bf_rcs[0].rix;
1558 flags = bf->bf_rcs[0].flags;
1559 rc = rt->info[rix].rateCode;
1560 width = (flags & ATH_RC_CW40_FLAG) ? 1 : 0;
1561 half_gi = (flags & ATH_RC_SGI_FLAG) ? 1 : 0;
1562
1563 if (half_gi)
1564 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
1565 else
1566 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
1567
1568 if (nsymbols == 0)
1569 nsymbols = 1;
1570
1571 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1572 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
1573
1574 /* Is frame shorter than required minimum length? */
1575 if (frmlen < minlen) {
1576 /* Get the minimum number of delimiters required. */
1577 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
1578 ndelim = max(mindelim, ndelim);
1579 }
1580
1581 return ndelim;
1582}
1583
1584/*
1585 * For aggregation from software buffer queue.
1586 * NB: must be called with txq lock held
1587 */
1588
1589static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
1590 struct ath_atx_tid *tid,
1591 struct list_head *bf_q,
1592 struct ath_buf **bf_last,
1593 struct aggr_rifs_param *param,
1594 int *prev_frames)
1595{
1596#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1597 struct ath_buf *bf, *tbf, *bf_first, *bf_prev = NULL;
1598 struct list_head bf_head;
1599 int rl = 0, nframes = 0, ndelim;
1600 u16 aggr_limit = 0, al = 0, bpad = 0,
1601 al_delta, h_baw = tid->baw_size / 2;
1602 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
1603 int prev_al = 0, is_ds_rate = 0;
1604 INIT_LIST_HEAD(&bf_head);
1605
1606 BUG_ON(list_empty(&tid->buf_q));
1607
1608 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
1609
1610 do {
1611 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1612
1613 /*
1614 * do not step over block-ack window
1615 */
1616 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
1617 status = ATH_AGGR_BAW_CLOSED;
1618 break;
1619 }
1620
1621 if (!rl) {
1622 aggr_limit = ath_lookup_rate(sc, bf);
1623 rl = 1;
1624 /*
1625 * Is rate dual stream
1626 */
1627 is_ds_rate =
1628 (bf->bf_rcs[0].flags & ATH_RC_DS_FLAG) ? 1 : 0;
1629 }
1630
1631 /*
1632 * do not exceed aggregation limit
1633 */
1634 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
1635
1636 if (nframes && (aggr_limit <
1637 (al + bpad + al_delta + prev_al))) {
1638 status = ATH_AGGR_LIMITED;
1639 break;
1640 }
1641
1642 /*
1643 * do not exceed subframe limit
1644 */
1645 if ((nframes + *prev_frames) >=
1646 min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
1647 status = ATH_AGGR_LIMITED;
1648 break;
1649 }
1650
1651 /*
1652 * add padding for previous frame to aggregation length
1653 */
1654 al += bpad + al_delta;
1655
1656 /*
1657 * Get the delimiters needed to meet the MPDU
1658 * density for this node.
1659 */
1660 ndelim = ath_compute_num_delims(sc, bf_first, bf->bf_frmlen);
1661
1662 bpad = PADBYTES(al_delta) + (ndelim << 2);
1663
1664 bf->bf_next = NULL;
1665 bf->bf_lastfrm->bf_desc->ds_link = 0;
1666
1667 /*
1668 * this packet is part of an aggregate
1669 * - remove all descriptors belonging to this frame from
1670 * software queue
1671 * - add it to block ack window
1672 * - set up descriptors for aggregation
1673 */
1674 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1675 ath_tx_addto_baw(sc, tid, bf);
1676
1677 list_for_each_entry(tbf, &bf_head, list) {
1678 ath9k_hw_set11n_aggr_middle(sc->sc_ah,
1679 tbf->bf_desc, ndelim);
1680 }
1681
1682 /*
1683 * link buffers of this frame to the aggregate
1684 */
1685 list_splice_tail_init(&bf_head, bf_q);
1686 nframes++;
1687
1688 if (bf_prev) {
1689 bf_prev->bf_next = bf;
1690 bf_prev->bf_lastfrm->bf_desc->ds_link = bf->bf_daddr;
1691 }
1692 bf_prev = bf;
1693
1694#ifdef AGGR_NOSHORT
1695 /*
1696 * terminate aggregation on a small packet boundary
1697 */
1698 if (bf->bf_frmlen < ATH_AGGR_MINPLEN) {
1699 status = ATH_AGGR_SHORTPKT;
1700 break;
1701 }
1702#endif
1703 } while (!list_empty(&tid->buf_q));
1704
1705 bf_first->bf_al = al;
1706 bf_first->bf_nframes = nframes;
1707 *bf_last = bf_prev;
1708 return status;
1709#undef PADBYTES
1710}
1711
1712/*
1713 * process pending frames possibly doing a-mpdu aggregation
1714 * NB: must be called with txq lock held
1715 */
1716
1717static void ath_tx_sched_aggr(struct ath_softc *sc,
1718 struct ath_txq *txq, struct ath_atx_tid *tid)
1719{
1720 struct ath_buf *bf, *tbf, *bf_last, *bf_lastaggr = NULL;
1721 enum ATH_AGGR_STATUS status;
1722 struct list_head bf_q;
1723 struct aggr_rifs_param param = {0, 0, 0, 0, NULL};
1724 int prev_frames = 0;
1725
1726 do {
1727 if (list_empty(&tid->buf_q))
1728 return;
1729
1730 INIT_LIST_HEAD(&bf_q);
1731
1732 status = ath_tx_form_aggr(sc, tid, &bf_q, &bf_lastaggr, &param,
1733 &prev_frames);
1734
1735 /*
1736 * no frames picked up to be aggregated; block-ack
1737 * window is not open
1738 */
1739 if (list_empty(&bf_q))
1740 break;
1741
1742 bf = list_first_entry(&bf_q, struct ath_buf, list);
1743 bf_last = list_entry(bf_q.prev, struct ath_buf, list);
1744 bf->bf_lastbf = bf_last;
1745
1746 /*
1747 * if only one frame, send as non-aggregate
1748 */
1749 if (bf->bf_nframes == 1) {
1750 ASSERT(bf->bf_lastfrm == bf_last);
1751
cd3d39a6 1752 bf->bf_state.bf_type &= ~BUF_AGGR;
f078f209
LR		 1753 /*
1754 * clear aggr bits for every descriptor
1755 * XXX TODO: is there a way to optimize it?
1756 */
1757 list_for_each_entry(tbf, &bf_q, list) {
1758 ath9k_hw_clr11n_aggr(sc->sc_ah, tbf->bf_desc);
1759 }
1760
1761 ath_buf_set_rate(sc, bf);
1762 ath_tx_txqaddbuf(sc, txq, &bf_q);
1763 continue;
1764 }
1765
1766 /*
1767 * setup first desc with rate and aggr info
1768 */
cd3d39a6 1769 bf->bf_state.bf_type |= BUF_AGGR;
f078f209
LR		 1770 ath_buf_set_rate(sc, bf);
1771 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
1772
1773 /*
1774 * anchor last frame of aggregate correctly
1775 */
1776 ASSERT(bf_lastaggr);
1777 ASSERT(bf_lastaggr->bf_lastfrm == bf_last);
1778 tbf = bf_lastaggr;
1779 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1780
1781 /* XXX: We don't enter into this loop, consider removing this */
1782 while (!list_empty(&bf_q) && !list_is_last(&tbf->list, &bf_q)) {
1783 tbf = list_entry(tbf->list.next, struct ath_buf, list);
1784 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1785 }
1786
1787 txq->axq_aggr_depth++;
1788
1789 /*
1790 * Normal aggregate, queue to hardware
1791 */
1792 ath_tx_txqaddbuf(sc, txq, &bf_q);
1793
1794 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1795 status != ATH_AGGR_BAW_CLOSED);
1796}
1797
1798/* Called with txq lock held */
1799
1800static void ath_tid_drain(struct ath_softc *sc,
1801 struct ath_txq *txq,
1802 struct ath_atx_tid *tid,
1803 bool bh_flag)
1804{
1805 struct ath_buf *bf;
1806 struct list_head bf_head;
1807 INIT_LIST_HEAD(&bf_head);
1808
1809 for (;;) {
1810 if (list_empty(&tid->buf_q))
1811 break;
1812 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1813
1814 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1815
1816 /* update baw for software retried frame */
cd3d39a6 1817 if (bf_isretried(bf))
f078f209
LR		 1818 ath_tx_update_baw(sc, tid, bf->bf_seqno);
1819
1820 /*
1821 * do not indicate packets while holding txq spinlock.
1822 * unlock is intentional here
1823 */
1824 if (likely(bh_flag))
1825 spin_unlock_bh(&txq->axq_lock);
1826 else
1827 spin_unlock(&txq->axq_lock);
1828
1829 /* complete this sub-frame */
1830 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1831
1832 if (likely(bh_flag))
1833 spin_lock_bh(&txq->axq_lock);
1834 else
1835 spin_lock(&txq->axq_lock);
1836 }
1837
1838 /*
1839 * TODO: For frame(s) that are in the retry state, we will reuse the
1840 * sequence number(s) without setting the retry bit. The
1841 * alternative is to give up on these and BAR the receiver's window
1842 * forward.
1843 */
1844 tid->seq_next = tid->seq_start;
1845 tid->baw_tail = tid->baw_head;
1846}
1847
1848/*
1849 * Drain all pending buffers
1850 * NB: must be called with txq lock held
1851 */
1852
1853static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1854 struct ath_txq *txq,
1855 bool bh_flag)
1856{
1857 struct ath_atx_ac *ac, *ac_tmp;
1858 struct ath_atx_tid *tid, *tid_tmp;
1859
1860 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1861 list_del(&ac->list);
1862 ac->sched = false;
1863 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1864 list_del(&tid->list);
1865 tid->sched = false;
1866 ath_tid_drain(sc, txq, tid, bh_flag);
1867 }
1868 }
1869}
1870
1871static int ath_tx_start_dma(struct ath_softc *sc,
1872 struct sk_buff *skb,
1873 struct scatterlist *sg,
1874 u32 n_sg,
1875 struct ath_tx_control *txctl)
1876{
1877 struct ath_node *an = txctl->an;
1878 struct ath_buf *bf = NULL;
1879 struct list_head bf_head;
1880 struct ath_desc *ds;
1881 struct ath_hal *ah = sc->sc_ah;
e022edbd 1882 struct ath_txq *txq;
f078f209
LR		 1883 struct ath_tx_info_priv *tx_info_priv;
1884 struct ath_rc_series *rcs;
1885 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1886 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1887 __le16 fc = hdr->frame_control;
1888
e022edbd
JM		 1889 if (unlikely(txctl->flags & ATH9K_TXDESC_CAB))
1890 txq = sc->sc_cabq;
1891 else
1892 txq = &sc->sc_txq[txctl->qnum];
1893
f078f209
LR		 1894 /* For each sglist entry, allocate an ath_buf for DMA */
1895 INIT_LIST_HEAD(&bf_head);
1896 spin_lock_bh(&sc->sc_txbuflock);
1897 if (unlikely(list_empty(&sc->sc_txbuf))) {
1898 spin_unlock_bh(&sc->sc_txbuflock);
1899 return -ENOMEM;
1900 }
1901
1902 bf = list_first_entry(&sc->sc_txbuf, struct ath_buf, list);
1903 list_del(&bf->list);
1904 spin_unlock_bh(&sc->sc_txbuflock);
1905
1906 list_add_tail(&bf->list, &bf_head);
1907
1908 /* set up this buffer */
1909 ATH_TXBUF_RESET(bf);
1910 bf->bf_frmlen = txctl->frmlen;
cd3d39a6
S		 1911
1912 ieee80211_is_data(fc) ?
1913 (bf->bf_state.bf_type |= BUF_DATA) :
1914 (bf->bf_state.bf_type &= ~BUF_DATA);
1915 ieee80211_is_back_req(fc) ?
1916 (bf->bf_state.bf_type |= BUF_BAR) :
1917 (bf->bf_state.bf_type &= ~BUF_BAR);
1918 ieee80211_is_pspoll(fc) ?
1919 (bf->bf_state.bf_type |= BUF_PSPOLL) :
1920 (bf->bf_state.bf_type &= ~BUF_PSPOLL);
672840ac 1921 (sc->sc_flags & SC_OP_PREAMBLE_SHORT) ?
cd3d39a6
S		 1922 (bf->bf_state.bf_type |= BUF_SHORT_PREAMBLE) :
1923 (bf->bf_state.bf_type &= ~BUF_SHORT_PREAMBLE);
1924
f078f209 1925 bf->bf_flags = txctl->flags;
f078f209
LR		 1926 bf->bf_keytype = txctl->keytype;
1927 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
1928 rcs = tx_info_priv->rcs;
1929 bf->bf_rcs[0] = rcs[0];
1930 bf->bf_rcs[1] = rcs[1];
1931 bf->bf_rcs[2] = rcs[2];
1932 bf->bf_rcs[3] = rcs[3];
1933 bf->bf_node = an;
1934 bf->bf_mpdu = skb;
1935 bf->bf_buf_addr = sg_dma_address(sg);
1936
1937 /* setup descriptor */
1938 ds = bf->bf_desc;
1939 ds->ds_link = 0;
1940 ds->ds_data = bf->bf_buf_addr;
1941
1942 /*
1943 * Save the DMA context in the first ath_buf
1944 */
ff9b662d 1945 bf->bf_dmacontext = txctl->dmacontext;
f078f209
LR		 1946
1947 /*
1948 * Formulate first tx descriptor with tx controls.
1949 */
1950 ath9k_hw_set11n_txdesc(ah,
1951 ds,
1952 bf->bf_frmlen, /* frame length */
1953 txctl->atype, /* Atheros packet type */
1954 min(txctl->txpower, (u16)60), /* txpower */
1955 txctl->keyix, /* key cache index */
1956 txctl->keytype, /* key type */
1957 txctl->flags); /* flags */
1958 ath9k_hw_filltxdesc(ah,
1959 ds,
1960 sg_dma_len(sg), /* segment length */
1961 true, /* first segment */
1962 (n_sg == 1) ? true : false, /* last segment */
1963 ds); /* first descriptor */
1964
1965 bf->bf_lastfrm = bf;
cd3d39a6
S		 1966 (txctl->ht) ?
1967 (bf->bf_state.bf_type |= BUF_HT) :
1968 (bf->bf_state.bf_type &= ~BUF_HT);
f078f209
LR		 1969
1970 spin_lock_bh(&txq->axq_lock);
1971
672840ac 1972 if (txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) {
f078f209
LR		 1973 struct ath_atx_tid *tid = ATH_AN_2_TID(an, txctl->tidno);
1974 if (ath_aggr_query(sc, an, txctl->tidno)) {
1975 /*
1976 * Try aggregation if it's a unicast data frame
1977 * and the destination is HT capable.
1978 */
1979 ath_tx_send_ampdu(sc, txq, tid, &bf_head, txctl);
1980 } else {
1981 /*
1982 * Send this frame as regular when ADDBA exchange
1983 * is neither complete nor pending.
1984 */
1985 ath_tx_send_normal(sc, txq, tid, &bf_head);
1986 }
1987 } else {
1988 bf->bf_lastbf = bf;
1989 bf->bf_nframes = 1;
1990 ath_buf_set_rate(sc, bf);
1991
1992 if (ieee80211_is_back_req(fc)) {
1993 /* This is required for resuming tid
1994 * during BAR completion */
1995 bf->bf_tidno = txctl->tidno;
1996 }
1997
e022edbd 1998 ath_tx_txqaddbuf(sc, txq, &bf_head);
f078f209
LR		 1999 }
2000 spin_unlock_bh(&txq->axq_lock);
2001 return 0;
2002}
2003
2004static void xmit_map_sg(struct ath_softc *sc,
2005 struct sk_buff *skb,
f078f209
LR		 2006 struct ath_tx_control *txctl)
2007{
2008 struct ath_xmit_status tx_status;
2009 struct ath_atx_tid *tid;
2010 struct scatterlist sg;
2011
ff9b662d
S		 2012 txctl->dmacontext = pci_map_single(sc->pdev, skb->data,
2013 skb->len, PCI_DMA_TODEVICE);
f078f209
LR		 2014
2015 /* setup S/G list */
2016 memset(&sg, 0, sizeof(struct scatterlist));
ff9b662d 2017 sg_dma_address(&sg) = txctl->dmacontext;
f078f209
LR		 2018 sg_dma_len(&sg) = skb->len;
2019
2020 if (ath_tx_start_dma(sc, skb, &sg, 1, txctl) != 0) {
2021 /*
2022 * We have to do drop frame here.
2023 */
ff9b662d
S		 2024 pci_unmap_single(sc->pdev, txctl->dmacontext,
2025 skb->len, PCI_DMA_TODEVICE);
f078f209
LR		 2026
2027 tx_status.retries = 0;
2028 tx_status.flags = ATH_TX_ERROR;
2029
672840ac 2030 if (txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) {
f078f209
LR		 2031 /* Reclaim the seqno. */
2032 tid = ATH_AN_2_TID((struct ath_node *)
2033 txctl->an, txctl->tidno);
2034 DECR(tid->seq_next, IEEE80211_SEQ_MAX);
2035 }
2036 ath_tx_complete(sc, skb, &tx_status, txctl->an);
2037 }
2038}
2039
2040/* Initialize TX queue and h/w */
2041
2042int ath_tx_init(struct ath_softc *sc, int nbufs)
2043{
2044 int error = 0;
2045
2046 do {
2047 spin_lock_init(&sc->sc_txbuflock);
2048
2049 /* Setup tx descriptors */
2050 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
556bb8f1 2051 "tx", nbufs, 1);
f078f209
LR		 2052 if (error != 0) {
2053 DPRINTF(sc, ATH_DBG_FATAL,
2054 "%s: failed to allocate tx descriptors: %d\n",
2055 __func__, error);
2056 break;
2057 }
2058
2059 /* XXX allocate beacon state together with vap */
2060 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
2061 "beacon", ATH_BCBUF, 1);
2062 if (error != 0) {
2063 DPRINTF(sc, ATH_DBG_FATAL,
2064 "%s: failed to allocate "
2065 "beacon descripotrs: %d\n",
2066 __func__, error);
2067 break;
2068 }
2069
2070 } while (0);
2071
2072 if (error != 0)
2073 ath_tx_cleanup(sc);
2074
2075 return error;
2076}
2077
2078/* Reclaim all tx queue resources */
2079
2080int ath_tx_cleanup(struct ath_softc *sc)
2081{
2082 /* cleanup beacon descriptors */
2083 if (sc->sc_bdma.dd_desc_len != 0)
2084 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
2085
2086 /* cleanup tx descriptors */
2087 if (sc->sc_txdma.dd_desc_len != 0)
2088 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2089
2090 return 0;
2091}
2092
2093/* Setup a h/w transmit queue */
2094
2095struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
2096{
2097 struct ath_hal *ah = sc->sc_ah;
ea9880fb 2098 struct ath9k_tx_queue_info qi;
f078f209
LR		 2099 int qnum;
2100
0345f37b 2101 memset(&qi, 0, sizeof(qi));
f078f209
LR		 2102 qi.tqi_subtype = subtype;
2103 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
2104 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
2105 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
ea9880fb 2106 qi.tqi_physCompBuf = 0;
f078f209
LR		 2107
2108 /*
2109 * Enable interrupts only for EOL and DESC conditions.
2110 * We mark tx descriptors to receive a DESC interrupt
2111 * when a tx queue gets deep; otherwise waiting for the
2112 * EOL to reap descriptors. Note that this is done to
2113 * reduce interrupt load and this only defers reaping
2114 * descriptors, never transmitting frames. Aside from
2115 * reducing interrupts this also permits more concurrency.
2116 * The only potential downside is if the tx queue backs
2117 * up in which case the top half of the kernel may backup
2118 * due to a lack of tx descriptors.
2119 *
2120 * The UAPSD queue is an exception, since we take a desc-
2121 * based intr on the EOSP frames.
2122 */
2123 if (qtype == ATH9K_TX_QUEUE_UAPSD)
2124 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
2125 else
2126 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
2127 TXQ_FLAG_TXDESCINT_ENABLE;
2128 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
2129 if (qnum == -1) {
2130 /*
2131 * NB: don't print a message, this happens
2132 * normally on parts with too few tx queues
2133 */
2134 return NULL;
2135 }
2136 if (qnum >= ARRAY_SIZE(sc->sc_txq)) {
2137 DPRINTF(sc, ATH_DBG_FATAL,
2138 "%s: hal qnum %u out of range, max %u!\n",
2139 __func__, qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq));
2140 ath9k_hw_releasetxqueue(ah, qnum);
2141 return NULL;
2142 }
2143 if (!ATH_TXQ_SETUP(sc, qnum)) {
2144 struct ath_txq *txq = &sc->sc_txq[qnum];
2145
2146 txq->axq_qnum = qnum;
2147 txq->axq_link = NULL;
2148 INIT_LIST_HEAD(&txq->axq_q);
2149 INIT_LIST_HEAD(&txq->axq_acq);
2150 spin_lock_init(&txq->axq_lock);
2151 txq->axq_depth = 0;
2152 txq->axq_aggr_depth = 0;
2153 txq->axq_totalqueued = 0;
2154 txq->axq_intrcnt = 0;
2155 txq->axq_linkbuf = NULL;
2156 sc->sc_txqsetup |= 1<<qnum;
2157 }
2158 return &sc->sc_txq[qnum];
2159}
2160
2161/* Reclaim resources for a setup queue */
2162
2163void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
2164{
2165 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
2166 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
2167}
2168
2169/*
2170 * Setup a hardware data transmit queue for the specified
2171 * access control. The hal may not support all requested
2172 * queues in which case it will return a reference to a
2173 * previously setup queue. We record the mapping from ac's
2174 * to h/w queues for use by ath_tx_start and also track
2175 * the set of h/w queues being used to optimize work in the
2176 * transmit interrupt handler and related routines.
2177 */
2178
2179int ath_tx_setup(struct ath_softc *sc, int haltype)
2180{
2181 struct ath_txq *txq;
2182
2183 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
2184 DPRINTF(sc, ATH_DBG_FATAL,
2185 "%s: HAL AC %u out of range, max %zu!\n",
2186 __func__, haltype, ARRAY_SIZE(sc->sc_haltype2q));
2187 return 0;
2188 }
2189 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
2190 if (txq != NULL) {
2191 sc->sc_haltype2q[haltype] = txq->axq_qnum;
2192 return 1;
2193 } else
2194 return 0;
2195}
2196
2197int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
2198{
2199 int qnum;
2200
2201 switch (qtype) {
2202 case ATH9K_TX_QUEUE_DATA:
2203 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
2204 DPRINTF(sc, ATH_DBG_FATAL,
2205 "%s: HAL AC %u out of range, max %zu!\n",
2206 __func__,
2207 haltype, ARRAY_SIZE(sc->sc_haltype2q));
2208 return -1;
2209 }
2210 qnum = sc->sc_haltype2q[haltype];
2211 break;
2212 case ATH9K_TX_QUEUE_BEACON:
2213 qnum = sc->sc_bhalq;
2214 break;
2215 case ATH9K_TX_QUEUE_CAB:
2216 qnum = sc->sc_cabq->axq_qnum;
2217 break;
2218 default:
2219 qnum = -1;
2220 }
2221 return qnum;
2222}
2223
2224/* Update parameters for a transmit queue */
2225
ea9880fb
S		 2226int ath_txq_update(struct ath_softc *sc, int qnum,
2227 struct ath9k_tx_queue_info *qinfo)
f078f209
LR		 2228{
2229 struct ath_hal *ah = sc->sc_ah;
2230 int error = 0;
ea9880fb 2231 struct ath9k_tx_queue_info qi;
f078f209
LR		 2232
2233 if (qnum == sc->sc_bhalq) {
2234 /*
2235 * XXX: for beacon queue, we just save the parameter.
2236 * It will be picked up by ath_beaconq_config when
2237 * it's necessary.
2238 */
ea9880fb 2239 sc->sc_beacon_qi = *qinfo;
f078f209
LR		 2240 return 0;
2241 }
2242
2243 ASSERT(sc->sc_txq[qnum].axq_qnum == qnum);
2244
ea9880fb
S		 2245 ath9k_hw_get_txq_props(ah, qnum, &qi);
2246 qi.tqi_aifs = qinfo->tqi_aifs;
2247 qi.tqi_cwmin = qinfo->tqi_cwmin;
2248 qi.tqi_cwmax = qinfo->tqi_cwmax;
2249 qi.tqi_burstTime = qinfo->tqi_burstTime;
2250 qi.tqi_readyTime = qinfo->tqi_readyTime;
f078f209 2251
ea9880fb 2252 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
f078f209
LR		 2253 DPRINTF(sc, ATH_DBG_FATAL,
2254 "%s: unable to update hardware queue %u!\n",
2255 __func__, qnum);
2256 error = -EIO;
2257 } else {
2258 ath9k_hw_resettxqueue(ah, qnum); /* push to h/w */
2259 }
2260
2261 return error;
2262}
2263
2264int ath_cabq_update(struct ath_softc *sc)
2265{
ea9880fb 2266 struct ath9k_tx_queue_info qi;
f078f209
LR		 2267 int qnum = sc->sc_cabq->axq_qnum;
2268 struct ath_beacon_config conf;
2269
ea9880fb 2270 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
f078f209
LR		 2271 /*
2272 * Ensure the readytime % is within the bounds.
2273 */
2274 if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
2275 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
2276 else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
2277 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
2278
2279 ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf);
2280 qi.tqi_readyTime =
2281 (conf.beacon_interval * sc->sc_config.cabqReadytime) / 100;
2282 ath_txq_update(sc, qnum, &qi);
2283
2284 return 0;
2285}
2286
2287int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb)
2288{
2289 struct ath_tx_control txctl;
2290 int error = 0;
2291
e022edbd 2292 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209
LR		 2293 error = ath_tx_prepare(sc, skb, &txctl);
2294 if (error == 0)
2295 /*
2296 * Start DMA mapping.
2297 * ath_tx_start_dma() will be called either synchronously
2298 * or asynchrounsly once DMA is complete.
2299 */
ff9b662d 2300 xmit_map_sg(sc, skb, &txctl);
f078f209
LR		 2301 else
2302 ath_node_put(sc, txctl.an, ATH9K_BH_STATUS_CHANGE);
2303
2304 /* failed packets will be dropped by the caller */
2305 return error;
2306}
2307
2308/* Deferred processing of transmit interrupt */
2309
2310void ath_tx_tasklet(struct ath_softc *sc)
2311{
1fe1132b 2312 int i;
f078f209
LR		 2313 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2314
2315 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2316
2317 /*
2318 * Process each active queue.
2319 */
2320 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2321 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
1fe1132b 2322 ath_tx_processq(sc, &sc->sc_txq[i]);
f078f209 2323 }
f078f209
LR		 2324}
2325
2326void ath_tx_draintxq(struct ath_softc *sc,
2327 struct ath_txq *txq, bool retry_tx)
2328{
2329 struct ath_buf *bf, *lastbf;
2330 struct list_head bf_head;
2331
2332 INIT_LIST_HEAD(&bf_head);
2333
2334 /*
2335 * NB: this assumes output has been stopped and
2336 * we do not need to block ath_tx_tasklet
2337 */
2338 for (;;) {
2339 spin_lock_bh(&txq->axq_lock);
2340
2341 if (list_empty(&txq->axq_q)) {
2342 txq->axq_link = NULL;
2343 txq->axq_linkbuf = NULL;
2344 spin_unlock_bh(&txq->axq_lock);
2345 break;
2346 }
2347
2348 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2349
2350 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
2351 list_del(&bf->list);
2352 spin_unlock_bh(&txq->axq_lock);
2353
2354 spin_lock_bh(&sc->sc_txbuflock);
2355 list_add_tail(&bf->list, &sc->sc_txbuf);
2356 spin_unlock_bh(&sc->sc_txbuflock);
2357 continue;
2358 }
2359
2360 lastbf = bf->bf_lastbf;
2361 if (!retry_tx)
2362 lastbf->bf_desc->ds_txstat.ts_flags =
2363 ATH9K_TX_SW_ABORTED;
2364
2365 /* remove ath_buf's of the same mpdu from txq */
2366 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
2367 txq->axq_depth--;
2368
2369 spin_unlock_bh(&txq->axq_lock);
2370
cd3d39a6 2371 if (bf_isampdu(bf))
f078f209
LR		 2372 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, 0);
2373 else
2374 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2375 }
2376
2377 /* flush any pending frames if aggregation is enabled */
672840ac 2378 if (sc->sc_flags & SC_OP_TXAGGR) {
f078f209
LR		 2379 if (!retry_tx) {
2380 spin_lock_bh(&txq->axq_lock);
2381 ath_txq_drain_pending_buffers(sc, txq,
2382 ATH9K_BH_STATUS_CHANGE);
2383 spin_unlock_bh(&txq->axq_lock);
2384 }
2385 }
2386}
2387
2388/* Drain the transmit queues and reclaim resources */
2389
2390void ath_draintxq(struct ath_softc *sc, bool retry_tx)
2391{
2392 /* stop beacon queue. The beacon will be freed when
2393 * we go to INIT state */
672840ac 2394 if (!(sc->sc_flags & SC_OP_INVALID)) {
f078f209
LR		 2395 (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2396 DPRINTF(sc, ATH_DBG_XMIT, "%s: beacon queue %x\n", __func__,
2397 ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq));
2398 }
2399
2400 ath_drain_txdataq(sc, retry_tx);
2401}
2402
2403u32 ath_txq_depth(struct ath_softc *sc, int qnum)
2404{
2405 return sc->sc_txq[qnum].axq_depth;
2406}
2407
2408u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum)
2409{
2410 return sc->sc_txq[qnum].axq_aggr_depth;
2411}
2412
2413/* Check if an ADDBA is required. A valid node must be passed. */
2414enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
2415 struct ath_node *an,
2416 u8 tidno)
2417{
2418 struct ath_atx_tid *txtid;
f078f209 2419
672840ac 2420 if (!(sc->sc_flags & SC_OP_TXAGGR))
f078f209
LR		 2421 return AGGR_NOT_REQUIRED;
2422
2423 /* ADDBA exchange must be completed before sending aggregates */
2424 txtid = ATH_AN_2_TID(an, tidno);
2425
2426 if (txtid->addba_exchangecomplete)
2427 return AGGR_EXCHANGE_DONE;
2428
2429 if (txtid->cleanup_inprogress)
2430 return AGGR_CLEANUP_PROGRESS;
2431
2432 if (txtid->addba_exchangeinprogress)
2433 return AGGR_EXCHANGE_PROGRESS;
2434
2435 if (!txtid->addba_exchangecomplete) {
2436 if (!txtid->addba_exchangeinprogress &&
2437 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
2438 txtid->addba_exchangeattempts++;
2439 return AGGR_REQUIRED;
2440 }
2441 }
2442
2443 return AGGR_NOT_REQUIRED;
2444}
2445
2446/* Start TX aggregation */
2447
2448int ath_tx_aggr_start(struct ath_softc *sc,
2449 const u8 *addr,
2450 u16 tid,
2451 u16 *ssn)
2452{
2453 struct ath_atx_tid *txtid;
2454 struct ath_node *an;
2455
2456 spin_lock_bh(&sc->node_lock);
2457 an = ath_node_find(sc, (u8 *) addr);
2458 spin_unlock_bh(&sc->node_lock);
2459
2460 if (!an) {
2461 DPRINTF(sc, ATH_DBG_AGGR,
2462 "%s: Node not found to initialize "
2463 "TX aggregation\n", __func__);
2464 return -1;
2465 }
2466
672840ac 2467 if (sc->sc_flags & SC_OP_TXAGGR) {
f078f209
LR		 2468 txtid = ATH_AN_2_TID(an, tid);
2469 txtid->addba_exchangeinprogress = 1;
2470 ath_tx_pause_tid(sc, txtid);
2471 }
2472
2473 return 0;
2474}
2475
2476/* Stop tx aggregation */
2477
2478int ath_tx_aggr_stop(struct ath_softc *sc,
2479 const u8 *addr,
2480 u16 tid)
2481{
2482 struct ath_node *an;
2483
2484 spin_lock_bh(&sc->node_lock);
2485 an = ath_node_find(sc, (u8 *) addr);
2486 spin_unlock_bh(&sc->node_lock);
2487
2488 if (!an) {
2489 DPRINTF(sc, ATH_DBG_AGGR,
2490 "%s: TX aggr stop for non-existent node\n", __func__);
2491 return -1;
2492 }
2493
2494 ath_tx_aggr_teardown(sc, an, tid);
2495 return 0;
2496}
2497
2498/*
2499 * Performs transmit side cleanup when TID changes from aggregated to
2500 * unaggregated.
2501 * - Pause the TID and mark cleanup in progress
2502 * - Discard all retry frames from the s/w queue.
2503 */
2504
2505void ath_tx_aggr_teardown(struct ath_softc *sc,
2506 struct ath_node *an, u8 tid)
2507{
2508 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
2509 struct ath_txq *txq = &sc->sc_txq[txtid->ac->qnum];
2510 struct ath_buf *bf;
2511 struct list_head bf_head;
2512 INIT_LIST_HEAD(&bf_head);
2513
2514 DPRINTF(sc, ATH_DBG_AGGR, "%s: teardown TX aggregation\n", __func__);
2515
2516 if (txtid->cleanup_inprogress) /* cleanup is in progress */
2517 return;
2518
2519 if (!txtid->addba_exchangecomplete) {
2520 txtid->addba_exchangeattempts = 0;
2521 return;
2522 }
2523
2524 /* TID must be paused first */
2525 ath_tx_pause_tid(sc, txtid);
2526
2527 /* drop all software retried frames and mark this TID */
2528 spin_lock_bh(&txq->axq_lock);
2529 while (!list_empty(&txtid->buf_q)) {
2530 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
cd3d39a6 2531 if (!bf_isretried(bf)) {
f078f209
LR		 2532 /*
2533 * NB: it's based on the assumption that
2534 * software retried frame will always stay
2535 * at the head of software queue.
2536 */
2537 break;
2538 }
2539 list_cut_position(&bf_head,
2540 &txtid->buf_q, &bf->bf_lastfrm->list);
2541 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
2542
2543 /* complete this sub-frame */
2544 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2545 }
2546
2547 if (txtid->baw_head != txtid->baw_tail) {
2548 spin_unlock_bh(&txq->axq_lock);
2549 txtid->cleanup_inprogress = true;
2550 } else {
2551 txtid->addba_exchangecomplete = 0;
2552 txtid->addba_exchangeattempts = 0;
2553 spin_unlock_bh(&txq->axq_lock);
2554 ath_tx_flush_tid(sc, txtid);
2555 }
2556}
2557
2558/*
2559 * Tx scheduling logic
2560 * NB: must be called with txq lock held
2561 */
2562
2563void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
2564{
2565 struct ath_atx_ac *ac;
2566 struct ath_atx_tid *tid;
2567
2568 /* nothing to schedule */
2569 if (list_empty(&txq->axq_acq))
2570 return;
2571 /*
2572 * get the first node/ac pair on the queue
2573 */
2574 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
2575 list_del(&ac->list);
2576 ac->sched = false;
2577
2578 /*
2579 * process a single tid per destination
2580 */
2581 do {
2582 /* nothing to schedule */
2583 if (list_empty(&ac->tid_q))
2584 return;
2585
2586 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
2587 list_del(&tid->list);
2588 tid->sched = false;
2589
2590 if (tid->paused) /* check next tid to keep h/w busy */
2591 continue;
2592
2593 if (!(tid->an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) ||
2594 ((txq->axq_depth % 2) == 0)) {
2595 ath_tx_sched_aggr(sc, txq, tid);
2596 }
2597
2598 /*
2599 * add tid to round-robin queue if more frames
2600 * are pending for the tid
2601 */
2602 if (!list_empty(&tid->buf_q))
2603 ath_tx_queue_tid(txq, tid);
2604
2605 /* only schedule one TID at a time */
2606 break;
2607 } while (!list_empty(&ac->tid_q));
2608
2609 /*
2610 * schedule AC if more TIDs need processing
2611 */
2612 if (!list_empty(&ac->tid_q)) {
2613 /*
2614 * add dest ac to txq if not already added
2615 */
2616 if (!ac->sched) {
2617 ac->sched = true;
2618 list_add_tail(&ac->list, &txq->axq_acq);
2619 }
2620 }
2621}
2622
2623/* Initialize per-node transmit state */
2624
2625void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2626{
672840ac 2627 if (sc->sc_flags & SC_OP_TXAGGR) {
f078f209
LR		 2628 struct ath_atx_tid *tid;
2629 struct ath_atx_ac *ac;
2630 int tidno, acno;
2631
2632 sc->sc_ht_info.maxampdu = ATH_AMPDU_LIMIT_DEFAULT;
2633
2634 /*
2635 * Init per tid tx state
2636 */
2637 for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
2638 tidno < WME_NUM_TID;
2639 tidno++, tid++) {
2640 tid->an = an;
2641 tid->tidno = tidno;
2642 tid->seq_start = tid->seq_next = 0;
2643 tid->baw_size = WME_MAX_BA;
2644 tid->baw_head = tid->baw_tail = 0;
2645 tid->sched = false;
2646 tid->paused = false;
2647 tid->cleanup_inprogress = false;
2648 INIT_LIST_HEAD(&tid->buf_q);
2649
2650 acno = TID_TO_WME_AC(tidno);
2651 tid->ac = &an->an_aggr.tx.ac[acno];
2652
2653 /* ADDBA state */
2654 tid->addba_exchangecomplete = 0;
2655 tid->addba_exchangeinprogress = 0;
2656 tid->addba_exchangeattempts = 0;
2657 }
2658
2659 /*
2660 * Init per ac tx state
2661 */
2662 for (acno = 0, ac = &an->an_aggr.tx.ac[acno];
2663 acno < WME_NUM_AC; acno++, ac++) {
2664 ac->sched = false;
2665 INIT_LIST_HEAD(&ac->tid_q);
2666
2667 switch (acno) {
2668 case WME_AC_BE:
2669 ac->qnum = ath_tx_get_qnum(sc,
2670 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2671 break;
2672 case WME_AC_BK:
2673 ac->qnum = ath_tx_get_qnum(sc,
2674 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2675 break;
2676 case WME_AC_VI:
2677 ac->qnum = ath_tx_get_qnum(sc,
2678 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2679 break;
2680 case WME_AC_VO:
2681 ac->qnum = ath_tx_get_qnum(sc,
2682 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2683 break;
2684 }
2685 }
2686 }
2687}
2688
2689/* Cleanupthe pending buffers for the node. */
2690
2691void ath_tx_node_cleanup(struct ath_softc *sc,
2692 struct ath_node *an, bool bh_flag)
2693{
2694 int i;
2695 struct ath_atx_ac *ac, *ac_tmp;
2696 struct ath_atx_tid *tid, *tid_tmp;
2697 struct ath_txq *txq;
2698 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2699 if (ATH_TXQ_SETUP(sc, i)) {
2700 txq = &sc->sc_txq[i];
2701
2702 if (likely(bh_flag))
2703 spin_lock_bh(&txq->axq_lock);
2704 else
2705 spin_lock(&txq->axq_lock);
2706
2707 list_for_each_entry_safe(ac,
2708 ac_tmp, &txq->axq_acq, list) {
2709 tid = list_first_entry(&ac->tid_q,
2710 struct ath_atx_tid, list);
2711 if (tid && tid->an != an)
2712 continue;
2713 list_del(&ac->list);
2714 ac->sched = false;
2715
2716 list_for_each_entry_safe(tid,
2717 tid_tmp, &ac->tid_q, list) {
2718 list_del(&tid->list);
2719 tid->sched = false;
2720 ath_tid_drain(sc, txq, tid, bh_flag);
2721 tid->addba_exchangecomplete = 0;
2722 tid->addba_exchangeattempts = 0;
2723 tid->cleanup_inprogress = false;
2724 }
2725 }
2726
2727 if (likely(bh_flag))
2728 spin_unlock_bh(&txq->axq_lock);
2729 else
2730 spin_unlock(&txq->axq_lock);
2731 }
2732 }
2733}
2734
2735/* Cleanup per node transmit state */
2736
2737void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an)
2738{
672840ac 2739 if (sc->sc_flags & SC_OP_TXAGGR) {
f078f209
LR		 2740 struct ath_atx_tid *tid;
2741 int tidno, i;
2742
2743 /* Init per tid rx state */
2744 for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
2745 tidno < WME_NUM_TID;
2746 tidno++, tid++) {
2747
2748 for (i = 0; i < ATH_TID_MAX_BUFS; i++)
2749 ASSERT(tid->tx_buf[i] == NULL);
2750 }
2751 }
2752}
e022edbd
JM		 2753
2754void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
2755{
2756 int hdrlen, padsize;
2757 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2758 struct ath_tx_control txctl;
2759
2760 /*
2761 * As a temporary workaround, assign seq# here; this will likely need
2762 * to be cleaned up to work better with Beacon transmission and virtual
2763 * BSSes.
2764 */
2765 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2766 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2767 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2768 sc->seq_no += 0x10;
2769 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2770 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
2771 }
2772
2773 /* Add the padding after the header if this is not already done */
2774 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2775 if (hdrlen & 3) {
2776 padsize = hdrlen % 4;
2777 if (skb_headroom(skb) < padsize) {
2778 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX CABQ padding "
2779 "failed\n", __func__);
2780 dev_kfree_skb_any(skb);
2781 return;
2782 }
2783 skb_push(skb, padsize);
2784 memmove(skb->data, skb->data + padsize, hdrlen);
2785 }
2786
2787 DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting CABQ packet, skb: %p\n",
2788 __func__,
2789 skb);
2790
2791 memset(&txctl, 0, sizeof(struct ath_tx_control));
2792 txctl.flags = ATH9K_TXDESC_CAB;
2793 if (ath_tx_prepare(sc, skb, &txctl) == 0) {
2794 /*
2795 * Start DMA mapping.
2796 * ath_tx_start_dma() will be called either synchronously
2797 * or asynchrounsly once DMA is complete.
2798 */
2799 xmit_map_sg(sc, skb, &txctl);
2800 } else {
2801 ath_node_put(sc, txctl.an, ATH9K_BH_STATUS_CHANGE);
2802 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX CABQ failed\n", __func__);
2803 dev_kfree_skb_any(skb);
2804 }
2805}
2806
Linux kernel - Deliverables
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