projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| e4d6b795 MB |
1 | #ifndef B43_H_ |
| 2 | #define B43_H_ | |
| 3 | ||
| 4 | #include <linux/kernel.h> | |
| 5 | #include <linux/spinlock.h> | |
| 6 | #include <linux/interrupt.h> | |
| 7 | #include <linux/hw_random.h> | |
| 3c65ab62 | 8 | #include <linux/bcma/bcma.h> |
| e4d6b795 MB |
9 | #include <linux/ssb/ssb.h> |
| 10 | #include <net/mac80211.h> | |
| 11 | ||
| 12 | #include "debugfs.h" | |
| 13 | #include "leds.h" | |
| 8e9f7529 | 14 | #include "rfkill.h" |
| 482f0538 | 15 | #include "bus.h" |
| e4d6b795 | 16 | #include "lo.h" |
| ef1a628d | 17 | #include "phy_common.h" |
| e4d6b795 | 18 | |
| 26bc783f MB |
19 | |
| 20 | /* The unique identifier of the firmware that's officially supported by | |
| 21 | * this driver version. */ | |
| 22 | #define B43_SUPPORTED_FIRMWARE_ID "FW13" | |
| 23 | ||
| 24 | ||
| e4d6b795 MB |
25 | #ifdef CONFIG_B43_DEBUG |
| 26 | # define B43_DEBUG 1 | |
| 27 | #else | |
| 28 | # define B43_DEBUG 0 | |
| 29 | #endif | |
| 30 | ||
| e4d6b795 MB |
31 | /* MMIO offsets */ |
| 32 | #define B43_MMIO_DMA0_REASON 0x20 | |
| 33 | #define B43_MMIO_DMA0_IRQ_MASK 0x24 | |
| 34 | #define B43_MMIO_DMA1_REASON 0x28 | |
| 35 | #define B43_MMIO_DMA1_IRQ_MASK 0x2C | |
| 36 | #define B43_MMIO_DMA2_REASON 0x30 | |
| 37 | #define B43_MMIO_DMA2_IRQ_MASK 0x34 | |
| 38 | #define B43_MMIO_DMA3_REASON 0x38 | |
| 39 | #define B43_MMIO_DMA3_IRQ_MASK 0x3C | |
| 40 | #define B43_MMIO_DMA4_REASON 0x40 | |
| 41 | #define B43_MMIO_DMA4_IRQ_MASK 0x44 | |
| 42 | #define B43_MMIO_DMA5_REASON 0x48 | |
| 43 | #define B43_MMIO_DMA5_IRQ_MASK 0x4C | |
| aa6c7ae2 MB |
44 | #define B43_MMIO_MACCTL 0x120 /* MAC control */ |
| 45 | #define B43_MMIO_MACCMD 0x124 /* MAC command */ | |
| e4d6b795 MB |
46 | #define B43_MMIO_GEN_IRQ_REASON 0x128 |
| 47 | #define B43_MMIO_GEN_IRQ_MASK 0x12C | |
| 48 | #define B43_MMIO_RAM_CONTROL 0x130 | |
| 49 | #define B43_MMIO_RAM_DATA 0x134 | |
| 50 | #define B43_MMIO_PS_STATUS 0x140 | |
| 51 | #define B43_MMIO_RADIO_HWENABLED_HI 0x158 | |
| 52 | #define B43_MMIO_SHM_CONTROL 0x160 | |
| 53 | #define B43_MMIO_SHM_DATA 0x164 | |
| 54 | #define B43_MMIO_SHM_DATA_UNALIGNED 0x166 | |
| 55 | #define B43_MMIO_XMITSTAT_0 0x170 | |
| 56 | #define B43_MMIO_XMITSTAT_1 0x174 | |
| 57 | #define B43_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */ | |
| 58 | #define B43_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */ | |
| f3dd3fcc MB |
59 | #define B43_MMIO_TSF_CFP_REP 0x188 |
| 60 | #define B43_MMIO_TSF_CFP_START 0x18C | |
| 61 | #define B43_MMIO_TSF_CFP_MAXDUR 0x190 | |
| e4d6b795 MB |
62 | |
| 63 | /* 32-bit DMA */ | |
| 64 | #define B43_MMIO_DMA32_BASE0 0x200 | |
| 65 | #define B43_MMIO_DMA32_BASE1 0x220 | |
| 66 | #define B43_MMIO_DMA32_BASE2 0x240 | |
| 67 | #define B43_MMIO_DMA32_BASE3 0x260 | |
| 68 | #define B43_MMIO_DMA32_BASE4 0x280 | |
| 69 | #define B43_MMIO_DMA32_BASE5 0x2A0 | |
| 70 | /* 64-bit DMA */ | |
| 71 | #define B43_MMIO_DMA64_BASE0 0x200 | |
| 72 | #define B43_MMIO_DMA64_BASE1 0x240 | |
| 73 | #define B43_MMIO_DMA64_BASE2 0x280 | |
| 74 | #define B43_MMIO_DMA64_BASE3 0x2C0 | |
| 75 | #define B43_MMIO_DMA64_BASE4 0x300 | |
| 76 | #define B43_MMIO_DMA64_BASE5 0x340 | |
| e4d6b795 | 77 | |
| 5100d5ac MB |
78 | /* PIO on core rev < 11 */ |
| 79 | #define B43_MMIO_PIO_BASE0 0x300 | |
| 80 | #define B43_MMIO_PIO_BASE1 0x310 | |
| 81 | #define B43_MMIO_PIO_BASE2 0x320 | |
| 82 | #define B43_MMIO_PIO_BASE3 0x330 | |
| 83 | #define B43_MMIO_PIO_BASE4 0x340 | |
| 84 | #define B43_MMIO_PIO_BASE5 0x350 | |
| 85 | #define B43_MMIO_PIO_BASE6 0x360 | |
| 86 | #define B43_MMIO_PIO_BASE7 0x370 | |
| 87 | /* PIO on core rev >= 11 */ | |
| 88 | #define B43_MMIO_PIO11_BASE0 0x200 | |
| 89 | #define B43_MMIO_PIO11_BASE1 0x240 | |
| 90 | #define B43_MMIO_PIO11_BASE2 0x280 | |
| 91 | #define B43_MMIO_PIO11_BASE3 0x2C0 | |
| 92 | #define B43_MMIO_PIO11_BASE4 0x300 | |
| 93 | #define B43_MMIO_PIO11_BASE5 0x340 | |
| 94 | ||
| 443c1a24 RM |
95 | #define B43_MMIO_RADIO24_CONTROL 0x3D8 /* core rev >= 24 only */ |
| 96 | #define B43_MMIO_RADIO24_DATA 0x3DA /* core rev >= 24 only */ | |
| e4d6b795 MB |
97 | #define B43_MMIO_PHY_VER 0x3E0 |
| 98 | #define B43_MMIO_PHY_RADIO 0x3E2 | |
| 99 | #define B43_MMIO_PHY0 0x3E6 | |
| 100 | #define B43_MMIO_ANTENNA 0x3E8 | |
| 101 | #define B43_MMIO_CHANNEL 0x3F0 | |
| 102 | #define B43_MMIO_CHANNEL_EXT 0x3F4 | |
| 103 | #define B43_MMIO_RADIO_CONTROL 0x3F6 | |
| 104 | #define B43_MMIO_RADIO_DATA_HIGH 0x3F8 | |
| 105 | #define B43_MMIO_RADIO_DATA_LOW 0x3FA | |
| 106 | #define B43_MMIO_PHY_CONTROL 0x3FC | |
| 107 | #define B43_MMIO_PHY_DATA 0x3FE | |
| 108 | #define B43_MMIO_MACFILTER_CONTROL 0x420 | |
| 109 | #define B43_MMIO_MACFILTER_DATA 0x422 | |
| 110 | #define B43_MMIO_RCMTA_COUNT 0x43C | |
| 9734485c | 111 | #define B43_MMIO_PSM_PHY_HDR 0x492 |
| e4d6b795 MB |
112 | #define B43_MMIO_RADIO_HWENABLED_LO 0x49A |
| 113 | #define B43_MMIO_GPIO_CONTROL 0x49C | |
| 114 | #define B43_MMIO_GPIO_MASK 0x49E | |
| f3dd3fcc MB |
115 | #define B43_MMIO_TSF_CFP_START_LOW 0x604 |
| 116 | #define B43_MMIO_TSF_CFP_START_HIGH 0x606 | |
| d59f720d | 117 | #define B43_MMIO_TSF_CFP_PRETBTT 0x612 |
| e4d6b795 MB |
118 | #define B43_MMIO_TSF_0 0x632 /* core rev < 3 only */ |
| 119 | #define B43_MMIO_TSF_1 0x634 /* core rev < 3 only */ | |
| 120 | #define B43_MMIO_TSF_2 0x636 /* core rev < 3 only */ | |
| 121 | #define B43_MMIO_TSF_3 0x638 /* core rev < 3 only */ | |
| 122 | #define B43_MMIO_RNG 0x65A | |
| b6c3f5be | 123 | #define B43_MMIO_IFSSLOT 0x684 /* Interframe slot time */ |
| e6f5b934 MB |
124 | #define B43_MMIO_IFSCTL 0x688 /* Interframe space control */ |
| 125 | #define B43_MMIO_IFSCTL_USE_EDCF 0x0004 | |
| e4d6b795 | 126 | #define B43_MMIO_POWERUP_DELAY 0x6A8 |
| ce1a9ee3 MB |
127 | #define B43_MMIO_BTCOEX_CTL 0x6B4 /* Bluetooth Coexistence Control */ |
| 128 | #define B43_MMIO_BTCOEX_STAT 0x6B6 /* Bluetooth Coexistence Status */ | |
| 129 | #define B43_MMIO_BTCOEX_TXCTL 0x6B8 /* Bluetooth Coexistence Transmit Control */ | |
| e4d6b795 MB |
130 | |
| 131 | /* SPROM boardflags_lo values */ | |
| 132 | #define B43_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */ | |
| 133 | #define B43_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */ | |
| 134 | #define B43_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */ | |
| 135 | #define B43_BFL_RSSI 0x0008 /* software calculates nrssi slope. */ | |
| 136 | #define B43_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */ | |
| 137 | #define B43_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */ | |
| 138 | #define B43_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */ | |
| 139 | #define B43_BFL_ENETADM 0x0080 /* has ADMtek switch */ | |
| 140 | #define B43_BFL_ENETVLAN 0x0100 /* can do vlan */ | |
| 141 | #define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */ | |
| 142 | #define B43_BFL_NOPCI 0x0400 /* leaves PCI floating */ | |
| 143 | #define B43_BFL_FEM 0x0800 /* supports the Front End Module */ | |
| 144 | #define B43_BFL_EXTLNA 0x1000 /* has an external LNA */ | |
| 145 | #define B43_BFL_HGPA 0x2000 /* had high gain PA */ | |
| 146 | #define B43_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */ | |
| 147 | #define B43_BFL_ALTIQ 0x8000 /* alternate I/Q settings */ | |
| 148 | ||
| 738f0f43 GS |
149 | /* SPROM boardflags_hi values */ |
| 150 | #define B43_BFH_NOPA 0x0001 /* has no PA */ | |
| 151 | #define B43_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */ | |
| 152 | #define B43_BFH_PAREF 0x0004 /* uses the PARef LDO */ | |
| 153 | #define B43_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared | |
| 154 | * with bluetooth */ | |
| 155 | #define B43_BFH_PHASESHIFT 0x0010 /* can support phase shifter */ | |
| 156 | #define B43_BFH_BUCKBOOST 0x0020 /* has buck/booster */ | |
| 157 | #define B43_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna | |
| 158 | * with bluetooth */ | |
| 159 | ||
| 7e6da2bf RM |
160 | /* SPROM boardflags2_lo values */ |
| 161 | #define B43_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */ | |
| 162 | #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */ | |
| 163 | #define B43_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */ | |
| 164 | #define B43_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */ | |
| 165 | #define B43_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */ | |
| 166 | #define B43_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */ | |
| 167 | #define B43_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */ | |
| 168 | #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */ | |
| 169 | #define B43_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */ | |
| 170 | #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */ | |
| 171 | #define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */ | |
| 172 | ||
| e4d6b795 MB |
173 | /* GPIO register offset, in both ChipCommon and PCI core. */ |
| 174 | #define B43_GPIO_CONTROL 0x6c | |
| 175 | ||
| 176 | /* SHM Routing */ | |
| 177 | enum { | |
| 178 | B43_SHM_UCODE, /* Microcode memory */ | |
| 179 | B43_SHM_SHARED, /* Shared memory */ | |
| 180 | B43_SHM_SCRATCH, /* Scratch memory */ | |
| 181 | B43_SHM_HW, /* Internal hardware register */ | |
| 182 | B43_SHM_RCMTA, /* Receive match transmitter address (rev >= 5 only) */ | |
| 183 | }; | |
| 184 | /* SHM Routing modifiers */ | |
| 185 | #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */ | |
| 186 | #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */ | |
| 187 | #define B43_SHM_AUTOINC_RW (B43_SHM_AUTOINC_R | \ | |
| 188 | B43_SHM_AUTOINC_W) | |
| 189 | ||
| 190 | /* Misc SHM_SHARED offsets */ | |
| 191 | #define B43_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */ | |
| 192 | #define B43_SHM_SH_PCTLWDPOS 0x0008 | |
| 193 | #define B43_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */ | |
| 403a3a13 | 194 | #define B43_SHM_SH_FWCAPA 0x0042 /* Firmware capabilities (Opensource firmware only) */ |
| e4d6b795 MB |
195 | #define B43_SHM_SH_PHYVER 0x0050 /* PHY version */ |
| 196 | #define B43_SHM_SH_PHYTYPE 0x0052 /* PHY type */ | |
| 197 | #define B43_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */ | |
| 198 | #define B43_SHM_SH_HOSTFLO 0x005E /* Hostflags for ucode options (low) */ | |
| 35f0d354 MB |
199 | #define B43_SHM_SH_HOSTFMI 0x0060 /* Hostflags for ucode options (middle) */ |
| 200 | #define B43_SHM_SH_HOSTFHI 0x0062 /* Hostflags for ucode options (high) */ | |
| e4d6b795 MB |
201 | #define B43_SHM_SH_RFATT 0x0064 /* Current radio attenuation value */ |
| 202 | #define B43_SHM_SH_RADAR 0x0066 /* Radar register */ | |
| 203 | #define B43_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */ | |
| 204 | #define B43_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */ | |
| 205 | #define B43_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */ | |
| 106cb09a RM |
206 | #define B43_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5 Ghz channel */ |
| 207 | #define B43_SHM_SH_CHAN_40MHZ 0x0200 /* Bit set, if 40 Mhz channel width */ | |
| e4d6b795 | 208 | #define B43_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */ |
| 18c8adeb MB |
209 | /* TSSI information */ |
| 210 | #define B43_SHM_SH_TSSI_CCK 0x0058 /* TSSI for last 4 CCK frames (32bit) */ | |
| 211 | #define B43_SHM_SH_TSSI_OFDM_A 0x0068 /* TSSI for last 4 OFDM frames (32bit) */ | |
| 212 | #define B43_SHM_SH_TSSI_OFDM_G 0x0070 /* TSSI for last 4 OFDM frames (32bit) */ | |
| 213 | #define B43_TSSI_MAX 0x7F /* Max value for one TSSI value */ | |
| e4d6b795 MB |
214 | /* SHM_SHARED TX FIFO variables */ |
| 215 | #define B43_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */ | |
| 216 | #define B43_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */ | |
| 217 | #define B43_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */ | |
| 218 | #define B43_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */ | |
| 219 | /* SHM_SHARED background noise */ | |
| 220 | #define B43_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */ | |
| 221 | #define B43_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */ | |
| 222 | #define B43_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */ | |
| 223 | /* SHM_SHARED crypto engine */ | |
| 224 | #define B43_SHM_SH_DEFAULTIV 0x003C /* Default IV location */ | |
| 225 | #define B43_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */ | |
| 226 | #define B43_SHM_SH_KTP 0x0056 /* Key table pointer */ | |
| 227 | #define B43_SHM_SH_TKIPTSCTTAK 0x0318 | |
| 228 | #define B43_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */ | |
| 229 | #define B43_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */ | |
| 230 | /* SHM_SHARED WME variables */ | |
| 231 | #define B43_SHM_SH_EDCFSTAT 0x000E /* EDCF status */ | |
| 232 | #define B43_SHM_SH_TXFCUR 0x0030 /* TXF current index */ | |
| 233 | #define B43_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */ | |
| 234 | /* SHM_SHARED powersave mode related */ | |
| 235 | #define B43_SHM_SH_SLOTT 0x0010 /* Slot time */ | |
| 236 | #define B43_SHM_SH_DTIMPER 0x0012 /* DTIM period */ | |
| 237 | #define B43_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */ | |
| 280d0e16 | 238 | /* SHM_SHARED beacon/AP variables */ |
| e4d6b795 MB |
239 | #define B43_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */ |
| 240 | #define B43_SHM_SH_BTL1 0x001A /* Beacon template length 1 */ | |
| 241 | #define B43_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */ | |
| 242 | #define B43_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */ | |
| 280d0e16 MB |
243 | #define B43_SHM_SH_DTIMP 0x0012 /* DTIP period */ |
| 244 | #define B43_SHM_SH_MCASTCOOKIE 0x00A8 /* Last bcast/mcast frame ID */ | |
| e4d6b795 MB |
245 | #define B43_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */ |
| 246 | #define B43_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */ | |
| 247 | #define B43_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */ | |
| 280d0e16 | 248 | #define B43_SHM_SH_EXTNPHYCTL 0x00B0 /* Extended bytes for beacon PHY control (N) */ |
| e4d6b795 MB |
249 | /* SHM_SHARED ACK/CTS control */ |
| 250 | #define B43_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */ | |
| 251 | /* SHM_SHARED probe response variables */ | |
| 252 | #define B43_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */ | |
| 253 | #define B43_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */ | |
| 254 | #define B43_SHM_SH_PRTLEN 0x004A /* Probe Response template length */ | |
| 255 | #define B43_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */ | |
| 256 | #define B43_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */ | |
| 257 | /* SHM_SHARED rate tables */ | |
| 258 | #define B43_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */ | |
| 259 | #define B43_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */ | |
| 260 | #define B43_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */ | |
| 261 | #define B43_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */ | |
| 262 | /* SHM_SHARED microcode soft registers */ | |
| 263 | #define B43_SHM_SH_UCODEREV 0x0000 /* Microcode revision */ | |
| 264 | #define B43_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */ | |
| 265 | #define B43_SHM_SH_UCODEDATE 0x0004 /* Microcode date */ | |
| 266 | #define B43_SHM_SH_UCODETIME 0x0006 /* Microcode time */ | |
| 267 | #define B43_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */ | |
| 268 | #define B43_SHM_SH_UCODESTAT_INVALID 0 | |
| 269 | #define B43_SHM_SH_UCODESTAT_INIT 1 | |
| 270 | #define B43_SHM_SH_UCODESTAT_ACTIVE 2 | |
| 271 | #define B43_SHM_SH_UCODESTAT_SUSP 3 /* suspended */ | |
| 272 | #define B43_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */ | |
| 273 | #define B43_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */ | |
| 274 | #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */ | |
| 275 | #define B43_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */ | |
| 76a4db30 RM |
276 | /* SHM_SHARED tx iq workarounds */ |
| 277 | #define B43_SHM_SH_NPHY_TXIQW0 0x0700 | |
| 278 | #define B43_SHM_SH_NPHY_TXIQW1 0x0702 | |
| 279 | #define B43_SHM_SH_NPHY_TXIQW2 0x0704 | |
| 280 | #define B43_SHM_SH_NPHY_TXIQW3 0x0706 | |
| 281 | /* SHM_SHARED tx pwr ctrl */ | |
| 282 | #define B43_SHM_SH_NPHY_TXPWR_INDX0 0x0708 | |
| 283 | #define B43_SHM_SH_NPHY_TXPWR_INDX1 0x070E | |
| e4d6b795 MB |
284 | |
| 285 | /* SHM_SCRATCH offsets */ | |
| 286 | #define B43_SHM_SC_MINCONT 0x0003 /* Minimum contention window */ | |
| 287 | #define B43_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */ | |
| 288 | #define B43_SHM_SC_CURCONT 0x0005 /* Current contention window */ | |
| 289 | #define B43_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */ | |
| 290 | #define B43_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */ | |
| 291 | #define B43_SHM_SC_DTIMC 0x0008 /* Current DTIM count */ | |
| 292 | #define B43_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */ | |
| 293 | #define B43_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */ | |
| 294 | #define B43_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */ | |
| 295 | #define B43_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */ | |
| 296 | ||
| 297 | /* Hardware Radio Enable masks */ | |
| 298 | #define B43_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16) | |
| 299 | #define B43_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4) | |
| 300 | ||
| 301 | /* HostFlags. See b43_hf_read/write() */ | |
| 35f0d354 MB |
302 | #define B43_HF_ANTDIVHELP 0x000000000001ULL /* ucode antenna div helper */ |
| 303 | #define B43_HF_SYMW 0x000000000002ULL /* G-PHY SYM workaround */ | |
| 304 | #define B43_HF_RXPULLW 0x000000000004ULL /* RX pullup workaround */ | |
| 305 | #define B43_HF_CCKBOOST 0x000000000008ULL /* 4dB CCK power boost (exclusive with OFDM boost) */ | |
| 306 | #define B43_HF_BTCOEX 0x000000000010ULL /* Bluetooth coexistance */ | |
| 307 | #define B43_HF_GDCW 0x000000000020ULL /* G-PHY DC canceller filter bw workaround */ | |
| 308 | #define B43_HF_OFDMPABOOST 0x000000000040ULL /* Enable PA gain boost for OFDM */ | |
| 309 | #define B43_HF_ACPR 0x000000000080ULL /* Disable for Japan, channel 14 */ | |
| 310 | #define B43_HF_EDCF 0x000000000100ULL /* on if WME and MAC suspended */ | |
| 311 | #define B43_HF_TSSIRPSMW 0x000000000200ULL /* TSSI reset PSM ucode workaround */ | |
| 312 | #define B43_HF_20IN40IQW 0x000000000200ULL /* 20 in 40 MHz I/Q workaround (rev >= 13 only) */ | |
| 313 | #define B43_HF_DSCRQ 0x000000000400ULL /* Disable slow clock request in ucode */ | |
| 314 | #define B43_HF_ACIW 0x000000000800ULL /* ACI workaround: shift bits by 2 on PHY CRS */ | |
| 315 | #define B43_HF_2060W 0x000000001000ULL /* 2060 radio workaround */ | |
| 316 | #define B43_HF_RADARW 0x000000002000ULL /* Radar workaround */ | |
| 317 | #define B43_HF_USEDEFKEYS 0x000000004000ULL /* Enable use of default keys */ | |
| 318 | #define B43_HF_AFTERBURNER 0x000000008000ULL /* Afterburner enabled */ | |
| 319 | #define B43_HF_BT4PRIOCOEX 0x000000010000ULL /* Bluetooth 4-priority coexistance */ | |
| 320 | #define B43_HF_FWKUP 0x000000020000ULL /* Fast wake-up ucode */ | |
| 321 | #define B43_HF_VCORECALC 0x000000040000ULL /* Force VCO recalculation when powering up synthpu */ | |
| 322 | #define B43_HF_PCISCW 0x000000080000ULL /* PCI slow clock workaround */ | |
| 323 | #define B43_HF_4318TSSI 0x000000200000ULL /* 4318 TSSI */ | |
| 324 | #define B43_HF_FBCMCFIFO 0x000000400000ULL /* Flush bcast/mcast FIFO immediately */ | |
| 325 | #define B43_HF_HWPCTL 0x000000800000ULL /* Enable hardwarre power control */ | |
| 326 | #define B43_HF_BTCOEXALT 0x000001000000ULL /* Bluetooth coexistance in alternate pins */ | |
| 327 | #define B43_HF_TXBTCHECK 0x000002000000ULL /* Bluetooth check during transmission */ | |
| 328 | #define B43_HF_SKCFPUP 0x000004000000ULL /* Skip CFP update */ | |
| 329 | #define B43_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */ | |
| 330 | #define B43_HF_ANTSEL 0x000020000000ULL /* Antenna selection (for testing antenna div.) */ | |
| 331 | #define B43_HF_BT3COEXT 0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */ | |
| 332 | #define B43_HF_BTCANT 0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */ | |
| 333 | #define B43_HF_ANTSELEN 0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */ | |
| 334 | #define B43_HF_ANTSELMODE 0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */ | |
| 335 | #define B43_HF_MLADVW 0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */ | |
| 336 | #define B43_HF_PR45960W 0x080000000000ULL /* PR 45960 workaround (rev >= 13 only) */ | |
| e4d6b795 | 337 | |
| 403a3a13 MB |
338 | /* Firmware capabilities field in SHM (Opensource firmware only) */ |
| 339 | #define B43_FWCAPA_HWCRYPTO 0x0001 | |
| 340 | #define B43_FWCAPA_QOS 0x0002 | |
| 341 | ||
| e4d6b795 MB |
342 | /* MacFilter offsets. */ |
| 343 | #define B43_MACFILTER_SELF 0x0000 | |
| 344 | #define B43_MACFILTER_BSSID 0x0003 | |
| 345 | ||
| 346 | /* PowerControl */ | |
| 347 | #define B43_PCTL_IN 0xB0 | |
| 348 | #define B43_PCTL_OUT 0xB4 | |
| 349 | #define B43_PCTL_OUTENABLE 0xB8 | |
| 350 | #define B43_PCTL_XTAL_POWERUP 0x40 | |
| 351 | #define B43_PCTL_PLL_POWERDOWN 0x80 | |
| 352 | ||
| 353 | /* PowerControl Clock Modes */ | |
| 354 | #define B43_PCTL_CLK_FAST 0x00 | |
| 355 | #define B43_PCTL_CLK_SLOW 0x01 | |
| 356 | #define B43_PCTL_CLK_DYNAMIC 0x02 | |
| 357 | ||
| 358 | #define B43_PCTL_FORCE_SLOW 0x0800 | |
| 359 | #define B43_PCTL_FORCE_PLL 0x1000 | |
| 360 | #define B43_PCTL_DYN_XTAL 0x2000 | |
| 361 | ||
| 362 | /* PHYVersioning */ | |
| 363 | #define B43_PHYTYPE_A 0x00 | |
| 364 | #define B43_PHYTYPE_B 0x01 | |
| 365 | #define B43_PHYTYPE_G 0x02 | |
| d987160b MB |
366 | #define B43_PHYTYPE_N 0x04 |
| 367 | #define B43_PHYTYPE_LP 0x05 | |
| 443c1a24 RM |
368 | #define B43_PHYTYPE_SSLPN 0x06 |
| 369 | #define B43_PHYTYPE_HT 0x07 | |
| 370 | #define B43_PHYTYPE_LCN 0x08 | |
| 371 | #define B43_PHYTYPE_LCNXN 0x09 | |
| e4d6b795 MB |
372 | |
| 373 | /* PHYRegisters */ | |
| 374 | #define B43_PHY_ILT_A_CTRL 0x0072 | |
| 375 | #define B43_PHY_ILT_A_DATA1 0x0073 | |
| 376 | #define B43_PHY_ILT_A_DATA2 0x0074 | |
| 377 | #define B43_PHY_G_LO_CONTROL 0x0810 | |
| 378 | #define B43_PHY_ILT_G_CTRL 0x0472 | |
| 379 | #define B43_PHY_ILT_G_DATA1 0x0473 | |
| 380 | #define B43_PHY_ILT_G_DATA2 0x0474 | |
| 381 | #define B43_PHY_A_PCTL 0x007B | |
| 382 | #define B43_PHY_G_PCTL 0x0029 | |
| 383 | #define B43_PHY_A_CRS 0x0029 | |
| 384 | #define B43_PHY_RADIO_BITFIELD 0x0401 | |
| 385 | #define B43_PHY_G_CRS 0x0429 | |
| 386 | #define B43_PHY_NRSSILT_CTRL 0x0803 | |
| 387 | #define B43_PHY_NRSSILT_DATA 0x0804 | |
| 388 | ||
| 389 | /* RadioRegisters */ | |
| 390 | #define B43_RADIOCTL_ID 0x01 | |
| 391 | ||
| 392 | /* MAC Control bitfield */ | |
| 393 | #define B43_MACCTL_ENABLED 0x00000001 /* MAC Enabled */ | |
| 394 | #define B43_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */ | |
| 395 | #define B43_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */ | |
| 396 | #define B43_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */ | |
| 397 | #define B43_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */ | |
| 398 | #define B43_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */ | |
| 399 | #define B43_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */ | |
| 400 | #define B43_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */ | |
| 401 | #define B43_MACCTL_BE 0x00010000 /* Big Endian mode */ | |
| 402 | #define B43_MACCTL_INFRA 0x00020000 /* Infrastructure mode */ | |
| 403 | #define B43_MACCTL_AP 0x00040000 /* AccessPoint mode */ | |
| 404 | #define B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */ | |
| 405 | #define B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */ | |
| 406 | #define B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */ | |
| 407 | #define B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */ | |
| 408 | #define B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */ | |
| 409 | #define B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */ | |
| 410 | #define B43_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */ | |
| 411 | #define B43_MACCTL_AWAKE 0x04000000 /* Device is awake */ | |
| 412 | #define B43_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */ | |
| 413 | #define B43_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */ | |
| 414 | #define B43_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */ | |
| 415 | #define B43_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */ | |
| 416 | #define B43_MACCTL_GMODE 0x80000000 /* G Mode */ | |
| 417 | ||
| aa6c7ae2 MB |
418 | /* MAC Command bitfield */ |
| 419 | #define B43_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */ | |
| 420 | #define B43_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */ | |
| 421 | #define B43_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */ | |
| 422 | #define B43_MACCMD_CCA 0x00000008 /* Clear channel assessment */ | |
| 423 | #define B43_MACCMD_BGNOISE 0x00000010 /* Background noise */ | |
| 424 | ||
| aa4e0141 RM |
425 | /* BCMA 802.11 core specific IO Control (BCMA_IOCTL) flags */ |
| 426 | #define B43_BCMA_IOCTL_PHY_CLKEN 0x00000004 /* PHY Clock Enable */ | |
| 427 | #define B43_BCMA_IOCTL_PHY_RESET 0x00000008 /* PHY Reset */ | |
| 428 | #define B43_BCMA_IOCTL_MACPHYCLKEN 0x00000010 /* MAC PHY Clock Control Enable */ | |
| 429 | #define B43_BCMA_IOCTL_PLLREFSEL 0x00000020 /* PLL Frequency Reference Select */ | |
| 430 | #define B43_BCMA_IOCTL_PHY_BW 0x000000C0 /* PHY band width and clock speed mask (N-PHY+ only?) */ | |
| 431 | #define B43_BCMA_IOCTL_PHY_BW_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */ | |
| 432 | #define B43_BCMA_IOCTL_PHY_BW_20MHZ 0x00000040 /* 20 MHz bandwidth, 80 MHz PHY */ | |
| 433 | #define B43_BCMA_IOCTL_PHY_BW_40MHZ 0x00000080 /* 40 MHz bandwidth, 160 MHz PHY */ | |
| 434 | #define B43_BCMA_IOCTL_GMODE 0x00002000 /* G Mode Enable */ | |
| 435 | ||
| 124cc111 RM |
436 | /* BCMA 802.11 core specific IO status (BCMA_IOST) flags */ |
| 437 | #define B43_BCMA_IOST_2G_PHY 0x00000001 /* 2.4G capable phy */ | |
| 438 | #define B43_BCMA_IOST_5G_PHY 0x00000002 /* 5G capable phy */ | |
| 439 | #define B43_BCMA_IOST_FASTCLKA 0x00000004 /* Fast Clock Available */ | |
| 440 | #define B43_BCMA_IOST_DUALB_PHY 0x00000008 /* Dualband phy */ | |
| 441 | ||
| 96c755a3 | 442 | /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */ |
| e4d6b795 | 443 | #define B43_TMSLOW_GMODE 0x20000000 /* G Mode Enable */ |
| 42ab135f RM |
444 | #define B43_TMSLOW_PHY_BANDWIDTH 0x00C00000 /* PHY band width and clock speed mask (N-PHY only) */ |
| 445 | #define B43_TMSLOW_PHY_BANDWIDTH_10MHZ 0x00000000 /* 10 MHz bandwidth, 40 MHz PHY */ | |
| 446 | #define B43_TMSLOW_PHY_BANDWIDTH_20MHZ 0x00400000 /* 20 MHz bandwidth, 80 MHz PHY */ | |
| 447 | #define B43_TMSLOW_PHY_BANDWIDTH_40MHZ 0x00800000 /* 40 MHz bandwidth, 160 MHz PHY */ | |
| 96c755a3 | 448 | #define B43_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */ |
| e4d6b795 MB |
449 | #define B43_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */ |
| 450 | #define B43_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */ | |
| 451 | #define B43_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */ | |
| 452 | ||
| 96c755a3 MB |
453 | /* 802.11 core specific TM State High (SSB_TMSHIGH) flags */ |
| 454 | #define B43_TMSHIGH_DUALBAND_PHY 0x00080000 /* Dualband PHY available */ | |
| e4d6b795 | 455 | #define B43_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5) */ |
| 96c755a3 MB |
456 | #define B43_TMSHIGH_HAVE_5GHZ_PHY 0x00020000 /* 5 GHz PHY available (rev >= 5) */ |
| 457 | #define B43_TMSHIGH_HAVE_2GHZ_PHY 0x00010000 /* 2.4 GHz PHY available (rev >= 5) */ | |
| e4d6b795 MB |
458 | |
| 459 | /* Generic-Interrupt reasons. */ | |
| 460 | #define B43_IRQ_MAC_SUSPENDED 0x00000001 | |
| 461 | #define B43_IRQ_BEACON 0x00000002 | |
| 462 | #define B43_IRQ_TBTT_INDI 0x00000004 | |
| 463 | #define B43_IRQ_BEACON_TX_OK 0x00000008 | |
| 464 | #define B43_IRQ_BEACON_CANCEL 0x00000010 | |
| 465 | #define B43_IRQ_ATIM_END 0x00000020 | |
| 466 | #define B43_IRQ_PMQ 0x00000040 | |
| 467 | #define B43_IRQ_PIO_WORKAROUND 0x00000100 | |
| 468 | #define B43_IRQ_MAC_TXERR 0x00000200 | |
| 469 | #define B43_IRQ_PHY_TXERR 0x00000800 | |
| 470 | #define B43_IRQ_PMEVENT 0x00001000 | |
| 471 | #define B43_IRQ_TIMER0 0x00002000 | |
| 472 | #define B43_IRQ_TIMER1 0x00004000 | |
| 473 | #define B43_IRQ_DMA 0x00008000 | |
| 474 | #define B43_IRQ_TXFIFO_FLUSH_OK 0x00010000 | |
| 475 | #define B43_IRQ_CCA_MEASURE_OK 0x00020000 | |
| 476 | #define B43_IRQ_NOISESAMPLE_OK 0x00040000 | |
| 477 | #define B43_IRQ_UCODE_DEBUG 0x08000000 | |
| 478 | #define B43_IRQ_RFKILL 0x10000000 | |
| 479 | #define B43_IRQ_TX_OK 0x20000000 | |
| 480 | #define B43_IRQ_PHY_G_CHANGED 0x40000000 | |
| 481 | #define B43_IRQ_TIMEOUT 0x80000000 | |
| 482 | ||
| 483 | #define B43_IRQ_ALL 0xFFFFFFFF | |
| e40ac414 | 484 | #define B43_IRQ_MASKTEMPLATE (B43_IRQ_TBTT_INDI | \ |
| e4d6b795 MB |
485 | B43_IRQ_ATIM_END | \ |
| 486 | B43_IRQ_PMQ | \ | |
| 487 | B43_IRQ_MAC_TXERR | \ | |
| 488 | B43_IRQ_PHY_TXERR | \ | |
| 489 | B43_IRQ_DMA | \ | |
| 490 | B43_IRQ_TXFIFO_FLUSH_OK | \ | |
| 491 | B43_IRQ_NOISESAMPLE_OK | \ | |
| 492 | B43_IRQ_UCODE_DEBUG | \ | |
| 493 | B43_IRQ_RFKILL | \ | |
| 494 | B43_IRQ_TX_OK) | |
| 495 | ||
| afa83e23 MB |
496 | /* The firmware register to fetch the debug-IRQ reason from. */ |
| 497 | #define B43_DEBUGIRQ_REASON_REG 63 | |
| e48b0eeb MB |
498 | /* Debug-IRQ reasons. */ |
| 499 | #define B43_DEBUGIRQ_PANIC 0 /* The firmware panic'ed */ | |
| 500 | #define B43_DEBUGIRQ_DUMP_SHM 1 /* Dump shared SHM */ | |
| 501 | #define B43_DEBUGIRQ_DUMP_REGS 2 /* Dump the microcode registers */ | |
| 53c06856 | 502 | #define B43_DEBUGIRQ_MARKER 3 /* A "marker" was thrown by the firmware. */ |
| e48b0eeb MB |
503 | #define B43_DEBUGIRQ_ACK 0xFFFF /* The host writes that to ACK the IRQ */ |
| 504 | ||
| 53c06856 MB |
505 | /* The firmware register that contains the "marker" line. */ |
| 506 | #define B43_MARKER_ID_REG 2 | |
| 507 | #define B43_MARKER_LINE_REG 3 | |
| 508 | ||
| afa83e23 MB |
509 | /* The firmware register to fetch the panic reason from. */ |
| 510 | #define B43_FWPANIC_REASON_REG 3 | |
| 511 | /* Firmware panic reason codes */ | |
| 512 | #define B43_FWPANIC_DIE 0 /* Firmware died. Don't auto-restart it. */ | |
| 513 | #define B43_FWPANIC_RESTART 1 /* Firmware died. Schedule a controller reset. */ | |
| 514 | ||
| 9b839a74 MB |
515 | /* The firmware register that contains the watchdog counter. */ |
| 516 | #define B43_WATCHDOG_REG 1 | |
| afa83e23 | 517 | |
| e4d6b795 MB |
518 | /* Device specific rate values. |
| 519 | * The actual values defined here are (rate_in_mbps * 2). | |
| 520 | * Some code depends on this. Don't change it. */ | |
| 521 | #define B43_CCK_RATE_1MB 0x02 | |
| 522 | #define B43_CCK_RATE_2MB 0x04 | |
| 523 | #define B43_CCK_RATE_5MB 0x0B | |
| 524 | #define B43_CCK_RATE_11MB 0x16 | |
| 525 | #define B43_OFDM_RATE_6MB 0x0C | |
| 526 | #define B43_OFDM_RATE_9MB 0x12 | |
| 527 | #define B43_OFDM_RATE_12MB 0x18 | |
| 528 | #define B43_OFDM_RATE_18MB 0x24 | |
| 529 | #define B43_OFDM_RATE_24MB 0x30 | |
| 530 | #define B43_OFDM_RATE_36MB 0x48 | |
| 531 | #define B43_OFDM_RATE_48MB 0x60 | |
| 532 | #define B43_OFDM_RATE_54MB 0x6C | |
| 533 | /* Convert a b43 rate value to a rate in 100kbps */ | |
| 534 | #define B43_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2) | |
| 535 | ||
| 536 | #define B43_DEFAULT_SHORT_RETRY_LIMIT 7 | |
| 537 | #define B43_DEFAULT_LONG_RETRY_LIMIT 4 | |
| 538 | ||
| 00e0b8cb SB |
539 | #define B43_PHY_TX_BADNESS_LIMIT 1000 |
| 540 | ||
| e4d6b795 MB |
541 | /* Max size of a security key */ |
| 542 | #define B43_SEC_KEYSIZE 16 | |
| 66d2d089 MB |
543 | /* Max number of group keys */ |
| 544 | #define B43_NR_GROUP_KEYS 4 | |
| 545 | /* Max number of pairwise keys */ | |
| 546 | #define B43_NR_PAIRWISE_KEYS 50 | |
| e4d6b795 MB |
547 | /* Security algorithms. */ |
| 548 | enum { | |
| 549 | B43_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */ | |
| 550 | B43_SEC_ALGO_WEP40, | |
| 551 | B43_SEC_ALGO_TKIP, | |
| 552 | B43_SEC_ALGO_AES, | |
| 553 | B43_SEC_ALGO_WEP104, | |
| 554 | B43_SEC_ALGO_AES_LEGACY, | |
| 555 | }; | |
| 556 | ||
| 557 | struct b43_dmaring; | |
| e4d6b795 MB |
558 | |
| 559 | /* The firmware file header */ | |
| 560 | #define B43_FW_TYPE_UCODE 'u' | |
| 561 | #define B43_FW_TYPE_PCM 'p' | |
| 562 | #define B43_FW_TYPE_IV 'i' | |
| 563 | struct b43_fw_header { | |
| 564 | /* File type */ | |
| 565 | u8 type; | |
| 566 | /* File format version */ | |
| 567 | u8 ver; | |
| 568 | u8 __padding[2]; | |
| 569 | /* Size of the data. For ucode and PCM this is in bytes. | |
| 570 | * For IV this is number-of-ivs. */ | |
| 571 | __be32 size; | |
| ba2d3587 | 572 | } __packed; |
| e4d6b795 MB |
573 | |
| 574 | /* Initial Value file format */ | |
| 575 | #define B43_IV_OFFSET_MASK 0x7FFF | |
| 576 | #define B43_IV_32BIT 0x8000 | |
| 577 | struct b43_iv { | |
| 578 | __be16 offset_size; | |
| 579 | union { | |
| 580 | __be16 d16; | |
| 581 | __be32 d32; | |
| ba2d3587 ED |
582 | } data __packed; |
| 583 | } __packed; | |
| e4d6b795 MB |
584 | |
| 585 | ||
| e4d6b795 MB |
586 | /* Data structures for DMA transmission, per 80211 core. */ |
| 587 | struct b43_dma { | |
| b27faf8e MB |
588 | struct b43_dmaring *tx_ring_AC_BK; /* Background */ |
| 589 | struct b43_dmaring *tx_ring_AC_BE; /* Best Effort */ | |
| 590 | struct b43_dmaring *tx_ring_AC_VI; /* Video */ | |
| 591 | struct b43_dmaring *tx_ring_AC_VO; /* Voice */ | |
| 592 | struct b43_dmaring *tx_ring_mcast; /* Multicast */ | |
| 593 | ||
| 594 | struct b43_dmaring *rx_ring; | |
| 05100a29 RM |
595 | |
| 596 | u32 translation; /* Routing bits */ | |
| 78c1ee7e | 597 | bool parity; /* Check for parity */ |
| e4d6b795 MB |
598 | }; |
| 599 | ||
| 5100d5ac MB |
600 | struct b43_pio_txqueue; |
| 601 | struct b43_pio_rxqueue; | |
| 602 | ||
| 603 | /* Data structures for PIO transmission, per 80211 core. */ | |
| 604 | struct b43_pio { | |
| 605 | struct b43_pio_txqueue *tx_queue_AC_BK; /* Background */ | |
| 606 | struct b43_pio_txqueue *tx_queue_AC_BE; /* Best Effort */ | |
| 607 | struct b43_pio_txqueue *tx_queue_AC_VI; /* Video */ | |
| 608 | struct b43_pio_txqueue *tx_queue_AC_VO; /* Voice */ | |
| 609 | struct b43_pio_txqueue *tx_queue_mcast; /* Multicast */ | |
| 610 | ||
| 611 | struct b43_pio_rxqueue *rx_queue; | |
| 612 | }; | |
| 613 | ||
| e4d6b795 MB |
614 | /* Context information for a noise calculation (Link Quality). */ |
| 615 | struct b43_noise_calculation { | |
| e4d6b795 MB |
616 | bool calculation_running; |
| 617 | u8 nr_samples; | |
| 618 | s8 samples[8][4]; | |
| 619 | }; | |
| 620 | ||
| 621 | struct b43_stats { | |
| 622 | u8 link_noise; | |
| e4d6b795 MB |
623 | }; |
| 624 | ||
| 625 | struct b43_key { | |
| 626 | /* If keyconf is NULL, this key is disabled. | |
| 627 | * keyconf is a cookie. Don't derefenrence it outside of the set_key | |
| 628 | * path, because b43 doesn't own it. */ | |
| 629 | struct ieee80211_key_conf *keyconf; | |
| 630 | u8 algorithm; | |
| 631 | }; | |
| 632 | ||
| e6f5b934 MB |
633 | /* SHM offsets to the QOS data structures for the 4 different queues. */ |
| 634 | #define B43_QOS_PARAMS(queue) (B43_SHM_SH_EDCFQ + \ | |
| 635 | (B43_NR_QOSPARAMS * sizeof(u16) * (queue))) | |
| 636 | #define B43_QOS_BACKGROUND B43_QOS_PARAMS(0) | |
| 637 | #define B43_QOS_BESTEFFORT B43_QOS_PARAMS(1) | |
| 638 | #define B43_QOS_VIDEO B43_QOS_PARAMS(2) | |
| 639 | #define B43_QOS_VOICE B43_QOS_PARAMS(3) | |
| 640 | ||
| 641 | /* QOS parameter hardware data structure offsets. */ | |
| e35cc4dd | 642 | #define B43_NR_QOSPARAMS 16 |
| e6f5b934 MB |
643 | enum { |
| 644 | B43_QOSPARAM_TXOP = 0, | |
| 645 | B43_QOSPARAM_CWMIN, | |
| 646 | B43_QOSPARAM_CWMAX, | |
| 647 | B43_QOSPARAM_CWCUR, | |
| 648 | B43_QOSPARAM_AIFS, | |
| 649 | B43_QOSPARAM_BSLOTS, | |
| 650 | B43_QOSPARAM_REGGAP, | |
| 651 | B43_QOSPARAM_STATUS, | |
| 652 | }; | |
| 653 | ||
| 654 | /* QOS parameters for a queue. */ | |
| 655 | struct b43_qos_params { | |
| 656 | /* The QOS parameters */ | |
| 657 | struct ieee80211_tx_queue_params p; | |
| e6f5b934 MB |
658 | }; |
| 659 | ||
| 7e937c63 | 660 | struct b43_wl; |
| e4d6b795 | 661 | |
| 1a9f5093 MB |
662 | /* The type of the firmware file. */ |
| 663 | enum b43_firmware_file_type { | |
| 664 | B43_FWTYPE_PROPRIETARY, | |
| 665 | B43_FWTYPE_OPENSOURCE, | |
| 666 | B43_NR_FWTYPES, | |
| 667 | }; | |
| 668 | ||
| 669 | /* Context data for fetching firmware. */ | |
| 670 | struct b43_request_fw_context { | |
| 671 | /* The device we are requesting the fw for. */ | |
| 672 | struct b43_wldev *dev; | |
| 673 | /* The type of firmware to request. */ | |
| 674 | enum b43_firmware_file_type req_type; | |
| 675 | /* Error messages for each firmware type. */ | |
| 676 | char errors[B43_NR_FWTYPES][128]; | |
| 677 | /* Temporary buffer for storing the firmware name. */ | |
| 678 | char fwname[64]; | |
| e64851f5 JC |
679 | /* A fatal error occurred while requesting. Firmware request |
| 680 | * can not continue, as any other request will also fail. */ | |
| 1a9f5093 MB |
681 | int fatal_failure; |
| 682 | }; | |
| 683 | ||
| 61cb5dd6 MB |
684 | /* In-memory representation of a cached microcode file. */ |
| 685 | struct b43_firmware_file { | |
| 686 | const char *filename; | |
| 687 | const struct firmware *data; | |
| 1a9f5093 MB |
688 | /* Type of the firmware file name. Note that this does only indicate |
| 689 | * the type by the firmware name. NOT the file contents. | |
| 690 | * If you want to check for proprietary vs opensource, use (struct b43_firmware)->opensource | |
| 691 | * instead! The (struct b43_firmware)->opensource flag is derived from the actual firmware | |
| 692 | * binary code, not just the filename. | |
| 693 | */ | |
| 694 | enum b43_firmware_file_type type; | |
| 61cb5dd6 MB |
695 | }; |
| 696 | ||
| efe0249b RM |
697 | enum b43_firmware_hdr_format { |
| 698 | B43_FW_HDR_410, | |
| 699 | B43_FW_HDR_351, | |
| 700 | }; | |
| 701 | ||
| e4d6b795 MB |
702 | /* Pointers to the firmware data and meta information about it. */ |
| 703 | struct b43_firmware { | |
| 704 | /* Microcode */ | |
| 61cb5dd6 | 705 | struct b43_firmware_file ucode; |
| e4d6b795 | 706 | /* PCM code */ |
| 61cb5dd6 | 707 | struct b43_firmware_file pcm; |
| e4d6b795 | 708 | /* Initial MMIO values for the firmware */ |
| 61cb5dd6 | 709 | struct b43_firmware_file initvals; |
| e4d6b795 | 710 | /* Initial MMIO values for the firmware, band-specific */ |
| 61cb5dd6 MB |
711 | struct b43_firmware_file initvals_band; |
| 712 | ||
| e4d6b795 MB |
713 | /* Firmware revision */ |
| 714 | u16 rev; | |
| 715 | /* Firmware patchlevel */ | |
| 716 | u16 patch; | |
| e48b0eeb | 717 | |
| efe0249b RM |
718 | /* Format of header used by firmware */ |
| 719 | enum b43_firmware_hdr_format hdr_format; | |
| 720 | ||
| 1a9f5093 MB |
721 | /* Set to true, if we are using an opensource firmware. |
| 722 | * Use this to check for proprietary vs opensource. */ | |
| e48b0eeb | 723 | bool opensource; |
| 68217832 MB |
724 | /* Set to true, if the core needs a PCM firmware, but |
| 725 | * we failed to load one. This is always false for | |
| 726 | * core rev > 10, as these don't need PCM firmware. */ | |
| 727 | bool pcm_request_failed; | |
| e4d6b795 MB |
728 | }; |
| 729 | ||
| 730 | /* Device (802.11 core) initialization status. */ | |
| 731 | enum { | |
| 732 | B43_STAT_UNINIT = 0, /* Uninitialized. */ | |
| 733 | B43_STAT_INITIALIZED = 1, /* Initialized, but not started, yet. */ | |
| 734 | B43_STAT_STARTED = 2, /* Up and running. */ | |
| 735 | }; | |
| 736 | #define b43_status(wldev) atomic_read(&(wldev)->__init_status) | |
| 737 | #define b43_set_status(wldev, stat) do { \ | |
| 738 | atomic_set(&(wldev)->__init_status, (stat)); \ | |
| 739 | smp_wmb(); \ | |
| 740 | } while (0) | |
| 741 | ||
| e4d6b795 MB |
742 | /* Data structure for one wireless device (802.11 core) */ |
| 743 | struct b43_wldev { | |
| 482f0538 | 744 | struct b43_bus_dev *dev; |
| e4d6b795 MB |
745 | struct b43_wl *wl; |
| 746 | ||
| 747 | /* The device initialization status. | |
| 748 | * Use b43_status() to query. */ | |
| 749 | atomic_t __init_status; | |
| e4d6b795 | 750 | |
| e4d6b795 | 751 | bool bad_frames_preempt; /* Use "Bad Frames Preemption" (default off) */ |
| aa6c7ae2 | 752 | bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM) */ |
| e4d6b795 | 753 | bool radio_hw_enable; /* saved state of radio hardware enabled state */ |
| 403a3a13 MB |
754 | bool qos_enabled; /* TRUE, if QoS is used. */ |
| 755 | bool hwcrypto_enabled; /* TRUE, if HW crypto acceleration is enabled. */ | |
| 9e3bd919 | 756 | bool use_pio; /* TRUE if next init should use PIO */ |
| e4d6b795 MB |
757 | |
| 758 | /* PHY/Radio device. */ | |
| 759 | struct b43_phy phy; | |
| 03b29773 | 760 | |
| 5100d5ac MB |
761 | union { |
| 762 | /* DMA engines. */ | |
| 763 | struct b43_dma dma; | |
| 764 | /* PIO engines. */ | |
| 765 | struct b43_pio pio; | |
| 766 | }; | |
| 767 | /* Use b43_using_pio_transfers() to check whether we are using | |
| 768 | * DMA or PIO data transfers. */ | |
| 769 | bool __using_pio_transfers; | |
| e4d6b795 MB |
770 | |
| 771 | /* Various statistics about the physical device. */ | |
| 772 | struct b43_stats stats; | |
| 773 | ||
| e4d6b795 MB |
774 | /* Reason code of the last interrupt. */ |
| 775 | u32 irq_reason; | |
| 776 | u32 dma_reason[6]; | |
| 13790728 MB |
777 | /* The currently active generic-interrupt mask. */ |
| 778 | u32 irq_mask; | |
| 36dbd954 | 779 | |
| e4d6b795 MB |
780 | /* Link Quality calculation context. */ |
| 781 | struct b43_noise_calculation noisecalc; | |
| 782 | /* if > 0 MAC is suspended. if == 0 MAC is enabled. */ | |
| 783 | int mac_suspended; | |
| 784 | ||
| e4d6b795 MB |
785 | /* Periodic tasks */ |
| 786 | struct delayed_work periodic_work; | |
| 787 | unsigned int periodic_state; | |
| 788 | ||
| 789 | struct work_struct restart_work; | |
| 790 | ||
| 791 | /* encryption/decryption */ | |
| 792 | u16 ktp; /* Key table pointer */ | |
| 66d2d089 | 793 | struct b43_key key[B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS]; |
| e4d6b795 | 794 | |
| e4d6b795 MB |
795 | /* Firmware data */ |
| 796 | struct b43_firmware fw; | |
| 797 | ||
| 798 | /* Devicelist in struct b43_wl (all 802.11 cores) */ | |
| 799 | struct list_head list; | |
| 800 | ||
| 801 | /* Debugging stuff follows. */ | |
| 802 | #ifdef CONFIG_B43_DEBUG | |
| 803 | struct b43_dfsentry *dfsentry; | |
| 990b86f4 MB |
804 | unsigned int irq_count; |
| 805 | unsigned int irq_bit_count[32]; | |
| 806 | unsigned int tx_count; | |
| 807 | unsigned int rx_count; | |
| e4d6b795 MB |
808 | #endif |
| 809 | }; | |
| 810 | ||
| 7e937c63 AH |
811 | /* Data structure for the WLAN parts (802.11 cores) of the b43 chip. */ |
| 812 | struct b43_wl { | |
| 813 | /* Pointer to the active wireless device on this chip */ | |
| 814 | struct b43_wldev *current_dev; | |
| 815 | /* Pointer to the ieee80211 hardware data structure */ | |
| 816 | struct ieee80211_hw *hw; | |
| 817 | ||
| 818 | /* Global driver mutex. Every operation must run with this mutex locked. */ | |
| 819 | struct mutex mutex; | |
| 820 | /* Hard-IRQ spinlock. This lock protects things used in the hard-IRQ | |
| 821 | * handler, only. This basically is just the IRQ mask register. */ | |
| 822 | spinlock_t hardirq_lock; | |
| 823 | ||
| 824 | /* The number of queues that were registered with the mac80211 subsystem | |
| 825 | * initially. This is a backup copy of hw->queues in case hw->queues has | |
| 826 | * to be dynamically lowered at runtime (Firmware does not support QoS). | |
| 827 | * hw->queues has to be restored to the original value before unregistering | |
| 828 | * from the mac80211 subsystem. */ | |
| 829 | u16 mac80211_initially_registered_queues; | |
| 830 | ||
| 831 | /* We can only have one operating interface (802.11 core) | |
| 832 | * at a time. General information about this interface follows. | |
| 833 | */ | |
| 834 | ||
| 835 | struct ieee80211_vif *vif; | |
| 836 | /* The MAC address of the operating interface. */ | |
| 837 | u8 mac_addr[ETH_ALEN]; | |
| 838 | /* Current BSSID */ | |
| 839 | u8 bssid[ETH_ALEN]; | |
| 840 | /* Interface type. (NL80211_IFTYPE_XXX) */ | |
| 841 | int if_type; | |
| 842 | /* Is the card operating in AP, STA or IBSS mode? */ | |
| 843 | bool operating; | |
| 844 | /* filter flags */ | |
| 845 | unsigned int filter_flags; | |
| 846 | /* Stats about the wireless interface */ | |
| 847 | struct ieee80211_low_level_stats ieee_stats; | |
| 848 | ||
| 849 | #ifdef CONFIG_B43_HWRNG | |
| 850 | struct hwrng rng; | |
| 851 | bool rng_initialized; | |
| 852 | char rng_name[30 + 1]; | |
| 853 | #endif /* CONFIG_B43_HWRNG */ | |
| 854 | ||
| 855 | /* List of all wireless devices on this chip */ | |
| 856 | struct list_head devlist; | |
| 857 | u8 nr_devs; | |
| 858 | ||
| 859 | bool radiotap_enabled; | |
| 860 | bool radio_enabled; | |
| 861 | ||
| 862 | /* The beacon we are currently using (AP or IBSS mode). */ | |
| 863 | struct sk_buff *current_beacon; | |
| 864 | bool beacon0_uploaded; | |
| 865 | bool beacon1_uploaded; | |
| 866 | bool beacon_templates_virgin; /* Never wrote the templates? */ | |
| 867 | struct work_struct beacon_update_trigger; | |
| 868 | ||
| 869 | /* The current QOS parameters for the 4 queues. */ | |
| 870 | struct b43_qos_params qos_params[4]; | |
| 871 | ||
| 872 | /* Work for adjustment of the transmission power. | |
| 873 | * This is scheduled when we determine that the actual TX output | |
| 874 | * power doesn't match what we want. */ | |
| 875 | struct work_struct txpower_adjust_work; | |
| 876 | ||
| 877 | /* Packet transmit work */ | |
| 878 | struct work_struct tx_work; | |
| 879 | /* Queue of packets to be transmitted. */ | |
| 880 | struct sk_buff_head tx_queue; | |
| 881 | ||
| 882 | /* The device LEDs. */ | |
| 883 | struct b43_leds leds; | |
| 884 | ||
| 88499ab3 MB |
885 | /* Kmalloc'ed scratch space for PIO TX/RX. Protected by wl->mutex. */ |
| 886 | u8 pio_scratchspace[110] __attribute__((__aligned__(8))); | |
| 887 | u8 pio_tailspace[4] __attribute__((__aligned__(8))); | |
| 7e937c63 AH |
888 | }; |
| 889 | ||
| e4d6b795 MB |
890 | static inline struct b43_wl *hw_to_b43_wl(struct ieee80211_hw *hw) |
| 891 | { | |
| 892 | return hw->priv; | |
| 893 | } | |
| 894 | ||
| e4d6b795 MB |
895 | static inline struct b43_wldev *dev_to_b43_wldev(struct device *dev) |
| 896 | { | |
| 897 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
| 898 | return ssb_get_drvdata(ssb_dev); | |
| 899 | } | |
| 900 | ||
| bedaf808 | 901 | /* Is the device operating in a specified mode (NL80211_IFTYPE_XXX). */ |
| e4d6b795 MB |
902 | static inline int b43_is_mode(struct b43_wl *wl, int type) |
| 903 | { | |
| e4d6b795 MB |
904 | return (wl->operating && wl->if_type == type); |
| 905 | } | |
| 906 | ||
| ef1a628d MB |
907 | /** |
| 908 | * b43_current_band - Returns the currently used band. | |
| 909 | * Returns one of IEEE80211_BAND_2GHZ and IEEE80211_BAND_5GHZ. | |
| 910 | */ | |
| 911 | static inline enum ieee80211_band b43_current_band(struct b43_wl *wl) | |
| 912 | { | |
| 913 | return wl->hw->conf.channel->band; | |
| 914 | } | |
| 915 | ||
| 24ca39d6 RM |
916 | static inline int b43_bus_may_powerdown(struct b43_wldev *wldev) |
| 917 | { | |
| 918 | return wldev->dev->bus_may_powerdown(wldev->dev); | |
| 919 | } | |
| 920 | static inline int b43_bus_powerup(struct b43_wldev *wldev, bool dynamic_pctl) | |
| 921 | { | |
| 922 | return wldev->dev->bus_powerup(wldev->dev, dynamic_pctl); | |
| 923 | } | |
| 924 | static inline int b43_device_is_enabled(struct b43_wldev *wldev) | |
| 925 | { | |
| 926 | return wldev->dev->device_is_enabled(wldev->dev); | |
| 927 | } | |
| 928 | static inline void b43_device_enable(struct b43_wldev *wldev, | |
| 929 | u32 core_specific_flags) | |
| 930 | { | |
| 931 | wldev->dev->device_enable(wldev->dev, core_specific_flags); | |
| 932 | } | |
| 933 | static inline void b43_device_disable(struct b43_wldev *wldev, | |
| 934 | u32 core_specific_flags) | |
| 935 | { | |
| 936 | wldev->dev->device_disable(wldev->dev, core_specific_flags); | |
| 937 | } | |
| 938 | ||
| e4d6b795 MB |
939 | static inline u16 b43_read16(struct b43_wldev *dev, u16 offset) |
| 940 | { | |
| c0b4c009 | 941 | return dev->dev->read16(dev->dev, offset); |
| e4d6b795 MB |
942 | } |
| 943 | ||
| 944 | static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value) | |
| 945 | { | |
| c0b4c009 | 946 | dev->dev->write16(dev->dev, offset, value); |
| e4d6b795 MB |
947 | } |
| 948 | ||
| 949 | static inline u32 b43_read32(struct b43_wldev *dev, u16 offset) | |
| 950 | { | |
| c0b4c009 | 951 | return dev->dev->read32(dev->dev, offset); |
| e4d6b795 MB |
952 | } |
| 953 | ||
| 954 | static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value) | |
| 955 | { | |
| c0b4c009 | 956 | dev->dev->write32(dev->dev, offset, value); |
| e4d6b795 MB |
957 | } |
| 958 | ||
| 620d785b RM |
959 | static inline void b43_block_read(struct b43_wldev *dev, void *buffer, |
| 960 | size_t count, u16 offset, u8 reg_width) | |
| 961 | { | |
| c0b4c009 | 962 | dev->dev->block_read(dev->dev, buffer, count, offset, reg_width); |
| 620d785b RM |
963 | } |
| 964 | ||
| 965 | static inline void b43_block_write(struct b43_wldev *dev, const void *buffer, | |
| 966 | size_t count, u16 offset, u8 reg_width) | |
| 967 | { | |
| c0b4c009 | 968 | dev->dev->block_write(dev->dev, buffer, count, offset, reg_width); |
| e4d6b795 MB |
969 | } |
| 970 | ||
| 5100d5ac MB |
971 | static inline bool b43_using_pio_transfers(struct b43_wldev *dev) |
| 972 | { | |
| 5100d5ac | 973 | return dev->__using_pio_transfers; |
| 5100d5ac MB |
974 | } |
| 975 | ||
| 9e3bd919 LT |
976 | #ifdef CONFIG_B43_FORCE_PIO |
| 977 | # define B43_PIO_DEFAULT 1 | |
| 978 | #else | |
| 979 | # define B43_PIO_DEFAULT 0 | |
| 980 | #endif | |
| 981 | ||
| e4d6b795 MB |
982 | /* Message printing */ |
| 983 | void b43info(struct b43_wl *wl, const char *fmt, ...) | |
| 984 | __attribute__ ((format(printf, 2, 3))); | |
| 985 | void b43err(struct b43_wl *wl, const char *fmt, ...) | |
| 986 | __attribute__ ((format(printf, 2, 3))); | |
| 987 | void b43warn(struct b43_wl *wl, const char *fmt, ...) | |
| 988 | __attribute__ ((format(printf, 2, 3))); | |
| e4d6b795 MB |
989 | void b43dbg(struct b43_wl *wl, const char *fmt, ...) |
| 990 | __attribute__ ((format(printf, 2, 3))); | |
| 060210f9 | 991 | |
| e4d6b795 MB |
992 | |
| 993 | /* A WARN_ON variant that vanishes when b43 debugging is disabled. | |
| 994 | * This _also_ evaluates the arg with debugging disabled. */ | |
| 995 | #if B43_DEBUG | |
| 996 | # define B43_WARN_ON(x) WARN_ON(x) | |
| 997 | #else | |
| 998 | static inline bool __b43_warn_on_dummy(bool x) { return x; } | |
| 999 | # define B43_WARN_ON(x) __b43_warn_on_dummy(unlikely(!!(x))) | |
| 1000 | #endif | |
| 1001 | ||
| e4d6b795 MB |
1002 | /* Convert an integer to a Q5.2 value */ |
| 1003 | #define INT_TO_Q52(i) ((i) << 2) | |
| 1004 | /* Convert a Q5.2 value to an integer (precision loss!) */ | |
| 1005 | #define Q52_TO_INT(q52) ((q52) >> 2) | |
| 1006 | /* Macros for printing a value in Q5.2 format */ | |
| 1007 | #define Q52_FMT "%u.%u" | |
| 1008 | #define Q52_ARG(q52) Q52_TO_INT(q52), ((((q52) & 0x3) * 100) / 4) | |
| 1009 | ||
| 1010 | #endif /* B43_H_ */ |