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e4d6b795 MB |
1 | /* |
2 | ||
3 | Broadcom B43 wireless driver | |
4 | ||
5 | Copyright (c) 2005 Martin Langer <martin-langer@gmx.de> | |
1f21ad2a | 6 | Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it> |
e4d6b795 MB |
7 | Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de> |
8 | Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org> | |
9 | Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch> | |
10 | ||
11 | Some parts of the code in this file are derived from the ipw2200 | |
12 | driver Copyright(c) 2003 - 2004 Intel Corporation. | |
13 | ||
14 | This program is free software; you can redistribute it and/or modify | |
15 | it under the terms of the GNU General Public License as published by | |
16 | the Free Software Foundation; either version 2 of the License, or | |
17 | (at your option) any later version. | |
18 | ||
19 | This program is distributed in the hope that it will be useful, | |
20 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | GNU General Public License for more details. | |
23 | ||
24 | You should have received a copy of the GNU General Public License | |
25 | along with this program; see the file COPYING. If not, write to | |
26 | the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, | |
27 | Boston, MA 02110-1301, USA. | |
28 | ||
29 | */ | |
30 | ||
31 | #include <linux/delay.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/moduleparam.h> | |
34 | #include <linux/if_arp.h> | |
35 | #include <linux/etherdevice.h> | |
36 | #include <linux/version.h> | |
37 | #include <linux/firmware.h> | |
38 | #include <linux/wireless.h> | |
39 | #include <linux/workqueue.h> | |
40 | #include <linux/skbuff.h> | |
96cf49a2 | 41 | #include <linux/io.h> |
e4d6b795 MB |
42 | #include <linux/dma-mapping.h> |
43 | #include <asm/unaligned.h> | |
44 | ||
45 | #include "b43.h" | |
46 | #include "main.h" | |
47 | #include "debugfs.h" | |
48 | #include "phy.h" | |
7b584163 | 49 | #include "nphy.h" |
e4d6b795 | 50 | #include "dma.h" |
5100d5ac | 51 | #include "pio.h" |
e4d6b795 MB |
52 | #include "sysfs.h" |
53 | #include "xmit.h" | |
e4d6b795 MB |
54 | #include "lo.h" |
55 | #include "pcmcia.h" | |
56 | ||
57 | MODULE_DESCRIPTION("Broadcom B43 wireless driver"); | |
58 | MODULE_AUTHOR("Martin Langer"); | |
59 | MODULE_AUTHOR("Stefano Brivio"); | |
60 | MODULE_AUTHOR("Michael Buesch"); | |
61 | MODULE_LICENSE("GPL"); | |
62 | ||
9c7d99d6 MB |
63 | MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID); |
64 | ||
e4d6b795 MB |
65 | |
66 | static int modparam_bad_frames_preempt; | |
67 | module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444); | |
68 | MODULE_PARM_DESC(bad_frames_preempt, | |
69 | "enable(1) / disable(0) Bad Frames Preemption"); | |
70 | ||
e4d6b795 MB |
71 | static char modparam_fwpostfix[16]; |
72 | module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444); | |
73 | MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load."); | |
74 | ||
e4d6b795 MB |
75 | static int modparam_hwpctl; |
76 | module_param_named(hwpctl, modparam_hwpctl, int, 0444); | |
77 | MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)"); | |
78 | ||
79 | static int modparam_nohwcrypt; | |
80 | module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444); | |
81 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); | |
82 | ||
e6f5b934 MB |
83 | int b43_modparam_qos = 1; |
84 | module_param_named(qos, b43_modparam_qos, int, 0444); | |
85 | MODULE_PARM_DESC(qos, "Enable QOS support (default on)"); | |
86 | ||
1855ba78 MB |
87 | static int modparam_btcoex = 1; |
88 | module_param_named(btcoex, modparam_btcoex, int, 0444); | |
89 | MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)"); | |
90 | ||
e6f5b934 | 91 | |
e4d6b795 MB |
92 | static const struct ssb_device_id b43_ssb_tbl[] = { |
93 | SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5), | |
94 | SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6), | |
95 | SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7), | |
96 | SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9), | |
97 | SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10), | |
d5c71e46 | 98 | SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11), |
013978b6 | 99 | SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13), |
e4d6b795 MB |
100 | SSB_DEVTABLE_END |
101 | }; | |
102 | ||
103 | MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl); | |
104 | ||
105 | /* Channel and ratetables are shared for all devices. | |
106 | * They can't be const, because ieee80211 puts some precalculated | |
107 | * data in there. This data is the same for all devices, so we don't | |
108 | * get concurrency issues */ | |
109 | #define RATETAB_ENT(_rateid, _flags) \ | |
8318d78a JB |
110 | { \ |
111 | .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \ | |
112 | .hw_value = (_rateid), \ | |
113 | .flags = (_flags), \ | |
e4d6b795 | 114 | } |
8318d78a JB |
115 | |
116 | /* | |
117 | * NOTE: When changing this, sync with xmit.c's | |
118 | * b43_plcp_get_bitrate_idx_* functions! | |
119 | */ | |
e4d6b795 | 120 | static struct ieee80211_rate __b43_ratetable[] = { |
8318d78a JB |
121 | RATETAB_ENT(B43_CCK_RATE_1MB, 0), |
122 | RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE), | |
123 | RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE), | |
124 | RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE), | |
125 | RATETAB_ENT(B43_OFDM_RATE_6MB, 0), | |
126 | RATETAB_ENT(B43_OFDM_RATE_9MB, 0), | |
127 | RATETAB_ENT(B43_OFDM_RATE_12MB, 0), | |
128 | RATETAB_ENT(B43_OFDM_RATE_18MB, 0), | |
129 | RATETAB_ENT(B43_OFDM_RATE_24MB, 0), | |
130 | RATETAB_ENT(B43_OFDM_RATE_36MB, 0), | |
131 | RATETAB_ENT(B43_OFDM_RATE_48MB, 0), | |
132 | RATETAB_ENT(B43_OFDM_RATE_54MB, 0), | |
e4d6b795 MB |
133 | }; |
134 | ||
135 | #define b43_a_ratetable (__b43_ratetable + 4) | |
136 | #define b43_a_ratetable_size 8 | |
137 | #define b43_b_ratetable (__b43_ratetable + 0) | |
138 | #define b43_b_ratetable_size 4 | |
139 | #define b43_g_ratetable (__b43_ratetable + 0) | |
140 | #define b43_g_ratetable_size 12 | |
141 | ||
bb1eeff1 MB |
142 | #define CHAN4G(_channel, _freq, _flags) { \ |
143 | .band = IEEE80211_BAND_2GHZ, \ | |
144 | .center_freq = (_freq), \ | |
145 | .hw_value = (_channel), \ | |
146 | .flags = (_flags), \ | |
147 | .max_antenna_gain = 0, \ | |
148 | .max_power = 30, \ | |
149 | } | |
96c755a3 | 150 | static struct ieee80211_channel b43_2ghz_chantable[] = { |
bb1eeff1 MB |
151 | CHAN4G(1, 2412, 0), |
152 | CHAN4G(2, 2417, 0), | |
153 | CHAN4G(3, 2422, 0), | |
154 | CHAN4G(4, 2427, 0), | |
155 | CHAN4G(5, 2432, 0), | |
156 | CHAN4G(6, 2437, 0), | |
157 | CHAN4G(7, 2442, 0), | |
158 | CHAN4G(8, 2447, 0), | |
159 | CHAN4G(9, 2452, 0), | |
160 | CHAN4G(10, 2457, 0), | |
161 | CHAN4G(11, 2462, 0), | |
162 | CHAN4G(12, 2467, 0), | |
163 | CHAN4G(13, 2472, 0), | |
164 | CHAN4G(14, 2484, 0), | |
165 | }; | |
166 | #undef CHAN4G | |
167 | ||
168 | #define CHAN5G(_channel, _flags) { \ | |
169 | .band = IEEE80211_BAND_5GHZ, \ | |
170 | .center_freq = 5000 + (5 * (_channel)), \ | |
171 | .hw_value = (_channel), \ | |
172 | .flags = (_flags), \ | |
173 | .max_antenna_gain = 0, \ | |
174 | .max_power = 30, \ | |
175 | } | |
176 | static struct ieee80211_channel b43_5ghz_nphy_chantable[] = { | |
177 | CHAN5G(32, 0), CHAN5G(34, 0), | |
178 | CHAN5G(36, 0), CHAN5G(38, 0), | |
179 | CHAN5G(40, 0), CHAN5G(42, 0), | |
180 | CHAN5G(44, 0), CHAN5G(46, 0), | |
181 | CHAN5G(48, 0), CHAN5G(50, 0), | |
182 | CHAN5G(52, 0), CHAN5G(54, 0), | |
183 | CHAN5G(56, 0), CHAN5G(58, 0), | |
184 | CHAN5G(60, 0), CHAN5G(62, 0), | |
185 | CHAN5G(64, 0), CHAN5G(66, 0), | |
186 | CHAN5G(68, 0), CHAN5G(70, 0), | |
187 | CHAN5G(72, 0), CHAN5G(74, 0), | |
188 | CHAN5G(76, 0), CHAN5G(78, 0), | |
189 | CHAN5G(80, 0), CHAN5G(82, 0), | |
190 | CHAN5G(84, 0), CHAN5G(86, 0), | |
191 | CHAN5G(88, 0), CHAN5G(90, 0), | |
192 | CHAN5G(92, 0), CHAN5G(94, 0), | |
193 | CHAN5G(96, 0), CHAN5G(98, 0), | |
194 | CHAN5G(100, 0), CHAN5G(102, 0), | |
195 | CHAN5G(104, 0), CHAN5G(106, 0), | |
196 | CHAN5G(108, 0), CHAN5G(110, 0), | |
197 | CHAN5G(112, 0), CHAN5G(114, 0), | |
198 | CHAN5G(116, 0), CHAN5G(118, 0), | |
199 | CHAN5G(120, 0), CHAN5G(122, 0), | |
200 | CHAN5G(124, 0), CHAN5G(126, 0), | |
201 | CHAN5G(128, 0), CHAN5G(130, 0), | |
202 | CHAN5G(132, 0), CHAN5G(134, 0), | |
203 | CHAN5G(136, 0), CHAN5G(138, 0), | |
204 | CHAN5G(140, 0), CHAN5G(142, 0), | |
205 | CHAN5G(144, 0), CHAN5G(145, 0), | |
206 | CHAN5G(146, 0), CHAN5G(147, 0), | |
207 | CHAN5G(148, 0), CHAN5G(149, 0), | |
208 | CHAN5G(150, 0), CHAN5G(151, 0), | |
209 | CHAN5G(152, 0), CHAN5G(153, 0), | |
210 | CHAN5G(154, 0), CHAN5G(155, 0), | |
211 | CHAN5G(156, 0), CHAN5G(157, 0), | |
212 | CHAN5G(158, 0), CHAN5G(159, 0), | |
213 | CHAN5G(160, 0), CHAN5G(161, 0), | |
214 | CHAN5G(162, 0), CHAN5G(163, 0), | |
215 | CHAN5G(164, 0), CHAN5G(165, 0), | |
216 | CHAN5G(166, 0), CHAN5G(168, 0), | |
217 | CHAN5G(170, 0), CHAN5G(172, 0), | |
218 | CHAN5G(174, 0), CHAN5G(176, 0), | |
219 | CHAN5G(178, 0), CHAN5G(180, 0), | |
220 | CHAN5G(182, 0), CHAN5G(184, 0), | |
221 | CHAN5G(186, 0), CHAN5G(188, 0), | |
222 | CHAN5G(190, 0), CHAN5G(192, 0), | |
223 | CHAN5G(194, 0), CHAN5G(196, 0), | |
224 | CHAN5G(198, 0), CHAN5G(200, 0), | |
225 | CHAN5G(202, 0), CHAN5G(204, 0), | |
226 | CHAN5G(206, 0), CHAN5G(208, 0), | |
227 | CHAN5G(210, 0), CHAN5G(212, 0), | |
228 | CHAN5G(214, 0), CHAN5G(216, 0), | |
229 | CHAN5G(218, 0), CHAN5G(220, 0), | |
230 | CHAN5G(222, 0), CHAN5G(224, 0), | |
231 | CHAN5G(226, 0), CHAN5G(228, 0), | |
e4d6b795 MB |
232 | }; |
233 | ||
bb1eeff1 MB |
234 | static struct ieee80211_channel b43_5ghz_aphy_chantable[] = { |
235 | CHAN5G(34, 0), CHAN5G(36, 0), | |
236 | CHAN5G(38, 0), CHAN5G(40, 0), | |
237 | CHAN5G(42, 0), CHAN5G(44, 0), | |
238 | CHAN5G(46, 0), CHAN5G(48, 0), | |
239 | CHAN5G(52, 0), CHAN5G(56, 0), | |
240 | CHAN5G(60, 0), CHAN5G(64, 0), | |
241 | CHAN5G(100, 0), CHAN5G(104, 0), | |
242 | CHAN5G(108, 0), CHAN5G(112, 0), | |
243 | CHAN5G(116, 0), CHAN5G(120, 0), | |
244 | CHAN5G(124, 0), CHAN5G(128, 0), | |
245 | CHAN5G(132, 0), CHAN5G(136, 0), | |
246 | CHAN5G(140, 0), CHAN5G(149, 0), | |
247 | CHAN5G(153, 0), CHAN5G(157, 0), | |
248 | CHAN5G(161, 0), CHAN5G(165, 0), | |
249 | CHAN5G(184, 0), CHAN5G(188, 0), | |
250 | CHAN5G(192, 0), CHAN5G(196, 0), | |
251 | CHAN5G(200, 0), CHAN5G(204, 0), | |
252 | CHAN5G(208, 0), CHAN5G(212, 0), | |
253 | CHAN5G(216, 0), | |
254 | }; | |
255 | #undef CHAN5G | |
256 | ||
257 | static struct ieee80211_supported_band b43_band_5GHz_nphy = { | |
258 | .band = IEEE80211_BAND_5GHZ, | |
259 | .channels = b43_5ghz_nphy_chantable, | |
260 | .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable), | |
261 | .bitrates = b43_a_ratetable, | |
262 | .n_bitrates = b43_a_ratetable_size, | |
e4d6b795 | 263 | }; |
8318d78a | 264 | |
bb1eeff1 MB |
265 | static struct ieee80211_supported_band b43_band_5GHz_aphy = { |
266 | .band = IEEE80211_BAND_5GHZ, | |
267 | .channels = b43_5ghz_aphy_chantable, | |
268 | .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable), | |
269 | .bitrates = b43_a_ratetable, | |
270 | .n_bitrates = b43_a_ratetable_size, | |
8318d78a | 271 | }; |
e4d6b795 | 272 | |
8318d78a | 273 | static struct ieee80211_supported_band b43_band_2GHz = { |
bb1eeff1 MB |
274 | .band = IEEE80211_BAND_2GHZ, |
275 | .channels = b43_2ghz_chantable, | |
276 | .n_channels = ARRAY_SIZE(b43_2ghz_chantable), | |
277 | .bitrates = b43_g_ratetable, | |
278 | .n_bitrates = b43_g_ratetable_size, | |
8318d78a JB |
279 | }; |
280 | ||
e4d6b795 MB |
281 | static void b43_wireless_core_exit(struct b43_wldev *dev); |
282 | static int b43_wireless_core_init(struct b43_wldev *dev); | |
283 | static void b43_wireless_core_stop(struct b43_wldev *dev); | |
284 | static int b43_wireless_core_start(struct b43_wldev *dev); | |
285 | ||
286 | static int b43_ratelimit(struct b43_wl *wl) | |
287 | { | |
288 | if (!wl || !wl->current_dev) | |
289 | return 1; | |
290 | if (b43_status(wl->current_dev) < B43_STAT_STARTED) | |
291 | return 1; | |
292 | /* We are up and running. | |
293 | * Ratelimit the messages to avoid DoS over the net. */ | |
294 | return net_ratelimit(); | |
295 | } | |
296 | ||
297 | void b43info(struct b43_wl *wl, const char *fmt, ...) | |
298 | { | |
299 | va_list args; | |
300 | ||
301 | if (!b43_ratelimit(wl)) | |
302 | return; | |
303 | va_start(args, fmt); | |
304 | printk(KERN_INFO "b43-%s: ", | |
305 | (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); | |
306 | vprintk(fmt, args); | |
307 | va_end(args); | |
308 | } | |
309 | ||
310 | void b43err(struct b43_wl *wl, const char *fmt, ...) | |
311 | { | |
312 | va_list args; | |
313 | ||
314 | if (!b43_ratelimit(wl)) | |
315 | return; | |
316 | va_start(args, fmt); | |
317 | printk(KERN_ERR "b43-%s ERROR: ", | |
318 | (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); | |
319 | vprintk(fmt, args); | |
320 | va_end(args); | |
321 | } | |
322 | ||
323 | void b43warn(struct b43_wl *wl, const char *fmt, ...) | |
324 | { | |
325 | va_list args; | |
326 | ||
327 | if (!b43_ratelimit(wl)) | |
328 | return; | |
329 | va_start(args, fmt); | |
330 | printk(KERN_WARNING "b43-%s warning: ", | |
331 | (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); | |
332 | vprintk(fmt, args); | |
333 | va_end(args); | |
334 | } | |
335 | ||
336 | #if B43_DEBUG | |
337 | void b43dbg(struct b43_wl *wl, const char *fmt, ...) | |
338 | { | |
339 | va_list args; | |
340 | ||
341 | va_start(args, fmt); | |
342 | printk(KERN_DEBUG "b43-%s debug: ", | |
343 | (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan"); | |
344 | vprintk(fmt, args); | |
345 | va_end(args); | |
346 | } | |
347 | #endif /* DEBUG */ | |
348 | ||
349 | static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val) | |
350 | { | |
351 | u32 macctl; | |
352 | ||
353 | B43_WARN_ON(offset % 4 != 0); | |
354 | ||
355 | macctl = b43_read32(dev, B43_MMIO_MACCTL); | |
356 | if (macctl & B43_MACCTL_BE) | |
357 | val = swab32(val); | |
358 | ||
359 | b43_write32(dev, B43_MMIO_RAM_CONTROL, offset); | |
360 | mmiowb(); | |
361 | b43_write32(dev, B43_MMIO_RAM_DATA, val); | |
362 | } | |
363 | ||
280d0e16 MB |
364 | static inline void b43_shm_control_word(struct b43_wldev *dev, |
365 | u16 routing, u16 offset) | |
e4d6b795 MB |
366 | { |
367 | u32 control; | |
368 | ||
369 | /* "offset" is the WORD offset. */ | |
e4d6b795 MB |
370 | control = routing; |
371 | control <<= 16; | |
372 | control |= offset; | |
373 | b43_write32(dev, B43_MMIO_SHM_CONTROL, control); | |
374 | } | |
375 | ||
376 | u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset) | |
377 | { | |
280d0e16 MB |
378 | struct b43_wl *wl = dev->wl; |
379 | unsigned long flags; | |
e4d6b795 MB |
380 | u32 ret; |
381 | ||
280d0e16 | 382 | spin_lock_irqsave(&wl->shm_lock, flags); |
e4d6b795 MB |
383 | if (routing == B43_SHM_SHARED) { |
384 | B43_WARN_ON(offset & 0x0001); | |
385 | if (offset & 0x0003) { | |
386 | /* Unaligned access */ | |
387 | b43_shm_control_word(dev, routing, offset >> 2); | |
388 | ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); | |
389 | ret <<= 16; | |
390 | b43_shm_control_word(dev, routing, (offset >> 2) + 1); | |
391 | ret |= b43_read16(dev, B43_MMIO_SHM_DATA); | |
392 | ||
280d0e16 | 393 | goto out; |
e4d6b795 MB |
394 | } |
395 | offset >>= 2; | |
396 | } | |
397 | b43_shm_control_word(dev, routing, offset); | |
398 | ret = b43_read32(dev, B43_MMIO_SHM_DATA); | |
280d0e16 MB |
399 | out: |
400 | spin_unlock_irqrestore(&wl->shm_lock, flags); | |
e4d6b795 MB |
401 | |
402 | return ret; | |
403 | } | |
404 | ||
405 | u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset) | |
406 | { | |
280d0e16 MB |
407 | struct b43_wl *wl = dev->wl; |
408 | unsigned long flags; | |
e4d6b795 MB |
409 | u16 ret; |
410 | ||
280d0e16 | 411 | spin_lock_irqsave(&wl->shm_lock, flags); |
e4d6b795 MB |
412 | if (routing == B43_SHM_SHARED) { |
413 | B43_WARN_ON(offset & 0x0001); | |
414 | if (offset & 0x0003) { | |
415 | /* Unaligned access */ | |
416 | b43_shm_control_word(dev, routing, offset >> 2); | |
417 | ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED); | |
418 | ||
280d0e16 | 419 | goto out; |
e4d6b795 MB |
420 | } |
421 | offset >>= 2; | |
422 | } | |
423 | b43_shm_control_word(dev, routing, offset); | |
424 | ret = b43_read16(dev, B43_MMIO_SHM_DATA); | |
280d0e16 MB |
425 | out: |
426 | spin_unlock_irqrestore(&wl->shm_lock, flags); | |
e4d6b795 MB |
427 | |
428 | return ret; | |
429 | } | |
430 | ||
431 | void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value) | |
432 | { | |
280d0e16 MB |
433 | struct b43_wl *wl = dev->wl; |
434 | unsigned long flags; | |
435 | ||
436 | spin_lock_irqsave(&wl->shm_lock, flags); | |
e4d6b795 MB |
437 | if (routing == B43_SHM_SHARED) { |
438 | B43_WARN_ON(offset & 0x0001); | |
439 | if (offset & 0x0003) { | |
440 | /* Unaligned access */ | |
441 | b43_shm_control_word(dev, routing, offset >> 2); | |
e4d6b795 MB |
442 | b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, |
443 | (value >> 16) & 0xffff); | |
e4d6b795 | 444 | b43_shm_control_word(dev, routing, (offset >> 2) + 1); |
e4d6b795 | 445 | b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff); |
280d0e16 | 446 | goto out; |
e4d6b795 MB |
447 | } |
448 | offset >>= 2; | |
449 | } | |
450 | b43_shm_control_word(dev, routing, offset); | |
e4d6b795 | 451 | b43_write32(dev, B43_MMIO_SHM_DATA, value); |
280d0e16 MB |
452 | out: |
453 | spin_unlock_irqrestore(&wl->shm_lock, flags); | |
e4d6b795 MB |
454 | } |
455 | ||
456 | void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value) | |
457 | { | |
280d0e16 MB |
458 | struct b43_wl *wl = dev->wl; |
459 | unsigned long flags; | |
460 | ||
461 | spin_lock_irqsave(&wl->shm_lock, flags); | |
e4d6b795 MB |
462 | if (routing == B43_SHM_SHARED) { |
463 | B43_WARN_ON(offset & 0x0001); | |
464 | if (offset & 0x0003) { | |
465 | /* Unaligned access */ | |
466 | b43_shm_control_word(dev, routing, offset >> 2); | |
e4d6b795 | 467 | b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value); |
280d0e16 | 468 | goto out; |
e4d6b795 MB |
469 | } |
470 | offset >>= 2; | |
471 | } | |
472 | b43_shm_control_word(dev, routing, offset); | |
e4d6b795 | 473 | b43_write16(dev, B43_MMIO_SHM_DATA, value); |
280d0e16 MB |
474 | out: |
475 | spin_unlock_irqrestore(&wl->shm_lock, flags); | |
e4d6b795 MB |
476 | } |
477 | ||
478 | /* Read HostFlags */ | |
35f0d354 | 479 | u64 b43_hf_read(struct b43_wldev * dev) |
e4d6b795 | 480 | { |
35f0d354 | 481 | u64 ret; |
e4d6b795 MB |
482 | |
483 | ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI); | |
484 | ret <<= 16; | |
35f0d354 MB |
485 | ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI); |
486 | ret <<= 16; | |
e4d6b795 MB |
487 | ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO); |
488 | ||
489 | return ret; | |
490 | } | |
491 | ||
492 | /* Write HostFlags */ | |
35f0d354 | 493 | void b43_hf_write(struct b43_wldev *dev, u64 value) |
e4d6b795 | 494 | { |
35f0d354 MB |
495 | u16 lo, mi, hi; |
496 | ||
497 | lo = (value & 0x00000000FFFFULL); | |
498 | mi = (value & 0x0000FFFF0000ULL) >> 16; | |
499 | hi = (value & 0xFFFF00000000ULL) >> 32; | |
500 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo); | |
501 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi); | |
502 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi); | |
e4d6b795 MB |
503 | } |
504 | ||
505 | void b43_tsf_read(struct b43_wldev *dev, u64 * tsf) | |
506 | { | |
507 | /* We need to be careful. As we read the TSF from multiple | |
508 | * registers, we should take care of register overflows. | |
509 | * In theory, the whole tsf read process should be atomic. | |
510 | * We try to be atomic here, by restaring the read process, | |
511 | * if any of the high registers changed (overflew). | |
512 | */ | |
513 | if (dev->dev->id.revision >= 3) { | |
514 | u32 low, high, high2; | |
515 | ||
516 | do { | |
517 | high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); | |
518 | low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW); | |
519 | high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH); | |
520 | } while (unlikely(high != high2)); | |
521 | ||
522 | *tsf = high; | |
523 | *tsf <<= 32; | |
524 | *tsf |= low; | |
525 | } else { | |
526 | u64 tmp; | |
527 | u16 v0, v1, v2, v3; | |
528 | u16 test1, test2, test3; | |
529 | ||
530 | do { | |
531 | v3 = b43_read16(dev, B43_MMIO_TSF_3); | |
532 | v2 = b43_read16(dev, B43_MMIO_TSF_2); | |
533 | v1 = b43_read16(dev, B43_MMIO_TSF_1); | |
534 | v0 = b43_read16(dev, B43_MMIO_TSF_0); | |
535 | ||
536 | test3 = b43_read16(dev, B43_MMIO_TSF_3); | |
537 | test2 = b43_read16(dev, B43_MMIO_TSF_2); | |
538 | test1 = b43_read16(dev, B43_MMIO_TSF_1); | |
539 | } while (v3 != test3 || v2 != test2 || v1 != test1); | |
540 | ||
541 | *tsf = v3; | |
542 | *tsf <<= 48; | |
543 | tmp = v2; | |
544 | tmp <<= 32; | |
545 | *tsf |= tmp; | |
546 | tmp = v1; | |
547 | tmp <<= 16; | |
548 | *tsf |= tmp; | |
549 | *tsf |= v0; | |
550 | } | |
551 | } | |
552 | ||
553 | static void b43_time_lock(struct b43_wldev *dev) | |
554 | { | |
555 | u32 macctl; | |
556 | ||
557 | macctl = b43_read32(dev, B43_MMIO_MACCTL); | |
558 | macctl |= B43_MACCTL_TBTTHOLD; | |
559 | b43_write32(dev, B43_MMIO_MACCTL, macctl); | |
560 | /* Commit the write */ | |
561 | b43_read32(dev, B43_MMIO_MACCTL); | |
562 | } | |
563 | ||
564 | static void b43_time_unlock(struct b43_wldev *dev) | |
565 | { | |
566 | u32 macctl; | |
567 | ||
568 | macctl = b43_read32(dev, B43_MMIO_MACCTL); | |
569 | macctl &= ~B43_MACCTL_TBTTHOLD; | |
570 | b43_write32(dev, B43_MMIO_MACCTL, macctl); | |
571 | /* Commit the write */ | |
572 | b43_read32(dev, B43_MMIO_MACCTL); | |
573 | } | |
574 | ||
575 | static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf) | |
576 | { | |
577 | /* Be careful with the in-progress timer. | |
578 | * First zero out the low register, so we have a full | |
579 | * register-overflow duration to complete the operation. | |
580 | */ | |
581 | if (dev->dev->id.revision >= 3) { | |
582 | u32 lo = (tsf & 0x00000000FFFFFFFFULL); | |
583 | u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32; | |
584 | ||
585 | b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0); | |
586 | mmiowb(); | |
587 | b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi); | |
588 | mmiowb(); | |
589 | b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo); | |
590 | } else { | |
591 | u16 v0 = (tsf & 0x000000000000FFFFULL); | |
592 | u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16; | |
593 | u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32; | |
594 | u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48; | |
595 | ||
596 | b43_write16(dev, B43_MMIO_TSF_0, 0); | |
597 | mmiowb(); | |
598 | b43_write16(dev, B43_MMIO_TSF_3, v3); | |
599 | mmiowb(); | |
600 | b43_write16(dev, B43_MMIO_TSF_2, v2); | |
601 | mmiowb(); | |
602 | b43_write16(dev, B43_MMIO_TSF_1, v1); | |
603 | mmiowb(); | |
604 | b43_write16(dev, B43_MMIO_TSF_0, v0); | |
605 | } | |
606 | } | |
607 | ||
608 | void b43_tsf_write(struct b43_wldev *dev, u64 tsf) | |
609 | { | |
610 | b43_time_lock(dev); | |
611 | b43_tsf_write_locked(dev, tsf); | |
612 | b43_time_unlock(dev); | |
613 | } | |
614 | ||
615 | static | |
616 | void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac) | |
617 | { | |
618 | static const u8 zero_addr[ETH_ALEN] = { 0 }; | |
619 | u16 data; | |
620 | ||
621 | if (!mac) | |
622 | mac = zero_addr; | |
623 | ||
624 | offset |= 0x0020; | |
625 | b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset); | |
626 | ||
627 | data = mac[0]; | |
628 | data |= mac[1] << 8; | |
629 | b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); | |
630 | data = mac[2]; | |
631 | data |= mac[3] << 8; | |
632 | b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); | |
633 | data = mac[4]; | |
634 | data |= mac[5] << 8; | |
635 | b43_write16(dev, B43_MMIO_MACFILTER_DATA, data); | |
636 | } | |
637 | ||
638 | static void b43_write_mac_bssid_templates(struct b43_wldev *dev) | |
639 | { | |
640 | const u8 *mac; | |
641 | const u8 *bssid; | |
642 | u8 mac_bssid[ETH_ALEN * 2]; | |
643 | int i; | |
644 | u32 tmp; | |
645 | ||
646 | bssid = dev->wl->bssid; | |
647 | mac = dev->wl->mac_addr; | |
648 | ||
649 | b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid); | |
650 | ||
651 | memcpy(mac_bssid, mac, ETH_ALEN); | |
652 | memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN); | |
653 | ||
654 | /* Write our MAC address and BSSID to template ram */ | |
655 | for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) { | |
656 | tmp = (u32) (mac_bssid[i + 0]); | |
657 | tmp |= (u32) (mac_bssid[i + 1]) << 8; | |
658 | tmp |= (u32) (mac_bssid[i + 2]) << 16; | |
659 | tmp |= (u32) (mac_bssid[i + 3]) << 24; | |
660 | b43_ram_write(dev, 0x20 + i, tmp); | |
661 | } | |
662 | } | |
663 | ||
4150c572 | 664 | static void b43_upload_card_macaddress(struct b43_wldev *dev) |
e4d6b795 | 665 | { |
e4d6b795 | 666 | b43_write_mac_bssid_templates(dev); |
4150c572 | 667 | b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr); |
e4d6b795 MB |
668 | } |
669 | ||
670 | static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time) | |
671 | { | |
672 | /* slot_time is in usec. */ | |
673 | if (dev->phy.type != B43_PHYTYPE_G) | |
674 | return; | |
675 | b43_write16(dev, 0x684, 510 + slot_time); | |
676 | b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time); | |
677 | } | |
678 | ||
679 | static void b43_short_slot_timing_enable(struct b43_wldev *dev) | |
680 | { | |
681 | b43_set_slot_time(dev, 9); | |
682 | dev->short_slot = 1; | |
683 | } | |
684 | ||
685 | static void b43_short_slot_timing_disable(struct b43_wldev *dev) | |
686 | { | |
687 | b43_set_slot_time(dev, 20); | |
688 | dev->short_slot = 0; | |
689 | } | |
690 | ||
691 | /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable. | |
692 | * Returns the _previously_ enabled IRQ mask. | |
693 | */ | |
694 | static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask) | |
695 | { | |
696 | u32 old_mask; | |
697 | ||
698 | old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); | |
699 | b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask); | |
700 | ||
701 | return old_mask; | |
702 | } | |
703 | ||
704 | /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable. | |
705 | * Returns the _previously_ enabled IRQ mask. | |
706 | */ | |
707 | static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask) | |
708 | { | |
709 | u32 old_mask; | |
710 | ||
711 | old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); | |
712 | b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask); | |
713 | ||
714 | return old_mask; | |
715 | } | |
716 | ||
717 | /* Synchronize IRQ top- and bottom-half. | |
718 | * IRQs must be masked before calling this. | |
719 | * This must not be called with the irq_lock held. | |
720 | */ | |
721 | static void b43_synchronize_irq(struct b43_wldev *dev) | |
722 | { | |
723 | synchronize_irq(dev->dev->irq); | |
724 | tasklet_kill(&dev->isr_tasklet); | |
725 | } | |
726 | ||
727 | /* DummyTransmission function, as documented on | |
728 | * http://bcm-specs.sipsolutions.net/DummyTransmission | |
729 | */ | |
730 | void b43_dummy_transmission(struct b43_wldev *dev) | |
731 | { | |
21a75d77 | 732 | struct b43_wl *wl = dev->wl; |
e4d6b795 MB |
733 | struct b43_phy *phy = &dev->phy; |
734 | unsigned int i, max_loop; | |
735 | u16 value; | |
736 | u32 buffer[5] = { | |
737 | 0x00000000, | |
738 | 0x00D40000, | |
739 | 0x00000000, | |
740 | 0x01000000, | |
741 | 0x00000000, | |
742 | }; | |
743 | ||
744 | switch (phy->type) { | |
745 | case B43_PHYTYPE_A: | |
746 | max_loop = 0x1E; | |
747 | buffer[0] = 0x000201CC; | |
748 | break; | |
749 | case B43_PHYTYPE_B: | |
750 | case B43_PHYTYPE_G: | |
751 | max_loop = 0xFA; | |
752 | buffer[0] = 0x000B846E; | |
753 | break; | |
754 | default: | |
755 | B43_WARN_ON(1); | |
756 | return; | |
757 | } | |
758 | ||
21a75d77 MB |
759 | spin_lock_irq(&wl->irq_lock); |
760 | write_lock(&wl->tx_lock); | |
761 | ||
e4d6b795 MB |
762 | for (i = 0; i < 5; i++) |
763 | b43_ram_write(dev, i * 4, buffer[i]); | |
764 | ||
765 | /* Commit writes */ | |
766 | b43_read32(dev, B43_MMIO_MACCTL); | |
767 | ||
768 | b43_write16(dev, 0x0568, 0x0000); | |
769 | b43_write16(dev, 0x07C0, 0x0000); | |
770 | value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0); | |
771 | b43_write16(dev, 0x050C, value); | |
772 | b43_write16(dev, 0x0508, 0x0000); | |
773 | b43_write16(dev, 0x050A, 0x0000); | |
774 | b43_write16(dev, 0x054C, 0x0000); | |
775 | b43_write16(dev, 0x056A, 0x0014); | |
776 | b43_write16(dev, 0x0568, 0x0826); | |
777 | b43_write16(dev, 0x0500, 0x0000); | |
778 | b43_write16(dev, 0x0502, 0x0030); | |
779 | ||
780 | if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) | |
781 | b43_radio_write16(dev, 0x0051, 0x0017); | |
782 | for (i = 0x00; i < max_loop; i++) { | |
783 | value = b43_read16(dev, 0x050E); | |
784 | if (value & 0x0080) | |
785 | break; | |
786 | udelay(10); | |
787 | } | |
788 | for (i = 0x00; i < 0x0A; i++) { | |
789 | value = b43_read16(dev, 0x050E); | |
790 | if (value & 0x0400) | |
791 | break; | |
792 | udelay(10); | |
793 | } | |
794 | for (i = 0x00; i < 0x0A; i++) { | |
795 | value = b43_read16(dev, 0x0690); | |
796 | if (!(value & 0x0100)) | |
797 | break; | |
798 | udelay(10); | |
799 | } | |
800 | if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5) | |
801 | b43_radio_write16(dev, 0x0051, 0x0037); | |
21a75d77 MB |
802 | |
803 | write_unlock(&wl->tx_lock); | |
804 | spin_unlock_irq(&wl->irq_lock); | |
e4d6b795 MB |
805 | } |
806 | ||
807 | static void key_write(struct b43_wldev *dev, | |
808 | u8 index, u8 algorithm, const u8 * key) | |
809 | { | |
810 | unsigned int i; | |
811 | u32 offset; | |
812 | u16 value; | |
813 | u16 kidx; | |
814 | ||
815 | /* Key index/algo block */ | |
816 | kidx = b43_kidx_to_fw(dev, index); | |
817 | value = ((kidx << 4) | algorithm); | |
818 | b43_shm_write16(dev, B43_SHM_SHARED, | |
819 | B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value); | |
820 | ||
821 | /* Write the key to the Key Table Pointer offset */ | |
822 | offset = dev->ktp + (index * B43_SEC_KEYSIZE); | |
823 | for (i = 0; i < B43_SEC_KEYSIZE; i += 2) { | |
824 | value = key[i]; | |
825 | value |= (u16) (key[i + 1]) << 8; | |
826 | b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value); | |
827 | } | |
828 | } | |
829 | ||
830 | static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr) | |
831 | { | |
832 | u32 addrtmp[2] = { 0, 0, }; | |
833 | u8 per_sta_keys_start = 8; | |
834 | ||
835 | if (b43_new_kidx_api(dev)) | |
836 | per_sta_keys_start = 4; | |
837 | ||
838 | B43_WARN_ON(index < per_sta_keys_start); | |
839 | /* We have two default TX keys and possibly two default RX keys. | |
840 | * Physical mac 0 is mapped to physical key 4 or 8, depending | |
841 | * on the firmware version. | |
842 | * So we must adjust the index here. | |
843 | */ | |
844 | index -= per_sta_keys_start; | |
845 | ||
846 | if (addr) { | |
847 | addrtmp[0] = addr[0]; | |
848 | addrtmp[0] |= ((u32) (addr[1]) << 8); | |
849 | addrtmp[0] |= ((u32) (addr[2]) << 16); | |
850 | addrtmp[0] |= ((u32) (addr[3]) << 24); | |
851 | addrtmp[1] = addr[4]; | |
852 | addrtmp[1] |= ((u32) (addr[5]) << 8); | |
853 | } | |
854 | ||
855 | if (dev->dev->id.revision >= 5) { | |
856 | /* Receive match transmitter address mechanism */ | |
857 | b43_shm_write32(dev, B43_SHM_RCMTA, | |
858 | (index * 2) + 0, addrtmp[0]); | |
859 | b43_shm_write16(dev, B43_SHM_RCMTA, | |
860 | (index * 2) + 1, addrtmp[1]); | |
861 | } else { | |
862 | /* RXE (Receive Engine) and | |
863 | * PSM (Programmable State Machine) mechanism | |
864 | */ | |
865 | if (index < 8) { | |
866 | /* TODO write to RCM 16, 19, 22 and 25 */ | |
867 | } else { | |
868 | b43_shm_write32(dev, B43_SHM_SHARED, | |
869 | B43_SHM_SH_PSM + (index * 6) + 0, | |
870 | addrtmp[0]); | |
871 | b43_shm_write16(dev, B43_SHM_SHARED, | |
872 | B43_SHM_SH_PSM + (index * 6) + 4, | |
873 | addrtmp[1]); | |
874 | } | |
875 | } | |
876 | } | |
877 | ||
878 | static void do_key_write(struct b43_wldev *dev, | |
879 | u8 index, u8 algorithm, | |
880 | const u8 * key, size_t key_len, const u8 * mac_addr) | |
881 | { | |
882 | u8 buf[B43_SEC_KEYSIZE] = { 0, }; | |
883 | u8 per_sta_keys_start = 8; | |
884 | ||
885 | if (b43_new_kidx_api(dev)) | |
886 | per_sta_keys_start = 4; | |
887 | ||
888 | B43_WARN_ON(index >= dev->max_nr_keys); | |
889 | B43_WARN_ON(key_len > B43_SEC_KEYSIZE); | |
890 | ||
891 | if (index >= per_sta_keys_start) | |
892 | keymac_write(dev, index, NULL); /* First zero out mac. */ | |
893 | if (key) | |
894 | memcpy(buf, key, key_len); | |
895 | key_write(dev, index, algorithm, buf); | |
896 | if (index >= per_sta_keys_start) | |
897 | keymac_write(dev, index, mac_addr); | |
898 | ||
899 | dev->key[index].algorithm = algorithm; | |
900 | } | |
901 | ||
902 | static int b43_key_write(struct b43_wldev *dev, | |
903 | int index, u8 algorithm, | |
904 | const u8 * key, size_t key_len, | |
905 | const u8 * mac_addr, | |
906 | struct ieee80211_key_conf *keyconf) | |
907 | { | |
908 | int i; | |
909 | int sta_keys_start; | |
910 | ||
911 | if (key_len > B43_SEC_KEYSIZE) | |
912 | return -EINVAL; | |
913 | for (i = 0; i < dev->max_nr_keys; i++) { | |
914 | /* Check that we don't already have this key. */ | |
915 | B43_WARN_ON(dev->key[i].keyconf == keyconf); | |
916 | } | |
917 | if (index < 0) { | |
918 | /* Either pairwise key or address is 00:00:00:00:00:00 | |
919 | * for transmit-only keys. Search the index. */ | |
920 | if (b43_new_kidx_api(dev)) | |
921 | sta_keys_start = 4; | |
922 | else | |
923 | sta_keys_start = 8; | |
924 | for (i = sta_keys_start; i < dev->max_nr_keys; i++) { | |
925 | if (!dev->key[i].keyconf) { | |
926 | /* found empty */ | |
927 | index = i; | |
928 | break; | |
929 | } | |
930 | } | |
931 | if (index < 0) { | |
932 | b43err(dev->wl, "Out of hardware key memory\n"); | |
933 | return -ENOSPC; | |
934 | } | |
935 | } else | |
936 | B43_WARN_ON(index > 3); | |
937 | ||
938 | do_key_write(dev, index, algorithm, key, key_len, mac_addr); | |
939 | if ((index <= 3) && !b43_new_kidx_api(dev)) { | |
940 | /* Default RX key */ | |
941 | B43_WARN_ON(mac_addr); | |
942 | do_key_write(dev, index + 4, algorithm, key, key_len, NULL); | |
943 | } | |
944 | keyconf->hw_key_idx = index; | |
945 | dev->key[index].keyconf = keyconf; | |
946 | ||
947 | return 0; | |
948 | } | |
949 | ||
950 | static int b43_key_clear(struct b43_wldev *dev, int index) | |
951 | { | |
952 | if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys))) | |
953 | return -EINVAL; | |
954 | do_key_write(dev, index, B43_SEC_ALGO_NONE, | |
955 | NULL, B43_SEC_KEYSIZE, NULL); | |
956 | if ((index <= 3) && !b43_new_kidx_api(dev)) { | |
957 | do_key_write(dev, index + 4, B43_SEC_ALGO_NONE, | |
958 | NULL, B43_SEC_KEYSIZE, NULL); | |
959 | } | |
960 | dev->key[index].keyconf = NULL; | |
961 | ||
962 | return 0; | |
963 | } | |
964 | ||
965 | static void b43_clear_keys(struct b43_wldev *dev) | |
966 | { | |
967 | int i; | |
968 | ||
969 | for (i = 0; i < dev->max_nr_keys; i++) | |
970 | b43_key_clear(dev, i); | |
971 | } | |
972 | ||
973 | void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags) | |
974 | { | |
975 | u32 macctl; | |
976 | u16 ucstat; | |
977 | bool hwps; | |
978 | bool awake; | |
979 | int i; | |
980 | ||
981 | B43_WARN_ON((ps_flags & B43_PS_ENABLED) && | |
982 | (ps_flags & B43_PS_DISABLED)); | |
983 | B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP)); | |
984 | ||
985 | if (ps_flags & B43_PS_ENABLED) { | |
986 | hwps = 1; | |
987 | } else if (ps_flags & B43_PS_DISABLED) { | |
988 | hwps = 0; | |
989 | } else { | |
990 | //TODO: If powersave is not off and FIXME is not set and we are not in adhoc | |
991 | // and thus is not an AP and we are associated, set bit 25 | |
992 | } | |
993 | if (ps_flags & B43_PS_AWAKE) { | |
994 | awake = 1; | |
995 | } else if (ps_flags & B43_PS_ASLEEP) { | |
996 | awake = 0; | |
997 | } else { | |
998 | //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME, | |
999 | // or we are associated, or FIXME, or the latest PS-Poll packet sent was | |
1000 | // successful, set bit26 | |
1001 | } | |
1002 | ||
1003 | /* FIXME: For now we force awake-on and hwps-off */ | |
1004 | hwps = 0; | |
1005 | awake = 1; | |
1006 | ||
1007 | macctl = b43_read32(dev, B43_MMIO_MACCTL); | |
1008 | if (hwps) | |
1009 | macctl |= B43_MACCTL_HWPS; | |
1010 | else | |
1011 | macctl &= ~B43_MACCTL_HWPS; | |
1012 | if (awake) | |
1013 | macctl |= B43_MACCTL_AWAKE; | |
1014 | else | |
1015 | macctl &= ~B43_MACCTL_AWAKE; | |
1016 | b43_write32(dev, B43_MMIO_MACCTL, macctl); | |
1017 | /* Commit write */ | |
1018 | b43_read32(dev, B43_MMIO_MACCTL); | |
1019 | if (awake && dev->dev->id.revision >= 5) { | |
1020 | /* Wait for the microcode to wake up. */ | |
1021 | for (i = 0; i < 100; i++) { | |
1022 | ucstat = b43_shm_read16(dev, B43_SHM_SHARED, | |
1023 | B43_SHM_SH_UCODESTAT); | |
1024 | if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP) | |
1025 | break; | |
1026 | udelay(10); | |
1027 | } | |
1028 | } | |
1029 | } | |
1030 | ||
1031 | /* Turn the Analog ON/OFF */ | |
1032 | static void b43_switch_analog(struct b43_wldev *dev, int on) | |
1033 | { | |
7b584163 MB |
1034 | switch (dev->phy.type) { |
1035 | case B43_PHYTYPE_A: | |
1036 | case B43_PHYTYPE_G: | |
1037 | b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4); | |
1038 | break; | |
1039 | case B43_PHYTYPE_N: | |
1040 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, | |
1041 | on ? 0 : 0x7FFF); | |
1042 | break; | |
1043 | default: | |
1044 | B43_WARN_ON(1); | |
1045 | } | |
e4d6b795 MB |
1046 | } |
1047 | ||
1048 | void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags) | |
1049 | { | |
1050 | u32 tmslow; | |
1051 | u32 macctl; | |
1052 | ||
1053 | flags |= B43_TMSLOW_PHYCLKEN; | |
1054 | flags |= B43_TMSLOW_PHYRESET; | |
1055 | ssb_device_enable(dev->dev, flags); | |
1056 | msleep(2); /* Wait for the PLL to turn on. */ | |
1057 | ||
1058 | /* Now take the PHY out of Reset again */ | |
1059 | tmslow = ssb_read32(dev->dev, SSB_TMSLOW); | |
1060 | tmslow |= SSB_TMSLOW_FGC; | |
1061 | tmslow &= ~B43_TMSLOW_PHYRESET; | |
1062 | ssb_write32(dev->dev, SSB_TMSLOW, tmslow); | |
1063 | ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ | |
1064 | msleep(1); | |
1065 | tmslow &= ~SSB_TMSLOW_FGC; | |
1066 | ssb_write32(dev->dev, SSB_TMSLOW, tmslow); | |
1067 | ssb_read32(dev->dev, SSB_TMSLOW); /* flush */ | |
1068 | msleep(1); | |
1069 | ||
1070 | /* Turn Analog ON */ | |
1071 | b43_switch_analog(dev, 1); | |
1072 | ||
1073 | macctl = b43_read32(dev, B43_MMIO_MACCTL); | |
1074 | macctl &= ~B43_MACCTL_GMODE; | |
1075 | if (flags & B43_TMSLOW_GMODE) | |
1076 | macctl |= B43_MACCTL_GMODE; | |
1077 | macctl |= B43_MACCTL_IHR_ENABLED; | |
1078 | b43_write32(dev, B43_MMIO_MACCTL, macctl); | |
1079 | } | |
1080 | ||
1081 | static void handle_irq_transmit_status(struct b43_wldev *dev) | |
1082 | { | |
1083 | u32 v0, v1; | |
1084 | u16 tmp; | |
1085 | struct b43_txstatus stat; | |
1086 | ||
1087 | while (1) { | |
1088 | v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0); | |
1089 | if (!(v0 & 0x00000001)) | |
1090 | break; | |
1091 | v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1); | |
1092 | ||
1093 | stat.cookie = (v0 >> 16); | |
1094 | stat.seq = (v1 & 0x0000FFFF); | |
1095 | stat.phy_stat = ((v1 & 0x00FF0000) >> 16); | |
1096 | tmp = (v0 & 0x0000FFFF); | |
1097 | stat.frame_count = ((tmp & 0xF000) >> 12); | |
1098 | stat.rts_count = ((tmp & 0x0F00) >> 8); | |
1099 | stat.supp_reason = ((tmp & 0x001C) >> 2); | |
1100 | stat.pm_indicated = !!(tmp & 0x0080); | |
1101 | stat.intermediate = !!(tmp & 0x0040); | |
1102 | stat.for_ampdu = !!(tmp & 0x0020); | |
1103 | stat.acked = !!(tmp & 0x0002); | |
1104 | ||
1105 | b43_handle_txstatus(dev, &stat); | |
1106 | } | |
1107 | } | |
1108 | ||
1109 | static void drain_txstatus_queue(struct b43_wldev *dev) | |
1110 | { | |
1111 | u32 dummy; | |
1112 | ||
1113 | if (dev->dev->id.revision < 5) | |
1114 | return; | |
1115 | /* Read all entries from the microcode TXstatus FIFO | |
1116 | * and throw them away. | |
1117 | */ | |
1118 | while (1) { | |
1119 | dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0); | |
1120 | if (!(dummy & 0x00000001)) | |
1121 | break; | |
1122 | dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1); | |
1123 | } | |
1124 | } | |
1125 | ||
1126 | static u32 b43_jssi_read(struct b43_wldev *dev) | |
1127 | { | |
1128 | u32 val = 0; | |
1129 | ||
1130 | val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A); | |
1131 | val <<= 16; | |
1132 | val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088); | |
1133 | ||
1134 | return val; | |
1135 | } | |
1136 | ||
1137 | static void b43_jssi_write(struct b43_wldev *dev, u32 jssi) | |
1138 | { | |
1139 | b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF)); | |
1140 | b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16); | |
1141 | } | |
1142 | ||
1143 | static void b43_generate_noise_sample(struct b43_wldev *dev) | |
1144 | { | |
1145 | b43_jssi_write(dev, 0x7F7F7F7F); | |
aa6c7ae2 MB |
1146 | b43_write32(dev, B43_MMIO_MACCMD, |
1147 | b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE); | |
e4d6b795 MB |
1148 | B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel); |
1149 | } | |
1150 | ||
1151 | static void b43_calculate_link_quality(struct b43_wldev *dev) | |
1152 | { | |
1153 | /* Top half of Link Quality calculation. */ | |
1154 | ||
1155 | if (dev->noisecalc.calculation_running) | |
1156 | return; | |
1157 | dev->noisecalc.channel_at_start = dev->phy.channel; | |
1158 | dev->noisecalc.calculation_running = 1; | |
1159 | dev->noisecalc.nr_samples = 0; | |
1160 | ||
1161 | b43_generate_noise_sample(dev); | |
1162 | } | |
1163 | ||
1164 | static void handle_irq_noise(struct b43_wldev *dev) | |
1165 | { | |
1166 | struct b43_phy *phy = &dev->phy; | |
1167 | u16 tmp; | |
1168 | u8 noise[4]; | |
1169 | u8 i, j; | |
1170 | s32 average; | |
1171 | ||
1172 | /* Bottom half of Link Quality calculation. */ | |
1173 | ||
1174 | B43_WARN_ON(!dev->noisecalc.calculation_running); | |
1175 | if (dev->noisecalc.channel_at_start != phy->channel) | |
1176 | goto drop_calculation; | |
1a09404a | 1177 | *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev)); |
e4d6b795 MB |
1178 | if (noise[0] == 0x7F || noise[1] == 0x7F || |
1179 | noise[2] == 0x7F || noise[3] == 0x7F) | |
1180 | goto generate_new; | |
1181 | ||
1182 | /* Get the noise samples. */ | |
1183 | B43_WARN_ON(dev->noisecalc.nr_samples >= 8); | |
1184 | i = dev->noisecalc.nr_samples; | |
1185 | noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); | |
1186 | noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); | |
1187 | noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); | |
1188 | noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1); | |
1189 | dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]]; | |
1190 | dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]]; | |
1191 | dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]]; | |
1192 | dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]]; | |
1193 | dev->noisecalc.nr_samples++; | |
1194 | if (dev->noisecalc.nr_samples == 8) { | |
1195 | /* Calculate the Link Quality by the noise samples. */ | |
1196 | average = 0; | |
1197 | for (i = 0; i < 8; i++) { | |
1198 | for (j = 0; j < 4; j++) | |
1199 | average += dev->noisecalc.samples[i][j]; | |
1200 | } | |
1201 | average /= (8 * 4); | |
1202 | average *= 125; | |
1203 | average += 64; | |
1204 | average /= 128; | |
1205 | tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C); | |
1206 | tmp = (tmp / 128) & 0x1F; | |
1207 | if (tmp >= 8) | |
1208 | average += 2; | |
1209 | else | |
1210 | average -= 25; | |
1211 | if (tmp == 8) | |
1212 | average -= 72; | |
1213 | else | |
1214 | average -= 48; | |
1215 | ||
1216 | dev->stats.link_noise = average; | |
1217 | drop_calculation: | |
1218 | dev->noisecalc.calculation_running = 0; | |
1219 | return; | |
1220 | } | |
1221 | generate_new: | |
1222 | b43_generate_noise_sample(dev); | |
1223 | } | |
1224 | ||
1225 | static void handle_irq_tbtt_indication(struct b43_wldev *dev) | |
1226 | { | |
1227 | if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) { | |
1228 | ///TODO: PS TBTT | |
1229 | } else { | |
1230 | if (1 /*FIXME: the last PSpoll frame was sent successfully */ ) | |
1231 | b43_power_saving_ctl_bits(dev, 0); | |
1232 | } | |
e4d6b795 | 1233 | if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) |
aa6c7ae2 | 1234 | dev->dfq_valid = 1; |
e4d6b795 MB |
1235 | } |
1236 | ||
1237 | static void handle_irq_atim_end(struct b43_wldev *dev) | |
1238 | { | |
aa6c7ae2 MB |
1239 | if (dev->dfq_valid) { |
1240 | b43_write32(dev, B43_MMIO_MACCMD, | |
1241 | b43_read32(dev, B43_MMIO_MACCMD) | |
1242 | | B43_MACCMD_DFQ_VALID); | |
1243 | dev->dfq_valid = 0; | |
1244 | } | |
e4d6b795 MB |
1245 | } |
1246 | ||
1247 | static void handle_irq_pmq(struct b43_wldev *dev) | |
1248 | { | |
1249 | u32 tmp; | |
1250 | ||
1251 | //TODO: AP mode. | |
1252 | ||
1253 | while (1) { | |
1254 | tmp = b43_read32(dev, B43_MMIO_PS_STATUS); | |
1255 | if (!(tmp & 0x00000008)) | |
1256 | break; | |
1257 | } | |
1258 | /* 16bit write is odd, but correct. */ | |
1259 | b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002); | |
1260 | } | |
1261 | ||
1262 | static void b43_write_template_common(struct b43_wldev *dev, | |
1263 | const u8 * data, u16 size, | |
1264 | u16 ram_offset, | |
1265 | u16 shm_size_offset, u8 rate) | |
1266 | { | |
1267 | u32 i, tmp; | |
1268 | struct b43_plcp_hdr4 plcp; | |
1269 | ||
1270 | plcp.data = 0; | |
1271 | b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate); | |
1272 | b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data)); | |
1273 | ram_offset += sizeof(u32); | |
1274 | /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet. | |
1275 | * So leave the first two bytes of the next write blank. | |
1276 | */ | |
1277 | tmp = (u32) (data[0]) << 16; | |
1278 | tmp |= (u32) (data[1]) << 24; | |
1279 | b43_ram_write(dev, ram_offset, tmp); | |
1280 | ram_offset += sizeof(u32); | |
1281 | for (i = 2; i < size; i += sizeof(u32)) { | |
1282 | tmp = (u32) (data[i + 0]); | |
1283 | if (i + 1 < size) | |
1284 | tmp |= (u32) (data[i + 1]) << 8; | |
1285 | if (i + 2 < size) | |
1286 | tmp |= (u32) (data[i + 2]) << 16; | |
1287 | if (i + 3 < size) | |
1288 | tmp |= (u32) (data[i + 3]) << 24; | |
1289 | b43_ram_write(dev, ram_offset + i - 2, tmp); | |
1290 | } | |
1291 | b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset, | |
1292 | size + sizeof(struct b43_plcp_hdr6)); | |
1293 | } | |
1294 | ||
5042c507 MB |
1295 | /* Check if the use of the antenna that ieee80211 told us to |
1296 | * use is possible. This will fall back to DEFAULT. | |
1297 | * "antenna_nr" is the antenna identifier we got from ieee80211. */ | |
1298 | u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev, | |
1299 | u8 antenna_nr) | |
1300 | { | |
1301 | u8 antenna_mask; | |
1302 | ||
1303 | if (antenna_nr == 0) { | |
1304 | /* Zero means "use default antenna". That's always OK. */ | |
1305 | return 0; | |
1306 | } | |
1307 | ||
1308 | /* Get the mask of available antennas. */ | |
1309 | if (dev->phy.gmode) | |
1310 | antenna_mask = dev->dev->bus->sprom.ant_available_bg; | |
1311 | else | |
1312 | antenna_mask = dev->dev->bus->sprom.ant_available_a; | |
1313 | ||
1314 | if (!(antenna_mask & (1 << (antenna_nr - 1)))) { | |
1315 | /* This antenna is not available. Fall back to default. */ | |
1316 | return 0; | |
1317 | } | |
1318 | ||
1319 | return antenna_nr; | |
1320 | } | |
1321 | ||
1322 | static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna) | |
1323 | { | |
1324 | antenna = b43_ieee80211_antenna_sanitize(dev, antenna); | |
1325 | switch (antenna) { | |
1326 | case 0: /* default/diversity */ | |
1327 | return B43_ANTENNA_DEFAULT; | |
1328 | case 1: /* Antenna 0 */ | |
1329 | return B43_ANTENNA0; | |
1330 | case 2: /* Antenna 1 */ | |
1331 | return B43_ANTENNA1; | |
1332 | case 3: /* Antenna 2 */ | |
1333 | return B43_ANTENNA2; | |
1334 | case 4: /* Antenna 3 */ | |
1335 | return B43_ANTENNA3; | |
1336 | default: | |
1337 | return B43_ANTENNA_DEFAULT; | |
1338 | } | |
1339 | } | |
1340 | ||
1341 | /* Convert a b43 antenna number value to the PHY TX control value. */ | |
1342 | static u16 b43_antenna_to_phyctl(int antenna) | |
1343 | { | |
1344 | switch (antenna) { | |
1345 | case B43_ANTENNA0: | |
1346 | return B43_TXH_PHY_ANT0; | |
1347 | case B43_ANTENNA1: | |
1348 | return B43_TXH_PHY_ANT1; | |
1349 | case B43_ANTENNA2: | |
1350 | return B43_TXH_PHY_ANT2; | |
1351 | case B43_ANTENNA3: | |
1352 | return B43_TXH_PHY_ANT3; | |
1353 | case B43_ANTENNA_AUTO: | |
1354 | return B43_TXH_PHY_ANT01AUTO; | |
1355 | } | |
1356 | B43_WARN_ON(1); | |
1357 | return 0; | |
1358 | } | |
1359 | ||
e4d6b795 MB |
1360 | static void b43_write_beacon_template(struct b43_wldev *dev, |
1361 | u16 ram_offset, | |
5042c507 | 1362 | u16 shm_size_offset) |
e4d6b795 | 1363 | { |
47f76ca3 | 1364 | unsigned int i, len, variable_len; |
e66fee6a MB |
1365 | const struct ieee80211_mgmt *bcn; |
1366 | const u8 *ie; | |
1367 | bool tim_found = 0; | |
5042c507 MB |
1368 | unsigned int rate; |
1369 | u16 ctl; | |
1370 | int antenna; | |
e4d6b795 | 1371 | |
e66fee6a MB |
1372 | bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data); |
1373 | len = min((size_t) dev->wl->current_beacon->len, | |
e4d6b795 | 1374 | 0x200 - sizeof(struct b43_plcp_hdr6)); |
5042c507 | 1375 | rate = dev->wl->beacon_txctl.tx_rate->hw_value; |
e66fee6a MB |
1376 | |
1377 | b43_write_template_common(dev, (const u8 *)bcn, | |
e4d6b795 | 1378 | len, ram_offset, shm_size_offset, rate); |
e66fee6a | 1379 | |
5042c507 MB |
1380 | /* Write the PHY TX control parameters. */ |
1381 | antenna = b43_antenna_from_ieee80211(dev, | |
1382 | dev->wl->beacon_txctl.antenna_sel_tx); | |
1383 | antenna = b43_antenna_to_phyctl(antenna); | |
1384 | ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL); | |
1385 | /* We can't send beacons with short preamble. Would get PHY errors. */ | |
1386 | ctl &= ~B43_TXH_PHY_SHORTPRMBL; | |
1387 | ctl &= ~B43_TXH_PHY_ANT; | |
1388 | ctl &= ~B43_TXH_PHY_ENC; | |
1389 | ctl |= antenna; | |
1390 | if (b43_is_cck_rate(rate)) | |
1391 | ctl |= B43_TXH_PHY_ENC_CCK; | |
1392 | else | |
1393 | ctl |= B43_TXH_PHY_ENC_OFDM; | |
1394 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); | |
1395 | ||
e66fee6a MB |
1396 | /* Find the position of the TIM and the DTIM_period value |
1397 | * and write them to SHM. */ | |
1398 | ie = bcn->u.beacon.variable; | |
47f76ca3 MB |
1399 | variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable); |
1400 | for (i = 0; i < variable_len - 2; ) { | |
e66fee6a MB |
1401 | uint8_t ie_id, ie_len; |
1402 | ||
1403 | ie_id = ie[i]; | |
1404 | ie_len = ie[i + 1]; | |
1405 | if (ie_id == 5) { | |
1406 | u16 tim_position; | |
1407 | u16 dtim_period; | |
1408 | /* This is the TIM Information Element */ | |
1409 | ||
1410 | /* Check whether the ie_len is in the beacon data range. */ | |
47f76ca3 | 1411 | if (variable_len < ie_len + 2 + i) |
e66fee6a MB |
1412 | break; |
1413 | /* A valid TIM is at least 4 bytes long. */ | |
1414 | if (ie_len < 4) | |
1415 | break; | |
1416 | tim_found = 1; | |
1417 | ||
1418 | tim_position = sizeof(struct b43_plcp_hdr6); | |
1419 | tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable); | |
1420 | tim_position += i; | |
1421 | ||
1422 | dtim_period = ie[i + 3]; | |
1423 | ||
1424 | b43_shm_write16(dev, B43_SHM_SHARED, | |
1425 | B43_SHM_SH_TIMBPOS, tim_position); | |
1426 | b43_shm_write16(dev, B43_SHM_SHARED, | |
1427 | B43_SHM_SH_DTIMPER, dtim_period); | |
1428 | break; | |
1429 | } | |
1430 | i += ie_len + 2; | |
1431 | } | |
1432 | if (!tim_found) { | |
1433 | b43warn(dev->wl, "Did not find a valid TIM IE in " | |
1434 | "the beacon template packet. AP or IBSS operation " | |
1435 | "may be broken.\n"); | |
a82d9922 MB |
1436 | } else |
1437 | b43dbg(dev->wl, "Updated beacon template\n"); | |
e4d6b795 MB |
1438 | } |
1439 | ||
1440 | static void b43_write_probe_resp_plcp(struct b43_wldev *dev, | |
8318d78a JB |
1441 | u16 shm_offset, u16 size, |
1442 | struct ieee80211_rate *rate) | |
e4d6b795 MB |
1443 | { |
1444 | struct b43_plcp_hdr4 plcp; | |
1445 | u32 tmp; | |
1446 | __le16 dur; | |
1447 | ||
1448 | plcp.data = 0; | |
8318d78a | 1449 | b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value); |
e4d6b795 | 1450 | dur = ieee80211_generic_frame_duration(dev->wl->hw, |
32bfd35d | 1451 | dev->wl->vif, size, |
8318d78a | 1452 | rate); |
e4d6b795 MB |
1453 | /* Write PLCP in two parts and timing for packet transfer */ |
1454 | tmp = le32_to_cpu(plcp.data); | |
1455 | b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF); | |
1456 | b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16); | |
1457 | b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur)); | |
1458 | } | |
1459 | ||
1460 | /* Instead of using custom probe response template, this function | |
1461 | * just patches custom beacon template by: | |
1462 | * 1) Changing packet type | |
1463 | * 2) Patching duration field | |
1464 | * 3) Stripping TIM | |
1465 | */ | |
e66fee6a | 1466 | static const u8 * b43_generate_probe_resp(struct b43_wldev *dev, |
8318d78a JB |
1467 | u16 *dest_size, |
1468 | struct ieee80211_rate *rate) | |
e4d6b795 MB |
1469 | { |
1470 | const u8 *src_data; | |
1471 | u8 *dest_data; | |
1472 | u16 src_size, elem_size, src_pos, dest_pos; | |
1473 | __le16 dur; | |
1474 | struct ieee80211_hdr *hdr; | |
e66fee6a MB |
1475 | size_t ie_start; |
1476 | ||
1477 | src_size = dev->wl->current_beacon->len; | |
1478 | src_data = (const u8 *)dev->wl->current_beacon->data; | |
e4d6b795 | 1479 | |
e66fee6a MB |
1480 | /* Get the start offset of the variable IEs in the packet. */ |
1481 | ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable); | |
1482 | B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable)); | |
e4d6b795 | 1483 | |
e66fee6a | 1484 | if (B43_WARN_ON(src_size < ie_start)) |
e4d6b795 | 1485 | return NULL; |
e4d6b795 MB |
1486 | |
1487 | dest_data = kmalloc(src_size, GFP_ATOMIC); | |
1488 | if (unlikely(!dest_data)) | |
1489 | return NULL; | |
1490 | ||
e66fee6a MB |
1491 | /* Copy the static data and all Information Elements, except the TIM. */ |
1492 | memcpy(dest_data, src_data, ie_start); | |
1493 | src_pos = ie_start; | |
1494 | dest_pos = ie_start; | |
1495 | for ( ; src_pos < src_size - 2; src_pos += elem_size) { | |
e4d6b795 | 1496 | elem_size = src_data[src_pos + 1] + 2; |
e66fee6a MB |
1497 | if (src_data[src_pos] == 5) { |
1498 | /* This is the TIM. */ | |
1499 | continue; | |
e4d6b795 | 1500 | } |
e66fee6a MB |
1501 | memcpy(dest_data + dest_pos, src_data + src_pos, |
1502 | elem_size); | |
1503 | dest_pos += elem_size; | |
e4d6b795 MB |
1504 | } |
1505 | *dest_size = dest_pos; | |
1506 | hdr = (struct ieee80211_hdr *)dest_data; | |
1507 | ||
1508 | /* Set the frame control. */ | |
1509 | hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | | |
1510 | IEEE80211_STYPE_PROBE_RESP); | |
1511 | dur = ieee80211_generic_frame_duration(dev->wl->hw, | |
32bfd35d | 1512 | dev->wl->vif, *dest_size, |
8318d78a | 1513 | rate); |
e4d6b795 MB |
1514 | hdr->duration_id = dur; |
1515 | ||
1516 | return dest_data; | |
1517 | } | |
1518 | ||
1519 | static void b43_write_probe_resp_template(struct b43_wldev *dev, | |
1520 | u16 ram_offset, | |
8318d78a JB |
1521 | u16 shm_size_offset, |
1522 | struct ieee80211_rate *rate) | |
e4d6b795 | 1523 | { |
e66fee6a | 1524 | const u8 *probe_resp_data; |
e4d6b795 MB |
1525 | u16 size; |
1526 | ||
e66fee6a | 1527 | size = dev->wl->current_beacon->len; |
e4d6b795 MB |
1528 | probe_resp_data = b43_generate_probe_resp(dev, &size, rate); |
1529 | if (unlikely(!probe_resp_data)) | |
1530 | return; | |
1531 | ||
1532 | /* Looks like PLCP headers plus packet timings are stored for | |
1533 | * all possible basic rates | |
1534 | */ | |
8318d78a JB |
1535 | b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]); |
1536 | b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]); | |
1537 | b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]); | |
1538 | b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]); | |
e4d6b795 MB |
1539 | |
1540 | size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6)); | |
1541 | b43_write_template_common(dev, probe_resp_data, | |
8318d78a JB |
1542 | size, ram_offset, shm_size_offset, |
1543 | rate->hw_value); | |
e4d6b795 MB |
1544 | kfree(probe_resp_data); |
1545 | } | |
1546 | ||
6b4bec01 MB |
1547 | static void b43_upload_beacon0(struct b43_wldev *dev) |
1548 | { | |
1549 | struct b43_wl *wl = dev->wl; | |
1550 | ||
1551 | if (wl->beacon0_uploaded) | |
1552 | return; | |
1553 | b43_write_beacon_template(dev, 0x68, 0x18); | |
1554 | /* FIXME: Probe resp upload doesn't really belong here, | |
1555 | * but we don't use that feature anyway. */ | |
1556 | b43_write_probe_resp_template(dev, 0x268, 0x4A, | |
1557 | &__b43_ratetable[3]); | |
1558 | wl->beacon0_uploaded = 1; | |
1559 | } | |
1560 | ||
1561 | static void b43_upload_beacon1(struct b43_wldev *dev) | |
1562 | { | |
1563 | struct b43_wl *wl = dev->wl; | |
1564 | ||
1565 | if (wl->beacon1_uploaded) | |
1566 | return; | |
1567 | b43_write_beacon_template(dev, 0x468, 0x1A); | |
1568 | wl->beacon1_uploaded = 1; | |
1569 | } | |
1570 | ||
c97a4ccc MB |
1571 | static void handle_irq_beacon(struct b43_wldev *dev) |
1572 | { | |
1573 | struct b43_wl *wl = dev->wl; | |
1574 | u32 cmd, beacon0_valid, beacon1_valid; | |
1575 | ||
1576 | if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) | |
1577 | return; | |
1578 | ||
1579 | /* This is the bottom half of the asynchronous beacon update. */ | |
1580 | ||
1581 | /* Ignore interrupt in the future. */ | |
1582 | dev->irq_savedstate &= ~B43_IRQ_BEACON; | |
1583 | ||
1584 | cmd = b43_read32(dev, B43_MMIO_MACCMD); | |
1585 | beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID); | |
1586 | beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID); | |
1587 | ||
1588 | /* Schedule interrupt manually, if busy. */ | |
1589 | if (beacon0_valid && beacon1_valid) { | |
1590 | b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON); | |
1591 | dev->irq_savedstate |= B43_IRQ_BEACON; | |
1592 | return; | |
1593 | } | |
1594 | ||
6b4bec01 MB |
1595 | if (unlikely(wl->beacon_templates_virgin)) { |
1596 | /* We never uploaded a beacon before. | |
1597 | * Upload both templates now, but only mark one valid. */ | |
1598 | wl->beacon_templates_virgin = 0; | |
1599 | b43_upload_beacon0(dev); | |
1600 | b43_upload_beacon1(dev); | |
c97a4ccc MB |
1601 | cmd = b43_read32(dev, B43_MMIO_MACCMD); |
1602 | cmd |= B43_MACCMD_BEACON0_VALID; | |
1603 | b43_write32(dev, B43_MMIO_MACCMD, cmd); | |
6b4bec01 MB |
1604 | } else { |
1605 | if (!beacon0_valid) { | |
1606 | b43_upload_beacon0(dev); | |
1607 | cmd = b43_read32(dev, B43_MMIO_MACCMD); | |
1608 | cmd |= B43_MACCMD_BEACON0_VALID; | |
1609 | b43_write32(dev, B43_MMIO_MACCMD, cmd); | |
1610 | } else if (!beacon1_valid) { | |
1611 | b43_upload_beacon1(dev); | |
1612 | cmd = b43_read32(dev, B43_MMIO_MACCMD); | |
1613 | cmd |= B43_MACCMD_BEACON1_VALID; | |
1614 | b43_write32(dev, B43_MMIO_MACCMD, cmd); | |
c97a4ccc | 1615 | } |
c97a4ccc MB |
1616 | } |
1617 | } | |
1618 | ||
a82d9922 MB |
1619 | static void b43_beacon_update_trigger_work(struct work_struct *work) |
1620 | { | |
1621 | struct b43_wl *wl = container_of(work, struct b43_wl, | |
1622 | beacon_update_trigger); | |
1623 | struct b43_wldev *dev; | |
1624 | ||
1625 | mutex_lock(&wl->mutex); | |
1626 | dev = wl->current_dev; | |
1627 | if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) { | |
a82d9922 | 1628 | spin_lock_irq(&wl->irq_lock); |
c97a4ccc MB |
1629 | /* update beacon right away or defer to irq */ |
1630 | dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); | |
1631 | handle_irq_beacon(dev); | |
1632 | /* The handler might have updated the IRQ mask. */ | |
1633 | b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, | |
1634 | dev->irq_savedstate); | |
1635 | mmiowb(); | |
a82d9922 MB |
1636 | spin_unlock_irq(&wl->irq_lock); |
1637 | } | |
1638 | mutex_unlock(&wl->mutex); | |
1639 | } | |
1640 | ||
d4df6f1a MB |
1641 | /* Asynchronously update the packet templates in template RAM. |
1642 | * Locking: Requires wl->irq_lock to be locked. */ | |
5042c507 MB |
1643 | static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon, |
1644 | const struct ieee80211_tx_control *txctl) | |
e4d6b795 | 1645 | { |
e66fee6a MB |
1646 | /* This is the top half of the ansynchronous beacon update. |
1647 | * The bottom half is the beacon IRQ. | |
1648 | * Beacon update must be asynchronous to avoid sending an | |
1649 | * invalid beacon. This can happen for example, if the firmware | |
1650 | * transmits a beacon while we are updating it. */ | |
e4d6b795 | 1651 | |
e66fee6a MB |
1652 | if (wl->current_beacon) |
1653 | dev_kfree_skb_any(wl->current_beacon); | |
1654 | wl->current_beacon = beacon; | |
5042c507 | 1655 | memcpy(&wl->beacon_txctl, txctl, sizeof(wl->beacon_txctl)); |
e66fee6a MB |
1656 | wl->beacon0_uploaded = 0; |
1657 | wl->beacon1_uploaded = 0; | |
a82d9922 | 1658 | queue_work(wl->hw->workqueue, &wl->beacon_update_trigger); |
e4d6b795 MB |
1659 | } |
1660 | ||
1661 | static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len) | |
1662 | { | |
1663 | u32 tmp; | |
1664 | u16 i, len; | |
1665 | ||
1666 | len = min((u16) ssid_len, (u16) 0x100); | |
1667 | for (i = 0; i < len; i += sizeof(u32)) { | |
1668 | tmp = (u32) (ssid[i + 0]); | |
1669 | if (i + 1 < len) | |
1670 | tmp |= (u32) (ssid[i + 1]) << 8; | |
1671 | if (i + 2 < len) | |
1672 | tmp |= (u32) (ssid[i + 2]) << 16; | |
1673 | if (i + 3 < len) | |
1674 | tmp |= (u32) (ssid[i + 3]) << 24; | |
1675 | b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp); | |
1676 | } | |
1677 | b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len); | |
1678 | } | |
1679 | ||
1680 | static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int) | |
1681 | { | |
1682 | b43_time_lock(dev); | |
1683 | if (dev->dev->id.revision >= 3) { | |
a82d9922 MB |
1684 | b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16)); |
1685 | b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10)); | |
e4d6b795 MB |
1686 | } else { |
1687 | b43_write16(dev, 0x606, (beacon_int >> 6)); | |
1688 | b43_write16(dev, 0x610, beacon_int); | |
1689 | } | |
1690 | b43_time_unlock(dev); | |
a82d9922 | 1691 | b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int); |
e4d6b795 MB |
1692 | } |
1693 | ||
e4d6b795 MB |
1694 | static void handle_irq_ucode_debug(struct b43_wldev *dev) |
1695 | { | |
1696 | //TODO | |
1697 | } | |
1698 | ||
1699 | /* Interrupt handler bottom-half */ | |
1700 | static void b43_interrupt_tasklet(struct b43_wldev *dev) | |
1701 | { | |
1702 | u32 reason; | |
1703 | u32 dma_reason[ARRAY_SIZE(dev->dma_reason)]; | |
1704 | u32 merged_dma_reason = 0; | |
21954c36 | 1705 | int i; |
e4d6b795 MB |
1706 | unsigned long flags; |
1707 | ||
1708 | spin_lock_irqsave(&dev->wl->irq_lock, flags); | |
1709 | ||
1710 | B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED); | |
1711 | ||
1712 | reason = dev->irq_reason; | |
1713 | for (i = 0; i < ARRAY_SIZE(dma_reason); i++) { | |
1714 | dma_reason[i] = dev->dma_reason[i]; | |
1715 | merged_dma_reason |= dma_reason[i]; | |
1716 | } | |
1717 | ||
1718 | if (unlikely(reason & B43_IRQ_MAC_TXERR)) | |
1719 | b43err(dev->wl, "MAC transmission error\n"); | |
1720 | ||
00e0b8cb | 1721 | if (unlikely(reason & B43_IRQ_PHY_TXERR)) { |
e4d6b795 | 1722 | b43err(dev->wl, "PHY transmission error\n"); |
00e0b8cb SB |
1723 | rmb(); |
1724 | if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) { | |
1725 | atomic_set(&dev->phy.txerr_cnt, | |
1726 | B43_PHY_TX_BADNESS_LIMIT); | |
1727 | b43err(dev->wl, "Too many PHY TX errors, " | |
1728 | "restarting the controller\n"); | |
1729 | b43_controller_restart(dev, "PHY TX errors"); | |
1730 | } | |
1731 | } | |
e4d6b795 MB |
1732 | |
1733 | if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK | | |
1734 | B43_DMAIRQ_NONFATALMASK))) { | |
1735 | if (merged_dma_reason & B43_DMAIRQ_FATALMASK) { | |
1736 | b43err(dev->wl, "Fatal DMA error: " | |
1737 | "0x%08X, 0x%08X, 0x%08X, " | |
1738 | "0x%08X, 0x%08X, 0x%08X\n", | |
1739 | dma_reason[0], dma_reason[1], | |
1740 | dma_reason[2], dma_reason[3], | |
1741 | dma_reason[4], dma_reason[5]); | |
1742 | b43_controller_restart(dev, "DMA error"); | |
1743 | mmiowb(); | |
1744 | spin_unlock_irqrestore(&dev->wl->irq_lock, flags); | |
1745 | return; | |
1746 | } | |
1747 | if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) { | |
1748 | b43err(dev->wl, "DMA error: " | |
1749 | "0x%08X, 0x%08X, 0x%08X, " | |
1750 | "0x%08X, 0x%08X, 0x%08X\n", | |
1751 | dma_reason[0], dma_reason[1], | |
1752 | dma_reason[2], dma_reason[3], | |
1753 | dma_reason[4], dma_reason[5]); | |
1754 | } | |
1755 | } | |
1756 | ||
1757 | if (unlikely(reason & B43_IRQ_UCODE_DEBUG)) | |
1758 | handle_irq_ucode_debug(dev); | |
1759 | if (reason & B43_IRQ_TBTT_INDI) | |
1760 | handle_irq_tbtt_indication(dev); | |
1761 | if (reason & B43_IRQ_ATIM_END) | |
1762 | handle_irq_atim_end(dev); | |
1763 | if (reason & B43_IRQ_BEACON) | |
1764 | handle_irq_beacon(dev); | |
1765 | if (reason & B43_IRQ_PMQ) | |
1766 | handle_irq_pmq(dev); | |
21954c36 MB |
1767 | if (reason & B43_IRQ_TXFIFO_FLUSH_OK) |
1768 | ;/* TODO */ | |
1769 | if (reason & B43_IRQ_NOISESAMPLE_OK) | |
e4d6b795 MB |
1770 | handle_irq_noise(dev); |
1771 | ||
1772 | /* Check the DMA reason registers for received data. */ | |
5100d5ac MB |
1773 | if (dma_reason[0] & B43_DMAIRQ_RX_DONE) { |
1774 | if (b43_using_pio_transfers(dev)) | |
1775 | b43_pio_rx(dev->pio.rx_queue); | |
1776 | else | |
1777 | b43_dma_rx(dev->dma.rx_ring); | |
1778 | } | |
e4d6b795 MB |
1779 | B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE); |
1780 | B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE); | |
b27faf8e | 1781 | B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE); |
e4d6b795 MB |
1782 | B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE); |
1783 | B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE); | |
1784 | ||
21954c36 | 1785 | if (reason & B43_IRQ_TX_OK) |
e4d6b795 | 1786 | handle_irq_transmit_status(dev); |
e4d6b795 | 1787 | |
e4d6b795 MB |
1788 | b43_interrupt_enable(dev, dev->irq_savedstate); |
1789 | mmiowb(); | |
1790 | spin_unlock_irqrestore(&dev->wl->irq_lock, flags); | |
1791 | } | |
1792 | ||
e4d6b795 MB |
1793 | static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason) |
1794 | { | |
e4d6b795 MB |
1795 | b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason); |
1796 | ||
1797 | b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]); | |
1798 | b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]); | |
1799 | b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]); | |
1800 | b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]); | |
1801 | b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]); | |
1802 | b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]); | |
1803 | } | |
1804 | ||
1805 | /* Interrupt handler top-half */ | |
1806 | static irqreturn_t b43_interrupt_handler(int irq, void *dev_id) | |
1807 | { | |
1808 | irqreturn_t ret = IRQ_NONE; | |
1809 | struct b43_wldev *dev = dev_id; | |
1810 | u32 reason; | |
1811 | ||
1812 | if (!dev) | |
1813 | return IRQ_NONE; | |
1814 | ||
1815 | spin_lock(&dev->wl->irq_lock); | |
1816 | ||
1817 | if (b43_status(dev) < B43_STAT_STARTED) | |
1818 | goto out; | |
1819 | reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); | |
1820 | if (reason == 0xffffffff) /* shared IRQ */ | |
1821 | goto out; | |
1822 | ret = IRQ_HANDLED; | |
1823 | reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); | |
1824 | if (!reason) | |
1825 | goto out; | |
1826 | ||
1827 | dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON) | |
1828 | & 0x0001DC00; | |
1829 | dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON) | |
1830 | & 0x0000DC00; | |
1831 | dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON) | |
1832 | & 0x0000DC00; | |
1833 | dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON) | |
1834 | & 0x0001DC00; | |
1835 | dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON) | |
1836 | & 0x0000DC00; | |
1837 | dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON) | |
1838 | & 0x0000DC00; | |
1839 | ||
1840 | b43_interrupt_ack(dev, reason); | |
1841 | /* disable all IRQs. They are enabled again in the bottom half. */ | |
1842 | dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL); | |
1843 | /* save the reason code and call our bottom half. */ | |
1844 | dev->irq_reason = reason; | |
1845 | tasklet_schedule(&dev->isr_tasklet); | |
1846 | out: | |
1847 | mmiowb(); | |
1848 | spin_unlock(&dev->wl->irq_lock); | |
1849 | ||
1850 | return ret; | |
1851 | } | |
1852 | ||
61cb5dd6 MB |
1853 | static void do_release_fw(struct b43_firmware_file *fw) |
1854 | { | |
1855 | release_firmware(fw->data); | |
1856 | fw->data = NULL; | |
1857 | fw->filename = NULL; | |
1858 | } | |
1859 | ||
e4d6b795 MB |
1860 | static void b43_release_firmware(struct b43_wldev *dev) |
1861 | { | |
61cb5dd6 MB |
1862 | do_release_fw(&dev->fw.ucode); |
1863 | do_release_fw(&dev->fw.pcm); | |
1864 | do_release_fw(&dev->fw.initvals); | |
1865 | do_release_fw(&dev->fw.initvals_band); | |
e4d6b795 MB |
1866 | } |
1867 | ||
eb189d8b | 1868 | static void b43_print_fw_helptext(struct b43_wl *wl, bool error) |
e4d6b795 | 1869 | { |
eb189d8b MB |
1870 | const char *text; |
1871 | ||
1872 | text = "You must go to " | |
354807e0 | 1873 | "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware " |
eb189d8b MB |
1874 | "and download the latest firmware (version 4).\n"; |
1875 | if (error) | |
1876 | b43err(wl, text); | |
1877 | else | |
1878 | b43warn(wl, text); | |
e4d6b795 MB |
1879 | } |
1880 | ||
1881 | static int do_request_fw(struct b43_wldev *dev, | |
1882 | const char *name, | |
61cb5dd6 | 1883 | struct b43_firmware_file *fw) |
e4d6b795 | 1884 | { |
1a09404a | 1885 | char path[sizeof(modparam_fwpostfix) + 32]; |
61cb5dd6 | 1886 | const struct firmware *blob; |
e4d6b795 MB |
1887 | struct b43_fw_header *hdr; |
1888 | u32 size; | |
1889 | int err; | |
1890 | ||
61cb5dd6 MB |
1891 | if (!name) { |
1892 | /* Don't fetch anything. Free possibly cached firmware. */ | |
1893 | do_release_fw(fw); | |
e4d6b795 | 1894 | return 0; |
61cb5dd6 MB |
1895 | } |
1896 | if (fw->filename) { | |
1897 | if (strcmp(fw->filename, name) == 0) | |
1898 | return 0; /* Already have this fw. */ | |
1899 | /* Free the cached firmware first. */ | |
1900 | do_release_fw(fw); | |
1901 | } | |
e4d6b795 MB |
1902 | |
1903 | snprintf(path, ARRAY_SIZE(path), | |
1904 | "b43%s/%s.fw", | |
1905 | modparam_fwpostfix, name); | |
61cb5dd6 | 1906 | err = request_firmware(&blob, path, dev->dev->dev); |
e4d6b795 MB |
1907 | if (err) { |
1908 | b43err(dev->wl, "Firmware file \"%s\" not found " | |
1909 | "or load failed.\n", path); | |
1910 | return err; | |
1911 | } | |
61cb5dd6 | 1912 | if (blob->size < sizeof(struct b43_fw_header)) |
e4d6b795 | 1913 | goto err_format; |
61cb5dd6 | 1914 | hdr = (struct b43_fw_header *)(blob->data); |
e4d6b795 MB |
1915 | switch (hdr->type) { |
1916 | case B43_FW_TYPE_UCODE: | |
1917 | case B43_FW_TYPE_PCM: | |
1918 | size = be32_to_cpu(hdr->size); | |
61cb5dd6 | 1919 | if (size != blob->size - sizeof(struct b43_fw_header)) |
e4d6b795 MB |
1920 | goto err_format; |
1921 | /* fallthrough */ | |
1922 | case B43_FW_TYPE_IV: | |
1923 | if (hdr->ver != 1) | |
1924 | goto err_format; | |
1925 | break; | |
1926 | default: | |
1927 | goto err_format; | |
1928 | } | |
1929 | ||
61cb5dd6 MB |
1930 | fw->data = blob; |
1931 | fw->filename = name; | |
1932 | ||
1933 | return 0; | |
e4d6b795 MB |
1934 | |
1935 | err_format: | |
1936 | b43err(dev->wl, "Firmware file \"%s\" format error.\n", path); | |
61cb5dd6 MB |
1937 | release_firmware(blob); |
1938 | ||
e4d6b795 MB |
1939 | return -EPROTO; |
1940 | } | |
1941 | ||
1942 | static int b43_request_firmware(struct b43_wldev *dev) | |
1943 | { | |
1944 | struct b43_firmware *fw = &dev->fw; | |
1945 | const u8 rev = dev->dev->id.revision; | |
1946 | const char *filename; | |
1947 | u32 tmshigh; | |
1948 | int err; | |
1949 | ||
61cb5dd6 | 1950 | /* Get microcode */ |
e4d6b795 | 1951 | tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); |
61cb5dd6 MB |
1952 | if ((rev >= 5) && (rev <= 10)) |
1953 | filename = "ucode5"; | |
1954 | else if ((rev >= 11) && (rev <= 12)) | |
1955 | filename = "ucode11"; | |
1956 | else if (rev >= 13) | |
1957 | filename = "ucode13"; | |
1958 | else | |
1959 | goto err_no_ucode; | |
1960 | err = do_request_fw(dev, filename, &fw->ucode); | |
1961 | if (err) | |
1962 | goto err_load; | |
1963 | ||
1964 | /* Get PCM code */ | |
1965 | if ((rev >= 5) && (rev <= 10)) | |
1966 | filename = "pcm5"; | |
1967 | else if (rev >= 11) | |
1968 | filename = NULL; | |
1969 | else | |
1970 | goto err_no_pcm; | |
1971 | err = do_request_fw(dev, filename, &fw->pcm); | |
1972 | if (err) | |
1973 | goto err_load; | |
1974 | ||
1975 | /* Get initvals */ | |
1976 | switch (dev->phy.type) { | |
1977 | case B43_PHYTYPE_A: | |
1978 | if ((rev >= 5) && (rev <= 10)) { | |
1979 | if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) | |
1980 | filename = "a0g1initvals5"; | |
1981 | else | |
1982 | filename = "a0g0initvals5"; | |
1983 | } else | |
1984 | goto err_no_initvals; | |
1985 | break; | |
1986 | case B43_PHYTYPE_G: | |
e4d6b795 | 1987 | if ((rev >= 5) && (rev <= 10)) |
61cb5dd6 | 1988 | filename = "b0g0initvals5"; |
e4d6b795 | 1989 | else if (rev >= 13) |
61cb5dd6 | 1990 | filename = "lp0initvals13"; |
e4d6b795 | 1991 | else |
61cb5dd6 MB |
1992 | goto err_no_initvals; |
1993 | break; | |
1994 | case B43_PHYTYPE_N: | |
1995 | if ((rev >= 11) && (rev <= 12)) | |
1996 | filename = "n0initvals11"; | |
1997 | else | |
1998 | goto err_no_initvals; | |
1999 | break; | |
2000 | default: | |
2001 | goto err_no_initvals; | |
e4d6b795 | 2002 | } |
61cb5dd6 MB |
2003 | err = do_request_fw(dev, filename, &fw->initvals); |
2004 | if (err) | |
2005 | goto err_load; | |
2006 | ||
2007 | /* Get bandswitch initvals */ | |
2008 | switch (dev->phy.type) { | |
2009 | case B43_PHYTYPE_A: | |
2010 | if ((rev >= 5) && (rev <= 10)) { | |
2011 | if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY) | |
2012 | filename = "a0g1bsinitvals5"; | |
2013 | else | |
2014 | filename = "a0g0bsinitvals5"; | |
2015 | } else if (rev >= 11) | |
2016 | filename = NULL; | |
2017 | else | |
2018 | goto err_no_initvals; | |
2019 | break; | |
2020 | case B43_PHYTYPE_G: | |
e4d6b795 | 2021 | if ((rev >= 5) && (rev <= 10)) |
61cb5dd6 | 2022 | filename = "b0g0bsinitvals5"; |
e4d6b795 MB |
2023 | else if (rev >= 11) |
2024 | filename = NULL; | |
2025 | else | |
e4d6b795 | 2026 | goto err_no_initvals; |
61cb5dd6 MB |
2027 | break; |
2028 | case B43_PHYTYPE_N: | |
2029 | if ((rev >= 11) && (rev <= 12)) | |
2030 | filename = "n0bsinitvals11"; | |
2031 | else | |
e4d6b795 | 2032 | goto err_no_initvals; |
61cb5dd6 MB |
2033 | break; |
2034 | default: | |
2035 | goto err_no_initvals; | |
e4d6b795 | 2036 | } |
61cb5dd6 MB |
2037 | err = do_request_fw(dev, filename, &fw->initvals_band); |
2038 | if (err) | |
2039 | goto err_load; | |
e4d6b795 MB |
2040 | |
2041 | return 0; | |
2042 | ||
2043 | err_load: | |
eb189d8b | 2044 | b43_print_fw_helptext(dev->wl, 1); |
e4d6b795 MB |
2045 | goto error; |
2046 | ||
2047 | err_no_ucode: | |
2048 | err = -ENODEV; | |
2049 | b43err(dev->wl, "No microcode available for core rev %u\n", rev); | |
2050 | goto error; | |
2051 | ||
2052 | err_no_pcm: | |
2053 | err = -ENODEV; | |
2054 | b43err(dev->wl, "No PCM available for core rev %u\n", rev); | |
2055 | goto error; | |
2056 | ||
2057 | err_no_initvals: | |
2058 | err = -ENODEV; | |
2059 | b43err(dev->wl, "No Initial Values firmware file for PHY %u, " | |
2060 | "core rev %u\n", dev->phy.type, rev); | |
2061 | goto error; | |
2062 | ||
2063 | error: | |
2064 | b43_release_firmware(dev); | |
2065 | return err; | |
2066 | } | |
2067 | ||
2068 | static int b43_upload_microcode(struct b43_wldev *dev) | |
2069 | { | |
2070 | const size_t hdr_len = sizeof(struct b43_fw_header); | |
2071 | const __be32 *data; | |
2072 | unsigned int i, len; | |
2073 | u16 fwrev, fwpatch, fwdate, fwtime; | |
1f7d87b0 | 2074 | u32 tmp, macctl; |
e4d6b795 MB |
2075 | int err = 0; |
2076 | ||
1f7d87b0 MB |
2077 | /* Jump the microcode PSM to offset 0 */ |
2078 | macctl = b43_read32(dev, B43_MMIO_MACCTL); | |
2079 | B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN); | |
2080 | macctl |= B43_MACCTL_PSM_JMP0; | |
2081 | b43_write32(dev, B43_MMIO_MACCTL, macctl); | |
2082 | /* Zero out all microcode PSM registers and shared memory. */ | |
2083 | for (i = 0; i < 64; i++) | |
2084 | b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0); | |
2085 | for (i = 0; i < 4096; i += 2) | |
2086 | b43_shm_write16(dev, B43_SHM_SHARED, i, 0); | |
2087 | ||
e4d6b795 | 2088 | /* Upload Microcode. */ |
61cb5dd6 MB |
2089 | data = (__be32 *) (dev->fw.ucode.data->data + hdr_len); |
2090 | len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32); | |
e4d6b795 MB |
2091 | b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000); |
2092 | for (i = 0; i < len; i++) { | |
2093 | b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); | |
2094 | udelay(10); | |
2095 | } | |
2096 | ||
61cb5dd6 | 2097 | if (dev->fw.pcm.data) { |
e4d6b795 | 2098 | /* Upload PCM data. */ |
61cb5dd6 MB |
2099 | data = (__be32 *) (dev->fw.pcm.data->data + hdr_len); |
2100 | len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32); | |
e4d6b795 MB |
2101 | b43_shm_control_word(dev, B43_SHM_HW, 0x01EA); |
2102 | b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000); | |
2103 | /* No need for autoinc bit in SHM_HW */ | |
2104 | b43_shm_control_word(dev, B43_SHM_HW, 0x01EB); | |
2105 | for (i = 0; i < len; i++) { | |
2106 | b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i])); | |
2107 | udelay(10); | |
2108 | } | |
2109 | } | |
2110 | ||
2111 | b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL); | |
1f7d87b0 MB |
2112 | |
2113 | /* Start the microcode PSM */ | |
2114 | macctl = b43_read32(dev, B43_MMIO_MACCTL); | |
2115 | macctl &= ~B43_MACCTL_PSM_JMP0; | |
2116 | macctl |= B43_MACCTL_PSM_RUN; | |
2117 | b43_write32(dev, B43_MMIO_MACCTL, macctl); | |
e4d6b795 MB |
2118 | |
2119 | /* Wait for the microcode to load and respond */ | |
2120 | i = 0; | |
2121 | while (1) { | |
2122 | tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); | |
2123 | if (tmp == B43_IRQ_MAC_SUSPENDED) | |
2124 | break; | |
2125 | i++; | |
1f7d87b0 | 2126 | if (i >= 20) { |
e4d6b795 | 2127 | b43err(dev->wl, "Microcode not responding\n"); |
eb189d8b | 2128 | b43_print_fw_helptext(dev->wl, 1); |
e4d6b795 | 2129 | err = -ENODEV; |
1f7d87b0 MB |
2130 | goto error; |
2131 | } | |
2132 | msleep_interruptible(50); | |
2133 | if (signal_pending(current)) { | |
2134 | err = -EINTR; | |
2135 | goto error; | |
e4d6b795 | 2136 | } |
e4d6b795 MB |
2137 | } |
2138 | b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */ | |
2139 | ||
2140 | /* Get and check the revisions. */ | |
2141 | fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV); | |
2142 | fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH); | |
2143 | fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE); | |
2144 | fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME); | |
2145 | ||
2146 | if (fwrev <= 0x128) { | |
2147 | b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from " | |
2148 | "binary drivers older than version 4.x is unsupported. " | |
2149 | "You must upgrade your firmware files.\n"); | |
eb189d8b | 2150 | b43_print_fw_helptext(dev->wl, 1); |
e4d6b795 | 2151 | err = -EOPNOTSUPP; |
1f7d87b0 | 2152 | goto error; |
e4d6b795 | 2153 | } |
588e6cdf MB |
2154 | b43info(dev->wl, "Loading firmware version %u.%u " |
2155 | "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", | |
2156 | fwrev, fwpatch, | |
2157 | (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF, | |
2158 | (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F); | |
e4d6b795 MB |
2159 | |
2160 | dev->fw.rev = fwrev; | |
2161 | dev->fw.patch = fwpatch; | |
2162 | ||
eb189d8b MB |
2163 | if (b43_is_old_txhdr_format(dev)) { |
2164 | b43warn(dev->wl, "You are using an old firmware image. " | |
2165 | "Support for old firmware will be removed in July 2008.\n"); | |
2166 | b43_print_fw_helptext(dev->wl, 0); | |
2167 | } | |
2168 | ||
1f7d87b0 MB |
2169 | return 0; |
2170 | ||
2171 | error: | |
2172 | macctl = b43_read32(dev, B43_MMIO_MACCTL); | |
2173 | macctl &= ~B43_MACCTL_PSM_RUN; | |
2174 | macctl |= B43_MACCTL_PSM_JMP0; | |
2175 | b43_write32(dev, B43_MMIO_MACCTL, macctl); | |
2176 | ||
e4d6b795 MB |
2177 | return err; |
2178 | } | |
2179 | ||
2180 | static int b43_write_initvals(struct b43_wldev *dev, | |
2181 | const struct b43_iv *ivals, | |
2182 | size_t count, | |
2183 | size_t array_size) | |
2184 | { | |
2185 | const struct b43_iv *iv; | |
2186 | u16 offset; | |
2187 | size_t i; | |
2188 | bool bit32; | |
2189 | ||
2190 | BUILD_BUG_ON(sizeof(struct b43_iv) != 6); | |
2191 | iv = ivals; | |
2192 | for (i = 0; i < count; i++) { | |
2193 | if (array_size < sizeof(iv->offset_size)) | |
2194 | goto err_format; | |
2195 | array_size -= sizeof(iv->offset_size); | |
2196 | offset = be16_to_cpu(iv->offset_size); | |
2197 | bit32 = !!(offset & B43_IV_32BIT); | |
2198 | offset &= B43_IV_OFFSET_MASK; | |
2199 | if (offset >= 0x1000) | |
2200 | goto err_format; | |
2201 | if (bit32) { | |
2202 | u32 value; | |
2203 | ||
2204 | if (array_size < sizeof(iv->data.d32)) | |
2205 | goto err_format; | |
2206 | array_size -= sizeof(iv->data.d32); | |
2207 | ||
533dd1b0 | 2208 | value = get_unaligned_be32(&iv->data.d32); |
e4d6b795 MB |
2209 | b43_write32(dev, offset, value); |
2210 | ||
2211 | iv = (const struct b43_iv *)((const uint8_t *)iv + | |
2212 | sizeof(__be16) + | |
2213 | sizeof(__be32)); | |
2214 | } else { | |
2215 | u16 value; | |
2216 | ||
2217 | if (array_size < sizeof(iv->data.d16)) | |
2218 | goto err_format; | |
2219 | array_size -= sizeof(iv->data.d16); | |
2220 | ||
2221 | value = be16_to_cpu(iv->data.d16); | |
2222 | b43_write16(dev, offset, value); | |
2223 | ||
2224 | iv = (const struct b43_iv *)((const uint8_t *)iv + | |
2225 | sizeof(__be16) + | |
2226 | sizeof(__be16)); | |
2227 | } | |
2228 | } | |
2229 | if (array_size) | |
2230 | goto err_format; | |
2231 | ||
2232 | return 0; | |
2233 | ||
2234 | err_format: | |
2235 | b43err(dev->wl, "Initial Values Firmware file-format error.\n"); | |
eb189d8b | 2236 | b43_print_fw_helptext(dev->wl, 1); |
e4d6b795 MB |
2237 | |
2238 | return -EPROTO; | |
2239 | } | |
2240 | ||
2241 | static int b43_upload_initvals(struct b43_wldev *dev) | |
2242 | { | |
2243 | const size_t hdr_len = sizeof(struct b43_fw_header); | |
2244 | const struct b43_fw_header *hdr; | |
2245 | struct b43_firmware *fw = &dev->fw; | |
2246 | const struct b43_iv *ivals; | |
2247 | size_t count; | |
2248 | int err; | |
2249 | ||
61cb5dd6 MB |
2250 | hdr = (const struct b43_fw_header *)(fw->initvals.data->data); |
2251 | ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len); | |
e4d6b795 MB |
2252 | count = be32_to_cpu(hdr->size); |
2253 | err = b43_write_initvals(dev, ivals, count, | |
61cb5dd6 | 2254 | fw->initvals.data->size - hdr_len); |
e4d6b795 MB |
2255 | if (err) |
2256 | goto out; | |
61cb5dd6 MB |
2257 | if (fw->initvals_band.data) { |
2258 | hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data); | |
2259 | ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len); | |
e4d6b795 MB |
2260 | count = be32_to_cpu(hdr->size); |
2261 | err = b43_write_initvals(dev, ivals, count, | |
61cb5dd6 | 2262 | fw->initvals_band.data->size - hdr_len); |
e4d6b795 MB |
2263 | if (err) |
2264 | goto out; | |
2265 | } | |
2266 | out: | |
2267 | ||
2268 | return err; | |
2269 | } | |
2270 | ||
2271 | /* Initialize the GPIOs | |
2272 | * http://bcm-specs.sipsolutions.net/GPIO | |
2273 | */ | |
2274 | static int b43_gpio_init(struct b43_wldev *dev) | |
2275 | { | |
2276 | struct ssb_bus *bus = dev->dev->bus; | |
2277 | struct ssb_device *gpiodev, *pcidev = NULL; | |
2278 | u32 mask, set; | |
2279 | ||
2280 | b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) | |
2281 | & ~B43_MACCTL_GPOUTSMSK); | |
2282 | ||
e4d6b795 MB |
2283 | b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK) |
2284 | | 0x000F); | |
2285 | ||
2286 | mask = 0x0000001F; | |
2287 | set = 0x0000000F; | |
2288 | if (dev->dev->bus->chip_id == 0x4301) { | |
2289 | mask |= 0x0060; | |
2290 | set |= 0x0060; | |
2291 | } | |
2292 | if (0 /* FIXME: conditional unknown */ ) { | |
2293 | b43_write16(dev, B43_MMIO_GPIO_MASK, | |
2294 | b43_read16(dev, B43_MMIO_GPIO_MASK) | |
2295 | | 0x0100); | |
2296 | mask |= 0x0180; | |
2297 | set |= 0x0180; | |
2298 | } | |
95de2841 | 2299 | if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) { |
e4d6b795 MB |
2300 | b43_write16(dev, B43_MMIO_GPIO_MASK, |
2301 | b43_read16(dev, B43_MMIO_GPIO_MASK) | |
2302 | | 0x0200); | |
2303 | mask |= 0x0200; | |
2304 | set |= 0x0200; | |
2305 | } | |
2306 | if (dev->dev->id.revision >= 2) | |
2307 | mask |= 0x0010; /* FIXME: This is redundant. */ | |
2308 | ||
2309 | #ifdef CONFIG_SSB_DRIVER_PCICORE | |
2310 | pcidev = bus->pcicore.dev; | |
2311 | #endif | |
2312 | gpiodev = bus->chipco.dev ? : pcidev; | |
2313 | if (!gpiodev) | |
2314 | return 0; | |
2315 | ssb_write32(gpiodev, B43_GPIO_CONTROL, | |
2316 | (ssb_read32(gpiodev, B43_GPIO_CONTROL) | |
2317 | & mask) | set); | |
2318 | ||
2319 | return 0; | |
2320 | } | |
2321 | ||
2322 | /* Turn off all GPIO stuff. Call this on module unload, for example. */ | |
2323 | static void b43_gpio_cleanup(struct b43_wldev *dev) | |
2324 | { | |
2325 | struct ssb_bus *bus = dev->dev->bus; | |
2326 | struct ssb_device *gpiodev, *pcidev = NULL; | |
2327 | ||
2328 | #ifdef CONFIG_SSB_DRIVER_PCICORE | |
2329 | pcidev = bus->pcicore.dev; | |
2330 | #endif | |
2331 | gpiodev = bus->chipco.dev ? : pcidev; | |
2332 | if (!gpiodev) | |
2333 | return; | |
2334 | ssb_write32(gpiodev, B43_GPIO_CONTROL, 0); | |
2335 | } | |
2336 | ||
2337 | /* http://bcm-specs.sipsolutions.net/EnableMac */ | |
affe0a02 | 2338 | static void b43_mac_enable(struct b43_wldev *dev) |
e4d6b795 MB |
2339 | { |
2340 | dev->mac_suspended--; | |
2341 | B43_WARN_ON(dev->mac_suspended < 0); | |
2342 | if (dev->mac_suspended == 0) { | |
2343 | b43_write32(dev, B43_MMIO_MACCTL, | |
2344 | b43_read32(dev, B43_MMIO_MACCTL) | |
2345 | | B43_MACCTL_ENABLED); | |
2346 | b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, | |
2347 | B43_IRQ_MAC_SUSPENDED); | |
2348 | /* Commit writes */ | |
2349 | b43_read32(dev, B43_MMIO_MACCTL); | |
2350 | b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); | |
2351 | b43_power_saving_ctl_bits(dev, 0); | |
05b64b36 MB |
2352 | |
2353 | /* Re-enable IRQs. */ | |
2354 | spin_lock_irq(&dev->wl->irq_lock); | |
2355 | b43_interrupt_enable(dev, dev->irq_savedstate); | |
2356 | spin_unlock_irq(&dev->wl->irq_lock); | |
e4d6b795 MB |
2357 | } |
2358 | } | |
2359 | ||
2360 | /* http://bcm-specs.sipsolutions.net/SuspendMAC */ | |
affe0a02 | 2361 | static void b43_mac_suspend(struct b43_wldev *dev) |
e4d6b795 MB |
2362 | { |
2363 | int i; | |
2364 | u32 tmp; | |
2365 | ||
05b64b36 | 2366 | might_sleep(); |
e4d6b795 | 2367 | B43_WARN_ON(dev->mac_suspended < 0); |
05b64b36 | 2368 | |
e4d6b795 | 2369 | if (dev->mac_suspended == 0) { |
05b64b36 MB |
2370 | /* Mask IRQs before suspending MAC. Otherwise |
2371 | * the MAC stays busy and won't suspend. */ | |
2372 | spin_lock_irq(&dev->wl->irq_lock); | |
2373 | tmp = b43_interrupt_disable(dev, B43_IRQ_ALL); | |
2374 | spin_unlock_irq(&dev->wl->irq_lock); | |
2375 | b43_synchronize_irq(dev); | |
2376 | dev->irq_savedstate = tmp; | |
2377 | ||
e4d6b795 MB |
2378 | b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); |
2379 | b43_write32(dev, B43_MMIO_MACCTL, | |
2380 | b43_read32(dev, B43_MMIO_MACCTL) | |
2381 | & ~B43_MACCTL_ENABLED); | |
2382 | /* force pci to flush the write */ | |
2383 | b43_read32(dev, B43_MMIO_MACCTL); | |
ba380013 MB |
2384 | for (i = 35; i; i--) { |
2385 | tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); | |
2386 | if (tmp & B43_IRQ_MAC_SUSPENDED) | |
2387 | goto out; | |
2388 | udelay(10); | |
2389 | } | |
2390 | /* Hm, it seems this will take some time. Use msleep(). */ | |
05b64b36 | 2391 | for (i = 40; i; i--) { |
e4d6b795 MB |
2392 | tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); |
2393 | if (tmp & B43_IRQ_MAC_SUSPENDED) | |
2394 | goto out; | |
05b64b36 | 2395 | msleep(1); |
e4d6b795 MB |
2396 | } |
2397 | b43err(dev->wl, "MAC suspend failed\n"); | |
2398 | } | |
05b64b36 | 2399 | out: |
e4d6b795 MB |
2400 | dev->mac_suspended++; |
2401 | } | |
2402 | ||
2403 | static void b43_adjust_opmode(struct b43_wldev *dev) | |
2404 | { | |
2405 | struct b43_wl *wl = dev->wl; | |
2406 | u32 ctl; | |
2407 | u16 cfp_pretbtt; | |
2408 | ||
2409 | ctl = b43_read32(dev, B43_MMIO_MACCTL); | |
2410 | /* Reset status to STA infrastructure mode. */ | |
2411 | ctl &= ~B43_MACCTL_AP; | |
2412 | ctl &= ~B43_MACCTL_KEEP_CTL; | |
2413 | ctl &= ~B43_MACCTL_KEEP_BADPLCP; | |
2414 | ctl &= ~B43_MACCTL_KEEP_BAD; | |
2415 | ctl &= ~B43_MACCTL_PROMISC; | |
4150c572 | 2416 | ctl &= ~B43_MACCTL_BEACPROMISC; |
e4d6b795 MB |
2417 | ctl |= B43_MACCTL_INFRA; |
2418 | ||
4150c572 JB |
2419 | if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) |
2420 | ctl |= B43_MACCTL_AP; | |
2421 | else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS)) | |
2422 | ctl &= ~B43_MACCTL_INFRA; | |
2423 | ||
2424 | if (wl->filter_flags & FIF_CONTROL) | |
e4d6b795 | 2425 | ctl |= B43_MACCTL_KEEP_CTL; |
4150c572 JB |
2426 | if (wl->filter_flags & FIF_FCSFAIL) |
2427 | ctl |= B43_MACCTL_KEEP_BAD; | |
2428 | if (wl->filter_flags & FIF_PLCPFAIL) | |
2429 | ctl |= B43_MACCTL_KEEP_BADPLCP; | |
2430 | if (wl->filter_flags & FIF_PROMISC_IN_BSS) | |
e4d6b795 | 2431 | ctl |= B43_MACCTL_PROMISC; |
4150c572 JB |
2432 | if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC) |
2433 | ctl |= B43_MACCTL_BEACPROMISC; | |
2434 | ||
e4d6b795 MB |
2435 | /* Workaround: On old hardware the HW-MAC-address-filter |
2436 | * doesn't work properly, so always run promisc in filter | |
2437 | * it in software. */ | |
2438 | if (dev->dev->id.revision <= 4) | |
2439 | ctl |= B43_MACCTL_PROMISC; | |
2440 | ||
2441 | b43_write32(dev, B43_MMIO_MACCTL, ctl); | |
2442 | ||
2443 | cfp_pretbtt = 2; | |
2444 | if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) { | |
2445 | if (dev->dev->bus->chip_id == 0x4306 && | |
2446 | dev->dev->bus->chip_rev == 3) | |
2447 | cfp_pretbtt = 100; | |
2448 | else | |
2449 | cfp_pretbtt = 50; | |
2450 | } | |
2451 | b43_write16(dev, 0x612, cfp_pretbtt); | |
2452 | } | |
2453 | ||
2454 | static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm) | |
2455 | { | |
2456 | u16 offset; | |
2457 | ||
2458 | if (is_ofdm) { | |
2459 | offset = 0x480; | |
2460 | offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2; | |
2461 | } else { | |
2462 | offset = 0x4C0; | |
2463 | offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2; | |
2464 | } | |
2465 | b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20, | |
2466 | b43_shm_read16(dev, B43_SHM_SHARED, offset)); | |
2467 | } | |
2468 | ||
2469 | static void b43_rate_memory_init(struct b43_wldev *dev) | |
2470 | { | |
2471 | switch (dev->phy.type) { | |
2472 | case B43_PHYTYPE_A: | |
2473 | case B43_PHYTYPE_G: | |
53a6e234 | 2474 | case B43_PHYTYPE_N: |
e4d6b795 MB |
2475 | b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1); |
2476 | b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1); | |
2477 | b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1); | |
2478 | b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1); | |
2479 | b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1); | |
2480 | b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1); | |
2481 | b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1); | |
2482 | if (dev->phy.type == B43_PHYTYPE_A) | |
2483 | break; | |
2484 | /* fallthrough */ | |
2485 | case B43_PHYTYPE_B: | |
2486 | b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0); | |
2487 | b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0); | |
2488 | b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0); | |
2489 | b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0); | |
2490 | break; | |
2491 | default: | |
2492 | B43_WARN_ON(1); | |
2493 | } | |
2494 | } | |
2495 | ||
5042c507 MB |
2496 | /* Set the default values for the PHY TX Control Words. */ |
2497 | static void b43_set_phytxctl_defaults(struct b43_wldev *dev) | |
2498 | { | |
2499 | u16 ctl = 0; | |
2500 | ||
2501 | ctl |= B43_TXH_PHY_ENC_CCK; | |
2502 | ctl |= B43_TXH_PHY_ANT01AUTO; | |
2503 | ctl |= B43_TXH_PHY_TXPWR; | |
2504 | ||
2505 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl); | |
2506 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl); | |
2507 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl); | |
2508 | } | |
2509 | ||
e4d6b795 MB |
2510 | /* Set the TX-Antenna for management frames sent by firmware. */ |
2511 | static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna) | |
2512 | { | |
5042c507 | 2513 | u16 ant; |
e4d6b795 MB |
2514 | u16 tmp; |
2515 | ||
5042c507 | 2516 | ant = b43_antenna_to_phyctl(antenna); |
e4d6b795 | 2517 | |
e4d6b795 MB |
2518 | /* For ACK/CTS */ |
2519 | tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL); | |
eb189d8b | 2520 | tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; |
e4d6b795 MB |
2521 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp); |
2522 | /* For Probe Resposes */ | |
2523 | tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL); | |
eb189d8b | 2524 | tmp = (tmp & ~B43_TXH_PHY_ANT) | ant; |
e4d6b795 MB |
2525 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp); |
2526 | } | |
2527 | ||
2528 | /* This is the opposite of b43_chip_init() */ | |
2529 | static void b43_chip_exit(struct b43_wldev *dev) | |
2530 | { | |
8e9f7529 | 2531 | b43_radio_turn_off(dev, 1); |
e4d6b795 MB |
2532 | b43_gpio_cleanup(dev); |
2533 | /* firmware is released later */ | |
2534 | } | |
2535 | ||
2536 | /* Initialize the chip | |
2537 | * http://bcm-specs.sipsolutions.net/ChipInit | |
2538 | */ | |
2539 | static int b43_chip_init(struct b43_wldev *dev) | |
2540 | { | |
2541 | struct b43_phy *phy = &dev->phy; | |
2542 | int err, tmp; | |
1f7d87b0 | 2543 | u32 value32, macctl; |
e4d6b795 MB |
2544 | u16 value16; |
2545 | ||
1f7d87b0 MB |
2546 | /* Initialize the MAC control */ |
2547 | macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED; | |
2548 | if (dev->phy.gmode) | |
2549 | macctl |= B43_MACCTL_GMODE; | |
2550 | macctl |= B43_MACCTL_INFRA; | |
2551 | b43_write32(dev, B43_MMIO_MACCTL, macctl); | |
e4d6b795 MB |
2552 | |
2553 | err = b43_request_firmware(dev); | |
2554 | if (err) | |
2555 | goto out; | |
2556 | err = b43_upload_microcode(dev); | |
2557 | if (err) | |
2558 | goto out; /* firmware is released later */ | |
2559 | ||
2560 | err = b43_gpio_init(dev); | |
2561 | if (err) | |
2562 | goto out; /* firmware is released later */ | |
21954c36 | 2563 | |
e4d6b795 MB |
2564 | err = b43_upload_initvals(dev); |
2565 | if (err) | |
1a8d1227 | 2566 | goto err_gpio_clean; |
e4d6b795 | 2567 | b43_radio_turn_on(dev); |
e4d6b795 MB |
2568 | |
2569 | b43_write16(dev, 0x03E6, 0x0000); | |
2570 | err = b43_phy_init(dev); | |
2571 | if (err) | |
2572 | goto err_radio_off; | |
2573 | ||
2574 | /* Select initial Interference Mitigation. */ | |
2575 | tmp = phy->interfmode; | |
2576 | phy->interfmode = B43_INTERFMODE_NONE; | |
2577 | b43_radio_set_interference_mitigation(dev, tmp); | |
2578 | ||
2579 | b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT); | |
2580 | b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT); | |
2581 | ||
2582 | if (phy->type == B43_PHYTYPE_B) { | |
2583 | value16 = b43_read16(dev, 0x005E); | |
2584 | value16 |= 0x0004; | |
2585 | b43_write16(dev, 0x005E, value16); | |
2586 | } | |
2587 | b43_write32(dev, 0x0100, 0x01000000); | |
2588 | if (dev->dev->id.revision < 5) | |
2589 | b43_write32(dev, 0x010C, 0x01000000); | |
2590 | ||
2591 | b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) | |
2592 | & ~B43_MACCTL_INFRA); | |
2593 | b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL) | |
2594 | | B43_MACCTL_INFRA); | |
e4d6b795 | 2595 | |
e4d6b795 MB |
2596 | /* Probe Response Timeout value */ |
2597 | /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */ | |
2598 | b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000); | |
2599 | ||
2600 | /* Initially set the wireless operation mode. */ | |
2601 | b43_adjust_opmode(dev); | |
2602 | ||
2603 | if (dev->dev->id.revision < 3) { | |
2604 | b43_write16(dev, 0x060E, 0x0000); | |
2605 | b43_write16(dev, 0x0610, 0x8000); | |
2606 | b43_write16(dev, 0x0604, 0x0000); | |
2607 | b43_write16(dev, 0x0606, 0x0200); | |
2608 | } else { | |
2609 | b43_write32(dev, 0x0188, 0x80000000); | |
2610 | b43_write32(dev, 0x018C, 0x02000000); | |
2611 | } | |
2612 | b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000); | |
2613 | b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00); | |
2614 | b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00); | |
2615 | b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00); | |
2616 | b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00); | |
2617 | b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00); | |
2618 | b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00); | |
2619 | ||
2620 | value32 = ssb_read32(dev->dev, SSB_TMSLOW); | |
2621 | value32 |= 0x00100000; | |
2622 | ssb_write32(dev->dev, SSB_TMSLOW, value32); | |
2623 | ||
2624 | b43_write16(dev, B43_MMIO_POWERUP_DELAY, | |
2625 | dev->dev->bus->chipco.fast_pwrup_delay); | |
2626 | ||
2627 | err = 0; | |
2628 | b43dbg(dev->wl, "Chip initialized\n"); | |
21954c36 | 2629 | out: |
e4d6b795 MB |
2630 | return err; |
2631 | ||
21954c36 | 2632 | err_radio_off: |
8e9f7529 | 2633 | b43_radio_turn_off(dev, 1); |
1a8d1227 | 2634 | err_gpio_clean: |
e4d6b795 | 2635 | b43_gpio_cleanup(dev); |
21954c36 | 2636 | return err; |
e4d6b795 MB |
2637 | } |
2638 | ||
2639 | static void b43_periodic_every120sec(struct b43_wldev *dev) | |
2640 | { | |
2641 | struct b43_phy *phy = &dev->phy; | |
2642 | ||
2643 | if (phy->type != B43_PHYTYPE_G || phy->rev < 2) | |
2644 | return; | |
2645 | ||
2646 | b43_mac_suspend(dev); | |
2647 | b43_lo_g_measure(dev); | |
2648 | b43_mac_enable(dev); | |
2649 | if (b43_has_hardware_pctl(phy)) | |
2650 | b43_lo_g_ctl_mark_all_unused(dev); | |
2651 | } | |
2652 | ||
2653 | static void b43_periodic_every60sec(struct b43_wldev *dev) | |
2654 | { | |
2655 | struct b43_phy *phy = &dev->phy; | |
2656 | ||
53a6e234 MB |
2657 | if (phy->type != B43_PHYTYPE_G) |
2658 | return; | |
e4d6b795 MB |
2659 | if (!b43_has_hardware_pctl(phy)) |
2660 | b43_lo_g_ctl_mark_all_unused(dev); | |
95de2841 | 2661 | if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) { |
e4d6b795 MB |
2662 | b43_mac_suspend(dev); |
2663 | b43_calc_nrssi_slope(dev); | |
2664 | if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) { | |
2665 | u8 old_chan = phy->channel; | |
2666 | ||
2667 | /* VCO Calibration */ | |
2668 | if (old_chan >= 8) | |
2669 | b43_radio_selectchannel(dev, 1, 0); | |
2670 | else | |
2671 | b43_radio_selectchannel(dev, 13, 0); | |
2672 | b43_radio_selectchannel(dev, old_chan, 0); | |
2673 | } | |
2674 | b43_mac_enable(dev); | |
2675 | } | |
2676 | } | |
2677 | ||
2678 | static void b43_periodic_every30sec(struct b43_wldev *dev) | |
2679 | { | |
2680 | /* Update device statistics. */ | |
2681 | b43_calculate_link_quality(dev); | |
2682 | } | |
2683 | ||
2684 | static void b43_periodic_every15sec(struct b43_wldev *dev) | |
2685 | { | |
2686 | struct b43_phy *phy = &dev->phy; | |
2687 | ||
2688 | if (phy->type == B43_PHYTYPE_G) { | |
2689 | //TODO: update_aci_moving_average | |
2690 | if (phy->aci_enable && phy->aci_wlan_automatic) { | |
2691 | b43_mac_suspend(dev); | |
2692 | if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) { | |
2693 | if (0 /*TODO: bunch of conditions */ ) { | |
2694 | b43_radio_set_interference_mitigation | |
2695 | (dev, B43_INTERFMODE_MANUALWLAN); | |
2696 | } | |
2697 | } else if (1 /*TODO*/) { | |
2698 | /* | |
2699 | if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) { | |
2700 | b43_radio_set_interference_mitigation(dev, | |
2701 | B43_INTERFMODE_NONE); | |
2702 | } | |
2703 | */ | |
2704 | } | |
2705 | b43_mac_enable(dev); | |
2706 | } else if (phy->interfmode == B43_INTERFMODE_NONWLAN && | |
2707 | phy->rev == 1) { | |
2708 | //TODO: implement rev1 workaround | |
2709 | } | |
2710 | } | |
2711 | b43_phy_xmitpower(dev); //FIXME: unless scanning? | |
2712 | //TODO for APHY (temperature?) | |
00e0b8cb SB |
2713 | |
2714 | atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); | |
2715 | wmb(); | |
e4d6b795 MB |
2716 | } |
2717 | ||
e4d6b795 MB |
2718 | static void do_periodic_work(struct b43_wldev *dev) |
2719 | { | |
2720 | unsigned int state; | |
2721 | ||
2722 | state = dev->periodic_state; | |
42bb4cd5 | 2723 | if (state % 8 == 0) |
e4d6b795 | 2724 | b43_periodic_every120sec(dev); |
42bb4cd5 | 2725 | if (state % 4 == 0) |
e4d6b795 | 2726 | b43_periodic_every60sec(dev); |
42bb4cd5 | 2727 | if (state % 2 == 0) |
e4d6b795 | 2728 | b43_periodic_every30sec(dev); |
42bb4cd5 | 2729 | b43_periodic_every15sec(dev); |
e4d6b795 MB |
2730 | } |
2731 | ||
05b64b36 MB |
2732 | /* Periodic work locking policy: |
2733 | * The whole periodic work handler is protected by | |
2734 | * wl->mutex. If another lock is needed somewhere in the | |
2735 | * pwork callchain, it's aquired in-place, where it's needed. | |
e4d6b795 | 2736 | */ |
e4d6b795 MB |
2737 | static void b43_periodic_work_handler(struct work_struct *work) |
2738 | { | |
05b64b36 MB |
2739 | struct b43_wldev *dev = container_of(work, struct b43_wldev, |
2740 | periodic_work.work); | |
2741 | struct b43_wl *wl = dev->wl; | |
2742 | unsigned long delay; | |
e4d6b795 | 2743 | |
05b64b36 | 2744 | mutex_lock(&wl->mutex); |
e4d6b795 MB |
2745 | |
2746 | if (unlikely(b43_status(dev) != B43_STAT_STARTED)) | |
2747 | goto out; | |
2748 | if (b43_debug(dev, B43_DBG_PWORK_STOP)) | |
2749 | goto out_requeue; | |
2750 | ||
05b64b36 | 2751 | do_periodic_work(dev); |
e4d6b795 | 2752 | |
e4d6b795 | 2753 | dev->periodic_state++; |
42bb4cd5 | 2754 | out_requeue: |
e4d6b795 MB |
2755 | if (b43_debug(dev, B43_DBG_PWORK_FAST)) |
2756 | delay = msecs_to_jiffies(50); | |
2757 | else | |
82cd682d | 2758 | delay = round_jiffies_relative(HZ * 15); |
05b64b36 | 2759 | queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay); |
42bb4cd5 | 2760 | out: |
05b64b36 | 2761 | mutex_unlock(&wl->mutex); |
e4d6b795 MB |
2762 | } |
2763 | ||
2764 | static void b43_periodic_tasks_setup(struct b43_wldev *dev) | |
2765 | { | |
2766 | struct delayed_work *work = &dev->periodic_work; | |
2767 | ||
2768 | dev->periodic_state = 0; | |
2769 | INIT_DELAYED_WORK(work, b43_periodic_work_handler); | |
2770 | queue_delayed_work(dev->wl->hw->workqueue, work, 0); | |
2771 | } | |
2772 | ||
f3dd3fcc | 2773 | /* Check if communication with the device works correctly. */ |
e4d6b795 MB |
2774 | static int b43_validate_chipaccess(struct b43_wldev *dev) |
2775 | { | |
f3dd3fcc | 2776 | u32 v, backup; |
e4d6b795 | 2777 | |
f3dd3fcc MB |
2778 | backup = b43_shm_read32(dev, B43_SHM_SHARED, 0); |
2779 | ||
2780 | /* Check for read/write and endianness problems. */ | |
e4d6b795 MB |
2781 | b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55); |
2782 | if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55) | |
2783 | goto error; | |
f3dd3fcc MB |
2784 | b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA); |
2785 | if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA) | |
e4d6b795 MB |
2786 | goto error; |
2787 | ||
f3dd3fcc MB |
2788 | b43_shm_write32(dev, B43_SHM_SHARED, 0, backup); |
2789 | ||
2790 | if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) { | |
2791 | /* The 32bit register shadows the two 16bit registers | |
2792 | * with update sideeffects. Validate this. */ | |
2793 | b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA); | |
2794 | b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB); | |
2795 | if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB) | |
2796 | goto error; | |
2797 | if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC) | |
2798 | goto error; | |
2799 | } | |
2800 | b43_write32(dev, B43_MMIO_TSF_CFP_START, 0); | |
2801 | ||
2802 | v = b43_read32(dev, B43_MMIO_MACCTL); | |
2803 | v |= B43_MACCTL_GMODE; | |
2804 | if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED)) | |
e4d6b795 MB |
2805 | goto error; |
2806 | ||
2807 | return 0; | |
f3dd3fcc | 2808 | error: |
e4d6b795 MB |
2809 | b43err(dev->wl, "Failed to validate the chipaccess\n"); |
2810 | return -ENODEV; | |
2811 | } | |
2812 | ||
2813 | static void b43_security_init(struct b43_wldev *dev) | |
2814 | { | |
2815 | dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20; | |
2816 | B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key)); | |
2817 | dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP); | |
2818 | /* KTP is a word address, but we address SHM bytewise. | |
2819 | * So multiply by two. | |
2820 | */ | |
2821 | dev->ktp *= 2; | |
2822 | if (dev->dev->id.revision >= 5) { | |
2823 | /* Number of RCMTA address slots */ | |
2824 | b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8); | |
2825 | } | |
2826 | b43_clear_keys(dev); | |
2827 | } | |
2828 | ||
2829 | static int b43_rng_read(struct hwrng *rng, u32 * data) | |
2830 | { | |
2831 | struct b43_wl *wl = (struct b43_wl *)rng->priv; | |
2832 | unsigned long flags; | |
2833 | ||
2834 | /* Don't take wl->mutex here, as it could deadlock with | |
2835 | * hwrng internal locking. It's not needed to take | |
2836 | * wl->mutex here, anyway. */ | |
2837 | ||
2838 | spin_lock_irqsave(&wl->irq_lock, flags); | |
2839 | *data = b43_read16(wl->current_dev, B43_MMIO_RNG); | |
2840 | spin_unlock_irqrestore(&wl->irq_lock, flags); | |
2841 | ||
2842 | return (sizeof(u16)); | |
2843 | } | |
2844 | ||
b844eba2 | 2845 | static void b43_rng_exit(struct b43_wl *wl) |
e4d6b795 MB |
2846 | { |
2847 | if (wl->rng_initialized) | |
b844eba2 | 2848 | hwrng_unregister(&wl->rng); |
e4d6b795 MB |
2849 | } |
2850 | ||
2851 | static int b43_rng_init(struct b43_wl *wl) | |
2852 | { | |
2853 | int err; | |
2854 | ||
2855 | snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name), | |
2856 | "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy)); | |
2857 | wl->rng.name = wl->rng_name; | |
2858 | wl->rng.data_read = b43_rng_read; | |
2859 | wl->rng.priv = (unsigned long)wl; | |
2860 | wl->rng_initialized = 1; | |
2861 | err = hwrng_register(&wl->rng); | |
2862 | if (err) { | |
2863 | wl->rng_initialized = 0; | |
2864 | b43err(wl, "Failed to register the random " | |
2865 | "number generator (%d)\n", err); | |
2866 | } | |
2867 | ||
2868 | return err; | |
2869 | } | |
2870 | ||
40faacc4 MB |
2871 | static int b43_op_tx(struct ieee80211_hw *hw, |
2872 | struct sk_buff *skb, | |
2873 | struct ieee80211_tx_control *ctl) | |
e4d6b795 MB |
2874 | { |
2875 | struct b43_wl *wl = hw_to_b43_wl(hw); | |
2876 | struct b43_wldev *dev = wl->current_dev; | |
21a75d77 MB |
2877 | unsigned long flags; |
2878 | int err; | |
e4d6b795 | 2879 | |
5100d5ac MB |
2880 | if (unlikely(skb->len < 2 + 2 + 6)) { |
2881 | /* Too short, this can't be a valid frame. */ | |
21a75d77 MB |
2882 | dev_kfree_skb_any(skb); |
2883 | return NETDEV_TX_OK; | |
5100d5ac MB |
2884 | } |
2885 | B43_WARN_ON(skb_shinfo(skb)->nr_frags); | |
e4d6b795 | 2886 | if (unlikely(!dev)) |
21a75d77 MB |
2887 | return NETDEV_TX_BUSY; |
2888 | ||
2889 | /* Transmissions on seperate queues can run concurrently. */ | |
2890 | read_lock_irqsave(&wl->tx_lock, flags); | |
2891 | ||
2892 | err = -ENODEV; | |
2893 | if (likely(b43_status(dev) >= B43_STAT_STARTED)) { | |
2894 | if (b43_using_pio_transfers(dev)) | |
2895 | err = b43_pio_tx(dev, skb, ctl); | |
2896 | else | |
2897 | err = b43_dma_tx(dev, skb, ctl); | |
2898 | } | |
2899 | ||
2900 | read_unlock_irqrestore(&wl->tx_lock, flags); | |
2901 | ||
e4d6b795 MB |
2902 | if (unlikely(err)) |
2903 | return NETDEV_TX_BUSY; | |
2904 | return NETDEV_TX_OK; | |
2905 | } | |
2906 | ||
e6f5b934 MB |
2907 | /* Locking: wl->irq_lock */ |
2908 | static void b43_qos_params_upload(struct b43_wldev *dev, | |
2909 | const struct ieee80211_tx_queue_params *p, | |
2910 | u16 shm_offset) | |
2911 | { | |
2912 | u16 params[B43_NR_QOSPARAMS]; | |
2913 | int cw_min, cw_max, aifs, bslots, tmp; | |
2914 | unsigned int i; | |
2915 | ||
2916 | const u16 aCWmin = 0x0001; | |
2917 | const u16 aCWmax = 0x03FF; | |
2918 | ||
2919 | /* Calculate the default values for the parameters, if needed. */ | |
2920 | switch (shm_offset) { | |
2921 | case B43_QOS_VOICE: | |
2922 | aifs = (p->aifs == -1) ? 2 : p->aifs; | |
2923 | cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 4 - 1) : p->cw_min; | |
2924 | cw_max = (p->cw_max == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_max; | |
2925 | break; | |
2926 | case B43_QOS_VIDEO: | |
2927 | aifs = (p->aifs == -1) ? 2 : p->aifs; | |
2928 | cw_min = (p->cw_min == 0) ? ((aCWmin + 1) / 2 - 1) : p->cw_min; | |
2929 | cw_max = (p->cw_max == 0) ? aCWmin : p->cw_max; | |
2930 | break; | |
2931 | case B43_QOS_BESTEFFORT: | |
2932 | aifs = (p->aifs == -1) ? 3 : p->aifs; | |
2933 | cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min; | |
2934 | cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max; | |
2935 | break; | |
2936 | case B43_QOS_BACKGROUND: | |
2937 | aifs = (p->aifs == -1) ? 7 : p->aifs; | |
2938 | cw_min = (p->cw_min == 0) ? aCWmin : p->cw_min; | |
2939 | cw_max = (p->cw_max == 0) ? aCWmax : p->cw_max; | |
2940 | break; | |
2941 | default: | |
2942 | B43_WARN_ON(1); | |
2943 | return; | |
2944 | } | |
2945 | if (cw_min <= 0) | |
2946 | cw_min = aCWmin; | |
2947 | if (cw_max <= 0) | |
2948 | cw_max = aCWmin; | |
2949 | bslots = b43_read16(dev, B43_MMIO_RNG) % cw_min; | |
2950 | ||
2951 | memset(¶ms, 0, sizeof(params)); | |
2952 | ||
2953 | params[B43_QOSPARAM_TXOP] = p->txop * 32; | |
2954 | params[B43_QOSPARAM_CWMIN] = cw_min; | |
2955 | params[B43_QOSPARAM_CWMAX] = cw_max; | |
2956 | params[B43_QOSPARAM_CWCUR] = cw_min; | |
2957 | params[B43_QOSPARAM_AIFS] = aifs; | |
2958 | params[B43_QOSPARAM_BSLOTS] = bslots; | |
2959 | params[B43_QOSPARAM_REGGAP] = bslots + aifs; | |
2960 | ||
2961 | for (i = 0; i < ARRAY_SIZE(params); i++) { | |
2962 | if (i == B43_QOSPARAM_STATUS) { | |
2963 | tmp = b43_shm_read16(dev, B43_SHM_SHARED, | |
2964 | shm_offset + (i * 2)); | |
2965 | /* Mark the parameters as updated. */ | |
2966 | tmp |= 0x100; | |
2967 | b43_shm_write16(dev, B43_SHM_SHARED, | |
2968 | shm_offset + (i * 2), | |
2969 | tmp); | |
2970 | } else { | |
2971 | b43_shm_write16(dev, B43_SHM_SHARED, | |
2972 | shm_offset + (i * 2), | |
2973 | params[i]); | |
2974 | } | |
2975 | } | |
2976 | } | |
2977 | ||
2978 | /* Update the QOS parameters in hardware. */ | |
2979 | static void b43_qos_update(struct b43_wldev *dev) | |
2980 | { | |
2981 | struct b43_wl *wl = dev->wl; | |
2982 | struct b43_qos_params *params; | |
2983 | unsigned long flags; | |
2984 | unsigned int i; | |
2985 | ||
2986 | /* Mapping of mac80211 queues to b43 SHM offsets. */ | |
2987 | static const u16 qos_shm_offsets[] = { | |
2988 | [0] = B43_QOS_VOICE, | |
2989 | [1] = B43_QOS_VIDEO, | |
2990 | [2] = B43_QOS_BESTEFFORT, | |
2991 | [3] = B43_QOS_BACKGROUND, | |
2992 | }; | |
2993 | BUILD_BUG_ON(ARRAY_SIZE(qos_shm_offsets) != ARRAY_SIZE(wl->qos_params)); | |
2994 | ||
2995 | b43_mac_suspend(dev); | |
2996 | spin_lock_irqsave(&wl->irq_lock, flags); | |
2997 | ||
2998 | for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { | |
2999 | params = &(wl->qos_params[i]); | |
3000 | if (params->need_hw_update) { | |
3001 | b43_qos_params_upload(dev, &(params->p), | |
3002 | qos_shm_offsets[i]); | |
3003 | params->need_hw_update = 0; | |
3004 | } | |
3005 | } | |
3006 | ||
3007 | spin_unlock_irqrestore(&wl->irq_lock, flags); | |
3008 | b43_mac_enable(dev); | |
3009 | } | |
3010 | ||
3011 | static void b43_qos_clear(struct b43_wl *wl) | |
3012 | { | |
3013 | struct b43_qos_params *params; | |
3014 | unsigned int i; | |
3015 | ||
3016 | for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) { | |
3017 | params = &(wl->qos_params[i]); | |
3018 | ||
3019 | memset(&(params->p), 0, sizeof(params->p)); | |
3020 | params->p.aifs = -1; | |
3021 | params->need_hw_update = 1; | |
3022 | } | |
3023 | } | |
3024 | ||
3025 | /* Initialize the core's QOS capabilities */ | |
3026 | static void b43_qos_init(struct b43_wldev *dev) | |
3027 | { | |
3028 | struct b43_wl *wl = dev->wl; | |
3029 | unsigned int i; | |
3030 | ||
3031 | /* Upload the current QOS parameters. */ | |
3032 | for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) | |
3033 | wl->qos_params[i].need_hw_update = 1; | |
3034 | b43_qos_update(dev); | |
3035 | ||
3036 | /* Enable QOS support. */ | |
3037 | b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF); | |
3038 | b43_write16(dev, B43_MMIO_IFSCTL, | |
3039 | b43_read16(dev, B43_MMIO_IFSCTL) | |
3040 | | B43_MMIO_IFSCTL_USE_EDCF); | |
3041 | } | |
3042 | ||
3043 | static void b43_qos_update_work(struct work_struct *work) | |
3044 | { | |
3045 | struct b43_wl *wl = container_of(work, struct b43_wl, qos_update_work); | |
3046 | struct b43_wldev *dev; | |
3047 | ||
3048 | mutex_lock(&wl->mutex); | |
3049 | dev = wl->current_dev; | |
3050 | if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) | |
3051 | b43_qos_update(dev); | |
3052 | mutex_unlock(&wl->mutex); | |
3053 | } | |
3054 | ||
40faacc4 | 3055 | static int b43_op_conf_tx(struct ieee80211_hw *hw, |
e6f5b934 | 3056 | int _queue, |
40faacc4 | 3057 | const struct ieee80211_tx_queue_params *params) |
e4d6b795 | 3058 | { |
e6f5b934 MB |
3059 | struct b43_wl *wl = hw_to_b43_wl(hw); |
3060 | unsigned long flags; | |
3061 | unsigned int queue = (unsigned int)_queue; | |
3062 | struct b43_qos_params *p; | |
3063 | ||
3064 | if (queue >= ARRAY_SIZE(wl->qos_params)) { | |
3065 | /* Queue not available or don't support setting | |
3066 | * params on this queue. Return success to not | |
3067 | * confuse mac80211. */ | |
3068 | return 0; | |
3069 | } | |
3070 | ||
3071 | spin_lock_irqsave(&wl->irq_lock, flags); | |
3072 | p = &(wl->qos_params[queue]); | |
3073 | memcpy(&(p->p), params, sizeof(p->p)); | |
3074 | p->need_hw_update = 1; | |
3075 | spin_unlock_irqrestore(&wl->irq_lock, flags); | |
3076 | ||
3077 | queue_work(hw->workqueue, &wl->qos_update_work); | |
3078 | ||
e4d6b795 MB |
3079 | return 0; |
3080 | } | |
3081 | ||
40faacc4 MB |
3082 | static int b43_op_get_tx_stats(struct ieee80211_hw *hw, |
3083 | struct ieee80211_tx_queue_stats *stats) | |
e4d6b795 MB |
3084 | { |
3085 | struct b43_wl *wl = hw_to_b43_wl(hw); | |
3086 | struct b43_wldev *dev = wl->current_dev; | |
3087 | unsigned long flags; | |
3088 | int err = -ENODEV; | |
3089 | ||
3090 | if (!dev) | |
3091 | goto out; | |
3092 | spin_lock_irqsave(&wl->irq_lock, flags); | |
3093 | if (likely(b43_status(dev) >= B43_STAT_STARTED)) { | |
5100d5ac MB |
3094 | if (b43_using_pio_transfers(dev)) |
3095 | b43_pio_get_tx_stats(dev, stats); | |
3096 | else | |
3097 | b43_dma_get_tx_stats(dev, stats); | |
e4d6b795 MB |
3098 | err = 0; |
3099 | } | |
3100 | spin_unlock_irqrestore(&wl->irq_lock, flags); | |
40faacc4 | 3101 | out: |
e4d6b795 MB |
3102 | return err; |
3103 | } | |
3104 | ||
40faacc4 MB |
3105 | static int b43_op_get_stats(struct ieee80211_hw *hw, |
3106 | struct ieee80211_low_level_stats *stats) | |
e4d6b795 MB |
3107 | { |
3108 | struct b43_wl *wl = hw_to_b43_wl(hw); | |
3109 | unsigned long flags; | |
3110 | ||
3111 | spin_lock_irqsave(&wl->irq_lock, flags); | |
3112 | memcpy(stats, &wl->ieee_stats, sizeof(*stats)); | |
3113 | spin_unlock_irqrestore(&wl->irq_lock, flags); | |
3114 | ||
3115 | return 0; | |
3116 | } | |
3117 | ||
e4d6b795 MB |
3118 | static void b43_put_phy_into_reset(struct b43_wldev *dev) |
3119 | { | |
3120 | struct ssb_device *sdev = dev->dev; | |
3121 | u32 tmslow; | |
3122 | ||
3123 | tmslow = ssb_read32(sdev, SSB_TMSLOW); | |
3124 | tmslow &= ~B43_TMSLOW_GMODE; | |
3125 | tmslow |= B43_TMSLOW_PHYRESET; | |
3126 | tmslow |= SSB_TMSLOW_FGC; | |
3127 | ssb_write32(sdev, SSB_TMSLOW, tmslow); | |
3128 | msleep(1); | |
3129 | ||
3130 | tmslow = ssb_read32(sdev, SSB_TMSLOW); | |
3131 | tmslow &= ~SSB_TMSLOW_FGC; | |
3132 | tmslow |= B43_TMSLOW_PHYRESET; | |
3133 | ssb_write32(sdev, SSB_TMSLOW, tmslow); | |
3134 | msleep(1); | |
3135 | } | |
3136 | ||
bb1eeff1 MB |
3137 | static const char * band_to_string(enum ieee80211_band band) |
3138 | { | |
3139 | switch (band) { | |
3140 | case IEEE80211_BAND_5GHZ: | |
3141 | return "5"; | |
3142 | case IEEE80211_BAND_2GHZ: | |
3143 | return "2.4"; | |
3144 | default: | |
3145 | break; | |
3146 | } | |
3147 | B43_WARN_ON(1); | |
3148 | return ""; | |
3149 | } | |
3150 | ||
e4d6b795 | 3151 | /* Expects wl->mutex locked */ |
bb1eeff1 | 3152 | static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan) |
e4d6b795 | 3153 | { |
bb1eeff1 | 3154 | struct b43_wldev *up_dev = NULL; |
e4d6b795 | 3155 | struct b43_wldev *down_dev; |
bb1eeff1 | 3156 | struct b43_wldev *d; |
e4d6b795 | 3157 | int err; |
bb1eeff1 | 3158 | bool gmode; |
e4d6b795 MB |
3159 | int prev_status; |
3160 | ||
bb1eeff1 MB |
3161 | /* Find a device and PHY which supports the band. */ |
3162 | list_for_each_entry(d, &wl->devlist, list) { | |
3163 | switch (chan->band) { | |
3164 | case IEEE80211_BAND_5GHZ: | |
3165 | if (d->phy.supports_5ghz) { | |
3166 | up_dev = d; | |
3167 | gmode = 0; | |
3168 | } | |
3169 | break; | |
3170 | case IEEE80211_BAND_2GHZ: | |
3171 | if (d->phy.supports_2ghz) { | |
3172 | up_dev = d; | |
3173 | gmode = 1; | |
3174 | } | |
3175 | break; | |
3176 | default: | |
3177 | B43_WARN_ON(1); | |
3178 | return -EINVAL; | |
3179 | } | |
3180 | if (up_dev) | |
3181 | break; | |
3182 | } | |
3183 | if (!up_dev) { | |
3184 | b43err(wl, "Could not find a device for %s-GHz band operation\n", | |
3185 | band_to_string(chan->band)); | |
3186 | return -ENODEV; | |
e4d6b795 MB |
3187 | } |
3188 | if ((up_dev == wl->current_dev) && | |
3189 | (!!wl->current_dev->phy.gmode == !!gmode)) { | |
3190 | /* This device is already running. */ | |
3191 | return 0; | |
3192 | } | |
bb1eeff1 MB |
3193 | b43dbg(wl, "Switching to %s-GHz band\n", |
3194 | band_to_string(chan->band)); | |
e4d6b795 MB |
3195 | down_dev = wl->current_dev; |
3196 | ||
3197 | prev_status = b43_status(down_dev); | |
3198 | /* Shutdown the currently running core. */ | |
3199 | if (prev_status >= B43_STAT_STARTED) | |
3200 | b43_wireless_core_stop(down_dev); | |
3201 | if (prev_status >= B43_STAT_INITIALIZED) | |
3202 | b43_wireless_core_exit(down_dev); | |
3203 | ||
3204 | if (down_dev != up_dev) { | |
3205 | /* We switch to a different core, so we put PHY into | |
3206 | * RESET on the old core. */ | |
3207 | b43_put_phy_into_reset(down_dev); | |
3208 | } | |
3209 | ||
3210 | /* Now start the new core. */ | |
3211 | up_dev->phy.gmode = gmode; | |
3212 | if (prev_status >= B43_STAT_INITIALIZED) { | |
3213 | err = b43_wireless_core_init(up_dev); | |
3214 | if (err) { | |
3215 | b43err(wl, "Fatal: Could not initialize device for " | |
bb1eeff1 MB |
3216 | "selected %s-GHz band\n", |
3217 | band_to_string(chan->band)); | |
e4d6b795 MB |
3218 | goto init_failure; |
3219 | } | |
3220 | } | |
3221 | if (prev_status >= B43_STAT_STARTED) { | |
3222 | err = b43_wireless_core_start(up_dev); | |
3223 | if (err) { | |
3224 | b43err(wl, "Fatal: Coult not start device for " | |
bb1eeff1 MB |
3225 | "selected %s-GHz band\n", |
3226 | band_to_string(chan->band)); | |
e4d6b795 MB |
3227 | b43_wireless_core_exit(up_dev); |
3228 | goto init_failure; | |
3229 | } | |
3230 | } | |
3231 | B43_WARN_ON(b43_status(up_dev) != prev_status); | |
3232 | ||
3233 | wl->current_dev = up_dev; | |
3234 | ||
3235 | return 0; | |
bb1eeff1 | 3236 | init_failure: |
e4d6b795 MB |
3237 | /* Whoops, failed to init the new core. No core is operating now. */ |
3238 | wl->current_dev = NULL; | |
3239 | return err; | |
3240 | } | |
3241 | ||
40faacc4 | 3242 | static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf) |
e4d6b795 MB |
3243 | { |
3244 | struct b43_wl *wl = hw_to_b43_wl(hw); | |
3245 | struct b43_wldev *dev; | |
3246 | struct b43_phy *phy; | |
3247 | unsigned long flags; | |
9db1f6d7 | 3248 | int antenna; |
e4d6b795 MB |
3249 | int err = 0; |
3250 | u32 savedirqs; | |
3251 | ||
e4d6b795 MB |
3252 | mutex_lock(&wl->mutex); |
3253 | ||
bb1eeff1 MB |
3254 | /* Switch the band (if necessary). This might change the active core. */ |
3255 | err = b43_switch_band(wl, conf->channel); | |
e4d6b795 MB |
3256 | if (err) |
3257 | goto out_unlock_mutex; | |
3258 | dev = wl->current_dev; | |
3259 | phy = &dev->phy; | |
3260 | ||
3261 | /* Disable IRQs while reconfiguring the device. | |
3262 | * This makes it possible to drop the spinlock throughout | |
3263 | * the reconfiguration process. */ | |
3264 | spin_lock_irqsave(&wl->irq_lock, flags); | |
3265 | if (b43_status(dev) < B43_STAT_STARTED) { | |
3266 | spin_unlock_irqrestore(&wl->irq_lock, flags); | |
3267 | goto out_unlock_mutex; | |
3268 | } | |
3269 | savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL); | |
3270 | spin_unlock_irqrestore(&wl->irq_lock, flags); | |
3271 | b43_synchronize_irq(dev); | |
3272 | ||
3273 | /* Switch to the requested channel. | |
3274 | * The firmware takes care of races with the TX handler. */ | |
8318d78a JB |
3275 | if (conf->channel->hw_value != phy->channel) |
3276 | b43_radio_selectchannel(dev, conf->channel->hw_value, 0); | |
e4d6b795 MB |
3277 | |
3278 | /* Enable/Disable ShortSlot timing. */ | |
3279 | if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) != | |
3280 | dev->short_slot) { | |
3281 | B43_WARN_ON(phy->type != B43_PHYTYPE_G); | |
3282 | if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) | |
3283 | b43_short_slot_timing_enable(dev); | |
3284 | else | |
3285 | b43_short_slot_timing_disable(dev); | |
3286 | } | |
3287 | ||
d42ce84a JB |
3288 | dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP); |
3289 | ||
e4d6b795 MB |
3290 | /* Adjust the desired TX power level. */ |
3291 | if (conf->power_level != 0) { | |
3292 | if (conf->power_level != phy->power_level) { | |
3293 | phy->power_level = conf->power_level; | |
3294 | b43_phy_xmitpower(dev); | |
3295 | } | |
3296 | } | |
3297 | ||
3298 | /* Antennas for RX and management frame TX. */ | |
9db1f6d7 MB |
3299 | antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx); |
3300 | b43_mgmtframe_txantenna(dev, antenna); | |
3301 | antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx); | |
3302 | b43_set_rx_antenna(dev, antenna); | |
e4d6b795 MB |
3303 | |
3304 | /* Update templates for AP mode. */ | |
3305 | if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) | |
3306 | b43_set_beacon_int(dev, conf->beacon_int); | |
3307 | ||
fda9abcf MB |
3308 | if (!!conf->radio_enabled != phy->radio_on) { |
3309 | if (conf->radio_enabled) { | |
3310 | b43_radio_turn_on(dev); | |
3311 | b43info(dev->wl, "Radio turned on by software\n"); | |
3312 | if (!dev->radio_hw_enable) { | |
3313 | b43info(dev->wl, "The hardware RF-kill button " | |
3314 | "still turns the radio physically off. " | |
3315 | "Press the button to turn it on.\n"); | |
3316 | } | |
3317 | } else { | |
8e9f7529 | 3318 | b43_radio_turn_off(dev, 0); |
fda9abcf MB |
3319 | b43info(dev->wl, "Radio turned off by software\n"); |
3320 | } | |
3321 | } | |
3322 | ||
e4d6b795 MB |
3323 | spin_lock_irqsave(&wl->irq_lock, flags); |
3324 | b43_interrupt_enable(dev, savedirqs); | |
3325 | mmiowb(); | |
3326 | spin_unlock_irqrestore(&wl->irq_lock, flags); | |
3327 | out_unlock_mutex: | |
3328 | mutex_unlock(&wl->mutex); | |
3329 | ||
3330 | return err; | |
3331 | } | |
3332 | ||
40faacc4 | 3333 | static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
4150c572 JB |
3334 | const u8 *local_addr, const u8 *addr, |
3335 | struct ieee80211_key_conf *key) | |
e4d6b795 MB |
3336 | { |
3337 | struct b43_wl *wl = hw_to_b43_wl(hw); | |
c6dfc9a8 | 3338 | struct b43_wldev *dev; |
e4d6b795 MB |
3339 | unsigned long flags; |
3340 | u8 algorithm; | |
3341 | u8 index; | |
c6dfc9a8 | 3342 | int err; |
0795af57 | 3343 | DECLARE_MAC_BUF(mac); |
e4d6b795 MB |
3344 | |
3345 | if (modparam_nohwcrypt) | |
3346 | return -ENOSPC; /* User disabled HW-crypto */ | |
3347 | ||
c6dfc9a8 MB |
3348 | mutex_lock(&wl->mutex); |
3349 | spin_lock_irqsave(&wl->irq_lock, flags); | |
3350 | ||
3351 | dev = wl->current_dev; | |
3352 | err = -ENODEV; | |
3353 | if (!dev || b43_status(dev) < B43_STAT_INITIALIZED) | |
3354 | goto out_unlock; | |
3355 | ||
3356 | err = -EINVAL; | |
e4d6b795 | 3357 | switch (key->alg) { |
e4d6b795 MB |
3358 | case ALG_WEP: |
3359 | if (key->keylen == 5) | |
3360 | algorithm = B43_SEC_ALGO_WEP40; | |
3361 | else | |
3362 | algorithm = B43_SEC_ALGO_WEP104; | |
3363 | break; | |
3364 | case ALG_TKIP: | |
3365 | algorithm = B43_SEC_ALGO_TKIP; | |
3366 | break; | |
3367 | case ALG_CCMP: | |
3368 | algorithm = B43_SEC_ALGO_AES; | |
3369 | break; | |
3370 | default: | |
3371 | B43_WARN_ON(1); | |
c6dfc9a8 | 3372 | goto out_unlock; |
e4d6b795 | 3373 | } |
e4d6b795 MB |
3374 | index = (u8) (key->keyidx); |
3375 | if (index > 3) | |
e4d6b795 | 3376 | goto out_unlock; |
e4d6b795 MB |
3377 | |
3378 | switch (cmd) { | |
3379 | case SET_KEY: | |
3380 | if (algorithm == B43_SEC_ALGO_TKIP) { | |
3381 | /* FIXME: No TKIP hardware encryption for now. */ | |
3382 | err = -EOPNOTSUPP; | |
3383 | goto out_unlock; | |
3384 | } | |
3385 | ||
3386 | if (is_broadcast_ether_addr(addr)) { | |
3387 | /* addr is FF:FF:FF:FF:FF:FF for default keys */ | |
3388 | err = b43_key_write(dev, index, algorithm, | |
3389 | key->key, key->keylen, NULL, key); | |
3390 | } else { | |
3391 | /* | |
3392 | * either pairwise key or address is 00:00:00:00:00:00 | |
3393 | * for transmit-only keys | |
3394 | */ | |
3395 | err = b43_key_write(dev, -1, algorithm, | |
3396 | key->key, key->keylen, addr, key); | |
3397 | } | |
3398 | if (err) | |
3399 | goto out_unlock; | |
3400 | ||
3401 | if (algorithm == B43_SEC_ALGO_WEP40 || | |
3402 | algorithm == B43_SEC_ALGO_WEP104) { | |
3403 | b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS); | |
3404 | } else { | |
3405 | b43_hf_write(dev, | |
3406 | b43_hf_read(dev) & ~B43_HF_USEDEFKEYS); | |
3407 | } | |
3408 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
3409 | break; | |
3410 | case DISABLE_KEY: { | |
3411 | err = b43_key_clear(dev, key->hw_key_idx); | |
3412 | if (err) | |
3413 | goto out_unlock; | |
3414 | break; | |
3415 | } | |
3416 | default: | |
3417 | B43_WARN_ON(1); | |
3418 | } | |
3419 | out_unlock: | |
3420 | spin_unlock_irqrestore(&wl->irq_lock, flags); | |
3421 | mutex_unlock(&wl->mutex); | |
e4d6b795 MB |
3422 | if (!err) { |
3423 | b43dbg(wl, "%s hardware based encryption for keyidx: %d, " | |
0795af57 | 3424 | "mac: %s\n", |
e4d6b795 | 3425 | cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, |
0795af57 | 3426 | print_mac(mac, addr)); |
e4d6b795 MB |
3427 | } |
3428 | return err; | |
3429 | } | |
3430 | ||
40faacc4 MB |
3431 | static void b43_op_configure_filter(struct ieee80211_hw *hw, |
3432 | unsigned int changed, unsigned int *fflags, | |
3433 | int mc_count, struct dev_addr_list *mc_list) | |
e4d6b795 MB |
3434 | { |
3435 | struct b43_wl *wl = hw_to_b43_wl(hw); | |
3436 | struct b43_wldev *dev = wl->current_dev; | |
3437 | unsigned long flags; | |
3438 | ||
4150c572 JB |
3439 | if (!dev) { |
3440 | *fflags = 0; | |
e4d6b795 | 3441 | return; |
e4d6b795 | 3442 | } |
4150c572 JB |
3443 | |
3444 | spin_lock_irqsave(&wl->irq_lock, flags); | |
3445 | *fflags &= FIF_PROMISC_IN_BSS | | |
3446 | FIF_ALLMULTI | | |
3447 | FIF_FCSFAIL | | |
3448 | FIF_PLCPFAIL | | |
3449 | FIF_CONTROL | | |
3450 | FIF_OTHER_BSS | | |
3451 | FIF_BCN_PRBRESP_PROMISC; | |
3452 | ||
3453 | changed &= FIF_PROMISC_IN_BSS | | |
3454 | FIF_ALLMULTI | | |
3455 | FIF_FCSFAIL | | |
3456 | FIF_PLCPFAIL | | |
3457 | FIF_CONTROL | | |
3458 | FIF_OTHER_BSS | | |
3459 | FIF_BCN_PRBRESP_PROMISC; | |
3460 | ||
3461 | wl->filter_flags = *fflags; | |
3462 | ||
3463 | if (changed && b43_status(dev) >= B43_STAT_INITIALIZED) | |
3464 | b43_adjust_opmode(dev); | |
e4d6b795 MB |
3465 | spin_unlock_irqrestore(&wl->irq_lock, flags); |
3466 | } | |
3467 | ||
40faacc4 | 3468 | static int b43_op_config_interface(struct ieee80211_hw *hw, |
32bfd35d | 3469 | struct ieee80211_vif *vif, |
40faacc4 | 3470 | struct ieee80211_if_conf *conf) |
e4d6b795 MB |
3471 | { |
3472 | struct b43_wl *wl = hw_to_b43_wl(hw); | |
3473 | struct b43_wldev *dev = wl->current_dev; | |
3474 | unsigned long flags; | |
3475 | ||
3476 | if (!dev) | |
3477 | return -ENODEV; | |
3478 | mutex_lock(&wl->mutex); | |
3479 | spin_lock_irqsave(&wl->irq_lock, flags); | |
32bfd35d | 3480 | B43_WARN_ON(wl->vif != vif); |
4150c572 JB |
3481 | if (conf->bssid) |
3482 | memcpy(wl->bssid, conf->bssid, ETH_ALEN); | |
3483 | else | |
3484 | memset(wl->bssid, 0, ETH_ALEN); | |
3485 | if (b43_status(dev) >= B43_STAT_INITIALIZED) { | |
3486 | if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) { | |
3487 | B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP); | |
3488 | b43_set_ssid(dev, conf->ssid, conf->ssid_len); | |
5042c507 MB |
3489 | if (conf->beacon) { |
3490 | b43_update_templates(wl, conf->beacon, | |
3491 | conf->beacon_control); | |
3492 | } | |
e4d6b795 | 3493 | } |
4150c572 | 3494 | b43_write_mac_bssid_templates(dev); |
e4d6b795 MB |
3495 | } |
3496 | spin_unlock_irqrestore(&wl->irq_lock, flags); | |
3497 | mutex_unlock(&wl->mutex); | |
3498 | ||
3499 | return 0; | |
3500 | } | |
3501 | ||
3502 | /* Locking: wl->mutex */ | |
3503 | static void b43_wireless_core_stop(struct b43_wldev *dev) | |
3504 | { | |
3505 | struct b43_wl *wl = dev->wl; | |
3506 | unsigned long flags; | |
3507 | ||
3508 | if (b43_status(dev) < B43_STAT_STARTED) | |
3509 | return; | |
a19d12d7 SB |
3510 | |
3511 | /* Disable and sync interrupts. We must do this before than | |
3512 | * setting the status to INITIALIZED, as the interrupt handler | |
3513 | * won't care about IRQs then. */ | |
3514 | spin_lock_irqsave(&wl->irq_lock, flags); | |
3515 | dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL); | |
3516 | b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */ | |
3517 | spin_unlock_irqrestore(&wl->irq_lock, flags); | |
3518 | b43_synchronize_irq(dev); | |
3519 | ||
21a75d77 | 3520 | write_lock_irqsave(&wl->tx_lock, flags); |
e4d6b795 | 3521 | b43_set_status(dev, B43_STAT_INITIALIZED); |
21a75d77 | 3522 | write_unlock_irqrestore(&wl->tx_lock, flags); |
e4d6b795 | 3523 | |
5100d5ac | 3524 | b43_pio_stop(dev); |
e4d6b795 MB |
3525 | mutex_unlock(&wl->mutex); |
3526 | /* Must unlock as it would otherwise deadlock. No races here. | |
3527 | * Cancel the possibly running self-rearming periodic work. */ | |
3528 | cancel_delayed_work_sync(&dev->periodic_work); | |
3529 | mutex_lock(&wl->mutex); | |
3530 | ||
e4d6b795 MB |
3531 | b43_mac_suspend(dev); |
3532 | free_irq(dev->dev->irq, dev); | |
3533 | b43dbg(wl, "Wireless interface stopped\n"); | |
3534 | } | |
3535 | ||
3536 | /* Locking: wl->mutex */ | |
3537 | static int b43_wireless_core_start(struct b43_wldev *dev) | |
3538 | { | |
3539 | int err; | |
3540 | ||
3541 | B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED); | |
3542 | ||
3543 | drain_txstatus_queue(dev); | |
3544 | err = request_irq(dev->dev->irq, b43_interrupt_handler, | |
3545 | IRQF_SHARED, KBUILD_MODNAME, dev); | |
3546 | if (err) { | |
3547 | b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq); | |
3548 | goto out; | |
3549 | } | |
3550 | ||
3551 | /* We are ready to run. */ | |
3552 | b43_set_status(dev, B43_STAT_STARTED); | |
3553 | ||
3554 | /* Start data flow (TX/RX). */ | |
3555 | b43_mac_enable(dev); | |
3556 | b43_interrupt_enable(dev, dev->irq_savedstate); | |
3557 | ieee80211_start_queues(dev->wl->hw); | |
3558 | ||
3559 | /* Start maintainance work */ | |
3560 | b43_periodic_tasks_setup(dev); | |
3561 | ||
3562 | b43dbg(dev->wl, "Wireless interface started\n"); | |
3563 | out: | |
3564 | return err; | |
3565 | } | |
3566 | ||
3567 | /* Get PHY and RADIO versioning numbers */ | |
3568 | static int b43_phy_versioning(struct b43_wldev *dev) | |
3569 | { | |
3570 | struct b43_phy *phy = &dev->phy; | |
3571 | u32 tmp; | |
3572 | u8 analog_type; | |
3573 | u8 phy_type; | |
3574 | u8 phy_rev; | |
3575 | u16 radio_manuf; | |
3576 | u16 radio_ver; | |
3577 | u16 radio_rev; | |
3578 | int unsupported = 0; | |
3579 | ||
3580 | /* Get PHY versioning */ | |
3581 | tmp = b43_read16(dev, B43_MMIO_PHY_VER); | |
3582 | analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT; | |
3583 | phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT; | |
3584 | phy_rev = (tmp & B43_PHYVER_VERSION); | |
3585 | switch (phy_type) { | |
3586 | case B43_PHYTYPE_A: | |
3587 | if (phy_rev >= 4) | |
3588 | unsupported = 1; | |
3589 | break; | |
3590 | case B43_PHYTYPE_B: | |
3591 | if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 | |
3592 | && phy_rev != 7) | |
3593 | unsupported = 1; | |
3594 | break; | |
3595 | case B43_PHYTYPE_G: | |
013978b6 | 3596 | if (phy_rev > 9) |
e4d6b795 MB |
3597 | unsupported = 1; |
3598 | break; | |
d5c71e46 MB |
3599 | #ifdef CONFIG_B43_NPHY |
3600 | case B43_PHYTYPE_N: | |
3601 | if (phy_rev > 1) | |
3602 | unsupported = 1; | |
3603 | break; | |
3604 | #endif | |
e4d6b795 MB |
3605 | default: |
3606 | unsupported = 1; | |
3607 | }; | |
3608 | if (unsupported) { | |
3609 | b43err(dev->wl, "FOUND UNSUPPORTED PHY " | |
3610 | "(Analog %u, Type %u, Revision %u)\n", | |
3611 | analog_type, phy_type, phy_rev); | |
3612 | return -EOPNOTSUPP; | |
3613 | } | |
3614 | b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n", | |
3615 | analog_type, phy_type, phy_rev); | |
3616 | ||
3617 | /* Get RADIO versioning */ | |
3618 | if (dev->dev->bus->chip_id == 0x4317) { | |
3619 | if (dev->dev->bus->chip_rev == 0) | |
3620 | tmp = 0x3205017F; | |
3621 | else if (dev->dev->bus->chip_rev == 1) | |
3622 | tmp = 0x4205017F; | |
3623 | else | |
3624 | tmp = 0x5205017F; | |
3625 | } else { | |
3626 | b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); | |
243dcfcc | 3627 | tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); |
e4d6b795 | 3628 | b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID); |
243dcfcc | 3629 | tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16; |
e4d6b795 MB |
3630 | } |
3631 | radio_manuf = (tmp & 0x00000FFF); | |
3632 | radio_ver = (tmp & 0x0FFFF000) >> 12; | |
3633 | radio_rev = (tmp & 0xF0000000) >> 28; | |
96c755a3 MB |
3634 | if (radio_manuf != 0x17F /* Broadcom */) |
3635 | unsupported = 1; | |
e4d6b795 MB |
3636 | switch (phy_type) { |
3637 | case B43_PHYTYPE_A: | |
3638 | if (radio_ver != 0x2060) | |
3639 | unsupported = 1; | |
3640 | if (radio_rev != 1) | |
3641 | unsupported = 1; | |
3642 | if (radio_manuf != 0x17F) | |
3643 | unsupported = 1; | |
3644 | break; | |
3645 | case B43_PHYTYPE_B: | |
3646 | if ((radio_ver & 0xFFF0) != 0x2050) | |
3647 | unsupported = 1; | |
3648 | break; | |
3649 | case B43_PHYTYPE_G: | |
3650 | if (radio_ver != 0x2050) | |
3651 | unsupported = 1; | |
3652 | break; | |
96c755a3 | 3653 | case B43_PHYTYPE_N: |
243dcfcc | 3654 | if (radio_ver != 0x2055) |
96c755a3 MB |
3655 | unsupported = 1; |
3656 | break; | |
e4d6b795 MB |
3657 | default: |
3658 | B43_WARN_ON(1); | |
3659 | } | |
3660 | if (unsupported) { | |
3661 | b43err(dev->wl, "FOUND UNSUPPORTED RADIO " | |
3662 | "(Manuf 0x%X, Version 0x%X, Revision %u)\n", | |
3663 | radio_manuf, radio_ver, radio_rev); | |
3664 | return -EOPNOTSUPP; | |
3665 | } | |
3666 | b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n", | |
3667 | radio_manuf, radio_ver, radio_rev); | |
3668 | ||
3669 | phy->radio_manuf = radio_manuf; | |
3670 | phy->radio_ver = radio_ver; | |
3671 | phy->radio_rev = radio_rev; | |
3672 | ||
3673 | phy->analog = analog_type; | |
3674 | phy->type = phy_type; | |
3675 | phy->rev = phy_rev; | |
3676 | ||
3677 | return 0; | |
3678 | } | |
3679 | ||
3680 | static void setup_struct_phy_for_init(struct b43_wldev *dev, | |
3681 | struct b43_phy *phy) | |
3682 | { | |
3683 | struct b43_txpower_lo_control *lo; | |
3684 | int i; | |
3685 | ||
3686 | memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig)); | |
3687 | memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos)); | |
3688 | ||
e4d6b795 MB |
3689 | phy->aci_enable = 0; |
3690 | phy->aci_wlan_automatic = 0; | |
3691 | phy->aci_hw_rssi = 0; | |
3692 | ||
fda9abcf MB |
3693 | phy->radio_off_context.valid = 0; |
3694 | ||
e4d6b795 MB |
3695 | lo = phy->lo_control; |
3696 | if (lo) { | |
3697 | memset(lo, 0, sizeof(*(phy->lo_control))); | |
3698 | lo->rebuild = 1; | |
3699 | lo->tx_bias = 0xFF; | |
3700 | } | |
3701 | phy->max_lb_gain = 0; | |
3702 | phy->trsw_rx_gain = 0; | |
3703 | phy->txpwr_offset = 0; | |
3704 | ||
3705 | /* NRSSI */ | |
3706 | phy->nrssislope = 0; | |
3707 | for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++) | |
3708 | phy->nrssi[i] = -1000; | |
3709 | for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++) | |
3710 | phy->nrssi_lt[i] = i; | |
3711 | ||
3712 | phy->lofcal = 0xFFFF; | |
3713 | phy->initval = 0xFFFF; | |
3714 | ||
e4d6b795 MB |
3715 | phy->interfmode = B43_INTERFMODE_NONE; |
3716 | phy->channel = 0xFF; | |
3717 | ||
3718 | phy->hardware_power_control = !!modparam_hwpctl; | |
8ed7fc48 MB |
3719 | |
3720 | /* PHY TX errors counter. */ | |
3721 | atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT); | |
3722 | ||
3723 | /* OFDM-table address caching. */ | |
3724 | phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN; | |
e4d6b795 MB |
3725 | } |
3726 | ||
3727 | static void setup_struct_wldev_for_init(struct b43_wldev *dev) | |
3728 | { | |
aa6c7ae2 MB |
3729 | dev->dfq_valid = 0; |
3730 | ||
6a724d68 MB |
3731 | /* Assume the radio is enabled. If it's not enabled, the state will |
3732 | * immediately get fixed on the first periodic work run. */ | |
3733 | dev->radio_hw_enable = 1; | |
e4d6b795 MB |
3734 | |
3735 | /* Stats */ | |
3736 | memset(&dev->stats, 0, sizeof(dev->stats)); | |
3737 | ||
3738 | setup_struct_phy_for_init(dev, &dev->phy); | |
3739 | ||
3740 | /* IRQ related flags */ | |
3741 | dev->irq_reason = 0; | |
3742 | memset(dev->dma_reason, 0, sizeof(dev->dma_reason)); | |
3743 | dev->irq_savedstate = B43_IRQ_MASKTEMPLATE; | |
3744 | ||
3745 | dev->mac_suspended = 1; | |
3746 | ||
3747 | /* Noise calculation context */ | |
3748 | memset(&dev->noisecalc, 0, sizeof(dev->noisecalc)); | |
3749 | } | |
3750 | ||
3751 | static void b43_bluetooth_coext_enable(struct b43_wldev *dev) | |
3752 | { | |
3753 | struct ssb_sprom *sprom = &dev->dev->bus->sprom; | |
a259d6a4 | 3754 | u64 hf; |
e4d6b795 | 3755 | |
1855ba78 MB |
3756 | if (!modparam_btcoex) |
3757 | return; | |
95de2841 | 3758 | if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST)) |
e4d6b795 MB |
3759 | return; |
3760 | if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode) | |
3761 | return; | |
3762 | ||
3763 | hf = b43_hf_read(dev); | |
95de2841 | 3764 | if (sprom->boardflags_lo & B43_BFL_BTCMOD) |
e4d6b795 MB |
3765 | hf |= B43_HF_BTCOEXALT; |
3766 | else | |
3767 | hf |= B43_HF_BTCOEX; | |
3768 | b43_hf_write(dev, hf); | |
e4d6b795 MB |
3769 | } |
3770 | ||
3771 | static void b43_bluetooth_coext_disable(struct b43_wldev *dev) | |
1855ba78 MB |
3772 | { |
3773 | if (!modparam_btcoex) | |
3774 | return; | |
3775 | //TODO | |
e4d6b795 MB |
3776 | } |
3777 | ||
3778 | static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev) | |
3779 | { | |
3780 | #ifdef CONFIG_SSB_DRIVER_PCICORE | |
3781 | struct ssb_bus *bus = dev->dev->bus; | |
3782 | u32 tmp; | |
3783 | ||
3784 | if (bus->pcicore.dev && | |
3785 | bus->pcicore.dev->id.coreid == SSB_DEV_PCI && | |
3786 | bus->pcicore.dev->id.revision <= 5) { | |
3787 | /* IMCFGLO timeouts workaround. */ | |
3788 | tmp = ssb_read32(dev->dev, SSB_IMCFGLO); | |
3789 | tmp &= ~SSB_IMCFGLO_REQTO; | |
3790 | tmp &= ~SSB_IMCFGLO_SERTO; | |
3791 | switch (bus->bustype) { | |
3792 | case SSB_BUSTYPE_PCI: | |
3793 | case SSB_BUSTYPE_PCMCIA: | |
3794 | tmp |= 0x32; | |
3795 | break; | |
3796 | case SSB_BUSTYPE_SSB: | |
3797 | tmp |= 0x53; | |
3798 | break; | |
3799 | } | |
3800 | ssb_write32(dev->dev, SSB_IMCFGLO, tmp); | |
3801 | } | |
3802 | #endif /* CONFIG_SSB_DRIVER_PCICORE */ | |
3803 | } | |
3804 | ||
74cfdba7 MB |
3805 | /* Write the short and long frame retry limit values. */ |
3806 | static void b43_set_retry_limits(struct b43_wldev *dev, | |
3807 | unsigned int short_retry, | |
3808 | unsigned int long_retry) | |
3809 | { | |
3810 | /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing | |
3811 | * the chip-internal counter. */ | |
3812 | short_retry = min(short_retry, (unsigned int)0xF); | |
3813 | long_retry = min(long_retry, (unsigned int)0xF); | |
3814 | ||
3815 | b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT, | |
3816 | short_retry); | |
3817 | b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT, | |
3818 | long_retry); | |
3819 | } | |
3820 | ||
d59f720d MB |
3821 | static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle) |
3822 | { | |
3823 | u16 pu_delay; | |
3824 | ||
3825 | /* The time value is in microseconds. */ | |
3826 | if (dev->phy.type == B43_PHYTYPE_A) | |
3827 | pu_delay = 3700; | |
3828 | else | |
3829 | pu_delay = 1050; | |
8cf6a31e | 3830 | if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS) || idle) |
d59f720d MB |
3831 | pu_delay = 500; |
3832 | if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8)) | |
3833 | pu_delay = max(pu_delay, (u16)2400); | |
3834 | ||
3835 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay); | |
3836 | } | |
3837 | ||
3838 | /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */ | |
3839 | static void b43_set_pretbtt(struct b43_wldev *dev) | |
3840 | { | |
3841 | u16 pretbtt; | |
3842 | ||
3843 | /* The time value is in microseconds. */ | |
8cf6a31e | 3844 | if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS)) { |
d59f720d MB |
3845 | pretbtt = 2; |
3846 | } else { | |
3847 | if (dev->phy.type == B43_PHYTYPE_A) | |
3848 | pretbtt = 120; | |
3849 | else | |
3850 | pretbtt = 250; | |
3851 | } | |
3852 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt); | |
3853 | b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt); | |
3854 | } | |
3855 | ||
e4d6b795 MB |
3856 | /* Shutdown a wireless core */ |
3857 | /* Locking: wl->mutex */ | |
3858 | static void b43_wireless_core_exit(struct b43_wldev *dev) | |
3859 | { | |
3860 | struct b43_phy *phy = &dev->phy; | |
1f7d87b0 | 3861 | u32 macctl; |
e4d6b795 MB |
3862 | |
3863 | B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED); | |
3864 | if (b43_status(dev) != B43_STAT_INITIALIZED) | |
3865 | return; | |
3866 | b43_set_status(dev, B43_STAT_UNINIT); | |
3867 | ||
1f7d87b0 MB |
3868 | /* Stop the microcode PSM. */ |
3869 | macctl = b43_read32(dev, B43_MMIO_MACCTL); | |
3870 | macctl &= ~B43_MACCTL_PSM_RUN; | |
3871 | macctl |= B43_MACCTL_PSM_JMP0; | |
3872 | b43_write32(dev, B43_MMIO_MACCTL, macctl); | |
3873 | ||
3506e0c4 RW |
3874 | if (!dev->suspend_in_progress) { |
3875 | b43_leds_exit(dev); | |
b844eba2 | 3876 | b43_rng_exit(dev->wl); |
3506e0c4 | 3877 | } |
e4d6b795 | 3878 | b43_dma_free(dev); |
5100d5ac | 3879 | b43_pio_free(dev); |
e4d6b795 | 3880 | b43_chip_exit(dev); |
8e9f7529 | 3881 | b43_radio_turn_off(dev, 1); |
e4d6b795 MB |
3882 | b43_switch_analog(dev, 0); |
3883 | if (phy->dyn_tssi_tbl) | |
3884 | kfree(phy->tssi2dbm); | |
3885 | kfree(phy->lo_control); | |
3886 | phy->lo_control = NULL; | |
e66fee6a MB |
3887 | if (dev->wl->current_beacon) { |
3888 | dev_kfree_skb_any(dev->wl->current_beacon); | |
3889 | dev->wl->current_beacon = NULL; | |
3890 | } | |
3891 | ||
e4d6b795 MB |
3892 | ssb_device_disable(dev->dev, 0); |
3893 | ssb_bus_may_powerdown(dev->dev->bus); | |
3894 | } | |
3895 | ||
3896 | /* Initialize a wireless core */ | |
3897 | static int b43_wireless_core_init(struct b43_wldev *dev) | |
3898 | { | |
3899 | struct b43_wl *wl = dev->wl; | |
3900 | struct ssb_bus *bus = dev->dev->bus; | |
3901 | struct ssb_sprom *sprom = &bus->sprom; | |
3902 | struct b43_phy *phy = &dev->phy; | |
3903 | int err; | |
a259d6a4 MB |
3904 | u64 hf; |
3905 | u32 tmp; | |
e4d6b795 MB |
3906 | |
3907 | B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); | |
3908 | ||
3909 | err = ssb_bus_powerup(bus, 0); | |
3910 | if (err) | |
3911 | goto out; | |
3912 | if (!ssb_device_is_enabled(dev->dev)) { | |
3913 | tmp = phy->gmode ? B43_TMSLOW_GMODE : 0; | |
3914 | b43_wireless_core_reset(dev, tmp); | |
3915 | } | |
3916 | ||
3917 | if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) { | |
3918 | phy->lo_control = | |
3919 | kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL); | |
3920 | if (!phy->lo_control) { | |
3921 | err = -ENOMEM; | |
3922 | goto err_busdown; | |
3923 | } | |
3924 | } | |
3925 | setup_struct_wldev_for_init(dev); | |
3926 | ||
3927 | err = b43_phy_init_tssi2dbm_table(dev); | |
3928 | if (err) | |
3929 | goto err_kfree_lo_control; | |
3930 | ||
3931 | /* Enable IRQ routing to this device. */ | |
3932 | ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev); | |
3933 | ||
3934 | b43_imcfglo_timeouts_workaround(dev); | |
3935 | b43_bluetooth_coext_disable(dev); | |
3936 | b43_phy_early_init(dev); | |
3937 | err = b43_chip_init(dev); | |
3938 | if (err) | |
3939 | goto err_kfree_tssitbl; | |
3940 | b43_shm_write16(dev, B43_SHM_SHARED, | |
3941 | B43_SHM_SH_WLCOREREV, dev->dev->id.revision); | |
3942 | hf = b43_hf_read(dev); | |
3943 | if (phy->type == B43_PHYTYPE_G) { | |
3944 | hf |= B43_HF_SYMW; | |
3945 | if (phy->rev == 1) | |
3946 | hf |= B43_HF_GDCW; | |
95de2841 | 3947 | if (sprom->boardflags_lo & B43_BFL_PACTRL) |
e4d6b795 MB |
3948 | hf |= B43_HF_OFDMPABOOST; |
3949 | } else if (phy->type == B43_PHYTYPE_B) { | |
3950 | hf |= B43_HF_SYMW; | |
3951 | if (phy->rev >= 2 && phy->radio_ver == 0x2050) | |
3952 | hf &= ~B43_HF_GDCW; | |
3953 | } | |
3954 | b43_hf_write(dev, hf); | |
3955 | ||
74cfdba7 MB |
3956 | b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT, |
3957 | B43_DEFAULT_LONG_RETRY_LIMIT); | |
e4d6b795 MB |
3958 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3); |
3959 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2); | |
3960 | ||
3961 | /* Disable sending probe responses from firmware. | |
3962 | * Setting the MaxTime to one usec will always trigger | |
3963 | * a timeout, so we never send any probe resp. | |
3964 | * A timeout of zero is infinite. */ | |
3965 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1); | |
3966 | ||
3967 | b43_rate_memory_init(dev); | |
5042c507 | 3968 | b43_set_phytxctl_defaults(dev); |
e4d6b795 MB |
3969 | |
3970 | /* Minimum Contention Window */ | |
3971 | if (phy->type == B43_PHYTYPE_B) { | |
3972 | b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F); | |
3973 | } else { | |
3974 | b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF); | |
3975 | } | |
3976 | /* Maximum Contention Window */ | |
3977 | b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF); | |
3978 | ||
5100d5ac MB |
3979 | if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) { |
3980 | dev->__using_pio_transfers = 1; | |
3981 | err = b43_pio_init(dev); | |
3982 | } else { | |
3983 | dev->__using_pio_transfers = 0; | |
3984 | err = b43_dma_init(dev); | |
3985 | } | |
e4d6b795 MB |
3986 | if (err) |
3987 | goto err_chip_exit; | |
03b29773 | 3988 | b43_qos_init(dev); |
d59f720d | 3989 | b43_set_synth_pu_delay(dev, 1); |
e4d6b795 MB |
3990 | b43_bluetooth_coext_enable(dev); |
3991 | ||
3992 | ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */ | |
4150c572 | 3993 | b43_upload_card_macaddress(dev); |
e4d6b795 | 3994 | b43_security_init(dev); |
3506e0c4 RW |
3995 | if (!dev->suspend_in_progress) |
3996 | b43_rng_init(wl); | |
e4d6b795 MB |
3997 | |
3998 | b43_set_status(dev, B43_STAT_INITIALIZED); | |
3999 | ||
3506e0c4 RW |
4000 | if (!dev->suspend_in_progress) |
4001 | b43_leds_init(dev); | |
1a8d1227 | 4002 | out: |
e4d6b795 MB |
4003 | return err; |
4004 | ||
4005 | err_chip_exit: | |
4006 | b43_chip_exit(dev); | |
4007 | err_kfree_tssitbl: | |
4008 | if (phy->dyn_tssi_tbl) | |
4009 | kfree(phy->tssi2dbm); | |
4010 | err_kfree_lo_control: | |
4011 | kfree(phy->lo_control); | |
4012 | phy->lo_control = NULL; | |
4013 | err_busdown: | |
4014 | ssb_bus_may_powerdown(bus); | |
4015 | B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT); | |
4016 | return err; | |
4017 | } | |
4018 | ||
40faacc4 MB |
4019 | static int b43_op_add_interface(struct ieee80211_hw *hw, |
4020 | struct ieee80211_if_init_conf *conf) | |
e4d6b795 MB |
4021 | { |
4022 | struct b43_wl *wl = hw_to_b43_wl(hw); | |
4023 | struct b43_wldev *dev; | |
4024 | unsigned long flags; | |
4025 | int err = -EOPNOTSUPP; | |
4150c572 JB |
4026 | |
4027 | /* TODO: allow WDS/AP devices to coexist */ | |
4028 | ||
4029 | if (conf->type != IEEE80211_IF_TYPE_AP && | |
4030 | conf->type != IEEE80211_IF_TYPE_STA && | |
4031 | conf->type != IEEE80211_IF_TYPE_WDS && | |
4032 | conf->type != IEEE80211_IF_TYPE_IBSS) | |
4033 | return -EOPNOTSUPP; | |
e4d6b795 MB |
4034 | |
4035 | mutex_lock(&wl->mutex); | |
4150c572 | 4036 | if (wl->operating) |
e4d6b795 MB |
4037 | goto out_mutex_unlock; |
4038 | ||
4039 | b43dbg(wl, "Adding Interface type %d\n", conf->type); | |
4040 | ||
4041 | dev = wl->current_dev; | |
4150c572 | 4042 | wl->operating = 1; |
32bfd35d | 4043 | wl->vif = conf->vif; |
4150c572 JB |
4044 | wl->if_type = conf->type; |
4045 | memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN); | |
4046 | ||
4047 | spin_lock_irqsave(&wl->irq_lock, flags); | |
4048 | b43_adjust_opmode(dev); | |
d59f720d MB |
4049 | b43_set_pretbtt(dev); |
4050 | b43_set_synth_pu_delay(dev, 0); | |
4150c572 JB |
4051 | b43_upload_card_macaddress(dev); |
4052 | spin_unlock_irqrestore(&wl->irq_lock, flags); | |
4053 | ||
4054 | err = 0; | |
4055 | out_mutex_unlock: | |
4056 | mutex_unlock(&wl->mutex); | |
4057 | ||
4058 | return err; | |
4059 | } | |
4060 | ||
40faacc4 MB |
4061 | static void b43_op_remove_interface(struct ieee80211_hw *hw, |
4062 | struct ieee80211_if_init_conf *conf) | |
4150c572 JB |
4063 | { |
4064 | struct b43_wl *wl = hw_to_b43_wl(hw); | |
4065 | struct b43_wldev *dev = wl->current_dev; | |
4066 | unsigned long flags; | |
4067 | ||
4068 | b43dbg(wl, "Removing Interface type %d\n", conf->type); | |
4069 | ||
4070 | mutex_lock(&wl->mutex); | |
4071 | ||
4072 | B43_WARN_ON(!wl->operating); | |
32bfd35d JB |
4073 | B43_WARN_ON(wl->vif != conf->vif); |
4074 | wl->vif = NULL; | |
4150c572 JB |
4075 | |
4076 | wl->operating = 0; | |
4077 | ||
4078 | spin_lock_irqsave(&wl->irq_lock, flags); | |
4079 | b43_adjust_opmode(dev); | |
4080 | memset(wl->mac_addr, 0, ETH_ALEN); | |
4081 | b43_upload_card_macaddress(dev); | |
4082 | spin_unlock_irqrestore(&wl->irq_lock, flags); | |
4083 | ||
4084 | mutex_unlock(&wl->mutex); | |
4085 | } | |
4086 | ||
40faacc4 | 4087 | static int b43_op_start(struct ieee80211_hw *hw) |
4150c572 JB |
4088 | { |
4089 | struct b43_wl *wl = hw_to_b43_wl(hw); | |
4090 | struct b43_wldev *dev = wl->current_dev; | |
4091 | int did_init = 0; | |
923403b8 | 4092 | int err = 0; |
1946a2c3 | 4093 | bool do_rfkill_exit = 0; |
4150c572 | 4094 | |
7be1bb6b MB |
4095 | /* Kill all old instance specific information to make sure |
4096 | * the card won't use it in the short timeframe between start | |
4097 | * and mac80211 reconfiguring it. */ | |
4098 | memset(wl->bssid, 0, ETH_ALEN); | |
4099 | memset(wl->mac_addr, 0, ETH_ALEN); | |
4100 | wl->filter_flags = 0; | |
4101 | wl->radiotap_enabled = 0; | |
e6f5b934 | 4102 | b43_qos_clear(wl); |
6b4bec01 MB |
4103 | wl->beacon0_uploaded = 0; |
4104 | wl->beacon1_uploaded = 0; | |
4105 | wl->beacon_templates_virgin = 1; | |
7be1bb6b | 4106 | |
1a8d1227 LF |
4107 | /* First register RFkill. |
4108 | * LEDs that are registered later depend on it. */ | |
4109 | b43_rfkill_init(dev); | |
4110 | ||
4150c572 JB |
4111 | mutex_lock(&wl->mutex); |
4112 | ||
e4d6b795 MB |
4113 | if (b43_status(dev) < B43_STAT_INITIALIZED) { |
4114 | err = b43_wireless_core_init(dev); | |
1946a2c3 MB |
4115 | if (err) { |
4116 | do_rfkill_exit = 1; | |
e4d6b795 | 4117 | goto out_mutex_unlock; |
1946a2c3 | 4118 | } |
e4d6b795 MB |
4119 | did_init = 1; |
4120 | } | |
4150c572 | 4121 | |
e4d6b795 MB |
4122 | if (b43_status(dev) < B43_STAT_STARTED) { |
4123 | err = b43_wireless_core_start(dev); | |
4124 | if (err) { | |
4125 | if (did_init) | |
4126 | b43_wireless_core_exit(dev); | |
1946a2c3 | 4127 | do_rfkill_exit = 1; |
e4d6b795 MB |
4128 | goto out_mutex_unlock; |
4129 | } | |
4130 | } | |
4131 | ||
4150c572 | 4132 | out_mutex_unlock: |
e4d6b795 MB |
4133 | mutex_unlock(&wl->mutex); |
4134 | ||
1946a2c3 MB |
4135 | if (do_rfkill_exit) |
4136 | b43_rfkill_exit(dev); | |
4137 | ||
e4d6b795 MB |
4138 | return err; |
4139 | } | |
4140 | ||
40faacc4 | 4141 | static void b43_op_stop(struct ieee80211_hw *hw) |
e4d6b795 MB |
4142 | { |
4143 | struct b43_wl *wl = hw_to_b43_wl(hw); | |
4150c572 | 4144 | struct b43_wldev *dev = wl->current_dev; |
e4d6b795 | 4145 | |
1a8d1227 | 4146 | b43_rfkill_exit(dev); |
e6f5b934 | 4147 | cancel_work_sync(&(wl->qos_update_work)); |
a82d9922 | 4148 | cancel_work_sync(&(wl->beacon_update_trigger)); |
1a8d1227 | 4149 | |
e4d6b795 | 4150 | mutex_lock(&wl->mutex); |
4150c572 JB |
4151 | if (b43_status(dev) >= B43_STAT_STARTED) |
4152 | b43_wireless_core_stop(dev); | |
4153 | b43_wireless_core_exit(dev); | |
e4d6b795 MB |
4154 | mutex_unlock(&wl->mutex); |
4155 | } | |
4156 | ||
74cfdba7 MB |
4157 | static int b43_op_set_retry_limit(struct ieee80211_hw *hw, |
4158 | u32 short_retry_limit, u32 long_retry_limit) | |
4159 | { | |
4160 | struct b43_wl *wl = hw_to_b43_wl(hw); | |
4161 | struct b43_wldev *dev; | |
4162 | int err = 0; | |
4163 | ||
4164 | mutex_lock(&wl->mutex); | |
4165 | dev = wl->current_dev; | |
4166 | if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) { | |
4167 | err = -ENODEV; | |
4168 | goto out_unlock; | |
4169 | } | |
4170 | b43_set_retry_limits(dev, short_retry_limit, long_retry_limit); | |
4171 | out_unlock: | |
4172 | mutex_unlock(&wl->mutex); | |
4173 | ||
4174 | return err; | |
4175 | } | |
4176 | ||
e66fee6a MB |
4177 | static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set) |
4178 | { | |
4179 | struct b43_wl *wl = hw_to_b43_wl(hw); | |
4180 | struct sk_buff *beacon; | |
d4df6f1a | 4181 | unsigned long flags; |
5042c507 | 4182 | struct ieee80211_tx_control txctl; |
e66fee6a MB |
4183 | |
4184 | /* We could modify the existing beacon and set the aid bit in | |
4185 | * the TIM field, but that would probably require resizing and | |
4186 | * moving of data within the beacon template. | |
4187 | * Simply request a new beacon and let mac80211 do the hard work. */ | |
5042c507 | 4188 | beacon = ieee80211_beacon_get(hw, wl->vif, &txctl); |
e66fee6a MB |
4189 | if (unlikely(!beacon)) |
4190 | return -ENOMEM; | |
d4df6f1a | 4191 | spin_lock_irqsave(&wl->irq_lock, flags); |
5042c507 | 4192 | b43_update_templates(wl, beacon, &txctl); |
d4df6f1a | 4193 | spin_unlock_irqrestore(&wl->irq_lock, flags); |
e66fee6a MB |
4194 | |
4195 | return 0; | |
4196 | } | |
4197 | ||
4198 | static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw, | |
4199 | struct sk_buff *beacon, | |
4200 | struct ieee80211_tx_control *ctl) | |
4201 | { | |
4202 | struct b43_wl *wl = hw_to_b43_wl(hw); | |
d4df6f1a | 4203 | unsigned long flags; |
e66fee6a | 4204 | |
d4df6f1a | 4205 | spin_lock_irqsave(&wl->irq_lock, flags); |
5042c507 | 4206 | b43_update_templates(wl, beacon, ctl); |
d4df6f1a | 4207 | spin_unlock_irqrestore(&wl->irq_lock, flags); |
e66fee6a MB |
4208 | |
4209 | return 0; | |
4210 | } | |
4211 | ||
38968d09 JB |
4212 | static void b43_op_sta_notify(struct ieee80211_hw *hw, |
4213 | struct ieee80211_vif *vif, | |
4214 | enum sta_notify_cmd notify_cmd, | |
4215 | const u8 *addr) | |
4216 | { | |
4217 | struct b43_wl *wl = hw_to_b43_wl(hw); | |
4218 | ||
4219 | B43_WARN_ON(!vif || wl->vif != vif); | |
4220 | } | |
4221 | ||
e4d6b795 | 4222 | static const struct ieee80211_ops b43_hw_ops = { |
40faacc4 MB |
4223 | .tx = b43_op_tx, |
4224 | .conf_tx = b43_op_conf_tx, | |
4225 | .add_interface = b43_op_add_interface, | |
4226 | .remove_interface = b43_op_remove_interface, | |
4227 | .config = b43_op_config, | |
4228 | .config_interface = b43_op_config_interface, | |
4229 | .configure_filter = b43_op_configure_filter, | |
4230 | .set_key = b43_op_set_key, | |
4231 | .get_stats = b43_op_get_stats, | |
4232 | .get_tx_stats = b43_op_get_tx_stats, | |
4233 | .start = b43_op_start, | |
4234 | .stop = b43_op_stop, | |
74cfdba7 | 4235 | .set_retry_limit = b43_op_set_retry_limit, |
e66fee6a MB |
4236 | .set_tim = b43_op_beacon_set_tim, |
4237 | .beacon_update = b43_op_ibss_beacon_update, | |
38968d09 | 4238 | .sta_notify = b43_op_sta_notify, |
e4d6b795 MB |
4239 | }; |
4240 | ||
4241 | /* Hard-reset the chip. Do not call this directly. | |
4242 | * Use b43_controller_restart() | |
4243 | */ | |
4244 | static void b43_chip_reset(struct work_struct *work) | |
4245 | { | |
4246 | struct b43_wldev *dev = | |
4247 | container_of(work, struct b43_wldev, restart_work); | |
4248 | struct b43_wl *wl = dev->wl; | |
4249 | int err = 0; | |
4250 | int prev_status; | |
4251 | ||
4252 | mutex_lock(&wl->mutex); | |
4253 | ||
4254 | prev_status = b43_status(dev); | |
4255 | /* Bring the device down... */ | |
4256 | if (prev_status >= B43_STAT_STARTED) | |
4257 | b43_wireless_core_stop(dev); | |
4258 | if (prev_status >= B43_STAT_INITIALIZED) | |
4259 | b43_wireless_core_exit(dev); | |
4260 | ||
4261 | /* ...and up again. */ | |
4262 | if (prev_status >= B43_STAT_INITIALIZED) { | |
4263 | err = b43_wireless_core_init(dev); | |
4264 | if (err) | |
4265 | goto out; | |
4266 | } | |
4267 | if (prev_status >= B43_STAT_STARTED) { | |
4268 | err = b43_wireless_core_start(dev); | |
4269 | if (err) { | |
4270 | b43_wireless_core_exit(dev); | |
4271 | goto out; | |
4272 | } | |
4273 | } | |
4274 | out: | |
4275 | mutex_unlock(&wl->mutex); | |
4276 | if (err) | |
4277 | b43err(wl, "Controller restart FAILED\n"); | |
4278 | else | |
4279 | b43info(wl, "Controller restarted\n"); | |
4280 | } | |
4281 | ||
bb1eeff1 | 4282 | static int b43_setup_bands(struct b43_wldev *dev, |
96c755a3 | 4283 | bool have_2ghz_phy, bool have_5ghz_phy) |
e4d6b795 MB |
4284 | { |
4285 | struct ieee80211_hw *hw = dev->wl->hw; | |
e4d6b795 | 4286 | |
bb1eeff1 MB |
4287 | if (have_2ghz_phy) |
4288 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz; | |
4289 | if (dev->phy.type == B43_PHYTYPE_N) { | |
4290 | if (have_5ghz_phy) | |
4291 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy; | |
4292 | } else { | |
4293 | if (have_5ghz_phy) | |
4294 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy; | |
4295 | } | |
96c755a3 | 4296 | |
bb1eeff1 MB |
4297 | dev->phy.supports_2ghz = have_2ghz_phy; |
4298 | dev->phy.supports_5ghz = have_5ghz_phy; | |
e4d6b795 MB |
4299 | |
4300 | return 0; | |
4301 | } | |
4302 | ||
4303 | static void b43_wireless_core_detach(struct b43_wldev *dev) | |
4304 | { | |
4305 | /* We release firmware that late to not be required to re-request | |
4306 | * is all the time when we reinit the core. */ | |
4307 | b43_release_firmware(dev); | |
4308 | } | |
4309 | ||
4310 | static int b43_wireless_core_attach(struct b43_wldev *dev) | |
4311 | { | |
4312 | struct b43_wl *wl = dev->wl; | |
4313 | struct ssb_bus *bus = dev->dev->bus; | |
4314 | struct pci_dev *pdev = bus->host_pci; | |
4315 | int err; | |
96c755a3 | 4316 | bool have_2ghz_phy = 0, have_5ghz_phy = 0; |
e4d6b795 MB |
4317 | u32 tmp; |
4318 | ||
4319 | /* Do NOT do any device initialization here. | |
4320 | * Do it in wireless_core_init() instead. | |
4321 | * This function is for gathering basic information about the HW, only. | |
4322 | * Also some structs may be set up here. But most likely you want to have | |
4323 | * that in core_init(), too. | |
4324 | */ | |
4325 | ||
4326 | err = ssb_bus_powerup(bus, 0); | |
4327 | if (err) { | |
4328 | b43err(wl, "Bus powerup failed\n"); | |
4329 | goto out; | |
4330 | } | |
4331 | /* Get the PHY type. */ | |
4332 | if (dev->dev->id.revision >= 5) { | |
4333 | u32 tmshigh; | |
4334 | ||
4335 | tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH); | |
96c755a3 MB |
4336 | have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY); |
4337 | have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY); | |
e4d6b795 | 4338 | } else |
96c755a3 | 4339 | B43_WARN_ON(1); |
e4d6b795 | 4340 | |
96c755a3 | 4341 | dev->phy.gmode = have_2ghz_phy; |
e4d6b795 MB |
4342 | tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; |
4343 | b43_wireless_core_reset(dev, tmp); | |
4344 | ||
4345 | err = b43_phy_versioning(dev); | |
4346 | if (err) | |
21954c36 | 4347 | goto err_powerdown; |
e4d6b795 MB |
4348 | /* Check if this device supports multiband. */ |
4349 | if (!pdev || | |
4350 | (pdev->device != 0x4312 && | |
4351 | pdev->device != 0x4319 && pdev->device != 0x4324)) { | |
4352 | /* No multiband support. */ | |
96c755a3 MB |
4353 | have_2ghz_phy = 0; |
4354 | have_5ghz_phy = 0; | |
e4d6b795 MB |
4355 | switch (dev->phy.type) { |
4356 | case B43_PHYTYPE_A: | |
96c755a3 | 4357 | have_5ghz_phy = 1; |
e4d6b795 MB |
4358 | break; |
4359 | case B43_PHYTYPE_G: | |
96c755a3 MB |
4360 | case B43_PHYTYPE_N: |
4361 | have_2ghz_phy = 1; | |
e4d6b795 MB |
4362 | break; |
4363 | default: | |
4364 | B43_WARN_ON(1); | |
4365 | } | |
4366 | } | |
96c755a3 MB |
4367 | if (dev->phy.type == B43_PHYTYPE_A) { |
4368 | /* FIXME */ | |
4369 | b43err(wl, "IEEE 802.11a devices are unsupported\n"); | |
4370 | err = -EOPNOTSUPP; | |
4371 | goto err_powerdown; | |
4372 | } | |
2e35af14 MB |
4373 | if (1 /* disable A-PHY */) { |
4374 | /* FIXME: For now we disable the A-PHY on multi-PHY devices. */ | |
4375 | if (dev->phy.type != B43_PHYTYPE_N) { | |
4376 | have_2ghz_phy = 1; | |
4377 | have_5ghz_phy = 0; | |
4378 | } | |
4379 | } | |
4380 | ||
96c755a3 | 4381 | dev->phy.gmode = have_2ghz_phy; |
e4d6b795 MB |
4382 | tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0; |
4383 | b43_wireless_core_reset(dev, tmp); | |
4384 | ||
4385 | err = b43_validate_chipaccess(dev); | |
4386 | if (err) | |
21954c36 | 4387 | goto err_powerdown; |
bb1eeff1 | 4388 | err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy); |
e4d6b795 | 4389 | if (err) |
21954c36 | 4390 | goto err_powerdown; |
e4d6b795 MB |
4391 | |
4392 | /* Now set some default "current_dev" */ | |
4393 | if (!wl->current_dev) | |
4394 | wl->current_dev = dev; | |
4395 | INIT_WORK(&dev->restart_work, b43_chip_reset); | |
4396 | ||
8e9f7529 | 4397 | b43_radio_turn_off(dev, 1); |
e4d6b795 MB |
4398 | b43_switch_analog(dev, 0); |
4399 | ssb_device_disable(dev->dev, 0); | |
4400 | ssb_bus_may_powerdown(bus); | |
4401 | ||
4402 | out: | |
4403 | return err; | |
4404 | ||
e4d6b795 MB |
4405 | err_powerdown: |
4406 | ssb_bus_may_powerdown(bus); | |
4407 | return err; | |
4408 | } | |
4409 | ||
4410 | static void b43_one_core_detach(struct ssb_device *dev) | |
4411 | { | |
4412 | struct b43_wldev *wldev; | |
4413 | struct b43_wl *wl; | |
4414 | ||
4415 | wldev = ssb_get_drvdata(dev); | |
4416 | wl = wldev->wl; | |
4417 | cancel_work_sync(&wldev->restart_work); | |
4418 | b43_debugfs_remove_device(wldev); | |
4419 | b43_wireless_core_detach(wldev); | |
4420 | list_del(&wldev->list); | |
4421 | wl->nr_devs--; | |
4422 | ssb_set_drvdata(dev, NULL); | |
4423 | kfree(wldev); | |
4424 | } | |
4425 | ||
4426 | static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl) | |
4427 | { | |
4428 | struct b43_wldev *wldev; | |
4429 | struct pci_dev *pdev; | |
4430 | int err = -ENOMEM; | |
4431 | ||
4432 | if (!list_empty(&wl->devlist)) { | |
4433 | /* We are not the first core on this chip. */ | |
4434 | pdev = dev->bus->host_pci; | |
4435 | /* Only special chips support more than one wireless | |
4436 | * core, although some of the other chips have more than | |
4437 | * one wireless core as well. Check for this and | |
4438 | * bail out early. | |
4439 | */ | |
4440 | if (!pdev || | |
4441 | ((pdev->device != 0x4321) && | |
4442 | (pdev->device != 0x4313) && (pdev->device != 0x431A))) { | |
4443 | b43dbg(wl, "Ignoring unconnected 802.11 core\n"); | |
4444 | return -ENODEV; | |
4445 | } | |
4446 | } | |
4447 | ||
4448 | wldev = kzalloc(sizeof(*wldev), GFP_KERNEL); | |
4449 | if (!wldev) | |
4450 | goto out; | |
4451 | ||
4452 | wldev->dev = dev; | |
4453 | wldev->wl = wl; | |
4454 | b43_set_status(wldev, B43_STAT_UNINIT); | |
4455 | wldev->bad_frames_preempt = modparam_bad_frames_preempt; | |
4456 | tasklet_init(&wldev->isr_tasklet, | |
4457 | (void (*)(unsigned long))b43_interrupt_tasklet, | |
4458 | (unsigned long)wldev); | |
e4d6b795 MB |
4459 | INIT_LIST_HEAD(&wldev->list); |
4460 | ||
4461 | err = b43_wireless_core_attach(wldev); | |
4462 | if (err) | |
4463 | goto err_kfree_wldev; | |
4464 | ||
4465 | list_add(&wldev->list, &wl->devlist); | |
4466 | wl->nr_devs++; | |
4467 | ssb_set_drvdata(dev, wldev); | |
4468 | b43_debugfs_add_device(wldev); | |
4469 | ||
4470 | out: | |
4471 | return err; | |
4472 | ||
4473 | err_kfree_wldev: | |
4474 | kfree(wldev); | |
4475 | return err; | |
4476 | } | |
4477 | ||
9fc38458 MB |
4478 | #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \ |
4479 | (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \ | |
4480 | (pdev->device == _device) && \ | |
4481 | (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \ | |
4482 | (pdev->subsystem_device == _subdevice) ) | |
4483 | ||
e4d6b795 MB |
4484 | static void b43_sprom_fixup(struct ssb_bus *bus) |
4485 | { | |
1855ba78 MB |
4486 | struct pci_dev *pdev; |
4487 | ||
e4d6b795 MB |
4488 | /* boardflags workarounds */ |
4489 | if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL && | |
4490 | bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74) | |
95de2841 | 4491 | bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST; |
e4d6b795 MB |
4492 | if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && |
4493 | bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40) | |
95de2841 | 4494 | bus->sprom.boardflags_lo |= B43_BFL_PACTRL; |
1855ba78 MB |
4495 | if (bus->bustype == SSB_BUSTYPE_PCI) { |
4496 | pdev = bus->host_pci; | |
9fc38458 MB |
4497 | if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) || |
4498 | IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) || | |
4499 | IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013)) | |
1855ba78 MB |
4500 | bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST; |
4501 | } | |
e4d6b795 MB |
4502 | } |
4503 | ||
4504 | static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl) | |
4505 | { | |
4506 | struct ieee80211_hw *hw = wl->hw; | |
4507 | ||
4508 | ssb_set_devtypedata(dev, NULL); | |
4509 | ieee80211_free_hw(hw); | |
4510 | } | |
4511 | ||
4512 | static int b43_wireless_init(struct ssb_device *dev) | |
4513 | { | |
4514 | struct ssb_sprom *sprom = &dev->bus->sprom; | |
4515 | struct ieee80211_hw *hw; | |
4516 | struct b43_wl *wl; | |
4517 | int err = -ENOMEM; | |
4518 | ||
4519 | b43_sprom_fixup(dev->bus); | |
4520 | ||
4521 | hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops); | |
4522 | if (!hw) { | |
4523 | b43err(NULL, "Could not allocate ieee80211 device\n"); | |
4524 | goto out; | |
4525 | } | |
4526 | ||
4527 | /* fill hw info */ | |
d8be11ee JB |
4528 | hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE | |
4529 | IEEE80211_HW_RX_INCLUDES_FCS; | |
e4d6b795 MB |
4530 | hw->max_signal = 100; |
4531 | hw->max_rssi = -110; | |
4532 | hw->max_noise = -110; | |
e6f5b934 | 4533 | hw->queues = b43_modparam_qos ? 4 : 1; |
e4d6b795 | 4534 | SET_IEEE80211_DEV(hw, dev->dev); |
95de2841 LF |
4535 | if (is_valid_ether_addr(sprom->et1mac)) |
4536 | SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac); | |
e4d6b795 | 4537 | else |
95de2841 | 4538 | SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac); |
e4d6b795 MB |
4539 | |
4540 | /* Get and initialize struct b43_wl */ | |
4541 | wl = hw_to_b43_wl(hw); | |
4542 | memset(wl, 0, sizeof(*wl)); | |
4543 | wl->hw = hw; | |
4544 | spin_lock_init(&wl->irq_lock); | |
21a75d77 | 4545 | rwlock_init(&wl->tx_lock); |
e4d6b795 | 4546 | spin_lock_init(&wl->leds_lock); |
280d0e16 | 4547 | spin_lock_init(&wl->shm_lock); |
e4d6b795 MB |
4548 | mutex_init(&wl->mutex); |
4549 | INIT_LIST_HEAD(&wl->devlist); | |
e6f5b934 | 4550 | INIT_WORK(&wl->qos_update_work, b43_qos_update_work); |
a82d9922 | 4551 | INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work); |
e4d6b795 MB |
4552 | |
4553 | ssb_set_devtypedata(dev, wl); | |
4554 | b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id); | |
4555 | err = 0; | |
4556 | out: | |
4557 | return err; | |
4558 | } | |
4559 | ||
4560 | static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id) | |
4561 | { | |
4562 | struct b43_wl *wl; | |
4563 | int err; | |
4564 | int first = 0; | |
4565 | ||
4566 | wl = ssb_get_devtypedata(dev); | |
4567 | if (!wl) { | |
4568 | /* Probing the first core. Must setup common struct b43_wl */ | |
4569 | first = 1; | |
4570 | err = b43_wireless_init(dev); | |
4571 | if (err) | |
4572 | goto out; | |
4573 | wl = ssb_get_devtypedata(dev); | |
4574 | B43_WARN_ON(!wl); | |
4575 | } | |
4576 | err = b43_one_core_attach(dev, wl); | |
4577 | if (err) | |
4578 | goto err_wireless_exit; | |
4579 | ||
4580 | if (first) { | |
4581 | err = ieee80211_register_hw(wl->hw); | |
4582 | if (err) | |
4583 | goto err_one_core_detach; | |
4584 | } | |
4585 | ||
4586 | out: | |
4587 | return err; | |
4588 | ||
4589 | err_one_core_detach: | |
4590 | b43_one_core_detach(dev); | |
4591 | err_wireless_exit: | |
4592 | if (first) | |
4593 | b43_wireless_exit(dev, wl); | |
4594 | return err; | |
4595 | } | |
4596 | ||
4597 | static void b43_remove(struct ssb_device *dev) | |
4598 | { | |
4599 | struct b43_wl *wl = ssb_get_devtypedata(dev); | |
4600 | struct b43_wldev *wldev = ssb_get_drvdata(dev); | |
4601 | ||
4602 | B43_WARN_ON(!wl); | |
4603 | if (wl->current_dev == wldev) | |
4604 | ieee80211_unregister_hw(wl->hw); | |
4605 | ||
4606 | b43_one_core_detach(dev); | |
4607 | ||
4608 | if (list_empty(&wl->devlist)) { | |
4609 | /* Last core on the chip unregistered. | |
4610 | * We can destroy common struct b43_wl. | |
4611 | */ | |
4612 | b43_wireless_exit(dev, wl); | |
4613 | } | |
4614 | } | |
4615 | ||
4616 | /* Perform a hardware reset. This can be called from any context. */ | |
4617 | void b43_controller_restart(struct b43_wldev *dev, const char *reason) | |
4618 | { | |
4619 | /* Must avoid requeueing, if we are in shutdown. */ | |
4620 | if (b43_status(dev) < B43_STAT_INITIALIZED) | |
4621 | return; | |
4622 | b43info(dev->wl, "Controller RESET (%s) ...\n", reason); | |
4623 | queue_work(dev->wl->hw->workqueue, &dev->restart_work); | |
4624 | } | |
4625 | ||
4626 | #ifdef CONFIG_PM | |
4627 | ||
4628 | static int b43_suspend(struct ssb_device *dev, pm_message_t state) | |
4629 | { | |
4630 | struct b43_wldev *wldev = ssb_get_drvdata(dev); | |
4631 | struct b43_wl *wl = wldev->wl; | |
4632 | ||
4633 | b43dbg(wl, "Suspending...\n"); | |
4634 | ||
4635 | mutex_lock(&wl->mutex); | |
3506e0c4 | 4636 | wldev->suspend_in_progress = true; |
e4d6b795 MB |
4637 | wldev->suspend_init_status = b43_status(wldev); |
4638 | if (wldev->suspend_init_status >= B43_STAT_STARTED) | |
4639 | b43_wireless_core_stop(wldev); | |
4640 | if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) | |
4641 | b43_wireless_core_exit(wldev); | |
4642 | mutex_unlock(&wl->mutex); | |
4643 | ||
4644 | b43dbg(wl, "Device suspended.\n"); | |
4645 | ||
4646 | return 0; | |
4647 | } | |
4648 | ||
4649 | static int b43_resume(struct ssb_device *dev) | |
4650 | { | |
4651 | struct b43_wldev *wldev = ssb_get_drvdata(dev); | |
4652 | struct b43_wl *wl = wldev->wl; | |
4653 | int err = 0; | |
4654 | ||
4655 | b43dbg(wl, "Resuming...\n"); | |
4656 | ||
4657 | mutex_lock(&wl->mutex); | |
4658 | if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) { | |
4659 | err = b43_wireless_core_init(wldev); | |
4660 | if (err) { | |
4661 | b43err(wl, "Resume failed at core init\n"); | |
4662 | goto out; | |
4663 | } | |
4664 | } | |
4665 | if (wldev->suspend_init_status >= B43_STAT_STARTED) { | |
4666 | err = b43_wireless_core_start(wldev); | |
4667 | if (err) { | |
3506e0c4 | 4668 | b43_leds_exit(wldev); |
b844eba2 | 4669 | b43_rng_exit(wldev->wl); |
e4d6b795 MB |
4670 | b43_wireless_core_exit(wldev); |
4671 | b43err(wl, "Resume failed at core start\n"); | |
4672 | goto out; | |
4673 | } | |
4674 | } | |
e4d6b795 | 4675 | b43dbg(wl, "Device resumed.\n"); |
3506e0c4 RW |
4676 | out: |
4677 | wldev->suspend_in_progress = false; | |
4678 | mutex_unlock(&wl->mutex); | |
e4d6b795 MB |
4679 | return err; |
4680 | } | |
4681 | ||
4682 | #else /* CONFIG_PM */ | |
4683 | # define b43_suspend NULL | |
4684 | # define b43_resume NULL | |
4685 | #endif /* CONFIG_PM */ | |
4686 | ||
4687 | static struct ssb_driver b43_ssb_driver = { | |
4688 | .name = KBUILD_MODNAME, | |
4689 | .id_table = b43_ssb_tbl, | |
4690 | .probe = b43_probe, | |
4691 | .remove = b43_remove, | |
4692 | .suspend = b43_suspend, | |
4693 | .resume = b43_resume, | |
4694 | }; | |
4695 | ||
26bc783f MB |
4696 | static void b43_print_driverinfo(void) |
4697 | { | |
4698 | const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "", | |
4699 | *feat_leds = "", *feat_rfkill = ""; | |
4700 | ||
4701 | #ifdef CONFIG_B43_PCI_AUTOSELECT | |
4702 | feat_pci = "P"; | |
4703 | #endif | |
4704 | #ifdef CONFIG_B43_PCMCIA | |
4705 | feat_pcmcia = "M"; | |
4706 | #endif | |
4707 | #ifdef CONFIG_B43_NPHY | |
4708 | feat_nphy = "N"; | |
4709 | #endif | |
4710 | #ifdef CONFIG_B43_LEDS | |
4711 | feat_leds = "L"; | |
4712 | #endif | |
4713 | #ifdef CONFIG_B43_RFKILL | |
4714 | feat_rfkill = "R"; | |
4715 | #endif | |
4716 | printk(KERN_INFO "Broadcom 43xx driver loaded " | |
4717 | "[ Features: %s%s%s%s%s, Firmware-ID: " | |
4718 | B43_SUPPORTED_FIRMWARE_ID " ]\n", | |
4719 | feat_pci, feat_pcmcia, feat_nphy, | |
4720 | feat_leds, feat_rfkill); | |
4721 | } | |
4722 | ||
e4d6b795 MB |
4723 | static int __init b43_init(void) |
4724 | { | |
4725 | int err; | |
4726 | ||
4727 | b43_debugfs_init(); | |
4728 | err = b43_pcmcia_init(); | |
4729 | if (err) | |
4730 | goto err_dfs_exit; | |
4731 | err = ssb_driver_register(&b43_ssb_driver); | |
4732 | if (err) | |
4733 | goto err_pcmcia_exit; | |
26bc783f | 4734 | b43_print_driverinfo(); |
e4d6b795 MB |
4735 | |
4736 | return err; | |
4737 | ||
4738 | err_pcmcia_exit: | |
4739 | b43_pcmcia_exit(); | |
4740 | err_dfs_exit: | |
4741 | b43_debugfs_exit(); | |
4742 | return err; | |
4743 | } | |
4744 | ||
4745 | static void __exit b43_exit(void) | |
4746 | { | |
4747 | ssb_driver_unregister(&b43_ssb_driver); | |
4748 | b43_pcmcia_exit(); | |
4749 | b43_debugfs_exit(); | |
4750 | } | |
4751 | ||
4752 | module_init(b43_init) | |
4753 | module_exit(b43_exit) |