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b43: Implement dynamic PHY API
[deliverable/linux.git] / drivers / net / wireless / b43 / phy_g.c
CommitLineData
ef1a628d
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11g PHY driver
5
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
26
27*/
28
29#include "b43.h"
30#include "phy_g.h"
31#include "phy_common.h"
32#include "lo.h"
33#include "main.h"
34
35#include <linux/bitrev.h>
36
37
38static const s8 b43_tssi2dbm_g_table[] = {
39 77, 77, 77, 76,
40 76, 76, 75, 75,
41 74, 74, 73, 73,
42 73, 72, 72, 71,
43 71, 70, 70, 69,
44 68, 68, 67, 67,
45 66, 65, 65, 64,
46 63, 63, 62, 61,
47 60, 59, 58, 57,
48 56, 55, 54, 53,
49 52, 50, 49, 47,
50 45, 43, 40, 37,
51 33, 28, 22, 14,
52 5, -7, -20, -20,
53 -20, -20, -20, -20,
54 -20, -20, -20, -20,
55};
56
57const u8 b43_radio_channel_codes_bg[] = {
58 12, 17, 22, 27,
59 32, 37, 42, 47,
60 52, 57, 62, 67,
61 72, 84,
62};
63
64
65static void b43_calc_nrssi_threshold(struct b43_wldev *dev);
66
67
68#define bitrev4(tmp) (bitrev8(tmp) >> 4)
69
70
71/* Get the freq, as it has to be written to the device. */
72static inline u16 channel2freq_bg(u8 channel)
73{
74 B43_WARN_ON(!(channel >= 1 && channel <= 14));
75
76 return b43_radio_channel_codes_bg[channel - 1];
77}
78
79static void generate_rfatt_list(struct b43_wldev *dev,
80 struct b43_rfatt_list *list)
81{
82 struct b43_phy *phy = &dev->phy;
83
84 /* APHY.rev < 5 || GPHY.rev < 6 */
85 static const struct b43_rfatt rfatt_0[] = {
86 {.att = 3,.with_padmix = 0,},
87 {.att = 1,.with_padmix = 0,},
88 {.att = 5,.with_padmix = 0,},
89 {.att = 7,.with_padmix = 0,},
90 {.att = 9,.with_padmix = 0,},
91 {.att = 2,.with_padmix = 0,},
92 {.att = 0,.with_padmix = 0,},
93 {.att = 4,.with_padmix = 0,},
94 {.att = 6,.with_padmix = 0,},
95 {.att = 8,.with_padmix = 0,},
96 {.att = 1,.with_padmix = 1,},
97 {.att = 2,.with_padmix = 1,},
98 {.att = 3,.with_padmix = 1,},
99 {.att = 4,.with_padmix = 1,},
100 };
101 /* Radio.rev == 8 && Radio.version == 0x2050 */
102 static const struct b43_rfatt rfatt_1[] = {
103 {.att = 2,.with_padmix = 1,},
104 {.att = 4,.with_padmix = 1,},
105 {.att = 6,.with_padmix = 1,},
106 {.att = 8,.with_padmix = 1,},
107 {.att = 10,.with_padmix = 1,},
108 {.att = 12,.with_padmix = 1,},
109 {.att = 14,.with_padmix = 1,},
110 };
111 /* Otherwise */
112 static const struct b43_rfatt rfatt_2[] = {
113 {.att = 0,.with_padmix = 1,},
114 {.att = 2,.with_padmix = 1,},
115 {.att = 4,.with_padmix = 1,},
116 {.att = 6,.with_padmix = 1,},
117 {.att = 8,.with_padmix = 1,},
118 {.att = 9,.with_padmix = 1,},
119 {.att = 9,.with_padmix = 1,},
120 };
121
122 if (!b43_has_hardware_pctl(dev)) {
123 /* Software pctl */
124 list->list = rfatt_0;
125 list->len = ARRAY_SIZE(rfatt_0);
126 list->min_val = 0;
127 list->max_val = 9;
128 return;
129 }
130 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
131 /* Hardware pctl */
132 list->list = rfatt_1;
133 list->len = ARRAY_SIZE(rfatt_1);
134 list->min_val = 0;
135 list->max_val = 14;
136 return;
137 }
138 /* Hardware pctl */
139 list->list = rfatt_2;
140 list->len = ARRAY_SIZE(rfatt_2);
141 list->min_val = 0;
142 list->max_val = 9;
143}
144
145static void generate_bbatt_list(struct b43_wldev *dev,
146 struct b43_bbatt_list *list)
147{
148 static const struct b43_bbatt bbatt_0[] = {
149 {.att = 0,},
150 {.att = 1,},
151 {.att = 2,},
152 {.att = 3,},
153 {.att = 4,},
154 {.att = 5,},
155 {.att = 6,},
156 {.att = 7,},
157 {.att = 8,},
158 };
159
160 list->list = bbatt_0;
161 list->len = ARRAY_SIZE(bbatt_0);
162 list->min_val = 0;
163 list->max_val = 8;
164}
165
166static void b43_shm_clear_tssi(struct b43_wldev *dev)
167{
168 b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
169 b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
170 b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
171 b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
172}
173
174/* Synthetic PU workaround */
175static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
176{
177 struct b43_phy *phy = &dev->phy;
178
179 might_sleep();
180
181 if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
182 /* We do not need the workaround. */
183 return;
184 }
185
186 if (channel <= 10) {
187 b43_write16(dev, B43_MMIO_CHANNEL,
188 channel2freq_bg(channel + 4));
189 } else {
190 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
191 }
192 msleep(1);
193 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
194}
195
196/* Set the baseband attenuation value on chip. */
197void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev,
198 u16 baseband_attenuation)
199{
200 struct b43_phy *phy = &dev->phy;
201
202 if (phy->analog == 0) {
203 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
204 & 0xFFF0) |
205 baseband_attenuation);
206 } else if (phy->analog > 1) {
207 b43_phy_write(dev, B43_PHY_DACCTL,
208 (b43_phy_read(dev, B43_PHY_DACCTL)
209 & 0xFFC3) | (baseband_attenuation << 2));
210 } else {
211 b43_phy_write(dev, B43_PHY_DACCTL,
212 (b43_phy_read(dev, B43_PHY_DACCTL)
213 & 0xFF87) | (baseband_attenuation << 3));
214 }
215}
216
217/* Adjust the transmission power output (G-PHY) */
218void b43_set_txpower_g(struct b43_wldev *dev,
219 const struct b43_bbatt *bbatt,
220 const struct b43_rfatt *rfatt, u8 tx_control)
221{
222 struct b43_phy *phy = &dev->phy;
223 struct b43_phy_g *gphy = phy->g;
224 struct b43_txpower_lo_control *lo = gphy->lo_control;
225 u16 bb, rf;
226 u16 tx_bias, tx_magn;
227
228 bb = bbatt->att;
229 rf = rfatt->att;
230 tx_bias = lo->tx_bias;
231 tx_magn = lo->tx_magn;
232 if (unlikely(tx_bias == 0xFF))
233 tx_bias = 0;
234
235 /* Save the values for later */
236 gphy->tx_control = tx_control;
237 memcpy(&gphy->rfatt, rfatt, sizeof(*rfatt));
238 gphy->rfatt.with_padmix = !!(tx_control & B43_TXCTL_TXMIX);
239 memcpy(&gphy->bbatt, bbatt, sizeof(*bbatt));
240
241 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
242 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
243 "rfatt(%u), tx_control(0x%02X), "
244 "tx_bias(0x%02X), tx_magn(0x%02X)\n",
245 bb, rf, tx_control, tx_bias, tx_magn);
246 }
247
248 b43_gphy_set_baseband_attenuation(dev, bb);
249 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
250 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
251 b43_radio_write16(dev, 0x43,
252 (rf & 0x000F) | (tx_control & 0x0070));
253 } else {
254 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
255 & 0xFFF0) | (rf & 0x000F));
256 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
257 & ~0x0070) | (tx_control &
258 0x0070));
259 }
260 if (has_tx_magnification(phy)) {
261 b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
262 } else {
263 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
264 & 0xFFF0) | (tx_bias & 0x000F));
265 }
266 b43_lo_g_adjust(dev);
267}
268
269/* GPHY_TSSI_Power_Lookup_Table_Init */
270static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
271{
272 struct b43_phy_g *gphy = dev->phy.g;
273 int i;
274 u16 value;
275
276 for (i = 0; i < 32; i++)
277 b43_ofdmtab_write16(dev, 0x3C20, i, gphy->tssi2dbm[i]);
278 for (i = 32; i < 64; i++)
279 b43_ofdmtab_write16(dev, 0x3C00, i - 32, gphy->tssi2dbm[i]);
280 for (i = 0; i < 64; i += 2) {
281 value = (u16) gphy->tssi2dbm[i];
282 value |= ((u16) gphy->tssi2dbm[i + 1]) << 8;
283 b43_phy_write(dev, 0x380 + (i / 2), value);
284 }
285}
286
287/* GPHY_Gain_Lookup_Table_Init */
288static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
289{
290 struct b43_phy *phy = &dev->phy;
291 struct b43_phy_g *gphy = phy->g;
292 struct b43_txpower_lo_control *lo = gphy->lo_control;
293 u16 nr_written = 0;
294 u16 tmp;
295 u8 rf, bb;
296
297 for (rf = 0; rf < lo->rfatt_list.len; rf++) {
298 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
299 if (nr_written >= 0x40)
300 return;
301 tmp = lo->bbatt_list.list[bb].att;
302 tmp <<= 8;
303 if (phy->radio_rev == 8)
304 tmp |= 0x50;
305 else
306 tmp |= 0x40;
307 tmp |= lo->rfatt_list.list[rf].att;
308 b43_phy_write(dev, 0x3C0 + nr_written, tmp);
309 nr_written++;
310 }
311 }
312}
313
314static void b43_set_all_gains(struct b43_wldev *dev,
315 s16 first, s16 second, s16 third)
316{
317 struct b43_phy *phy = &dev->phy;
318 u16 i;
319 u16 start = 0x08, end = 0x18;
320 u16 tmp;
321 u16 table;
322
323 if (phy->rev <= 1) {
324 start = 0x10;
325 end = 0x20;
326 }
327
328 table = B43_OFDMTAB_GAINX;
329 if (phy->rev <= 1)
330 table = B43_OFDMTAB_GAINX_R1;
331 for (i = 0; i < 4; i++)
332 b43_ofdmtab_write16(dev, table, i, first);
333
334 for (i = start; i < end; i++)
335 b43_ofdmtab_write16(dev, table, i, second);
336
337 if (third != -1) {
338 tmp = ((u16) third << 14) | ((u16) third << 6);
339 b43_phy_write(dev, 0x04A0,
340 (b43_phy_read(dev, 0x04A0) & 0xBFBF) | tmp);
341 b43_phy_write(dev, 0x04A1,
342 (b43_phy_read(dev, 0x04A1) & 0xBFBF) | tmp);
343 b43_phy_write(dev, 0x04A2,
344 (b43_phy_read(dev, 0x04A2) & 0xBFBF) | tmp);
345 }
346 b43_dummy_transmission(dev);
347}
348
349static void b43_set_original_gains(struct b43_wldev *dev)
350{
351 struct b43_phy *phy = &dev->phy;
352 u16 i, tmp;
353 u16 table;
354 u16 start = 0x0008, end = 0x0018;
355
356 if (phy->rev <= 1) {
357 start = 0x0010;
358 end = 0x0020;
359 }
360
361 table = B43_OFDMTAB_GAINX;
362 if (phy->rev <= 1)
363 table = B43_OFDMTAB_GAINX_R1;
364 for (i = 0; i < 4; i++) {
365 tmp = (i & 0xFFFC);
366 tmp |= (i & 0x0001) << 1;
367 tmp |= (i & 0x0002) >> 1;
368
369 b43_ofdmtab_write16(dev, table, i, tmp);
370 }
371
372 for (i = start; i < end; i++)
373 b43_ofdmtab_write16(dev, table, i, i - start);
374
375 b43_phy_write(dev, 0x04A0,
376 (b43_phy_read(dev, 0x04A0) & 0xBFBF) | 0x4040);
377 b43_phy_write(dev, 0x04A1,
378 (b43_phy_read(dev, 0x04A1) & 0xBFBF) | 0x4040);
379 b43_phy_write(dev, 0x04A2,
380 (b43_phy_read(dev, 0x04A2) & 0xBFBF) | 0x4000);
381 b43_dummy_transmission(dev);
382}
383
384/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
385void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
386{
387 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
388 mmiowb();
389 b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
390}
391
392/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
393s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
394{
395 u16 val;
396
397 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
398 val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
399
400 return (s16) val;
401}
402
403/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
404void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
405{
406 u16 i;
407 s16 tmp;
408
409 for (i = 0; i < 64; i++) {
410 tmp = b43_nrssi_hw_read(dev, i);
411 tmp -= val;
412 tmp = clamp_val(tmp, -32, 31);
413 b43_nrssi_hw_write(dev, i, tmp);
414 }
415}
416
417/* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
418void b43_nrssi_mem_update(struct b43_wldev *dev)
419{
420 struct b43_phy_g *gphy = dev->phy.g;
421 s16 i, delta;
422 s32 tmp;
423
424 delta = 0x1F - gphy->nrssi[0];
425 for (i = 0; i < 64; i++) {
426 tmp = (i - delta) * gphy->nrssislope;
427 tmp /= 0x10000;
428 tmp += 0x3A;
429 tmp = clamp_val(tmp, 0, 0x3F);
430 gphy->nrssi_lt[i] = tmp;
431 }
432}
433
434static void b43_calc_nrssi_offset(struct b43_wldev *dev)
435{
436 struct b43_phy *phy = &dev->phy;
437 u16 backup[20] = { 0 };
438 s16 v47F;
439 u16 i;
440 u16 saved = 0xFFFF;
441
442 backup[0] = b43_phy_read(dev, 0x0001);
443 backup[1] = b43_phy_read(dev, 0x0811);
444 backup[2] = b43_phy_read(dev, 0x0812);
445 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
446 backup[3] = b43_phy_read(dev, 0x0814);
447 backup[4] = b43_phy_read(dev, 0x0815);
448 }
449 backup[5] = b43_phy_read(dev, 0x005A);
450 backup[6] = b43_phy_read(dev, 0x0059);
451 backup[7] = b43_phy_read(dev, 0x0058);
452 backup[8] = b43_phy_read(dev, 0x000A);
453 backup[9] = b43_phy_read(dev, 0x0003);
454 backup[10] = b43_radio_read16(dev, 0x007A);
455 backup[11] = b43_radio_read16(dev, 0x0043);
456
457 b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) & 0x7FFF);
458 b43_phy_write(dev, 0x0001,
459 (b43_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
460 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
461 b43_phy_write(dev, 0x0812,
462 (b43_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
463 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & ~(0x1 | 0x2));
464 if (phy->rev >= 6) {
465 backup[12] = b43_phy_read(dev, 0x002E);
466 backup[13] = b43_phy_read(dev, 0x002F);
467 backup[14] = b43_phy_read(dev, 0x080F);
468 backup[15] = b43_phy_read(dev, 0x0810);
469 backup[16] = b43_phy_read(dev, 0x0801);
470 backup[17] = b43_phy_read(dev, 0x0060);
471 backup[18] = b43_phy_read(dev, 0x0014);
472 backup[19] = b43_phy_read(dev, 0x0478);
473
474 b43_phy_write(dev, 0x002E, 0);
475 b43_phy_write(dev, 0x002F, 0);
476 b43_phy_write(dev, 0x080F, 0);
477 b43_phy_write(dev, 0x0810, 0);
478 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478) | 0x0100);
479 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801) | 0x0040);
480 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) | 0x0040);
481 b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014) | 0x0200);
482 }
483 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0070);
484 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0080);
485 udelay(30);
486
487 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
488 if (v47F >= 0x20)
489 v47F -= 0x40;
490 if (v47F == 31) {
491 for (i = 7; i >= 4; i--) {
492 b43_radio_write16(dev, 0x007B, i);
493 udelay(20);
494 v47F =
495 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
496 if (v47F >= 0x20)
497 v47F -= 0x40;
498 if (v47F < 31 && saved == 0xFFFF)
499 saved = i;
500 }
501 if (saved == 0xFFFF)
502 saved = 4;
503 } else {
504 b43_radio_write16(dev, 0x007A,
505 b43_radio_read16(dev, 0x007A) & 0x007F);
506 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
507 b43_phy_write(dev, 0x0814,
508 b43_phy_read(dev, 0x0814) | 0x0001);
509 b43_phy_write(dev, 0x0815,
510 b43_phy_read(dev, 0x0815) & 0xFFFE);
511 }
512 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
513 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x000C);
514 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x0030);
515 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x0030);
516 b43_phy_write(dev, 0x005A, 0x0480);
517 b43_phy_write(dev, 0x0059, 0x0810);
518 b43_phy_write(dev, 0x0058, 0x000D);
519 if (phy->rev == 0) {
520 b43_phy_write(dev, 0x0003, 0x0122);
521 } else {
522 b43_phy_write(dev, 0x000A, b43_phy_read(dev, 0x000A)
523 | 0x2000);
524 }
525 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
526 b43_phy_write(dev, 0x0814,
527 b43_phy_read(dev, 0x0814) | 0x0004);
528 b43_phy_write(dev, 0x0815,
529 b43_phy_read(dev, 0x0815) & 0xFFFB);
530 }
531 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) & 0xFF9F)
532 | 0x0040);
533 b43_radio_write16(dev, 0x007A,
534 b43_radio_read16(dev, 0x007A) | 0x000F);
535 b43_set_all_gains(dev, 3, 0, 1);
536 b43_radio_write16(dev, 0x0043, (b43_radio_read16(dev, 0x0043)
537 & 0x00F0) | 0x000F);
538 udelay(30);
539 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
540 if (v47F >= 0x20)
541 v47F -= 0x40;
542 if (v47F == -32) {
543 for (i = 0; i < 4; i++) {
544 b43_radio_write16(dev, 0x007B, i);
545 udelay(20);
546 v47F =
547 (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
548 0x003F);
549 if (v47F >= 0x20)
550 v47F -= 0x40;
551 if (v47F > -31 && saved == 0xFFFF)
552 saved = i;
553 }
554 if (saved == 0xFFFF)
555 saved = 3;
556 } else
557 saved = 0;
558 }
559 b43_radio_write16(dev, 0x007B, saved);
560
561 if (phy->rev >= 6) {
562 b43_phy_write(dev, 0x002E, backup[12]);
563 b43_phy_write(dev, 0x002F, backup[13]);
564 b43_phy_write(dev, 0x080F, backup[14]);
565 b43_phy_write(dev, 0x0810, backup[15]);
566 }
567 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
568 b43_phy_write(dev, 0x0814, backup[3]);
569 b43_phy_write(dev, 0x0815, backup[4]);
570 }
571 b43_phy_write(dev, 0x005A, backup[5]);
572 b43_phy_write(dev, 0x0059, backup[6]);
573 b43_phy_write(dev, 0x0058, backup[7]);
574 b43_phy_write(dev, 0x000A, backup[8]);
575 b43_phy_write(dev, 0x0003, backup[9]);
576 b43_radio_write16(dev, 0x0043, backup[11]);
577 b43_radio_write16(dev, 0x007A, backup[10]);
578 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
579 b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) | 0x8000);
580 b43_set_original_gains(dev);
581 if (phy->rev >= 6) {
582 b43_phy_write(dev, 0x0801, backup[16]);
583 b43_phy_write(dev, 0x0060, backup[17]);
584 b43_phy_write(dev, 0x0014, backup[18]);
585 b43_phy_write(dev, 0x0478, backup[19]);
586 }
587 b43_phy_write(dev, 0x0001, backup[0]);
588 b43_phy_write(dev, 0x0812, backup[2]);
589 b43_phy_write(dev, 0x0811, backup[1]);
590}
591
592void b43_calc_nrssi_slope(struct b43_wldev *dev)
593{
594 struct b43_phy *phy = &dev->phy;
595 struct b43_phy_g *gphy = phy->g;
596 u16 backup[18] = { 0 };
597 u16 tmp;
598 s16 nrssi0, nrssi1;
599
600 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
601
602 if (phy->radio_rev >= 9)
603 return;
604 if (phy->radio_rev == 8)
605 b43_calc_nrssi_offset(dev);
606
607 b43_phy_write(dev, B43_PHY_G_CRS,
608 b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
609 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
610 backup[7] = b43_read16(dev, 0x03E2);
611 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
612 backup[0] = b43_radio_read16(dev, 0x007A);
613 backup[1] = b43_radio_read16(dev, 0x0052);
614 backup[2] = b43_radio_read16(dev, 0x0043);
615 backup[3] = b43_phy_read(dev, 0x0015);
616 backup[4] = b43_phy_read(dev, 0x005A);
617 backup[5] = b43_phy_read(dev, 0x0059);
618 backup[6] = b43_phy_read(dev, 0x0058);
619 backup[8] = b43_read16(dev, 0x03E6);
620 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
621 if (phy->rev >= 3) {
622 backup[10] = b43_phy_read(dev, 0x002E);
623 backup[11] = b43_phy_read(dev, 0x002F);
624 backup[12] = b43_phy_read(dev, 0x080F);
625 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
626 backup[14] = b43_phy_read(dev, 0x0801);
627 backup[15] = b43_phy_read(dev, 0x0060);
628 backup[16] = b43_phy_read(dev, 0x0014);
629 backup[17] = b43_phy_read(dev, 0x0478);
630 b43_phy_write(dev, 0x002E, 0);
631 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
632 switch (phy->rev) {
633 case 4:
634 case 6:
635 case 7:
636 b43_phy_write(dev, 0x0478,
637 b43_phy_read(dev, 0x0478)
638 | 0x0100);
639 b43_phy_write(dev, 0x0801,
640 b43_phy_read(dev, 0x0801)
641 | 0x0040);
642 break;
643 case 3:
644 case 5:
645 b43_phy_write(dev, 0x0801,
646 b43_phy_read(dev, 0x0801)
647 & 0xFFBF);
648 break;
649 }
650 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060)
651 | 0x0040);
652 b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014)
653 | 0x0200);
654 }
655 b43_radio_write16(dev, 0x007A,
656 b43_radio_read16(dev, 0x007A) | 0x0070);
657 b43_set_all_gains(dev, 0, 8, 0);
658 b43_radio_write16(dev, 0x007A,
659 b43_radio_read16(dev, 0x007A) & 0x00F7);
660 if (phy->rev >= 2) {
661 b43_phy_write(dev, 0x0811,
662 (b43_phy_read(dev, 0x0811) & 0xFFCF) |
663 0x0030);
664 b43_phy_write(dev, 0x0812,
665 (b43_phy_read(dev, 0x0812) & 0xFFCF) |
666 0x0010);
667 }
668 b43_radio_write16(dev, 0x007A,
669 b43_radio_read16(dev, 0x007A) | 0x0080);
670 udelay(20);
671
672 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
673 if (nrssi0 >= 0x0020)
674 nrssi0 -= 0x0040;
675
676 b43_radio_write16(dev, 0x007A,
677 b43_radio_read16(dev, 0x007A) & 0x007F);
678 if (phy->rev >= 2) {
679 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003)
680 & 0xFF9F) | 0x0040);
681 }
682
683 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
684 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
685 | 0x2000);
686 b43_radio_write16(dev, 0x007A,
687 b43_radio_read16(dev, 0x007A) | 0x000F);
688 b43_phy_write(dev, 0x0015, 0xF330);
689 if (phy->rev >= 2) {
690 b43_phy_write(dev, 0x0812,
691 (b43_phy_read(dev, 0x0812) & 0xFFCF) |
692 0x0020);
693 b43_phy_write(dev, 0x0811,
694 (b43_phy_read(dev, 0x0811) & 0xFFCF) |
695 0x0020);
696 }
697
698 b43_set_all_gains(dev, 3, 0, 1);
699 if (phy->radio_rev == 8) {
700 b43_radio_write16(dev, 0x0043, 0x001F);
701 } else {
702 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
703 b43_radio_write16(dev, 0x0052, tmp | 0x0060);
704 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
705 b43_radio_write16(dev, 0x0043, tmp | 0x0009);
706 }
707 b43_phy_write(dev, 0x005A, 0x0480);
708 b43_phy_write(dev, 0x0059, 0x0810);
709 b43_phy_write(dev, 0x0058, 0x000D);
710 udelay(20);
711 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
712 if (nrssi1 >= 0x0020)
713 nrssi1 -= 0x0040;
714 if (nrssi0 == nrssi1)
715 gphy->nrssislope = 0x00010000;
716 else
717 gphy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
718 if (nrssi0 >= -4) {
719 gphy->nrssi[0] = nrssi1;
720 gphy->nrssi[1] = nrssi0;
721 }
722 if (phy->rev >= 3) {
723 b43_phy_write(dev, 0x002E, backup[10]);
724 b43_phy_write(dev, 0x002F, backup[11]);
725 b43_phy_write(dev, 0x080F, backup[12]);
726 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
727 }
728 if (phy->rev >= 2) {
729 b43_phy_write(dev, 0x0812,
730 b43_phy_read(dev, 0x0812) & 0xFFCF);
731 b43_phy_write(dev, 0x0811,
732 b43_phy_read(dev, 0x0811) & 0xFFCF);
733 }
734
735 b43_radio_write16(dev, 0x007A, backup[0]);
736 b43_radio_write16(dev, 0x0052, backup[1]);
737 b43_radio_write16(dev, 0x0043, backup[2]);
738 b43_write16(dev, 0x03E2, backup[7]);
739 b43_write16(dev, 0x03E6, backup[8]);
740 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
741 b43_phy_write(dev, 0x0015, backup[3]);
742 b43_phy_write(dev, 0x005A, backup[4]);
743 b43_phy_write(dev, 0x0059, backup[5]);
744 b43_phy_write(dev, 0x0058, backup[6]);
745 b43_synth_pu_workaround(dev, phy->channel);
746 b43_phy_write(dev, 0x0802,
747 b43_phy_read(dev, 0x0802) | (0x0001 | 0x0002));
748 b43_set_original_gains(dev);
749 b43_phy_write(dev, B43_PHY_G_CRS,
750 b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
751 if (phy->rev >= 3) {
752 b43_phy_write(dev, 0x0801, backup[14]);
753 b43_phy_write(dev, 0x0060, backup[15]);
754 b43_phy_write(dev, 0x0014, backup[16]);
755 b43_phy_write(dev, 0x0478, backup[17]);
756 }
757 b43_nrssi_mem_update(dev);
758 b43_calc_nrssi_threshold(dev);
759}
760
761static void b43_calc_nrssi_threshold(struct b43_wldev *dev)
762{
763 struct b43_phy *phy = &dev->phy;
764 struct b43_phy_g *gphy = phy->g;
765 s32 a, b;
766 s16 tmp16;
767 u16 tmp_u16;
768
769 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
770
771 if (!phy->gmode ||
772 !(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
773 tmp16 = b43_nrssi_hw_read(dev, 0x20);
774 if (tmp16 >= 0x20)
775 tmp16 -= 0x40;
776 if (tmp16 < 3) {
777 b43_phy_write(dev, 0x048A,
778 (b43_phy_read(dev, 0x048A)
779 & 0xF000) | 0x09EB);
780 } else {
781 b43_phy_write(dev, 0x048A,
782 (b43_phy_read(dev, 0x048A)
783 & 0xF000) | 0x0AED);
784 }
785 } else {
786 if (gphy->interfmode == B43_INTERFMODE_NONWLAN) {
787 a = 0xE;
788 b = 0xA;
789 } else if (!gphy->aci_wlan_automatic && gphy->aci_enable) {
790 a = 0x13;
791 b = 0x12;
792 } else {
793 a = 0xE;
794 b = 0x11;
795 }
796
797 a = a * (gphy->nrssi[1] - gphy->nrssi[0]);
798 a += (gphy->nrssi[0] << 6);
799 if (a < 32)
800 a += 31;
801 else
802 a += 32;
803 a = a >> 6;
804 a = clamp_val(a, -31, 31);
805
806 b = b * (gphy->nrssi[1] - gphy->nrssi[0]);
807 b += (gphy->nrssi[0] << 6);
808 if (b < 32)
809 b += 31;
810 else
811 b += 32;
812 b = b >> 6;
813 b = clamp_val(b, -31, 31);
814
815 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
816 tmp_u16 |= ((u32) b & 0x0000003F);
817 tmp_u16 |= (((u32) a & 0x0000003F) << 6);
818 b43_phy_write(dev, 0x048A, tmp_u16);
819 }
820}
821
822/* Stack implementation to save/restore values from the
823 * interference mitigation code.
824 * It is save to restore values in random order.
825 */
826static void _stack_save(u32 * _stackptr, size_t * stackidx,
827 u8 id, u16 offset, u16 value)
828{
829 u32 *stackptr = &(_stackptr[*stackidx]);
830
831 B43_WARN_ON(offset & 0xF000);
832 B43_WARN_ON(id & 0xF0);
833 *stackptr = offset;
834 *stackptr |= ((u32) id) << 12;
835 *stackptr |= ((u32) value) << 16;
836 (*stackidx)++;
837 B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
838}
839
840static u16 _stack_restore(u32 * stackptr, u8 id, u16 offset)
841{
842 size_t i;
843
844 B43_WARN_ON(offset & 0xF000);
845 B43_WARN_ON(id & 0xF0);
846 for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
847 if ((*stackptr & 0x00000FFF) != offset)
848 continue;
849 if (((*stackptr & 0x0000F000) >> 12) != id)
850 continue;
851 return ((*stackptr & 0xFFFF0000) >> 16);
852 }
853 B43_WARN_ON(1);
854
855 return 0;
856}
857
858#define phy_stacksave(offset) \
859 do { \
860 _stack_save(stack, &stackidx, 0x1, (offset), \
861 b43_phy_read(dev, (offset))); \
862 } while (0)
863#define phy_stackrestore(offset) \
864 do { \
865 b43_phy_write(dev, (offset), \
866 _stack_restore(stack, 0x1, \
867 (offset))); \
868 } while (0)
869#define radio_stacksave(offset) \
870 do { \
871 _stack_save(stack, &stackidx, 0x2, (offset), \
872 b43_radio_read16(dev, (offset))); \
873 } while (0)
874#define radio_stackrestore(offset) \
875 do { \
876 b43_radio_write16(dev, (offset), \
877 _stack_restore(stack, 0x2, \
878 (offset))); \
879 } while (0)
880#define ofdmtab_stacksave(table, offset) \
881 do { \
882 _stack_save(stack, &stackidx, 0x3, (offset)|(table), \
883 b43_ofdmtab_read16(dev, (table), (offset))); \
884 } while (0)
885#define ofdmtab_stackrestore(table, offset) \
886 do { \
887 b43_ofdmtab_write16(dev, (table), (offset), \
888 _stack_restore(stack, 0x3, \
889 (offset)|(table))); \
890 } while (0)
891
892static void
893b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
894{
895 struct b43_phy *phy = &dev->phy;
896 struct b43_phy_g *gphy = phy->g;
897 u16 tmp, flipped;
898 size_t stackidx = 0;
899 u32 *stack = gphy->interfstack;
900
901 switch (mode) {
902 case B43_INTERFMODE_NONWLAN:
903 if (phy->rev != 1) {
904 b43_phy_write(dev, 0x042B,
905 b43_phy_read(dev, 0x042B) | 0x0800);
906 b43_phy_write(dev, B43_PHY_G_CRS,
907 b43_phy_read(dev,
908 B43_PHY_G_CRS) & ~0x4000);
909 break;
910 }
911 radio_stacksave(0x0078);
912 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
913 B43_WARN_ON(tmp > 15);
914 flipped = bitrev4(tmp);
915 if (flipped < 10 && flipped >= 8)
916 flipped = 7;
917 else if (flipped >= 10)
918 flipped -= 3;
919 flipped = (bitrev4(flipped) << 1) | 0x0020;
920 b43_radio_write16(dev, 0x0078, flipped);
921
922 b43_calc_nrssi_threshold(dev);
923
924 phy_stacksave(0x0406);
925 b43_phy_write(dev, 0x0406, 0x7E28);
926
927 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x0800);
928 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
929 b43_phy_read(dev,
930 B43_PHY_RADIO_BITFIELD) | 0x1000);
931
932 phy_stacksave(0x04A0);
933 b43_phy_write(dev, 0x04A0,
934 (b43_phy_read(dev, 0x04A0) & 0xC0C0) | 0x0008);
935 phy_stacksave(0x04A1);
936 b43_phy_write(dev, 0x04A1,
937 (b43_phy_read(dev, 0x04A1) & 0xC0C0) | 0x0605);
938 phy_stacksave(0x04A2);
939 b43_phy_write(dev, 0x04A2,
940 (b43_phy_read(dev, 0x04A2) & 0xC0C0) | 0x0204);
941 phy_stacksave(0x04A8);
942 b43_phy_write(dev, 0x04A8,
943 (b43_phy_read(dev, 0x04A8) & 0xC0C0) | 0x0803);
944 phy_stacksave(0x04AB);
945 b43_phy_write(dev, 0x04AB,
946 (b43_phy_read(dev, 0x04AB) & 0xC0C0) | 0x0605);
947
948 phy_stacksave(0x04A7);
949 b43_phy_write(dev, 0x04A7, 0x0002);
950 phy_stacksave(0x04A3);
951 b43_phy_write(dev, 0x04A3, 0x287A);
952 phy_stacksave(0x04A9);
953 b43_phy_write(dev, 0x04A9, 0x2027);
954 phy_stacksave(0x0493);
955 b43_phy_write(dev, 0x0493, 0x32F5);
956 phy_stacksave(0x04AA);
957 b43_phy_write(dev, 0x04AA, 0x2027);
958 phy_stacksave(0x04AC);
959 b43_phy_write(dev, 0x04AC, 0x32F5);
960 break;
961 case B43_INTERFMODE_MANUALWLAN:
962 if (b43_phy_read(dev, 0x0033) & 0x0800)
963 break;
964
965 gphy->aci_enable = 1;
966
967 phy_stacksave(B43_PHY_RADIO_BITFIELD);
968 phy_stacksave(B43_PHY_G_CRS);
969 if (phy->rev < 2) {
970 phy_stacksave(0x0406);
971 } else {
972 phy_stacksave(0x04C0);
973 phy_stacksave(0x04C1);
974 }
975 phy_stacksave(0x0033);
976 phy_stacksave(0x04A7);
977 phy_stacksave(0x04A3);
978 phy_stacksave(0x04A9);
979 phy_stacksave(0x04AA);
980 phy_stacksave(0x04AC);
981 phy_stacksave(0x0493);
982 phy_stacksave(0x04A1);
983 phy_stacksave(0x04A0);
984 phy_stacksave(0x04A2);
985 phy_stacksave(0x048A);
986 phy_stacksave(0x04A8);
987 phy_stacksave(0x04AB);
988 if (phy->rev == 2) {
989 phy_stacksave(0x04AD);
990 phy_stacksave(0x04AE);
991 } else if (phy->rev >= 3) {
992 phy_stacksave(0x04AD);
993 phy_stacksave(0x0415);
994 phy_stacksave(0x0416);
995 phy_stacksave(0x0417);
996 ofdmtab_stacksave(0x1A00, 0x2);
997 ofdmtab_stacksave(0x1A00, 0x3);
998 }
999 phy_stacksave(0x042B);
1000 phy_stacksave(0x048C);
1001
1002 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
1003 b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
1004 & ~0x1000);
1005 b43_phy_write(dev, B43_PHY_G_CRS,
1006 (b43_phy_read(dev, B43_PHY_G_CRS)
1007 & 0xFFFC) | 0x0002);
1008
1009 b43_phy_write(dev, 0x0033, 0x0800);
1010 b43_phy_write(dev, 0x04A3, 0x2027);
1011 b43_phy_write(dev, 0x04A9, 0x1CA8);
1012 b43_phy_write(dev, 0x0493, 0x287A);
1013 b43_phy_write(dev, 0x04AA, 0x1CA8);
1014 b43_phy_write(dev, 0x04AC, 0x287A);
1015
1016 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
1017 & 0xFFC0) | 0x001A);
1018 b43_phy_write(dev, 0x04A7, 0x000D);
1019
1020 if (phy->rev < 2) {
1021 b43_phy_write(dev, 0x0406, 0xFF0D);
1022 } else if (phy->rev == 2) {
1023 b43_phy_write(dev, 0x04C0, 0xFFFF);
1024 b43_phy_write(dev, 0x04C1, 0x00A9);
1025 } else {
1026 b43_phy_write(dev, 0x04C0, 0x00C1);
1027 b43_phy_write(dev, 0x04C1, 0x0059);
1028 }
1029
1030 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
1031 & 0xC0FF) | 0x1800);
1032 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
1033 & 0xFFC0) | 0x0015);
1034 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
1035 & 0xCFFF) | 0x1000);
1036 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
1037 & 0xF0FF) | 0x0A00);
1038 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
1039 & 0xCFFF) | 0x1000);
1040 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
1041 & 0xF0FF) | 0x0800);
1042 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
1043 & 0xFFCF) | 0x0010);
1044 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
1045 & 0xFFF0) | 0x0005);
1046 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
1047 & 0xFFCF) | 0x0010);
1048 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
1049 & 0xFFF0) | 0x0006);
1050 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
1051 & 0xF0FF) | 0x0800);
1052 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
1053 & 0xF0FF) | 0x0500);
1054 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
1055 & 0xFFF0) | 0x000B);
1056
1057 if (phy->rev >= 3) {
1058 b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
1059 & ~0x8000);
1060 b43_phy_write(dev, 0x0415, (b43_phy_read(dev, 0x0415)
1061 & 0x8000) | 0x36D8);
1062 b43_phy_write(dev, 0x0416, (b43_phy_read(dev, 0x0416)
1063 & 0x8000) | 0x36D8);
1064 b43_phy_write(dev, 0x0417, (b43_phy_read(dev, 0x0417)
1065 & 0xFE00) | 0x016D);
1066 } else {
1067 b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
1068 | 0x1000);
1069 b43_phy_write(dev, 0x048A, (b43_phy_read(dev, 0x048A)
1070 & 0x9FFF) | 0x2000);
1071 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
1072 }
1073 if (phy->rev >= 2) {
1074 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B)
1075 | 0x0800);
1076 }
1077 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
1078 & 0xF0FF) | 0x0200);
1079 if (phy->rev == 2) {
1080 b43_phy_write(dev, 0x04AE, (b43_phy_read(dev, 0x04AE)
1081 & 0xFF00) | 0x007F);
1082 b43_phy_write(dev, 0x04AD, (b43_phy_read(dev, 0x04AD)
1083 & 0x00FF) | 0x1300);
1084 } else if (phy->rev >= 6) {
1085 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
1086 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
1087 b43_phy_write(dev, 0x04AD, b43_phy_read(dev, 0x04AD)
1088 & 0x00FF);
1089 }
1090 b43_calc_nrssi_slope(dev);
1091 break;
1092 default:
1093 B43_WARN_ON(1);
1094 }
1095}
1096
1097static void
1098b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
1099{
1100 struct b43_phy *phy = &dev->phy;
1101 struct b43_phy_g *gphy = phy->g;
1102 u32 *stack = gphy->interfstack;
1103
1104 switch (mode) {
1105 case B43_INTERFMODE_NONWLAN:
1106 if (phy->rev != 1) {
1107 b43_phy_write(dev, 0x042B,
1108 b43_phy_read(dev, 0x042B) & ~0x0800);
1109 b43_phy_write(dev, B43_PHY_G_CRS,
1110 b43_phy_read(dev,
1111 B43_PHY_G_CRS) | 0x4000);
1112 break;
1113 }
1114 radio_stackrestore(0x0078);
1115 b43_calc_nrssi_threshold(dev);
1116 phy_stackrestore(0x0406);
1117 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) & ~0x0800);
1118 if (!dev->bad_frames_preempt) {
1119 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
1120 b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
1121 & ~(1 << 11));
1122 }
1123 b43_phy_write(dev, B43_PHY_G_CRS,
1124 b43_phy_read(dev, B43_PHY_G_CRS) | 0x4000);
1125 phy_stackrestore(0x04A0);
1126 phy_stackrestore(0x04A1);
1127 phy_stackrestore(0x04A2);
1128 phy_stackrestore(0x04A8);
1129 phy_stackrestore(0x04AB);
1130 phy_stackrestore(0x04A7);
1131 phy_stackrestore(0x04A3);
1132 phy_stackrestore(0x04A9);
1133 phy_stackrestore(0x0493);
1134 phy_stackrestore(0x04AA);
1135 phy_stackrestore(0x04AC);
1136 break;
1137 case B43_INTERFMODE_MANUALWLAN:
1138 if (!(b43_phy_read(dev, 0x0033) & 0x0800))
1139 break;
1140
1141 gphy->aci_enable = 0;
1142
1143 phy_stackrestore(B43_PHY_RADIO_BITFIELD);
1144 phy_stackrestore(B43_PHY_G_CRS);
1145 phy_stackrestore(0x0033);
1146 phy_stackrestore(0x04A3);
1147 phy_stackrestore(0x04A9);
1148 phy_stackrestore(0x0493);
1149 phy_stackrestore(0x04AA);
1150 phy_stackrestore(0x04AC);
1151 phy_stackrestore(0x04A0);
1152 phy_stackrestore(0x04A7);
1153 if (phy->rev >= 2) {
1154 phy_stackrestore(0x04C0);
1155 phy_stackrestore(0x04C1);
1156 } else
1157 phy_stackrestore(0x0406);
1158 phy_stackrestore(0x04A1);
1159 phy_stackrestore(0x04AB);
1160 phy_stackrestore(0x04A8);
1161 if (phy->rev == 2) {
1162 phy_stackrestore(0x04AD);
1163 phy_stackrestore(0x04AE);
1164 } else if (phy->rev >= 3) {
1165 phy_stackrestore(0x04AD);
1166 phy_stackrestore(0x0415);
1167 phy_stackrestore(0x0416);
1168 phy_stackrestore(0x0417);
1169 ofdmtab_stackrestore(0x1A00, 0x2);
1170 ofdmtab_stackrestore(0x1A00, 0x3);
1171 }
1172 phy_stackrestore(0x04A2);
1173 phy_stackrestore(0x048A);
1174 phy_stackrestore(0x042B);
1175 phy_stackrestore(0x048C);
1176 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
1177 b43_calc_nrssi_slope(dev);
1178 break;
1179 default:
1180 B43_WARN_ON(1);
1181 }
1182}
1183
1184#undef phy_stacksave
1185#undef phy_stackrestore
1186#undef radio_stacksave
1187#undef radio_stackrestore
1188#undef ofdmtab_stacksave
1189#undef ofdmtab_stackrestore
1190
1191static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
1192{
1193 u16 reg, index, ret;
1194
1195 static const u8 rcc_table[] = {
1196 0x02, 0x03, 0x01, 0x0F,
1197 0x06, 0x07, 0x05, 0x0F,
1198 0x0A, 0x0B, 0x09, 0x0F,
1199 0x0E, 0x0F, 0x0D, 0x0F,
1200 };
1201
1202 reg = b43_radio_read16(dev, 0x60);
1203 index = (reg & 0x001E) >> 1;
1204 ret = rcc_table[index] << 1;
1205 ret |= (reg & 0x0001);
1206 ret |= 0x0020;
1207
1208 return ret;
1209}
1210
1211#define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
1212static u16 radio2050_rfover_val(struct b43_wldev *dev,
1213 u16 phy_register, unsigned int lpd)
1214{
1215 struct b43_phy *phy = &dev->phy;
1216 struct b43_phy_g *gphy = phy->g;
1217 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
1218
1219 if (!phy->gmode)
1220 return 0;
1221
1222 if (has_loopback_gain(phy)) {
1223 int max_lb_gain = gphy->max_lb_gain;
1224 u16 extlna;
1225 u16 i;
1226
1227 if (phy->radio_rev == 8)
1228 max_lb_gain += 0x3E;
1229 else
1230 max_lb_gain += 0x26;
1231 if (max_lb_gain >= 0x46) {
1232 extlna = 0x3000;
1233 max_lb_gain -= 0x46;
1234 } else if (max_lb_gain >= 0x3A) {
1235 extlna = 0x1000;
1236 max_lb_gain -= 0x3A;
1237 } else if (max_lb_gain >= 0x2E) {
1238 extlna = 0x2000;
1239 max_lb_gain -= 0x2E;
1240 } else {
1241 extlna = 0;
1242 max_lb_gain -= 0x10;
1243 }
1244
1245 for (i = 0; i < 16; i++) {
1246 max_lb_gain -= (i * 6);
1247 if (max_lb_gain < 6)
1248 break;
1249 }
1250
1251 if ((phy->rev < 7) ||
1252 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
1253 if (phy_register == B43_PHY_RFOVER) {
1254 return 0x1B3;
1255 } else if (phy_register == B43_PHY_RFOVERVAL) {
1256 extlna |= (i << 8);
1257 switch (lpd) {
1258 case LPD(0, 1, 1):
1259 return 0x0F92;
1260 case LPD(0, 0, 1):
1261 case LPD(1, 0, 1):
1262 return (0x0092 | extlna);
1263 case LPD(1, 0, 0):
1264 return (0x0093 | extlna);
1265 }
1266 B43_WARN_ON(1);
1267 }
1268 B43_WARN_ON(1);
1269 } else {
1270 if (phy_register == B43_PHY_RFOVER) {
1271 return 0x9B3;
1272 } else if (phy_register == B43_PHY_RFOVERVAL) {
1273 if (extlna)
1274 extlna |= 0x8000;
1275 extlna |= (i << 8);
1276 switch (lpd) {
1277 case LPD(0, 1, 1):
1278 return 0x8F92;
1279 case LPD(0, 0, 1):
1280 return (0x8092 | extlna);
1281 case LPD(1, 0, 1):
1282 return (0x2092 | extlna);
1283 case LPD(1, 0, 0):
1284 return (0x2093 | extlna);
1285 }
1286 B43_WARN_ON(1);
1287 }
1288 B43_WARN_ON(1);
1289 }
1290 } else {
1291 if ((phy->rev < 7) ||
1292 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
1293 if (phy_register == B43_PHY_RFOVER) {
1294 return 0x1B3;
1295 } else if (phy_register == B43_PHY_RFOVERVAL) {
1296 switch (lpd) {
1297 case LPD(0, 1, 1):
1298 return 0x0FB2;
1299 case LPD(0, 0, 1):
1300 return 0x00B2;
1301 case LPD(1, 0, 1):
1302 return 0x30B2;
1303 case LPD(1, 0, 0):
1304 return 0x30B3;
1305 }
1306 B43_WARN_ON(1);
1307 }
1308 B43_WARN_ON(1);
1309 } else {
1310 if (phy_register == B43_PHY_RFOVER) {
1311 return 0x9B3;
1312 } else if (phy_register == B43_PHY_RFOVERVAL) {
1313 switch (lpd) {
1314 case LPD(0, 1, 1):
1315 return 0x8FB2;
1316 case LPD(0, 0, 1):
1317 return 0x80B2;
1318 case LPD(1, 0, 1):
1319 return 0x20B2;
1320 case LPD(1, 0, 0):
1321 return 0x20B3;
1322 }
1323 B43_WARN_ON(1);
1324 }
1325 B43_WARN_ON(1);
1326 }
1327 }
1328 return 0;
1329}
1330
1331struct init2050_saved_values {
1332 /* Core registers */
1333 u16 reg_3EC;
1334 u16 reg_3E6;
1335 u16 reg_3F4;
1336 /* Radio registers */
1337 u16 radio_43;
1338 u16 radio_51;
1339 u16 radio_52;
1340 /* PHY registers */
1341 u16 phy_pgactl;
1342 u16 phy_cck_5A;
1343 u16 phy_cck_59;
1344 u16 phy_cck_58;
1345 u16 phy_cck_30;
1346 u16 phy_rfover;
1347 u16 phy_rfoverval;
1348 u16 phy_analogover;
1349 u16 phy_analogoverval;
1350 u16 phy_crs0;
1351 u16 phy_classctl;
1352 u16 phy_lo_mask;
1353 u16 phy_lo_ctl;
1354 u16 phy_syncctl;
1355};
1356
1357u16 b43_radio_init2050(struct b43_wldev *dev)
1358{
1359 struct b43_phy *phy = &dev->phy;
1360 struct init2050_saved_values sav;
1361 u16 rcc;
1362 u16 radio78;
1363 u16 ret;
1364 u16 i, j;
1365 u32 tmp1 = 0, tmp2 = 0;
1366
1367 memset(&sav, 0, sizeof(sav)); /* get rid of "may be used uninitialized..." */
1368
1369 sav.radio_43 = b43_radio_read16(dev, 0x43);
1370 sav.radio_51 = b43_radio_read16(dev, 0x51);
1371 sav.radio_52 = b43_radio_read16(dev, 0x52);
1372 sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
1373 sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1374 sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59));
1375 sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58));
1376
1377 if (phy->type == B43_PHYTYPE_B) {
1378 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
1379 sav.reg_3EC = b43_read16(dev, 0x3EC);
1380
1381 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF);
1382 b43_write16(dev, 0x3EC, 0x3F3F);
1383 } else if (phy->gmode || phy->rev >= 2) {
1384 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
1385 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1386 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1387 sav.phy_analogoverval =
1388 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1389 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
1390 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
1391
1392 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1393 b43_phy_read(dev, B43_PHY_ANALOGOVER)
1394 | 0x0003);
1395 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1396 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL)
1397 & 0xFFFC);
1398 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
1399 & 0x7FFF);
1400 b43_phy_write(dev, B43_PHY_CLASSCTL,
1401 b43_phy_read(dev, B43_PHY_CLASSCTL)
1402 & 0xFFFC);
1403 if (has_loopback_gain(phy)) {
1404 sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
1405 sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
1406
1407 if (phy->rev >= 3)
1408 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1409 else
1410 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1411 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1412 }
1413
1414 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1415 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1416 LPD(0, 1, 1)));
1417 b43_phy_write(dev, B43_PHY_RFOVER,
1418 radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
1419 }
1420 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
1421
1422 sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
1423 b43_phy_write(dev, B43_PHY_SYNCCTL, b43_phy_read(dev, B43_PHY_SYNCCTL)
1424 & 0xFF7F);
1425 sav.reg_3E6 = b43_read16(dev, 0x3E6);
1426 sav.reg_3F4 = b43_read16(dev, 0x3F4);
1427
1428 if (phy->analog == 0) {
1429 b43_write16(dev, 0x03E6, 0x0122);
1430 } else {
1431 if (phy->analog >= 2) {
1432 b43_phy_write(dev, B43_PHY_CCK(0x03),
1433 (b43_phy_read(dev, B43_PHY_CCK(0x03))
1434 & 0xFFBF) | 0x40);
1435 }
1436 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
1437 (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
1438 }
1439
1440 rcc = b43_radio_core_calibration_value(dev);
1441
1442 if (phy->type == B43_PHYTYPE_B)
1443 b43_radio_write16(dev, 0x78, 0x26);
1444 if (phy->gmode || phy->rev >= 2) {
1445 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1446 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1447 LPD(0, 1, 1)));
1448 }
1449 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
1450 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403);
1451 if (phy->gmode || phy->rev >= 2) {
1452 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1453 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1454 LPD(0, 0, 1)));
1455 }
1456 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
1457 b43_radio_write16(dev, 0x51, b43_radio_read16(dev, 0x51)
1458 | 0x0004);
1459 if (phy->radio_rev == 8) {
1460 b43_radio_write16(dev, 0x43, 0x1F);
1461 } else {
1462 b43_radio_write16(dev, 0x52, 0);
1463 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1464 & 0xFFF0) | 0x0009);
1465 }
1466 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1467
1468 for (i = 0; i < 16; i++) {
1469 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480);
1470 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1471 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1472 if (phy->gmode || phy->rev >= 2) {
1473 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1474 radio2050_rfover_val(dev,
1475 B43_PHY_RFOVERVAL,
1476 LPD(1, 0, 1)));
1477 }
1478 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1479 udelay(10);
1480 if (phy->gmode || phy->rev >= 2) {
1481 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1482 radio2050_rfover_val(dev,
1483 B43_PHY_RFOVERVAL,
1484 LPD(1, 0, 1)));
1485 }
1486 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1487 udelay(10);
1488 if (phy->gmode || phy->rev >= 2) {
1489 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1490 radio2050_rfover_val(dev,
1491 B43_PHY_RFOVERVAL,
1492 LPD(1, 0, 0)));
1493 }
1494 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1495 udelay(20);
1496 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1497 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1498 if (phy->gmode || phy->rev >= 2) {
1499 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1500 radio2050_rfover_val(dev,
1501 B43_PHY_RFOVERVAL,
1502 LPD(1, 0, 1)));
1503 }
1504 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1505 }
1506 udelay(10);
1507
1508 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1509 tmp1++;
1510 tmp1 >>= 9;
1511
1512 for (i = 0; i < 16; i++) {
1513 radio78 = (bitrev4(i) << 1) | 0x0020;
1514 b43_radio_write16(dev, 0x78, radio78);
1515 udelay(10);
1516 for (j = 0; j < 16; j++) {
1517 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80);
1518 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1519 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1520 if (phy->gmode || phy->rev >= 2) {
1521 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1522 radio2050_rfover_val(dev,
1523 B43_PHY_RFOVERVAL,
1524 LPD(1, 0,
1525 1)));
1526 }
1527 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1528 udelay(10);
1529 if (phy->gmode || phy->rev >= 2) {
1530 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1531 radio2050_rfover_val(dev,
1532 B43_PHY_RFOVERVAL,
1533 LPD(1, 0,
1534 1)));
1535 }
1536 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1537 udelay(10);
1538 if (phy->gmode || phy->rev >= 2) {
1539 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1540 radio2050_rfover_val(dev,
1541 B43_PHY_RFOVERVAL,
1542 LPD(1, 0,
1543 0)));
1544 }
1545 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1546 udelay(10);
1547 tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1548 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1549 if (phy->gmode || phy->rev >= 2) {
1550 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1551 radio2050_rfover_val(dev,
1552 B43_PHY_RFOVERVAL,
1553 LPD(1, 0,
1554 1)));
1555 }
1556 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1557 }
1558 tmp2++;
1559 tmp2 >>= 8;
1560 if (tmp1 < tmp2)
1561 break;
1562 }
1563
1564 /* Restore the registers */
1565 b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
1566 b43_radio_write16(dev, 0x51, sav.radio_51);
1567 b43_radio_write16(dev, 0x52, sav.radio_52);
1568 b43_radio_write16(dev, 0x43, sav.radio_43);
1569 b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A);
1570 b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59);
1571 b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58);
1572 b43_write16(dev, 0x3E6, sav.reg_3E6);
1573 if (phy->analog != 0)
1574 b43_write16(dev, 0x3F4, sav.reg_3F4);
1575 b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
1576 b43_synth_pu_workaround(dev, phy->channel);
1577 if (phy->type == B43_PHYTYPE_B) {
1578 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30);
1579 b43_write16(dev, 0x3EC, sav.reg_3EC);
1580 } else if (phy->gmode) {
1581 b43_write16(dev, B43_MMIO_PHY_RADIO,
1582 b43_read16(dev, B43_MMIO_PHY_RADIO)
1583 & 0x7FFF);
1584 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
1585 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
1586 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
1587 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1588 sav.phy_analogoverval);
1589 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
1590 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
1591 if (has_loopback_gain(phy)) {
1592 b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
1593 b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
1594 }
1595 }
1596 if (i > 15)
1597 ret = radio78;
1598 else
1599 ret = rcc;
1600
1601 return ret;
1602}
1603
1604static void b43_phy_initb5(struct b43_wldev *dev)
1605{
1606 struct ssb_bus *bus = dev->dev->bus;
1607 struct b43_phy *phy = &dev->phy;
1608 struct b43_phy_g *gphy = phy->g;
1609 u16 offset, value;
1610 u8 old_channel;
1611
1612 if (phy->analog == 1) {
1613 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
1614 | 0x0050);
1615 }
1616 if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
1617 (bus->boardinfo.type != SSB_BOARD_BU4306)) {
1618 value = 0x2120;
1619 for (offset = 0x00A8; offset < 0x00C7; offset++) {
1620 b43_phy_write(dev, offset, value);
1621 value += 0x202;
1622 }
1623 }
1624 b43_phy_write(dev, 0x0035, (b43_phy_read(dev, 0x0035) & 0xF0FF)
1625 | 0x0700);
1626 if (phy->radio_ver == 0x2050)
1627 b43_phy_write(dev, 0x0038, 0x0667);
1628
1629 if (phy->gmode || phy->rev >= 2) {
1630 if (phy->radio_ver == 0x2050) {
1631 b43_radio_write16(dev, 0x007A,
1632 b43_radio_read16(dev, 0x007A)
1633 | 0x0020);
1634 b43_radio_write16(dev, 0x0051,
1635 b43_radio_read16(dev, 0x0051)
1636 | 0x0004);
1637 }
1638 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
1639
1640 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1641 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1642
1643 b43_phy_write(dev, 0x001C, 0x186A);
1644
1645 b43_phy_write(dev, 0x0013,
1646 (b43_phy_read(dev, 0x0013) & 0x00FF) | 0x1900);
1647 b43_phy_write(dev, 0x0035,
1648 (b43_phy_read(dev, 0x0035) & 0xFFC0) | 0x0064);
1649 b43_phy_write(dev, 0x005D,
1650 (b43_phy_read(dev, 0x005D) & 0xFF80) | 0x000A);
1651 }
1652
1653 if (dev->bad_frames_preempt) {
1654 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
1655 b43_phy_read(dev,
1656 B43_PHY_RADIO_BITFIELD) | (1 << 11));
1657 }
1658
1659 if (phy->analog == 1) {
1660 b43_phy_write(dev, 0x0026, 0xCE00);
1661 b43_phy_write(dev, 0x0021, 0x3763);
1662 b43_phy_write(dev, 0x0022, 0x1BC3);
1663 b43_phy_write(dev, 0x0023, 0x06F9);
1664 b43_phy_write(dev, 0x0024, 0x037E);
1665 } else
1666 b43_phy_write(dev, 0x0026, 0xCC00);
1667 b43_phy_write(dev, 0x0030, 0x00C6);
1668 b43_write16(dev, 0x03EC, 0x3F22);
1669
1670 if (phy->analog == 1)
1671 b43_phy_write(dev, 0x0020, 0x3E1C);
1672 else
1673 b43_phy_write(dev, 0x0020, 0x301C);
1674
1675 if (phy->analog == 0)
1676 b43_write16(dev, 0x03E4, 0x3000);
1677
1678 old_channel = phy->channel;
1679 /* Force to channel 7, even if not supported. */
1680 b43_gphy_channel_switch(dev, 7, 0);
1681
1682 if (phy->radio_ver != 0x2050) {
1683 b43_radio_write16(dev, 0x0075, 0x0080);
1684 b43_radio_write16(dev, 0x0079, 0x0081);
1685 }
1686
1687 b43_radio_write16(dev, 0x0050, 0x0020);
1688 b43_radio_write16(dev, 0x0050, 0x0023);
1689
1690 if (phy->radio_ver == 0x2050) {
1691 b43_radio_write16(dev, 0x0050, 0x0020);
1692 b43_radio_write16(dev, 0x005A, 0x0070);
1693 }
1694
1695 b43_radio_write16(dev, 0x005B, 0x007B);
1696 b43_radio_write16(dev, 0x005C, 0x00B0);
1697
1698 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0007);
1699
1700 b43_gphy_channel_switch(dev, old_channel, 0);
1701
1702 b43_phy_write(dev, 0x0014, 0x0080);
1703 b43_phy_write(dev, 0x0032, 0x00CA);
1704 b43_phy_write(dev, 0x002A, 0x88A3);
1705
1706 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1707
1708 if (phy->radio_ver == 0x2050)
1709 b43_radio_write16(dev, 0x005D, 0x000D);
1710
1711 b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
1712}
1713
1714static void b43_phy_initb6(struct b43_wldev *dev)
1715{
1716 struct b43_phy *phy = &dev->phy;
1717 struct b43_phy_g *gphy = phy->g;
1718 u16 offset, val;
1719 u8 old_channel;
1720
1721 b43_phy_write(dev, 0x003E, 0x817A);
1722 b43_radio_write16(dev, 0x007A,
1723 (b43_radio_read16(dev, 0x007A) | 0x0058));
1724 if (phy->radio_rev == 4 || phy->radio_rev == 5) {
1725 b43_radio_write16(dev, 0x51, 0x37);
1726 b43_radio_write16(dev, 0x52, 0x70);
1727 b43_radio_write16(dev, 0x53, 0xB3);
1728 b43_radio_write16(dev, 0x54, 0x9B);
1729 b43_radio_write16(dev, 0x5A, 0x88);
1730 b43_radio_write16(dev, 0x5B, 0x88);
1731 b43_radio_write16(dev, 0x5D, 0x88);
1732 b43_radio_write16(dev, 0x5E, 0x88);
1733 b43_radio_write16(dev, 0x7D, 0x88);
1734 b43_hf_write(dev, b43_hf_read(dev)
1735 | B43_HF_TSSIRPSMW);
1736 }
1737 B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7); /* We had code for these revs here... */
1738 if (phy->radio_rev == 8) {
1739 b43_radio_write16(dev, 0x51, 0);
1740 b43_radio_write16(dev, 0x52, 0x40);
1741 b43_radio_write16(dev, 0x53, 0xB7);
1742 b43_radio_write16(dev, 0x54, 0x98);
1743 b43_radio_write16(dev, 0x5A, 0x88);
1744 b43_radio_write16(dev, 0x5B, 0x6B);
1745 b43_radio_write16(dev, 0x5C, 0x0F);
1746 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_ALTIQ) {
1747 b43_radio_write16(dev, 0x5D, 0xFA);
1748 b43_radio_write16(dev, 0x5E, 0xD8);
1749 } else {
1750 b43_radio_write16(dev, 0x5D, 0xF5);
1751 b43_radio_write16(dev, 0x5E, 0xB8);
1752 }
1753 b43_radio_write16(dev, 0x0073, 0x0003);
1754 b43_radio_write16(dev, 0x007D, 0x00A8);
1755 b43_radio_write16(dev, 0x007C, 0x0001);
1756 b43_radio_write16(dev, 0x007E, 0x0008);
1757 }
1758 val = 0x1E1F;
1759 for (offset = 0x0088; offset < 0x0098; offset++) {
1760 b43_phy_write(dev, offset, val);
1761 val -= 0x0202;
1762 }
1763 val = 0x3E3F;
1764 for (offset = 0x0098; offset < 0x00A8; offset++) {
1765 b43_phy_write(dev, offset, val);
1766 val -= 0x0202;
1767 }
1768 val = 0x2120;
1769 for (offset = 0x00A8; offset < 0x00C8; offset++) {
1770 b43_phy_write(dev, offset, (val & 0x3F3F));
1771 val += 0x0202;
1772 }
1773 if (phy->type == B43_PHYTYPE_G) {
1774 b43_radio_write16(dev, 0x007A,
1775 b43_radio_read16(dev, 0x007A) | 0x0020);
1776 b43_radio_write16(dev, 0x0051,
1777 b43_radio_read16(dev, 0x0051) | 0x0004);
1778 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1779 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1780 b43_phy_write(dev, 0x5B, 0);
1781 b43_phy_write(dev, 0x5C, 0);
1782 }
1783
1784 old_channel = phy->channel;
1785 if (old_channel >= 8)
1786 b43_gphy_channel_switch(dev, 1, 0);
1787 else
1788 b43_gphy_channel_switch(dev, 13, 0);
1789
1790 b43_radio_write16(dev, 0x0050, 0x0020);
1791 b43_radio_write16(dev, 0x0050, 0x0023);
1792 udelay(40);
1793 if (phy->radio_rev < 6 || phy->radio_rev == 8) {
1794 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
1795 | 0x0002));
1796 b43_radio_write16(dev, 0x50, 0x20);
1797 }
1798 if (phy->radio_rev <= 2) {
1799 b43_radio_write16(dev, 0x7C, 0x20);
1800 b43_radio_write16(dev, 0x5A, 0x70);
1801 b43_radio_write16(dev, 0x5B, 0x7B);
1802 b43_radio_write16(dev, 0x5C, 0xB0);
1803 }
1804 b43_radio_write16(dev, 0x007A,
1805 (b43_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
1806
1807 b43_gphy_channel_switch(dev, old_channel, 0);
1808
1809 b43_phy_write(dev, 0x0014, 0x0200);
1810 if (phy->radio_rev >= 6)
1811 b43_phy_write(dev, 0x2A, 0x88C2);
1812 else
1813 b43_phy_write(dev, 0x2A, 0x8AC0);
1814 b43_phy_write(dev, 0x0038, 0x0668);
1815 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1816 if (phy->radio_rev <= 5) {
1817 b43_phy_write(dev, 0x5D, (b43_phy_read(dev, 0x5D)
1818 & 0xFF80) | 0x0003);
1819 }
1820 if (phy->radio_rev <= 2)
1821 b43_radio_write16(dev, 0x005D, 0x000D);
1822
1823 if (phy->analog == 4) {
1824 b43_write16(dev, 0x3E4, 9);
1825 b43_phy_write(dev, 0x61, b43_phy_read(dev, 0x61)
1826 & 0x0FFF);
1827 } else {
1828 b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0)
1829 | 0x0004);
1830 }
1831 if (phy->type == B43_PHYTYPE_B)
1832 B43_WARN_ON(1);
1833 else if (phy->type == B43_PHYTYPE_G)
1834 b43_write16(dev, 0x03E6, 0x0);
1835}
1836
1837static void b43_calc_loopback_gain(struct b43_wldev *dev)
1838{
1839 struct b43_phy *phy = &dev->phy;
1840 struct b43_phy_g *gphy = phy->g;
1841 u16 backup_phy[16] = { 0 };
1842 u16 backup_radio[3];
1843 u16 backup_bband;
1844 u16 i, j, loop_i_max;
1845 u16 trsw_rx;
1846 u16 loop1_outer_done, loop1_inner_done;
1847
1848 backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
1849 backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1850 backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
1851 backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1852 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1853 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1854 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1855 }
1856 backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1857 backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59));
1858 backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58));
1859 backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A));
1860 backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03));
1861 backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1862 backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1863 backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B));
1864 backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1865 backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1866 backup_bband = gphy->bbatt.att;
1867 backup_radio[0] = b43_radio_read16(dev, 0x52);
1868 backup_radio[1] = b43_radio_read16(dev, 0x43);
1869 backup_radio[2] = b43_radio_read16(dev, 0x7A);
1870
1871 b43_phy_write(dev, B43_PHY_CRS0,
1872 b43_phy_read(dev, B43_PHY_CRS0) & 0x3FFF);
1873 b43_phy_write(dev, B43_PHY_CCKBBANDCFG,
1874 b43_phy_read(dev, B43_PHY_CCKBBANDCFG) | 0x8000);
1875 b43_phy_write(dev, B43_PHY_RFOVER,
1876 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0002);
1877 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1878 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFD);
1879 b43_phy_write(dev, B43_PHY_RFOVER,
1880 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0001);
1881 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1882 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFE);
1883 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1884 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1885 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0001);
1886 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1887 b43_phy_read(dev,
1888 B43_PHY_ANALOGOVERVAL) & 0xFFFE);
1889 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1890 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0002);
1891 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1892 b43_phy_read(dev,
1893 B43_PHY_ANALOGOVERVAL) & 0xFFFD);
1894 }
1895 b43_phy_write(dev, B43_PHY_RFOVER,
1896 b43_phy_read(dev, B43_PHY_RFOVER) | 0x000C);
1897 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1898 b43_phy_read(dev, B43_PHY_RFOVERVAL) | 0x000C);
1899 b43_phy_write(dev, B43_PHY_RFOVER,
1900 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0030);
1901 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1902 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1903 & 0xFFCF) | 0x10);
1904
1905 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780);
1906 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1907 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1908
1909 b43_phy_write(dev, B43_PHY_CCK(0x0A),
1910 b43_phy_read(dev, B43_PHY_CCK(0x0A)) | 0x2000);
1911 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1912 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1913 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0004);
1914 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1915 b43_phy_read(dev,
1916 B43_PHY_ANALOGOVERVAL) & 0xFFFB);
1917 }
1918 b43_phy_write(dev, B43_PHY_CCK(0x03),
1919 (b43_phy_read(dev, B43_PHY_CCK(0x03))
1920 & 0xFF9F) | 0x40);
1921
1922 if (phy->radio_rev == 8) {
1923 b43_radio_write16(dev, 0x43, 0x000F);
1924 } else {
1925 b43_radio_write16(dev, 0x52, 0);
1926 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1927 & 0xFFF0) | 0x9);
1928 }
1929 b43_gphy_set_baseband_attenuation(dev, 11);
1930
1931 if (phy->rev >= 3)
1932 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1933 else
1934 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1935 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1936
1937 b43_phy_write(dev, B43_PHY_CCK(0x2B),
1938 (b43_phy_read(dev, B43_PHY_CCK(0x2B))
1939 & 0xFFC0) | 0x01);
1940 b43_phy_write(dev, B43_PHY_CCK(0x2B),
1941 (b43_phy_read(dev, B43_PHY_CCK(0x2B))
1942 & 0xC0FF) | 0x800);
1943
1944 b43_phy_write(dev, B43_PHY_RFOVER,
1945 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0100);
1946 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1947 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xCFFF);
1948
1949 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA) {
1950 if (phy->rev >= 7) {
1951 b43_phy_write(dev, B43_PHY_RFOVER,
1952 b43_phy_read(dev, B43_PHY_RFOVER)
1953 | 0x0800);
1954 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1955 b43_phy_read(dev, B43_PHY_RFOVERVAL)
1956 | 0x8000);
1957 }
1958 }
1959 b43_radio_write16(dev, 0x7A, b43_radio_read16(dev, 0x7A)
1960 & 0x00F7);
1961
1962 j = 0;
1963 loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
1964 for (i = 0; i < loop_i_max; i++) {
1965 for (j = 0; j < 16; j++) {
1966 b43_radio_write16(dev, 0x43, i);
1967 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1968 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1969 & 0xF0FF) | (j << 8));
1970 b43_phy_write(dev, B43_PHY_PGACTL,
1971 (b43_phy_read(dev, B43_PHY_PGACTL)
1972 & 0x0FFF) | 0xA000);
1973 b43_phy_write(dev, B43_PHY_PGACTL,
1974 b43_phy_read(dev, B43_PHY_PGACTL)
1975 | 0xF000);
1976 udelay(20);
1977 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1978 goto exit_loop1;
1979 }
1980 }
1981 exit_loop1:
1982 loop1_outer_done = i;
1983 loop1_inner_done = j;
1984 if (j >= 8) {
1985 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1986 b43_phy_read(dev, B43_PHY_RFOVERVAL)
1987 | 0x30);
1988 trsw_rx = 0x1B;
1989 for (j = j - 8; j < 16; j++) {
1990 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1991 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1992 & 0xF0FF) | (j << 8));
1993 b43_phy_write(dev, B43_PHY_PGACTL,
1994 (b43_phy_read(dev, B43_PHY_PGACTL)
1995 & 0x0FFF) | 0xA000);
1996 b43_phy_write(dev, B43_PHY_PGACTL,
1997 b43_phy_read(dev, B43_PHY_PGACTL)
1998 | 0xF000);
1999 udelay(20);
2000 trsw_rx -= 3;
2001 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
2002 goto exit_loop2;
2003 }
2004 } else
2005 trsw_rx = 0x18;
2006 exit_loop2:
2007
2008 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2009 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
2010 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
2011 }
2012 b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]);
2013 b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]);
2014 b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]);
2015 b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]);
2016 b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]);
2017 b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
2018 b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
2019 b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]);
2020 b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
2021
2022 b43_gphy_set_baseband_attenuation(dev, backup_bband);
2023
2024 b43_radio_write16(dev, 0x52, backup_radio[0]);
2025 b43_radio_write16(dev, 0x43, backup_radio[1]);
2026 b43_radio_write16(dev, 0x7A, backup_radio[2]);
2027
2028 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
2029 udelay(10);
2030 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
2031 b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
2032 b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
2033 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
2034
2035 gphy->max_lb_gain =
2036 ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
2037 gphy->trsw_rx_gain = trsw_rx * 2;
2038}
2039
2040static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
2041{
2042 struct b43_phy *phy = &dev->phy;
2043
2044 if (!b43_has_hardware_pctl(dev)) {
2045 b43_phy_write(dev, 0x047A, 0xC111);
2046 return;
2047 }
2048
2049 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036) & 0xFEFF);
2050 b43_phy_write(dev, 0x002F, 0x0202);
2051 b43_phy_write(dev, 0x047C, b43_phy_read(dev, 0x047C) | 0x0002);
2052 b43_phy_write(dev, 0x047A, b43_phy_read(dev, 0x047A) | 0xF000);
2053 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
2054 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
2055 & 0xFF0F) | 0x0010);
2056 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
2057 | 0x8000);
2058 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
2059 & 0xFFC0) | 0x0010);
2060 b43_phy_write(dev, 0x002E, 0xC07F);
2061 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
2062 | 0x0400);
2063 } else {
2064 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
2065 | 0x0200);
2066 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
2067 | 0x0400);
2068 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
2069 & 0x7FFF);
2070 b43_phy_write(dev, 0x004F, b43_phy_read(dev, 0x004F)
2071 & 0xFFFE);
2072 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
2073 & 0xFFC0) | 0x0010);
2074 b43_phy_write(dev, 0x002E, 0xC07F);
2075 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
2076 & 0xFF0F) | 0x0010);
2077 }
2078}
2079
2080/* Hardware power control for G-PHY */
2081static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev)
2082{
2083 struct b43_phy *phy = &dev->phy;
2084 struct b43_phy_g *gphy = phy->g;
2085
2086 if (!b43_has_hardware_pctl(dev)) {
2087 /* No hardware power control */
2088 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
2089 return;
2090 }
2091
2092 b43_phy_write(dev, 0x0036, (b43_phy_read(dev, 0x0036) & 0xFFC0)
2093 | (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
2094 b43_phy_write(dev, 0x0478, (b43_phy_read(dev, 0x0478) & 0xFF00)
2095 | (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
2096 b43_gphy_tssi_power_lt_init(dev);
2097 b43_gphy_gain_lt_init(dev);
2098 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) & 0xFFBF);
2099 b43_phy_write(dev, 0x0014, 0x0000);
2100
2101 B43_WARN_ON(phy->rev < 6);
2102 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
2103 | 0x0800);
2104 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
2105 & 0xFEFF);
2106 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801)
2107 & 0xFFBF);
2108
2109 b43_gphy_dc_lt_init(dev, 1);
2110
2111 /* Enable hardware pctl in firmware. */
2112 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
2113}
2114
2115/* Intialize B/G PHY power control */
2116static void b43_phy_init_pctl(struct b43_wldev *dev)
2117{
2118 struct ssb_bus *bus = dev->dev->bus;
2119 struct b43_phy *phy = &dev->phy;
2120 struct b43_phy_g *gphy = phy->g;
2121 struct b43_rfatt old_rfatt;
2122 struct b43_bbatt old_bbatt;
2123 u8 old_tx_control = 0;
2124
2125 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2126
2127 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
2128 (bus->boardinfo.type == SSB_BOARD_BU4306))
2129 return;
2130
2131 b43_phy_write(dev, 0x0028, 0x8018);
2132
2133 /* This does something with the Analog... */
2134 b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
2135 & 0xFFDF);
2136
2137 if (!phy->gmode)
2138 return;
2139 b43_hardware_pctl_early_init(dev);
2140 if (gphy->cur_idle_tssi == 0) {
2141 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
2142 b43_radio_write16(dev, 0x0076,
2143 (b43_radio_read16(dev, 0x0076)
2144 & 0x00F7) | 0x0084);
2145 } else {
2146 struct b43_rfatt rfatt;
2147 struct b43_bbatt bbatt;
2148
2149 memcpy(&old_rfatt, &gphy->rfatt, sizeof(old_rfatt));
2150 memcpy(&old_bbatt, &gphy->bbatt, sizeof(old_bbatt));
2151 old_tx_control = gphy->tx_control;
2152
2153 bbatt.att = 11;
2154 if (phy->radio_rev == 8) {
2155 rfatt.att = 15;
2156 rfatt.with_padmix = 1;
2157 } else {
2158 rfatt.att = 9;
2159 rfatt.with_padmix = 0;
2160 }
2161 b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
2162 }
2163 b43_dummy_transmission(dev);
2164 gphy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
2165 if (B43_DEBUG) {
2166 /* Current-Idle-TSSI sanity check. */
2167 if (abs(gphy->cur_idle_tssi - gphy->tgt_idle_tssi) >= 20) {
2168 b43dbg(dev->wl,
2169 "!WARNING! Idle-TSSI phy->cur_idle_tssi "
2170 "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
2171 "adjustment.\n", gphy->cur_idle_tssi,
2172 gphy->tgt_idle_tssi);
2173 gphy->cur_idle_tssi = 0;
2174 }
2175 }
2176 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
2177 b43_radio_write16(dev, 0x0076,
2178 b43_radio_read16(dev, 0x0076)
2179 & 0xFF7B);
2180 } else {
2181 b43_set_txpower_g(dev, &old_bbatt,
2182 &old_rfatt, old_tx_control);
2183 }
2184 }
2185 b43_hardware_pctl_init_gphy(dev);
2186 b43_shm_clear_tssi(dev);
2187}
2188
2189static void b43_phy_initg(struct b43_wldev *dev)
2190{
2191 struct b43_phy *phy = &dev->phy;
2192 struct b43_phy_g *gphy = phy->g;
2193 u16 tmp;
2194
2195 if (phy->rev == 1)
2196 b43_phy_initb5(dev);
2197 else
2198 b43_phy_initb6(dev);
2199
2200 if (phy->rev >= 2 || phy->gmode)
2201 b43_phy_inita(dev);
2202
2203 if (phy->rev >= 2) {
2204 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
2205 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
2206 }
2207 if (phy->rev == 2) {
2208 b43_phy_write(dev, B43_PHY_RFOVER, 0);
2209 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2210 }
2211 if (phy->rev > 5) {
2212 b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
2213 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2214 }
2215 if (phy->gmode || phy->rev >= 2) {
2216 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
2217 tmp &= B43_PHYVER_VERSION;
2218 if (tmp == 3 || tmp == 5) {
2219 b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
2220 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
2221 }
2222 if (tmp == 5) {
2223 b43_phy_write(dev, B43_PHY_OFDM(0xCC),
2224 (b43_phy_read(dev, B43_PHY_OFDM(0xCC))
2225 & 0x00FF) | 0x1F00);
2226 }
2227 }
2228 if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
2229 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
2230 if (phy->radio_rev == 8) {
2231 b43_phy_write(dev, B43_PHY_EXTG(0x01),
2232 b43_phy_read(dev, B43_PHY_EXTG(0x01))
2233 | 0x80);
2234 b43_phy_write(dev, B43_PHY_OFDM(0x3E),
2235 b43_phy_read(dev, B43_PHY_OFDM(0x3E))
2236 | 0x4);
2237 }
2238 if (has_loopback_gain(phy))
2239 b43_calc_loopback_gain(dev);
2240
2241 if (phy->radio_rev != 8) {
2242 if (gphy->initval == 0xFFFF)
2243 gphy->initval = b43_radio_init2050(dev);
2244 else
2245 b43_radio_write16(dev, 0x0078, gphy->initval);
2246 }
2247 b43_lo_g_init(dev);
2248 if (has_tx_magnification(phy)) {
2249 b43_radio_write16(dev, 0x52,
2250 (b43_radio_read16(dev, 0x52) & 0xFF00)
2251 | gphy->lo_control->tx_bias | gphy->
2252 lo_control->tx_magn);
2253 } else {
2254 b43_radio_write16(dev, 0x52,
2255 (b43_radio_read16(dev, 0x52) & 0xFFF0)
2256 | gphy->lo_control->tx_bias);
2257 }
2258 if (phy->rev >= 6) {
2259 b43_phy_write(dev, B43_PHY_CCK(0x36),
2260 (b43_phy_read(dev, B43_PHY_CCK(0x36))
2261 & 0x0FFF) | (gphy->lo_control->
2262 tx_bias << 12));
2263 }
2264 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
2265 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
2266 else
2267 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
2268 if (phy->rev < 2)
2269 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
2270 else
2271 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
2272 if (phy->gmode || phy->rev >= 2) {
2273 b43_lo_g_adjust(dev);
2274 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
2275 }
2276
2277 if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
2278 /* The specs state to update the NRSSI LT with
2279 * the value 0x7FFFFFFF here. I think that is some weird
2280 * compiler optimization in the original driver.
2281 * Essentially, what we do here is resetting all NRSSI LT
2282 * entries to -32 (see the clamp_val() in nrssi_hw_update())
2283 */
2284 b43_nrssi_hw_update(dev, 0xFFFF); //FIXME?
2285 b43_calc_nrssi_threshold(dev);
2286 } else if (phy->gmode || phy->rev >= 2) {
2287 if (gphy->nrssi[0] == -1000) {
2288 B43_WARN_ON(gphy->nrssi[1] != -1000);
2289 b43_calc_nrssi_slope(dev);
2290 } else
2291 b43_calc_nrssi_threshold(dev);
2292 }
2293 if (phy->radio_rev == 8)
2294 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
2295 b43_phy_init_pctl(dev);
2296 /* FIXME: The spec says in the following if, the 0 should be replaced
2297 'if OFDM may not be used in the current locale'
2298 but OFDM is legal everywhere */
2299 if ((dev->dev->bus->chip_id == 0x4306
2300 && dev->dev->bus->chip_package == 2) || 0) {
2301 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
2302 & 0xBFFF);
2303 b43_phy_write(dev, B43_PHY_OFDM(0xC3),
2304 b43_phy_read(dev, B43_PHY_OFDM(0xC3))
2305 & 0x7FFF);
2306 }
2307}
2308
2309void b43_gphy_channel_switch(struct b43_wldev *dev,
2310 unsigned int channel,
2311 bool synthetic_pu_workaround)
2312{
2313 if (synthetic_pu_workaround)
2314 b43_synth_pu_workaround(dev, channel);
2315
2316 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2317
2318 if (channel == 14) {
2319 if (dev->dev->bus->sprom.country_code ==
2320 SSB_SPROM1CCODE_JAPAN)
2321 b43_hf_write(dev,
2322 b43_hf_read(dev) & ~B43_HF_ACPR);
2323 else
2324 b43_hf_write(dev,
2325 b43_hf_read(dev) | B43_HF_ACPR);
2326 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2327 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2328 | (1 << 11));
2329 } else {
2330 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2331 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2332 & 0xF7BF);
2333 }
2334}
2335
2336static void default_baseband_attenuation(struct b43_wldev *dev,
2337 struct b43_bbatt *bb)
2338{
2339 struct b43_phy *phy = &dev->phy;
2340
2341 if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
2342 bb->att = 0;
2343 else
2344 bb->att = 2;
2345}
2346
2347static void default_radio_attenuation(struct b43_wldev *dev,
2348 struct b43_rfatt *rf)
2349{
2350 struct ssb_bus *bus = dev->dev->bus;
2351 struct b43_phy *phy = &dev->phy;
2352
2353 rf->with_padmix = 0;
2354
2355 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
2356 bus->boardinfo.type == SSB_BOARD_BCM4309G) {
2357 if (bus->boardinfo.rev < 0x43) {
2358 rf->att = 2;
2359 return;
2360 } else if (bus->boardinfo.rev < 0x51) {
2361 rf->att = 3;
2362 return;
2363 }
2364 }
2365
2366 if (phy->type == B43_PHYTYPE_A) {
2367 rf->att = 0x60;
2368 return;
2369 }
2370
2371 switch (phy->radio_ver) {
2372 case 0x2053:
2373 switch (phy->radio_rev) {
2374 case 1:
2375 rf->att = 6;
2376 return;
2377 }
2378 break;
2379 case 0x2050:
2380 switch (phy->radio_rev) {
2381 case 0:
2382 rf->att = 5;
2383 return;
2384 case 1:
2385 if (phy->type == B43_PHYTYPE_G) {
2386 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2387 && bus->boardinfo.type == SSB_BOARD_BCM4309G
2388 && bus->boardinfo.rev >= 30)
2389 rf->att = 3;
2390 else if (bus->boardinfo.vendor ==
2391 SSB_BOARDVENDOR_BCM
2392 && bus->boardinfo.type ==
2393 SSB_BOARD_BU4306)
2394 rf->att = 3;
2395 else
2396 rf->att = 1;
2397 } else {
2398 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2399 && bus->boardinfo.type == SSB_BOARD_BCM4309G
2400 && bus->boardinfo.rev >= 30)
2401 rf->att = 7;
2402 else
2403 rf->att = 6;
2404 }
2405 return;
2406 case 2:
2407 if (phy->type == B43_PHYTYPE_G) {
2408 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2409 && bus->boardinfo.type == SSB_BOARD_BCM4309G
2410 && bus->boardinfo.rev >= 30)
2411 rf->att = 3;
2412 else if (bus->boardinfo.vendor ==
2413 SSB_BOARDVENDOR_BCM
2414 && bus->boardinfo.type ==
2415 SSB_BOARD_BU4306)
2416 rf->att = 5;
2417 else if (bus->chip_id == 0x4320)
2418 rf->att = 4;
2419 else
2420 rf->att = 3;
2421 } else
2422 rf->att = 6;
2423 return;
2424 case 3:
2425 rf->att = 5;
2426 return;
2427 case 4:
2428 case 5:
2429 rf->att = 1;
2430 return;
2431 case 6:
2432 case 7:
2433 rf->att = 5;
2434 return;
2435 case 8:
2436 rf->att = 0xA;
2437 rf->with_padmix = 1;
2438 return;
2439 case 9:
2440 default:
2441 rf->att = 5;
2442 return;
2443 }
2444 }
2445 rf->att = 5;
2446}
2447
2448static u16 default_tx_control(struct b43_wldev *dev)
2449{
2450 struct b43_phy *phy = &dev->phy;
2451
2452 if (phy->radio_ver != 0x2050)
2453 return 0;
2454 if (phy->radio_rev == 1)
2455 return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
2456 if (phy->radio_rev < 6)
2457 return B43_TXCTL_PA2DB;
2458 if (phy->radio_rev == 8)
2459 return B43_TXCTL_TXMIX;
2460 return 0;
2461}
2462
2463static u8 b43_gphy_aci_detect(struct b43_wldev *dev, u8 channel)
2464{
2465 struct b43_phy *phy = &dev->phy;
2466 struct b43_phy_g *gphy = phy->g;
2467 u8 ret = 0;
2468 u16 saved, rssi, temp;
2469 int i, j = 0;
2470
2471 saved = b43_phy_read(dev, 0x0403);
2472 b43_switch_channel(dev, channel);
2473 b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2474 if (gphy->aci_hw_rssi)
2475 rssi = b43_phy_read(dev, 0x048A) & 0x3F;
2476 else
2477 rssi = saved & 0x3F;
2478 /* clamp temp to signed 5bit */
2479 if (rssi > 32)
2480 rssi -= 64;
2481 for (i = 0; i < 100; i++) {
2482 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
2483 if (temp > 32)
2484 temp -= 64;
2485 if (temp < rssi)
2486 j++;
2487 if (j >= 20)
2488 ret = 1;
2489 }
2490 b43_phy_write(dev, 0x0403, saved);
2491
2492 return ret;
2493}
2494
2495static u8 b43_gphy_aci_scan(struct b43_wldev *dev)
2496{
2497 struct b43_phy *phy = &dev->phy;
2498 u8 ret[13];
2499 unsigned int channel = phy->channel;
2500 unsigned int i, j, start, end;
2501
2502 if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
2503 return 0;
2504
2505 b43_phy_lock(dev);
2506 b43_radio_lock(dev);
2507 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2508 b43_phy_write(dev, B43_PHY_G_CRS,
2509 b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2510 b43_set_all_gains(dev, 3, 8, 1);
2511
2512 start = (channel - 5 > 0) ? channel - 5 : 1;
2513 end = (channel + 5 < 14) ? channel + 5 : 13;
2514
2515 for (i = start; i <= end; i++) {
2516 if (abs(channel - i) > 2)
2517 ret[i - 1] = b43_gphy_aci_detect(dev, i);
2518 }
2519 b43_switch_channel(dev, channel);
2520 b43_phy_write(dev, 0x0802,
2521 (b43_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
2522 b43_phy_write(dev, 0x0403, b43_phy_read(dev, 0x0403) & 0xFFF8);
2523 b43_phy_write(dev, B43_PHY_G_CRS,
2524 b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
2525 b43_set_original_gains(dev);
2526 for (i = 0; i < 13; i++) {
2527 if (!ret[i])
2528 continue;
2529 end = (i + 5 < 13) ? i + 5 : 13;
2530 for (j = i; j < end; j++)
2531 ret[j] = 1;
2532 }
2533 b43_radio_unlock(dev);
2534 b43_phy_unlock(dev);
2535
2536 return ret[channel - 1];
2537}
2538
2539static s32 b43_tssi2dbm_ad(s32 num, s32 den)
2540{
2541 if (num < 0)
2542 return num / den;
2543 else
2544 return (num + den / 2) / den;
2545}
2546
2547static s8 b43_tssi2dbm_entry(s8 entry[], u8 index,
2548 s16 pab0, s16 pab1, s16 pab2)
2549{
2550 s32 m1, m2, f = 256, q, delta;
2551 s8 i = 0;
2552
2553 m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
2554 m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1);
2555 do {
2556 if (i > 15)
2557 return -EINVAL;
2558 q = b43_tssi2dbm_ad(f * 4096 -
2559 b43_tssi2dbm_ad(m2 * f, 16) * f, 2048);
2560 delta = abs(q - f);
2561 f = q;
2562 i++;
2563 } while (delta >= 2);
2564 entry[index] = clamp_val(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
2565 return 0;
2566}
2567
2568u8 * b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev,
2569 s16 pab0, s16 pab1, s16 pab2)
2570{
2571 unsigned int i;
2572 u8 *tab;
2573 int err;
2574
2575 tab = kmalloc(64, GFP_KERNEL);
2576 if (!tab) {
2577 b43err(dev->wl, "Could not allocate memory "
2578 "for tssi2dbm table\n");
2579 return NULL;
2580 }
2581 for (i = 0; i < 64; i++) {
2582 err = b43_tssi2dbm_entry(tab, i, pab0, pab1, pab2);
2583 if (err) {
2584 b43err(dev->wl, "Could not generate "
2585 "tssi2dBm table\n");
2586 kfree(tab);
2587 return NULL;
2588 }
2589 }
2590
2591 return tab;
2592}
2593
2594/* Initialise the TSSI->dBm lookup table */
2595static int b43_gphy_init_tssi2dbm_table(struct b43_wldev *dev)
2596{
2597 struct b43_phy *phy = &dev->phy;
2598 struct b43_phy_g *gphy = phy->g;
2599 s16 pab0, pab1, pab2;
2600
2601 pab0 = (s16) (dev->dev->bus->sprom.pa0b0);
2602 pab1 = (s16) (dev->dev->bus->sprom.pa0b1);
2603 pab2 = (s16) (dev->dev->bus->sprom.pa0b2);
2604
2605 B43_WARN_ON((dev->dev->bus->chip_id == 0x4301) &&
2606 (phy->radio_ver != 0x2050)); /* Not supported anymore */
2607
2608 gphy->dyn_tssi_tbl = 0;
2609
2610 if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
2611 pab0 != -1 && pab1 != -1 && pab2 != -1) {
2612 /* The pabX values are set in SPROM. Use them. */
2613 if ((s8) dev->dev->bus->sprom.itssi_bg != 0 &&
2614 (s8) dev->dev->bus->sprom.itssi_bg != -1) {
2615 gphy->tgt_idle_tssi =
2616 (s8) (dev->dev->bus->sprom.itssi_bg);
2617 } else
2618 gphy->tgt_idle_tssi = 62;
2619 gphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
2620 pab1, pab2);
2621 if (!gphy->tssi2dbm)
2622 return -ENOMEM;
2623 gphy->dyn_tssi_tbl = 1;
2624 } else {
2625 /* pabX values not set in SPROM. */
2626 gphy->tgt_idle_tssi = 52;
2627 gphy->tssi2dbm = b43_tssi2dbm_g_table;
2628 }
2629
2630 return 0;
2631}
2632
2633static int b43_gphy_op_allocate(struct b43_wldev *dev)
2634{
2635 struct b43_phy_g *gphy;
2636 struct b43_txpower_lo_control *lo;
2637 int err, i;
2638
2639 gphy = kzalloc(sizeof(*gphy), GFP_KERNEL);
2640 if (!gphy) {
2641 err = -ENOMEM;
2642 goto error;
2643 }
2644 dev->phy.g = gphy;
2645
2646 memset(gphy->minlowsig, 0xFF, sizeof(gphy->minlowsig));
2647
2648 /* NRSSI */
2649 for (i = 0; i < ARRAY_SIZE(gphy->nrssi); i++)
2650 gphy->nrssi[i] = -1000;
2651 for (i = 0; i < ARRAY_SIZE(gphy->nrssi_lt); i++)
2652 gphy->nrssi_lt[i] = i;
2653
2654 gphy->lofcal = 0xFFFF;
2655 gphy->initval = 0xFFFF;
2656
2657 gphy->interfmode = B43_INTERFMODE_NONE;
2658
2659 /* OFDM-table address caching. */
2660 gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
2661
2662
2663 lo = kzalloc(sizeof(*lo), GFP_KERNEL);
2664 if (!lo) {
2665 err = -ENOMEM;
2666 goto err_free_gphy;
2667 }
2668 gphy->lo_control = lo;
2669
2670 lo->tx_bias = 0xFF;
2671 INIT_LIST_HEAD(&lo->calib_list);
2672
2673 err = b43_gphy_init_tssi2dbm_table(dev);
2674 if (err)
2675 goto err_free_lo;
2676
2677 return 0;
2678
2679err_free_lo:
2680 kfree(lo);
2681err_free_gphy:
2682 kfree(gphy);
2683error:
2684 return err;
2685}
2686
2687static int b43_gphy_op_prepare(struct b43_wldev *dev)
2688{
2689 struct b43_phy *phy = &dev->phy;
2690 struct b43_phy_g *gphy = phy->g;
2691 struct b43_txpower_lo_control *lo = gphy->lo_control;
2692
2693 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2694
2695 default_baseband_attenuation(dev, &gphy->bbatt);
2696 default_radio_attenuation(dev, &gphy->rfatt);
2697 gphy->tx_control = (default_tx_control(dev) << 4);
2698 generate_rfatt_list(dev, &lo->rfatt_list);
2699 generate_bbatt_list(dev, &lo->bbatt_list);
2700
2701 /* Commit previous writes */
2702 b43_read32(dev, B43_MMIO_MACCTL);
2703
2704 if (phy->rev == 1) {
2705 /* Workaround: Temporarly disable gmode through the early init
2706 * phase, as the gmode stuff is not needed for phy rev 1 */
2707 phy->gmode = 0;
2708 b43_wireless_core_reset(dev, 0);
2709 b43_phy_initg(dev);
2710 phy->gmode = 1;
2711 b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
2712 }
2713
2714 return 0;
2715}
2716
2717static int b43_gphy_op_init(struct b43_wldev *dev)
2718{
2719 struct b43_phy_g *gphy = dev->phy.g;
2720
2721 b43_phy_initg(dev);
2722 gphy->initialised = 1;
2723
2724 return 0;
2725}
2726
2727static void b43_gphy_op_exit(struct b43_wldev *dev)
2728{
2729 struct b43_phy_g *gphy = dev->phy.g;
2730
2731 if (gphy->initialised) {
2732 //TODO
2733 gphy->initialised = 0;
2734 }
2735 b43_lo_g_cleanup(dev);
2736 kfree(gphy->lo_control);
2737 if (gphy->dyn_tssi_tbl)
2738 kfree(gphy->tssi2dbm);
2739 kfree(gphy);
2740 dev->phy.g = NULL;
2741}
2742
2743static u16 b43_gphy_op_read(struct b43_wldev *dev, u16 reg)
2744{
2745 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2746 return b43_read16(dev, B43_MMIO_PHY_DATA);
2747}
2748
2749static void b43_gphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2750{
2751 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2752 b43_write16(dev, B43_MMIO_PHY_DATA, value);
2753}
2754
2755static u16 b43_gphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2756{
2757 /* Register 1 is a 32-bit register. */
2758 B43_WARN_ON(reg == 1);
2759 /* G-PHY needs 0x80 for read access. */
2760 reg |= 0x80;
2761
2762 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2763 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2764}
2765
2766static void b43_gphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2767{
2768 /* Register 1 is a 32-bit register. */
2769 B43_WARN_ON(reg == 1);
2770
2771 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2772 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2773}
2774
2775static bool b43_gphy_op_supports_hwpctl(struct b43_wldev *dev)
2776{
2777 return (dev->phy.rev >= 6);
2778}
2779
2780static void b43_gphy_op_software_rfkill(struct b43_wldev *dev,
2781 enum rfkill_state state)
2782{
2783 struct b43_phy *phy = &dev->phy;
2784 struct b43_phy_g *gphy = phy->g;
2785 unsigned int channel;
2786
2787 might_sleep();
2788
2789 if (state == RFKILL_STATE_UNBLOCKED) {
2790 /* Turn radio ON */
2791 if (phy->radio_on)
2792 return;
2793
2794 b43_phy_write(dev, 0x0015, 0x8000);
2795 b43_phy_write(dev, 0x0015, 0xCC00);
2796 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
2797 if (gphy->radio_off_context.valid) {
2798 /* Restore the RFover values. */
2799 b43_phy_write(dev, B43_PHY_RFOVER,
2800 gphy->radio_off_context.rfover);
2801 b43_phy_write(dev, B43_PHY_RFOVERVAL,
2802 gphy->radio_off_context.rfoverval);
2803 gphy->radio_off_context.valid = 0;
2804 }
2805 channel = phy->channel;
2806 b43_gphy_channel_switch(dev, 6, 1);
2807 b43_gphy_channel_switch(dev, channel, 0);
2808 } else {
2809 /* Turn radio OFF */
2810 u16 rfover, rfoverval;
2811
2812 rfover = b43_phy_read(dev, B43_PHY_RFOVER);
2813 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
2814 gphy->radio_off_context.rfover = rfover;
2815 gphy->radio_off_context.rfoverval = rfoverval;
2816 gphy->radio_off_context.valid = 1;
2817 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
2818 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
2819 }
2820}
2821
2822static int b43_gphy_op_switch_channel(struct b43_wldev *dev,
2823 unsigned int new_channel)
2824{
2825 if ((new_channel < 1) || (new_channel > 14))
2826 return -EINVAL;
2827 b43_gphy_channel_switch(dev, new_channel, 0);
2828
2829 return 0;
2830}
2831
2832static unsigned int b43_gphy_op_get_default_chan(struct b43_wldev *dev)
2833{
2834 return 1; /* Default to channel 1 */
2835}
2836
2837static void b43_gphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2838{
2839 struct b43_phy *phy = &dev->phy;
2840 u64 hf;
2841 u16 tmp;
2842 int autodiv = 0;
2843
2844 if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
2845 autodiv = 1;
2846
2847 hf = b43_hf_read(dev);
2848 hf &= ~B43_HF_ANTDIVHELP;
2849 b43_hf_write(dev, hf);
2850
2851 tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
2852 tmp &= ~B43_PHY_BBANDCFG_RXANT;
2853 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2854 << B43_PHY_BBANDCFG_RXANT_SHIFT;
2855 b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
2856
2857 if (autodiv) {
2858 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2859 if (antenna == B43_ANTENNA_AUTO0)
2860 tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
2861 else
2862 tmp |= B43_PHY_ANTDWELL_AUTODIV1;
2863 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2864 }
2865 tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
2866 if (autodiv)
2867 tmp |= B43_PHY_ANTWRSETT_ARXDIV;
2868 else
2869 tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
2870 b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
2871 if (phy->rev >= 2) {
2872 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2873 tmp |= B43_PHY_OFDM61_10;
2874 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2875
2876 tmp =
2877 b43_phy_read(dev, B43_PHY_DIVSRCHGAINBACK);
2878 tmp = (tmp & 0xFF00) | 0x15;
2879 b43_phy_write(dev, B43_PHY_DIVSRCHGAINBACK,
2880 tmp);
2881
2882 if (phy->rev == 2) {
2883 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2884 8);
2885 } else {
2886 tmp =
2887 b43_phy_read(dev,
2888 B43_PHY_ADIVRELATED);
2889 tmp = (tmp & 0xFF00) | 8;
2890 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2891 tmp);
2892 }
2893 }
2894 if (phy->rev >= 6)
2895 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
2896
2897 hf |= B43_HF_ANTDIVHELP;
2898 b43_hf_write(dev, hf);
2899}
2900
2901static int b43_gphy_op_interf_mitigation(struct b43_wldev *dev,
2902 enum b43_interference_mitigation mode)
2903{
2904 struct b43_phy *phy = &dev->phy;
2905 struct b43_phy_g *gphy = phy->g;
2906 int currentmode;
2907
2908 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2909 if ((phy->rev == 0) || (!phy->gmode))
2910 return -ENODEV;
2911
2912 gphy->aci_wlan_automatic = 0;
2913 switch (mode) {
2914 case B43_INTERFMODE_AUTOWLAN:
2915 gphy->aci_wlan_automatic = 1;
2916 if (gphy->aci_enable)
2917 mode = B43_INTERFMODE_MANUALWLAN;
2918 else
2919 mode = B43_INTERFMODE_NONE;
2920 break;
2921 case B43_INTERFMODE_NONE:
2922 case B43_INTERFMODE_NONWLAN:
2923 case B43_INTERFMODE_MANUALWLAN:
2924 break;
2925 default:
2926 return -EINVAL;
2927 }
2928
2929 currentmode = gphy->interfmode;
2930 if (currentmode == mode)
2931 return 0;
2932 if (currentmode != B43_INTERFMODE_NONE)
2933 b43_radio_interference_mitigation_disable(dev, currentmode);
2934
2935 if (mode == B43_INTERFMODE_NONE) {
2936 gphy->aci_enable = 0;
2937 gphy->aci_hw_rssi = 0;
2938 } else
2939 b43_radio_interference_mitigation_enable(dev, mode);
2940 gphy->interfmode = mode;
2941
2942 return 0;
2943}
2944
2945/* http://bcm-specs.sipsolutions.net/EstimatePowerOut
2946 * This function converts a TSSI value to dBm in Q5.2
2947 */
2948static s8 b43_gphy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
2949{
2950 struct b43_phy_g *gphy = dev->phy.g;
2951 s8 dbm;
2952 s32 tmp;
2953
2954 tmp = (gphy->tgt_idle_tssi - gphy->cur_idle_tssi + tssi);
2955 tmp = clamp_val(tmp, 0x00, 0x3F);
2956 dbm = gphy->tssi2dbm[tmp];
2957
2958 return dbm;
2959}
2960
2961static void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
2962 int *_bbatt, int *_rfatt)
2963{
2964 int rfatt = *_rfatt;
2965 int bbatt = *_bbatt;
2966 struct b43_txpower_lo_control *lo = dev->phy.g->lo_control;
2967
2968 /* Get baseband and radio attenuation values into their permitted ranges.
2969 * Radio attenuation affects power level 4 times as much as baseband. */
2970
2971 /* Range constants */
2972 const int rf_min = lo->rfatt_list.min_val;
2973 const int rf_max = lo->rfatt_list.max_val;
2974 const int bb_min = lo->bbatt_list.min_val;
2975 const int bb_max = lo->bbatt_list.max_val;
2976
2977 while (1) {
2978 if (rfatt > rf_max && bbatt > bb_max - 4)
2979 break; /* Can not get it into ranges */
2980 if (rfatt < rf_min && bbatt < bb_min + 4)
2981 break; /* Can not get it into ranges */
2982 if (bbatt > bb_max && rfatt > rf_max - 1)
2983 break; /* Can not get it into ranges */
2984 if (bbatt < bb_min && rfatt < rf_min + 1)
2985 break; /* Can not get it into ranges */
2986
2987 if (bbatt > bb_max) {
2988 bbatt -= 4;
2989 rfatt += 1;
2990 continue;
2991 }
2992 if (bbatt < bb_min) {
2993 bbatt += 4;
2994 rfatt -= 1;
2995 continue;
2996 }
2997 if (rfatt > rf_max) {
2998 rfatt -= 1;
2999 bbatt += 4;
3000 continue;
3001 }
3002 if (rfatt < rf_min) {
3003 rfatt += 1;
3004 bbatt -= 4;
3005 continue;
3006 }
3007 break;
3008 }
3009
3010 *_rfatt = clamp_val(rfatt, rf_min, rf_max);
3011 *_bbatt = clamp_val(bbatt, bb_min, bb_max);
3012}
3013
3014static void b43_gphy_op_xmitpower(struct b43_wldev *dev)
3015{
3016 struct ssb_bus *bus = dev->dev->bus;
3017 struct b43_phy *phy = &dev->phy;
3018 struct b43_phy_g *gphy = phy->g;
3019 u16 tmp;
3020 s8 v0, v1, v2, v3;
3021 s8 average;
3022 int max_pwr;
3023 int desired_pwr, estimated_pwr, pwr_adjust;
3024 int rfatt_delta, bbatt_delta;
3025 int rfatt, bbatt;
3026 u8 tx_control;
3027
3028 if (gphy->cur_idle_tssi == 0)
3029 return;
3030 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
3031 (bus->boardinfo.type == SSB_BOARD_BU4306))
3032 return;
3033
3034 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x0058);
3035 v0 = (s8) (tmp & 0x00FF);
3036 v1 = (s8) ((tmp & 0xFF00) >> 8);
3037 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x005A);
3038 v2 = (s8) (tmp & 0x00FF);
3039 v3 = (s8) ((tmp & 0xFF00) >> 8);
3040 tmp = 0;
3041
3042 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
3043 || v3 == 0x7F) {
3044 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x0070);
3045 v0 = (s8) (tmp & 0x00FF);
3046 v1 = (s8) ((tmp & 0xFF00) >> 8);
3047 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x0072);
3048 v2 = (s8) (tmp & 0x00FF);
3049 v3 = (s8) ((tmp & 0xFF00) >> 8);
3050 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
3051 || v3 == 0x7F)
3052 return;
3053 v0 = (v0 + 0x20) & 0x3F;
3054 v1 = (v1 + 0x20) & 0x3F;
3055 v2 = (v2 + 0x20) & 0x3F;
3056 v3 = (v3 + 0x20) & 0x3F;
3057 tmp = 1;
3058 }
3059 b43_shm_clear_tssi(dev);
3060
3061 average = (v0 + v1 + v2 + v3 + 2) / 4;
3062
3063 if (tmp && (b43_shm_read16(dev, B43_SHM_SHARED, 0x005E) & 0x8))
3064 average -= 13;
3065
3066 estimated_pwr = b43_gphy_estimate_power_out(dev, average);
3067
3068 max_pwr = dev->dev->bus->sprom.maxpwr_bg;
3069 if ((dev->dev->bus->sprom.boardflags_lo
3070 & B43_BFL_PACTRL) && (phy->type == B43_PHYTYPE_G))
3071 max_pwr -= 0x3;
3072 if (unlikely(max_pwr <= 0)) {
3073 b43warn(dev->wl,
3074 "Invalid max-TX-power value in SPROM.\n");
3075 max_pwr = 60; /* fake it */
3076 dev->dev->bus->sprom.maxpwr_bg = max_pwr;
3077 }
3078
3079 /*TODO:
3080 max_pwr = min(REG - dev->dev->bus->sprom.antennagain_bgphy - 0x6, max_pwr)
3081 where REG is the max power as per the regulatory domain
3082 */
3083
3084 /* Get desired power (in Q5.2) */
3085 desired_pwr = INT_TO_Q52(phy->power_level);
3086 /* And limit it. max_pwr already is Q5.2 */
3087 desired_pwr = clamp_val(desired_pwr, 0, max_pwr);
3088 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
3089 b43dbg(dev->wl,
3090 "Current TX power output: " Q52_FMT
3091 " dBm, " "Desired TX power output: "
3092 Q52_FMT " dBm\n", Q52_ARG(estimated_pwr),
3093 Q52_ARG(desired_pwr));
3094 }
3095
3096 /* Calculate the adjustment delta. */
3097 pwr_adjust = desired_pwr - estimated_pwr;
3098
3099 /* RF attenuation delta. */
3100 rfatt_delta = ((pwr_adjust + 7) / 8);
3101 /* Lower attenuation => Bigger power output. Negate it. */
3102 rfatt_delta = -rfatt_delta;
3103
3104 /* Baseband attenuation delta. */
3105 bbatt_delta = pwr_adjust / 2;
3106 /* Lower attenuation => Bigger power output. Negate it. */
3107 bbatt_delta = -bbatt_delta;
3108 /* RF att affects power level 4 times as much as
3109 * Baseband attennuation. Subtract it. */
3110 bbatt_delta -= 4 * rfatt_delta;
3111
3112 /* So do we finally need to adjust something? */
3113 if ((rfatt_delta == 0) && (bbatt_delta == 0))
3114 return;
3115
3116 /* Calculate the new attenuation values. */
3117 bbatt = gphy->bbatt.att;
3118 bbatt += bbatt_delta;
3119 rfatt = gphy->rfatt.att;
3120 rfatt += rfatt_delta;
3121
3122 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
3123 tx_control = gphy->tx_control;
3124 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
3125 if (rfatt <= 1) {
3126 if (tx_control == 0) {
3127 tx_control =
3128 B43_TXCTL_PA2DB |
3129 B43_TXCTL_TXMIX;
3130 rfatt += 2;
3131 bbatt += 2;
3132 } else if (dev->dev->bus->sprom.
3133 boardflags_lo &
3134 B43_BFL_PACTRL) {
3135 bbatt += 4 * (rfatt - 2);
3136 rfatt = 2;
3137 }
3138 } else if (rfatt > 4 && tx_control) {
3139 tx_control = 0;
3140 if (bbatt < 3) {
3141 rfatt -= 3;
3142 bbatt += 2;
3143 } else {
3144 rfatt -= 2;
3145 bbatt -= 2;
3146 }
3147 }
3148 }
3149 /* Save the control values */
3150 gphy->tx_control = tx_control;
3151 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
3152 gphy->rfatt.att = rfatt;
3153 gphy->bbatt.att = bbatt;
3154
3155 /* Adjust the hardware */
3156 b43_phy_lock(dev);
3157 b43_radio_lock(dev);
3158 b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt,
3159 gphy->tx_control);
3160 b43_radio_unlock(dev);
3161 b43_phy_unlock(dev);
3162}
3163
3164static void b43_gphy_op_pwork_15sec(struct b43_wldev *dev)
3165{
3166 struct b43_phy *phy = &dev->phy;
3167 struct b43_phy_g *gphy = phy->g;
3168
3169 //TODO: update_aci_moving_average
3170 if (gphy->aci_enable && gphy->aci_wlan_automatic) {
3171 b43_mac_suspend(dev);
3172 if (!gphy->aci_enable && 1 /*TODO: not scanning? */ ) {
3173 if (0 /*TODO: bunch of conditions */ ) {
3174 phy->ops->interf_mitigation(dev,
3175 B43_INTERFMODE_MANUALWLAN);
3176 }
3177 } else if (0 /*TODO*/) {
3178 if (/*(aci_average > 1000) &&*/ !b43_gphy_aci_scan(dev))
3179 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3180 }
3181 b43_mac_enable(dev);
3182 } else if (gphy->interfmode == B43_INTERFMODE_NONWLAN &&
3183 phy->rev == 1) {
3184 //TODO: implement rev1 workaround
3185 }
3186 b43_lo_g_maintanance_work(dev);
3187}
3188
3189static void b43_gphy_op_pwork_60sec(struct b43_wldev *dev)
3190{
3191 struct b43_phy *phy = &dev->phy;
3192
3193 if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI))
3194 return;
3195
3196 b43_mac_suspend(dev);
3197 b43_calc_nrssi_slope(dev);
3198 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
3199 u8 old_chan = phy->channel;
3200
3201 /* VCO Calibration */
3202 if (old_chan >= 8)
3203 b43_switch_channel(dev, 1);
3204 else
3205 b43_switch_channel(dev, 13);
3206 b43_switch_channel(dev, old_chan);
3207 }
3208 b43_mac_enable(dev);
3209}
3210
3211const struct b43_phy_operations b43_phyops_g = {
3212 .allocate = b43_gphy_op_allocate,
3213 .prepare = b43_gphy_op_prepare,
3214 .init = b43_gphy_op_init,
3215 .exit = b43_gphy_op_exit,
3216 .phy_read = b43_gphy_op_read,
3217 .phy_write = b43_gphy_op_write,
3218 .radio_read = b43_gphy_op_radio_read,
3219 .radio_write = b43_gphy_op_radio_write,
3220 .supports_hwpctl = b43_gphy_op_supports_hwpctl,
3221 .software_rfkill = b43_gphy_op_software_rfkill,
3222 .switch_channel = b43_gphy_op_switch_channel,
3223 .get_default_chan = b43_gphy_op_get_default_chan,
3224 .set_rx_antenna = b43_gphy_op_set_rx_antenna,
3225 .interf_mitigation = b43_gphy_op_interf_mitigation,
3226 .xmitpower = b43_gphy_op_xmitpower,
3227 .pwork_15sec = b43_gphy_op_pwork_15sec,
3228 .pwork_60sec = b43_gphy_op_pwork_60sec,
3229};
Linux kernel - Deliverables
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