[deliverable/linux.git] / drivers / net / wireless / b43 / pio.h

#ifndef B43_PIO_H_
#define B43_PIO_H_

#include "b43.h"

#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/skbuff.h>


/*** Registers for PIO queues up to revision 7. ***/
/* TX queue. */
#define B43_PIO_TXCTL			0x00
#define  B43_PIO_TXCTL_WRITELO		0x0001
#define  B43_PIO_TXCTL_WRITEHI		0x0002
#define  B43_PIO_TXCTL_EOF		0x0004
#define  B43_PIO_TXCTL_FREADY		0x0008
#define  B43_PIO_TXCTL_FLUSHREQ		0x0020
#define  B43_PIO_TXCTL_FLUSHPEND	0x0040
#define  B43_PIO_TXCTL_SUSPREQ		0x0080
#define  B43_PIO_TXCTL_QSUSP		0x0100
#define  B43_PIO_TXCTL_COMMCNT		0xFC00
#define  B43_PIO_TXCTL_COMMCNT_SHIFT	10
#define B43_PIO_TXDATA			0x02
#define B43_PIO_TXQBUFSIZE		0x04
/* RX queue. */
#define B43_PIO_RXCTL			0x00
#define  B43_PIO_RXCTL_FRAMERDY		0x0001
#define  B43_PIO_RXCTL_DATARDY		0x0002
#define B43_PIO_RXDATA			0x02

/*** Registers for PIO queues revision 8 and later. ***/
/* TX queue */
#define B43_PIO8_TXCTL			0x00
#define  B43_PIO8_TXCTL_0_7		0x00000001
#define  B43_PIO8_TXCTL_8_15		0x00000002
#define  B43_PIO8_TXCTL_16_23		0x00000004
#define  B43_PIO8_TXCTL_24_31		0x00000008
#define  B43_PIO8_TXCTL_EOF		0x00000010
#define  B43_PIO8_TXCTL_FREADY		0x00000080
#define  B43_PIO8_TXCTL_SUSPREQ		0x00000100
#define  B43_PIO8_TXCTL_QSUSP		0x00000200
#define  B43_PIO8_TXCTL_FLUSHREQ	0x00000400
#define  B43_PIO8_TXCTL_FLUSHPEND	0x00000800
#define B43_PIO8_TXDATA			0x04
/* RX queue */
#define B43_PIO8_RXCTL			0x00
#define  B43_PIO8_RXCTL_FRAMERDY	0x00000001
#define  B43_PIO8_RXCTL_DATARDY		0x00000002
#define B43_PIO8_RXDATA			0x04


/* The maximum number of TX-packets the HW can handle. */
#define B43_PIO_MAX_NR_TXPACKETS	32


struct b43_pio_txpacket {
	/* Pointer to the TX queue we belong to. */
	struct b43_pio_txqueue *queue;
	/* The TX data packet. */
	struct sk_buff *skb;
	/* Index in the (struct b43_pio_txqueue)->packets array. */
	u8 index;

	struct list_head list;
};

struct b43_pio_txqueue {
	struct b43_wldev *dev;
	u16 mmio_base;

	/* The device queue buffer size in bytes. */
	u16 buffer_size;
	/* The number of used bytes in the device queue buffer. */
	u16 buffer_used;
	/* The number of packets that can still get queued.
	 * This is decremented on queueing a packet and incremented
	 * after receiving the transmit status. */
	u16 free_packet_slots;

	/* True, if the mac80211 queue was stopped due to overflow at TX. */
	bool stopped;
	/* Our b43 queue index number */
	u8 index;
	/* The mac80211 QoS queue priority. */
	u8 queue_prio;

	/* Buffer for TX packet meta data. */
	struct b43_pio_txpacket packets[B43_PIO_MAX_NR_TXPACKETS];
	struct list_head packets_list;

	/* Shortcut to the 802.11 core revision. This is to
	 * avoid horrible pointer dereferencing in the fastpaths. */
	u8 rev;
};

struct b43_pio_rxqueue {
	struct b43_wldev *dev;
	u16 mmio_base;

	/* Shortcut to the 802.11 core revision. This is to
	 * avoid horrible pointer dereferencing in the fastpaths. */
	u8 rev;
};


static inline u16 b43_piotx_read16(struct b43_pio_txqueue *q, u16 offset)
{
	return b43_read16(q->dev, q->mmio_base + offset);
}

static inline u32 b43_piotx_read32(struct b43_pio_txqueue *q, u16 offset)
{
	return b43_read32(q->dev, q->mmio_base + offset);
}

static inline void b43_piotx_write16(struct b43_pio_txqueue *q,
				     u16 offset, u16 value)
{
	b43_write16(q->dev, q->mmio_base + offset, value);
}

static inline void b43_piotx_write32(struct b43_pio_txqueue *q,
				     u16 offset, u32 value)
{
	b43_write32(q->dev, q->mmio_base + offset, value);
}


static inline u16 b43_piorx_read16(struct b43_pio_rxqueue *q, u16 offset)
{
	return b43_read16(q->dev, q->mmio_base + offset);
}

static inline u32 b43_piorx_read32(struct b43_pio_rxqueue *q, u16 offset)
{
	return b43_read32(q->dev, q->mmio_base + offset);
}

static inline void b43_piorx_write16(struct b43_pio_rxqueue *q,
				     u16 offset, u16 value)
{
	b43_write16(q->dev, q->mmio_base + offset, value);
}

static inline void b43_piorx_write32(struct b43_pio_rxqueue *q,
				     u16 offset, u32 value)
{
	b43_write32(q->dev, q->mmio_base + offset, value);
}


int b43_pio_init(struct b43_wldev *dev);
void b43_pio_free(struct b43_wldev *dev);

int b43_pio_tx(struct b43_wldev *dev, struct sk_buff *skb);
void b43_pio_handle_txstatus(struct b43_wldev *dev,
			     const struct b43_txstatus *status);
void b43_pio_rx(struct b43_pio_rxqueue *q);

void b43_pio_tx_suspend(struct b43_wldev *dev);
void b43_pio_tx_resume(struct b43_wldev *dev);

#endif /* B43_PIO_H_ */
Commit	Line	Data
5100d5ac MB	1	#ifndef B43_PIO_H_
	2	#define B43_PIO_H_
	3
	4	#include "b43.h"
	5
	6	#include <linux/interrupt.h>
	7	#include <linux/io.h>
	8	#include <linux/list.h>
	9	#include <linux/skbuff.h>
	10
	11
	12	/* Registers for PIO queues up to revision 7. */
	13	/* TX queue. */
	14	#define B43_PIO_TXCTL 0x00
	15	#define B43_PIO_TXCTL_WRITELO 0x0001
	16	#define B43_PIO_TXCTL_WRITEHI 0x0002
	17	#define B43_PIO_TXCTL_EOF 0x0004
	18	#define B43_PIO_TXCTL_FREADY 0x0008
	19	#define B43_PIO_TXCTL_FLUSHREQ 0x0020
	20	#define B43_PIO_TXCTL_FLUSHPEND 0x0040
	21	#define B43_PIO_TXCTL_SUSPREQ 0x0080
	22	#define B43_PIO_TXCTL_QSUSP 0x0100
	23	#define B43_PIO_TXCTL_COMMCNT 0xFC00
	24	#define B43_PIO_TXCTL_COMMCNT_SHIFT 10
	25	#define B43_PIO_TXDATA 0x02
	26	#define B43_PIO_TXQBUFSIZE 0x04
	27	/* RX queue. */
	28	#define B43_PIO_RXCTL 0x00
	29	#define B43_PIO_RXCTL_FRAMERDY 0x0001
	30	#define B43_PIO_RXCTL_DATARDY 0x0002
	31	#define B43_PIO_RXDATA 0x02
	32
	33	/* Registers for PIO queues revision 8 and later. */
	34	/* TX queue */
	35	#define B43_PIO8_TXCTL 0x00
	36	#define B43_PIO8_TXCTL_0_7 0x00000001
	37	#define B43_PIO8_TXCTL_8_15 0x00000002
	38	#define B43_PIO8_TXCTL_16_23 0x00000004
	39	#define B43_PIO8_TXCTL_24_31 0x00000008
	40	#define B43_PIO8_TXCTL_EOF 0x00000010
	41	#define B43_PIO8_TXCTL_FREADY 0x00000080
	42	#define B43_PIO8_TXCTL_SUSPREQ 0x00000100
	43	#define B43_PIO8_TXCTL_QSUSP 0x00000200
	44	#define B43_PIO8_TXCTL_FLUSHREQ 0x00000400
	45	#define B43_PIO8_TXCTL_FLUSHPEND 0x00000800
	46	#define B43_PIO8_TXDATA 0x04
	47	/* RX queue */
	48	#define B43_PIO8_RXCTL 0x00
	49	#define B43_PIO8_RXCTL_FRAMERDY 0x00000001
	50	#define B43_PIO8_RXCTL_DATARDY 0x00000002
	51	#define B43_PIO8_RXDATA 0x04
	52
	53
	54	/* The maximum number of TX-packets the HW can handle. */
	55	#define B43_PIO_MAX_NR_TXPACKETS 32
	56
	57
5100d5ac MB	58	struct b43_pio_txpacket {
	59	/* Pointer to the TX queue we belong to. */
	60	struct b43_pio_txqueue *queue;
	61	/* The TX data packet. */
	62	struct sk_buff *skb;
5100d5ac MB	63	/* Index in the (struct b43_pio_txqueue)->packets array. */
	64	u8 index;
	65
	66	struct list_head list;
	67	};
	68
	69	struct b43_pio_txqueue {
	70	struct b43_wldev *dev;
5100d5ac MB	71	u16 mmio_base;
	72
	73	/* The device queue buffer size in bytes. */
	74	u16 buffer_size;
	75	/* The number of used bytes in the device queue buffer. */
	76	u16 buffer_used;
	77	/* The number of packets that can still get queued.
	78	* This is decremented on queueing a packet and incremented
	79	* after receiving the transmit status. */
	80	u16 free_packet_slots;
	81
	82	/* True, if the mac80211 queue was stopped due to overflow at TX. */
	83	bool stopped;
	84	/* Our b43 queue index number */
	85	u8 index;
	86	/* The mac80211 QoS queue priority. */
	87	u8 queue_prio;
	88
	89	/* Buffer for TX packet meta data. */
	90	struct b43_pio_txpacket packets[B43_PIO_MAX_NR_TXPACKETS];
	91	struct list_head packets_list;
	92
5100d5ac MB	93	/* Shortcut to the 802.11 core revision. This is to
	94	* avoid horrible pointer dereferencing in the fastpaths. */
	95	u8 rev;
	96	};
	97
	98	struct b43_pio_rxqueue {
	99	struct b43_wldev *dev;
5100d5ac MB	100	u16 mmio_base;
5100d5ac MB	101
5100d5ac MB	102	/* Shortcut to the 802.11 core revision. This is to
	103	* avoid horrible pointer dereferencing in the fastpaths. */
	104	u8 rev;
	105	};
	106
	107
	108	static inline u16 b43_piotx_read16(struct b43_pio_txqueue *q, u16 offset)
	109	{
	110	return b43_read16(q->dev, q->mmio_base + offset);
	111	}
	112
	113	static inline u32 b43_piotx_read32(struct b43_pio_txqueue *q, u16 offset)
	114	{
	115	return b43_read32(q->dev, q->mmio_base + offset);
	116	}
	117
	118	static inline void b43_piotx_write16(struct b43_pio_txqueue *q,
	119	u16 offset, u16 value)
	120	{
	121	b43_write16(q->dev, q->mmio_base + offset, value);
	122	}
	123
	124	static inline void b43_piotx_write32(struct b43_pio_txqueue *q,
	125	u16 offset, u32 value)
	126	{
	127	b43_write32(q->dev, q->mmio_base + offset, value);
	128	}
	129
	130
	131	static inline u16 b43_piorx_read16(struct b43_pio_rxqueue *q, u16 offset)
	132	{
	133	return b43_read16(q->dev, q->mmio_base + offset);
	134	}
	135
	136	static inline u32 b43_piorx_read32(struct b43_pio_rxqueue *q, u16 offset)
	137	{
	138	return b43_read32(q->dev, q->mmio_base + offset);
	139	}
	140
	141	static inline void b43_piorx_write16(struct b43_pio_rxqueue *q,
	142	u16 offset, u16 value)
	143	{
	144	b43_write16(q->dev, q->mmio_base + offset, value);
	145	}
	146
	147	static inline void b43_piorx_write32(struct b43_pio_rxqueue *q,
	148	u16 offset, u32 value)
	149	{
	150	b43_write32(q->dev, q->mmio_base + offset, value);
	151	}
	152
	153
	154	int b43_pio_init(struct b43_wldev *dev);
5100d5ac MB	155	void b43_pio_free(struct b43_wldev *dev);
5100d5ac MB	156
e039fa4a	157	int b43_pio_tx(struct b43_wldev dev, struct sk_buff skb);
5100d5ac MB	158	void b43_pio_handle_txstatus(struct b43_wldev *dev,
5100d5ac MB	159	const struct b43_txstatus *status);
5100d5ac MB	160	void b43_pio_rx(struct b43_pio_rxqueue *q);
	161
	162	void b43_pio_tx_suspend(struct b43_wldev *dev);
	163	void b43_pio_tx_resume(struct b43_wldev *dev);
	164
5100d5ac	165	#endif /* B43_PIO_H_ */