Commit | Line | Data |
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e4d6b795 MB |
1 | #ifndef B43_XMIT_H_ |
2 | #define B43_XMIT_H_ | |
3 | ||
4 | #include "main.h" | |
f54a5202 MB |
5 | #include <net/mac80211.h> |
6 | ||
e4d6b795 MB |
7 | |
8 | #define _b43_declare_plcp_hdr(size) \ | |
9 | struct b43_plcp_hdr##size { \ | |
10 | union { \ | |
11 | __le32 data; \ | |
12 | __u8 raw[size]; \ | |
ba2d3587 ED |
13 | } __packed; \ |
14 | } __packed | |
e4d6b795 MB |
15 | |
16 | /* struct b43_plcp_hdr4 */ | |
17 | _b43_declare_plcp_hdr(4); | |
18 | /* struct b43_plcp_hdr6 */ | |
19 | _b43_declare_plcp_hdr(6); | |
20 | ||
21 | #undef _b43_declare_plcp_hdr | |
22 | ||
23 | /* TX header for v4 firmware */ | |
eb189d8b MB |
24 | struct b43_txhdr { |
25 | __le32 mac_ctl; /* MAC TX control */ | |
26 | __le16 mac_frame_ctl; /* Copy of the FrameControl field */ | |
e4d6b795 | 27 | __le16 tx_fes_time_norm; /* TX FES Time Normal */ |
eb189d8b MB |
28 | __le16 phy_ctl; /* PHY TX control */ |
29 | __le16 phy_ctl1; /* PHY TX control word 1 */ | |
30 | __le16 phy_ctl1_fb; /* PHY TX control word 1 for fallback rates */ | |
31 | __le16 phy_ctl1_rts; /* PHY TX control word 1 RTS */ | |
32 | __le16 phy_ctl1_rts_fb; /* PHY TX control word 1 RTS for fallback rates */ | |
33 | __u8 phy_rate; /* PHY rate */ | |
34 | __u8 phy_rate_rts; /* PHY rate for RTS/CTS */ | |
35 | __u8 extra_ft; /* Extra Frame Types */ | |
36 | __u8 chan_radio_code; /* Channel Radio Code */ | |
37 | __u8 iv[16]; /* Encryption IV */ | |
38 | __u8 tx_receiver[6]; /* TX Frame Receiver address */ | |
39 | __le16 tx_fes_time_fb; /* TX FES Time Fallback */ | |
40 | struct b43_plcp_hdr6 rts_plcp_fb; /* RTS fallback PLCP header */ | |
41 | __le16 rts_dur_fb; /* RTS fallback duration */ | |
42 | struct b43_plcp_hdr6 plcp_fb; /* Fallback PLCP header */ | |
43 | __le16 dur_fb; /* Fallback duration */ | |
44 | __le16 mimo_modelen; /* MIMO mode length */ | |
45 | __le16 mimo_ratelen_fb; /* MIMO fallback rate length */ | |
46 | __le32 timeout; /* Timeout */ | |
47 | ||
48 | union { | |
5d852905 RM |
49 | /* Tested with 598.314, 644.1001 and 666.2 */ |
50 | struct { | |
51 | __le16 mimo_antenna; /* MIMO antenna select */ | |
52 | __le16 preload_size; /* Preload size */ | |
53 | PAD_BYTES(2); | |
54 | __le16 cookie; /* TX frame cookie */ | |
55 | __le16 tx_status; /* TX status */ | |
56 | __le16 max_n_mpdus; | |
57 | __le16 max_a_bytes_mrt; | |
58 | __le16 max_a_bytes_fbr; | |
59 | __le16 min_m_bytes; | |
60 | struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */ | |
61 | __u8 rts_frame[16]; /* The RTS frame (if used) */ | |
62 | PAD_BYTES(2); | |
63 | struct b43_plcp_hdr6 plcp; /* Main PLCP header */ | |
64 | } format_598 __packed; | |
65 | ||
2391b7e8 | 66 | /* Tested with 410.2160, 478.104 and 508.* */ |
eb189d8b MB |
67 | struct { |
68 | __le16 mimo_antenna; /* MIMO antenna select */ | |
69 | __le16 preload_size; /* Preload size */ | |
70 | PAD_BYTES(2); | |
71 | __le16 cookie; /* TX frame cookie */ | |
72 | __le16 tx_status; /* TX status */ | |
73 | struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */ | |
74 | __u8 rts_frame[16]; /* The RTS frame (if used) */ | |
75 | PAD_BYTES(2); | |
76 | struct b43_plcp_hdr6 plcp; /* Main PLCP header */ | |
2391b7e8 | 77 | } format_410 __packed; |
eb189d8b | 78 | |
2391b7e8 | 79 | /* Tested with 351.126 */ |
eb189d8b MB |
80 | struct { |
81 | PAD_BYTES(2); | |
82 | __le16 cookie; /* TX frame cookie */ | |
83 | __le16 tx_status; /* TX status */ | |
84 | struct b43_plcp_hdr6 rts_plcp; /* RTS PLCP header */ | |
85 | __u8 rts_frame[16]; /* The RTS frame (if used) */ | |
86 | PAD_BYTES(2); | |
87 | struct b43_plcp_hdr6 plcp; /* Main PLCP header */ | |
2391b7e8 | 88 | } format_351 __packed; |
eb189d8b | 89 | |
ba2d3587 ED |
90 | } __packed; |
91 | } __packed; | |
e4d6b795 | 92 | |
3311abbb RM |
93 | struct b43_tx_legacy_rate_phy_ctl_entry { |
94 | u8 bitrate; | |
95 | u16 coding_rate; | |
96 | u16 modulation; | |
97 | }; | |
98 | ||
e4d6b795 | 99 | /* MAC TX control */ |
eb189d8b MB |
100 | #define B43_TXH_MAC_USEFBR 0x10000000 /* Use fallback rate for this AMPDU */ |
101 | #define B43_TXH_MAC_KEYIDX 0x0FF00000 /* Security key index */ | |
102 | #define B43_TXH_MAC_KEYIDX_SHIFT 20 | |
103 | #define B43_TXH_MAC_KEYALG 0x00070000 /* Security key algorithm */ | |
104 | #define B43_TXH_MAC_KEYALG_SHIFT 16 | |
105 | #define B43_TXH_MAC_AMIC 0x00008000 /* AMIC */ | |
106 | #define B43_TXH_MAC_RIFS 0x00004000 /* Use RIFS */ | |
107 | #define B43_TXH_MAC_LIFETIME 0x00002000 /* Lifetime */ | |
108 | #define B43_TXH_MAC_FRAMEBURST 0x00001000 /* Frameburst */ | |
109 | #define B43_TXH_MAC_SENDCTS 0x00000800 /* Send CTS-to-self */ | |
110 | #define B43_TXH_MAC_AMPDU 0x00000600 /* AMPDU status */ | |
111 | #define B43_TXH_MAC_AMPDU_MPDU 0x00000000 /* Regular MPDU, not an AMPDU */ | |
112 | #define B43_TXH_MAC_AMPDU_FIRST 0x00000200 /* First MPDU or AMPDU */ | |
113 | #define B43_TXH_MAC_AMPDU_INTER 0x00000400 /* Intermediate MPDU or AMPDU */ | |
114 | #define B43_TXH_MAC_AMPDU_LAST 0x00000600 /* Last (or only) MPDU of AMPDU */ | |
115 | #define B43_TXH_MAC_40MHZ 0x00000100 /* Use 40 MHz bandwidth */ | |
116 | #define B43_TXH_MAC_5GHZ 0x00000080 /* 5GHz band */ | |
117 | #define B43_TXH_MAC_DFCS 0x00000040 /* DFCS */ | |
118 | #define B43_TXH_MAC_IGNPMQ 0x00000020 /* Ignore PMQ */ | |
119 | #define B43_TXH_MAC_HWSEQ 0x00000010 /* Use Hardware Sequence Number */ | |
120 | #define B43_TXH_MAC_STMSDU 0x00000008 /* Start MSDU */ | |
121 | #define B43_TXH_MAC_SENDRTS 0x00000004 /* Send RTS */ | |
122 | #define B43_TXH_MAC_LONGFRAME 0x00000002 /* Long frame */ | |
123 | #define B43_TXH_MAC_ACK 0x00000001 /* Immediate ACK */ | |
e4d6b795 MB |
124 | |
125 | /* Extra Frame Types */ | |
eb189d8b MB |
126 | #define B43_TXH_EFT_FB 0x03 /* Data frame fallback encoding */ |
127 | #define B43_TXH_EFT_FB_CCK 0x00 /* CCK */ | |
128 | #define B43_TXH_EFT_FB_OFDM 0x01 /* OFDM */ | |
129 | #define B43_TXH_EFT_FB_EWC 0x02 /* EWC */ | |
130 | #define B43_TXH_EFT_FB_N 0x03 /* N */ | |
131 | #define B43_TXH_EFT_RTS 0x0C /* RTS/CTS encoding */ | |
132 | #define B43_TXH_EFT_RTS_CCK 0x00 /* CCK */ | |
133 | #define B43_TXH_EFT_RTS_OFDM 0x04 /* OFDM */ | |
134 | #define B43_TXH_EFT_RTS_EWC 0x08 /* EWC */ | |
135 | #define B43_TXH_EFT_RTS_N 0x0C /* N */ | |
136 | #define B43_TXH_EFT_RTSFB 0x30 /* RTS/CTS fallback encoding */ | |
137 | #define B43_TXH_EFT_RTSFB_CCK 0x00 /* CCK */ | |
138 | #define B43_TXH_EFT_RTSFB_OFDM 0x10 /* OFDM */ | |
139 | #define B43_TXH_EFT_RTSFB_EWC 0x20 /* EWC */ | |
140 | #define B43_TXH_EFT_RTSFB_N 0x30 /* N */ | |
e4d6b795 MB |
141 | |
142 | /* PHY TX control word */ | |
eb189d8b MB |
143 | #define B43_TXH_PHY_ENC 0x0003 /* Data frame encoding */ |
144 | #define B43_TXH_PHY_ENC_CCK 0x0000 /* CCK */ | |
145 | #define B43_TXH_PHY_ENC_OFDM 0x0001 /* OFDM */ | |
146 | #define B43_TXH_PHY_ENC_EWC 0x0002 /* EWC */ | |
147 | #define B43_TXH_PHY_ENC_N 0x0003 /* N */ | |
148 | #define B43_TXH_PHY_SHORTPRMBL 0x0010 /* Use short preamble */ | |
149 | #define B43_TXH_PHY_ANT 0x03C0 /* Antenna selection */ | |
150 | #define B43_TXH_PHY_ANT0 0x0000 /* Use antenna 0 */ | |
151 | #define B43_TXH_PHY_ANT1 0x0040 /* Use antenna 1 */ | |
152 | #define B43_TXH_PHY_ANT01AUTO 0x00C0 /* Use antenna 0/1 auto */ | |
153 | #define B43_TXH_PHY_ANT2 0x0100 /* Use antenna 2 */ | |
154 | #define B43_TXH_PHY_ANT3 0x0200 /* Use antenna 3 */ | |
155 | #define B43_TXH_PHY_TXPWR 0xFC00 /* TX power */ | |
156 | #define B43_TXH_PHY_TXPWR_SHIFT 10 | |
157 | ||
158 | /* PHY TX control word 1 */ | |
159 | #define B43_TXH_PHY1_BW 0x0007 /* Bandwidth */ | |
160 | #define B43_TXH_PHY1_BW_10 0x0000 /* 10 MHz */ | |
161 | #define B43_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */ | |
162 | #define B43_TXH_PHY1_BW_20 0x0002 /* 20 MHz */ | |
163 | #define B43_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */ | |
164 | #define B43_TXH_PHY1_BW_40 0x0004 /* 40 MHz */ | |
165 | #define B43_TXH_PHY1_BW_40DUP 0x0005 /* 50 MHz duplicate */ | |
166 | #define B43_TXH_PHY1_MODE 0x0038 /* Mode */ | |
167 | #define B43_TXH_PHY1_MODE_SISO 0x0000 /* SISO */ | |
168 | #define B43_TXH_PHY1_MODE_CDD 0x0008 /* CDD */ | |
169 | #define B43_TXH_PHY1_MODE_STBC 0x0010 /* STBC */ | |
170 | #define B43_TXH_PHY1_MODE_SDM 0x0018 /* SDM */ | |
171 | #define B43_TXH_PHY1_CRATE 0x0700 /* Coding rate */ | |
172 | #define B43_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */ | |
173 | #define B43_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */ | |
174 | #define B43_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */ | |
175 | #define B43_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */ | |
176 | #define B43_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */ | |
177 | #define B43_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */ | |
178 | #define B43_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */ | |
179 | #define B43_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */ | |
180 | #define B43_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */ | |
181 | #define B43_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */ | |
182 | #define B43_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */ | |
183 | #define B43_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */ | |
184 | ||
185 | ||
eb189d8b MB |
186 | static inline |
187 | size_t b43_txhdr_size(struct b43_wldev *dev) | |
188 | { | |
efe0249b | 189 | switch (dev->fw.hdr_format) { |
5d852905 RM |
190 | case B43_FW_HDR_598: |
191 | return 112 + sizeof(struct b43_plcp_hdr6); | |
efe0249b RM |
192 | case B43_FW_HDR_410: |
193 | return 104 + sizeof(struct b43_plcp_hdr6); | |
194 | case B43_FW_HDR_351: | |
eb189d8b | 195 | return 100 + sizeof(struct b43_plcp_hdr6); |
efe0249b RM |
196 | } |
197 | return 0; | |
eb189d8b MB |
198 | } |
199 | ||
e4d6b795 | 200 | |
09552ccd MB |
201 | int b43_generate_txhdr(struct b43_wldev *dev, |
202 | u8 * txhdr, | |
035d0243 | 203 | struct sk_buff *skb_frag, |
e6a9854b | 204 | struct ieee80211_tx_info *txctl, u16 cookie); |
e4d6b795 MB |
205 | |
206 | /* Transmit Status */ | |
207 | struct b43_txstatus { | |
208 | u16 cookie; /* The cookie from the txhdr */ | |
209 | u16 seq; /* Sequence number */ | |
210 | u8 phy_stat; /* PHY TX status */ | |
211 | u8 frame_count; /* Frame transmit count */ | |
212 | u8 rts_count; /* RTS transmit count */ | |
213 | u8 supp_reason; /* Suppression reason */ | |
214 | /* flags */ | |
215 | u8 pm_indicated; /* PM mode indicated to AP */ | |
216 | u8 intermediate; /* Intermediate status notification (not final) */ | |
217 | u8 for_ampdu; /* Status is for an AMPDU (afterburner) */ | |
218 | u8 acked; /* Wireless ACK received */ | |
219 | }; | |
220 | ||
221 | /* txstatus supp_reason values */ | |
222 | enum { | |
223 | B43_TXST_SUPP_NONE, /* Not suppressed */ | |
224 | B43_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */ | |
225 | B43_TXST_SUPP_FLUSH, /* Suppressed due to flush request */ | |
226 | B43_TXST_SUPP_PREV, /* Previous fragment failed */ | |
227 | B43_TXST_SUPP_CHAN, /* Channel mismatch */ | |
228 | B43_TXST_SUPP_LIFE, /* Lifetime expired */ | |
229 | B43_TXST_SUPP_UNDER, /* Buffer underflow */ | |
230 | B43_TXST_SUPP_ABNACK, /* Afterburner NACK */ | |
231 | }; | |
232 | ||
e4d6b795 MB |
233 | /* Receive header for v4 firmware. */ |
234 | struct b43_rxhdr_fw4 { | |
235 | __le16 frame_len; /* Frame length */ | |
236 | PAD_BYTES(2); | |
237 | __le16 phy_status0; /* PHY RX Status 0 */ | |
7b584163 MB |
238 | union { |
239 | /* RSSI for A/B/G-PHYs */ | |
240 | struct { | |
241 | __u8 jssi; /* PHY RX Status 1: JSSI */ | |
242 | __u8 sig_qual; /* PHY RX Status 1: Signal Quality */ | |
ba2d3587 | 243 | } __packed; |
7b584163 MB |
244 | |
245 | /* RSSI for N-PHYs */ | |
246 | struct { | |
247 | __s8 power0; /* PHY RX Status 1: Power 0 */ | |
248 | __s8 power1; /* PHY RX Status 1: Power 1 */ | |
ba2d3587 ED |
249 | } __packed; |
250 | } __packed; | |
e4d6b795 MB |
251 | __le16 phy_status2; /* PHY RX Status 2 */ |
252 | __le16 phy_status3; /* PHY RX Status 3 */ | |
17030f48 RM |
253 | union { |
254 | /* Tested with 598.314, 644.1001 and 666.2 */ | |
255 | struct { | |
256 | __le16 phy_status4; /* PHY RX Status 4 */ | |
257 | __le16 phy_status5; /* PHY RX Status 5 */ | |
258 | __le32 mac_status; /* MAC RX status */ | |
259 | __le16 mac_time; | |
260 | __le16 channel; | |
261 | } format_598 __packed; | |
262 | ||
263 | /* Tested with 351.126, 410.2160, 478.104 and 508.* */ | |
264 | struct { | |
265 | __le32 mac_status; /* MAC RX status */ | |
266 | __le16 mac_time; | |
267 | __le16 channel; | |
268 | } format_351 __packed; | |
269 | } __packed; | |
ba2d3587 | 270 | } __packed; |
e4d6b795 MB |
271 | |
272 | /* PHY RX Status 0 */ | |
d987160b MB |
273 | #define B43_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */ |
274 | #define B43_RX_PHYST0_PLCPHCF 0x0200 | |
275 | #define B43_RX_PHYST0_PLCPFV 0x0100 | |
276 | #define B43_RX_PHYST0_SHORTPRMBL 0x0080 /* Received with Short Preamble */ | |
e4d6b795 | 277 | #define B43_RX_PHYST0_LCRS 0x0040 |
d987160b MB |
278 | #define B43_RX_PHYST0_ANT 0x0020 /* Antenna */ |
279 | #define B43_RX_PHYST0_UNSRATE 0x0010 | |
e4d6b795 MB |
280 | #define B43_RX_PHYST0_CLIP 0x000C |
281 | #define B43_RX_PHYST0_CLIP_SHIFT 2 | |
d987160b MB |
282 | #define B43_RX_PHYST0_FTYPE 0x0003 /* Frame type */ |
283 | #define B43_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */ | |
284 | #define B43_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */ | |
285 | #define B43_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */ | |
286 | #define B43_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */ | |
e4d6b795 MB |
287 | |
288 | /* PHY RX Status 2 */ | |
d987160b | 289 | #define B43_RX_PHYST2_LNAG 0xC000 /* LNA Gain */ |
e4d6b795 | 290 | #define B43_RX_PHYST2_LNAG_SHIFT 14 |
d987160b | 291 | #define B43_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */ |
e4d6b795 | 292 | #define B43_RX_PHYST2_PNAG_SHIFT 10 |
d987160b | 293 | #define B43_RX_PHYST2_FOFF 0x03FF /* F offset */ |
e4d6b795 MB |
294 | |
295 | /* PHY RX Status 3 */ | |
d987160b | 296 | #define B43_RX_PHYST3_DIGG 0x1800 /* DIG Gain */ |
e4d6b795 | 297 | #define B43_RX_PHYST3_DIGG_SHIFT 11 |
d987160b | 298 | #define B43_RX_PHYST3_TRSTATE 0x0400 /* TR state */ |
e4d6b795 MB |
299 | |
300 | /* MAC RX Status */ | |
d987160b MB |
301 | #define B43_RX_MAC_RXST_VALID 0x01000000 /* PHY RXST valid */ |
302 | #define B43_RX_MAC_TKIP_MICERR 0x00100000 /* TKIP MIC error */ | |
303 | #define B43_RX_MAC_TKIP_MICATT 0x00080000 /* TKIP MIC attempted */ | |
304 | #define B43_RX_MAC_AGGTYPE 0x00060000 /* Aggregation type */ | |
305 | #define B43_RX_MAC_AGGTYPE_SHIFT 17 | |
306 | #define B43_RX_MAC_AMSDU 0x00010000 /* A-MSDU mask */ | |
307 | #define B43_RX_MAC_BEACONSENT 0x00008000 /* Beacon sent flag */ | |
308 | #define B43_RX_MAC_KEYIDX 0x000007E0 /* Key index */ | |
309 | #define B43_RX_MAC_KEYIDX_SHIFT 5 | |
310 | #define B43_RX_MAC_DECERR 0x00000010 /* Decrypt error */ | |
311 | #define B43_RX_MAC_DEC 0x00000008 /* Decryption attempted */ | |
312 | #define B43_RX_MAC_PADDING 0x00000004 /* Pad bytes present */ | |
313 | #define B43_RX_MAC_RESP 0x00000002 /* Response frame transmitted */ | |
314 | #define B43_RX_MAC_FCSERR 0x00000001 /* FCS error */ | |
e4d6b795 MB |
315 | |
316 | /* RX channel */ | |
d987160b MB |
317 | #define B43_RX_CHAN_40MHZ 0x1000 /* 40 Mhz channel width */ |
318 | #define B43_RX_CHAN_5GHZ 0x0800 /* 5 Ghz band */ | |
319 | #define B43_RX_CHAN_ID 0x07F8 /* Channel ID */ | |
320 | #define B43_RX_CHAN_ID_SHIFT 3 | |
321 | #define B43_RX_CHAN_PHYTYPE 0x0007 /* PHY type */ | |
322 | ||
e4d6b795 MB |
323 | |
324 | u8 b43_plcp_get_ratecode_cck(const u8 bitrate); | |
325 | u8 b43_plcp_get_ratecode_ofdm(const u8 bitrate); | |
326 | ||
327 | void b43_generate_plcp_hdr(struct b43_plcp_hdr4 *plcp, | |
328 | const u16 octets, const u8 bitrate); | |
329 | ||
330 | void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr); | |
331 | ||
332 | void b43_handle_txstatus(struct b43_wldev *dev, | |
333 | const struct b43_txstatus *status); | |
e6a9854b JB |
334 | bool b43_fill_txstatus_report(struct b43_wldev *dev, |
335 | struct ieee80211_tx_info *report, | |
5100d5ac | 336 | const struct b43_txstatus *status); |
e4d6b795 MB |
337 | |
338 | void b43_tx_suspend(struct b43_wldev *dev); | |
339 | void b43_tx_resume(struct b43_wldev *dev); | |
340 | ||
e4d6b795 MB |
341 | |
342 | /* Helper functions for converting the key-table index from "firmware-format" | |
343 | * to "raw-format" and back. The firmware API changed for this at some revision. | |
344 | * We need to account for that here. */ | |
345 | static inline int b43_new_kidx_api(struct b43_wldev *dev) | |
346 | { | |
347 | /* FIXME: Not sure the change was at rev 351 */ | |
348 | return (dev->fw.rev >= 351); | |
349 | } | |
350 | static inline u8 b43_kidx_to_fw(struct b43_wldev *dev, u8 raw_kidx) | |
351 | { | |
352 | u8 firmware_kidx; | |
353 | if (b43_new_kidx_api(dev)) { | |
354 | firmware_kidx = raw_kidx; | |
355 | } else { | |
356 | if (raw_kidx >= 4) /* Is per STA key? */ | |
357 | firmware_kidx = raw_kidx - 4; | |
358 | else | |
359 | firmware_kidx = raw_kidx; /* TX default key */ | |
360 | } | |
361 | return firmware_kidx; | |
362 | } | |
363 | static inline u8 b43_kidx_to_raw(struct b43_wldev *dev, u8 firmware_kidx) | |
364 | { | |
365 | u8 raw_kidx; | |
366 | if (b43_new_kidx_api(dev)) | |
367 | raw_kidx = firmware_kidx; | |
368 | else | |
369 | raw_kidx = firmware_kidx + 4; /* RX default keys or per STA keys */ | |
370 | return raw_kidx; | |
371 | } | |
372 | ||
f54a5202 MB |
373 | /* struct b43_private_tx_info - TX info private to b43. |
374 | * The structure is placed in (struct ieee80211_tx_info *)->rate_driver_data | |
375 | * | |
376 | * @bouncebuffer: DMA Bouncebuffer (if used) | |
377 | */ | |
378 | struct b43_private_tx_info { | |
379 | void *bouncebuffer; | |
380 | }; | |
381 | ||
382 | static inline struct b43_private_tx_info * | |
383 | b43_get_priv_tx_info(struct ieee80211_tx_info *info) | |
384 | { | |
385 | BUILD_BUG_ON(sizeof(struct b43_private_tx_info) > | |
386 | sizeof(info->rate_driver_data)); | |
387 | return (struct b43_private_tx_info *)info->rate_driver_data; | |
388 | } | |
389 | ||
e4d6b795 | 390 | #endif /* B43_XMIT_H_ */ |