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be663ab6 WYG |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
30 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
31 | ||
32 | #include <linux/kernel.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/pci-aspm.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/sched.h> | |
41 | #include <linux/skbuff.h> | |
42 | #include <linux/netdevice.h> | |
be663ab6 WYG |
43 | #include <linux/firmware.h> |
44 | #include <linux/etherdevice.h> | |
45 | #include <linux/if_arp.h> | |
46 | ||
47 | #include <net/mac80211.h> | |
48 | ||
49 | #include <asm/div64.h> | |
50 | ||
51 | #define DRV_NAME "iwl4965" | |
52 | ||
98613be0 | 53 | #include "common.h" |
af038f40 | 54 | #include "4965.h" |
be663ab6 | 55 | |
be663ab6 WYG |
56 | /****************************************************************************** |
57 | * | |
58 | * module boiler plate | |
59 | * | |
60 | ******************************************************************************/ | |
61 | ||
62 | /* | |
63 | * module name, copyright, version, etc. | |
64 | */ | |
65 | #define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux" | |
66 | ||
d3175167 | 67 | #ifdef CONFIG_IWLEGACY_DEBUG |
be663ab6 WYG |
68 | #define VD "d" |
69 | #else | |
70 | #define VD | |
71 | #endif | |
72 | ||
73 | #define DRV_VERSION IWLWIFI_VERSION VD | |
74 | ||
be663ab6 WYG |
75 | MODULE_DESCRIPTION(DRV_DESCRIPTION); |
76 | MODULE_VERSION(DRV_VERSION); | |
77 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); | |
78 | MODULE_LICENSE("GPL"); | |
79 | MODULE_ALIAS("iwl4965"); | |
80 | ||
e7392364 SG |
81 | void |
82 | il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status) | |
fcb74588 SG |
83 | { |
84 | if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) { | |
85 | IL_ERR("Tx flush command to flush out all frames\n"); | |
a6766ccd | 86 | if (!test_bit(S_EXIT_PENDING, &il->status)) |
fcb74588 SG |
87 | queue_work(il->workqueue, &il->tx_flush); |
88 | } | |
89 | } | |
90 | ||
91 | /* | |
92 | * EEPROM | |
93 | */ | |
94 | struct il_mod_params il4965_mod_params = { | |
95 | .amsdu_size_8K = 1, | |
96 | .restart_fw = 1, | |
97 | /* the rest are 0 by default */ | |
98 | }; | |
99 | ||
e7392364 SG |
100 | void |
101 | il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq) | |
fcb74588 SG |
102 | { |
103 | unsigned long flags; | |
104 | int i; | |
105 | spin_lock_irqsave(&rxq->lock, flags); | |
106 | INIT_LIST_HEAD(&rxq->rx_free); | |
107 | INIT_LIST_HEAD(&rxq->rx_used); | |
108 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
109 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { | |
110 | /* In the reset function, these buffers may have been allocated | |
111 | * to an SKB, so we need to unmap and free potential storage */ | |
112 | if (rxq->pool[i].page != NULL) { | |
113 | pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma, | |
e7392364 SG |
114 | PAGE_SIZE << il->hw_params.rx_page_order, |
115 | PCI_DMA_FROMDEVICE); | |
fcb74588 SG |
116 | __il_free_pages(il, rxq->pool[i].page); |
117 | rxq->pool[i].page = NULL; | |
118 | } | |
119 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
120 | } | |
121 | ||
122 | for (i = 0; i < RX_QUEUE_SIZE; i++) | |
123 | rxq->queue[i] = NULL; | |
124 | ||
125 | /* Set us so that we have processed and used all buffers, but have | |
126 | * not restocked the Rx queue with fresh buffers */ | |
127 | rxq->read = rxq->write = 0; | |
128 | rxq->write_actual = 0; | |
129 | rxq->free_count = 0; | |
130 | spin_unlock_irqrestore(&rxq->lock, flags); | |
131 | } | |
132 | ||
e7392364 SG |
133 | int |
134 | il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq) | |
fcb74588 SG |
135 | { |
136 | u32 rb_size; | |
e7392364 | 137 | const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ |
fcb74588 SG |
138 | u32 rb_timeout = 0; |
139 | ||
140 | if (il->cfg->mod_params->amsdu_size_8K) | |
9a95b370 | 141 | rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; |
fcb74588 | 142 | else |
9a95b370 | 143 | rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; |
fcb74588 SG |
144 | |
145 | /* Stop Rx DMA */ | |
9a95b370 | 146 | il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
fcb74588 SG |
147 | |
148 | /* Reset driver's Rx queue write idx */ | |
9a95b370 | 149 | il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); |
fcb74588 SG |
150 | |
151 | /* Tell device where to find RBD circular buffer in DRAM */ | |
e7392364 | 152 | il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8)); |
fcb74588 SG |
153 | |
154 | /* Tell device where in DRAM to update its Rx status */ | |
e7392364 | 155 | il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4); |
fcb74588 SG |
156 | |
157 | /* Enable Rx DMA | |
158 | * Direct rx interrupts to hosts | |
159 | * Rx buffer size 4 or 8k | |
160 | * RB timeout 0x10 | |
161 | * 256 RBDs | |
162 | */ | |
9a95b370 | 163 | il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, |
e7392364 SG |
164 | FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | |
165 | FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | | |
1722f8e1 SG |
166 | FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | |
167 | rb_size | | |
168 | (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | | |
169 | (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); | |
fcb74588 SG |
170 | |
171 | /* Set interrupt coalescing timer to default (2048 usecs) */ | |
172 | il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF); | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
e7392364 SG |
177 | static void |
178 | il4965_set_pwr_vmain(struct il_priv *il) | |
fcb74588 SG |
179 | { |
180 | /* | |
181 | * (for documentation purposes) | |
182 | * to set power to V_AUX, do: | |
183 | ||
184 | if (pci_pme_capable(il->pci_dev, PCI_D3cold)) | |
185 | il_set_bits_mask_prph(il, APMG_PS_CTRL_REG, | |
186 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, | |
187 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
188 | */ | |
189 | ||
190 | il_set_bits_mask_prph(il, APMG_PS_CTRL_REG, | |
e7392364 SG |
191 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, |
192 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
fcb74588 SG |
193 | } |
194 | ||
e7392364 SG |
195 | int |
196 | il4965_hw_nic_init(struct il_priv *il) | |
fcb74588 SG |
197 | { |
198 | unsigned long flags; | |
199 | struct il_rx_queue *rxq = &il->rxq; | |
200 | int ret; | |
201 | ||
fcb74588 | 202 | spin_lock_irqsave(&il->lock, flags); |
f03ee2a8 | 203 | il_apm_init(il); |
fcb74588 SG |
204 | /* Set interrupt coalescing calibration timer to default (512 usecs) */ |
205 | il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF); | |
fcb74588 SG |
206 | spin_unlock_irqrestore(&il->lock, flags); |
207 | ||
208 | il4965_set_pwr_vmain(il); | |
f03ee2a8 | 209 | il4965_nic_config(il); |
fcb74588 SG |
210 | |
211 | /* Allocate the RX queue, or reset if it is already allocated */ | |
212 | if (!rxq->bd) { | |
213 | ret = il_rx_queue_alloc(il); | |
214 | if (ret) { | |
215 | IL_ERR("Unable to initialize Rx queue\n"); | |
216 | return -ENOMEM; | |
217 | } | |
218 | } else | |
219 | il4965_rx_queue_reset(il, rxq); | |
220 | ||
221 | il4965_rx_replenish(il); | |
222 | ||
223 | il4965_rx_init(il, rxq); | |
224 | ||
225 | spin_lock_irqsave(&il->lock, flags); | |
226 | ||
227 | rxq->need_update = 1; | |
228 | il_rx_queue_update_write_ptr(il, rxq); | |
229 | ||
230 | spin_unlock_irqrestore(&il->lock, flags); | |
231 | ||
232 | /* Allocate or reset and init all Tx and Command queues */ | |
233 | if (!il->txq) { | |
234 | ret = il4965_txq_ctx_alloc(il); | |
235 | if (ret) | |
236 | return ret; | |
237 | } else | |
238 | il4965_txq_ctx_reset(il); | |
239 | ||
a6766ccd | 240 | set_bit(S_INIT, &il->status); |
fcb74588 SG |
241 | |
242 | return 0; | |
243 | } | |
244 | ||
245 | /** | |
246 | * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr | |
247 | */ | |
e7392364 SG |
248 | static inline __le32 |
249 | il4965_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr) | |
fcb74588 | 250 | { |
e7392364 | 251 | return cpu_to_le32((u32) (dma_addr >> 8)); |
fcb74588 SG |
252 | } |
253 | ||
254 | /** | |
255 | * il4965_rx_queue_restock - refill RX queue from pre-allocated pool | |
256 | * | |
257 | * If there are slots in the RX queue that need to be restocked, | |
258 | * and we have free pre-allocated buffers, fill the ranks as much | |
259 | * as we can, pulling from rx_free. | |
260 | * | |
261 | * This moves the 'write' idx forward to catch up with 'processed', and | |
262 | * also updates the memory address in the firmware to reference the new | |
263 | * target buffer. | |
264 | */ | |
e7392364 SG |
265 | void |
266 | il4965_rx_queue_restock(struct il_priv *il) | |
fcb74588 SG |
267 | { |
268 | struct il_rx_queue *rxq = &il->rxq; | |
269 | struct list_head *element; | |
270 | struct il_rx_buf *rxb; | |
271 | unsigned long flags; | |
272 | ||
273 | spin_lock_irqsave(&rxq->lock, flags); | |
274 | while (il_rx_queue_space(rxq) > 0 && rxq->free_count) { | |
275 | /* The overwritten rxb must be a used one */ | |
276 | rxb = rxq->queue[rxq->write]; | |
277 | BUG_ON(rxb && rxb->page); | |
278 | ||
279 | /* Get next free Rx buffer, remove from free list */ | |
280 | element = rxq->rx_free.next; | |
281 | rxb = list_entry(element, struct il_rx_buf, list); | |
282 | list_del(element); | |
283 | ||
284 | /* Point to Rx buffer via next RBD in circular buffer */ | |
e7392364 SG |
285 | rxq->bd[rxq->write] = |
286 | il4965_dma_addr2rbd_ptr(il, rxb->page_dma); | |
fcb74588 SG |
287 | rxq->queue[rxq->write] = rxb; |
288 | rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; | |
289 | rxq->free_count--; | |
290 | } | |
291 | spin_unlock_irqrestore(&rxq->lock, flags); | |
292 | /* If the pre-allocated buffer pool is dropping low, schedule to | |
293 | * refill it */ | |
294 | if (rxq->free_count <= RX_LOW_WATERMARK) | |
295 | queue_work(il->workqueue, &il->rx_replenish); | |
296 | ||
fcb74588 SG |
297 | /* If we've added more space for the firmware to place data, tell it. |
298 | * Increment device's write pointer in multiples of 8. */ | |
299 | if (rxq->write_actual != (rxq->write & ~0x7)) { | |
300 | spin_lock_irqsave(&rxq->lock, flags); | |
301 | rxq->need_update = 1; | |
302 | spin_unlock_irqrestore(&rxq->lock, flags); | |
303 | il_rx_queue_update_write_ptr(il, rxq); | |
304 | } | |
305 | } | |
306 | ||
307 | /** | |
308 | * il4965_rx_replenish - Move all used packet from rx_used to rx_free | |
309 | * | |
310 | * When moving to rx_free an SKB is allocated for the slot. | |
311 | * | |
312 | * Also restock the Rx queue via il_rx_queue_restock. | |
313 | * This is called as a scheduled work item (except for during initialization) | |
314 | */ | |
e7392364 SG |
315 | static void |
316 | il4965_rx_allocate(struct il_priv *il, gfp_t priority) | |
fcb74588 SG |
317 | { |
318 | struct il_rx_queue *rxq = &il->rxq; | |
319 | struct list_head *element; | |
320 | struct il_rx_buf *rxb; | |
321 | struct page *page; | |
322 | unsigned long flags; | |
323 | gfp_t gfp_mask = priority; | |
324 | ||
325 | while (1) { | |
326 | spin_lock_irqsave(&rxq->lock, flags); | |
327 | if (list_empty(&rxq->rx_used)) { | |
328 | spin_unlock_irqrestore(&rxq->lock, flags); | |
329 | return; | |
330 | } | |
331 | spin_unlock_irqrestore(&rxq->lock, flags); | |
332 | ||
333 | if (rxq->free_count > RX_LOW_WATERMARK) | |
334 | gfp_mask |= __GFP_NOWARN; | |
335 | ||
336 | if (il->hw_params.rx_page_order > 0) | |
337 | gfp_mask |= __GFP_COMP; | |
338 | ||
339 | /* Alloc a new receive buffer */ | |
340 | page = alloc_pages(gfp_mask, il->hw_params.rx_page_order); | |
341 | if (!page) { | |
342 | if (net_ratelimit()) | |
e7392364 SG |
343 | D_INFO("alloc_pages failed, " "order: %d\n", |
344 | il->hw_params.rx_page_order); | |
fcb74588 SG |
345 | |
346 | if (rxq->free_count <= RX_LOW_WATERMARK && | |
347 | net_ratelimit()) | |
e7392364 SG |
348 | IL_ERR("Failed to alloc_pages with %s. " |
349 | "Only %u free buffers remaining.\n", | |
350 | priority == | |
351 | GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL", | |
352 | rxq->free_count); | |
fcb74588 SG |
353 | /* We don't reschedule replenish work here -- we will |
354 | * call the restock method and if it still needs | |
355 | * more buffers it will schedule replenish */ | |
356 | return; | |
357 | } | |
358 | ||
359 | spin_lock_irqsave(&rxq->lock, flags); | |
360 | ||
361 | if (list_empty(&rxq->rx_used)) { | |
362 | spin_unlock_irqrestore(&rxq->lock, flags); | |
363 | __free_pages(page, il->hw_params.rx_page_order); | |
364 | return; | |
365 | } | |
366 | element = rxq->rx_used.next; | |
367 | rxb = list_entry(element, struct il_rx_buf, list); | |
368 | list_del(element); | |
369 | ||
370 | spin_unlock_irqrestore(&rxq->lock, flags); | |
371 | ||
372 | BUG_ON(rxb->page); | |
373 | rxb->page = page; | |
374 | /* Get physical address of the RB */ | |
e7392364 SG |
375 | rxb->page_dma = |
376 | pci_map_page(il->pci_dev, page, 0, | |
377 | PAGE_SIZE << il->hw_params.rx_page_order, | |
378 | PCI_DMA_FROMDEVICE); | |
fcb74588 SG |
379 | /* dma address must be no more than 36 bits */ |
380 | BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36)); | |
381 | /* and also 256 byte aligned! */ | |
382 | BUG_ON(rxb->page_dma & DMA_BIT_MASK(8)); | |
383 | ||
384 | spin_lock_irqsave(&rxq->lock, flags); | |
385 | ||
386 | list_add_tail(&rxb->list, &rxq->rx_free); | |
387 | rxq->free_count++; | |
388 | il->alloc_rxb_page++; | |
389 | ||
390 | spin_unlock_irqrestore(&rxq->lock, flags); | |
391 | } | |
392 | } | |
393 | ||
e7392364 SG |
394 | void |
395 | il4965_rx_replenish(struct il_priv *il) | |
fcb74588 SG |
396 | { |
397 | unsigned long flags; | |
398 | ||
399 | il4965_rx_allocate(il, GFP_KERNEL); | |
400 | ||
401 | spin_lock_irqsave(&il->lock, flags); | |
402 | il4965_rx_queue_restock(il); | |
403 | spin_unlock_irqrestore(&il->lock, flags); | |
404 | } | |
405 | ||
e7392364 SG |
406 | void |
407 | il4965_rx_replenish_now(struct il_priv *il) | |
fcb74588 SG |
408 | { |
409 | il4965_rx_allocate(il, GFP_ATOMIC); | |
410 | ||
411 | il4965_rx_queue_restock(il); | |
412 | } | |
413 | ||
414 | /* Assumes that the skb field of the buffers in 'pool' is kept accurate. | |
415 | * If an SKB has been detached, the POOL needs to have its SKB set to NULL | |
416 | * This free routine walks the list of POOL entries and if SKB is set to | |
417 | * non NULL it is unmapped and freed | |
418 | */ | |
e7392364 SG |
419 | void |
420 | il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq) | |
fcb74588 SG |
421 | { |
422 | int i; | |
423 | for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { | |
424 | if (rxq->pool[i].page != NULL) { | |
425 | pci_unmap_page(il->pci_dev, rxq->pool[i].page_dma, | |
e7392364 SG |
426 | PAGE_SIZE << il->hw_params.rx_page_order, |
427 | PCI_DMA_FROMDEVICE); | |
fcb74588 SG |
428 | __il_free_pages(il, rxq->pool[i].page); |
429 | rxq->pool[i].page = NULL; | |
430 | } | |
431 | } | |
432 | ||
433 | dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
434 | rxq->bd_dma); | |
435 | dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status), | |
436 | rxq->rb_stts, rxq->rb_stts_dma); | |
437 | rxq->bd = NULL; | |
e7392364 | 438 | rxq->rb_stts = NULL; |
fcb74588 SG |
439 | } |
440 | ||
e7392364 SG |
441 | int |
442 | il4965_rxq_stop(struct il_priv *il) | |
fcb74588 | 443 | { |
775ed8ab | 444 | int ret; |
fcb74588 | 445 | |
775ed8ab SG |
446 | _il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
447 | ret = _il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG, | |
448 | FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, | |
449 | FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, | |
450 | 1000); | |
451 | if (ret < 0) | |
452 | IL_ERR("Can't stop Rx DMA.\n"); | |
fcb74588 SG |
453 | |
454 | return 0; | |
455 | } | |
456 | ||
e7392364 SG |
457 | int |
458 | il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band) | |
fcb74588 SG |
459 | { |
460 | int idx = 0; | |
461 | int band_offset = 0; | |
462 | ||
463 | /* HT rate format: mac80211 wants an MCS number, which is just LSB */ | |
464 | if (rate_n_flags & RATE_MCS_HT_MSK) { | |
465 | idx = (rate_n_flags & 0xff); | |
466 | return idx; | |
e7392364 | 467 | /* Legacy rate format, search for match in table */ |
fcb74588 SG |
468 | } else { |
469 | if (band == IEEE80211_BAND_5GHZ) | |
470 | band_offset = IL_FIRST_OFDM_RATE; | |
471 | for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++) | |
472 | if (il_rates[idx].plcp == (rate_n_flags & 0xFF)) | |
473 | return idx - band_offset; | |
474 | } | |
475 | ||
476 | return -1; | |
477 | } | |
478 | ||
e7392364 SG |
479 | static int |
480 | il4965_calc_rssi(struct il_priv *il, struct il_rx_phy_res *rx_resp) | |
fcb74588 SG |
481 | { |
482 | /* data from PHY/DSP regarding signal strength, etc., | |
483 | * contents are always there, not configurable by host. */ | |
484 | struct il4965_rx_non_cfg_phy *ncphy = | |
485 | (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf; | |
e7392364 SG |
486 | u32 agc = |
487 | (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK) >> | |
488 | IL49_AGC_DB_POS; | |
fcb74588 SG |
489 | |
490 | u32 valid_antennae = | |
491 | (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK) | |
e7392364 | 492 | >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET; |
fcb74588 SG |
493 | u8 max_rssi = 0; |
494 | u32 i; | |
495 | ||
496 | /* Find max rssi among 3 possible receivers. | |
497 | * These values are measured by the digital signal processor (DSP). | |
498 | * They should stay fairly constant even as the signal strength varies, | |
499 | * if the radio's automatic gain control (AGC) is working right. | |
500 | * AGC value (see below) will provide the "interesting" info. */ | |
501 | for (i = 0; i < 3; i++) | |
502 | if (valid_antennae & (1 << i)) | |
503 | max_rssi = max(ncphy->rssi_info[i << 1], max_rssi); | |
504 | ||
505 | D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", | |
506 | ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4], | |
507 | max_rssi, agc); | |
508 | ||
509 | /* dBm = max_rssi dB - agc dB - constant. | |
510 | * Higher AGC (higher radio gain) means lower signal. */ | |
511 | return max_rssi - agc - IL4965_RSSI_OFFSET; | |
512 | } | |
513 | ||
e7392364 SG |
514 | static u32 |
515 | il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in) | |
fcb74588 SG |
516 | { |
517 | u32 decrypt_out = 0; | |
518 | ||
519 | if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) == | |
e7392364 SG |
520 | RX_RES_STATUS_STATION_FOUND) |
521 | decrypt_out |= | |
522 | (RX_RES_STATUS_STATION_FOUND | | |
523 | RX_RES_STATUS_NO_STATION_INFO_MISMATCH); | |
fcb74588 SG |
524 | |
525 | decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK); | |
526 | ||
527 | /* packet was not encrypted */ | |
528 | if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == | |
e7392364 | 529 | RX_RES_STATUS_SEC_TYPE_NONE) |
fcb74588 SG |
530 | return decrypt_out; |
531 | ||
532 | /* packet was encrypted with unknown alg */ | |
533 | if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == | |
e7392364 | 534 | RX_RES_STATUS_SEC_TYPE_ERR) |
fcb74588 SG |
535 | return decrypt_out; |
536 | ||
537 | /* decryption was not done in HW */ | |
538 | if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) != | |
e7392364 | 539 | RX_MPDU_RES_STATUS_DEC_DONE_MSK) |
fcb74588 SG |
540 | return decrypt_out; |
541 | ||
542 | switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) { | |
543 | ||
544 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
545 | /* alg is CCM: check MIC only */ | |
546 | if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK)) | |
547 | /* Bad MIC */ | |
548 | decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; | |
549 | else | |
550 | decrypt_out |= RX_RES_STATUS_DECRYPT_OK; | |
551 | ||
552 | break; | |
553 | ||
554 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
555 | if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) { | |
556 | /* Bad TTAK */ | |
557 | decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK; | |
558 | break; | |
559 | } | |
560 | /* fall through if TTAK OK */ | |
561 | default: | |
562 | if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK)) | |
563 | decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; | |
564 | else | |
565 | decrypt_out |= RX_RES_STATUS_DECRYPT_OK; | |
566 | break; | |
567 | } | |
568 | ||
e7392364 | 569 | D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", decrypt_in, decrypt_out); |
fcb74588 SG |
570 | |
571 | return decrypt_out; | |
572 | } | |
573 | ||
e7392364 SG |
574 | static void |
575 | il4965_pass_packet_to_mac80211(struct il_priv *il, struct ieee80211_hdr *hdr, | |
576 | u16 len, u32 ampdu_status, struct il_rx_buf *rxb, | |
577 | struct ieee80211_rx_status *stats) | |
fcb74588 SG |
578 | { |
579 | struct sk_buff *skb; | |
580 | __le16 fc = hdr->frame_control; | |
581 | ||
582 | /* We only process data packets if the interface is open */ | |
583 | if (unlikely(!il->is_open)) { | |
e7392364 | 584 | D_DROP("Dropping packet while interface is not open.\n"); |
fcb74588 SG |
585 | return; |
586 | } | |
587 | ||
588 | /* In case of HW accelerated crypto and bad decryption, drop */ | |
589 | if (!il->cfg->mod_params->sw_crypto && | |
590 | il_set_decrypted_flag(il, hdr, ampdu_status, stats)) | |
591 | return; | |
592 | ||
593 | skb = dev_alloc_skb(128); | |
594 | if (!skb) { | |
595 | IL_ERR("dev_alloc_skb failed\n"); | |
596 | return; | |
597 | } | |
598 | ||
50269e19 ED |
599 | skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len, |
600 | len); | |
fcb74588 SG |
601 | |
602 | il_update_stats(il, false, fc, len); | |
603 | memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats)); | |
604 | ||
605 | ieee80211_rx(il->hw, skb); | |
606 | il->alloc_rxb_page--; | |
607 | rxb->page = NULL; | |
608 | } | |
609 | ||
4d69c752 SG |
610 | /* Called for N_RX (legacy ABG frames), or |
611 | * N_RX_MPDU (HT high-throughput N frames). */ | |
e7392364 SG |
612 | void |
613 | il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb) | |
fcb74588 SG |
614 | { |
615 | struct ieee80211_hdr *header; | |
616 | struct ieee80211_rx_status rx_status; | |
617 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
618 | struct il_rx_phy_res *phy_res; | |
619 | __le32 rx_pkt_status; | |
620 | struct il_rx_mpdu_res_start *amsdu; | |
621 | u32 len; | |
622 | u32 ampdu_status; | |
623 | u32 rate_n_flags; | |
624 | ||
625 | /** | |
4d69c752 SG |
626 | * N_RX and N_RX_MPDU are handled differently. |
627 | * N_RX: physical layer info is in this buffer | |
628 | * N_RX_MPDU: physical layer info was sent in separate | |
fcb74588 SG |
629 | * command and cached in il->last_phy_res |
630 | * | |
631 | * Here we set up local variables depending on which command is | |
632 | * received. | |
633 | */ | |
4d69c752 | 634 | if (pkt->hdr.cmd == N_RX) { |
fcb74588 | 635 | phy_res = (struct il_rx_phy_res *)pkt->u.raw; |
e7392364 SG |
636 | header = |
637 | (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) + | |
638 | phy_res->cfg_phy_cnt); | |
fcb74588 SG |
639 | |
640 | len = le16_to_cpu(phy_res->byte_count); | |
e7392364 SG |
641 | rx_pkt_status = |
642 | *(__le32 *) (pkt->u.raw + sizeof(*phy_res) + | |
643 | phy_res->cfg_phy_cnt + len); | |
fcb74588 SG |
644 | ampdu_status = le32_to_cpu(rx_pkt_status); |
645 | } else { | |
646 | if (!il->_4965.last_phy_res_valid) { | |
647 | IL_ERR("MPDU frame without cached PHY data\n"); | |
648 | return; | |
649 | } | |
650 | phy_res = &il->_4965.last_phy_res; | |
651 | amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw; | |
652 | header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu)); | |
653 | len = le16_to_cpu(amsdu->byte_count); | |
e7392364 SG |
654 | rx_pkt_status = *(__le32 *) (pkt->u.raw + sizeof(*amsdu) + len); |
655 | ampdu_status = | |
656 | il4965_translate_rx_status(il, le32_to_cpu(rx_pkt_status)); | |
fcb74588 SG |
657 | } |
658 | ||
659 | if ((unlikely(phy_res->cfg_phy_cnt > 20))) { | |
660 | D_DROP("dsp size out of range [0,20]: %d/n", | |
e7392364 | 661 | phy_res->cfg_phy_cnt); |
fcb74588 SG |
662 | return; |
663 | } | |
664 | ||
665 | if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) || | |
666 | !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) { | |
e7392364 | 667 | D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status)); |
fcb74588 SG |
668 | return; |
669 | } | |
670 | ||
671 | /* This will be used in several places later */ | |
672 | rate_n_flags = le32_to_cpu(phy_res->rate_n_flags); | |
673 | ||
674 | /* rx_status carries information about the packet to mac80211 */ | |
675 | rx_status.mactime = le64_to_cpu(phy_res->timestamp); | |
e7392364 SG |
676 | rx_status.band = |
677 | (phy_res-> | |
678 | phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? IEEE80211_BAND_2GHZ : | |
679 | IEEE80211_BAND_5GHZ; | |
fcb74588 | 680 | rx_status.freq = |
e7392364 SG |
681 | ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel), |
682 | rx_status.band); | |
fcb74588 | 683 | rx_status.rate_idx = |
e7392364 | 684 | il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band); |
fcb74588 SG |
685 | rx_status.flag = 0; |
686 | ||
687 | /* TSF isn't reliable. In order to allow smooth user experience, | |
688 | * this W/A doesn't propagate it to the mac80211 */ | |
e7392364 | 689 | /*rx_status.flag |= RX_FLAG_MACTIME_MPDU; */ |
fcb74588 SG |
690 | |
691 | il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp); | |
692 | ||
693 | /* Find max signal strength (dBm) among 3 antenna/receiver chains */ | |
694 | rx_status.signal = il4965_calc_rssi(il, phy_res); | |
695 | ||
e7392364 SG |
696 | D_STATS("Rssi %d, TSF %llu\n", rx_status.signal, |
697 | (unsigned long long)rx_status.mactime); | |
fcb74588 SG |
698 | |
699 | /* | |
700 | * "antenna number" | |
701 | * | |
702 | * It seems that the antenna field in the phy flags value | |
703 | * is actually a bit field. This is undefined by radiotap, | |
704 | * it wants an actual antenna number but I always get "7" | |
705 | * for most legacy frames I receive indicating that the | |
706 | * same frame was received on all three RX chains. | |
707 | * | |
708 | * I think this field should be removed in favor of a | |
709 | * new 802.11n radiotap field "RX chains" that is defined | |
710 | * as a bitmask. | |
711 | */ | |
712 | rx_status.antenna = | |
e7392364 SG |
713 | (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> |
714 | RX_RES_PHY_FLAGS_ANTENNA_POS; | |
fcb74588 SG |
715 | |
716 | /* set the preamble flag if appropriate */ | |
717 | if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK) | |
718 | rx_status.flag |= RX_FLAG_SHORTPRE; | |
719 | ||
720 | /* Set up the HT phy flags */ | |
721 | if (rate_n_flags & RATE_MCS_HT_MSK) | |
722 | rx_status.flag |= RX_FLAG_HT; | |
723 | if (rate_n_flags & RATE_MCS_HT40_MSK) | |
724 | rx_status.flag |= RX_FLAG_40MHZ; | |
725 | if (rate_n_flags & RATE_MCS_SGI_MSK) | |
726 | rx_status.flag |= RX_FLAG_SHORT_GI; | |
727 | ||
e7392364 SG |
728 | il4965_pass_packet_to_mac80211(il, header, len, ampdu_status, rxb, |
729 | &rx_status); | |
fcb74588 SG |
730 | } |
731 | ||
4d69c752 | 732 | /* Cache phy data (Rx signal strength, etc) for HT frame (N_RX_PHY). |
6e9848b4 | 733 | * This will be used later in il_hdl_rx() for N_RX_MPDU. */ |
e7392364 SG |
734 | void |
735 | il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb) | |
fcb74588 SG |
736 | { |
737 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
738 | il->_4965.last_phy_res_valid = true; | |
739 | memcpy(&il->_4965.last_phy_res, pkt->u.raw, | |
740 | sizeof(struct il_rx_phy_res)); | |
741 | } | |
742 | ||
e7392364 SG |
743 | static int |
744 | il4965_get_channels_for_scan(struct il_priv *il, struct ieee80211_vif *vif, | |
745 | enum ieee80211_band band, u8 is_active, | |
746 | u8 n_probes, struct il_scan_channel *scan_ch) | |
fcb74588 SG |
747 | { |
748 | struct ieee80211_channel *chan; | |
749 | const struct ieee80211_supported_band *sband; | |
750 | const struct il_channel_info *ch_info; | |
751 | u16 passive_dwell = 0; | |
752 | u16 active_dwell = 0; | |
753 | int added, i; | |
754 | u16 channel; | |
755 | ||
756 | sband = il_get_hw_mode(il, band); | |
757 | if (!sband) | |
758 | return 0; | |
759 | ||
760 | active_dwell = il_get_active_dwell_time(il, band, n_probes); | |
761 | passive_dwell = il_get_passive_dwell_time(il, band, vif); | |
762 | ||
763 | if (passive_dwell <= active_dwell) | |
764 | passive_dwell = active_dwell + 1; | |
765 | ||
766 | for (i = 0, added = 0; i < il->scan_request->n_channels; i++) { | |
767 | chan = il->scan_request->channels[i]; | |
768 | ||
769 | if (chan->band != band) | |
770 | continue; | |
771 | ||
772 | channel = chan->hw_value; | |
773 | scan_ch->channel = cpu_to_le16(channel); | |
774 | ||
775 | ch_info = il_get_channel_info(il, band, channel); | |
776 | if (!il_is_channel_valid(ch_info)) { | |
e7392364 SG |
777 | D_SCAN("Channel %d is INVALID for this band.\n", |
778 | channel); | |
fcb74588 SG |
779 | continue; |
780 | } | |
781 | ||
782 | if (!is_active || il_is_channel_passive(ch_info) || | |
783 | (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) | |
784 | scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE; | |
785 | else | |
786 | scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE; | |
787 | ||
788 | if (n_probes) | |
789 | scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes); | |
790 | ||
791 | scan_ch->active_dwell = cpu_to_le16(active_dwell); | |
792 | scan_ch->passive_dwell = cpu_to_le16(passive_dwell); | |
793 | ||
794 | /* Set txpower levels to defaults */ | |
795 | scan_ch->dsp_atten = 110; | |
796 | ||
797 | /* NOTE: if we were doing 6Mb OFDM for scans we'd use | |
798 | * power level: | |
799 | * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3; | |
800 | */ | |
801 | if (band == IEEE80211_BAND_5GHZ) | |
802 | scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3; | |
803 | else | |
804 | scan_ch->tx_gain = ((1 << 5) | (5 << 3)); | |
805 | ||
e7392364 SG |
806 | D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel, |
807 | le32_to_cpu(scan_ch->type), | |
808 | (scan_ch-> | |
809 | type & SCAN_CHANNEL_TYPE_ACTIVE) ? "ACTIVE" : "PASSIVE", | |
810 | (scan_ch-> | |
811 | type & SCAN_CHANNEL_TYPE_ACTIVE) ? active_dwell : | |
812 | passive_dwell); | |
fcb74588 SG |
813 | |
814 | scan_ch++; | |
815 | added++; | |
816 | } | |
817 | ||
818 | D_SCAN("total channels to scan %d\n", added); | |
819 | return added; | |
820 | } | |
821 | ||
a0c1ef3b SG |
822 | static void |
823 | il4965_toggle_tx_ant(struct il_priv *il, u8 *ant, u8 valid) | |
824 | { | |
825 | int i; | |
826 | u8 ind = *ant; | |
827 | ||
828 | for (i = 0; i < RATE_ANT_NUM - 1; i++) { | |
829 | ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0; | |
830 | if (valid & BIT(ind)) { | |
831 | *ant = ind; | |
832 | return; | |
833 | } | |
834 | } | |
835 | } | |
836 | ||
e7392364 SG |
837 | int |
838 | il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif) | |
fcb74588 SG |
839 | { |
840 | struct il_host_cmd cmd = { | |
4d69c752 | 841 | .id = C_SCAN, |
fcb74588 SG |
842 | .len = sizeof(struct il_scan_cmd), |
843 | .flags = CMD_SIZE_HUGE, | |
844 | }; | |
845 | struct il_scan_cmd *scan; | |
fcb74588 SG |
846 | u32 rate_flags = 0; |
847 | u16 cmd_len; | |
848 | u16 rx_chain = 0; | |
849 | enum ieee80211_band band; | |
850 | u8 n_probes = 0; | |
851 | u8 rx_ant = il->hw_params.valid_rx_ant; | |
852 | u8 rate; | |
853 | bool is_active = false; | |
e7392364 | 854 | int chan_mod; |
fcb74588 SG |
855 | u8 active_chains; |
856 | u8 scan_tx_antennas = il->hw_params.valid_tx_ant; | |
857 | int ret; | |
858 | ||
859 | lockdep_assert_held(&il->mutex); | |
860 | ||
fcb74588 | 861 | if (!il->scan_cmd) { |
e7392364 SG |
862 | il->scan_cmd = |
863 | kmalloc(sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE, | |
864 | GFP_KERNEL); | |
fcb74588 | 865 | if (!il->scan_cmd) { |
e7392364 | 866 | D_SCAN("fail to allocate memory for scan\n"); |
fcb74588 SG |
867 | return -ENOMEM; |
868 | } | |
869 | } | |
870 | scan = il->scan_cmd; | |
871 | memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE); | |
872 | ||
873 | scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH; | |
874 | scan->quiet_time = IL_ACTIVE_QUIET_TIME; | |
875 | ||
876 | if (il_is_any_associated(il)) { | |
877 | u16 interval; | |
878 | u32 extra; | |
879 | u32 suspend_time = 100; | |
880 | u32 scan_suspend_time = 100; | |
881 | ||
882 | D_INFO("Scanning while associated...\n"); | |
883 | interval = vif->bss_conf.beacon_int; | |
884 | ||
885 | scan->suspend_time = 0; | |
886 | scan->max_out_time = cpu_to_le32(200 * 1024); | |
887 | if (!interval) | |
888 | interval = suspend_time; | |
889 | ||
890 | extra = (suspend_time / interval) << 22; | |
e7392364 SG |
891 | scan_suspend_time = |
892 | (extra | ((suspend_time % interval) * 1024)); | |
fcb74588 SG |
893 | scan->suspend_time = cpu_to_le32(scan_suspend_time); |
894 | D_SCAN("suspend_time 0x%X beacon interval %d\n", | |
e7392364 | 895 | scan_suspend_time, interval); |
fcb74588 SG |
896 | } |
897 | ||
898 | if (il->scan_request->n_ssids) { | |
899 | int i, p = 0; | |
900 | D_SCAN("Kicking off active scan\n"); | |
901 | for (i = 0; i < il->scan_request->n_ssids; i++) { | |
902 | /* always does wildcard anyway */ | |
903 | if (!il->scan_request->ssids[i].ssid_len) | |
904 | continue; | |
905 | scan->direct_scan[p].id = WLAN_EID_SSID; | |
906 | scan->direct_scan[p].len = | |
e7392364 | 907 | il->scan_request->ssids[i].ssid_len; |
fcb74588 SG |
908 | memcpy(scan->direct_scan[p].ssid, |
909 | il->scan_request->ssids[i].ssid, | |
910 | il->scan_request->ssids[i].ssid_len); | |
911 | n_probes++; | |
912 | p++; | |
913 | } | |
914 | is_active = true; | |
915 | } else | |
916 | D_SCAN("Start passive scan.\n"); | |
917 | ||
918 | scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; | |
b16db50a | 919 | scan->tx_cmd.sta_id = il->hw_params.bcast_id; |
fcb74588 SG |
920 | scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
921 | ||
922 | switch (il->scan_band) { | |
923 | case IEEE80211_BAND_2GHZ: | |
924 | scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; | |
e7392364 | 925 | chan_mod = |
c8b03958 | 926 | le32_to_cpu(il->active.flags & RXON_FLG_CHANNEL_MODE_MSK) >> |
e7392364 | 927 | RXON_FLG_CHANNEL_MODE_POS; |
fcb74588 SG |
928 | if (chan_mod == CHANNEL_MODE_PURE_40) { |
929 | rate = RATE_6M_PLCP; | |
930 | } else { | |
931 | rate = RATE_1M_PLCP; | |
932 | rate_flags = RATE_MCS_CCK_MSK; | |
933 | } | |
934 | break; | |
935 | case IEEE80211_BAND_5GHZ: | |
936 | rate = RATE_6M_PLCP; | |
937 | break; | |
938 | default: | |
939 | IL_WARN("Invalid scan band\n"); | |
940 | return -EIO; | |
941 | } | |
942 | ||
943 | /* | |
944 | * If active scanning is requested but a certain channel is | |
945 | * marked passive, we can do active scanning if we detect | |
946 | * transmissions. | |
947 | * | |
948 | * There is an issue with some firmware versions that triggers | |
949 | * a sysassert on a "good CRC threshold" of zero (== disabled), | |
950 | * on a radar channel even though this means that we should NOT | |
951 | * send probes. | |
952 | * | |
953 | * The "good CRC threshold" is the number of frames that we | |
954 | * need to receive during our dwell time on a channel before | |
955 | * sending out probes -- setting this to a huge value will | |
956 | * mean we never reach it, but at the same time work around | |
957 | * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER | |
958 | * here instead of IL_GOOD_CRC_TH_DISABLED. | |
959 | */ | |
e7392364 SG |
960 | scan->good_CRC_th = |
961 | is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER; | |
fcb74588 SG |
962 | |
963 | band = il->scan_band; | |
964 | ||
965 | if (il->cfg->scan_rx_antennas[band]) | |
966 | rx_ant = il->cfg->scan_rx_antennas[band]; | |
967 | ||
a0c1ef3b | 968 | il4965_toggle_tx_ant(il, &il->scan_tx_ant[band], scan_tx_antennas); |
616107ed SG |
969 | rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS; |
970 | scan->tx_cmd.rate_n_flags = cpu_to_le32(rate | rate_flags); | |
fcb74588 SG |
971 | |
972 | /* In power save mode use one chain, otherwise use all chains */ | |
a6766ccd | 973 | if (test_bit(S_POWER_PMI, &il->status)) { |
fcb74588 | 974 | /* rx_ant has been set to all valid chains previously */ |
e7392364 SG |
975 | active_chains = |
976 | rx_ant & ((u8) (il->chain_noise_data.active_chains)); | |
fcb74588 SG |
977 | if (!active_chains) |
978 | active_chains = rx_ant; | |
979 | ||
980 | D_SCAN("chain_noise_data.active_chains: %u\n", | |
e7392364 | 981 | il->chain_noise_data.active_chains); |
fcb74588 SG |
982 | |
983 | rx_ant = il4965_first_antenna(active_chains); | |
984 | } | |
985 | ||
986 | /* MIMO is not used here, but value is required */ | |
987 | rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS; | |
988 | rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS; | |
989 | rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS; | |
990 | rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS; | |
991 | scan->rx_chain = cpu_to_le16(rx_chain); | |
992 | ||
e7392364 SG |
993 | cmd_len = |
994 | il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data, | |
995 | vif->addr, il->scan_request->ie, | |
996 | il->scan_request->ie_len, | |
997 | IL_MAX_SCAN_SIZE - sizeof(*scan)); | |
fcb74588 SG |
998 | scan->tx_cmd.len = cpu_to_le16(cmd_len); |
999 | ||
e7392364 SG |
1000 | scan->filter_flags |= |
1001 | (RXON_FILTER_ACCEPT_GRP_MSK | RXON_FILTER_BCON_AWARE_MSK); | |
fcb74588 | 1002 | |
e7392364 SG |
1003 | scan->channel_count = |
1004 | il4965_get_channels_for_scan(il, vif, band, is_active, n_probes, | |
1005 | (void *)&scan->data[cmd_len]); | |
fcb74588 SG |
1006 | if (scan->channel_count == 0) { |
1007 | D_SCAN("channel count %d\n", scan->channel_count); | |
1008 | return -EIO; | |
1009 | } | |
1010 | ||
e7392364 SG |
1011 | cmd.len += |
1012 | le16_to_cpu(scan->tx_cmd.len) + | |
fcb74588 SG |
1013 | scan->channel_count * sizeof(struct il_scan_channel); |
1014 | cmd.data = scan; | |
1015 | scan->len = cpu_to_le16(cmd.len); | |
1016 | ||
a6766ccd | 1017 | set_bit(S_SCAN_HW, &il->status); |
fcb74588 SG |
1018 | |
1019 | ret = il_send_cmd_sync(il, &cmd); | |
1020 | if (ret) | |
a6766ccd | 1021 | clear_bit(S_SCAN_HW, &il->status); |
fcb74588 SG |
1022 | |
1023 | return ret; | |
1024 | } | |
1025 | ||
e7392364 SG |
1026 | int |
1027 | il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif, | |
1028 | bool add) | |
fcb74588 SG |
1029 | { |
1030 | struct il_vif_priv *vif_priv = (void *)vif->drv_priv; | |
1031 | ||
1032 | if (add) | |
83007196 | 1033 | return il4965_add_bssid_station(il, vif->bss_conf.bssid, |
fcb74588 SG |
1034 | &vif_priv->ibss_bssid_sta_id); |
1035 | return il_remove_station(il, vif_priv->ibss_bssid_sta_id, | |
e7392364 | 1036 | vif->bss_conf.bssid); |
fcb74588 SG |
1037 | } |
1038 | ||
e7392364 SG |
1039 | void |
1040 | il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, int freed) | |
fcb74588 SG |
1041 | { |
1042 | lockdep_assert_held(&il->sta_lock); | |
1043 | ||
1044 | if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed) | |
1045 | il->stations[sta_id].tid[tid].tfds_in_queue -= freed; | |
1046 | else { | |
1047 | D_TX("free more than tfds_in_queue (%u:%d)\n", | |
e7392364 | 1048 | il->stations[sta_id].tid[tid].tfds_in_queue, freed); |
fcb74588 SG |
1049 | il->stations[sta_id].tid[tid].tfds_in_queue = 0; |
1050 | } | |
1051 | } | |
1052 | ||
1053 | #define IL_TX_QUEUE_MSK 0xfffff | |
1054 | ||
e7392364 SG |
1055 | static bool |
1056 | il4965_is_single_rx_stream(struct il_priv *il) | |
fcb74588 SG |
1057 | { |
1058 | return il->current_ht_config.smps == IEEE80211_SMPS_STATIC || | |
e7392364 | 1059 | il->current_ht_config.single_chain_sufficient; |
fcb74588 SG |
1060 | } |
1061 | ||
1062 | #define IL_NUM_RX_CHAINS_MULTIPLE 3 | |
1063 | #define IL_NUM_RX_CHAINS_SINGLE 2 | |
1064 | #define IL_NUM_IDLE_CHAINS_DUAL 2 | |
1065 | #define IL_NUM_IDLE_CHAINS_SINGLE 1 | |
1066 | ||
1067 | /* | |
1068 | * Determine how many receiver/antenna chains to use. | |
1069 | * | |
1070 | * More provides better reception via diversity. Fewer saves power | |
1071 | * at the expense of throughput, but only when not in powersave to | |
1072 | * start with. | |
1073 | * | |
1074 | * MIMO (dual stream) requires at least 2, but works better with 3. | |
1075 | * This does not determine *which* chains to use, just how many. | |
1076 | */ | |
e7392364 SG |
1077 | static int |
1078 | il4965_get_active_rx_chain_count(struct il_priv *il) | |
fcb74588 SG |
1079 | { |
1080 | /* # of Rx chains to use when expecting MIMO. */ | |
1081 | if (il4965_is_single_rx_stream(il)) | |
1082 | return IL_NUM_RX_CHAINS_SINGLE; | |
1083 | else | |
1084 | return IL_NUM_RX_CHAINS_MULTIPLE; | |
1085 | } | |
1086 | ||
1087 | /* | |
1088 | * When we are in power saving mode, unless device support spatial | |
1089 | * multiplexing power save, use the active count for rx chain count. | |
1090 | */ | |
1091 | static int | |
1092 | il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt) | |
1093 | { | |
1094 | /* # Rx chains when idling, depending on SMPS mode */ | |
1095 | switch (il->current_ht_config.smps) { | |
1096 | case IEEE80211_SMPS_STATIC: | |
1097 | case IEEE80211_SMPS_DYNAMIC: | |
1098 | return IL_NUM_IDLE_CHAINS_SINGLE; | |
1099 | case IEEE80211_SMPS_OFF: | |
1100 | return active_cnt; | |
1101 | default: | |
e7392364 | 1102 | WARN(1, "invalid SMPS mode %d", il->current_ht_config.smps); |
fcb74588 SG |
1103 | return active_cnt; |
1104 | } | |
1105 | } | |
1106 | ||
1107 | /* up to 4 chains */ | |
e7392364 SG |
1108 | static u8 |
1109 | il4965_count_chain_bitmap(u32 chain_bitmap) | |
fcb74588 SG |
1110 | { |
1111 | u8 res; | |
1112 | res = (chain_bitmap & BIT(0)) >> 0; | |
1113 | res += (chain_bitmap & BIT(1)) >> 1; | |
1114 | res += (chain_bitmap & BIT(2)) >> 2; | |
1115 | res += (chain_bitmap & BIT(3)) >> 3; | |
1116 | return res; | |
1117 | } | |
1118 | ||
1119 | /** | |
1120 | * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image | |
1121 | * | |
1122 | * Selects how many and which Rx receivers/antennas/chains to use. | |
1123 | * This should not be used for scan command ... it puts data in wrong place. | |
1124 | */ | |
e7392364 | 1125 | void |
83007196 | 1126 | il4965_set_rxon_chain(struct il_priv *il) |
fcb74588 SG |
1127 | { |
1128 | bool is_single = il4965_is_single_rx_stream(il); | |
a6766ccd | 1129 | bool is_cam = !test_bit(S_POWER_PMI, &il->status); |
fcb74588 SG |
1130 | u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt; |
1131 | u32 active_chains; | |
1132 | u16 rx_chain; | |
1133 | ||
1134 | /* Tell uCode which antennas are actually connected. | |
1135 | * Before first association, we assume all antennas are connected. | |
1136 | * Just after first association, il4965_chain_noise_calibration() | |
1137 | * checks which antennas actually *are* connected. */ | |
1138 | if (il->chain_noise_data.active_chains) | |
1139 | active_chains = il->chain_noise_data.active_chains; | |
1140 | else | |
1141 | active_chains = il->hw_params.valid_rx_ant; | |
1142 | ||
1143 | rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS; | |
1144 | ||
1145 | /* How many receivers should we use? */ | |
1146 | active_rx_cnt = il4965_get_active_rx_chain_count(il); | |
1147 | idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt); | |
1148 | ||
fcb74588 SG |
1149 | /* correct rx chain count according hw settings |
1150 | * and chain noise calibration | |
1151 | */ | |
1152 | valid_rx_cnt = il4965_count_chain_bitmap(active_chains); | |
1153 | if (valid_rx_cnt < active_rx_cnt) | |
1154 | active_rx_cnt = valid_rx_cnt; | |
1155 | ||
1156 | if (valid_rx_cnt < idle_rx_cnt) | |
1157 | idle_rx_cnt = valid_rx_cnt; | |
1158 | ||
1159 | rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS; | |
e7392364 | 1160 | rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS; |
fcb74588 | 1161 | |
c8b03958 | 1162 | il->staging.rx_chain = cpu_to_le16(rx_chain); |
fcb74588 SG |
1163 | |
1164 | if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam) | |
c8b03958 | 1165 | il->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK; |
fcb74588 | 1166 | else |
c8b03958 | 1167 | il->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK; |
fcb74588 | 1168 | |
c8b03958 | 1169 | D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", il->staging.rx_chain, |
e7392364 | 1170 | active_rx_cnt, idle_rx_cnt); |
fcb74588 SG |
1171 | |
1172 | WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 || | |
1173 | active_rx_cnt < idle_rx_cnt); | |
1174 | } | |
1175 | ||
e7392364 SG |
1176 | static const char * |
1177 | il4965_get_fh_string(int cmd) | |
fcb74588 SG |
1178 | { |
1179 | switch (cmd) { | |
e7392364 SG |
1180 | IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG); |
1181 | IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG); | |
1182 | IL_CMD(FH49_RSCSR_CHNL0_WPTR); | |
1183 | IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG); | |
1184 | IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG); | |
1185 | IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG); | |
1186 | IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); | |
1187 | IL_CMD(FH49_TSSR_TX_STATUS_REG); | |
1188 | IL_CMD(FH49_TSSR_TX_ERROR_REG); | |
fcb74588 SG |
1189 | default: |
1190 | return "UNKNOWN"; | |
1191 | } | |
1192 | } | |
1193 | ||
e7392364 SG |
1194 | int |
1195 | il4965_dump_fh(struct il_priv *il, char **buf, bool display) | |
fcb74588 SG |
1196 | { |
1197 | int i; | |
1198 | #ifdef CONFIG_IWLEGACY_DEBUG | |
1199 | int pos = 0; | |
1200 | size_t bufsz = 0; | |
1201 | #endif | |
1202 | static const u32 fh_tbl[] = { | |
9a95b370 SG |
1203 | FH49_RSCSR_CHNL0_STTS_WPTR_REG, |
1204 | FH49_RSCSR_CHNL0_RBDCB_BASE_REG, | |
1205 | FH49_RSCSR_CHNL0_WPTR, | |
1206 | FH49_MEM_RCSR_CHNL0_CONFIG_REG, | |
1207 | FH49_MEM_RSSR_SHARED_CTRL_REG, | |
1208 | FH49_MEM_RSSR_RX_STATUS_REG, | |
1209 | FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, | |
1210 | FH49_TSSR_TX_STATUS_REG, | |
1211 | FH49_TSSR_TX_ERROR_REG | |
fcb74588 SG |
1212 | }; |
1213 | #ifdef CONFIG_IWLEGACY_DEBUG | |
1214 | if (display) { | |
1215 | bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; | |
1216 | *buf = kmalloc(bufsz, GFP_KERNEL); | |
1217 | if (!*buf) | |
1218 | return -ENOMEM; | |
e7392364 SG |
1219 | pos += |
1220 | scnprintf(*buf + pos, bufsz - pos, "FH register values:\n"); | |
fcb74588 | 1221 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { |
e7392364 SG |
1222 | pos += |
1223 | scnprintf(*buf + pos, bufsz - pos, | |
1224 | " %34s: 0X%08x\n", | |
1722f8e1 SG |
1225 | il4965_get_fh_string(fh_tbl[i]), |
1226 | il_rd(il, fh_tbl[i])); | |
fcb74588 SG |
1227 | } |
1228 | return pos; | |
1229 | } | |
1230 | #endif | |
1231 | IL_ERR("FH register values:\n"); | |
e7392364 SG |
1232 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { |
1233 | IL_ERR(" %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]), | |
1234 | il_rd(il, fh_tbl[i])); | |
fcb74588 SG |
1235 | } |
1236 | return 0; | |
1237 | } | |
a1751b22 | 1238 | |
e7392364 SG |
1239 | void |
1240 | il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb) | |
a1751b22 SG |
1241 | { |
1242 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
1243 | struct il_missed_beacon_notif *missed_beacon; | |
1244 | ||
1245 | missed_beacon = &pkt->u.missed_beacon; | |
1246 | if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) > | |
1247 | il->missed_beacon_threshold) { | |
e7392364 SG |
1248 | D_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n", |
1249 | le32_to_cpu(missed_beacon->consecutive_missed_beacons), | |
1250 | le32_to_cpu(missed_beacon->total_missed_becons), | |
1251 | le32_to_cpu(missed_beacon->num_recvd_beacons), | |
1252 | le32_to_cpu(missed_beacon->num_expected_beacons)); | |
a6766ccd | 1253 | if (!test_bit(S_SCANNING, &il->status)) |
a1751b22 SG |
1254 | il4965_init_sensitivity(il); |
1255 | } | |
1256 | } | |
1257 | ||
1258 | /* Calculate noise level, based on measurements during network silence just | |
1259 | * before arriving beacon. This measurement can be done only if we know | |
1260 | * exactly when to expect beacons, therefore only when we're associated. */ | |
e7392364 SG |
1261 | static void |
1262 | il4965_rx_calc_noise(struct il_priv *il) | |
a1751b22 SG |
1263 | { |
1264 | struct stats_rx_non_phy *rx_info; | |
1265 | int num_active_rx = 0; | |
1266 | int total_silence = 0; | |
1267 | int bcn_silence_a, bcn_silence_b, bcn_silence_c; | |
1268 | int last_rx_noise; | |
1269 | ||
1270 | rx_info = &(il->_4965.stats.rx.general); | |
1271 | bcn_silence_a = | |
e7392364 | 1272 | le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER; |
a1751b22 | 1273 | bcn_silence_b = |
e7392364 | 1274 | le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER; |
a1751b22 | 1275 | bcn_silence_c = |
e7392364 | 1276 | le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER; |
a1751b22 SG |
1277 | |
1278 | if (bcn_silence_a) { | |
1279 | total_silence += bcn_silence_a; | |
1280 | num_active_rx++; | |
1281 | } | |
1282 | if (bcn_silence_b) { | |
1283 | total_silence += bcn_silence_b; | |
1284 | num_active_rx++; | |
1285 | } | |
1286 | if (bcn_silence_c) { | |
1287 | total_silence += bcn_silence_c; | |
1288 | num_active_rx++; | |
1289 | } | |
1290 | ||
1291 | /* Average among active antennas */ | |
1292 | if (num_active_rx) | |
1293 | last_rx_noise = (total_silence / num_active_rx) - 107; | |
1294 | else | |
1295 | last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE; | |
1296 | ||
e7392364 SG |
1297 | D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", bcn_silence_a, |
1298 | bcn_silence_b, bcn_silence_c, last_rx_noise); | |
a1751b22 SG |
1299 | } |
1300 | ||
1301 | #ifdef CONFIG_IWLEGACY_DEBUGFS | |
1302 | /* | |
1303 | * based on the assumption of all stats counter are in DWORD | |
1304 | * FIXME: This function is for debugging, do not deal with | |
1305 | * the case of counters roll-over. | |
1306 | */ | |
e7392364 SG |
1307 | static void |
1308 | il4965_accumulative_stats(struct il_priv *il, __le32 * stats) | |
a1751b22 SG |
1309 | { |
1310 | int i, size; | |
1311 | __le32 *prev_stats; | |
1312 | u32 *accum_stats; | |
1313 | u32 *delta, *max_delta; | |
1314 | struct stats_general_common *general, *accum_general; | |
1315 | struct stats_tx *tx, *accum_tx; | |
1316 | ||
1722f8e1 SG |
1317 | prev_stats = (__le32 *) &il->_4965.stats; |
1318 | accum_stats = (u32 *) &il->_4965.accum_stats; | |
a1751b22 SG |
1319 | size = sizeof(struct il_notif_stats); |
1320 | general = &il->_4965.stats.general.common; | |
1321 | accum_general = &il->_4965.accum_stats.general.common; | |
1322 | tx = &il->_4965.stats.tx; | |
1323 | accum_tx = &il->_4965.accum_stats.tx; | |
1722f8e1 SG |
1324 | delta = (u32 *) &il->_4965.delta_stats; |
1325 | max_delta = (u32 *) &il->_4965.max_delta; | |
a1751b22 SG |
1326 | |
1327 | for (i = sizeof(__le32); i < size; | |
e7392364 SG |
1328 | i += |
1329 | sizeof(__le32), stats++, prev_stats++, delta++, max_delta++, | |
1330 | accum_stats++) { | |
a1751b22 | 1331 | if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) { |
e7392364 SG |
1332 | *delta = |
1333 | (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats)); | |
a1751b22 SG |
1334 | *accum_stats += *delta; |
1335 | if (*delta > *max_delta) | |
1336 | *max_delta = *delta; | |
1337 | } | |
1338 | } | |
1339 | ||
1340 | /* reset accumulative stats for "no-counter" type stats */ | |
1341 | accum_general->temperature = general->temperature; | |
1342 | accum_general->ttl_timestamp = general->ttl_timestamp; | |
1343 | } | |
1344 | #endif | |
1345 | ||
e7392364 SG |
1346 | void |
1347 | il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb) | |
a1751b22 | 1348 | { |
527901d0 SG |
1349 | const int recalib_seconds = 60; |
1350 | bool change; | |
a1751b22 SG |
1351 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
1352 | ||
e7392364 SG |
1353 | D_RX("Statistics notification received (%d vs %d).\n", |
1354 | (int)sizeof(struct il_notif_stats), | |
1355 | le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK); | |
1356 | ||
1357 | change = | |
1358 | ((il->_4965.stats.general.common.temperature != | |
1359 | pkt->u.stats.general.common.temperature) || | |
1360 | ((il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK) != | |
1361 | (pkt->u.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK))); | |
a1751b22 | 1362 | #ifdef CONFIG_IWLEGACY_DEBUGFS |
1722f8e1 | 1363 | il4965_accumulative_stats(il, (__le32 *) &pkt->u.stats); |
a1751b22 SG |
1364 | #endif |
1365 | ||
1366 | /* TODO: reading some of stats is unneeded */ | |
e7392364 | 1367 | memcpy(&il->_4965.stats, &pkt->u.stats, sizeof(il->_4965.stats)); |
a1751b22 | 1368 | |
db7746f7 | 1369 | set_bit(S_STATS, &il->status); |
a1751b22 | 1370 | |
527901d0 SG |
1371 | /* |
1372 | * Reschedule the stats timer to occur in recalib_seconds to ensure | |
1373 | * we get a thermal update even if the uCode doesn't give us one | |
1374 | */ | |
e7392364 | 1375 | mod_timer(&il->stats_periodic, |
527901d0 | 1376 | jiffies + msecs_to_jiffies(recalib_seconds * 1000)); |
a1751b22 | 1377 | |
a6766ccd | 1378 | if (unlikely(!test_bit(S_SCANNING, &il->status)) && |
4d69c752 | 1379 | (pkt->hdr.cmd == N_STATS)) { |
a1751b22 SG |
1380 | il4965_rx_calc_noise(il); |
1381 | queue_work(il->workqueue, &il->run_time_calib_work); | |
1382 | } | |
527901d0 SG |
1383 | |
1384 | if (change) | |
1385 | il4965_temperature_calib(il); | |
a1751b22 SG |
1386 | } |
1387 | ||
e7392364 SG |
1388 | void |
1389 | il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb) | |
a1751b22 SG |
1390 | { |
1391 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
1392 | ||
db7746f7 | 1393 | if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATS_CLEAR_MSK) { |
a1751b22 SG |
1394 | #ifdef CONFIG_IWLEGACY_DEBUGFS |
1395 | memset(&il->_4965.accum_stats, 0, | |
e7392364 | 1396 | sizeof(struct il_notif_stats)); |
a1751b22 | 1397 | memset(&il->_4965.delta_stats, 0, |
e7392364 SG |
1398 | sizeof(struct il_notif_stats)); |
1399 | memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats)); | |
a1751b22 SG |
1400 | #endif |
1401 | D_RX("Statistics have been cleared\n"); | |
1402 | } | |
d2dfb33e | 1403 | il4965_hdl_stats(il, rxb); |
a1751b22 SG |
1404 | } |
1405 | ||
8f29b456 SG |
1406 | |
1407 | /* | |
1408 | * mac80211 queues, ACs, hardware queues, FIFOs. | |
1409 | * | |
1410 | * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues | |
1411 | * | |
1412 | * Mac80211 uses the following numbers, which we get as from it | |
1413 | * by way of skb_get_queue_mapping(skb): | |
1414 | * | |
1415 | * VO 0 | |
1416 | * VI 1 | |
1417 | * BE 2 | |
1418 | * BK 3 | |
1419 | * | |
1420 | * | |
1421 | * Regular (not A-MPDU) frames are put into hardware queues corresponding | |
1422 | * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their | |
1423 | * own queue per aggregation session (RA/TID combination), such queues are | |
1424 | * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In | |
1425 | * order to map frames to the right queue, we also need an AC->hw queue | |
1426 | * mapping. This is implemented here. | |
1427 | * | |
1428 | * Due to the way hw queues are set up (by the hw specific modules like | |
af038f40 | 1429 | * 4965.c), the AC->hw queue mapping is the identity |
8f29b456 SG |
1430 | * mapping. |
1431 | */ | |
1432 | ||
a1751b22 SG |
1433 | static const u8 tid_to_ac[] = { |
1434 | IEEE80211_AC_BE, | |
1435 | IEEE80211_AC_BK, | |
1436 | IEEE80211_AC_BK, | |
1437 | IEEE80211_AC_BE, | |
1438 | IEEE80211_AC_VI, | |
1439 | IEEE80211_AC_VI, | |
1440 | IEEE80211_AC_VO, | |
1441 | IEEE80211_AC_VO | |
1442 | }; | |
1443 | ||
e7392364 SG |
1444 | static inline int |
1445 | il4965_get_ac_from_tid(u16 tid) | |
a1751b22 SG |
1446 | { |
1447 | if (likely(tid < ARRAY_SIZE(tid_to_ac))) | |
1448 | return tid_to_ac[tid]; | |
1449 | ||
1450 | /* no support for TIDs 8-15 yet */ | |
1451 | return -EINVAL; | |
1452 | } | |
1453 | ||
1454 | static inline int | |
83007196 | 1455 | il4965_get_fifo_from_tid(u16 tid) |
a1751b22 | 1456 | { |
b75b3a70 SG |
1457 | const u8 ac_to_fifo[] = { |
1458 | IL_TX_FIFO_VO, | |
1459 | IL_TX_FIFO_VI, | |
1460 | IL_TX_FIFO_BE, | |
1461 | IL_TX_FIFO_BK, | |
1462 | }; | |
1463 | ||
a1751b22 | 1464 | if (likely(tid < ARRAY_SIZE(tid_to_ac))) |
b75b3a70 | 1465 | return ac_to_fifo[tid_to_ac[tid]]; |
a1751b22 SG |
1466 | |
1467 | /* no support for TIDs 8-15 yet */ | |
1468 | return -EINVAL; | |
1469 | } | |
1470 | ||
1471 | /* | |
4d69c752 | 1472 | * handle build C_TX command notification. |
a1751b22 | 1473 | */ |
e7392364 SG |
1474 | static void |
1475 | il4965_tx_cmd_build_basic(struct il_priv *il, struct sk_buff *skb, | |
1476 | struct il_tx_cmd *tx_cmd, | |
1477 | struct ieee80211_tx_info *info, | |
1478 | struct ieee80211_hdr *hdr, u8 std_id) | |
a1751b22 SG |
1479 | { |
1480 | __le16 fc = hdr->frame_control; | |
1481 | __le32 tx_flags = tx_cmd->tx_flags; | |
1482 | ||
1483 | tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
1484 | if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { | |
1485 | tx_flags |= TX_CMD_FLG_ACK_MSK; | |
1486 | if (ieee80211_is_mgmt(fc)) | |
1487 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
1488 | if (ieee80211_is_probe_resp(fc) && | |
1489 | !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) | |
1490 | tx_flags |= TX_CMD_FLG_TSF_MSK; | |
1491 | } else { | |
1492 | tx_flags &= (~TX_CMD_FLG_ACK_MSK); | |
1493 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
1494 | } | |
1495 | ||
1496 | if (ieee80211_is_back_req(fc)) | |
1497 | tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; | |
1498 | ||
1499 | tx_cmd->sta_id = std_id; | |
1500 | if (ieee80211_has_morefrags(fc)) | |
1501 | tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; | |
1502 | ||
1503 | if (ieee80211_is_data_qos(fc)) { | |
1504 | u8 *qc = ieee80211_get_qos_ctl(hdr); | |
1505 | tx_cmd->tid_tspec = qc[0] & 0xf; | |
1506 | tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; | |
1507 | } else { | |
1508 | tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; | |
1509 | } | |
1510 | ||
1511 | il_tx_cmd_protection(il, info, fc, &tx_flags); | |
1512 | ||
1513 | tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); | |
1514 | if (ieee80211_is_mgmt(fc)) { | |
1515 | if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) | |
1516 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); | |
1517 | else | |
1518 | tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); | |
1519 | } else { | |
1520 | tx_cmd->timeout.pm_frame_timeout = 0; | |
1521 | } | |
1522 | ||
1523 | tx_cmd->driver_txop = 0; | |
1524 | tx_cmd->tx_flags = tx_flags; | |
1525 | tx_cmd->next_frame_len = 0; | |
1526 | } | |
1527 | ||
e7392364 SG |
1528 | static void |
1529 | il4965_tx_cmd_build_rate(struct il_priv *il, struct il_tx_cmd *tx_cmd, | |
1530 | struct ieee80211_tx_info *info, __le16 fc) | |
a1751b22 | 1531 | { |
616107ed | 1532 | const u8 rts_retry_limit = 60; |
a1751b22 SG |
1533 | u32 rate_flags; |
1534 | int rate_idx; | |
a1751b22 SG |
1535 | u8 data_retry_limit; |
1536 | u8 rate_plcp; | |
1537 | ||
e7392364 | 1538 | /* Set retry limit on DATA packets and Probe Responses */ |
a1751b22 SG |
1539 | if (ieee80211_is_probe_resp(fc)) |
1540 | data_retry_limit = 3; | |
1541 | else | |
1542 | data_retry_limit = IL4965_DEFAULT_TX_RETRY; | |
1543 | tx_cmd->data_retry_limit = data_retry_limit; | |
a1751b22 | 1544 | /* Set retry limit on RTS packets */ |
616107ed | 1545 | tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit); |
a1751b22 SG |
1546 | |
1547 | /* DATA packets will use the uCode station table for rate/antenna | |
1548 | * selection */ | |
1549 | if (ieee80211_is_data(fc)) { | |
1550 | tx_cmd->initial_rate_idx = 0; | |
1551 | tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; | |
1552 | return; | |
1553 | } | |
1554 | ||
1555 | /** | |
1556 | * If the current TX rate stored in mac80211 has the MCS bit set, it's | |
1557 | * not really a TX rate. Thus, we use the lowest supported rate for | |
1558 | * this band. Also use the lowest supported rate if the stored rate | |
1559 | * idx is invalid. | |
1560 | */ | |
1561 | rate_idx = info->control.rates[0].idx; | |
e7392364 SG |
1562 | if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0 |
1563 | || rate_idx > RATE_COUNT_LEGACY) | |
1564 | rate_idx = | |
1565 | rate_lowest_index(&il->bands[info->band], | |
1566 | info->control.sta); | |
a1751b22 SG |
1567 | /* For 5 GHZ band, remap mac80211 rate indices into driver indices */ |
1568 | if (info->band == IEEE80211_BAND_5GHZ) | |
1569 | rate_idx += IL_FIRST_OFDM_RATE; | |
1570 | /* Get PLCP rate for tx_cmd->rate_n_flags */ | |
1571 | rate_plcp = il_rates[rate_idx].plcp; | |
1572 | /* Zero out flags for this packet */ | |
1573 | rate_flags = 0; | |
1574 | ||
1575 | /* Set CCK flag as needed */ | |
1576 | if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE) | |
1577 | rate_flags |= RATE_MCS_CCK_MSK; | |
1578 | ||
1579 | /* Set up antennas */ | |
a0c1ef3b | 1580 | il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant); |
616107ed | 1581 | rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS; |
a1751b22 SG |
1582 | |
1583 | /* Set the rate in the TX cmd */ | |
616107ed | 1584 | tx_cmd->rate_n_flags = cpu_to_le32(rate_plcp | rate_flags); |
a1751b22 SG |
1585 | } |
1586 | ||
e7392364 SG |
1587 | static void |
1588 | il4965_tx_cmd_build_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info, | |
1589 | struct il_tx_cmd *tx_cmd, struct sk_buff *skb_frag, | |
1590 | int sta_id) | |
a1751b22 SG |
1591 | { |
1592 | struct ieee80211_key_conf *keyconf = info->control.hw_key; | |
1593 | ||
1594 | switch (keyconf->cipher) { | |
1595 | case WLAN_CIPHER_SUITE_CCMP: | |
1596 | tx_cmd->sec_ctl = TX_CMD_SEC_CCM; | |
1597 | memcpy(tx_cmd->key, keyconf->key, keyconf->keylen); | |
1598 | if (info->flags & IEEE80211_TX_CTL_AMPDU) | |
1599 | tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; | |
1600 | D_TX("tx_cmd with AES hwcrypto\n"); | |
1601 | break; | |
1602 | ||
1603 | case WLAN_CIPHER_SUITE_TKIP: | |
1604 | tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; | |
1605 | ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key); | |
1606 | D_TX("tx_cmd with tkip hwcrypto\n"); | |
1607 | break; | |
1608 | ||
1609 | case WLAN_CIPHER_SUITE_WEP104: | |
1610 | tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; | |
1611 | /* fall through */ | |
1612 | case WLAN_CIPHER_SUITE_WEP40: | |
e7392364 SG |
1613 | tx_cmd->sec_ctl |= |
1614 | (TX_CMD_SEC_WEP | (keyconf->keyidx & TX_CMD_SEC_MSK) << | |
1615 | TX_CMD_SEC_SHIFT); | |
a1751b22 SG |
1616 | |
1617 | memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen); | |
1618 | ||
e7392364 SG |
1619 | D_TX("Configuring packet for WEP encryption " "with key %d\n", |
1620 | keyconf->keyidx); | |
a1751b22 SG |
1621 | break; |
1622 | ||
1623 | default: | |
1624 | IL_ERR("Unknown encode cipher %x\n", keyconf->cipher); | |
1625 | break; | |
1626 | } | |
1627 | } | |
1628 | ||
1629 | /* | |
4d69c752 | 1630 | * start C_TX command process |
a1751b22 | 1631 | */ |
e7392364 SG |
1632 | int |
1633 | il4965_tx_skb(struct il_priv *il, struct sk_buff *skb) | |
a1751b22 SG |
1634 | { |
1635 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
1636 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
1637 | struct ieee80211_sta *sta = info->control.sta; | |
1638 | struct il_station_priv *sta_priv = NULL; | |
1639 | struct il_tx_queue *txq; | |
1640 | struct il_queue *q; | |
1641 | struct il_device_cmd *out_cmd; | |
1642 | struct il_cmd_meta *out_meta; | |
1643 | struct il_tx_cmd *tx_cmd; | |
a1751b22 SG |
1644 | int txq_id; |
1645 | dma_addr_t phys_addr; | |
1646 | dma_addr_t txcmd_phys; | |
1647 | dma_addr_t scratch_phys; | |
1648 | u16 len, firstlen, secondlen; | |
1649 | u16 seq_number = 0; | |
1650 | __le16 fc; | |
1651 | u8 hdr_len; | |
1652 | u8 sta_id; | |
1653 | u8 wait_write_ptr = 0; | |
1654 | u8 tid = 0; | |
1655 | u8 *qc = NULL; | |
1656 | unsigned long flags; | |
1657 | bool is_agg = false; | |
1658 | ||
a1751b22 SG |
1659 | spin_lock_irqsave(&il->lock, flags); |
1660 | if (il_is_rfkill(il)) { | |
1661 | D_DROP("Dropping - RF KILL\n"); | |
1662 | goto drop_unlock; | |
1663 | } | |
1664 | ||
1665 | fc = hdr->frame_control; | |
1666 | ||
1667 | #ifdef CONFIG_IWLEGACY_DEBUG | |
1668 | if (ieee80211_is_auth(fc)) | |
1669 | D_TX("Sending AUTH frame\n"); | |
1670 | else if (ieee80211_is_assoc_req(fc)) | |
1671 | D_TX("Sending ASSOC frame\n"); | |
1672 | else if (ieee80211_is_reassoc_req(fc)) | |
1673 | D_TX("Sending REASSOC frame\n"); | |
1674 | #endif | |
1675 | ||
1676 | hdr_len = ieee80211_hdrlen(fc); | |
1677 | ||
1678 | /* For management frames use broadcast id to do not break aggregation */ | |
1679 | if (!ieee80211_is_data(fc)) | |
b16db50a | 1680 | sta_id = il->hw_params.bcast_id; |
a1751b22 SG |
1681 | else { |
1682 | /* Find idx into station table for destination station */ | |
83007196 | 1683 | sta_id = il_sta_id_or_broadcast(il, info->control.sta); |
a1751b22 SG |
1684 | |
1685 | if (sta_id == IL_INVALID_STATION) { | |
e7392364 | 1686 | D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1); |
a1751b22 SG |
1687 | goto drop_unlock; |
1688 | } | |
1689 | } | |
1690 | ||
1691 | D_TX("station Id %d\n", sta_id); | |
1692 | ||
1693 | if (sta) | |
1694 | sta_priv = (void *)sta->drv_priv; | |
1695 | ||
1696 | if (sta_priv && sta_priv->asleep && | |
02f2f1a9 | 1697 | (info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER)) { |
a1751b22 SG |
1698 | /* |
1699 | * This sends an asynchronous command to the device, | |
1700 | * but we can rely on it being processed before the | |
1701 | * next frame is processed -- and the next frame to | |
1702 | * this station is the one that will consume this | |
1703 | * counter. | |
1704 | * For now set the counter to just 1 since we do not | |
1705 | * support uAPSD yet. | |
1706 | */ | |
1707 | il4965_sta_modify_sleep_tx_count(il, sta_id, 1); | |
1708 | } | |
1709 | ||
d1e14e94 SG |
1710 | /* FIXME: remove me ? */ |
1711 | WARN_ON_ONCE(info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM); | |
1712 | ||
eb123af3 SG |
1713 | /* Access category (AC) is also the queue number */ |
1714 | txq_id = skb_get_queue_mapping(skb); | |
a1751b22 SG |
1715 | |
1716 | /* irqs already disabled/saved above when locking il->lock */ | |
1717 | spin_lock(&il->sta_lock); | |
1718 | ||
1719 | if (ieee80211_is_data_qos(fc)) { | |
1720 | qc = ieee80211_get_qos_ctl(hdr); | |
1721 | tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; | |
1722 | if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) { | |
1723 | spin_unlock(&il->sta_lock); | |
1724 | goto drop_unlock; | |
1725 | } | |
1726 | seq_number = il->stations[sta_id].tid[tid].seq_number; | |
1727 | seq_number &= IEEE80211_SCTL_SEQ; | |
e7392364 SG |
1728 | hdr->seq_ctrl = |
1729 | hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG); | |
a1751b22 SG |
1730 | hdr->seq_ctrl |= cpu_to_le16(seq_number); |
1731 | seq_number += 0x10; | |
1732 | /* aggregation is on for this <sta,tid> */ | |
1733 | if (info->flags & IEEE80211_TX_CTL_AMPDU && | |
1734 | il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) { | |
1735 | txq_id = il->stations[sta_id].tid[tid].agg.txq_id; | |
1736 | is_agg = true; | |
1737 | } | |
1738 | } | |
1739 | ||
1740 | txq = &il->txq[txq_id]; | |
1741 | q = &txq->q; | |
1742 | ||
1743 | if (unlikely(il_queue_space(q) < q->high_mark)) { | |
1744 | spin_unlock(&il->sta_lock); | |
1745 | goto drop_unlock; | |
1746 | } | |
1747 | ||
1748 | if (ieee80211_is_data_qos(fc)) { | |
1749 | il->stations[sta_id].tid[tid].tfds_in_queue++; | |
1750 | if (!ieee80211_has_morefrags(fc)) | |
1751 | il->stations[sta_id].tid[tid].seq_number = seq_number; | |
1752 | } | |
1753 | ||
1754 | spin_unlock(&il->sta_lock); | |
1755 | ||
00ea99e1 | 1756 | txq->skbs[q->write_ptr] = skb; |
a1751b22 SG |
1757 | |
1758 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ | |
1759 | out_cmd = txq->cmd[q->write_ptr]; | |
1760 | out_meta = &txq->meta[q->write_ptr]; | |
1761 | tx_cmd = &out_cmd->cmd.tx; | |
1762 | memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); | |
1763 | memset(tx_cmd, 0, sizeof(struct il_tx_cmd)); | |
1764 | ||
1765 | /* | |
1766 | * Set up the Tx-command (not MAC!) header. | |
1767 | * Store the chosen Tx queue and TFD idx within the sequence field; | |
1768 | * after Tx, uCode's Tx response will return this value so driver can | |
1769 | * locate the frame within the tx queue and do post-tx processing. | |
1770 | */ | |
4d69c752 | 1771 | out_cmd->hdr.cmd = C_TX; |
e7392364 SG |
1772 | out_cmd->hdr.sequence = |
1773 | cpu_to_le16((u16) | |
1774 | (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr))); | |
a1751b22 SG |
1775 | |
1776 | /* Copy MAC header from skb into command buffer */ | |
1777 | memcpy(tx_cmd->hdr, hdr, hdr_len); | |
1778 | ||
a1751b22 | 1779 | /* Total # bytes to be transmitted */ |
e7392364 | 1780 | len = (u16) skb->len; |
a1751b22 SG |
1781 | tx_cmd->len = cpu_to_le16(len); |
1782 | ||
1783 | if (info->control.hw_key) | |
1784 | il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id); | |
1785 | ||
1786 | /* TODO need this for burst mode later on */ | |
1787 | il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id); | |
a1751b22 SG |
1788 | |
1789 | il4965_tx_cmd_build_rate(il, tx_cmd, info, fc); | |
1790 | ||
1791 | il_update_stats(il, true, fc, len); | |
1792 | /* | |
1793 | * Use the first empty entry in this queue's command buffer array | |
1794 | * to contain the Tx command and MAC header concatenated together | |
1795 | * (payload data will be in another buffer). | |
1796 | * Size of this varies, due to varying MAC header length. | |
1797 | * If end is not dword aligned, we'll have 2 extra bytes at the end | |
1798 | * of the MAC header (device reads on dword boundaries). | |
1799 | * We'll tell device about this padding later. | |
1800 | */ | |
e7392364 | 1801 | len = sizeof(struct il_tx_cmd) + sizeof(struct il_cmd_header) + hdr_len; |
a1751b22 SG |
1802 | firstlen = (len + 3) & ~3; |
1803 | ||
1804 | /* Tell NIC about any 2-byte padding after MAC header */ | |
1805 | if (firstlen != len) | |
1806 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; | |
1807 | ||
1808 | /* Physical address of this Tx command's header (not MAC header!), | |
1809 | * within command buffer array. */ | |
e7392364 SG |
1810 | txcmd_phys = |
1811 | pci_map_single(il->pci_dev, &out_cmd->hdr, firstlen, | |
1812 | PCI_DMA_BIDIRECTIONAL); | |
a1751b22 SG |
1813 | dma_unmap_addr_set(out_meta, mapping, txcmd_phys); |
1814 | dma_unmap_len_set(out_meta, len, firstlen); | |
1815 | /* Add buffer containing Tx command and MAC(!) header to TFD's | |
1816 | * first entry */ | |
1600b875 | 1817 | il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0); |
a1751b22 SG |
1818 | |
1819 | if (!ieee80211_has_morefrags(hdr->frame_control)) { | |
1820 | txq->need_update = 1; | |
1821 | } else { | |
1822 | wait_write_ptr = 1; | |
1823 | txq->need_update = 0; | |
1824 | } | |
1825 | ||
1826 | /* Set up TFD's 2nd entry to point directly to remainder of skb, | |
1827 | * if any (802.11 null frames have no payload). */ | |
1828 | secondlen = skb->len - hdr_len; | |
1829 | if (secondlen > 0) { | |
e7392364 SG |
1830 | phys_addr = |
1831 | pci_map_single(il->pci_dev, skb->data + hdr_len, secondlen, | |
1832 | PCI_DMA_TODEVICE); | |
1600b875 SG |
1833 | il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen, |
1834 | 0, 0); | |
a1751b22 SG |
1835 | } |
1836 | ||
e7392364 SG |
1837 | scratch_phys = |
1838 | txcmd_phys + sizeof(struct il_cmd_header) + | |
1839 | offsetof(struct il_tx_cmd, scratch); | |
a1751b22 SG |
1840 | |
1841 | /* take back ownership of DMA buffer to enable update */ | |
e7392364 SG |
1842 | pci_dma_sync_single_for_cpu(il->pci_dev, txcmd_phys, firstlen, |
1843 | PCI_DMA_BIDIRECTIONAL); | |
a1751b22 SG |
1844 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); |
1845 | tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys); | |
1846 | ||
e7392364 | 1847 | D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence)); |
a1751b22 | 1848 | D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); |
e7392364 SG |
1849 | il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd, sizeof(*tx_cmd)); |
1850 | il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr, hdr_len); | |
a1751b22 SG |
1851 | |
1852 | /* Set up entry for this TFD in Tx byte-count array */ | |
1853 | if (info->flags & IEEE80211_TX_CTL_AMPDU) | |
1600b875 | 1854 | il->ops->txq_update_byte_cnt_tbl(il, txq, le16_to_cpu(tx_cmd->len)); |
a1751b22 | 1855 | |
e7392364 SG |
1856 | pci_dma_sync_single_for_device(il->pci_dev, txcmd_phys, firstlen, |
1857 | PCI_DMA_BIDIRECTIONAL); | |
a1751b22 SG |
1858 | |
1859 | /* Tell device the write idx *just past* this latest filled TFD */ | |
1860 | q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd); | |
1861 | il_txq_update_write_ptr(il, txq); | |
1862 | spin_unlock_irqrestore(&il->lock, flags); | |
1863 | ||
1864 | /* | |
1865 | * At this point the frame is "transmitted" successfully | |
1866 | * and we will get a TX status notification eventually, | |
1867 | * regardless of the value of ret. "ret" only indicates | |
1868 | * whether or not we should update the write pointer. | |
1869 | */ | |
1870 | ||
1871 | /* | |
1872 | * Avoid atomic ops if it isn't an associated client. | |
1873 | * Also, if this is a packet for aggregation, don't | |
1874 | * increase the counter because the ucode will stop | |
1875 | * aggregation queues when their respective station | |
1876 | * goes to sleep. | |
1877 | */ | |
1878 | if (sta_priv && sta_priv->client && !is_agg) | |
1879 | atomic_inc(&sta_priv->pending_frames); | |
1880 | ||
1881 | if (il_queue_space(q) < q->high_mark && il->mac80211_registered) { | |
1882 | if (wait_write_ptr) { | |
1883 | spin_lock_irqsave(&il->lock, flags); | |
1884 | txq->need_update = 1; | |
1885 | il_txq_update_write_ptr(il, txq); | |
1886 | spin_unlock_irqrestore(&il->lock, flags); | |
1887 | } else { | |
1888 | il_stop_queue(il, txq); | |
1889 | } | |
1890 | } | |
1891 | ||
1892 | return 0; | |
1893 | ||
1894 | drop_unlock: | |
1895 | spin_unlock_irqrestore(&il->lock, flags); | |
1896 | return -1; | |
1897 | } | |
1898 | ||
e7392364 SG |
1899 | static inline int |
1900 | il4965_alloc_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr, size_t size) | |
a1751b22 | 1901 | { |
e7392364 SG |
1902 | ptr->addr = |
1903 | dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma, GFP_KERNEL); | |
a1751b22 SG |
1904 | if (!ptr->addr) |
1905 | return -ENOMEM; | |
1906 | ptr->size = size; | |
1907 | return 0; | |
1908 | } | |
1909 | ||
e7392364 SG |
1910 | static inline void |
1911 | il4965_free_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr) | |
a1751b22 SG |
1912 | { |
1913 | if (unlikely(!ptr->addr)) | |
1914 | return; | |
1915 | ||
1916 | dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma); | |
1917 | memset(ptr, 0, sizeof(*ptr)); | |
1918 | } | |
1919 | ||
1920 | /** | |
1921 | * il4965_hw_txq_ctx_free - Free TXQ Context | |
1922 | * | |
1923 | * Destroy all TX DMA queues and structures | |
1924 | */ | |
e7392364 SG |
1925 | void |
1926 | il4965_hw_txq_ctx_free(struct il_priv *il) | |
a1751b22 SG |
1927 | { |
1928 | int txq_id; | |
1929 | ||
1930 | /* Tx queues */ | |
1931 | if (il->txq) { | |
1932 | for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) | |
1933 | if (txq_id == il->cmd_queue) | |
1934 | il_cmd_queue_free(il); | |
1935 | else | |
1936 | il_tx_queue_free(il, txq_id); | |
1937 | } | |
1938 | il4965_free_dma_ptr(il, &il->kw); | |
1939 | ||
1940 | il4965_free_dma_ptr(il, &il->scd_bc_tbls); | |
1941 | ||
1942 | /* free tx queue structure */ | |
6668e4eb | 1943 | il_free_txq_mem(il); |
a1751b22 SG |
1944 | } |
1945 | ||
1946 | /** | |
1947 | * il4965_txq_ctx_alloc - allocate TX queue context | |
1948 | * Allocate all Tx DMA structures and initialize them | |
1949 | * | |
1950 | * @param il | |
1951 | * @return error code | |
1952 | */ | |
e7392364 SG |
1953 | int |
1954 | il4965_txq_ctx_alloc(struct il_priv *il) | |
a1751b22 | 1955 | { |
d87c771f | 1956 | int ret, txq_id; |
a1751b22 SG |
1957 | unsigned long flags; |
1958 | ||
1959 | /* Free all tx/cmd queues and keep-warm buffer */ | |
1960 | il4965_hw_txq_ctx_free(il); | |
1961 | ||
e7392364 SG |
1962 | ret = |
1963 | il4965_alloc_dma_ptr(il, &il->scd_bc_tbls, | |
1964 | il->hw_params.scd_bc_tbls_size); | |
a1751b22 SG |
1965 | if (ret) { |
1966 | IL_ERR("Scheduler BC Table allocation failed\n"); | |
1967 | goto error_bc_tbls; | |
1968 | } | |
1969 | /* Alloc keep-warm buffer */ | |
1970 | ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE); | |
1971 | if (ret) { | |
1972 | IL_ERR("Keep Warm allocation failed\n"); | |
1973 | goto error_kw; | |
1974 | } | |
1975 | ||
1976 | /* allocate tx queue structure */ | |
1977 | ret = il_alloc_txq_mem(il); | |
1978 | if (ret) | |
1979 | goto error; | |
1980 | ||
1981 | spin_lock_irqsave(&il->lock, flags); | |
1982 | ||
1983 | /* Turn off all Tx DMA fifos */ | |
1984 | il4965_txq_set_sched(il, 0); | |
1985 | ||
1986 | /* Tell NIC where to find the "keep warm" buffer */ | |
9a95b370 | 1987 | il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4); |
a1751b22 SG |
1988 | |
1989 | spin_unlock_irqrestore(&il->lock, flags); | |
1990 | ||
1991 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
1992 | for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) { | |
d87c771f | 1993 | ret = il_tx_queue_init(il, txq_id); |
a1751b22 SG |
1994 | if (ret) { |
1995 | IL_ERR("Tx %d queue init failed\n", txq_id); | |
1996 | goto error; | |
1997 | } | |
1998 | } | |
1999 | ||
2000 | return ret; | |
2001 | ||
e7392364 | 2002 | error: |
a1751b22 SG |
2003 | il4965_hw_txq_ctx_free(il); |
2004 | il4965_free_dma_ptr(il, &il->kw); | |
e7392364 | 2005 | error_kw: |
a1751b22 | 2006 | il4965_free_dma_ptr(il, &il->scd_bc_tbls); |
e7392364 | 2007 | error_bc_tbls: |
a1751b22 SG |
2008 | return ret; |
2009 | } | |
2010 | ||
e7392364 SG |
2011 | void |
2012 | il4965_txq_ctx_reset(struct il_priv *il) | |
a1751b22 | 2013 | { |
d87c771f | 2014 | int txq_id; |
a1751b22 SG |
2015 | unsigned long flags; |
2016 | ||
2017 | spin_lock_irqsave(&il->lock, flags); | |
2018 | ||
2019 | /* Turn off all Tx DMA fifos */ | |
2020 | il4965_txq_set_sched(il, 0); | |
a1751b22 | 2021 | /* Tell NIC where to find the "keep warm" buffer */ |
9a95b370 | 2022 | il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4); |
a1751b22 SG |
2023 | |
2024 | spin_unlock_irqrestore(&il->lock, flags); | |
2025 | ||
2026 | /* Alloc and init all Tx queues, including the command queue (#4) */ | |
d87c771f SG |
2027 | for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) |
2028 | il_tx_queue_reset(il, txq_id); | |
a1751b22 SG |
2029 | } |
2030 | ||
e7392364 | 2031 | void |
775ed8ab | 2032 | il4965_txq_ctx_unmap(struct il_priv *il) |
a1751b22 | 2033 | { |
775ed8ab | 2034 | int txq_id; |
a1751b22 SG |
2035 | |
2036 | if (!il->txq) | |
2037 | return; | |
2038 | ||
2039 | /* Unmap DMA from host system and free skb's */ | |
2040 | for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) | |
2041 | if (txq_id == il->cmd_queue) | |
2042 | il_cmd_queue_unmap(il); | |
2043 | else | |
2044 | il_tx_queue_unmap(il, txq_id); | |
2045 | } | |
2046 | ||
775ed8ab SG |
2047 | /** |
2048 | * il4965_txq_ctx_stop - Stop all Tx DMA channels | |
2049 | */ | |
2050 | void | |
2051 | il4965_txq_ctx_stop(struct il_priv *il) | |
2052 | { | |
2053 | int ch, ret; | |
2054 | ||
2055 | _il_wr_prph(il, IL49_SCD_TXFACT, 0); | |
2056 | ||
2057 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
2058 | for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) { | |
2059 | _il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
2060 | ret = | |
2061 | _il_poll_bit(il, FH49_TSSR_TX_STATUS_REG, | |
2062 | FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), | |
2063 | FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), | |
2064 | 1000); | |
2065 | if (ret < 0) | |
2066 | IL_ERR("Timeout stopping DMA channel %d [0x%08x]", | |
2067 | ch, _il_rd(il, FH49_TSSR_TX_STATUS_REG)); | |
2068 | } | |
2069 | } | |
2070 | ||
a1751b22 SG |
2071 | /* |
2072 | * Find first available (lowest unused) Tx Queue, mark it "active". | |
2073 | * Called only when finding queue for aggregation. | |
2074 | * Should never return anything < 7, because they should already | |
2075 | * be in use as EDCA AC (0-3), Command (4), reserved (5, 6) | |
2076 | */ | |
e7392364 SG |
2077 | static int |
2078 | il4965_txq_ctx_activate_free(struct il_priv *il) | |
a1751b22 SG |
2079 | { |
2080 | int txq_id; | |
2081 | ||
2082 | for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) | |
2083 | if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk)) | |
2084 | return txq_id; | |
2085 | return -1; | |
2086 | } | |
2087 | ||
2088 | /** | |
2089 | * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration | |
2090 | */ | |
e7392364 SG |
2091 | static void |
2092 | il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id) | |
a1751b22 SG |
2093 | { |
2094 | /* Simply stop the queue, but don't change any configuration; | |
2095 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
e7392364 | 2096 | il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id), |
1722f8e1 SG |
2097 | (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) | |
2098 | (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
a1751b22 SG |
2099 | } |
2100 | ||
2101 | /** | |
2102 | * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue | |
2103 | */ | |
e7392364 SG |
2104 | static int |
2105 | il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id) | |
a1751b22 SG |
2106 | { |
2107 | u32 tbl_dw_addr; | |
2108 | u32 tbl_dw; | |
2109 | u16 scd_q2ratid; | |
2110 | ||
2111 | scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
2112 | ||
e7392364 SG |
2113 | tbl_dw_addr = |
2114 | il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); | |
a1751b22 SG |
2115 | |
2116 | tbl_dw = il_read_targ_mem(il, tbl_dw_addr); | |
2117 | ||
2118 | if (txq_id & 0x1) | |
2119 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
2120 | else | |
2121 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
2122 | ||
2123 | il_write_targ_mem(il, tbl_dw_addr, tbl_dw); | |
2124 | ||
2125 | return 0; | |
2126 | } | |
2127 | ||
2128 | /** | |
2129 | * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue | |
2130 | * | |
2131 | * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE, | |
2132 | * i.e. it must be one of the higher queues used for aggregation | |
2133 | */ | |
e7392364 SG |
2134 | static int |
2135 | il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id, | |
2136 | int tid, u16 ssn_idx) | |
a1751b22 SG |
2137 | { |
2138 | unsigned long flags; | |
2139 | u16 ra_tid; | |
2140 | int ret; | |
2141 | ||
2142 | if ((IL49_FIRST_AMPDU_QUEUE > txq_id) || | |
2143 | (IL49_FIRST_AMPDU_QUEUE + | |
89ef1ed2 | 2144 | il->cfg->num_of_ampdu_queues <= txq_id)) { |
e7392364 | 2145 | IL_WARN("queue number out of range: %d, must be %d to %d\n", |
a1751b22 SG |
2146 | txq_id, IL49_FIRST_AMPDU_QUEUE, |
2147 | IL49_FIRST_AMPDU_QUEUE + | |
89ef1ed2 | 2148 | il->cfg->num_of_ampdu_queues - 1); |
a1751b22 SG |
2149 | return -EINVAL; |
2150 | } | |
2151 | ||
2152 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
2153 | ||
2154 | /* Modify device's station table to Tx this TID */ | |
2155 | ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid); | |
2156 | if (ret) | |
2157 | return ret; | |
2158 | ||
2159 | spin_lock_irqsave(&il->lock, flags); | |
2160 | ||
2161 | /* Stop this Tx queue before configuring it */ | |
2162 | il4965_tx_queue_stop_scheduler(il, txq_id); | |
2163 | ||
2164 | /* Map receiver-address / traffic-ID to this queue */ | |
2165 | il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id); | |
2166 | ||
2167 | /* Set this queue as a chain-building queue */ | |
2168 | il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id)); | |
2169 | ||
2170 | /* Place first TFD at idx corresponding to start sequence number. | |
2171 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
2172 | il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
2173 | il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
2174 | il4965_set_wr_ptrs(il, txq_id, ssn_idx); | |
2175 | ||
2176 | /* Set up Tx win size and frame limit for this queue */ | |
2177 | il_write_targ_mem(il, | |
e7392364 SG |
2178 | il->scd_base_addr + |
2179 | IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id), | |
2180 | (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) | |
2181 | & IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); | |
a1751b22 | 2182 | |
e7392364 SG |
2183 | il_write_targ_mem(il, |
2184 | il->scd_base_addr + | |
2185 | IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), | |
2186 | (SCD_FRAME_LIMIT << | |
2187 | IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
2188 | IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); | |
a1751b22 SG |
2189 | |
2190 | il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id)); | |
2191 | ||
2192 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
2193 | il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1); | |
2194 | ||
2195 | spin_unlock_irqrestore(&il->lock, flags); | |
2196 | ||
2197 | return 0; | |
2198 | } | |
2199 | ||
e7392364 SG |
2200 | int |
2201 | il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif, | |
2202 | struct ieee80211_sta *sta, u16 tid, u16 * ssn) | |
a1751b22 SG |
2203 | { |
2204 | int sta_id; | |
2205 | int tx_fifo; | |
2206 | int txq_id; | |
2207 | int ret; | |
2208 | unsigned long flags; | |
2209 | struct il_tid_data *tid_data; | |
2210 | ||
83007196 SG |
2211 | /* FIXME: warning if tx fifo not found ? */ |
2212 | tx_fifo = il4965_get_fifo_from_tid(tid); | |
a1751b22 SG |
2213 | if (unlikely(tx_fifo < 0)) |
2214 | return tx_fifo; | |
2215 | ||
53611e05 | 2216 | D_HT("%s on ra = %pM tid = %d\n", __func__, sta->addr, tid); |
a1751b22 SG |
2217 | |
2218 | sta_id = il_sta_id(sta); | |
2219 | if (sta_id == IL_INVALID_STATION) { | |
2220 | IL_ERR("Start AGG on invalid station\n"); | |
2221 | return -ENXIO; | |
2222 | } | |
2223 | if (unlikely(tid >= MAX_TID_COUNT)) | |
2224 | return -EINVAL; | |
2225 | ||
2226 | if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) { | |
2227 | IL_ERR("Start AGG when state is not IL_AGG_OFF !\n"); | |
2228 | return -ENXIO; | |
2229 | } | |
2230 | ||
2231 | txq_id = il4965_txq_ctx_activate_free(il); | |
2232 | if (txq_id == -1) { | |
2233 | IL_ERR("No free aggregation queue available\n"); | |
2234 | return -ENXIO; | |
2235 | } | |
2236 | ||
2237 | spin_lock_irqsave(&il->sta_lock, flags); | |
2238 | tid_data = &il->stations[sta_id].tid[tid]; | |
2239 | *ssn = SEQ_TO_SN(tid_data->seq_number); | |
2240 | tid_data->agg.txq_id = txq_id; | |
e7392364 | 2241 | il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id); |
a1751b22 SG |
2242 | spin_unlock_irqrestore(&il->sta_lock, flags); |
2243 | ||
e7392364 | 2244 | ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn); |
a1751b22 SG |
2245 | if (ret) |
2246 | return ret; | |
2247 | ||
2248 | spin_lock_irqsave(&il->sta_lock, flags); | |
2249 | tid_data = &il->stations[sta_id].tid[tid]; | |
2250 | if (tid_data->tfds_in_queue == 0) { | |
2251 | D_HT("HW queue is empty\n"); | |
2252 | tid_data->agg.state = IL_AGG_ON; | |
2253 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
2254 | } else { | |
e7392364 SG |
2255 | D_HT("HW queue is NOT empty: %d packets in HW queue\n", |
2256 | tid_data->tfds_in_queue); | |
a1751b22 SG |
2257 | tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA; |
2258 | } | |
2259 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
2260 | return ret; | |
2261 | } | |
2262 | ||
2263 | /** | |
2264 | * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE | |
2265 | * il->lock must be held by the caller | |
2266 | */ | |
e7392364 SG |
2267 | static int |
2268 | il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo) | |
a1751b22 SG |
2269 | { |
2270 | if ((IL49_FIRST_AMPDU_QUEUE > txq_id) || | |
2271 | (IL49_FIRST_AMPDU_QUEUE + | |
89ef1ed2 | 2272 | il->cfg->num_of_ampdu_queues <= txq_id)) { |
e7392364 | 2273 | IL_WARN("queue number out of range: %d, must be %d to %d\n", |
a1751b22 SG |
2274 | txq_id, IL49_FIRST_AMPDU_QUEUE, |
2275 | IL49_FIRST_AMPDU_QUEUE + | |
89ef1ed2 | 2276 | il->cfg->num_of_ampdu_queues - 1); |
a1751b22 SG |
2277 | return -EINVAL; |
2278 | } | |
2279 | ||
2280 | il4965_tx_queue_stop_scheduler(il, txq_id); | |
2281 | ||
e7392364 | 2282 | il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id)); |
a1751b22 SG |
2283 | |
2284 | il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
2285 | il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
2286 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
2287 | il4965_set_wr_ptrs(il, txq_id, ssn_idx); | |
2288 | ||
e7392364 | 2289 | il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id)); |
a1751b22 SG |
2290 | il_txq_ctx_deactivate(il, txq_id); |
2291 | il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0); | |
2292 | ||
2293 | return 0; | |
2294 | } | |
2295 | ||
e7392364 SG |
2296 | int |
2297 | il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif, | |
2298 | struct ieee80211_sta *sta, u16 tid) | |
a1751b22 SG |
2299 | { |
2300 | int tx_fifo_id, txq_id, sta_id, ssn; | |
2301 | struct il_tid_data *tid_data; | |
2302 | int write_ptr, read_ptr; | |
2303 | unsigned long flags; | |
2304 | ||
83007196 SG |
2305 | /* FIXME: warning if tx_fifo_id not found ? */ |
2306 | tx_fifo_id = il4965_get_fifo_from_tid(tid); | |
a1751b22 SG |
2307 | if (unlikely(tx_fifo_id < 0)) |
2308 | return tx_fifo_id; | |
2309 | ||
2310 | sta_id = il_sta_id(sta); | |
2311 | ||
2312 | if (sta_id == IL_INVALID_STATION) { | |
2313 | IL_ERR("Invalid station for AGG tid %d\n", tid); | |
2314 | return -ENXIO; | |
2315 | } | |
2316 | ||
2317 | spin_lock_irqsave(&il->sta_lock, flags); | |
2318 | ||
2319 | tid_data = &il->stations[sta_id].tid[tid]; | |
2320 | ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4; | |
2321 | txq_id = tid_data->agg.txq_id; | |
2322 | ||
2323 | switch (il->stations[sta_id].tid[tid].agg.state) { | |
2324 | case IL_EMPTYING_HW_QUEUE_ADDBA: | |
2325 | /* | |
2326 | * This can happen if the peer stops aggregation | |
2327 | * again before we've had a chance to drain the | |
2328 | * queue we selected previously, i.e. before the | |
2329 | * session was really started completely. | |
2330 | */ | |
2331 | D_HT("AGG stop before setup done\n"); | |
2332 | goto turn_off; | |
2333 | case IL_AGG_ON: | |
2334 | break; | |
2335 | default: | |
2336 | IL_WARN("Stopping AGG while state not ON or starting\n"); | |
2337 | } | |
2338 | ||
2339 | write_ptr = il->txq[txq_id].q.write_ptr; | |
2340 | read_ptr = il->txq[txq_id].q.read_ptr; | |
2341 | ||
2342 | /* The queue is not empty */ | |
2343 | if (write_ptr != read_ptr) { | |
2344 | D_HT("Stopping a non empty AGG HW QUEUE\n"); | |
2345 | il->stations[sta_id].tid[tid].agg.state = | |
e7392364 | 2346 | IL_EMPTYING_HW_QUEUE_DELBA; |
a1751b22 SG |
2347 | spin_unlock_irqrestore(&il->sta_lock, flags); |
2348 | return 0; | |
2349 | } | |
2350 | ||
2351 | D_HT("HW queue is empty\n"); | |
e7392364 | 2352 | turn_off: |
a1751b22 SG |
2353 | il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF; |
2354 | ||
2355 | /* do not restore/save irqs */ | |
2356 | spin_unlock(&il->sta_lock); | |
2357 | spin_lock(&il->lock); | |
2358 | ||
2359 | /* | |
2360 | * the only reason this call can fail is queue number out of range, | |
2361 | * which can happen if uCode is reloaded and all the station | |
2362 | * information are lost. if it is outside the range, there is no need | |
2363 | * to deactivate the uCode queue, just return "success" to allow | |
2364 | * mac80211 to clean up it own data. | |
2365 | */ | |
2366 | il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id); | |
2367 | spin_unlock_irqrestore(&il->lock, flags); | |
2368 | ||
2369 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); | |
2370 | ||
2371 | return 0; | |
2372 | } | |
2373 | ||
e7392364 SG |
2374 | int |
2375 | il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id) | |
a1751b22 SG |
2376 | { |
2377 | struct il_queue *q = &il->txq[txq_id].q; | |
2378 | u8 *addr = il->stations[sta_id].sta.sta.addr; | |
2379 | struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid]; | |
a1751b22 SG |
2380 | |
2381 | lockdep_assert_held(&il->sta_lock); | |
2382 | ||
2383 | switch (il->stations[sta_id].tid[tid].agg.state) { | |
2384 | case IL_EMPTYING_HW_QUEUE_DELBA: | |
2385 | /* We are reclaiming the last packet of the */ | |
2386 | /* aggregated HW queue */ | |
e7392364 | 2387 | if (txq_id == tid_data->agg.txq_id && |
a1751b22 SG |
2388 | q->read_ptr == q->write_ptr) { |
2389 | u16 ssn = SEQ_TO_SN(tid_data->seq_number); | |
83007196 | 2390 | int tx_fifo = il4965_get_fifo_from_tid(tid); |
e7392364 | 2391 | D_HT("HW queue empty: continue DELBA flow\n"); |
a1751b22 SG |
2392 | il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo); |
2393 | tid_data->agg.state = IL_AGG_OFF; | |
83007196 | 2394 | ieee80211_stop_tx_ba_cb_irqsafe(il->vif, addr, tid); |
a1751b22 SG |
2395 | } |
2396 | break; | |
2397 | case IL_EMPTYING_HW_QUEUE_ADDBA: | |
2398 | /* We are reclaiming the last packet of the queue */ | |
2399 | if (tid_data->tfds_in_queue == 0) { | |
e7392364 | 2400 | D_HT("HW queue empty: continue ADDBA flow\n"); |
a1751b22 | 2401 | tid_data->agg.state = IL_AGG_ON; |
83007196 | 2402 | ieee80211_start_tx_ba_cb_irqsafe(il->vif, addr, tid); |
a1751b22 SG |
2403 | } |
2404 | break; | |
2405 | } | |
2406 | ||
2407 | return 0; | |
2408 | } | |
2409 | ||
e7392364 | 2410 | static void |
83007196 | 2411 | il4965_non_agg_tx_status(struct il_priv *il, const u8 *addr1) |
a1751b22 SG |
2412 | { |
2413 | struct ieee80211_sta *sta; | |
2414 | struct il_station_priv *sta_priv; | |
2415 | ||
2416 | rcu_read_lock(); | |
83007196 | 2417 | sta = ieee80211_find_sta(il->vif, addr1); |
a1751b22 SG |
2418 | if (sta) { |
2419 | sta_priv = (void *)sta->drv_priv; | |
2420 | /* avoid atomic ops if this isn't a client */ | |
2421 | if (sta_priv->client && | |
2422 | atomic_dec_return(&sta_priv->pending_frames) == 0) | |
2423 | ieee80211_sta_block_awake(il->hw, sta, false); | |
2424 | } | |
2425 | rcu_read_unlock(); | |
2426 | } | |
2427 | ||
2428 | static void | |
00ea99e1 | 2429 | il4965_tx_status(struct il_priv *il, struct sk_buff *skb, bool is_agg) |
a1751b22 | 2430 | { |
00ea99e1 | 2431 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
a1751b22 SG |
2432 | |
2433 | if (!is_agg) | |
83007196 | 2434 | il4965_non_agg_tx_status(il, hdr->addr1); |
a1751b22 | 2435 | |
00ea99e1 | 2436 | ieee80211_tx_status_irqsafe(il->hw, skb); |
a1751b22 SG |
2437 | } |
2438 | ||
e7392364 SG |
2439 | int |
2440 | il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx) | |
a1751b22 SG |
2441 | { |
2442 | struct il_tx_queue *txq = &il->txq[txq_id]; | |
2443 | struct il_queue *q = &txq->q; | |
a1751b22 SG |
2444 | int nfreed = 0; |
2445 | struct ieee80211_hdr *hdr; | |
00ea99e1 | 2446 | struct sk_buff *skb; |
a1751b22 SG |
2447 | |
2448 | if (idx >= q->n_bd || il_queue_used(q, idx) == 0) { | |
2449 | IL_ERR("Read idx for DMA queue txq id (%d), idx %d, " | |
e7392364 SG |
2450 | "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd, |
2451 | q->write_ptr, q->read_ptr); | |
a1751b22 SG |
2452 | return 0; |
2453 | } | |
2454 | ||
e7392364 | 2455 | for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
a1751b22 SG |
2456 | q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) { |
2457 | ||
00ea99e1 | 2458 | skb = txq->skbs[txq->q.read_ptr]; |
a1751b22 | 2459 | |
00ea99e1 | 2460 | if (WARN_ON_ONCE(skb == NULL)) |
a1751b22 SG |
2461 | continue; |
2462 | ||
00ea99e1 | 2463 | hdr = (struct ieee80211_hdr *) skb->data; |
a1751b22 SG |
2464 | if (ieee80211_is_data_qos(hdr->frame_control)) |
2465 | nfreed++; | |
2466 | ||
00ea99e1 | 2467 | il4965_tx_status(il, skb, txq_id >= IL4965_FIRST_AMPDU_QUEUE); |
a1751b22 | 2468 | |
00ea99e1 | 2469 | txq->skbs[txq->q.read_ptr] = NULL; |
1600b875 | 2470 | il->ops->txq_free_tfd(il, txq); |
a1751b22 SG |
2471 | } |
2472 | return nfreed; | |
2473 | } | |
2474 | ||
2475 | /** | |
2476 | * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack | |
2477 | * | |
2478 | * Go through block-ack's bitmap of ACK'd frames, update driver's record of | |
2479 | * ACK vs. not. This gets sent to mac80211, then to rate scaling algo. | |
2480 | */ | |
e7392364 SG |
2481 | static int |
2482 | il4965_tx_status_reply_compressed_ba(struct il_priv *il, struct il_ht_agg *agg, | |
2483 | struct il_compressed_ba_resp *ba_resp) | |
a1751b22 SG |
2484 | { |
2485 | int i, sh, ack; | |
2486 | u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl); | |
2487 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
2488 | int successes = 0; | |
2489 | struct ieee80211_tx_info *info; | |
2490 | u64 bitmap, sent_bitmap; | |
2491 | ||
e7392364 | 2492 | if (unlikely(!agg->wait_for_ba)) { |
a1751b22 SG |
2493 | if (unlikely(ba_resp->bitmap)) |
2494 | IL_ERR("Received BA when not expected\n"); | |
2495 | return -EINVAL; | |
2496 | } | |
2497 | ||
2498 | /* Mark that the expected block-ack response arrived */ | |
2499 | agg->wait_for_ba = 0; | |
e7392364 | 2500 | D_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl); |
a1751b22 SG |
2501 | |
2502 | /* Calculate shift to align block-ack bits with our Tx win bits */ | |
2503 | sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4); | |
e7392364 | 2504 | if (sh < 0) /* tbw something is wrong with indices */ |
a1751b22 SG |
2505 | sh += 0x100; |
2506 | ||
2507 | if (agg->frame_count > (64 - sh)) { | |
2508 | D_TX_REPLY("more frames than bitmap size"); | |
2509 | return -1; | |
2510 | } | |
2511 | ||
2512 | /* don't use 64-bit values for now */ | |
2513 | bitmap = le64_to_cpu(ba_resp->bitmap) >> sh; | |
2514 | ||
2515 | /* check for success or failure according to the | |
2516 | * transmitted bitmap and block-ack bitmap */ | |
2517 | sent_bitmap = bitmap & agg->bitmap; | |
2518 | ||
2519 | /* For each frame attempted in aggregation, | |
2520 | * update driver's record of tx frame's status. */ | |
2521 | i = 0; | |
2522 | while (sent_bitmap) { | |
2523 | ack = sent_bitmap & 1ULL; | |
2524 | successes += ack; | |
e7392364 SG |
2525 | D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", ack ? "ACK" : "NACK", |
2526 | i, (agg->start_idx + i) & 0xff, agg->start_idx + i); | |
a1751b22 SG |
2527 | sent_bitmap >>= 1; |
2528 | ++i; | |
2529 | } | |
2530 | ||
e7392364 | 2531 | D_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap); |
a1751b22 | 2532 | |
00ea99e1 | 2533 | info = IEEE80211_SKB_CB(il->txq[scd_flow].skbs[agg->start_idx]); |
a1751b22 SG |
2534 | memset(&info->status, 0, sizeof(info->status)); |
2535 | info->flags |= IEEE80211_TX_STAT_ACK; | |
2536 | info->flags |= IEEE80211_TX_STAT_AMPDU; | |
2537 | info->status.ampdu_ack_len = successes; | |
2538 | info->status.ampdu_len = agg->frame_count; | |
2539 | il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info); | |
2540 | ||
2541 | return 0; | |
2542 | } | |
2543 | ||
3dfea27d SG |
2544 | static inline bool |
2545 | il4965_is_tx_success(u32 status) | |
2546 | { | |
2547 | status &= TX_STATUS_MSK; | |
2548 | return (status == TX_STATUS_SUCCESS || status == TX_STATUS_DIRECT_DONE); | |
2549 | } | |
2550 | ||
2551 | static u8 | |
2552 | il4965_find_station(struct il_priv *il, const u8 *addr) | |
2553 | { | |
2554 | int i; | |
2555 | int start = 0; | |
2556 | int ret = IL_INVALID_STATION; | |
2557 | unsigned long flags; | |
2558 | ||
2559 | if (il->iw_mode == NL80211_IFTYPE_ADHOC) | |
2560 | start = IL_STA_ID; | |
2561 | ||
2562 | if (is_broadcast_ether_addr(addr)) | |
2563 | return il->hw_params.bcast_id; | |
2564 | ||
2565 | spin_lock_irqsave(&il->sta_lock, flags); | |
2566 | for (i = start; i < il->hw_params.max_stations; i++) | |
2567 | if (il->stations[i].used && | |
2e42e474 | 2568 | ether_addr_equal(il->stations[i].sta.sta.addr, addr)) { |
3dfea27d SG |
2569 | ret = i; |
2570 | goto out; | |
2571 | } | |
2572 | ||
2573 | D_ASSOC("can not find STA %pM total %d\n", addr, il->num_stations); | |
2574 | ||
2575 | out: | |
2576 | /* | |
2577 | * It may be possible that more commands interacting with stations | |
2578 | * arrive before we completed processing the adding of | |
2579 | * station | |
2580 | */ | |
2581 | if (ret != IL_INVALID_STATION && | |
2582 | (!(il->stations[ret].used & IL_STA_UCODE_ACTIVE) || | |
2583 | ((il->stations[ret].used & IL_STA_UCODE_ACTIVE) && | |
2584 | (il->stations[ret].used & IL_STA_UCODE_INPROGRESS)))) { | |
2585 | IL_ERR("Requested station info for sta %d before ready.\n", | |
2586 | ret); | |
2587 | ret = IL_INVALID_STATION; | |
2588 | } | |
2589 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
2590 | return ret; | |
2591 | } | |
2592 | ||
2593 | static int | |
2594 | il4965_get_ra_sta_id(struct il_priv *il, struct ieee80211_hdr *hdr) | |
2595 | { | |
2596 | if (il->iw_mode == NL80211_IFTYPE_STATION) | |
2597 | return IL_AP_ID; | |
2598 | else { | |
2599 | u8 *da = ieee80211_get_DA(hdr); | |
2600 | ||
2601 | return il4965_find_station(il, da); | |
2602 | } | |
2603 | } | |
2604 | ||
2605 | static inline u32 | |
2606 | il4965_get_scd_ssn(struct il4965_tx_resp *tx_resp) | |
2607 | { | |
2608 | return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN; | |
2609 | } | |
2610 | ||
2611 | static inline u32 | |
2612 | il4965_tx_status_to_mac80211(u32 status) | |
2613 | { | |
2614 | status &= TX_STATUS_MSK; | |
2615 | ||
2616 | switch (status) { | |
2617 | case TX_STATUS_SUCCESS: | |
2618 | case TX_STATUS_DIRECT_DONE: | |
2619 | return IEEE80211_TX_STAT_ACK; | |
2620 | case TX_STATUS_FAIL_DEST_PS: | |
2621 | return IEEE80211_TX_STAT_TX_FILTERED; | |
2622 | default: | |
2623 | return 0; | |
2624 | } | |
2625 | } | |
2626 | ||
2627 | /** | |
2628 | * il4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue | |
2629 | */ | |
2630 | static int | |
2631 | il4965_tx_status_reply_tx(struct il_priv *il, struct il_ht_agg *agg, | |
2632 | struct il4965_tx_resp *tx_resp, int txq_id, | |
2633 | u16 start_idx) | |
2634 | { | |
2635 | u16 status; | |
2636 | struct agg_tx_status *frame_status = tx_resp->u.agg_status; | |
2637 | struct ieee80211_tx_info *info = NULL; | |
2638 | struct ieee80211_hdr *hdr = NULL; | |
2639 | u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); | |
2640 | int i, sh, idx; | |
2641 | u16 seq; | |
2642 | if (agg->wait_for_ba) | |
2643 | D_TX_REPLY("got tx response w/o block-ack\n"); | |
2644 | ||
2645 | agg->frame_count = tx_resp->frame_count; | |
2646 | agg->start_idx = start_idx; | |
2647 | agg->rate_n_flags = rate_n_flags; | |
2648 | agg->bitmap = 0; | |
2649 | ||
2650 | /* num frames attempted by Tx command */ | |
2651 | if (agg->frame_count == 1) { | |
2652 | /* Only one frame was attempted; no block-ack will arrive */ | |
2653 | status = le16_to_cpu(frame_status[0].status); | |
2654 | idx = start_idx; | |
2655 | ||
2656 | D_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", | |
2657 | agg->frame_count, agg->start_idx, idx); | |
2658 | ||
2659 | info = IEEE80211_SKB_CB(il->txq[txq_id].skbs[idx]); | |
2660 | info->status.rates[0].count = tx_resp->failure_frame + 1; | |
2661 | info->flags &= ~IEEE80211_TX_CTL_AMPDU; | |
2662 | info->flags |= il4965_tx_status_to_mac80211(status); | |
2663 | il4965_hwrate_to_tx_control(il, rate_n_flags, info); | |
2664 | ||
2665 | D_TX_REPLY("1 Frame 0x%x failure :%d\n", status & 0xff, | |
2666 | tx_resp->failure_frame); | |
2667 | D_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags); | |
2668 | ||
2669 | agg->wait_for_ba = 0; | |
2670 | } else { | |
2671 | /* Two or more frames were attempted; expect block-ack */ | |
2672 | u64 bitmap = 0; | |
2673 | int start = agg->start_idx; | |
2674 | struct sk_buff *skb; | |
2675 | ||
2676 | /* Construct bit-map of pending frames within Tx win */ | |
2677 | for (i = 0; i < agg->frame_count; i++) { | |
2678 | u16 sc; | |
2679 | status = le16_to_cpu(frame_status[i].status); | |
2680 | seq = le16_to_cpu(frame_status[i].sequence); | |
2681 | idx = SEQ_TO_IDX(seq); | |
2682 | txq_id = SEQ_TO_QUEUE(seq); | |
2683 | ||
2684 | if (status & | |
2685 | (AGG_TX_STATE_FEW_BYTES_MSK | | |
2686 | AGG_TX_STATE_ABORT_MSK)) | |
2687 | continue; | |
2688 | ||
2689 | D_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", | |
2690 | agg->frame_count, txq_id, idx); | |
2691 | ||
2692 | skb = il->txq[txq_id].skbs[idx]; | |
2693 | if (WARN_ON_ONCE(skb == NULL)) | |
2694 | return -1; | |
2695 | hdr = (struct ieee80211_hdr *) skb->data; | |
2696 | ||
2697 | sc = le16_to_cpu(hdr->seq_ctrl); | |
2698 | if (idx != (SEQ_TO_SN(sc) & 0xff)) { | |
2699 | IL_ERR("BUG_ON idx doesn't match seq control" | |
2700 | " idx=%d, seq_idx=%d, seq=%d\n", idx, | |
2701 | SEQ_TO_SN(sc), hdr->seq_ctrl); | |
2702 | return -1; | |
2703 | } | |
2704 | ||
2705 | D_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", i, idx, | |
2706 | SEQ_TO_SN(sc)); | |
2707 | ||
2708 | sh = idx - start; | |
2709 | if (sh > 64) { | |
2710 | sh = (start - idx) + 0xff; | |
2711 | bitmap = bitmap << sh; | |
2712 | sh = 0; | |
2713 | start = idx; | |
2714 | } else if (sh < -64) | |
2715 | sh = 0xff - (start - idx); | |
2716 | else if (sh < 0) { | |
2717 | sh = start - idx; | |
2718 | start = idx; | |
2719 | bitmap = bitmap << sh; | |
2720 | sh = 0; | |
2721 | } | |
2722 | bitmap |= 1ULL << sh; | |
2723 | D_TX_REPLY("start=%d bitmap=0x%llx\n", start, | |
2724 | (unsigned long long)bitmap); | |
2725 | } | |
2726 | ||
2727 | agg->bitmap = bitmap; | |
2728 | agg->start_idx = start; | |
2729 | D_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", | |
2730 | agg->frame_count, agg->start_idx, | |
2731 | (unsigned long long)agg->bitmap); | |
2732 | ||
2733 | if (bitmap) | |
2734 | agg->wait_for_ba = 1; | |
2735 | } | |
2736 | return 0; | |
2737 | } | |
2738 | ||
2739 | /** | |
2740 | * il4965_hdl_tx - Handle standard (non-aggregation) Tx response | |
2741 | */ | |
2742 | static void | |
2743 | il4965_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb) | |
2744 | { | |
2745 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
2746 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | |
2747 | int txq_id = SEQ_TO_QUEUE(sequence); | |
2748 | int idx = SEQ_TO_IDX(sequence); | |
2749 | struct il_tx_queue *txq = &il->txq[txq_id]; | |
2750 | struct sk_buff *skb; | |
2751 | struct ieee80211_hdr *hdr; | |
2752 | struct ieee80211_tx_info *info; | |
2753 | struct il4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; | |
2754 | u32 status = le32_to_cpu(tx_resp->u.status); | |
2755 | int uninitialized_var(tid); | |
2756 | int sta_id; | |
2757 | int freed; | |
2758 | u8 *qc = NULL; | |
2759 | unsigned long flags; | |
2760 | ||
2761 | if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) { | |
2762 | IL_ERR("Read idx for DMA queue txq_id (%d) idx %d " | |
2763 | "is out of range [0-%d] %d %d\n", txq_id, idx, | |
2764 | txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr); | |
2765 | return; | |
2766 | } | |
2767 | ||
2768 | txq->time_stamp = jiffies; | |
2769 | ||
2770 | skb = txq->skbs[txq->q.read_ptr]; | |
2771 | info = IEEE80211_SKB_CB(skb); | |
2772 | memset(&info->status, 0, sizeof(info->status)); | |
2773 | ||
2774 | hdr = (struct ieee80211_hdr *) skb->data; | |
2775 | if (ieee80211_is_data_qos(hdr->frame_control)) { | |
2776 | qc = ieee80211_get_qos_ctl(hdr); | |
2777 | tid = qc[0] & 0xf; | |
2778 | } | |
2779 | ||
2780 | sta_id = il4965_get_ra_sta_id(il, hdr); | |
2781 | if (txq->sched_retry && unlikely(sta_id == IL_INVALID_STATION)) { | |
2782 | IL_ERR("Station not known\n"); | |
2783 | return; | |
2784 | } | |
2785 | ||
2786 | spin_lock_irqsave(&il->sta_lock, flags); | |
2787 | if (txq->sched_retry) { | |
2788 | const u32 scd_ssn = il4965_get_scd_ssn(tx_resp); | |
2789 | struct il_ht_agg *agg = NULL; | |
2790 | WARN_ON(!qc); | |
2791 | ||
2792 | agg = &il->stations[sta_id].tid[tid].agg; | |
2793 | ||
2794 | il4965_tx_status_reply_tx(il, agg, tx_resp, txq_id, idx); | |
2795 | ||
2796 | /* check if BAR is needed */ | |
2797 | if (tx_resp->frame_count == 1 && | |
2798 | !il4965_is_tx_success(status)) | |
2799 | info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; | |
2800 | ||
2801 | if (txq->q.read_ptr != (scd_ssn & 0xff)) { | |
2802 | idx = il_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); | |
2803 | D_TX_REPLY("Retry scheduler reclaim scd_ssn " | |
2804 | "%d idx %d\n", scd_ssn, idx); | |
2805 | freed = il4965_tx_queue_reclaim(il, txq_id, idx); | |
2806 | if (qc) | |
2807 | il4965_free_tfds_in_queue(il, sta_id, tid, | |
2808 | freed); | |
2809 | ||
2810 | if (il->mac80211_registered && | |
2811 | il_queue_space(&txq->q) > txq->q.low_mark && | |
2812 | agg->state != IL_EMPTYING_HW_QUEUE_DELBA) | |
2813 | il_wake_queue(il, txq); | |
2814 | } | |
2815 | } else { | |
2816 | info->status.rates[0].count = tx_resp->failure_frame + 1; | |
2817 | info->flags |= il4965_tx_status_to_mac80211(status); | |
2818 | il4965_hwrate_to_tx_control(il, | |
2819 | le32_to_cpu(tx_resp->rate_n_flags), | |
2820 | info); | |
2821 | ||
2822 | D_TX_REPLY("TXQ %d status %s (0x%08x) " | |
2823 | "rate_n_flags 0x%x retries %d\n", txq_id, | |
2824 | il4965_get_tx_fail_reason(status), status, | |
2825 | le32_to_cpu(tx_resp->rate_n_flags), | |
2826 | tx_resp->failure_frame); | |
2827 | ||
2828 | freed = il4965_tx_queue_reclaim(il, txq_id, idx); | |
2829 | if (qc && likely(sta_id != IL_INVALID_STATION)) | |
2830 | il4965_free_tfds_in_queue(il, sta_id, tid, freed); | |
2831 | else if (sta_id == IL_INVALID_STATION) | |
2832 | D_TX_REPLY("Station not known\n"); | |
2833 | ||
2834 | if (il->mac80211_registered && | |
2835 | il_queue_space(&txq->q) > txq->q.low_mark) | |
2836 | il_wake_queue(il, txq); | |
2837 | } | |
2838 | if (qc && likely(sta_id != IL_INVALID_STATION)) | |
2839 | il4965_txq_check_empty(il, sta_id, tid, txq_id); | |
2840 | ||
2841 | il4965_check_abort_status(il, tx_resp->frame_count, status); | |
2842 | ||
2843 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
2844 | } | |
2845 | ||
a1751b22 SG |
2846 | /** |
2847 | * translate ucode response to mac80211 tx status control values | |
2848 | */ | |
e7392364 SG |
2849 | void |
2850 | il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags, | |
2851 | struct ieee80211_tx_info *info) | |
a1751b22 | 2852 | { |
d748b464 | 2853 | struct ieee80211_tx_rate *r = &info->status.rates[0]; |
a1751b22 | 2854 | |
d748b464 | 2855 | info->status.antenna = |
e7392364 | 2856 | ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS); |
a1751b22 SG |
2857 | if (rate_n_flags & RATE_MCS_HT_MSK) |
2858 | r->flags |= IEEE80211_TX_RC_MCS; | |
2859 | if (rate_n_flags & RATE_MCS_GF_MSK) | |
2860 | r->flags |= IEEE80211_TX_RC_GREEN_FIELD; | |
2861 | if (rate_n_flags & RATE_MCS_HT40_MSK) | |
2862 | r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; | |
2863 | if (rate_n_flags & RATE_MCS_DUP_MSK) | |
2864 | r->flags |= IEEE80211_TX_RC_DUP_DATA; | |
2865 | if (rate_n_flags & RATE_MCS_SGI_MSK) | |
2866 | r->flags |= IEEE80211_TX_RC_SHORT_GI; | |
2867 | r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band); | |
2868 | } | |
2869 | ||
2870 | /** | |
6e9848b4 | 2871 | * il4965_hdl_compressed_ba - Handler for N_COMPRESSED_BA |
a1751b22 SG |
2872 | * |
2873 | * Handles block-acknowledge notification from device, which reports success | |
2874 | * of frames sent via aggregation. | |
2875 | */ | |
e7392364 SG |
2876 | void |
2877 | il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb) | |
a1751b22 SG |
2878 | { |
2879 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
2880 | struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba; | |
2881 | struct il_tx_queue *txq = NULL; | |
2882 | struct il_ht_agg *agg; | |
2883 | int idx; | |
2884 | int sta_id; | |
2885 | int tid; | |
2886 | unsigned long flags; | |
2887 | ||
2888 | /* "flow" corresponds to Tx queue */ | |
2889 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
2890 | ||
2891 | /* "ssn" is start of block-ack Tx win, corresponds to idx | |
2892 | * (in Tx queue's circular buffer) of first TFD/frame in win */ | |
2893 | u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn); | |
2894 | ||
2895 | if (scd_flow >= il->hw_params.max_txq_num) { | |
e7392364 | 2896 | IL_ERR("BUG_ON scd_flow is bigger than number of queues\n"); |
a1751b22 SG |
2897 | return; |
2898 | } | |
2899 | ||
2900 | txq = &il->txq[scd_flow]; | |
2901 | sta_id = ba_resp->sta_id; | |
2902 | tid = ba_resp->tid; | |
2903 | agg = &il->stations[sta_id].tid[tid].agg; | |
2904 | if (unlikely(agg->txq_id != scd_flow)) { | |
2905 | /* | |
2906 | * FIXME: this is a uCode bug which need to be addressed, | |
2907 | * log the information and return for now! | |
2908 | * since it is possible happen very often and in order | |
2909 | * not to fill the syslog, don't enable the logging by default | |
2910 | */ | |
e7392364 SG |
2911 | D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n", |
2912 | scd_flow, agg->txq_id); | |
a1751b22 SG |
2913 | return; |
2914 | } | |
2915 | ||
2916 | /* Find idx just before block-ack win */ | |
2917 | idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd); | |
2918 | ||
2919 | spin_lock_irqsave(&il->sta_lock, flags); | |
2920 | ||
e7392364 | 2921 | D_TX_REPLY("N_COMPRESSED_BA [%d] Received from %pM, " "sta_id = %d\n", |
1722f8e1 | 2922 | agg->wait_for_ba, (u8 *) &ba_resp->sta_addr_lo32, |
e7392364 SG |
2923 | ba_resp->sta_id); |
2924 | D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = " | |
2925 | "%d, scd_ssn = %d\n", ba_resp->tid, ba_resp->seq_ctl, | |
2926 | (unsigned long long)le64_to_cpu(ba_resp->bitmap), | |
2927 | ba_resp->scd_flow, ba_resp->scd_ssn); | |
2928 | D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx, | |
2929 | (unsigned long long)agg->bitmap); | |
a1751b22 SG |
2930 | |
2931 | /* Update driver's record of ACK vs. not for each frame in win */ | |
2932 | il4965_tx_status_reply_compressed_ba(il, agg, ba_resp); | |
2933 | ||
2934 | /* Release all TFDs before the SSN, i.e. all TFDs in front of | |
2935 | * block-ack win (we assume that they've been successfully | |
2936 | * transmitted ... if not, it's too late anyway). */ | |
2937 | if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) { | |
2938 | /* calculate mac80211 ampdu sw queue to wake */ | |
2939 | int freed = il4965_tx_queue_reclaim(il, scd_flow, idx); | |
2940 | il4965_free_tfds_in_queue(il, sta_id, tid, freed); | |
2941 | ||
2942 | if (il_queue_space(&txq->q) > txq->q.low_mark && | |
2943 | il->mac80211_registered && | |
2944 | agg->state != IL_EMPTYING_HW_QUEUE_DELBA) | |
2945 | il_wake_queue(il, txq); | |
2946 | ||
2947 | il4965_txq_check_empty(il, sta_id, tid, scd_flow); | |
2948 | } | |
2949 | ||
2950 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
2951 | } | |
2952 | ||
2953 | #ifdef CONFIG_IWLEGACY_DEBUG | |
e7392364 SG |
2954 | const char * |
2955 | il4965_get_tx_fail_reason(u32 status) | |
a1751b22 SG |
2956 | { |
2957 | #define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x | |
2958 | #define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x | |
2959 | ||
2960 | switch (status & TX_STATUS_MSK) { | |
2961 | case TX_STATUS_SUCCESS: | |
2962 | return "SUCCESS"; | |
e7392364 SG |
2963 | TX_STATUS_POSTPONE(DELAY); |
2964 | TX_STATUS_POSTPONE(FEW_BYTES); | |
2965 | TX_STATUS_POSTPONE(QUIET_PERIOD); | |
2966 | TX_STATUS_POSTPONE(CALC_TTAK); | |
2967 | TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY); | |
2968 | TX_STATUS_FAIL(SHORT_LIMIT); | |
2969 | TX_STATUS_FAIL(LONG_LIMIT); | |
2970 | TX_STATUS_FAIL(FIFO_UNDERRUN); | |
2971 | TX_STATUS_FAIL(DRAIN_FLOW); | |
2972 | TX_STATUS_FAIL(RFKILL_FLUSH); | |
2973 | TX_STATUS_FAIL(LIFE_EXPIRE); | |
2974 | TX_STATUS_FAIL(DEST_PS); | |
2975 | TX_STATUS_FAIL(HOST_ABORTED); | |
2976 | TX_STATUS_FAIL(BT_RETRY); | |
2977 | TX_STATUS_FAIL(STA_INVALID); | |
2978 | TX_STATUS_FAIL(FRAG_DROPPED); | |
2979 | TX_STATUS_FAIL(TID_DISABLE); | |
2980 | TX_STATUS_FAIL(FIFO_FLUSHED); | |
2981 | TX_STATUS_FAIL(INSUFFICIENT_CF_POLL); | |
2982 | TX_STATUS_FAIL(PASSIVE_NO_RX); | |
2983 | TX_STATUS_FAIL(NO_BEACON_ON_RADAR); | |
a1751b22 SG |
2984 | } |
2985 | ||
2986 | return "UNKNOWN"; | |
2987 | ||
2988 | #undef TX_STATUS_FAIL | |
2989 | #undef TX_STATUS_POSTPONE | |
2990 | } | |
2991 | #endif /* CONFIG_IWLEGACY_DEBUG */ | |
2992 | ||
eb3cdfb7 SG |
2993 | static struct il_link_quality_cmd * |
2994 | il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id) | |
2995 | { | |
2996 | int i, r; | |
2997 | struct il_link_quality_cmd *link_cmd; | |
2998 | u32 rate_flags = 0; | |
2999 | __le32 rate_n_flags; | |
3000 | ||
3001 | link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL); | |
3002 | if (!link_cmd) { | |
3003 | IL_ERR("Unable to allocate memory for LQ cmd.\n"); | |
3004 | return NULL; | |
3005 | } | |
3006 | /* Set up the rate scaling to start at selected rate, fall back | |
3007 | * all the way down to 1M in IEEE order, and then spin on 1M */ | |
3008 | if (il->band == IEEE80211_BAND_5GHZ) | |
3009 | r = RATE_6M_IDX; | |
3010 | else | |
3011 | r = RATE_1M_IDX; | |
3012 | ||
3013 | if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE) | |
3014 | rate_flags |= RATE_MCS_CCK_MSK; | |
3015 | ||
e7392364 SG |
3016 | rate_flags |= |
3017 | il4965_first_antenna(il->hw_params. | |
3018 | valid_tx_ant) << RATE_MCS_ANT_POS; | |
616107ed | 3019 | rate_n_flags = cpu_to_le32(il_rates[r].plcp | rate_flags); |
eb3cdfb7 SG |
3020 | for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) |
3021 | link_cmd->rs_table[i].rate_n_flags = rate_n_flags; | |
3022 | ||
3023 | link_cmd->general_params.single_stream_ant_msk = | |
e7392364 | 3024 | il4965_first_antenna(il->hw_params.valid_tx_ant); |
eb3cdfb7 SG |
3025 | |
3026 | link_cmd->general_params.dual_stream_ant_msk = | |
e7392364 SG |
3027 | il->hw_params.valid_tx_ant & ~il4965_first_antenna(il->hw_params. |
3028 | valid_tx_ant); | |
eb3cdfb7 SG |
3029 | if (!link_cmd->general_params.dual_stream_ant_msk) { |
3030 | link_cmd->general_params.dual_stream_ant_msk = ANT_AB; | |
3031 | } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) { | |
3032 | link_cmd->general_params.dual_stream_ant_msk = | |
e7392364 | 3033 | il->hw_params.valid_tx_ant; |
eb3cdfb7 SG |
3034 | } |
3035 | ||
3036 | link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF; | |
3037 | link_cmd->agg_params.agg_time_limit = | |
e7392364 | 3038 | cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF); |
eb3cdfb7 SG |
3039 | |
3040 | link_cmd->sta_id = sta_id; | |
3041 | ||
3042 | return link_cmd; | |
3043 | } | |
3044 | ||
3045 | /* | |
3046 | * il4965_add_bssid_station - Add the special IBSS BSSID station | |
3047 | * | |
3048 | * Function sleeps. | |
3049 | */ | |
3050 | int | |
83007196 | 3051 | il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r) |
eb3cdfb7 SG |
3052 | { |
3053 | int ret; | |
3054 | u8 sta_id; | |
3055 | struct il_link_quality_cmd *link_cmd; | |
3056 | unsigned long flags; | |
3057 | ||
3058 | if (sta_id_r) | |
3059 | *sta_id_r = IL_INVALID_STATION; | |
3060 | ||
83007196 | 3061 | ret = il_add_station_common(il, addr, 0, NULL, &sta_id); |
eb3cdfb7 SG |
3062 | if (ret) { |
3063 | IL_ERR("Unable to add station %pM\n", addr); | |
3064 | return ret; | |
3065 | } | |
3066 | ||
3067 | if (sta_id_r) | |
3068 | *sta_id_r = sta_id; | |
3069 | ||
3070 | spin_lock_irqsave(&il->sta_lock, flags); | |
3071 | il->stations[sta_id].used |= IL_STA_LOCAL; | |
3072 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
3073 | ||
3074 | /* Set up default rate scaling table in device's station table */ | |
3075 | link_cmd = il4965_sta_alloc_lq(il, sta_id); | |
3076 | if (!link_cmd) { | |
e7392364 SG |
3077 | IL_ERR("Unable to initialize rate scaling for station %pM.\n", |
3078 | addr); | |
eb3cdfb7 SG |
3079 | return -ENOMEM; |
3080 | } | |
3081 | ||
83007196 | 3082 | ret = il_send_lq_cmd(il, link_cmd, CMD_SYNC, true); |
eb3cdfb7 SG |
3083 | if (ret) |
3084 | IL_ERR("Link quality command failed (%d)\n", ret); | |
3085 | ||
3086 | spin_lock_irqsave(&il->sta_lock, flags); | |
3087 | il->stations[sta_id].lq = link_cmd; | |
3088 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
3089 | ||
3090 | return 0; | |
3091 | } | |
3092 | ||
e7392364 | 3093 | static int |
83007196 | 3094 | il4965_static_wepkey_cmd(struct il_priv *il, bool send_if_empty) |
eb3cdfb7 | 3095 | { |
d735f921 | 3096 | int i; |
eb3cdfb7 SG |
3097 | u8 buff[sizeof(struct il_wep_cmd) + |
3098 | sizeof(struct il_wep_key) * WEP_KEYS_MAX]; | |
3099 | struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff; | |
e7392364 | 3100 | size_t cmd_size = sizeof(struct il_wep_cmd); |
eb3cdfb7 | 3101 | struct il_host_cmd cmd = { |
d98e2942 | 3102 | .id = C_WEPKEY, |
eb3cdfb7 SG |
3103 | .data = wep_cmd, |
3104 | .flags = CMD_SYNC, | |
3105 | }; | |
d735f921 | 3106 | bool not_empty = false; |
eb3cdfb7 SG |
3107 | |
3108 | might_sleep(); | |
3109 | ||
e7392364 SG |
3110 | memset(wep_cmd, 0, |
3111 | cmd_size + (sizeof(struct il_wep_key) * WEP_KEYS_MAX)); | |
eb3cdfb7 | 3112 | |
e7392364 | 3113 | for (i = 0; i < WEP_KEYS_MAX; i++) { |
d735f921 SG |
3114 | u8 key_size = il->_4965.wep_keys[i].key_size; |
3115 | ||
eb3cdfb7 | 3116 | wep_cmd->key[i].key_idx = i; |
d735f921 | 3117 | if (key_size) { |
eb3cdfb7 | 3118 | wep_cmd->key[i].key_offset = i; |
d735f921 SG |
3119 | not_empty = true; |
3120 | } else | |
eb3cdfb7 | 3121 | wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET; |
eb3cdfb7 | 3122 | |
d735f921 SG |
3123 | wep_cmd->key[i].key_size = key_size; |
3124 | memcpy(&wep_cmd->key[i].key[3], il->_4965.wep_keys[i].key, key_size); | |
eb3cdfb7 SG |
3125 | } |
3126 | ||
3127 | wep_cmd->global_key_type = WEP_KEY_WEP_TYPE; | |
3128 | wep_cmd->num_keys = WEP_KEYS_MAX; | |
3129 | ||
3130 | cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX; | |
eb3cdfb7 SG |
3131 | cmd.len = cmd_size; |
3132 | ||
3133 | if (not_empty || send_if_empty) | |
3134 | return il_send_cmd(il, &cmd); | |
3135 | else | |
3136 | return 0; | |
3137 | } | |
3138 | ||
e7392364 | 3139 | int |
83007196 | 3140 | il4965_restore_default_wep_keys(struct il_priv *il) |
eb3cdfb7 SG |
3141 | { |
3142 | lockdep_assert_held(&il->mutex); | |
3143 | ||
83007196 | 3144 | return il4965_static_wepkey_cmd(il, false); |
eb3cdfb7 SG |
3145 | } |
3146 | ||
e7392364 | 3147 | int |
83007196 | 3148 | il4965_remove_default_wep_key(struct il_priv *il, |
e7392364 | 3149 | struct ieee80211_key_conf *keyconf) |
eb3cdfb7 SG |
3150 | { |
3151 | int ret; | |
d735f921 | 3152 | int idx = keyconf->keyidx; |
eb3cdfb7 SG |
3153 | |
3154 | lockdep_assert_held(&il->mutex); | |
3155 | ||
d735f921 | 3156 | D_WEP("Removing default WEP key: idx=%d\n", idx); |
eb3cdfb7 | 3157 | |
d735f921 | 3158 | memset(&il->_4965.wep_keys[idx], 0, sizeof(struct il_wep_key)); |
eb3cdfb7 | 3159 | if (il_is_rfkill(il)) { |
e7392364 | 3160 | D_WEP("Not sending C_WEPKEY command due to RFKILL.\n"); |
eb3cdfb7 SG |
3161 | /* but keys in device are clear anyway so return success */ |
3162 | return 0; | |
3163 | } | |
83007196 | 3164 | ret = il4965_static_wepkey_cmd(il, 1); |
d735f921 | 3165 | D_WEP("Remove default WEP key: idx=%d ret=%d\n", idx, ret); |
eb3cdfb7 SG |
3166 | |
3167 | return ret; | |
3168 | } | |
3169 | ||
e7392364 | 3170 | int |
83007196 | 3171 | il4965_set_default_wep_key(struct il_priv *il, |
e7392364 | 3172 | struct ieee80211_key_conf *keyconf) |
eb3cdfb7 SG |
3173 | { |
3174 | int ret; | |
d735f921 SG |
3175 | int len = keyconf->keylen; |
3176 | int idx = keyconf->keyidx; | |
eb3cdfb7 SG |
3177 | |
3178 | lockdep_assert_held(&il->mutex); | |
3179 | ||
d735f921 | 3180 | if (len != WEP_KEY_LEN_128 && len != WEP_KEY_LEN_64) { |
eb3cdfb7 SG |
3181 | D_WEP("Bad WEP key length %d\n", keyconf->keylen); |
3182 | return -EINVAL; | |
3183 | } | |
3184 | ||
3185 | keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV; | |
3186 | keyconf->hw_key_idx = HW_KEY_DEFAULT; | |
8f9e5645 | 3187 | il->stations[IL_AP_ID].keyinfo.cipher = keyconf->cipher; |
eb3cdfb7 | 3188 | |
d735f921 SG |
3189 | il->_4965.wep_keys[idx].key_size = len; |
3190 | memcpy(&il->_4965.wep_keys[idx].key, &keyconf->key, len); | |
eb3cdfb7 | 3191 | |
83007196 | 3192 | ret = il4965_static_wepkey_cmd(il, false); |
eb3cdfb7 | 3193 | |
d735f921 | 3194 | D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n", len, idx, ret); |
eb3cdfb7 SG |
3195 | return ret; |
3196 | } | |
3197 | ||
e7392364 | 3198 | static int |
83007196 | 3199 | il4965_set_wep_dynamic_key_info(struct il_priv *il, |
e7392364 | 3200 | struct ieee80211_key_conf *keyconf, u8 sta_id) |
eb3cdfb7 SG |
3201 | { |
3202 | unsigned long flags; | |
3203 | __le16 key_flags = 0; | |
3204 | struct il_addsta_cmd sta_cmd; | |
3205 | ||
3206 | lockdep_assert_held(&il->mutex); | |
3207 | ||
3208 | keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV; | |
3209 | ||
3210 | key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK); | |
3211 | key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
3212 | key_flags &= ~STA_KEY_FLG_INVALID; | |
3213 | ||
3214 | if (keyconf->keylen == WEP_KEY_LEN_128) | |
3215 | key_flags |= STA_KEY_FLG_KEY_SIZE_MSK; | |
3216 | ||
b16db50a | 3217 | if (sta_id == il->hw_params.bcast_id) |
eb3cdfb7 SG |
3218 | key_flags |= STA_KEY_MULTICAST_MSK; |
3219 | ||
3220 | spin_lock_irqsave(&il->sta_lock, flags); | |
3221 | ||
3222 | il->stations[sta_id].keyinfo.cipher = keyconf->cipher; | |
3223 | il->stations[sta_id].keyinfo.keylen = keyconf->keylen; | |
3224 | il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx; | |
3225 | ||
e7392364 | 3226 | memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen); |
eb3cdfb7 | 3227 | |
e7392364 SG |
3228 | memcpy(&il->stations[sta_id].sta.key.key[3], keyconf->key, |
3229 | keyconf->keylen); | |
eb3cdfb7 | 3230 | |
e7392364 SG |
3231 | if ((il->stations[sta_id].sta.key. |
3232 | key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC) | |
eb3cdfb7 | 3233 | il->stations[sta_id].sta.key.key_offset = |
e7392364 | 3234 | il_get_free_ucode_key_idx(il); |
eb3cdfb7 SG |
3235 | /* else, we are overriding an existing key => no need to allocated room |
3236 | * in uCode. */ | |
3237 | ||
3238 | WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, | |
e7392364 | 3239 | "no space for a new key"); |
eb3cdfb7 SG |
3240 | |
3241 | il->stations[sta_id].sta.key.key_flags = key_flags; | |
3242 | il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
3243 | il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
3244 | ||
3245 | memcpy(&sta_cmd, &il->stations[sta_id].sta, | |
e7392364 | 3246 | sizeof(struct il_addsta_cmd)); |
eb3cdfb7 SG |
3247 | spin_unlock_irqrestore(&il->sta_lock, flags); |
3248 | ||
3249 | return il_send_add_sta(il, &sta_cmd, CMD_SYNC); | |
3250 | } | |
3251 | ||
e7392364 SG |
3252 | static int |
3253 | il4965_set_ccmp_dynamic_key_info(struct il_priv *il, | |
e7392364 | 3254 | struct ieee80211_key_conf *keyconf, u8 sta_id) |
eb3cdfb7 SG |
3255 | { |
3256 | unsigned long flags; | |
3257 | __le16 key_flags = 0; | |
3258 | struct il_addsta_cmd sta_cmd; | |
3259 | ||
3260 | lockdep_assert_held(&il->mutex); | |
3261 | ||
3262 | key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK); | |
3263 | key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
3264 | key_flags &= ~STA_KEY_FLG_INVALID; | |
3265 | ||
b16db50a | 3266 | if (sta_id == il->hw_params.bcast_id) |
eb3cdfb7 SG |
3267 | key_flags |= STA_KEY_MULTICAST_MSK; |
3268 | ||
3269 | keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
3270 | ||
3271 | spin_lock_irqsave(&il->sta_lock, flags); | |
3272 | il->stations[sta_id].keyinfo.cipher = keyconf->cipher; | |
3273 | il->stations[sta_id].keyinfo.keylen = keyconf->keylen; | |
3274 | ||
e7392364 | 3275 | memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen); |
eb3cdfb7 | 3276 | |
e7392364 | 3277 | memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen); |
eb3cdfb7 | 3278 | |
e7392364 SG |
3279 | if ((il->stations[sta_id].sta.key. |
3280 | key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC) | |
eb3cdfb7 | 3281 | il->stations[sta_id].sta.key.key_offset = |
e7392364 | 3282 | il_get_free_ucode_key_idx(il); |
eb3cdfb7 SG |
3283 | /* else, we are overriding an existing key => no need to allocated room |
3284 | * in uCode. */ | |
3285 | ||
3286 | WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, | |
e7392364 | 3287 | "no space for a new key"); |
eb3cdfb7 SG |
3288 | |
3289 | il->stations[sta_id].sta.key.key_flags = key_flags; | |
3290 | il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
3291 | il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
3292 | ||
3293 | memcpy(&sta_cmd, &il->stations[sta_id].sta, | |
e7392364 | 3294 | sizeof(struct il_addsta_cmd)); |
eb3cdfb7 SG |
3295 | spin_unlock_irqrestore(&il->sta_lock, flags); |
3296 | ||
3297 | return il_send_add_sta(il, &sta_cmd, CMD_SYNC); | |
3298 | } | |
3299 | ||
e7392364 SG |
3300 | static int |
3301 | il4965_set_tkip_dynamic_key_info(struct il_priv *il, | |
e7392364 | 3302 | struct ieee80211_key_conf *keyconf, u8 sta_id) |
eb3cdfb7 SG |
3303 | { |
3304 | unsigned long flags; | |
3305 | int ret = 0; | |
3306 | __le16 key_flags = 0; | |
3307 | ||
3308 | key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK); | |
3309 | key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); | |
3310 | key_flags &= ~STA_KEY_FLG_INVALID; | |
3311 | ||
b16db50a | 3312 | if (sta_id == il->hw_params.bcast_id) |
eb3cdfb7 SG |
3313 | key_flags |= STA_KEY_MULTICAST_MSK; |
3314 | ||
3315 | keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
3316 | keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | |
3317 | ||
3318 | spin_lock_irqsave(&il->sta_lock, flags); | |
3319 | ||
3320 | il->stations[sta_id].keyinfo.cipher = keyconf->cipher; | |
3321 | il->stations[sta_id].keyinfo.keylen = 16; | |
3322 | ||
e7392364 SG |
3323 | if ((il->stations[sta_id].sta.key. |
3324 | key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC) | |
eb3cdfb7 | 3325 | il->stations[sta_id].sta.key.key_offset = |
e7392364 | 3326 | il_get_free_ucode_key_idx(il); |
eb3cdfb7 SG |
3327 | /* else, we are overriding an existing key => no need to allocated room |
3328 | * in uCode. */ | |
3329 | ||
3330 | WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, | |
e7392364 | 3331 | "no space for a new key"); |
eb3cdfb7 SG |
3332 | |
3333 | il->stations[sta_id].sta.key.key_flags = key_flags; | |
3334 | ||
eb3cdfb7 SG |
3335 | /* This copy is acutally not needed: we get the key with each TX */ |
3336 | memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16); | |
3337 | ||
3338 | memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16); | |
3339 | ||
3340 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
3341 | ||
3342 | return ret; | |
3343 | } | |
3344 | ||
e7392364 | 3345 | void |
83007196 SG |
3346 | il4965_update_tkip_key(struct il_priv *il, struct ieee80211_key_conf *keyconf, |
3347 | struct ieee80211_sta *sta, u32 iv32, u16 *phase1key) | |
eb3cdfb7 SG |
3348 | { |
3349 | u8 sta_id; | |
3350 | unsigned long flags; | |
3351 | int i; | |
3352 | ||
3353 | if (il_scan_cancel(il)) { | |
3354 | /* cancel scan failed, just live w/ bad key and rely | |
3355 | briefly on SW decryption */ | |
3356 | return; | |
3357 | } | |
3358 | ||
83007196 | 3359 | sta_id = il_sta_id_or_broadcast(il, sta); |
eb3cdfb7 SG |
3360 | if (sta_id == IL_INVALID_STATION) |
3361 | return; | |
3362 | ||
3363 | spin_lock_irqsave(&il->sta_lock, flags); | |
3364 | ||
3365 | il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32; | |
3366 | ||
3367 | for (i = 0; i < 5; i++) | |
3368 | il->stations[sta_id].sta.key.tkip_rx_ttak[i] = | |
e7392364 | 3369 | cpu_to_le16(phase1key[i]); |
eb3cdfb7 SG |
3370 | |
3371 | il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
3372 | il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
3373 | ||
3374 | il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC); | |
3375 | ||
3376 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
eb3cdfb7 SG |
3377 | } |
3378 | ||
e7392364 | 3379 | int |
83007196 | 3380 | il4965_remove_dynamic_key(struct il_priv *il, |
e7392364 | 3381 | struct ieee80211_key_conf *keyconf, u8 sta_id) |
eb3cdfb7 SG |
3382 | { |
3383 | unsigned long flags; | |
3384 | u16 key_flags; | |
3385 | u8 keyidx; | |
3386 | struct il_addsta_cmd sta_cmd; | |
3387 | ||
3388 | lockdep_assert_held(&il->mutex); | |
3389 | ||
d735f921 | 3390 | il->_4965.key_mapping_keys--; |
eb3cdfb7 SG |
3391 | |
3392 | spin_lock_irqsave(&il->sta_lock, flags); | |
3393 | key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags); | |
3394 | keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3; | |
3395 | ||
e7392364 | 3396 | D_WEP("Remove dynamic key: idx=%d sta=%d\n", keyconf->keyidx, sta_id); |
eb3cdfb7 SG |
3397 | |
3398 | if (keyconf->keyidx != keyidx) { | |
3399 | /* We need to remove a key with idx different that the one | |
3400 | * in the uCode. This means that the key we need to remove has | |
3401 | * been replaced by another one with different idx. | |
3402 | * Don't do anything and return ok | |
3403 | */ | |
3404 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
3405 | return 0; | |
3406 | } | |
3407 | ||
3408 | if (il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET) { | |
e7392364 SG |
3409 | IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx, |
3410 | key_flags); | |
eb3cdfb7 SG |
3411 | spin_unlock_irqrestore(&il->sta_lock, flags); |
3412 | return 0; | |
3413 | } | |
3414 | ||
e7392364 SG |
3415 | if (!test_and_clear_bit |
3416 | (il->stations[sta_id].sta.key.key_offset, &il->ucode_key_table)) | |
eb3cdfb7 | 3417 | IL_ERR("idx %d not used in uCode key table.\n", |
e7392364 SG |
3418 | il->stations[sta_id].sta.key.key_offset); |
3419 | memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key)); | |
3420 | memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo)); | |
eb3cdfb7 | 3421 | il->stations[sta_id].sta.key.key_flags = |
e7392364 | 3422 | STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID; |
eb3cdfb7 SG |
3423 | il->stations[sta_id].sta.key.key_offset = WEP_INVALID_OFFSET; |
3424 | il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; | |
3425 | il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
3426 | ||
3427 | if (il_is_rfkill(il)) { | |
e7392364 SG |
3428 | D_WEP |
3429 | ("Not sending C_ADD_STA command because RFKILL enabled.\n"); | |
eb3cdfb7 SG |
3430 | spin_unlock_irqrestore(&il->sta_lock, flags); |
3431 | return 0; | |
3432 | } | |
3433 | memcpy(&sta_cmd, &il->stations[sta_id].sta, | |
e7392364 | 3434 | sizeof(struct il_addsta_cmd)); |
eb3cdfb7 SG |
3435 | spin_unlock_irqrestore(&il->sta_lock, flags); |
3436 | ||
3437 | return il_send_add_sta(il, &sta_cmd, CMD_SYNC); | |
3438 | } | |
3439 | ||
e7392364 | 3440 | int |
83007196 SG |
3441 | il4965_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf, |
3442 | u8 sta_id) | |
eb3cdfb7 SG |
3443 | { |
3444 | int ret; | |
3445 | ||
3446 | lockdep_assert_held(&il->mutex); | |
3447 | ||
d735f921 | 3448 | il->_4965.key_mapping_keys++; |
eb3cdfb7 SG |
3449 | keyconf->hw_key_idx = HW_KEY_DYNAMIC; |
3450 | ||
3451 | switch (keyconf->cipher) { | |
3452 | case WLAN_CIPHER_SUITE_CCMP: | |
e7392364 | 3453 | ret = |
83007196 | 3454 | il4965_set_ccmp_dynamic_key_info(il, keyconf, sta_id); |
eb3cdfb7 SG |
3455 | break; |
3456 | case WLAN_CIPHER_SUITE_TKIP: | |
e7392364 | 3457 | ret = |
83007196 | 3458 | il4965_set_tkip_dynamic_key_info(il, keyconf, sta_id); |
eb3cdfb7 SG |
3459 | break; |
3460 | case WLAN_CIPHER_SUITE_WEP40: | |
3461 | case WLAN_CIPHER_SUITE_WEP104: | |
83007196 | 3462 | ret = il4965_set_wep_dynamic_key_info(il, keyconf, sta_id); |
eb3cdfb7 SG |
3463 | break; |
3464 | default: | |
e7392364 SG |
3465 | IL_ERR("Unknown alg: %s cipher = %x\n", __func__, |
3466 | keyconf->cipher); | |
eb3cdfb7 SG |
3467 | ret = -EINVAL; |
3468 | } | |
3469 | ||
e7392364 SG |
3470 | D_WEP("Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n", |
3471 | keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret); | |
eb3cdfb7 SG |
3472 | |
3473 | return ret; | |
3474 | } | |
3475 | ||
3476 | /** | |
3477 | * il4965_alloc_bcast_station - add broadcast station into driver's station table. | |
3478 | * | |
3479 | * This adds the broadcast station into the driver's station table | |
3480 | * and marks it driver active, so that it will be restored to the | |
3481 | * device at the next best time. | |
3482 | */ | |
e7392364 | 3483 | int |
83007196 | 3484 | il4965_alloc_bcast_station(struct il_priv *il) |
eb3cdfb7 SG |
3485 | { |
3486 | struct il_link_quality_cmd *link_cmd; | |
3487 | unsigned long flags; | |
3488 | u8 sta_id; | |
3489 | ||
3490 | spin_lock_irqsave(&il->sta_lock, flags); | |
83007196 | 3491 | sta_id = il_prep_station(il, il_bcast_addr, false, NULL); |
eb3cdfb7 SG |
3492 | if (sta_id == IL_INVALID_STATION) { |
3493 | IL_ERR("Unable to prepare broadcast station\n"); | |
3494 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
3495 | ||
3496 | return -EINVAL; | |
3497 | } | |
3498 | ||
3499 | il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE; | |
3500 | il->stations[sta_id].used |= IL_STA_BCAST; | |
3501 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
3502 | ||
3503 | link_cmd = il4965_sta_alloc_lq(il, sta_id); | |
3504 | if (!link_cmd) { | |
e7392364 SG |
3505 | IL_ERR |
3506 | ("Unable to initialize rate scaling for bcast station.\n"); | |
eb3cdfb7 SG |
3507 | return -ENOMEM; |
3508 | } | |
3509 | ||
3510 | spin_lock_irqsave(&il->sta_lock, flags); | |
3511 | il->stations[sta_id].lq = link_cmd; | |
3512 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
3513 | ||
3514 | return 0; | |
3515 | } | |
3516 | ||
3517 | /** | |
3518 | * il4965_update_bcast_station - update broadcast station's LQ command | |
3519 | * | |
3520 | * Only used by iwl4965. Placed here to have all bcast station management | |
3521 | * code together. | |
3522 | */ | |
e7392364 | 3523 | static int |
83007196 | 3524 | il4965_update_bcast_station(struct il_priv *il) |
eb3cdfb7 SG |
3525 | { |
3526 | unsigned long flags; | |
3527 | struct il_link_quality_cmd *link_cmd; | |
b16db50a | 3528 | u8 sta_id = il->hw_params.bcast_id; |
eb3cdfb7 SG |
3529 | |
3530 | link_cmd = il4965_sta_alloc_lq(il, sta_id); | |
3531 | if (!link_cmd) { | |
1722f8e1 | 3532 | IL_ERR("Unable to initialize rate scaling for bcast sta.\n"); |
eb3cdfb7 SG |
3533 | return -ENOMEM; |
3534 | } | |
3535 | ||
3536 | spin_lock_irqsave(&il->sta_lock, flags); | |
3537 | if (il->stations[sta_id].lq) | |
3538 | kfree(il->stations[sta_id].lq); | |
3539 | else | |
1722f8e1 | 3540 | D_INFO("Bcast sta rate scaling has not been initialized.\n"); |
eb3cdfb7 SG |
3541 | il->stations[sta_id].lq = link_cmd; |
3542 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
3543 | ||
3544 | return 0; | |
3545 | } | |
3546 | ||
e7392364 SG |
3547 | int |
3548 | il4965_update_bcast_stations(struct il_priv *il) | |
eb3cdfb7 | 3549 | { |
83007196 | 3550 | return il4965_update_bcast_station(il); |
eb3cdfb7 SG |
3551 | } |
3552 | ||
3553 | /** | |
3554 | * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table | |
3555 | */ | |
e7392364 SG |
3556 | int |
3557 | il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid) | |
eb3cdfb7 SG |
3558 | { |
3559 | unsigned long flags; | |
3560 | struct il_addsta_cmd sta_cmd; | |
3561 | ||
3562 | lockdep_assert_held(&il->mutex); | |
3563 | ||
3564 | /* Remove "disable" flag, to enable Tx for this TID */ | |
3565 | spin_lock_irqsave(&il->sta_lock, flags); | |
3566 | il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX; | |
3567 | il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid)); | |
3568 | il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
3569 | memcpy(&sta_cmd, &il->stations[sta_id].sta, | |
e7392364 | 3570 | sizeof(struct il_addsta_cmd)); |
eb3cdfb7 SG |
3571 | spin_unlock_irqrestore(&il->sta_lock, flags); |
3572 | ||
3573 | return il_send_add_sta(il, &sta_cmd, CMD_SYNC); | |
3574 | } | |
3575 | ||
e7392364 SG |
3576 | int |
3577 | il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, int tid, | |
3578 | u16 ssn) | |
eb3cdfb7 SG |
3579 | { |
3580 | unsigned long flags; | |
3581 | int sta_id; | |
3582 | struct il_addsta_cmd sta_cmd; | |
3583 | ||
3584 | lockdep_assert_held(&il->mutex); | |
3585 | ||
3586 | sta_id = il_sta_id(sta); | |
3587 | if (sta_id == IL_INVALID_STATION) | |
3588 | return -ENXIO; | |
3589 | ||
3590 | spin_lock_irqsave(&il->sta_lock, flags); | |
3591 | il->stations[sta_id].sta.station_flags_msk = 0; | |
3592 | il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK; | |
e7392364 | 3593 | il->stations[sta_id].sta.add_immediate_ba_tid = (u8) tid; |
eb3cdfb7 SG |
3594 | il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn); |
3595 | il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
3596 | memcpy(&sta_cmd, &il->stations[sta_id].sta, | |
e7392364 | 3597 | sizeof(struct il_addsta_cmd)); |
eb3cdfb7 SG |
3598 | spin_unlock_irqrestore(&il->sta_lock, flags); |
3599 | ||
3600 | return il_send_add_sta(il, &sta_cmd, CMD_SYNC); | |
3601 | } | |
3602 | ||
e7392364 SG |
3603 | int |
3604 | il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, int tid) | |
eb3cdfb7 SG |
3605 | { |
3606 | unsigned long flags; | |
3607 | int sta_id; | |
3608 | struct il_addsta_cmd sta_cmd; | |
3609 | ||
3610 | lockdep_assert_held(&il->mutex); | |
3611 | ||
3612 | sta_id = il_sta_id(sta); | |
3613 | if (sta_id == IL_INVALID_STATION) { | |
3614 | IL_ERR("Invalid station for AGG tid %d\n", tid); | |
3615 | return -ENXIO; | |
3616 | } | |
3617 | ||
3618 | spin_lock_irqsave(&il->sta_lock, flags); | |
3619 | il->stations[sta_id].sta.station_flags_msk = 0; | |
3620 | il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK; | |
e7392364 | 3621 | il->stations[sta_id].sta.remove_immediate_ba_tid = (u8) tid; |
eb3cdfb7 SG |
3622 | il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; |
3623 | memcpy(&sta_cmd, &il->stations[sta_id].sta, | |
e7392364 | 3624 | sizeof(struct il_addsta_cmd)); |
eb3cdfb7 SG |
3625 | spin_unlock_irqrestore(&il->sta_lock, flags); |
3626 | ||
3627 | return il_send_add_sta(il, &sta_cmd, CMD_SYNC); | |
3628 | } | |
3629 | ||
3630 | void | |
3631 | il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt) | |
3632 | { | |
3633 | unsigned long flags; | |
3634 | ||
3635 | spin_lock_irqsave(&il->sta_lock, flags); | |
3636 | il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK; | |
3637 | il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK; | |
3638 | il->stations[sta_id].sta.sta.modify_mask = | |
e7392364 | 3639 | STA_MODIFY_SLEEP_TX_COUNT_MSK; |
eb3cdfb7 SG |
3640 | il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt); |
3641 | il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
e7392364 | 3642 | il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC); |
eb3cdfb7 SG |
3643 | spin_unlock_irqrestore(&il->sta_lock, flags); |
3644 | ||
3645 | } | |
3646 | ||
e7392364 SG |
3647 | void |
3648 | il4965_update_chain_flags(struct il_priv *il) | |
be663ab6 | 3649 | { |
c9363551 SG |
3650 | if (il->ops->set_rxon_chain) { |
3651 | il->ops->set_rxon_chain(il); | |
c8b03958 | 3652 | if (il->active.rx_chain != il->staging.rx_chain) |
83007196 | 3653 | il_commit_rxon(il); |
be663ab6 WYG |
3654 | } |
3655 | } | |
3656 | ||
e7392364 SG |
3657 | static void |
3658 | il4965_clear_free_frames(struct il_priv *il) | |
be663ab6 WYG |
3659 | { |
3660 | struct list_head *element; | |
3661 | ||
e7392364 | 3662 | D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count); |
be663ab6 | 3663 | |
46bc8d4b SG |
3664 | while (!list_empty(&il->free_frames)) { |
3665 | element = il->free_frames.next; | |
be663ab6 | 3666 | list_del(element); |
e2ebc833 | 3667 | kfree(list_entry(element, struct il_frame, list)); |
46bc8d4b | 3668 | il->frames_count--; |
be663ab6 WYG |
3669 | } |
3670 | ||
46bc8d4b | 3671 | if (il->frames_count) { |
9406f797 | 3672 | IL_WARN("%d frames still in use. Did we lose one?\n", |
e7392364 | 3673 | il->frames_count); |
46bc8d4b | 3674 | il->frames_count = 0; |
be663ab6 WYG |
3675 | } |
3676 | } | |
3677 | ||
e7392364 SG |
3678 | static struct il_frame * |
3679 | il4965_get_free_frame(struct il_priv *il) | |
be663ab6 | 3680 | { |
e2ebc833 | 3681 | struct il_frame *frame; |
be663ab6 | 3682 | struct list_head *element; |
46bc8d4b | 3683 | if (list_empty(&il->free_frames)) { |
be663ab6 WYG |
3684 | frame = kzalloc(sizeof(*frame), GFP_KERNEL); |
3685 | if (!frame) { | |
9406f797 | 3686 | IL_ERR("Could not allocate frame!\n"); |
be663ab6 WYG |
3687 | return NULL; |
3688 | } | |
3689 | ||
46bc8d4b | 3690 | il->frames_count++; |
be663ab6 WYG |
3691 | return frame; |
3692 | } | |
3693 | ||
46bc8d4b | 3694 | element = il->free_frames.next; |
be663ab6 | 3695 | list_del(element); |
e2ebc833 | 3696 | return list_entry(element, struct il_frame, list); |
be663ab6 WYG |
3697 | } |
3698 | ||
e7392364 SG |
3699 | static void |
3700 | il4965_free_frame(struct il_priv *il, struct il_frame *frame) | |
be663ab6 WYG |
3701 | { |
3702 | memset(frame, 0, sizeof(*frame)); | |
46bc8d4b | 3703 | list_add(&frame->list, &il->free_frames); |
be663ab6 WYG |
3704 | } |
3705 | ||
e7392364 SG |
3706 | static u32 |
3707 | il4965_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr, | |
3708 | int left) | |
be663ab6 | 3709 | { |
46bc8d4b | 3710 | lockdep_assert_held(&il->mutex); |
be663ab6 | 3711 | |
46bc8d4b | 3712 | if (!il->beacon_skb) |
be663ab6 WYG |
3713 | return 0; |
3714 | ||
46bc8d4b | 3715 | if (il->beacon_skb->len > left) |
be663ab6 WYG |
3716 | return 0; |
3717 | ||
46bc8d4b | 3718 | memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len); |
be663ab6 | 3719 | |
46bc8d4b | 3720 | return il->beacon_skb->len; |
be663ab6 WYG |
3721 | } |
3722 | ||
3723 | /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */ | |
e7392364 SG |
3724 | static void |
3725 | il4965_set_beacon_tim(struct il_priv *il, | |
3726 | struct il_tx_beacon_cmd *tx_beacon_cmd, u8 * beacon, | |
3727 | u32 frame_size) | |
be663ab6 WYG |
3728 | { |
3729 | u16 tim_idx; | |
3730 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon; | |
3731 | ||
3732 | /* | |
0c2c8852 | 3733 | * The idx is relative to frame start but we start looking at the |
be663ab6 WYG |
3734 | * variable-length part of the beacon. |
3735 | */ | |
3736 | tim_idx = mgmt->u.beacon.variable - beacon; | |
3737 | ||
3738 | /* Parse variable-length elements of beacon to find WLAN_EID_TIM */ | |
3739 | while ((tim_idx < (frame_size - 2)) && | |
e7392364 SG |
3740 | (beacon[tim_idx] != WLAN_EID_TIM)) |
3741 | tim_idx += beacon[tim_idx + 1] + 2; | |
be663ab6 WYG |
3742 | |
3743 | /* If TIM field was found, set variables */ | |
3744 | if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) { | |
3745 | tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx); | |
e7392364 | 3746 | tx_beacon_cmd->tim_size = beacon[tim_idx + 1]; |
be663ab6 | 3747 | } else |
9406f797 | 3748 | IL_WARN("Unable to find TIM Element in beacon\n"); |
be663ab6 WYG |
3749 | } |
3750 | ||
e7392364 SG |
3751 | static unsigned int |
3752 | il4965_hw_get_beacon_cmd(struct il_priv *il, struct il_frame *frame) | |
be663ab6 | 3753 | { |
e2ebc833 | 3754 | struct il_tx_beacon_cmd *tx_beacon_cmd; |
be663ab6 WYG |
3755 | u32 frame_size; |
3756 | u32 rate_flags; | |
3757 | u32 rate; | |
3758 | /* | |
3759 | * We have to set up the TX command, the TX Beacon command, and the | |
3760 | * beacon contents. | |
3761 | */ | |
3762 | ||
46bc8d4b | 3763 | lockdep_assert_held(&il->mutex); |
be663ab6 | 3764 | |
83007196 SG |
3765 | if (!il->beacon_enabled) { |
3766 | IL_ERR("Trying to build beacon without beaconing enabled\n"); | |
be663ab6 WYG |
3767 | return 0; |
3768 | } | |
3769 | ||
3770 | /* Initialize memory */ | |
3771 | tx_beacon_cmd = &frame->u.beacon; | |
3772 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
3773 | ||
3774 | /* Set up TX beacon contents */ | |
e7392364 SG |
3775 | frame_size = |
3776 | il4965_fill_beacon_frame(il, tx_beacon_cmd->frame, | |
3777 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); | |
be663ab6 WYG |
3778 | if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE)) |
3779 | return 0; | |
3780 | if (!frame_size) | |
3781 | return 0; | |
3782 | ||
3783 | /* Set up TX command fields */ | |
e7392364 | 3784 | tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size); |
b16db50a | 3785 | tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id; |
be663ab6 | 3786 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
e7392364 SG |
3787 | tx_beacon_cmd->tx.tx_flags = |
3788 | TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK | | |
3789 | TX_CMD_FLG_STA_RATE_MSK; | |
be663ab6 WYG |
3790 | |
3791 | /* Set up TX beacon command fields */ | |
e7392364 SG |
3792 | il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *) tx_beacon_cmd->frame, |
3793 | frame_size); | |
be663ab6 WYG |
3794 | |
3795 | /* Set up packet rate and flags */ | |
83007196 | 3796 | rate = il_get_lowest_plcp(il); |
a0c1ef3b | 3797 | il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant); |
616107ed | 3798 | rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS; |
e2ebc833 | 3799 | if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE)) |
be663ab6 | 3800 | rate_flags |= RATE_MCS_CCK_MSK; |
616107ed | 3801 | tx_beacon_cmd->tx.rate_n_flags = cpu_to_le32(rate | rate_flags); |
be663ab6 WYG |
3802 | |
3803 | return sizeof(*tx_beacon_cmd) + frame_size; | |
3804 | } | |
3805 | ||
e7392364 SG |
3806 | int |
3807 | il4965_send_beacon_cmd(struct il_priv *il) | |
be663ab6 | 3808 | { |
e2ebc833 | 3809 | struct il_frame *frame; |
be663ab6 WYG |
3810 | unsigned int frame_size; |
3811 | int rc; | |
3812 | ||
46bc8d4b | 3813 | frame = il4965_get_free_frame(il); |
be663ab6 | 3814 | if (!frame) { |
9406f797 | 3815 | IL_ERR("Could not obtain free frame buffer for beacon " |
e7392364 | 3816 | "command.\n"); |
be663ab6 WYG |
3817 | return -ENOMEM; |
3818 | } | |
3819 | ||
46bc8d4b | 3820 | frame_size = il4965_hw_get_beacon_cmd(il, frame); |
be663ab6 | 3821 | if (!frame_size) { |
9406f797 | 3822 | IL_ERR("Error configuring the beacon command\n"); |
46bc8d4b | 3823 | il4965_free_frame(il, frame); |
be663ab6 WYG |
3824 | return -EINVAL; |
3825 | } | |
3826 | ||
e7392364 | 3827 | rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]); |
be663ab6 | 3828 | |
46bc8d4b | 3829 | il4965_free_frame(il, frame); |
be663ab6 WYG |
3830 | |
3831 | return rc; | |
3832 | } | |
3833 | ||
e7392364 SG |
3834 | static inline dma_addr_t |
3835 | il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx) | |
be663ab6 | 3836 | { |
e2ebc833 | 3837 | struct il_tfd_tb *tb = &tfd->tbs[idx]; |
be663ab6 WYG |
3838 | |
3839 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
3840 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
3841 | addr |= | |
e7392364 SG |
3842 | ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << |
3843 | 16; | |
be663ab6 WYG |
3844 | |
3845 | return addr; | |
3846 | } | |
3847 | ||
e7392364 SG |
3848 | static inline u16 |
3849 | il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx) | |
be663ab6 | 3850 | { |
e2ebc833 | 3851 | struct il_tfd_tb *tb = &tfd->tbs[idx]; |
be663ab6 WYG |
3852 | |
3853 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
3854 | } | |
3855 | ||
e7392364 SG |
3856 | static inline void |
3857 | il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, dma_addr_t addr, u16 len) | |
be663ab6 | 3858 | { |
e2ebc833 | 3859 | struct il_tfd_tb *tb = &tfd->tbs[idx]; |
be663ab6 WYG |
3860 | u16 hi_n_len = len << 4; |
3861 | ||
3862 | put_unaligned_le32(addr, &tb->lo); | |
3863 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
3864 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
3865 | ||
3866 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
3867 | ||
3868 | tfd->num_tbs = idx + 1; | |
3869 | } | |
3870 | ||
e7392364 SG |
3871 | static inline u8 |
3872 | il4965_tfd_get_num_tbs(struct il_tfd *tfd) | |
be663ab6 WYG |
3873 | { |
3874 | return tfd->num_tbs & 0x1f; | |
3875 | } | |
3876 | ||
3877 | /** | |
e2ebc833 | 3878 | * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] |
46bc8d4b | 3879 | * @il - driver ilate data |
be663ab6 WYG |
3880 | * @txq - tx queue |
3881 | * | |
0c2c8852 | 3882 | * Does NOT advance any TFD circular buffer read/write idxes |
be663ab6 WYG |
3883 | * Does NOT free the TFD itself (which is within circular buffer) |
3884 | */ | |
e7392364 SG |
3885 | void |
3886 | il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq) | |
be663ab6 | 3887 | { |
e2ebc833 SG |
3888 | struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds; |
3889 | struct il_tfd *tfd; | |
46bc8d4b | 3890 | struct pci_dev *dev = il->pci_dev; |
0c2c8852 | 3891 | int idx = txq->q.read_ptr; |
be663ab6 WYG |
3892 | int i; |
3893 | int num_tbs; | |
3894 | ||
0c2c8852 | 3895 | tfd = &tfd_tmp[idx]; |
be663ab6 WYG |
3896 | |
3897 | /* Sanity check on number of chunks */ | |
e2ebc833 | 3898 | num_tbs = il4965_tfd_get_num_tbs(tfd); |
be663ab6 | 3899 | |
e2ebc833 | 3900 | if (num_tbs >= IL_NUM_OF_TBS) { |
9406f797 | 3901 | IL_ERR("Too many chunks: %i\n", num_tbs); |
be663ab6 WYG |
3902 | /* @todo issue fatal error, it is quite serious situation */ |
3903 | return; | |
3904 | } | |
3905 | ||
3906 | /* Unmap tx_cmd */ | |
3907 | if (num_tbs) | |
e7392364 SG |
3908 | pci_unmap_single(dev, dma_unmap_addr(&txq->meta[idx], mapping), |
3909 | dma_unmap_len(&txq->meta[idx], len), | |
3910 | PCI_DMA_BIDIRECTIONAL); | |
be663ab6 WYG |
3911 | |
3912 | /* Unmap chunks, if any. */ | |
3913 | for (i = 1; i < num_tbs; i++) | |
e2ebc833 | 3914 | pci_unmap_single(dev, il4965_tfd_tb_get_addr(tfd, i), |
e7392364 SG |
3915 | il4965_tfd_tb_get_len(tfd, i), |
3916 | PCI_DMA_TODEVICE); | |
be663ab6 WYG |
3917 | |
3918 | /* free SKB */ | |
00ea99e1 SG |
3919 | if (txq->skbs) { |
3920 | struct sk_buff *skb = txq->skbs[txq->q.read_ptr]; | |
be663ab6 WYG |
3921 | |
3922 | /* can be called from irqs-disabled context */ | |
3923 | if (skb) { | |
3924 | dev_kfree_skb_any(skb); | |
00ea99e1 | 3925 | txq->skbs[txq->q.read_ptr] = NULL; |
be663ab6 WYG |
3926 | } |
3927 | } | |
3928 | } | |
3929 | ||
e7392364 SG |
3930 | int |
3931 | il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq, | |
3932 | dma_addr_t addr, u16 len, u8 reset, u8 pad) | |
be663ab6 | 3933 | { |
e2ebc833 SG |
3934 | struct il_queue *q; |
3935 | struct il_tfd *tfd, *tfd_tmp; | |
be663ab6 WYG |
3936 | u32 num_tbs; |
3937 | ||
3938 | q = &txq->q; | |
e2ebc833 | 3939 | tfd_tmp = (struct il_tfd *)txq->tfds; |
be663ab6 WYG |
3940 | tfd = &tfd_tmp[q->write_ptr]; |
3941 | ||
3942 | if (reset) | |
3943 | memset(tfd, 0, sizeof(*tfd)); | |
3944 | ||
e2ebc833 | 3945 | num_tbs = il4965_tfd_get_num_tbs(tfd); |
be663ab6 WYG |
3946 | |
3947 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
e2ebc833 | 3948 | if (num_tbs >= IL_NUM_OF_TBS) { |
9406f797 | 3949 | IL_ERR("Error can not send more than %d chunks\n", |
e7392364 | 3950 | IL_NUM_OF_TBS); |
be663ab6 WYG |
3951 | return -EINVAL; |
3952 | } | |
3953 | ||
3954 | BUG_ON(addr & ~DMA_BIT_MASK(36)); | |
e2ebc833 | 3955 | if (unlikely(addr & ~IL_TX_DMA_MASK)) |
e7392364 | 3956 | IL_ERR("Unaligned address = %llx\n", (unsigned long long)addr); |
be663ab6 | 3957 | |
e2ebc833 | 3958 | il4965_tfd_set_tb(tfd, num_tbs, addr, len); |
be663ab6 WYG |
3959 | |
3960 | return 0; | |
3961 | } | |
3962 | ||
3963 | /* | |
3964 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
3965 | * given Tx queue, and enable the DMA channel used for that queue. | |
3966 | * | |
3967 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
3968 | * channels supported in hardware. | |
3969 | */ | |
e7392364 SG |
3970 | int |
3971 | il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq) | |
be663ab6 WYG |
3972 | { |
3973 | int txq_id = txq->q.id; | |
3974 | ||
3975 | /* Circular buffer (TFD queue in DRAM) physical base address */ | |
e7392364 | 3976 | il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8); |
be663ab6 WYG |
3977 | |
3978 | return 0; | |
3979 | } | |
3980 | ||
3981 | /****************************************************************************** | |
3982 | * | |
3983 | * Generic RX handler implementations | |
3984 | * | |
3985 | ******************************************************************************/ | |
e7392364 SG |
3986 | static void |
3987 | il4965_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb) | |
be663ab6 | 3988 | { |
dcae1c64 | 3989 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
e2ebc833 | 3990 | struct il_alive_resp *palive; |
be663ab6 WYG |
3991 | struct delayed_work *pwork; |
3992 | ||
3993 | palive = &pkt->u.alive_frame; | |
3994 | ||
e7392364 SG |
3995 | D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n", |
3996 | palive->is_valid, palive->ver_type, palive->ver_subtype); | |
be663ab6 WYG |
3997 | |
3998 | if (palive->ver_subtype == INITIALIZE_SUBTYPE) { | |
58de00a4 | 3999 | D_INFO("Initialization Alive received.\n"); |
e7392364 | 4000 | memcpy(&il->card_alive_init, &pkt->u.alive_frame, |
e2ebc833 | 4001 | sizeof(struct il_init_alive_resp)); |
46bc8d4b | 4002 | pwork = &il->init_alive_start; |
be663ab6 | 4003 | } else { |
58de00a4 | 4004 | D_INFO("Runtime Alive received.\n"); |
46bc8d4b | 4005 | memcpy(&il->card_alive, &pkt->u.alive_frame, |
e2ebc833 | 4006 | sizeof(struct il_alive_resp)); |
46bc8d4b | 4007 | pwork = &il->alive_start; |
be663ab6 WYG |
4008 | } |
4009 | ||
4010 | /* We delay the ALIVE response by 5ms to | |
4011 | * give the HW RF Kill time to activate... */ | |
4012 | if (palive->is_valid == UCODE_VALID_OK) | |
e7392364 | 4013 | queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5)); |
be663ab6 | 4014 | else |
9406f797 | 4015 | IL_WARN("uCode did not respond OK.\n"); |
be663ab6 WYG |
4016 | } |
4017 | ||
4018 | /** | |
ebf0d90d | 4019 | * il4965_bg_stats_periodic - Timer callback to queue stats |
be663ab6 | 4020 | * |
ebf0d90d | 4021 | * This callback is provided in order to send a stats request. |
be663ab6 WYG |
4022 | * |
4023 | * This timer function is continually reset to execute within | |
527901d0 SG |
4024 | * 60 seconds since the last N_STATS was received. We need to |
4025 | * ensure we receive the stats in order to update the temperature | |
4026 | * used for calibrating the TXPOWER. | |
be663ab6 | 4027 | */ |
e7392364 SG |
4028 | static void |
4029 | il4965_bg_stats_periodic(unsigned long data) | |
be663ab6 | 4030 | { |
46bc8d4b | 4031 | struct il_priv *il = (struct il_priv *)data; |
be663ab6 | 4032 | |
a6766ccd | 4033 | if (test_bit(S_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
4034 | return; |
4035 | ||
4036 | /* dont send host command if rf-kill is on */ | |
46bc8d4b | 4037 | if (!il_is_ready_rf(il)) |
be663ab6 WYG |
4038 | return; |
4039 | ||
ebf0d90d | 4040 | il_send_stats_request(il, CMD_ASYNC, false); |
be663ab6 WYG |
4041 | } |
4042 | ||
e7392364 SG |
4043 | static void |
4044 | il4965_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb) | |
be663ab6 | 4045 | { |
dcae1c64 | 4046 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
e2ebc833 | 4047 | struct il4965_beacon_notif *beacon = |
e7392364 | 4048 | (struct il4965_beacon_notif *)pkt->u.raw; |
d3175167 | 4049 | #ifdef CONFIG_IWLEGACY_DEBUG |
e2ebc833 | 4050 | u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); |
be663ab6 | 4051 | |
5bf0dac4 | 4052 | D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n", |
e7392364 SG |
4053 | le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, |
4054 | beacon->beacon_notify_hdr.failure_frame, | |
4055 | le32_to_cpu(beacon->ibss_mgr_status), | |
4056 | le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate); | |
be663ab6 | 4057 | #endif |
46bc8d4b | 4058 | il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status); |
be663ab6 WYG |
4059 | } |
4060 | ||
e7392364 SG |
4061 | static void |
4062 | il4965_perform_ct_kill_task(struct il_priv *il) | |
be663ab6 WYG |
4063 | { |
4064 | unsigned long flags; | |
4065 | ||
58de00a4 | 4066 | D_POWER("Stop all queues\n"); |
be663ab6 | 4067 | |
46bc8d4b SG |
4068 | if (il->mac80211_registered) |
4069 | ieee80211_stop_queues(il->hw); | |
be663ab6 | 4070 | |
841b2cca | 4071 | _il_wr(il, CSR_UCODE_DRV_GP1_SET, |
e7392364 | 4072 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); |
841b2cca | 4073 | _il_rd(il, CSR_UCODE_DRV_GP1); |
be663ab6 | 4074 | |
46bc8d4b | 4075 | spin_lock_irqsave(&il->reg_lock, flags); |
1e0f32a4 | 4076 | if (likely(_il_grab_nic_access(il))) |
13882269 | 4077 | _il_release_nic_access(il); |
46bc8d4b | 4078 | spin_unlock_irqrestore(&il->reg_lock, flags); |
be663ab6 WYG |
4079 | } |
4080 | ||
4081 | /* Handle notification from uCode that card's power state is changing | |
4082 | * due to software, hardware, or critical temperature RFKILL */ | |
e7392364 SG |
4083 | static void |
4084 | il4965_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb) | |
be663ab6 | 4085 | { |
dcae1c64 | 4086 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
be663ab6 | 4087 | u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); |
46bc8d4b | 4088 | unsigned long status = il->status; |
be663ab6 | 4089 | |
58de00a4 | 4090 | D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n", |
e7392364 SG |
4091 | (flags & HW_CARD_DISABLED) ? "Kill" : "On", |
4092 | (flags & SW_CARD_DISABLED) ? "Kill" : "On", | |
4093 | (flags & CT_CARD_DISABLED) ? "Reached" : "Not reached"); | |
be663ab6 | 4094 | |
e7392364 | 4095 | if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | CT_CARD_DISABLED)) { |
be663ab6 | 4096 | |
841b2cca | 4097 | _il_wr(il, CSR_UCODE_DRV_GP1_SET, |
e7392364 | 4098 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
be663ab6 | 4099 | |
e7392364 | 4100 | il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
be663ab6 WYG |
4101 | |
4102 | if (!(flags & RXON_CARD_DISABLED)) { | |
841b2cca | 4103 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, |
e7392364 | 4104 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
0c1a94e2 | 4105 | il_wr(il, HBUS_TARG_MBX_C, |
e7392364 | 4106 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
be663ab6 WYG |
4107 | } |
4108 | } | |
4109 | ||
4110 | if (flags & CT_CARD_DISABLED) | |
46bc8d4b | 4111 | il4965_perform_ct_kill_task(il); |
be663ab6 WYG |
4112 | |
4113 | if (flags & HW_CARD_DISABLED) | |
bc269a8e | 4114 | set_bit(S_RFKILL, &il->status); |
be663ab6 | 4115 | else |
bc269a8e | 4116 | clear_bit(S_RFKILL, &il->status); |
be663ab6 WYG |
4117 | |
4118 | if (!(flags & RXON_CARD_DISABLED)) | |
46bc8d4b | 4119 | il_scan_cancel(il); |
be663ab6 | 4120 | |
bc269a8e SG |
4121 | if ((test_bit(S_RFKILL, &status) != |
4122 | test_bit(S_RFKILL, &il->status))) | |
46bc8d4b | 4123 | wiphy_rfkill_set_hw_state(il->hw->wiphy, |
bc269a8e | 4124 | test_bit(S_RFKILL, &il->status)); |
be663ab6 | 4125 | else |
46bc8d4b | 4126 | wake_up(&il->wait_command_queue); |
be663ab6 WYG |
4127 | } |
4128 | ||
4129 | /** | |
d0c72347 | 4130 | * il4965_setup_handlers - Initialize Rx handler callbacks |
be663ab6 WYG |
4131 | * |
4132 | * Setup the RX handlers for each of the reply types sent from the uCode | |
4133 | * to the host. | |
4134 | * | |
4135 | * This function chains into the hardware specific files for them to setup | |
4136 | * any hardware specific handlers as well. | |
4137 | */ | |
e7392364 SG |
4138 | static void |
4139 | il4965_setup_handlers(struct il_priv *il) | |
be663ab6 | 4140 | { |
6e9848b4 SG |
4141 | il->handlers[N_ALIVE] = il4965_hdl_alive; |
4142 | il->handlers[N_ERROR] = il_hdl_error; | |
d2dfb33e | 4143 | il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa; |
e7392364 | 4144 | il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement; |
d2dfb33e | 4145 | il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep; |
e7392364 | 4146 | il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats; |
d2dfb33e | 4147 | il->handlers[N_BEACON] = il4965_hdl_beacon; |
be663ab6 WYG |
4148 | |
4149 | /* | |
4150 | * The same handler is used for both the REPLY to a discrete | |
ebf0d90d SG |
4151 | * stats request from the host as well as for the periodic |
4152 | * stats notifications (after received beacons) from the uCode. | |
be663ab6 | 4153 | */ |
d2dfb33e SG |
4154 | il->handlers[C_STATS] = il4965_hdl_c_stats; |
4155 | il->handlers[N_STATS] = il4965_hdl_stats; | |
be663ab6 | 4156 | |
46bc8d4b | 4157 | il_setup_rx_scan_handlers(il); |
be663ab6 WYG |
4158 | |
4159 | /* status change handler */ | |
e7392364 | 4160 | il->handlers[N_CARD_STATE] = il4965_hdl_card_state; |
be663ab6 | 4161 | |
e7392364 | 4162 | il->handlers[N_MISSED_BEACONS] = il4965_hdl_missed_beacon; |
be663ab6 | 4163 | /* Rx handlers */ |
6e9848b4 SG |
4164 | il->handlers[N_RX_PHY] = il4965_hdl_rx_phy; |
4165 | il->handlers[N_RX_MPDU] = il4965_hdl_rx; | |
3dfea27d | 4166 | il->handlers[N_RX] = il4965_hdl_rx; |
be663ab6 | 4167 | /* block ack */ |
6e9848b4 | 4168 | il->handlers[N_COMPRESSED_BA] = il4965_hdl_compressed_ba; |
3dfea27d SG |
4169 | /* Tx response */ |
4170 | il->handlers[C_TX] = il4965_hdl_tx; | |
be663ab6 WYG |
4171 | } |
4172 | ||
4173 | /** | |
e2ebc833 | 4174 | * il4965_rx_handle - Main entry function for receiving responses from uCode |
be663ab6 | 4175 | * |
d0c72347 | 4176 | * Uses the il->handlers callback function array to invoke |
be663ab6 WYG |
4177 | * the appropriate handlers, including command responses, |
4178 | * frame-received notifications, and other notifications. | |
4179 | */ | |
e7392364 SG |
4180 | void |
4181 | il4965_rx_handle(struct il_priv *il) | |
be663ab6 | 4182 | { |
b73bb5f1 | 4183 | struct il_rx_buf *rxb; |
dcae1c64 | 4184 | struct il_rx_pkt *pkt; |
46bc8d4b | 4185 | struct il_rx_queue *rxq = &il->rxq; |
be663ab6 WYG |
4186 | u32 r, i; |
4187 | int reclaim; | |
4188 | unsigned long flags; | |
4189 | u8 fill_rx = 0; | |
4190 | u32 count = 8; | |
4191 | int total_empty; | |
4192 | ||
0c2c8852 | 4193 | /* uCode's read idx (stored in shared DRAM) indicates the last Rx |
be663ab6 | 4194 | * buffer that the driver may process (last buffer filled by ucode). */ |
e7392364 | 4195 | r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; |
be663ab6 WYG |
4196 | i = rxq->read; |
4197 | ||
4198 | /* Rx interrupt, but nothing sent from uCode */ | |
4199 | if (i == r) | |
58de00a4 | 4200 | D_RX("r = %d, i = %d\n", r, i); |
be663ab6 WYG |
4201 | |
4202 | /* calculate total frames need to be restock after handling RX */ | |
4203 | total_empty = r - rxq->write_actual; | |
4204 | if (total_empty < 0) | |
4205 | total_empty += RX_QUEUE_SIZE; | |
4206 | ||
4207 | if (total_empty > (RX_QUEUE_SIZE / 2)) | |
4208 | fill_rx = 1; | |
4209 | ||
4210 | while (i != r) { | |
4211 | int len; | |
4212 | ||
4213 | rxb = rxq->queue[i]; | |
4214 | ||
4215 | /* If an RXB doesn't have a Rx queue slot associated with it, | |
4216 | * then a bug has been introduced in the queue refilling | |
4217 | * routines -- catch it here */ | |
4218 | BUG_ON(rxb == NULL); | |
4219 | ||
4220 | rxq->queue[i] = NULL; | |
4221 | ||
46bc8d4b SG |
4222 | pci_unmap_page(il->pci_dev, rxb->page_dma, |
4223 | PAGE_SIZE << il->hw_params.rx_page_order, | |
be663ab6 WYG |
4224 | PCI_DMA_FROMDEVICE); |
4225 | pkt = rxb_addr(rxb); | |
4226 | ||
e94a4099 | 4227 | len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK; |
e7392364 | 4228 | len += sizeof(u32); /* account for status word */ |
be663ab6 WYG |
4229 | |
4230 | /* Reclaim a command buffer only if this packet is a response | |
4231 | * to a (driver-originated) command. | |
4232 | * If the packet (e.g. Rx frame) originated from uCode, | |
4233 | * there is no command buffer to reclaim. | |
4234 | * Ucode should set SEQ_RX_FRAME bit if ucode-originated, | |
4235 | * but apparently a few don't get set; catch them here. */ | |
4236 | reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) && | |
e7392364 SG |
4237 | (pkt->hdr.cmd != N_RX_PHY) && (pkt->hdr.cmd != N_RX) && |
4238 | (pkt->hdr.cmd != N_RX_MPDU) && | |
4239 | (pkt->hdr.cmd != N_COMPRESSED_BA) && | |
4240 | (pkt->hdr.cmd != N_STATS) && (pkt->hdr.cmd != C_TX); | |
be663ab6 WYG |
4241 | |
4242 | /* Based on type of command response or notification, | |
4243 | * handle those that need handling via function in | |
d0c72347 SG |
4244 | * handlers table. See il4965_setup_handlers() */ |
4245 | if (il->handlers[pkt->hdr.cmd]) { | |
e7392364 SG |
4246 | D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i, |
4247 | il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); | |
d0c72347 SG |
4248 | il->isr_stats.handlers[pkt->hdr.cmd]++; |
4249 | il->handlers[pkt->hdr.cmd] (il, rxb); | |
be663ab6 WYG |
4250 | } else { |
4251 | /* No handling needed */ | |
e7392364 SG |
4252 | D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r, |
4253 | i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); | |
be663ab6 WYG |
4254 | } |
4255 | ||
4256 | /* | |
4257 | * XXX: After here, we should always check rxb->page | |
4258 | * against NULL before touching it or its virtual | |
d0c72347 | 4259 | * memory (pkt). Because some handler might have |
be663ab6 WYG |
4260 | * already taken or freed the pages. |
4261 | */ | |
4262 | ||
4263 | if (reclaim) { | |
4264 | /* Invoke any callbacks, transfer the buffer to caller, | |
e2ebc833 | 4265 | * and fire off the (possibly) blocking il_send_cmd() |
be663ab6 WYG |
4266 | * as we reclaim the driver command queue */ |
4267 | if (rxb->page) | |
46bc8d4b | 4268 | il_tx_cmd_complete(il, rxb); |
be663ab6 | 4269 | else |
9406f797 | 4270 | IL_WARN("Claim null rxb?\n"); |
be663ab6 WYG |
4271 | } |
4272 | ||
4273 | /* Reuse the page if possible. For notification packets and | |
4274 | * SKBs that fail to Rx correctly, add them back into the | |
4275 | * rx_free list for reuse later. */ | |
4276 | spin_lock_irqsave(&rxq->lock, flags); | |
4277 | if (rxb->page != NULL) { | |
e7392364 SG |
4278 | rxb->page_dma = |
4279 | pci_map_page(il->pci_dev, rxb->page, 0, | |
4280 | PAGE_SIZE << il->hw_params. | |
4281 | rx_page_order, PCI_DMA_FROMDEVICE); | |
be663ab6 WYG |
4282 | list_add_tail(&rxb->list, &rxq->rx_free); |
4283 | rxq->free_count++; | |
4284 | } else | |
4285 | list_add_tail(&rxb->list, &rxq->rx_used); | |
4286 | ||
4287 | spin_unlock_irqrestore(&rxq->lock, flags); | |
4288 | ||
4289 | i = (i + 1) & RX_QUEUE_MASK; | |
4290 | /* If there are a lot of unused frames, | |
4291 | * restock the Rx queue so ucode wont assert. */ | |
4292 | if (fill_rx) { | |
4293 | count++; | |
4294 | if (count >= 8) { | |
4295 | rxq->read = i; | |
46bc8d4b | 4296 | il4965_rx_replenish_now(il); |
be663ab6 WYG |
4297 | count = 0; |
4298 | } | |
4299 | } | |
4300 | } | |
4301 | ||
4302 | /* Backtrack one entry */ | |
4303 | rxq->read = i; | |
4304 | if (fill_rx) | |
46bc8d4b | 4305 | il4965_rx_replenish_now(il); |
be663ab6 | 4306 | else |
46bc8d4b | 4307 | il4965_rx_queue_restock(il); |
be663ab6 WYG |
4308 | } |
4309 | ||
4310 | /* call this function to flush any scheduled tasklet */ | |
e7392364 SG |
4311 | static inline void |
4312 | il4965_synchronize_irq(struct il_priv *il) | |
be663ab6 | 4313 | { |
e7392364 | 4314 | /* wait to make sure we flush pending tasklet */ |
46bc8d4b SG |
4315 | synchronize_irq(il->pci_dev->irq); |
4316 | tasklet_kill(&il->irq_tasklet); | |
be663ab6 WYG |
4317 | } |
4318 | ||
e7392364 SG |
4319 | static void |
4320 | il4965_irq_tasklet(struct il_priv *il) | |
be663ab6 WYG |
4321 | { |
4322 | u32 inta, handled = 0; | |
4323 | u32 inta_fh; | |
4324 | unsigned long flags; | |
4325 | u32 i; | |
d3175167 | 4326 | #ifdef CONFIG_IWLEGACY_DEBUG |
be663ab6 WYG |
4327 | u32 inta_mask; |
4328 | #endif | |
4329 | ||
46bc8d4b | 4330 | spin_lock_irqsave(&il->lock, flags); |
be663ab6 WYG |
4331 | |
4332 | /* Ack/clear/reset pending uCode interrupts. | |
4333 | * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, | |
4334 | * and will clear only when CSR_FH_INT_STATUS gets cleared. */ | |
841b2cca SG |
4335 | inta = _il_rd(il, CSR_INT); |
4336 | _il_wr(il, CSR_INT, inta); | |
be663ab6 WYG |
4337 | |
4338 | /* Ack/clear/reset pending flow-handler (DMA) interrupts. | |
4339 | * Any new interrupts that happen after this, either while we're | |
4340 | * in this tasklet, or later, will show up in next ISR/tasklet. */ | |
841b2cca SG |
4341 | inta_fh = _il_rd(il, CSR_FH_INT_STATUS); |
4342 | _il_wr(il, CSR_FH_INT_STATUS, inta_fh); | |
be663ab6 | 4343 | |
d3175167 | 4344 | #ifdef CONFIG_IWLEGACY_DEBUG |
46bc8d4b | 4345 | if (il_get_debug_level(il) & IL_DL_ISR) { |
be663ab6 | 4346 | /* just for debug */ |
841b2cca | 4347 | inta_mask = _il_rd(il, CSR_INT_MASK); |
e7392364 SG |
4348 | D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, |
4349 | inta_mask, inta_fh); | |
be663ab6 WYG |
4350 | } |
4351 | #endif | |
4352 | ||
46bc8d4b | 4353 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 WYG |
4354 | |
4355 | /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not | |
4356 | * atomic, make sure that inta covers all the interrupts that | |
4357 | * we've discovered, even if FH interrupt came in just after | |
4358 | * reading CSR_INT. */ | |
4359 | if (inta_fh & CSR49_FH_INT_RX_MASK) | |
4360 | inta |= CSR_INT_BIT_FH_RX; | |
4361 | if (inta_fh & CSR49_FH_INT_TX_MASK) | |
4362 | inta |= CSR_INT_BIT_FH_TX; | |
4363 | ||
4364 | /* Now service all interrupt bits discovered above. */ | |
4365 | if (inta & CSR_INT_BIT_HW_ERR) { | |
9406f797 | 4366 | IL_ERR("Hardware error detected. Restarting.\n"); |
be663ab6 WYG |
4367 | |
4368 | /* Tell the device to stop sending interrupts */ | |
46bc8d4b | 4369 | il_disable_interrupts(il); |
be663ab6 | 4370 | |
46bc8d4b SG |
4371 | il->isr_stats.hw++; |
4372 | il_irq_handle_error(il); | |
be663ab6 WYG |
4373 | |
4374 | handled |= CSR_INT_BIT_HW_ERR; | |
4375 | ||
4376 | return; | |
4377 | } | |
d3175167 | 4378 | #ifdef CONFIG_IWLEGACY_DEBUG |
46bc8d4b | 4379 | if (il_get_debug_level(il) & (IL_DL_ISR)) { |
be663ab6 WYG |
4380 | /* NIC fires this, but we don't use it, redundant with WAKEUP */ |
4381 | if (inta & CSR_INT_BIT_SCD) { | |
58de00a4 | 4382 | D_ISR("Scheduler finished to transmit " |
e7392364 | 4383 | "the frame/frames.\n"); |
46bc8d4b | 4384 | il->isr_stats.sch++; |
be663ab6 WYG |
4385 | } |
4386 | ||
4387 | /* Alive notification via Rx interrupt will do the real work */ | |
4388 | if (inta & CSR_INT_BIT_ALIVE) { | |
58de00a4 | 4389 | D_ISR("Alive interrupt\n"); |
46bc8d4b | 4390 | il->isr_stats.alive++; |
be663ab6 WYG |
4391 | } |
4392 | } | |
4393 | #endif | |
4394 | /* Safely ignore these bits for debug checks below */ | |
4395 | inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); | |
4396 | ||
4397 | /* HW RF KILL switch toggled */ | |
4398 | if (inta & CSR_INT_BIT_RF_KILL) { | |
4399 | int hw_rf_kill = 0; | |
c9363551 SG |
4400 | |
4401 | if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) | |
be663ab6 WYG |
4402 | hw_rf_kill = 1; |
4403 | ||
9406f797 | 4404 | IL_WARN("RF_KILL bit toggled to %s.\n", |
e7392364 | 4405 | hw_rf_kill ? "disable radio" : "enable radio"); |
be663ab6 | 4406 | |
46bc8d4b | 4407 | il->isr_stats.rfkill++; |
be663ab6 WYG |
4408 | |
4409 | /* driver only loads ucode once setting the interface up. | |
4410 | * the driver allows loading the ucode even if the radio | |
4411 | * is killed. Hence update the killswitch state here. The | |
4412 | * rfkill handler will care about restarting if needed. | |
4413 | */ | |
a6766ccd | 4414 | if (!test_bit(S_ALIVE, &il->status)) { |
be663ab6 | 4415 | if (hw_rf_kill) |
bc269a8e | 4416 | set_bit(S_RFKILL, &il->status); |
be663ab6 | 4417 | else |
bc269a8e | 4418 | clear_bit(S_RFKILL, &il->status); |
46bc8d4b | 4419 | wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill); |
be663ab6 WYG |
4420 | } |
4421 | ||
4422 | handled |= CSR_INT_BIT_RF_KILL; | |
4423 | } | |
4424 | ||
4425 | /* Chip got too hot and stopped itself */ | |
4426 | if (inta & CSR_INT_BIT_CT_KILL) { | |
9406f797 | 4427 | IL_ERR("Microcode CT kill error detected.\n"); |
46bc8d4b | 4428 | il->isr_stats.ctkill++; |
be663ab6 WYG |
4429 | handled |= CSR_INT_BIT_CT_KILL; |
4430 | } | |
4431 | ||
4432 | /* Error detected by uCode */ | |
4433 | if (inta & CSR_INT_BIT_SW_ERR) { | |
e7392364 SG |
4434 | IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n", |
4435 | inta); | |
46bc8d4b SG |
4436 | il->isr_stats.sw++; |
4437 | il_irq_handle_error(il); | |
be663ab6 WYG |
4438 | handled |= CSR_INT_BIT_SW_ERR; |
4439 | } | |
4440 | ||
4441 | /* | |
4442 | * uCode wakes up after power-down sleep. | |
4443 | * Tell device about any new tx or host commands enqueued, | |
4444 | * and about any Rx buffers made available while asleep. | |
4445 | */ | |
4446 | if (inta & CSR_INT_BIT_WAKEUP) { | |
58de00a4 | 4447 | D_ISR("Wakeup interrupt\n"); |
46bc8d4b SG |
4448 | il_rx_queue_update_write_ptr(il, &il->rxq); |
4449 | for (i = 0; i < il->hw_params.max_txq_num; i++) | |
4450 | il_txq_update_write_ptr(il, &il->txq[i]); | |
4451 | il->isr_stats.wakeup++; | |
be663ab6 WYG |
4452 | handled |= CSR_INT_BIT_WAKEUP; |
4453 | } | |
4454 | ||
4455 | /* All uCode command responses, including Tx command responses, | |
4456 | * Rx "responses" (frame-received notification), and other | |
4457 | * notifications from uCode come through here*/ | |
4458 | if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { | |
46bc8d4b SG |
4459 | il4965_rx_handle(il); |
4460 | il->isr_stats.rx++; | |
be663ab6 WYG |
4461 | handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); |
4462 | } | |
4463 | ||
4464 | /* This "Tx" DMA channel is used only for loading uCode */ | |
4465 | if (inta & CSR_INT_BIT_FH_TX) { | |
58de00a4 | 4466 | D_ISR("uCode load interrupt\n"); |
46bc8d4b | 4467 | il->isr_stats.tx++; |
be663ab6 WYG |
4468 | handled |= CSR_INT_BIT_FH_TX; |
4469 | /* Wake up uCode load routine, now that load is complete */ | |
46bc8d4b SG |
4470 | il->ucode_write_complete = 1; |
4471 | wake_up(&il->wait_command_queue); | |
be663ab6 WYG |
4472 | } |
4473 | ||
4474 | if (inta & ~handled) { | |
9406f797 | 4475 | IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled); |
46bc8d4b | 4476 | il->isr_stats.unhandled++; |
be663ab6 WYG |
4477 | } |
4478 | ||
46bc8d4b | 4479 | if (inta & ~(il->inta_mask)) { |
9406f797 | 4480 | IL_WARN("Disabled INTA bits 0x%08x were pending\n", |
e7392364 | 4481 | inta & ~il->inta_mask); |
9a95b370 | 4482 | IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh); |
be663ab6 WYG |
4483 | } |
4484 | ||
4485 | /* Re-enable all interrupts */ | |
93fd74e3 | 4486 | /* only Re-enable if disabled by irq */ |
a6766ccd | 4487 | if (test_bit(S_INT_ENABLED, &il->status)) |
46bc8d4b | 4488 | il_enable_interrupts(il); |
a078a1fd SG |
4489 | /* Re-enable RF_KILL if it occurred */ |
4490 | else if (handled & CSR_INT_BIT_RF_KILL) | |
46bc8d4b | 4491 | il_enable_rfkill_int(il); |
be663ab6 | 4492 | |
d3175167 | 4493 | #ifdef CONFIG_IWLEGACY_DEBUG |
46bc8d4b | 4494 | if (il_get_debug_level(il) & (IL_DL_ISR)) { |
841b2cca SG |
4495 | inta = _il_rd(il, CSR_INT); |
4496 | inta_mask = _il_rd(il, CSR_INT_MASK); | |
4497 | inta_fh = _il_rd(il, CSR_FH_INT_STATUS); | |
e7392364 SG |
4498 | D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " |
4499 | "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); | |
be663ab6 WYG |
4500 | } |
4501 | #endif | |
4502 | } | |
4503 | ||
4504 | /***************************************************************************** | |
4505 | * | |
4506 | * sysfs attributes | |
4507 | * | |
4508 | *****************************************************************************/ | |
4509 | ||
d3175167 | 4510 | #ifdef CONFIG_IWLEGACY_DEBUG |
be663ab6 WYG |
4511 | |
4512 | /* | |
4513 | * The following adds a new attribute to the sysfs representation | |
4514 | * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) | |
4515 | * used for controlling the debug level. | |
4516 | * | |
4517 | * See the level definitions in iwl for details. | |
4518 | * | |
4519 | * The debug_level being managed using sysfs below is a per device debug | |
4520 | * level that is used instead of the global debug level if it (the per | |
4521 | * device debug level) is set. | |
4522 | */ | |
e7392364 SG |
4523 | static ssize_t |
4524 | il4965_show_debug_level(struct device *d, struct device_attribute *attr, | |
4525 | char *buf) | |
be663ab6 | 4526 | { |
46bc8d4b SG |
4527 | struct il_priv *il = dev_get_drvdata(d); |
4528 | return sprintf(buf, "0x%08X\n", il_get_debug_level(il)); | |
be663ab6 | 4529 | } |
e7392364 SG |
4530 | |
4531 | static ssize_t | |
4532 | il4965_store_debug_level(struct device *d, struct device_attribute *attr, | |
4533 | const char *buf, size_t count) | |
be663ab6 | 4534 | { |
46bc8d4b | 4535 | struct il_priv *il = dev_get_drvdata(d); |
be663ab6 WYG |
4536 | unsigned long val; |
4537 | int ret; | |
4538 | ||
4539 | ret = strict_strtoul(buf, 0, &val); | |
4540 | if (ret) | |
9406f797 | 4541 | IL_ERR("%s is not in hex or decimal form.\n", buf); |
288f9954 | 4542 | else |
46bc8d4b | 4543 | il->debug_level = val; |
288f9954 | 4544 | |
be663ab6 WYG |
4545 | return strnlen(buf, count); |
4546 | } | |
4547 | ||
e7392364 SG |
4548 | static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO, il4965_show_debug_level, |
4549 | il4965_store_debug_level); | |
be663ab6 | 4550 | |
d3175167 | 4551 | #endif /* CONFIG_IWLEGACY_DEBUG */ |
be663ab6 | 4552 | |
e7392364 SG |
4553 | static ssize_t |
4554 | il4965_show_temperature(struct device *d, struct device_attribute *attr, | |
4555 | char *buf) | |
be663ab6 | 4556 | { |
46bc8d4b | 4557 | struct il_priv *il = dev_get_drvdata(d); |
be663ab6 | 4558 | |
46bc8d4b | 4559 | if (!il_is_alive(il)) |
be663ab6 WYG |
4560 | return -EAGAIN; |
4561 | ||
46bc8d4b | 4562 | return sprintf(buf, "%d\n", il->temperature); |
be663ab6 WYG |
4563 | } |
4564 | ||
e2ebc833 | 4565 | static DEVICE_ATTR(temperature, S_IRUGO, il4965_show_temperature, NULL); |
be663ab6 | 4566 | |
e7392364 SG |
4567 | static ssize_t |
4568 | il4965_show_tx_power(struct device *d, struct device_attribute *attr, char *buf) | |
be663ab6 | 4569 | { |
46bc8d4b | 4570 | struct il_priv *il = dev_get_drvdata(d); |
be663ab6 | 4571 | |
46bc8d4b | 4572 | if (!il_is_ready_rf(il)) |
be663ab6 WYG |
4573 | return sprintf(buf, "off\n"); |
4574 | else | |
46bc8d4b | 4575 | return sprintf(buf, "%d\n", il->tx_power_user_lmt); |
be663ab6 WYG |
4576 | } |
4577 | ||
e7392364 SG |
4578 | static ssize_t |
4579 | il4965_store_tx_power(struct device *d, struct device_attribute *attr, | |
4580 | const char *buf, size_t count) | |
be663ab6 | 4581 | { |
46bc8d4b | 4582 | struct il_priv *il = dev_get_drvdata(d); |
be663ab6 WYG |
4583 | unsigned long val; |
4584 | int ret; | |
4585 | ||
4586 | ret = strict_strtoul(buf, 10, &val); | |
4587 | if (ret) | |
9406f797 | 4588 | IL_INFO("%s is not in decimal form.\n", buf); |
be663ab6 | 4589 | else { |
46bc8d4b | 4590 | ret = il_set_tx_power(il, val, false); |
be663ab6 | 4591 | if (ret) |
e7392364 | 4592 | IL_ERR("failed setting tx power (0x%d).\n", ret); |
be663ab6 WYG |
4593 | else |
4594 | ret = count; | |
4595 | } | |
4596 | return ret; | |
4597 | } | |
4598 | ||
e7392364 SG |
4599 | static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, il4965_show_tx_power, |
4600 | il4965_store_tx_power); | |
be663ab6 | 4601 | |
e2ebc833 | 4602 | static struct attribute *il_sysfs_entries[] = { |
be663ab6 WYG |
4603 | &dev_attr_temperature.attr, |
4604 | &dev_attr_tx_power.attr, | |
d3175167 | 4605 | #ifdef CONFIG_IWLEGACY_DEBUG |
be663ab6 WYG |
4606 | &dev_attr_debug_level.attr, |
4607 | #endif | |
4608 | NULL | |
4609 | }; | |
4610 | ||
e2ebc833 | 4611 | static struct attribute_group il_attribute_group = { |
be663ab6 | 4612 | .name = NULL, /* put in device directory */ |
e2ebc833 | 4613 | .attrs = il_sysfs_entries, |
be663ab6 WYG |
4614 | }; |
4615 | ||
4616 | /****************************************************************************** | |
4617 | * | |
4618 | * uCode download functions | |
4619 | * | |
4620 | ******************************************************************************/ | |
4621 | ||
e7392364 SG |
4622 | static void |
4623 | il4965_dealloc_ucode_pci(struct il_priv *il) | |
be663ab6 | 4624 | { |
46bc8d4b SG |
4625 | il_free_fw_desc(il->pci_dev, &il->ucode_code); |
4626 | il_free_fw_desc(il->pci_dev, &il->ucode_data); | |
4627 | il_free_fw_desc(il->pci_dev, &il->ucode_data_backup); | |
4628 | il_free_fw_desc(il->pci_dev, &il->ucode_init); | |
4629 | il_free_fw_desc(il->pci_dev, &il->ucode_init_data); | |
4630 | il_free_fw_desc(il->pci_dev, &il->ucode_boot); | |
be663ab6 WYG |
4631 | } |
4632 | ||
e7392364 SG |
4633 | static void |
4634 | il4965_nic_start(struct il_priv *il) | |
be663ab6 WYG |
4635 | { |
4636 | /* Remove all resets to allow NIC to operate */ | |
841b2cca | 4637 | _il_wr(il, CSR_RESET, 0); |
be663ab6 WYG |
4638 | } |
4639 | ||
e2ebc833 | 4640 | static void il4965_ucode_callback(const struct firmware *ucode_raw, |
e7392364 SG |
4641 | void *context); |
4642 | static int il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length); | |
be663ab6 | 4643 | |
e7392364 SG |
4644 | static int __must_check |
4645 | il4965_request_firmware(struct il_priv *il, bool first) | |
be663ab6 | 4646 | { |
46bc8d4b | 4647 | const char *name_pre = il->cfg->fw_name_pre; |
be663ab6 WYG |
4648 | char tag[8]; |
4649 | ||
4650 | if (first) { | |
0c2c8852 SG |
4651 | il->fw_idx = il->cfg->ucode_api_max; |
4652 | sprintf(tag, "%d", il->fw_idx); | |
be663ab6 | 4653 | } else { |
0c2c8852 SG |
4654 | il->fw_idx--; |
4655 | sprintf(tag, "%d", il->fw_idx); | |
be663ab6 WYG |
4656 | } |
4657 | ||
0c2c8852 | 4658 | if (il->fw_idx < il->cfg->ucode_api_min) { |
9406f797 | 4659 | IL_ERR("no suitable firmware found!\n"); |
be663ab6 WYG |
4660 | return -ENOENT; |
4661 | } | |
4662 | ||
46bc8d4b | 4663 | sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode"); |
be663ab6 | 4664 | |
e7392364 | 4665 | D_INFO("attempting to load firmware '%s'\n", il->firmware_name); |
be663ab6 | 4666 | |
46bc8d4b SG |
4667 | return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name, |
4668 | &il->pci_dev->dev, GFP_KERNEL, il, | |
e2ebc833 | 4669 | il4965_ucode_callback); |
be663ab6 WYG |
4670 | } |
4671 | ||
e2ebc833 | 4672 | struct il4965_firmware_pieces { |
be663ab6 WYG |
4673 | const void *inst, *data, *init, *init_data, *boot; |
4674 | size_t inst_size, data_size, init_size, init_data_size, boot_size; | |
4675 | }; | |
4676 | ||
e7392364 SG |
4677 | static int |
4678 | il4965_load_firmware(struct il_priv *il, const struct firmware *ucode_raw, | |
4679 | struct il4965_firmware_pieces *pieces) | |
be663ab6 | 4680 | { |
e2ebc833 | 4681 | struct il_ucode_header *ucode = (void *)ucode_raw->data; |
be663ab6 WYG |
4682 | u32 api_ver, hdr_size; |
4683 | const u8 *src; | |
4684 | ||
46bc8d4b SG |
4685 | il->ucode_ver = le32_to_cpu(ucode->ver); |
4686 | api_ver = IL_UCODE_API(il->ucode_ver); | |
be663ab6 WYG |
4687 | |
4688 | switch (api_ver) { | |
4689 | default: | |
4690 | case 0: | |
4691 | case 1: | |
4692 | case 2: | |
4693 | hdr_size = 24; | |
4694 | if (ucode_raw->size < hdr_size) { | |
9406f797 | 4695 | IL_ERR("File size too small!\n"); |
be663ab6 WYG |
4696 | return -EINVAL; |
4697 | } | |
4698 | pieces->inst_size = le32_to_cpu(ucode->v1.inst_size); | |
4699 | pieces->data_size = le32_to_cpu(ucode->v1.data_size); | |
4700 | pieces->init_size = le32_to_cpu(ucode->v1.init_size); | |
e7392364 | 4701 | pieces->init_data_size = le32_to_cpu(ucode->v1.init_data_size); |
be663ab6 WYG |
4702 | pieces->boot_size = le32_to_cpu(ucode->v1.boot_size); |
4703 | src = ucode->v1.data; | |
4704 | break; | |
4705 | } | |
4706 | ||
4707 | /* Verify size of file vs. image size info in file's header */ | |
e7392364 SG |
4708 | if (ucode_raw->size != |
4709 | hdr_size + pieces->inst_size + pieces->data_size + | |
4710 | pieces->init_size + pieces->init_data_size + pieces->boot_size) { | |
be663ab6 | 4711 | |
e7392364 SG |
4712 | IL_ERR("uCode file size %d does not match expected size\n", |
4713 | (int)ucode_raw->size); | |
be663ab6 WYG |
4714 | return -EINVAL; |
4715 | } | |
4716 | ||
4717 | pieces->inst = src; | |
4718 | src += pieces->inst_size; | |
4719 | pieces->data = src; | |
4720 | src += pieces->data_size; | |
4721 | pieces->init = src; | |
4722 | src += pieces->init_size; | |
4723 | pieces->init_data = src; | |
4724 | src += pieces->init_data_size; | |
4725 | pieces->boot = src; | |
4726 | src += pieces->boot_size; | |
4727 | ||
4728 | return 0; | |
4729 | } | |
4730 | ||
4731 | /** | |
e2ebc833 | 4732 | * il4965_ucode_callback - callback when firmware was loaded |
be663ab6 WYG |
4733 | * |
4734 | * If loaded successfully, copies the firmware into buffers | |
4735 | * for the card to fetch (via DMA). | |
4736 | */ | |
4737 | static void | |
e2ebc833 | 4738 | il4965_ucode_callback(const struct firmware *ucode_raw, void *context) |
be663ab6 | 4739 | { |
46bc8d4b | 4740 | struct il_priv *il = context; |
e2ebc833 | 4741 | struct il_ucode_header *ucode; |
be663ab6 | 4742 | int err; |
e2ebc833 | 4743 | struct il4965_firmware_pieces pieces; |
46bc8d4b SG |
4744 | const unsigned int api_max = il->cfg->ucode_api_max; |
4745 | const unsigned int api_min = il->cfg->ucode_api_min; | |
be663ab6 WYG |
4746 | u32 api_ver; |
4747 | ||
4748 | u32 max_probe_length = 200; | |
4749 | u32 standard_phy_calibration_size = | |
e7392364 | 4750 | IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE; |
be663ab6 WYG |
4751 | |
4752 | memset(&pieces, 0, sizeof(pieces)); | |
4753 | ||
4754 | if (!ucode_raw) { | |
0c2c8852 | 4755 | if (il->fw_idx <= il->cfg->ucode_api_max) |
e7392364 SG |
4756 | IL_ERR("request for firmware file '%s' failed.\n", |
4757 | il->firmware_name); | |
be663ab6 WYG |
4758 | goto try_again; |
4759 | } | |
4760 | ||
e7392364 SG |
4761 | D_INFO("Loaded firmware file '%s' (%zd bytes).\n", il->firmware_name, |
4762 | ucode_raw->size); | |
be663ab6 WYG |
4763 | |
4764 | /* Make sure that we got at least the API version number */ | |
4765 | if (ucode_raw->size < 4) { | |
9406f797 | 4766 | IL_ERR("File size way too small!\n"); |
be663ab6 WYG |
4767 | goto try_again; |
4768 | } | |
4769 | ||
4770 | /* Data from ucode file: header followed by uCode images */ | |
e2ebc833 | 4771 | ucode = (struct il_ucode_header *)ucode_raw->data; |
be663ab6 | 4772 | |
46bc8d4b | 4773 | err = il4965_load_firmware(il, ucode_raw, &pieces); |
be663ab6 WYG |
4774 | |
4775 | if (err) | |
4776 | goto try_again; | |
4777 | ||
46bc8d4b | 4778 | api_ver = IL_UCODE_API(il->ucode_ver); |
be663ab6 WYG |
4779 | |
4780 | /* | |
4781 | * api_ver should match the api version forming part of the | |
4782 | * firmware filename ... but we don't check for that and only rely | |
4783 | * on the API version read from firmware header from here on forward | |
4784 | */ | |
4785 | if (api_ver < api_min || api_ver > api_max) { | |
e7392364 SG |
4786 | IL_ERR("Driver unable to support your firmware API. " |
4787 | "Driver supports v%u, firmware is v%u.\n", api_max, | |
4788 | api_ver); | |
be663ab6 WYG |
4789 | goto try_again; |
4790 | } | |
4791 | ||
4792 | if (api_ver != api_max) | |
e7392364 SG |
4793 | IL_ERR("Firmware has old API version. Expected v%u, " |
4794 | "got v%u. New firmware can be obtained " | |
4795 | "from http://www.intellinuxwireless.org.\n", api_max, | |
4796 | api_ver); | |
be663ab6 | 4797 | |
9406f797 | 4798 | IL_INFO("loaded firmware version %u.%u.%u.%u\n", |
e7392364 SG |
4799 | IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver), |
4800 | IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver)); | |
be663ab6 | 4801 | |
e7392364 SG |
4802 | snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version), |
4803 | "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver), | |
4804 | IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver), | |
46bc8d4b | 4805 | IL_UCODE_SERIAL(il->ucode_ver)); |
be663ab6 WYG |
4806 | |
4807 | /* | |
4808 | * For any of the failures below (before allocating pci memory) | |
4809 | * we will try to load a version with a smaller API -- maybe the | |
4810 | * user just got a corrupted version of the latest API. | |
4811 | */ | |
4812 | ||
e7392364 SG |
4813 | D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver); |
4814 | D_INFO("f/w package hdr runtime inst size = %Zd\n", pieces.inst_size); | |
4815 | D_INFO("f/w package hdr runtime data size = %Zd\n", pieces.data_size); | |
4816 | D_INFO("f/w package hdr init inst size = %Zd\n", pieces.init_size); | |
4817 | D_INFO("f/w package hdr init data size = %Zd\n", pieces.init_data_size); | |
4818 | D_INFO("f/w package hdr boot inst size = %Zd\n", pieces.boot_size); | |
be663ab6 WYG |
4819 | |
4820 | /* Verify that uCode images will fit in card's SRAM */ | |
46bc8d4b | 4821 | if (pieces.inst_size > il->hw_params.max_inst_size) { |
9406f797 | 4822 | IL_ERR("uCode instr len %Zd too large to fit in\n", |
e7392364 | 4823 | pieces.inst_size); |
be663ab6 WYG |
4824 | goto try_again; |
4825 | } | |
4826 | ||
46bc8d4b | 4827 | if (pieces.data_size > il->hw_params.max_data_size) { |
9406f797 | 4828 | IL_ERR("uCode data len %Zd too large to fit in\n", |
e7392364 | 4829 | pieces.data_size); |
be663ab6 WYG |
4830 | goto try_again; |
4831 | } | |
4832 | ||
46bc8d4b | 4833 | if (pieces.init_size > il->hw_params.max_inst_size) { |
9406f797 | 4834 | IL_ERR("uCode init instr len %Zd too large to fit in\n", |
e7392364 | 4835 | pieces.init_size); |
be663ab6 WYG |
4836 | goto try_again; |
4837 | } | |
4838 | ||
46bc8d4b | 4839 | if (pieces.init_data_size > il->hw_params.max_data_size) { |
9406f797 | 4840 | IL_ERR("uCode init data len %Zd too large to fit in\n", |
e7392364 | 4841 | pieces.init_data_size); |
be663ab6 WYG |
4842 | goto try_again; |
4843 | } | |
4844 | ||
46bc8d4b | 4845 | if (pieces.boot_size > il->hw_params.max_bsm_size) { |
9406f797 | 4846 | IL_ERR("uCode boot instr len %Zd too large to fit in\n", |
e7392364 | 4847 | pieces.boot_size); |
be663ab6 WYG |
4848 | goto try_again; |
4849 | } | |
4850 | ||
4851 | /* Allocate ucode buffers for card's bus-master loading ... */ | |
4852 | ||
4853 | /* Runtime instructions and 2 copies of data: | |
4854 | * 1) unmodified from disk | |
4855 | * 2) backup cache for save/restore during power-downs */ | |
46bc8d4b SG |
4856 | il->ucode_code.len = pieces.inst_size; |
4857 | il_alloc_fw_desc(il->pci_dev, &il->ucode_code); | |
be663ab6 | 4858 | |
46bc8d4b SG |
4859 | il->ucode_data.len = pieces.data_size; |
4860 | il_alloc_fw_desc(il->pci_dev, &il->ucode_data); | |
be663ab6 | 4861 | |
46bc8d4b SG |
4862 | il->ucode_data_backup.len = pieces.data_size; |
4863 | il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup); | |
be663ab6 | 4864 | |
46bc8d4b SG |
4865 | if (!il->ucode_code.v_addr || !il->ucode_data.v_addr || |
4866 | !il->ucode_data_backup.v_addr) | |
be663ab6 WYG |
4867 | goto err_pci_alloc; |
4868 | ||
4869 | /* Initialization instructions and data */ | |
4870 | if (pieces.init_size && pieces.init_data_size) { | |
46bc8d4b SG |
4871 | il->ucode_init.len = pieces.init_size; |
4872 | il_alloc_fw_desc(il->pci_dev, &il->ucode_init); | |
be663ab6 | 4873 | |
46bc8d4b SG |
4874 | il->ucode_init_data.len = pieces.init_data_size; |
4875 | il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data); | |
be663ab6 | 4876 | |
46bc8d4b | 4877 | if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr) |
be663ab6 WYG |
4878 | goto err_pci_alloc; |
4879 | } | |
4880 | ||
4881 | /* Bootstrap (instructions only, no data) */ | |
4882 | if (pieces.boot_size) { | |
46bc8d4b SG |
4883 | il->ucode_boot.len = pieces.boot_size; |
4884 | il_alloc_fw_desc(il->pci_dev, &il->ucode_boot); | |
be663ab6 | 4885 | |
46bc8d4b | 4886 | if (!il->ucode_boot.v_addr) |
be663ab6 WYG |
4887 | goto err_pci_alloc; |
4888 | } | |
4889 | ||
4890 | /* Now that we can no longer fail, copy information */ | |
4891 | ||
46bc8d4b | 4892 | il->sta_key_max_num = STA_KEY_MAX_NUM; |
be663ab6 WYG |
4893 | |
4894 | /* Copy images into buffers for card's bus-master reads ... */ | |
4895 | ||
4896 | /* Runtime instructions (first block of data in file) */ | |
58de00a4 | 4897 | D_INFO("Copying (but not loading) uCode instr len %Zd\n", |
e7392364 | 4898 | pieces.inst_size); |
46bc8d4b | 4899 | memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size); |
be663ab6 | 4900 | |
58de00a4 | 4901 | D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", |
e7392364 | 4902 | il->ucode_code.v_addr, (u32) il->ucode_code.p_addr); |
be663ab6 WYG |
4903 | |
4904 | /* | |
4905 | * Runtime data | |
e2ebc833 | 4906 | * NOTE: Copy into backup buffer will be done in il_up() |
be663ab6 | 4907 | */ |
58de00a4 | 4908 | D_INFO("Copying (but not loading) uCode data len %Zd\n", |
e7392364 | 4909 | pieces.data_size); |
46bc8d4b SG |
4910 | memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size); |
4911 | memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size); | |
be663ab6 WYG |
4912 | |
4913 | /* Initialization instructions */ | |
4914 | if (pieces.init_size) { | |
e7392364 SG |
4915 | D_INFO("Copying (but not loading) init instr len %Zd\n", |
4916 | pieces.init_size); | |
46bc8d4b | 4917 | memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size); |
be663ab6 WYG |
4918 | } |
4919 | ||
4920 | /* Initialization data */ | |
4921 | if (pieces.init_data_size) { | |
e7392364 SG |
4922 | D_INFO("Copying (but not loading) init data len %Zd\n", |
4923 | pieces.init_data_size); | |
46bc8d4b | 4924 | memcpy(il->ucode_init_data.v_addr, pieces.init_data, |
be663ab6 WYG |
4925 | pieces.init_data_size); |
4926 | } | |
4927 | ||
4928 | /* Bootstrap instructions */ | |
58de00a4 | 4929 | D_INFO("Copying (but not loading) boot instr len %Zd\n", |
e7392364 | 4930 | pieces.boot_size); |
46bc8d4b | 4931 | memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size); |
be663ab6 WYG |
4932 | |
4933 | /* | |
4934 | * figure out the offset of chain noise reset and gain commands | |
4935 | * base on the size of standard phy calibration commands table size | |
4936 | */ | |
46bc8d4b | 4937 | il->_4965.phy_calib_chain_noise_reset_cmd = |
e7392364 | 4938 | standard_phy_calibration_size; |
46bc8d4b | 4939 | il->_4965.phy_calib_chain_noise_gain_cmd = |
e7392364 | 4940 | standard_phy_calibration_size + 1; |
be663ab6 WYG |
4941 | |
4942 | /************************************************** | |
4943 | * This is still part of probe() in a sense... | |
4944 | * | |
4945 | * 9. Setup and register with mac80211 and debugfs | |
4946 | **************************************************/ | |
46bc8d4b | 4947 | err = il4965_mac_setup_register(il, max_probe_length); |
be663ab6 WYG |
4948 | if (err) |
4949 | goto out_unbind; | |
4950 | ||
46bc8d4b | 4951 | err = il_dbgfs_register(il, DRV_NAME); |
be663ab6 | 4952 | if (err) |
e7392364 SG |
4953 | IL_ERR("failed to create debugfs files. Ignoring error: %d\n", |
4954 | err); | |
be663ab6 | 4955 | |
e7392364 | 4956 | err = sysfs_create_group(&il->pci_dev->dev.kobj, &il_attribute_group); |
be663ab6 | 4957 | if (err) { |
9406f797 | 4958 | IL_ERR("failed to create sysfs device attributes\n"); |
be663ab6 WYG |
4959 | goto out_unbind; |
4960 | } | |
4961 | ||
4962 | /* We have our copies now, allow OS release its copies */ | |
4963 | release_firmware(ucode_raw); | |
46bc8d4b | 4964 | complete(&il->_4965.firmware_loading_complete); |
be663ab6 WYG |
4965 | return; |
4966 | ||
e7392364 | 4967 | try_again: |
be663ab6 | 4968 | /* try next, if any */ |
46bc8d4b | 4969 | if (il4965_request_firmware(il, false)) |
be663ab6 WYG |
4970 | goto out_unbind; |
4971 | release_firmware(ucode_raw); | |
4972 | return; | |
4973 | ||
e7392364 | 4974 | err_pci_alloc: |
9406f797 | 4975 | IL_ERR("failed to allocate pci memory\n"); |
46bc8d4b | 4976 | il4965_dealloc_ucode_pci(il); |
e7392364 | 4977 | out_unbind: |
46bc8d4b SG |
4978 | complete(&il->_4965.firmware_loading_complete); |
4979 | device_release_driver(&il->pci_dev->dev); | |
be663ab6 WYG |
4980 | release_firmware(ucode_raw); |
4981 | } | |
4982 | ||
e7392364 | 4983 | static const char *const desc_lookup_text[] = { |
be663ab6 WYG |
4984 | "OK", |
4985 | "FAIL", | |
4986 | "BAD_PARAM", | |
4987 | "BAD_CHECKSUM", | |
4988 | "NMI_INTERRUPT_WDG", | |
4989 | "SYSASSERT", | |
4990 | "FATAL_ERROR", | |
4991 | "BAD_COMMAND", | |
4992 | "HW_ERROR_TUNE_LOCK", | |
4993 | "HW_ERROR_TEMPERATURE", | |
4994 | "ILLEGAL_CHAN_FREQ", | |
3b98c7f4 | 4995 | "VCC_NOT_STBL", |
9a95b370 | 4996 | "FH49_ERROR", |
be663ab6 WYG |
4997 | "NMI_INTERRUPT_HOST", |
4998 | "NMI_INTERRUPT_ACTION_PT", | |
4999 | "NMI_INTERRUPT_UNKNOWN", | |
5000 | "UCODE_VERSION_MISMATCH", | |
5001 | "HW_ERROR_ABS_LOCK", | |
5002 | "HW_ERROR_CAL_LOCK_FAIL", | |
5003 | "NMI_INTERRUPT_INST_ACTION_PT", | |
5004 | "NMI_INTERRUPT_DATA_ACTION_PT", | |
5005 | "NMI_TRM_HW_ER", | |
5006 | "NMI_INTERRUPT_TRM", | |
861d9c3f | 5007 | "NMI_INTERRUPT_BREAK_POINT", |
be663ab6 WYG |
5008 | "DEBUG_0", |
5009 | "DEBUG_1", | |
5010 | "DEBUG_2", | |
5011 | "DEBUG_3", | |
5012 | }; | |
5013 | ||
e7392364 SG |
5014 | static struct { |
5015 | char *name; | |
5016 | u8 num; | |
5017 | } advanced_lookup[] = { | |
5018 | { | |
5019 | "NMI_INTERRUPT_WDG", 0x34}, { | |
5020 | "SYSASSERT", 0x35}, { | |
5021 | "UCODE_VERSION_MISMATCH", 0x37}, { | |
5022 | "BAD_COMMAND", 0x38}, { | |
5023 | "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, { | |
5024 | "FATAL_ERROR", 0x3D}, { | |
5025 | "NMI_TRM_HW_ERR", 0x46}, { | |
5026 | "NMI_INTERRUPT_TRM", 0x4C}, { | |
5027 | "NMI_INTERRUPT_BREAK_POINT", 0x54}, { | |
5028 | "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, { | |
5029 | "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, { | |
5030 | "NMI_INTERRUPT_HOST", 0x66}, { | |
5031 | "NMI_INTERRUPT_ACTION_PT", 0x7C}, { | |
5032 | "NMI_INTERRUPT_UNKNOWN", 0x84}, { | |
5033 | "NMI_INTERRUPT_INST_ACTION_PT", 0x86}, { | |
5034 | "ADVANCED_SYSASSERT", 0},}; | |
5035 | ||
5036 | static const char * | |
5037 | il4965_desc_lookup(u32 num) | |
be663ab6 WYG |
5038 | { |
5039 | int i; | |
5040 | int max = ARRAY_SIZE(desc_lookup_text); | |
5041 | ||
5042 | if (num < max) | |
5043 | return desc_lookup_text[num]; | |
5044 | ||
5045 | max = ARRAY_SIZE(advanced_lookup) - 1; | |
5046 | for (i = 0; i < max; i++) { | |
5047 | if (advanced_lookup[i].num == num) | |
5048 | break; | |
5049 | } | |
5050 | return advanced_lookup[i].name; | |
5051 | } | |
5052 | ||
5053 | #define ERROR_START_OFFSET (1 * sizeof(u32)) | |
5054 | #define ERROR_ELEM_SIZE (7 * sizeof(u32)) | |
5055 | ||
e7392364 SG |
5056 | void |
5057 | il4965_dump_nic_error_log(struct il_priv *il) | |
be663ab6 WYG |
5058 | { |
5059 | u32 data2, line; | |
5060 | u32 desc, time, count, base, data1; | |
5061 | u32 blink1, blink2, ilink1, ilink2; | |
5062 | u32 pc, hcmd; | |
5063 | ||
1722f8e1 | 5064 | if (il->ucode_type == UCODE_INIT) |
46bc8d4b | 5065 | base = le32_to_cpu(il->card_alive_init.error_event_table_ptr); |
1722f8e1 | 5066 | else |
46bc8d4b | 5067 | base = le32_to_cpu(il->card_alive.error_event_table_ptr); |
be663ab6 | 5068 | |
1600b875 | 5069 | if (!il->ops->is_valid_rtc_data_addr(base)) { |
e7392364 SG |
5070 | IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n", |
5071 | base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT"); | |
be663ab6 WYG |
5072 | return; |
5073 | } | |
5074 | ||
46bc8d4b | 5075 | count = il_read_targ_mem(il, base); |
be663ab6 WYG |
5076 | |
5077 | if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { | |
9406f797 | 5078 | IL_ERR("Start IWL Error Log Dump:\n"); |
e7392364 | 5079 | IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count); |
46bc8d4b SG |
5080 | } |
5081 | ||
5082 | desc = il_read_targ_mem(il, base + 1 * sizeof(u32)); | |
5083 | il->isr_stats.err_code = desc; | |
5084 | pc = il_read_targ_mem(il, base + 2 * sizeof(u32)); | |
5085 | blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32)); | |
5086 | blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32)); | |
5087 | ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32)); | |
5088 | ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32)); | |
5089 | data1 = il_read_targ_mem(il, base + 7 * sizeof(u32)); | |
5090 | data2 = il_read_targ_mem(il, base + 8 * sizeof(u32)); | |
5091 | line = il_read_targ_mem(il, base + 9 * sizeof(u32)); | |
5092 | time = il_read_targ_mem(il, base + 11 * sizeof(u32)); | |
5093 | hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32)); | |
5094 | ||
9406f797 | 5095 | IL_ERR("Desc Time " |
e7392364 | 5096 | "data1 data2 line\n"); |
9406f797 | 5097 | IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n", |
e7392364 | 5098 | il4965_desc_lookup(desc), desc, time, data1, data2, line); |
9406f797 | 5099 | IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n"); |
e7392364 SG |
5100 | IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1, |
5101 | blink2, ilink1, ilink2, hcmd); | |
be663ab6 WYG |
5102 | } |
5103 | ||
e7392364 SG |
5104 | static void |
5105 | il4965_rf_kill_ct_config(struct il_priv *il) | |
be663ab6 | 5106 | { |
e2ebc833 | 5107 | struct il_ct_kill_config cmd; |
be663ab6 WYG |
5108 | unsigned long flags; |
5109 | int ret = 0; | |
5110 | ||
46bc8d4b | 5111 | spin_lock_irqsave(&il->lock, flags); |
841b2cca | 5112 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, |
e7392364 | 5113 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); |
46bc8d4b | 5114 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 WYG |
5115 | |
5116 | cmd.critical_temperature_R = | |
e7392364 | 5117 | cpu_to_le32(il->hw_params.ct_kill_threshold); |
be663ab6 | 5118 | |
e7392364 | 5119 | ret = il_send_cmd_pdu(il, C_CT_KILL_CONFIG, sizeof(cmd), &cmd); |
be663ab6 | 5120 | if (ret) |
4d69c752 | 5121 | IL_ERR("C_CT_KILL_CONFIG failed\n"); |
be663ab6 | 5122 | else |
e7392364 SG |
5123 | D_INFO("C_CT_KILL_CONFIG " "succeeded, " |
5124 | "critical temperature is %d\n", | |
5125 | il->hw_params.ct_kill_threshold); | |
be663ab6 WYG |
5126 | } |
5127 | ||
5128 | static const s8 default_queue_to_tx_fifo[] = { | |
e2ebc833 SG |
5129 | IL_TX_FIFO_VO, |
5130 | IL_TX_FIFO_VI, | |
5131 | IL_TX_FIFO_BE, | |
5132 | IL_TX_FIFO_BK, | |
d3175167 | 5133 | IL49_CMD_FIFO_NUM, |
e2ebc833 SG |
5134 | IL_TX_FIFO_UNUSED, |
5135 | IL_TX_FIFO_UNUSED, | |
be663ab6 WYG |
5136 | }; |
5137 | ||
e53aac42 SG |
5138 | #define IL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) |
5139 | ||
e7392364 SG |
5140 | static int |
5141 | il4965_alive_notify(struct il_priv *il) | |
be663ab6 WYG |
5142 | { |
5143 | u32 a; | |
5144 | unsigned long flags; | |
5145 | int i, chan; | |
5146 | u32 reg_val; | |
5147 | ||
46bc8d4b | 5148 | spin_lock_irqsave(&il->lock, flags); |
be663ab6 WYG |
5149 | |
5150 | /* Clear 4965's internal Tx Scheduler data base */ | |
e7392364 | 5151 | il->scd_base_addr = il_rd_prph(il, IL49_SCD_SRAM_BASE_ADDR); |
d3175167 SG |
5152 | a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET; |
5153 | for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4) | |
46bc8d4b | 5154 | il_write_targ_mem(il, a, 0); |
d3175167 | 5155 | for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4) |
46bc8d4b | 5156 | il_write_targ_mem(il, a, 0); |
e7392364 SG |
5157 | for (; |
5158 | a < | |
5159 | il->scd_base_addr + | |
5160 | IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num); | |
5161 | a += 4) | |
46bc8d4b | 5162 | il_write_targ_mem(il, a, 0); |
be663ab6 WYG |
5163 | |
5164 | /* Tel 4965 where to find Tx byte count tables */ | |
e7392364 | 5165 | il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, il->scd_bc_tbls.dma >> 10); |
be663ab6 WYG |
5166 | |
5167 | /* Enable DMA channel */ | |
e7392364 SG |
5168 | for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++) |
5169 | il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan), | |
5170 | FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
5171 | FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
be663ab6 WYG |
5172 | |
5173 | /* Update FH chicken bits */ | |
9a95b370 SG |
5174 | reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG); |
5175 | il_wr(il, FH49_TX_CHICKEN_BITS_REG, | |
e7392364 | 5176 | reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); |
be663ab6 WYG |
5177 | |
5178 | /* Disable chain mode for all queues */ | |
d3175167 | 5179 | il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0); |
be663ab6 WYG |
5180 | |
5181 | /* Initialize each Tx queue (including the command queue) */ | |
46bc8d4b | 5182 | for (i = 0; i < il->hw_params.max_txq_num; i++) { |
be663ab6 | 5183 | |
0c2c8852 | 5184 | /* TFD circular buffer read/write idxes */ |
d3175167 | 5185 | il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0); |
0c1a94e2 | 5186 | il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8)); |
be663ab6 WYG |
5187 | |
5188 | /* Max Tx Window size for Scheduler-ACK mode */ | |
e7392364 SG |
5189 | il_write_targ_mem(il, |
5190 | il->scd_base_addr + | |
5191 | IL49_SCD_CONTEXT_QUEUE_OFFSET(i), | |
5192 | (SCD_WIN_SIZE << | |
5193 | IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & | |
5194 | IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); | |
be663ab6 WYG |
5195 | |
5196 | /* Frame limit */ | |
e7392364 SG |
5197 | il_write_targ_mem(il, |
5198 | il->scd_base_addr + | |
5199 | IL49_SCD_CONTEXT_QUEUE_OFFSET(i) + | |
5200 | sizeof(u32), | |
5201 | (SCD_FRAME_LIMIT << | |
5202 | IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
5203 | IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); | |
be663ab6 WYG |
5204 | |
5205 | } | |
d3175167 | 5206 | il_wr_prph(il, IL49_SCD_INTERRUPT_MASK, |
e7392364 | 5207 | (1 << il->hw_params.max_txq_num) - 1); |
be663ab6 WYG |
5208 | |
5209 | /* Activate all Tx DMA/FIFO channels */ | |
46bc8d4b | 5210 | il4965_txq_set_sched(il, IL_MASK(0, 6)); |
be663ab6 | 5211 | |
46bc8d4b | 5212 | il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0); |
be663ab6 WYG |
5213 | |
5214 | /* make sure all queue are not stopped */ | |
46bc8d4b | 5215 | memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped)); |
be663ab6 | 5216 | for (i = 0; i < 4; i++) |
46bc8d4b | 5217 | atomic_set(&il->queue_stop_count[i], 0); |
be663ab6 WYG |
5218 | |
5219 | /* reset to 0 to enable all the queue first */ | |
46bc8d4b | 5220 | il->txq_ctx_active_msk = 0; |
be663ab6 WYG |
5221 | /* Map each Tx/cmd queue to its corresponding fifo */ |
5222 | BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7); | |
5223 | ||
5224 | for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) { | |
5225 | int ac = default_queue_to_tx_fifo[i]; | |
5226 | ||
46bc8d4b | 5227 | il_txq_ctx_activate(il, i); |
be663ab6 | 5228 | |
e2ebc833 | 5229 | if (ac == IL_TX_FIFO_UNUSED) |
be663ab6 WYG |
5230 | continue; |
5231 | ||
46bc8d4b | 5232 | il4965_tx_queue_set_status(il, &il->txq[i], ac, 0); |
be663ab6 WYG |
5233 | } |
5234 | ||
46bc8d4b | 5235 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 WYG |
5236 | |
5237 | return 0; | |
5238 | } | |
5239 | ||
5240 | /** | |
4d69c752 | 5241 | * il4965_alive_start - called after N_ALIVE notification received |
be663ab6 | 5242 | * from protocol/runtime uCode (initialization uCode's |
e2ebc833 | 5243 | * Alive gets handled by il_init_alive_start()). |
be663ab6 | 5244 | */ |
e7392364 SG |
5245 | static void |
5246 | il4965_alive_start(struct il_priv *il) | |
be663ab6 WYG |
5247 | { |
5248 | int ret = 0; | |
be663ab6 | 5249 | |
58de00a4 | 5250 | D_INFO("Runtime Alive received.\n"); |
be663ab6 | 5251 | |
46bc8d4b | 5252 | if (il->card_alive.is_valid != UCODE_VALID_OK) { |
be663ab6 WYG |
5253 | /* We had an error bringing up the hardware, so take it |
5254 | * all the way back down so we can try again */ | |
58de00a4 | 5255 | D_INFO("Alive failed.\n"); |
be663ab6 WYG |
5256 | goto restart; |
5257 | } | |
5258 | ||
5259 | /* Initialize uCode has loaded Runtime uCode ... verify inst image. | |
5260 | * This is a paranoid check, because we would not have gotten the | |
5261 | * "runtime" alive if code weren't properly loaded. */ | |
46bc8d4b | 5262 | if (il4965_verify_ucode(il)) { |
be663ab6 WYG |
5263 | /* Runtime instruction load was bad; |
5264 | * take it all the way back down so we can try again */ | |
58de00a4 | 5265 | D_INFO("Bad runtime uCode load.\n"); |
be663ab6 WYG |
5266 | goto restart; |
5267 | } | |
5268 | ||
46bc8d4b | 5269 | ret = il4965_alive_notify(il); |
be663ab6 | 5270 | if (ret) { |
e7392364 | 5271 | IL_WARN("Could not complete ALIVE transition [ntf]: %d\n", ret); |
be663ab6 WYG |
5272 | goto restart; |
5273 | } | |
5274 | ||
be663ab6 | 5275 | /* After the ALIVE response, we can send host commands to the uCode */ |
a6766ccd | 5276 | set_bit(S_ALIVE, &il->status); |
be663ab6 WYG |
5277 | |
5278 | /* Enable watchdog to monitor the driver tx queues */ | |
46bc8d4b | 5279 | il_setup_watchdog(il); |
be663ab6 | 5280 | |
46bc8d4b | 5281 | if (il_is_rfkill(il)) |
be663ab6 WYG |
5282 | return; |
5283 | ||
46bc8d4b | 5284 | ieee80211_wake_queues(il->hw); |
be663ab6 | 5285 | |
2eb05816 | 5286 | il->active_rate = RATES_MASK; |
be663ab6 | 5287 | |
c8b03958 | 5288 | if (il_is_associated(il)) { |
e2ebc833 | 5289 | struct il_rxon_cmd *active_rxon = |
c8b03958 | 5290 | (struct il_rxon_cmd *)&il->active; |
be663ab6 | 5291 | /* apply any changes in staging */ |
c8b03958 | 5292 | il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; |
be663ab6 WYG |
5293 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
5294 | } else { | |
be663ab6 | 5295 | /* Initialize our rx_config data */ |
83007196 | 5296 | il_connection_init_rx_config(il); |
be663ab6 | 5297 | |
c9363551 SG |
5298 | if (il->ops->set_rxon_chain) |
5299 | il->ops->set_rxon_chain(il); | |
be663ab6 WYG |
5300 | } |
5301 | ||
5302 | /* Configure bluetooth coexistence if enabled */ | |
46bc8d4b | 5303 | il_send_bt_config(il); |
be663ab6 | 5304 | |
46bc8d4b | 5305 | il4965_reset_run_time_calib(il); |
be663ab6 | 5306 | |
a6766ccd | 5307 | set_bit(S_READY, &il->status); |
be663ab6 WYG |
5308 | |
5309 | /* Configure the adapter for unassociated operation */ | |
83007196 | 5310 | il_commit_rxon(il); |
be663ab6 WYG |
5311 | |
5312 | /* At this point, the NIC is initialized and operational */ | |
46bc8d4b | 5313 | il4965_rf_kill_ct_config(il); |
be663ab6 | 5314 | |
58de00a4 | 5315 | D_INFO("ALIVE processing complete.\n"); |
46bc8d4b | 5316 | wake_up(&il->wait_command_queue); |
be663ab6 | 5317 | |
46bc8d4b | 5318 | il_power_update_mode(il, true); |
58de00a4 | 5319 | D_INFO("Updated power mode\n"); |
be663ab6 WYG |
5320 | |
5321 | return; | |
5322 | ||
e7392364 | 5323 | restart: |
46bc8d4b | 5324 | queue_work(il->workqueue, &il->restart); |
be663ab6 WYG |
5325 | } |
5326 | ||
46bc8d4b | 5327 | static void il4965_cancel_deferred_work(struct il_priv *il); |
be663ab6 | 5328 | |
e7392364 SG |
5329 | static void |
5330 | __il4965_down(struct il_priv *il) | |
be663ab6 WYG |
5331 | { |
5332 | unsigned long flags; | |
ab42b404 | 5333 | int exit_pending; |
be663ab6 | 5334 | |
58de00a4 | 5335 | D_INFO(DRV_NAME " is going down\n"); |
be663ab6 | 5336 | |
46bc8d4b | 5337 | il_scan_cancel_timeout(il, 200); |
be663ab6 | 5338 | |
a6766ccd | 5339 | exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status); |
be663ab6 | 5340 | |
a6766ccd | 5341 | /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set |
be663ab6 | 5342 | * to prevent rearm timer */ |
46bc8d4b | 5343 | del_timer_sync(&il->watchdog); |
be663ab6 | 5344 | |
83007196 | 5345 | il_clear_ucode_stations(il); |
d735f921 SG |
5346 | |
5347 | /* FIXME: race conditions ? */ | |
5348 | spin_lock_irq(&il->sta_lock); | |
5349 | /* | |
5350 | * Remove all key information that is not stored as part | |
5351 | * of station information since mac80211 may not have had | |
5352 | * a chance to remove all the keys. When device is | |
5353 | * reconfigured by mac80211 after an error all keys will | |
5354 | * be reconfigured. | |
5355 | */ | |
5356 | memset(il->_4965.wep_keys, 0, sizeof(il->_4965.wep_keys)); | |
5357 | il->_4965.key_mapping_keys = 0; | |
5358 | spin_unlock_irq(&il->sta_lock); | |
5359 | ||
46bc8d4b SG |
5360 | il_dealloc_bcast_stations(il); |
5361 | il_clear_driver_stations(il); | |
be663ab6 WYG |
5362 | |
5363 | /* Unblock any waiting calls */ | |
46bc8d4b | 5364 | wake_up_all(&il->wait_command_queue); |
be663ab6 WYG |
5365 | |
5366 | /* Wipe out the EXIT_PENDING status bit if we are not actually | |
5367 | * exiting the module */ | |
5368 | if (!exit_pending) | |
a6766ccd | 5369 | clear_bit(S_EXIT_PENDING, &il->status); |
be663ab6 WYG |
5370 | |
5371 | /* stop and reset the on-board processor */ | |
841b2cca | 5372 | _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
be663ab6 WYG |
5373 | |
5374 | /* tell the device to stop sending interrupts */ | |
46bc8d4b SG |
5375 | spin_lock_irqsave(&il->lock, flags); |
5376 | il_disable_interrupts(il); | |
5377 | spin_unlock_irqrestore(&il->lock, flags); | |
5378 | il4965_synchronize_irq(il); | |
be663ab6 | 5379 | |
46bc8d4b SG |
5380 | if (il->mac80211_registered) |
5381 | ieee80211_stop_queues(il->hw); | |
be663ab6 | 5382 | |
e2ebc833 | 5383 | /* If we have not previously called il_init() then |
be663ab6 | 5384 | * clear all bits but the RF Kill bit and return */ |
46bc8d4b | 5385 | if (!il_is_init(il)) { |
e7392364 | 5386 | il->status = |
bc269a8e | 5387 | test_bit(S_RFKILL, &il->status) << S_RFKILL | |
c37281a0 | 5388 | test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED | |
e7392364 | 5389 | test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING; |
be663ab6 WYG |
5390 | goto exit; |
5391 | } | |
5392 | ||
5393 | /* ...otherwise clear out all the status bits but the RF Kill | |
5394 | * bit and continue taking the NIC down. */ | |
e7392364 | 5395 | il->status &= |
bc269a8e | 5396 | test_bit(S_RFKILL, &il->status) << S_RFKILL | |
c37281a0 SG |
5397 | test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED | |
5398 | test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR | | |
e7392364 | 5399 | test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING; |
be663ab6 | 5400 | |
775ed8ab SG |
5401 | /* |
5402 | * We disabled and synchronized interrupt, and priv->mutex is taken, so | |
5403 | * here is the only thread which will program device registers, but | |
5404 | * still have lockdep assertions, so we are taking reg_lock. | |
5405 | */ | |
5406 | spin_lock_irq(&il->reg_lock); | |
5407 | /* FIXME: il_grab_nic_access if rfkill is off ? */ | |
5408 | ||
46bc8d4b SG |
5409 | il4965_txq_ctx_stop(il); |
5410 | il4965_rxq_stop(il); | |
be663ab6 | 5411 | /* Power-down device's busmaster DMA clocks */ |
775ed8ab | 5412 | _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); |
be663ab6 | 5413 | udelay(5); |
be663ab6 | 5414 | /* Make sure (redundant) we've released our request to stay awake */ |
775ed8ab | 5415 | _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
be663ab6 | 5416 | /* Stop the device, and put it in low power state */ |
775ed8ab SG |
5417 | _il_apm_stop(il); |
5418 | ||
5419 | spin_unlock_irq(&il->reg_lock); | |
be663ab6 | 5420 | |
775ed8ab | 5421 | il4965_txq_ctx_unmap(il); |
e7392364 | 5422 | exit: |
46bc8d4b | 5423 | memset(&il->card_alive, 0, sizeof(struct il_alive_resp)); |
be663ab6 | 5424 | |
46bc8d4b SG |
5425 | dev_kfree_skb(il->beacon_skb); |
5426 | il->beacon_skb = NULL; | |
be663ab6 WYG |
5427 | |
5428 | /* clear out any free frames */ | |
46bc8d4b | 5429 | il4965_clear_free_frames(il); |
be663ab6 WYG |
5430 | } |
5431 | ||
e7392364 SG |
5432 | static void |
5433 | il4965_down(struct il_priv *il) | |
be663ab6 | 5434 | { |
46bc8d4b SG |
5435 | mutex_lock(&il->mutex); |
5436 | __il4965_down(il); | |
5437 | mutex_unlock(&il->mutex); | |
be663ab6 | 5438 | |
46bc8d4b | 5439 | il4965_cancel_deferred_work(il); |
be663ab6 WYG |
5440 | } |
5441 | ||
be663ab6 | 5442 | |
71e0c6c2 | 5443 | static void |
e7392364 | 5444 | il4965_set_hw_ready(struct il_priv *il) |
be663ab6 | 5445 | { |
71e0c6c2 | 5446 | int ret; |
be663ab6 | 5447 | |
46bc8d4b | 5448 | il_set_bit(il, CSR_HW_IF_CONFIG_REG, |
e7392364 | 5449 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); |
be663ab6 WYG |
5450 | |
5451 | /* See if we got it */ | |
71e0c6c2 SG |
5452 | ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG, |
5453 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
5454 | CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, | |
5455 | 100); | |
5456 | if (ret >= 0) | |
46bc8d4b | 5457 | il->hw_ready = true; |
be663ab6 | 5458 | |
71e0c6c2 | 5459 | D_INFO("hardware %s ready\n", (il->hw_ready) ? "" : "not"); |
be663ab6 WYG |
5460 | } |
5461 | ||
71e0c6c2 | 5462 | static void |
e7392364 | 5463 | il4965_prepare_card_hw(struct il_priv *il) |
be663ab6 | 5464 | { |
71e0c6c2 | 5465 | int ret; |
be663ab6 | 5466 | |
71e0c6c2 | 5467 | il->hw_ready = false; |
be663ab6 | 5468 | |
71e0c6c2 | 5469 | il4965_set_hw_ready(il); |
46bc8d4b | 5470 | if (il->hw_ready) |
71e0c6c2 | 5471 | return; |
be663ab6 WYG |
5472 | |
5473 | /* If HW is not ready, prepare the conditions to check again */ | |
e7392364 | 5474 | il_set_bit(il, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE); |
be663ab6 | 5475 | |
e7392364 SG |
5476 | ret = |
5477 | _il_poll_bit(il, CSR_HW_IF_CONFIG_REG, | |
5478 | ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, | |
5479 | CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); | |
be663ab6 WYG |
5480 | |
5481 | /* HW should be ready by now, check again. */ | |
5482 | if (ret != -ETIMEDOUT) | |
46bc8d4b | 5483 | il4965_set_hw_ready(il); |
be663ab6 WYG |
5484 | } |
5485 | ||
5486 | #define MAX_HW_RESTARTS 5 | |
5487 | ||
e7392364 SG |
5488 | static int |
5489 | __il4965_up(struct il_priv *il) | |
be663ab6 | 5490 | { |
be663ab6 WYG |
5491 | int i; |
5492 | int ret; | |
5493 | ||
a6766ccd | 5494 | if (test_bit(S_EXIT_PENDING, &il->status)) { |
9406f797 | 5495 | IL_WARN("Exit pending; will not bring the NIC up\n"); |
be663ab6 WYG |
5496 | return -EIO; |
5497 | } | |
5498 | ||
46bc8d4b | 5499 | if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) { |
9406f797 | 5500 | IL_ERR("ucode not available for device bringup\n"); |
be663ab6 WYG |
5501 | return -EIO; |
5502 | } | |
5503 | ||
83007196 | 5504 | ret = il4965_alloc_bcast_station(il); |
17d6e557 SG |
5505 | if (ret) { |
5506 | il_dealloc_bcast_stations(il); | |
5507 | return ret; | |
be663ab6 WYG |
5508 | } |
5509 | ||
46bc8d4b | 5510 | il4965_prepare_card_hw(il); |
46bc8d4b | 5511 | if (!il->hw_ready) { |
71e0c6c2 | 5512 | IL_ERR("HW not ready\n"); |
be663ab6 WYG |
5513 | return -EIO; |
5514 | } | |
5515 | ||
5516 | /* If platform's RF_KILL switch is NOT set to KILL */ | |
e7392364 | 5517 | if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
bc269a8e | 5518 | clear_bit(S_RFKILL, &il->status); |
3976b451 | 5519 | else { |
bc269a8e | 5520 | set_bit(S_RFKILL, &il->status); |
46bc8d4b | 5521 | wiphy_rfkill_set_hw_state(il->hw->wiphy, true); |
be663ab6 | 5522 | |
3976b451 | 5523 | il_enable_rfkill_int(il); |
9406f797 | 5524 | IL_WARN("Radio disabled by HW RF Kill switch\n"); |
be663ab6 WYG |
5525 | return 0; |
5526 | } | |
5527 | ||
841b2cca | 5528 | _il_wr(il, CSR_INT, 0xFFFFFFFF); |
be663ab6 | 5529 | |
e2ebc833 | 5530 | /* must be initialised before il_hw_nic_init */ |
46bc8d4b | 5531 | il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM; |
be663ab6 | 5532 | |
46bc8d4b | 5533 | ret = il4965_hw_nic_init(il); |
be663ab6 | 5534 | if (ret) { |
9406f797 | 5535 | IL_ERR("Unable to init nic\n"); |
be663ab6 WYG |
5536 | return ret; |
5537 | } | |
5538 | ||
5539 | /* make sure rfkill handshake bits are cleared */ | |
841b2cca | 5540 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
e7392364 | 5541 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
be663ab6 WYG |
5542 | |
5543 | /* clear (again), then enable host interrupts */ | |
841b2cca | 5544 | _il_wr(il, CSR_INT, 0xFFFFFFFF); |
46bc8d4b | 5545 | il_enable_interrupts(il); |
be663ab6 WYG |
5546 | |
5547 | /* really make sure rfkill handshake bits are cleared */ | |
841b2cca SG |
5548 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); |
5549 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); | |
be663ab6 WYG |
5550 | |
5551 | /* Copy original ucode data image from disk into backup cache. | |
5552 | * This will be used to initialize the on-board processor's | |
5553 | * data SRAM for a clean start when the runtime program first loads. */ | |
46bc8d4b SG |
5554 | memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr, |
5555 | il->ucode_data.len); | |
be663ab6 WYG |
5556 | |
5557 | for (i = 0; i < MAX_HW_RESTARTS; i++) { | |
5558 | ||
5559 | /* load bootstrap state machine, | |
5560 | * load bootstrap program into processor's memory, | |
5561 | * prepare to load the "initialize" uCode */ | |
1600b875 | 5562 | ret = il->ops->load_ucode(il); |
be663ab6 WYG |
5563 | |
5564 | if (ret) { | |
e7392364 | 5565 | IL_ERR("Unable to set up bootstrap uCode: %d\n", ret); |
be663ab6 WYG |
5566 | continue; |
5567 | } | |
5568 | ||
5569 | /* start card; "initialize" will load runtime ucode */ | |
46bc8d4b | 5570 | il4965_nic_start(il); |
be663ab6 | 5571 | |
58de00a4 | 5572 | D_INFO(DRV_NAME " is coming up\n"); |
be663ab6 WYG |
5573 | |
5574 | return 0; | |
5575 | } | |
5576 | ||
a6766ccd | 5577 | set_bit(S_EXIT_PENDING, &il->status); |
46bc8d4b | 5578 | __il4965_down(il); |
a6766ccd | 5579 | clear_bit(S_EXIT_PENDING, &il->status); |
be663ab6 WYG |
5580 | |
5581 | /* tried to restart and config the device for as long as our | |
5582 | * patience could withstand */ | |
9406f797 | 5583 | IL_ERR("Unable to initialize device after %d attempts.\n", i); |
be663ab6 WYG |
5584 | return -EIO; |
5585 | } | |
5586 | ||
be663ab6 WYG |
5587 | /***************************************************************************** |
5588 | * | |
5589 | * Workqueue callbacks | |
5590 | * | |
5591 | *****************************************************************************/ | |
5592 | ||
e7392364 SG |
5593 | static void |
5594 | il4965_bg_init_alive_start(struct work_struct *data) | |
be663ab6 | 5595 | { |
46bc8d4b | 5596 | struct il_priv *il = |
e2ebc833 | 5597 | container_of(data, struct il_priv, init_alive_start.work); |
be663ab6 | 5598 | |
46bc8d4b | 5599 | mutex_lock(&il->mutex); |
a6766ccd | 5600 | if (test_bit(S_EXIT_PENDING, &il->status)) |
28a6e577 | 5601 | goto out; |
be663ab6 | 5602 | |
1600b875 | 5603 | il->ops->init_alive_start(il); |
28a6e577 | 5604 | out: |
46bc8d4b | 5605 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
5606 | } |
5607 | ||
e7392364 SG |
5608 | static void |
5609 | il4965_bg_alive_start(struct work_struct *data) | |
be663ab6 | 5610 | { |
46bc8d4b | 5611 | struct il_priv *il = |
e2ebc833 | 5612 | container_of(data, struct il_priv, alive_start.work); |
be663ab6 | 5613 | |
46bc8d4b | 5614 | mutex_lock(&il->mutex); |
a6766ccd | 5615 | if (test_bit(S_EXIT_PENDING, &il->status)) |
28a6e577 | 5616 | goto out; |
be663ab6 | 5617 | |
46bc8d4b | 5618 | il4965_alive_start(il); |
28a6e577 | 5619 | out: |
46bc8d4b | 5620 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
5621 | } |
5622 | ||
e7392364 SG |
5623 | static void |
5624 | il4965_bg_run_time_calib_work(struct work_struct *work) | |
be663ab6 | 5625 | { |
46bc8d4b | 5626 | struct il_priv *il = container_of(work, struct il_priv, |
e7392364 | 5627 | run_time_calib_work); |
be663ab6 | 5628 | |
46bc8d4b | 5629 | mutex_lock(&il->mutex); |
be663ab6 | 5630 | |
a6766ccd SG |
5631 | if (test_bit(S_EXIT_PENDING, &il->status) || |
5632 | test_bit(S_SCANNING, &il->status)) { | |
46bc8d4b | 5633 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
5634 | return; |
5635 | } | |
5636 | ||
46bc8d4b | 5637 | if (il->start_calib) { |
e7392364 SG |
5638 | il4965_chain_noise_calibration(il, (void *)&il->_4965.stats); |
5639 | il4965_sensitivity_calibration(il, (void *)&il->_4965.stats); | |
be663ab6 WYG |
5640 | } |
5641 | ||
46bc8d4b | 5642 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
5643 | } |
5644 | ||
e7392364 SG |
5645 | static void |
5646 | il4965_bg_restart(struct work_struct *data) | |
be663ab6 | 5647 | { |
46bc8d4b | 5648 | struct il_priv *il = container_of(data, struct il_priv, restart); |
be663ab6 | 5649 | |
a6766ccd | 5650 | if (test_bit(S_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
5651 | return; |
5652 | ||
a6766ccd | 5653 | if (test_and_clear_bit(S_FW_ERROR, &il->status)) { |
46bc8d4b | 5654 | mutex_lock(&il->mutex); |
46bc8d4b | 5655 | il->is_open = 0; |
be663ab6 | 5656 | |
46bc8d4b | 5657 | __il4965_down(il); |
be663ab6 | 5658 | |
46bc8d4b SG |
5659 | mutex_unlock(&il->mutex); |
5660 | il4965_cancel_deferred_work(il); | |
5661 | ieee80211_restart_hw(il->hw); | |
be663ab6 | 5662 | } else { |
46bc8d4b | 5663 | il4965_down(il); |
be663ab6 | 5664 | |
46bc8d4b | 5665 | mutex_lock(&il->mutex); |
a6766ccd | 5666 | if (test_bit(S_EXIT_PENDING, &il->status)) { |
46bc8d4b | 5667 | mutex_unlock(&il->mutex); |
be663ab6 | 5668 | return; |
28a6e577 | 5669 | } |
be663ab6 | 5670 | |
46bc8d4b SG |
5671 | __il4965_up(il); |
5672 | mutex_unlock(&il->mutex); | |
be663ab6 WYG |
5673 | } |
5674 | } | |
5675 | ||
e7392364 SG |
5676 | static void |
5677 | il4965_bg_rx_replenish(struct work_struct *data) | |
be663ab6 | 5678 | { |
e7392364 | 5679 | struct il_priv *il = container_of(data, struct il_priv, rx_replenish); |
be663ab6 | 5680 | |
a6766ccd | 5681 | if (test_bit(S_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
5682 | return; |
5683 | ||
46bc8d4b SG |
5684 | mutex_lock(&il->mutex); |
5685 | il4965_rx_replenish(il); | |
5686 | mutex_unlock(&il->mutex); | |
be663ab6 WYG |
5687 | } |
5688 | ||
5689 | /***************************************************************************** | |
5690 | * | |
5691 | * mac80211 entry point functions | |
5692 | * | |
5693 | *****************************************************************************/ | |
5694 | ||
5695 | #define UCODE_READY_TIMEOUT (4 * HZ) | |
5696 | ||
5697 | /* | |
5698 | * Not a mac80211 entry point function, but it fits in with all the | |
5699 | * other mac80211 functions grouped here. | |
5700 | */ | |
e7392364 SG |
5701 | static int |
5702 | il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length) | |
be663ab6 WYG |
5703 | { |
5704 | int ret; | |
46bc8d4b | 5705 | struct ieee80211_hw *hw = il->hw; |
be663ab6 WYG |
5706 | |
5707 | hw->rate_control_algorithm = "iwl-4965-rs"; | |
5708 | ||
5709 | /* Tell mac80211 our characteristics */ | |
e7392364 SG |
5710 | hw->flags = |
5711 | IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_AMPDU_AGGREGATION | | |
5712 | IEEE80211_HW_NEED_DTIM_PERIOD | IEEE80211_HW_SPECTRUM_MGMT | | |
5713 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; | |
be663ab6 | 5714 | |
46bc8d4b | 5715 | if (il->cfg->sku & IL_SKU_N) |
e7392364 SG |
5716 | hw->flags |= |
5717 | IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS | | |
5718 | IEEE80211_HW_SUPPORTS_STATIC_SMPS; | |
be663ab6 | 5719 | |
e2ebc833 SG |
5720 | hw->sta_data_size = sizeof(struct il_station_priv); |
5721 | hw->vif_data_size = sizeof(struct il_vif_priv); | |
be663ab6 | 5722 | |
8c9c48d5 SG |
5723 | hw->wiphy->interface_modes = |
5724 | BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC); | |
be663ab6 | 5725 | |
e7392364 SG |
5726 | hw->wiphy->flags |= |
5727 | WIPHY_FLAG_CUSTOM_REGULATORY | WIPHY_FLAG_DISABLE_BEACON_HINTS; | |
be663ab6 WYG |
5728 | |
5729 | /* | |
5730 | * For now, disable PS by default because it affects | |
5731 | * RX performance significantly. | |
5732 | */ | |
5733 | hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; | |
5734 | ||
5735 | hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; | |
5736 | /* we create the 802.11 header and a zero-length SSID element */ | |
5737 | hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2; | |
5738 | ||
5739 | /* Default value; 4 EDCA QOS priorities */ | |
5740 | hw->queues = 4; | |
5741 | ||
e2ebc833 | 5742 | hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL; |
be663ab6 | 5743 | |
46bc8d4b SG |
5744 | if (il->bands[IEEE80211_BAND_2GHZ].n_channels) |
5745 | il->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = | |
e7392364 | 5746 | &il->bands[IEEE80211_BAND_2GHZ]; |
46bc8d4b SG |
5747 | if (il->bands[IEEE80211_BAND_5GHZ].n_channels) |
5748 | il->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
e7392364 | 5749 | &il->bands[IEEE80211_BAND_5GHZ]; |
be663ab6 | 5750 | |
46bc8d4b | 5751 | il_leds_init(il); |
be663ab6 | 5752 | |
46bc8d4b | 5753 | ret = ieee80211_register_hw(il->hw); |
be663ab6 | 5754 | if (ret) { |
9406f797 | 5755 | IL_ERR("Failed to register hw (error %d)\n", ret); |
be663ab6 WYG |
5756 | return ret; |
5757 | } | |
46bc8d4b | 5758 | il->mac80211_registered = 1; |
be663ab6 WYG |
5759 | |
5760 | return 0; | |
5761 | } | |
5762 | ||
e7392364 SG |
5763 | int |
5764 | il4965_mac_start(struct ieee80211_hw *hw) | |
be663ab6 | 5765 | { |
46bc8d4b | 5766 | struct il_priv *il = hw->priv; |
be663ab6 WYG |
5767 | int ret; |
5768 | ||
58de00a4 | 5769 | D_MAC80211("enter\n"); |
be663ab6 WYG |
5770 | |
5771 | /* we should be verifying the device is ready to be opened */ | |
46bc8d4b SG |
5772 | mutex_lock(&il->mutex); |
5773 | ret = __il4965_up(il); | |
5774 | mutex_unlock(&il->mutex); | |
be663ab6 WYG |
5775 | |
5776 | if (ret) | |
5777 | return ret; | |
5778 | ||
46bc8d4b | 5779 | if (il_is_rfkill(il)) |
be663ab6 WYG |
5780 | goto out; |
5781 | ||
58de00a4 | 5782 | D_INFO("Start UP work done.\n"); |
be663ab6 WYG |
5783 | |
5784 | /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from | |
5785 | * mac80211 will not be run successfully. */ | |
46bc8d4b | 5786 | ret = wait_event_timeout(il->wait_command_queue, |
e7392364 SG |
5787 | test_bit(S_READY, &il->status), |
5788 | UCODE_READY_TIMEOUT); | |
be663ab6 | 5789 | if (!ret) { |
a6766ccd | 5790 | if (!test_bit(S_READY, &il->status)) { |
9406f797 | 5791 | IL_ERR("START_ALIVE timeout after %dms.\n", |
be663ab6 WYG |
5792 | jiffies_to_msecs(UCODE_READY_TIMEOUT)); |
5793 | return -ETIMEDOUT; | |
5794 | } | |
5795 | } | |
5796 | ||
46bc8d4b | 5797 | il4965_led_enable(il); |
be663ab6 WYG |
5798 | |
5799 | out: | |
46bc8d4b | 5800 | il->is_open = 1; |
58de00a4 | 5801 | D_MAC80211("leave\n"); |
be663ab6 WYG |
5802 | return 0; |
5803 | } | |
5804 | ||
e7392364 SG |
5805 | void |
5806 | il4965_mac_stop(struct ieee80211_hw *hw) | |
be663ab6 | 5807 | { |
46bc8d4b | 5808 | struct il_priv *il = hw->priv; |
be663ab6 | 5809 | |
58de00a4 | 5810 | D_MAC80211("enter\n"); |
be663ab6 | 5811 | |
46bc8d4b | 5812 | if (!il->is_open) |
be663ab6 WYG |
5813 | return; |
5814 | ||
46bc8d4b | 5815 | il->is_open = 0; |
be663ab6 | 5816 | |
46bc8d4b | 5817 | il4965_down(il); |
be663ab6 | 5818 | |
46bc8d4b | 5819 | flush_workqueue(il->workqueue); |
be663ab6 | 5820 | |
a078a1fd SG |
5821 | /* User space software may expect getting rfkill changes |
5822 | * even if interface is down */ | |
841b2cca | 5823 | _il_wr(il, CSR_INT, 0xFFFFFFFF); |
46bc8d4b | 5824 | il_enable_rfkill_int(il); |
be663ab6 | 5825 | |
58de00a4 | 5826 | D_MAC80211("leave\n"); |
be663ab6 WYG |
5827 | } |
5828 | ||
e7392364 SG |
5829 | void |
5830 | il4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |
be663ab6 | 5831 | { |
46bc8d4b | 5832 | struct il_priv *il = hw->priv; |
be663ab6 | 5833 | |
58de00a4 | 5834 | D_MACDUMP("enter\n"); |
be663ab6 | 5835 | |
58de00a4 | 5836 | D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, |
e7392364 | 5837 | ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); |
be663ab6 | 5838 | |
46bc8d4b | 5839 | if (il4965_tx_skb(il, skb)) |
be663ab6 WYG |
5840 | dev_kfree_skb_any(skb); |
5841 | ||
58de00a4 | 5842 | D_MACDUMP("leave\n"); |
be663ab6 WYG |
5843 | } |
5844 | ||
e7392364 SG |
5845 | void |
5846 | il4965_mac_update_tkip_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
5847 | struct ieee80211_key_conf *keyconf, | |
5848 | struct ieee80211_sta *sta, u32 iv32, u16 * phase1key) | |
be663ab6 | 5849 | { |
46bc8d4b | 5850 | struct il_priv *il = hw->priv; |
be663ab6 | 5851 | |
58de00a4 | 5852 | D_MAC80211("enter\n"); |
be663ab6 | 5853 | |
83007196 | 5854 | il4965_update_tkip_key(il, keyconf, sta, iv32, phase1key); |
be663ab6 | 5855 | |
58de00a4 | 5856 | D_MAC80211("leave\n"); |
be663ab6 WYG |
5857 | } |
5858 | ||
e7392364 SG |
5859 | int |
5860 | il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, | |
5861 | struct ieee80211_vif *vif, struct ieee80211_sta *sta, | |
5862 | struct ieee80211_key_conf *key) | |
be663ab6 | 5863 | { |
46bc8d4b | 5864 | struct il_priv *il = hw->priv; |
be663ab6 WYG |
5865 | int ret; |
5866 | u8 sta_id; | |
5867 | bool is_default_wep_key = false; | |
5868 | ||
58de00a4 | 5869 | D_MAC80211("enter\n"); |
be663ab6 | 5870 | |
46bc8d4b | 5871 | if (il->cfg->mod_params->sw_crypto) { |
58de00a4 | 5872 | D_MAC80211("leave - hwcrypto disabled\n"); |
be663ab6 WYG |
5873 | return -EOPNOTSUPP; |
5874 | } | |
5875 | ||
83007196 | 5876 | sta_id = il_sta_id_or_broadcast(il, sta); |
e2ebc833 | 5877 | if (sta_id == IL_INVALID_STATION) |
be663ab6 WYG |
5878 | return -EINVAL; |
5879 | ||
46bc8d4b SG |
5880 | mutex_lock(&il->mutex); |
5881 | il_scan_cancel_timeout(il, 100); | |
be663ab6 WYG |
5882 | |
5883 | /* | |
5884 | * If we are getting WEP group key and we didn't receive any key mapping | |
5885 | * so far, we are in legacy wep mode (group key only), otherwise we are | |
5886 | * in 1X mode. | |
5887 | * In legacy wep mode, we use another host command to the uCode. | |
5888 | */ | |
5889 | if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 || | |
e7392364 | 5890 | key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) { |
be663ab6 | 5891 | if (cmd == SET_KEY) |
d735f921 | 5892 | is_default_wep_key = !il->_4965.key_mapping_keys; |
be663ab6 WYG |
5893 | else |
5894 | is_default_wep_key = | |
e7392364 | 5895 | (key->hw_key_idx == HW_KEY_DEFAULT); |
be663ab6 WYG |
5896 | } |
5897 | ||
5898 | switch (cmd) { | |
5899 | case SET_KEY: | |
5900 | if (is_default_wep_key) | |
83007196 | 5901 | ret = il4965_set_default_wep_key(il, key); |
be663ab6 | 5902 | else |
83007196 | 5903 | ret = il4965_set_dynamic_key(il, key, sta_id); |
be663ab6 | 5904 | |
58de00a4 | 5905 | D_MAC80211("enable hwcrypto key\n"); |
be663ab6 WYG |
5906 | break; |
5907 | case DISABLE_KEY: | |
5908 | if (is_default_wep_key) | |
83007196 | 5909 | ret = il4965_remove_default_wep_key(il, key); |
be663ab6 | 5910 | else |
83007196 | 5911 | ret = il4965_remove_dynamic_key(il, key, sta_id); |
be663ab6 | 5912 | |
58de00a4 | 5913 | D_MAC80211("disable hwcrypto key\n"); |
be663ab6 WYG |
5914 | break; |
5915 | default: | |
5916 | ret = -EINVAL; | |
5917 | } | |
5918 | ||
46bc8d4b | 5919 | mutex_unlock(&il->mutex); |
58de00a4 | 5920 | D_MAC80211("leave\n"); |
be663ab6 WYG |
5921 | |
5922 | return ret; | |
5923 | } | |
5924 | ||
e7392364 SG |
5925 | int |
5926 | il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
5927 | enum ieee80211_ampdu_mlme_action action, | |
5928 | struct ieee80211_sta *sta, u16 tid, u16 * ssn, | |
5929 | u8 buf_size) | |
be663ab6 | 5930 | { |
46bc8d4b | 5931 | struct il_priv *il = hw->priv; |
be663ab6 WYG |
5932 | int ret = -EINVAL; |
5933 | ||
e7392364 | 5934 | D_HT("A-MPDU action on addr %pM tid %d\n", sta->addr, tid); |
be663ab6 | 5935 | |
46bc8d4b | 5936 | if (!(il->cfg->sku & IL_SKU_N)) |
be663ab6 WYG |
5937 | return -EACCES; |
5938 | ||
46bc8d4b | 5939 | mutex_lock(&il->mutex); |
be663ab6 WYG |
5940 | |
5941 | switch (action) { | |
5942 | case IEEE80211_AMPDU_RX_START: | |
58de00a4 | 5943 | D_HT("start Rx\n"); |
46bc8d4b | 5944 | ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn); |
be663ab6 WYG |
5945 | break; |
5946 | case IEEE80211_AMPDU_RX_STOP: | |
58de00a4 | 5947 | D_HT("stop Rx\n"); |
46bc8d4b | 5948 | ret = il4965_sta_rx_agg_stop(il, sta, tid); |
a6766ccd | 5949 | if (test_bit(S_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
5950 | ret = 0; |
5951 | break; | |
5952 | case IEEE80211_AMPDU_TX_START: | |
58de00a4 | 5953 | D_HT("start Tx\n"); |
46bc8d4b | 5954 | ret = il4965_tx_agg_start(il, vif, sta, tid, ssn); |
be663ab6 WYG |
5955 | break; |
5956 | case IEEE80211_AMPDU_TX_STOP: | |
58de00a4 | 5957 | D_HT("stop Tx\n"); |
46bc8d4b | 5958 | ret = il4965_tx_agg_stop(il, vif, sta, tid); |
a6766ccd | 5959 | if (test_bit(S_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
5960 | ret = 0; |
5961 | break; | |
5962 | case IEEE80211_AMPDU_TX_OPERATIONAL: | |
5963 | ret = 0; | |
5964 | break; | |
5965 | } | |
46bc8d4b | 5966 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
5967 | |
5968 | return ret; | |
5969 | } | |
5970 | ||
e7392364 SG |
5971 | int |
5972 | il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
5973 | struct ieee80211_sta *sta) | |
be663ab6 | 5974 | { |
46bc8d4b | 5975 | struct il_priv *il = hw->priv; |
e2ebc833 | 5976 | struct il_station_priv *sta_priv = (void *)sta->drv_priv; |
be663ab6 WYG |
5977 | bool is_ap = vif->type == NL80211_IFTYPE_STATION; |
5978 | int ret; | |
5979 | u8 sta_id; | |
5980 | ||
e7392364 | 5981 | D_INFO("received request to add station %pM\n", sta->addr); |
46bc8d4b | 5982 | mutex_lock(&il->mutex); |
e7392364 | 5983 | D_INFO("proceeding to add station %pM\n", sta->addr); |
e2ebc833 | 5984 | sta_priv->common.sta_id = IL_INVALID_STATION; |
be663ab6 WYG |
5985 | |
5986 | atomic_set(&sta_priv->pending_frames, 0); | |
5987 | ||
e7392364 | 5988 | ret = |
83007196 | 5989 | il_add_station_common(il, sta->addr, is_ap, sta, &sta_id); |
be663ab6 | 5990 | if (ret) { |
e7392364 | 5991 | IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret); |
be663ab6 | 5992 | /* Should we return success if return code is EEXIST ? */ |
46bc8d4b | 5993 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
5994 | return ret; |
5995 | } | |
5996 | ||
5997 | sta_priv->common.sta_id = sta_id; | |
5998 | ||
5999 | /* Initialize rate scaling */ | |
e7392364 | 6000 | D_INFO("Initializing rate scaling for station %pM\n", sta->addr); |
46bc8d4b SG |
6001 | il4965_rs_rate_init(il, sta, sta_id); |
6002 | mutex_unlock(&il->mutex); | |
be663ab6 WYG |
6003 | |
6004 | return 0; | |
6005 | } | |
6006 | ||
e7392364 SG |
6007 | void |
6008 | il4965_mac_channel_switch(struct ieee80211_hw *hw, | |
6009 | struct ieee80211_channel_switch *ch_switch) | |
be663ab6 | 6010 | { |
46bc8d4b | 6011 | struct il_priv *il = hw->priv; |
e2ebc833 | 6012 | const struct il_channel_info *ch_info; |
be663ab6 WYG |
6013 | struct ieee80211_conf *conf = &hw->conf; |
6014 | struct ieee80211_channel *channel = ch_switch->channel; | |
46bc8d4b | 6015 | struct il_ht_config *ht_conf = &il->current_ht_config; |
be663ab6 | 6016 | u16 ch; |
be663ab6 | 6017 | |
58de00a4 | 6018 | D_MAC80211("enter\n"); |
be663ab6 | 6019 | |
46bc8d4b | 6020 | mutex_lock(&il->mutex); |
28a6e577 | 6021 | |
46bc8d4b | 6022 | if (il_is_rfkill(il)) |
28a6e577 | 6023 | goto out; |
be663ab6 | 6024 | |
a6766ccd SG |
6025 | if (test_bit(S_EXIT_PENDING, &il->status) || |
6026 | test_bit(S_SCANNING, &il->status) || | |
6027 | test_bit(S_CHANNEL_SWITCH_PENDING, &il->status)) | |
28a6e577 | 6028 | goto out; |
be663ab6 | 6029 | |
c8b03958 | 6030 | if (!il_is_associated(il)) |
28a6e577 | 6031 | goto out; |
be663ab6 | 6032 | |
1600b875 | 6033 | if (!il->ops->set_channel_switch) |
7f1f9742 | 6034 | goto out; |
be663ab6 | 6035 | |
7f1f9742 | 6036 | ch = channel->hw_value; |
c8b03958 | 6037 | if (le16_to_cpu(il->active.channel) == ch) |
7f1f9742 SG |
6038 | goto out; |
6039 | ||
46bc8d4b | 6040 | ch_info = il_get_channel_info(il, channel->band, ch); |
e2ebc833 | 6041 | if (!il_is_channel_valid(ch_info)) { |
58de00a4 | 6042 | D_MAC80211("invalid channel\n"); |
7f1f9742 SG |
6043 | goto out; |
6044 | } | |
6045 | ||
46bc8d4b | 6046 | spin_lock_irq(&il->lock); |
7f1f9742 | 6047 | |
46bc8d4b | 6048 | il->current_ht_config.smps = conf->smps_mode; |
7f1f9742 SG |
6049 | |
6050 | /* Configure HT40 channels */ | |
1c03c462 SG |
6051 | il->ht.enabled = conf_is_ht(conf); |
6052 | if (il->ht.enabled) { | |
7f1f9742 | 6053 | if (conf_is_ht40_minus(conf)) { |
1c03c462 | 6054 | il->ht.extension_chan_offset = |
e7392364 | 6055 | IEEE80211_HT_PARAM_CHA_SEC_BELOW; |
1c03c462 | 6056 | il->ht.is_40mhz = true; |
7f1f9742 | 6057 | } else if (conf_is_ht40_plus(conf)) { |
1c03c462 | 6058 | il->ht.extension_chan_offset = |
e7392364 | 6059 | IEEE80211_HT_PARAM_CHA_SEC_ABOVE; |
1c03c462 | 6060 | il->ht.is_40mhz = true; |
7f1f9742 | 6061 | } else { |
1c03c462 | 6062 | il->ht.extension_chan_offset = |
e7392364 | 6063 | IEEE80211_HT_PARAM_CHA_SEC_NONE; |
1c03c462 | 6064 | il->ht.is_40mhz = false; |
be663ab6 | 6065 | } |
7f1f9742 | 6066 | } else |
1c03c462 | 6067 | il->ht.is_40mhz = false; |
7f1f9742 | 6068 | |
c8b03958 SG |
6069 | if ((le16_to_cpu(il->staging.channel) != ch)) |
6070 | il->staging.flags = 0; | |
7f1f9742 | 6071 | |
83007196 | 6072 | il_set_rxon_channel(il, channel); |
46bc8d4b | 6073 | il_set_rxon_ht(il, ht_conf); |
83007196 | 6074 | il_set_flags_for_band(il, channel->band, il->vif); |
7f1f9742 | 6075 | |
46bc8d4b | 6076 | spin_unlock_irq(&il->lock); |
7f1f9742 | 6077 | |
46bc8d4b | 6078 | il_set_rate(il); |
7f1f9742 SG |
6079 | /* |
6080 | * at this point, staging_rxon has the | |
6081 | * configuration for channel switch | |
6082 | */ | |
a6766ccd | 6083 | set_bit(S_CHANNEL_SWITCH_PENDING, &il->status); |
46bc8d4b | 6084 | il->switch_channel = cpu_to_le16(ch); |
1600b875 | 6085 | if (il->ops->set_channel_switch(il, ch_switch)) { |
a6766ccd | 6086 | clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status); |
46bc8d4b | 6087 | il->switch_channel = 0; |
83007196 | 6088 | ieee80211_chswitch_done(il->vif, false); |
be663ab6 | 6089 | } |
7f1f9742 | 6090 | |
be663ab6 | 6091 | out: |
46bc8d4b | 6092 | mutex_unlock(&il->mutex); |
58de00a4 | 6093 | D_MAC80211("leave\n"); |
be663ab6 WYG |
6094 | } |
6095 | ||
e7392364 SG |
6096 | void |
6097 | il4965_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags, | |
6098 | unsigned int *total_flags, u64 multicast) | |
be663ab6 | 6099 | { |
46bc8d4b | 6100 | struct il_priv *il = hw->priv; |
be663ab6 | 6101 | __le32 filter_or = 0, filter_nand = 0; |
be663ab6 WYG |
6102 | |
6103 | #define CHK(test, flag) do { \ | |
6104 | if (*total_flags & (test)) \ | |
6105 | filter_or |= (flag); \ | |
6106 | else \ | |
6107 | filter_nand |= (flag); \ | |
6108 | } while (0) | |
6109 | ||
e7392364 SG |
6110 | D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags, |
6111 | *total_flags); | |
be663ab6 WYG |
6112 | |
6113 | CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK); | |
6114 | /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */ | |
6115 | CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK); | |
6116 | CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK); | |
6117 | ||
6118 | #undef CHK | |
6119 | ||
46bc8d4b | 6120 | mutex_lock(&il->mutex); |
be663ab6 | 6121 | |
c8b03958 SG |
6122 | il->staging.filter_flags &= ~filter_nand; |
6123 | il->staging.filter_flags |= filter_or; | |
be663ab6 | 6124 | |
17d6e557 SG |
6125 | /* |
6126 | * Not committing directly because hardware can perform a scan, | |
6127 | * but we'll eventually commit the filter flags change anyway. | |
6128 | */ | |
be663ab6 | 6129 | |
46bc8d4b | 6130 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
6131 | |
6132 | /* | |
6133 | * Receiving all multicast frames is always enabled by the | |
e2ebc833 | 6134 | * default flags setup in il_connection_init_rx_config() |
be663ab6 WYG |
6135 | * since we currently do not support programming multicast |
6136 | * filters into the device. | |
6137 | */ | |
e7392364 SG |
6138 | *total_flags &= |
6139 | FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS | | |
6140 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; | |
be663ab6 WYG |
6141 | } |
6142 | ||
6143 | /***************************************************************************** | |
6144 | * | |
6145 | * driver setup and teardown | |
6146 | * | |
6147 | *****************************************************************************/ | |
6148 | ||
e7392364 SG |
6149 | static void |
6150 | il4965_bg_txpower_work(struct work_struct *work) | |
be663ab6 | 6151 | { |
46bc8d4b | 6152 | struct il_priv *il = container_of(work, struct il_priv, |
e7392364 | 6153 | txpower_work); |
be663ab6 | 6154 | |
46bc8d4b | 6155 | mutex_lock(&il->mutex); |
f325757a | 6156 | |
be663ab6 | 6157 | /* If a scan happened to start before we got here |
ebf0d90d | 6158 | * then just return; the stats notification will |
be663ab6 WYG |
6159 | * kick off another scheduled work to compensate for |
6160 | * any temperature delta we missed here. */ | |
a6766ccd SG |
6161 | if (test_bit(S_EXIT_PENDING, &il->status) || |
6162 | test_bit(S_SCANNING, &il->status)) | |
f325757a | 6163 | goto out; |
be663ab6 WYG |
6164 | |
6165 | /* Regardless of if we are associated, we must reconfigure the | |
6166 | * TX power since frames can be sent on non-radar channels while | |
6167 | * not associated */ | |
1600b875 | 6168 | il->ops->send_tx_power(il); |
be663ab6 WYG |
6169 | |
6170 | /* Update last_temperature to keep is_calib_needed from running | |
6171 | * when it isn't needed... */ | |
46bc8d4b | 6172 | il->last_temperature = il->temperature; |
f325757a | 6173 | out: |
46bc8d4b | 6174 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
6175 | } |
6176 | ||
e7392364 SG |
6177 | static void |
6178 | il4965_setup_deferred_work(struct il_priv *il) | |
be663ab6 | 6179 | { |
46bc8d4b | 6180 | il->workqueue = create_singlethread_workqueue(DRV_NAME); |
be663ab6 | 6181 | |
46bc8d4b | 6182 | init_waitqueue_head(&il->wait_command_queue); |
be663ab6 | 6183 | |
46bc8d4b SG |
6184 | INIT_WORK(&il->restart, il4965_bg_restart); |
6185 | INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish); | |
6186 | INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work); | |
6187 | INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start); | |
6188 | INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start); | |
be663ab6 | 6189 | |
46bc8d4b | 6190 | il_setup_scan_deferred_work(il); |
be663ab6 | 6191 | |
46bc8d4b | 6192 | INIT_WORK(&il->txpower_work, il4965_bg_txpower_work); |
be663ab6 | 6193 | |
ebf0d90d SG |
6194 | init_timer(&il->stats_periodic); |
6195 | il->stats_periodic.data = (unsigned long)il; | |
6196 | il->stats_periodic.function = il4965_bg_stats_periodic; | |
be663ab6 | 6197 | |
46bc8d4b SG |
6198 | init_timer(&il->watchdog); |
6199 | il->watchdog.data = (unsigned long)il; | |
6200 | il->watchdog.function = il_bg_watchdog; | |
be663ab6 | 6201 | |
e7392364 SG |
6202 | tasklet_init(&il->irq_tasklet, |
6203 | (void (*)(unsigned long))il4965_irq_tasklet, | |
6204 | (unsigned long)il); | |
be663ab6 WYG |
6205 | } |
6206 | ||
e7392364 SG |
6207 | static void |
6208 | il4965_cancel_deferred_work(struct il_priv *il) | |
be663ab6 | 6209 | { |
46bc8d4b SG |
6210 | cancel_work_sync(&il->txpower_work); |
6211 | cancel_delayed_work_sync(&il->init_alive_start); | |
6212 | cancel_delayed_work(&il->alive_start); | |
6213 | cancel_work_sync(&il->run_time_calib_work); | |
be663ab6 | 6214 | |
46bc8d4b | 6215 | il_cancel_scan_deferred_work(il); |
be663ab6 | 6216 | |
ebf0d90d | 6217 | del_timer_sync(&il->stats_periodic); |
be663ab6 WYG |
6218 | } |
6219 | ||
e7392364 SG |
6220 | static void |
6221 | il4965_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates) | |
be663ab6 WYG |
6222 | { |
6223 | int i; | |
6224 | ||
2eb05816 | 6225 | for (i = 0; i < RATE_COUNT_LEGACY; i++) { |
d2ddf621 | 6226 | rates[i].bitrate = il_rates[i].ieee * 5; |
e7392364 | 6227 | rates[i].hw_value = i; /* Rate scaling will work on idxes */ |
be663ab6 WYG |
6228 | rates[i].hw_value_short = i; |
6229 | rates[i].flags = 0; | |
e2ebc833 | 6230 | if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) { |
be663ab6 WYG |
6231 | /* |
6232 | * If CCK != 1M then set short preamble rate flag. | |
6233 | */ | |
6234 | rates[i].flags |= | |
e7392364 SG |
6235 | (il_rates[i].plcp == |
6236 | RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE; | |
be663ab6 WYG |
6237 | } |
6238 | } | |
6239 | } | |
e7392364 | 6240 | |
be663ab6 | 6241 | /* |
46bc8d4b | 6242 | * Acquire il->lock before calling this function ! |
be663ab6 | 6243 | */ |
e7392364 SG |
6244 | void |
6245 | il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx) | |
be663ab6 | 6246 | { |
e7392364 | 6247 | il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8)); |
0c2c8852 | 6248 | il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx); |
be663ab6 WYG |
6249 | } |
6250 | ||
e7392364 SG |
6251 | void |
6252 | il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq, | |
6253 | int tx_fifo_id, int scd_retry) | |
be663ab6 WYG |
6254 | { |
6255 | int txq_id = txq->q.id; | |
6256 | ||
6257 | /* Find out whether to activate Tx queue */ | |
46bc8d4b | 6258 | int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0; |
be663ab6 WYG |
6259 | |
6260 | /* Set up and activate */ | |
d3175167 | 6261 | il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id), |
1722f8e1 SG |
6262 | (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) | |
6263 | (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) | | |
6264 | (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) | | |
6265 | (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) | | |
6266 | IL49_SCD_QUEUE_STTS_REG_MSK); | |
be663ab6 WYG |
6267 | |
6268 | txq->sched_retry = scd_retry; | |
6269 | ||
e7392364 SG |
6270 | D_INFO("%s %s Queue %d on AC %d\n", active ? "Activate" : "Deactivate", |
6271 | scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); | |
be663ab6 WYG |
6272 | } |
6273 | ||
c39ae9fd SG |
6274 | const struct ieee80211_ops il4965_mac_ops = { |
6275 | .tx = il4965_mac_tx, | |
6276 | .start = il4965_mac_start, | |
6277 | .stop = il4965_mac_stop, | |
6278 | .add_interface = il_mac_add_interface, | |
6279 | .remove_interface = il_mac_remove_interface, | |
6280 | .change_interface = il_mac_change_interface, | |
6281 | .config = il_mac_config, | |
6282 | .configure_filter = il4965_configure_filter, | |
6283 | .set_key = il4965_mac_set_key, | |
6284 | .update_tkip_key = il4965_mac_update_tkip_key, | |
6285 | .conf_tx = il_mac_conf_tx, | |
6286 | .reset_tsf = il_mac_reset_tsf, | |
6287 | .bss_info_changed = il_mac_bss_info_changed, | |
6288 | .ampdu_action = il4965_mac_ampdu_action, | |
6289 | .hw_scan = il_mac_hw_scan, | |
6290 | .sta_add = il4965_mac_sta_add, | |
6291 | .sta_remove = il_mac_sta_remove, | |
6292 | .channel_switch = il4965_mac_channel_switch, | |
6293 | .tx_last_beacon = il_mac_tx_last_beacon, | |
6294 | }; | |
6295 | ||
e7392364 SG |
6296 | static int |
6297 | il4965_init_drv(struct il_priv *il) | |
be663ab6 WYG |
6298 | { |
6299 | int ret; | |
6300 | ||
46bc8d4b SG |
6301 | spin_lock_init(&il->sta_lock); |
6302 | spin_lock_init(&il->hcmd_lock); | |
be663ab6 | 6303 | |
46bc8d4b | 6304 | INIT_LIST_HEAD(&il->free_frames); |
be663ab6 | 6305 | |
46bc8d4b | 6306 | mutex_init(&il->mutex); |
be663ab6 | 6307 | |
46bc8d4b SG |
6308 | il->ieee_channels = NULL; |
6309 | il->ieee_rates = NULL; | |
6310 | il->band = IEEE80211_BAND_2GHZ; | |
be663ab6 | 6311 | |
46bc8d4b SG |
6312 | il->iw_mode = NL80211_IFTYPE_STATION; |
6313 | il->current_ht_config.smps = IEEE80211_SMPS_STATIC; | |
6314 | il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF; | |
be663ab6 WYG |
6315 | |
6316 | /* initialize force reset */ | |
46bc8d4b | 6317 | il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD; |
be663ab6 WYG |
6318 | |
6319 | /* Choose which receivers/antennas to use */ | |
c9363551 SG |
6320 | if (il->ops->set_rxon_chain) |
6321 | il->ops->set_rxon_chain(il); | |
be663ab6 | 6322 | |
46bc8d4b | 6323 | il_init_scan_params(il); |
be663ab6 | 6324 | |
46bc8d4b | 6325 | ret = il_init_channel_map(il); |
be663ab6 | 6326 | if (ret) { |
9406f797 | 6327 | IL_ERR("initializing regulatory failed: %d\n", ret); |
be663ab6 WYG |
6328 | goto err; |
6329 | } | |
6330 | ||
46bc8d4b | 6331 | ret = il_init_geos(il); |
be663ab6 | 6332 | if (ret) { |
9406f797 | 6333 | IL_ERR("initializing geos failed: %d\n", ret); |
be663ab6 WYG |
6334 | goto err_free_channel_map; |
6335 | } | |
46bc8d4b | 6336 | il4965_init_hw_rates(il, il->ieee_rates); |
be663ab6 WYG |
6337 | |
6338 | return 0; | |
6339 | ||
6340 | err_free_channel_map: | |
46bc8d4b | 6341 | il_free_channel_map(il); |
be663ab6 WYG |
6342 | err: |
6343 | return ret; | |
6344 | } | |
6345 | ||
e7392364 SG |
6346 | static void |
6347 | il4965_uninit_drv(struct il_priv *il) | |
be663ab6 | 6348 | { |
46bc8d4b SG |
6349 | il_free_geos(il); |
6350 | il_free_channel_map(il); | |
6351 | kfree(il->scan_cmd); | |
be663ab6 WYG |
6352 | } |
6353 | ||
e7392364 SG |
6354 | static void |
6355 | il4965_hw_detect(struct il_priv *il) | |
be663ab6 | 6356 | { |
841b2cca SG |
6357 | il->hw_rev = _il_rd(il, CSR_HW_REV); |
6358 | il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG); | |
46bc8d4b | 6359 | il->rev_id = il->pci_dev->revision; |
58de00a4 | 6360 | D_INFO("HW Revision ID = 0x%X\n", il->rev_id); |
be663ab6 WYG |
6361 | } |
6362 | ||
1023f3bc SG |
6363 | static struct il_sensitivity_ranges il4965_sensitivity = { |
6364 | .min_nrg_cck = 97, | |
6365 | .max_nrg_cck = 0, /* not used, set to 0 */ | |
6366 | ||
6367 | .auto_corr_min_ofdm = 85, | |
6368 | .auto_corr_min_ofdm_mrc = 170, | |
6369 | .auto_corr_min_ofdm_x1 = 105, | |
6370 | .auto_corr_min_ofdm_mrc_x1 = 220, | |
6371 | ||
6372 | .auto_corr_max_ofdm = 120, | |
6373 | .auto_corr_max_ofdm_mrc = 210, | |
6374 | .auto_corr_max_ofdm_x1 = 140, | |
6375 | .auto_corr_max_ofdm_mrc_x1 = 270, | |
6376 | ||
6377 | .auto_corr_min_cck = 125, | |
6378 | .auto_corr_max_cck = 200, | |
6379 | .auto_corr_min_cck_mrc = 200, | |
6380 | .auto_corr_max_cck_mrc = 400, | |
6381 | ||
6382 | .nrg_th_cck = 100, | |
6383 | .nrg_th_ofdm = 100, | |
6384 | ||
6385 | .barker_corr_th_min = 190, | |
6386 | .barker_corr_th_min_mrc = 390, | |
6387 | .nrg_th_cca = 62, | |
6388 | }; | |
6389 | ||
6390 | static void | |
e7392364 | 6391 | il4965_set_hw_params(struct il_priv *il) |
be663ab6 | 6392 | { |
b16db50a | 6393 | il->hw_params.bcast_id = IL4965_BROADCAST_ID; |
46bc8d4b SG |
6394 | il->hw_params.max_rxq_size = RX_QUEUE_SIZE; |
6395 | il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; | |
6396 | if (il->cfg->mod_params->amsdu_size_8K) | |
6397 | il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K); | |
be663ab6 | 6398 | else |
46bc8d4b | 6399 | il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K); |
be663ab6 | 6400 | |
46bc8d4b | 6401 | il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL; |
be663ab6 | 6402 | |
46bc8d4b SG |
6403 | if (il->cfg->mod_params->disable_11n) |
6404 | il->cfg->sku &= ~IL_SKU_N; | |
be663ab6 | 6405 | |
1023f3bc SG |
6406 | if (il->cfg->mod_params->num_of_queues >= IL_MIN_NUM_QUEUES && |
6407 | il->cfg->mod_params->num_of_queues <= IL49_NUM_QUEUES) | |
6408 | il->cfg->num_of_queues = | |
6409 | il->cfg->mod_params->num_of_queues; | |
6410 | ||
6411 | il->hw_params.max_txq_num = il->cfg->num_of_queues; | |
6412 | il->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM; | |
6413 | il->hw_params.scd_bc_tbls_size = | |
6414 | il->cfg->num_of_queues * | |
6415 | sizeof(struct il4965_scd_bc_tbl); | |
6416 | ||
6417 | il->hw_params.tfd_size = sizeof(struct il_tfd); | |
6418 | il->hw_params.max_stations = IL4965_STATION_COUNT; | |
6419 | il->hw_params.max_data_size = IL49_RTC_DATA_SIZE; | |
6420 | il->hw_params.max_inst_size = IL49_RTC_INST_SIZE; | |
6421 | il->hw_params.max_bsm_size = BSM_SRAM_SIZE; | |
6422 | il->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ); | |
6423 | ||
6424 | il->hw_params.rx_wrt_ptr_reg = FH49_RSCSR_CHNL0_WPTR; | |
6425 | ||
6426 | il->hw_params.tx_chains_num = il4965_num_of_ant(il->cfg->valid_tx_ant); | |
6427 | il->hw_params.rx_chains_num = il4965_num_of_ant(il->cfg->valid_rx_ant); | |
6428 | il->hw_params.valid_tx_ant = il->cfg->valid_tx_ant; | |
6429 | il->hw_params.valid_rx_ant = il->cfg->valid_rx_ant; | |
6430 | ||
6431 | il->hw_params.ct_kill_threshold = | |
6432 | CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY); | |
6433 | ||
6434 | il->hw_params.sens = &il4965_sensitivity; | |
6435 | il->hw_params.beacon_time_tsf_bits = IL4965_EXT_BEACON_TIME_POS; | |
be663ab6 WYG |
6436 | } |
6437 | ||
be663ab6 | 6438 | static int |
e2ebc833 | 6439 | il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
be663ab6 | 6440 | { |
7c2cde2e | 6441 | int err = 0; |
46bc8d4b | 6442 | struct il_priv *il; |
be663ab6 | 6443 | struct ieee80211_hw *hw; |
e2ebc833 | 6444 | struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data); |
be663ab6 WYG |
6445 | unsigned long flags; |
6446 | u16 pci_cmd; | |
6447 | ||
6448 | /************************ | |
6449 | * 1. Allocating HW data | |
6450 | ************************/ | |
6451 | ||
c39ae9fd | 6452 | hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il4965_mac_ops); |
be663ab6 WYG |
6453 | if (!hw) { |
6454 | err = -ENOMEM; | |
6455 | goto out; | |
6456 | } | |
46bc8d4b | 6457 | il = hw->priv; |
c39ae9fd | 6458 | il->hw = hw; |
be663ab6 WYG |
6459 | SET_IEEE80211_DEV(hw, &pdev->dev); |
6460 | ||
58de00a4 | 6461 | D_INFO("*** LOAD DRIVER ***\n"); |
46bc8d4b | 6462 | il->cfg = cfg; |
c39ae9fd | 6463 | il->ops = &il4965_ops; |
93b7654e SG |
6464 | #ifdef CONFIG_IWLEGACY_DEBUGFS |
6465 | il->debugfs_ops = &il4965_debugfs_ops; | |
6466 | #endif | |
46bc8d4b SG |
6467 | il->pci_dev = pdev; |
6468 | il->inta_mask = CSR_INI_SET_MASK; | |
be663ab6 | 6469 | |
be663ab6 WYG |
6470 | /************************** |
6471 | * 2. Initializing PCI bus | |
6472 | **************************/ | |
e7392364 SG |
6473 | pci_disable_link_state(pdev, |
6474 | PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
6475 | PCIE_LINK_STATE_CLKPM); | |
be663ab6 WYG |
6476 | |
6477 | if (pci_enable_device(pdev)) { | |
6478 | err = -ENODEV; | |
6479 | goto out_ieee80211_free_hw; | |
6480 | } | |
6481 | ||
6482 | pci_set_master(pdev); | |
6483 | ||
6484 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36)); | |
6485 | if (!err) | |
6486 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36)); | |
6487 | if (err) { | |
6488 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
6489 | if (!err) | |
e7392364 SG |
6490 | err = |
6491 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
be663ab6 WYG |
6492 | /* both attempts failed: */ |
6493 | if (err) { | |
9406f797 | 6494 | IL_WARN("No suitable DMA available.\n"); |
be663ab6 WYG |
6495 | goto out_pci_disable_device; |
6496 | } | |
6497 | } | |
6498 | ||
6499 | err = pci_request_regions(pdev, DRV_NAME); | |
6500 | if (err) | |
6501 | goto out_pci_disable_device; | |
6502 | ||
46bc8d4b | 6503 | pci_set_drvdata(pdev, il); |
be663ab6 | 6504 | |
be663ab6 WYG |
6505 | /*********************** |
6506 | * 3. Read REV register | |
6507 | ***********************/ | |
a5f16137 | 6508 | il->hw_base = pci_ioremap_bar(pdev, 0); |
46bc8d4b | 6509 | if (!il->hw_base) { |
be663ab6 WYG |
6510 | err = -ENODEV; |
6511 | goto out_pci_release_regions; | |
6512 | } | |
6513 | ||
58de00a4 | 6514 | D_INFO("pci_resource_len = 0x%08llx\n", |
e7392364 | 6515 | (unsigned long long)pci_resource_len(pdev, 0)); |
58de00a4 | 6516 | D_INFO("pci_resource_base = %p\n", il->hw_base); |
be663ab6 WYG |
6517 | |
6518 | /* these spin locks will be used in apm_ops.init and EEPROM access | |
6519 | * we should init now | |
6520 | */ | |
46bc8d4b SG |
6521 | spin_lock_init(&il->reg_lock); |
6522 | spin_lock_init(&il->lock); | |
be663ab6 WYG |
6523 | |
6524 | /* | |
6525 | * stop and reset the on-board processor just in case it is in a | |
6526 | * strange state ... like being left stranded by a primary kernel | |
6527 | * and this is now the kdump kernel trying to start up | |
6528 | */ | |
841b2cca | 6529 | _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); |
be663ab6 | 6530 | |
46bc8d4b | 6531 | il4965_hw_detect(il); |
e7392364 | 6532 | IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev); |
be663ab6 WYG |
6533 | |
6534 | /* We disable the RETRY_TIMEOUT register (0x41) to keep | |
6535 | * PCI Tx retries from interfering with C3 CPU state */ | |
6536 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
6537 | ||
46bc8d4b SG |
6538 | il4965_prepare_card_hw(il); |
6539 | if (!il->hw_ready) { | |
9406f797 | 6540 | IL_WARN("Failed, HW not ready\n"); |
be663ab6 WYG |
6541 | goto out_iounmap; |
6542 | } | |
6543 | ||
6544 | /***************** | |
6545 | * 4. Read EEPROM | |
6546 | *****************/ | |
6547 | /* Read the EEPROM */ | |
46bc8d4b | 6548 | err = il_eeprom_init(il); |
be663ab6 | 6549 | if (err) { |
9406f797 | 6550 | IL_ERR("Unable to init EEPROM\n"); |
be663ab6 WYG |
6551 | goto out_iounmap; |
6552 | } | |
46bc8d4b | 6553 | err = il4965_eeprom_check_version(il); |
be663ab6 WYG |
6554 | if (err) |
6555 | goto out_free_eeprom; | |
6556 | ||
6557 | if (err) | |
6558 | goto out_free_eeprom; | |
6559 | ||
6560 | /* extract MAC Address */ | |
46bc8d4b | 6561 | il4965_eeprom_get_mac(il, il->addresses[0].addr); |
58de00a4 | 6562 | D_INFO("MAC address: %pM\n", il->addresses[0].addr); |
46bc8d4b SG |
6563 | il->hw->wiphy->addresses = il->addresses; |
6564 | il->hw->wiphy->n_addresses = 1; | |
be663ab6 WYG |
6565 | |
6566 | /************************ | |
6567 | * 5. Setup HW constants | |
6568 | ************************/ | |
1023f3bc | 6569 | il4965_set_hw_params(il); |
be663ab6 WYG |
6570 | |
6571 | /******************* | |
46bc8d4b | 6572 | * 6. Setup il |
be663ab6 WYG |
6573 | *******************/ |
6574 | ||
46bc8d4b | 6575 | err = il4965_init_drv(il); |
be663ab6 WYG |
6576 | if (err) |
6577 | goto out_free_eeprom; | |
46bc8d4b | 6578 | /* At this point both hw and il are initialized. */ |
be663ab6 WYG |
6579 | |
6580 | /******************** | |
6581 | * 7. Setup services | |
6582 | ********************/ | |
46bc8d4b SG |
6583 | spin_lock_irqsave(&il->lock, flags); |
6584 | il_disable_interrupts(il); | |
6585 | spin_unlock_irqrestore(&il->lock, flags); | |
be663ab6 | 6586 | |
46bc8d4b | 6587 | pci_enable_msi(il->pci_dev); |
be663ab6 | 6588 | |
e7392364 | 6589 | err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il); |
be663ab6 | 6590 | if (err) { |
9406f797 | 6591 | IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq); |
be663ab6 WYG |
6592 | goto out_disable_msi; |
6593 | } | |
6594 | ||
46bc8d4b | 6595 | il4965_setup_deferred_work(il); |
d0c72347 | 6596 | il4965_setup_handlers(il); |
be663ab6 WYG |
6597 | |
6598 | /********************************************* | |
6599 | * 8. Enable interrupts and read RFKILL state | |
6600 | *********************************************/ | |
6601 | ||
a078a1fd | 6602 | /* enable rfkill interrupt: hw bug w/a */ |
46bc8d4b | 6603 | pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd); |
be663ab6 WYG |
6604 | if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { |
6605 | pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; | |
46bc8d4b | 6606 | pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd); |
be663ab6 WYG |
6607 | } |
6608 | ||
46bc8d4b | 6609 | il_enable_rfkill_int(il); |
be663ab6 WYG |
6610 | |
6611 | /* If platform's RF_KILL switch is NOT set to KILL */ | |
e7392364 | 6612 | if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) |
bc269a8e | 6613 | clear_bit(S_RFKILL, &il->status); |
be663ab6 | 6614 | else |
bc269a8e | 6615 | set_bit(S_RFKILL, &il->status); |
be663ab6 | 6616 | |
46bc8d4b | 6617 | wiphy_rfkill_set_hw_state(il->hw->wiphy, |
bc269a8e | 6618 | test_bit(S_RFKILL, &il->status)); |
be663ab6 | 6619 | |
46bc8d4b | 6620 | il_power_initialize(il); |
be663ab6 | 6621 | |
46bc8d4b | 6622 | init_completion(&il->_4965.firmware_loading_complete); |
be663ab6 | 6623 | |
46bc8d4b | 6624 | err = il4965_request_firmware(il, true); |
be663ab6 WYG |
6625 | if (err) |
6626 | goto out_destroy_workqueue; | |
6627 | ||
6628 | return 0; | |
6629 | ||
e7392364 | 6630 | out_destroy_workqueue: |
46bc8d4b SG |
6631 | destroy_workqueue(il->workqueue); |
6632 | il->workqueue = NULL; | |
6633 | free_irq(il->pci_dev->irq, il); | |
e7392364 | 6634 | out_disable_msi: |
46bc8d4b SG |
6635 | pci_disable_msi(il->pci_dev); |
6636 | il4965_uninit_drv(il); | |
e7392364 | 6637 | out_free_eeprom: |
46bc8d4b | 6638 | il_eeprom_free(il); |
e7392364 | 6639 | out_iounmap: |
a5f16137 | 6640 | iounmap(il->hw_base); |
e7392364 | 6641 | out_pci_release_regions: |
be663ab6 WYG |
6642 | pci_set_drvdata(pdev, NULL); |
6643 | pci_release_regions(pdev); | |
e7392364 | 6644 | out_pci_disable_device: |
be663ab6 | 6645 | pci_disable_device(pdev); |
e7392364 | 6646 | out_ieee80211_free_hw: |
46bc8d4b | 6647 | ieee80211_free_hw(il->hw); |
e7392364 | 6648 | out: |
be663ab6 WYG |
6649 | return err; |
6650 | } | |
6651 | ||
e7392364 SG |
6652 | static void __devexit |
6653 | il4965_pci_remove(struct pci_dev *pdev) | |
be663ab6 | 6654 | { |
46bc8d4b | 6655 | struct il_priv *il = pci_get_drvdata(pdev); |
be663ab6 WYG |
6656 | unsigned long flags; |
6657 | ||
46bc8d4b | 6658 | if (!il) |
be663ab6 WYG |
6659 | return; |
6660 | ||
46bc8d4b | 6661 | wait_for_completion(&il->_4965.firmware_loading_complete); |
be663ab6 | 6662 | |
58de00a4 | 6663 | D_INFO("*** UNLOAD DRIVER ***\n"); |
be663ab6 | 6664 | |
46bc8d4b | 6665 | il_dbgfs_unregister(il); |
e2ebc833 | 6666 | sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group); |
be663ab6 | 6667 | |
e2ebc833 SG |
6668 | /* ieee80211_unregister_hw call wil cause il_mac_stop to |
6669 | * to be called and il4965_down since we are removing the device | |
a6766ccd | 6670 | * we need to set S_EXIT_PENDING bit. |
be663ab6 | 6671 | */ |
a6766ccd | 6672 | set_bit(S_EXIT_PENDING, &il->status); |
be663ab6 | 6673 | |
46bc8d4b | 6674 | il_leds_exit(il); |
be663ab6 | 6675 | |
46bc8d4b SG |
6676 | if (il->mac80211_registered) { |
6677 | ieee80211_unregister_hw(il->hw); | |
6678 | il->mac80211_registered = 0; | |
be663ab6 | 6679 | } else { |
46bc8d4b | 6680 | il4965_down(il); |
be663ab6 WYG |
6681 | } |
6682 | ||
6683 | /* | |
6684 | * Make sure device is reset to low power before unloading driver. | |
e2ebc833 SG |
6685 | * This may be redundant with il4965_down(), but there are paths to |
6686 | * run il4965_down() without calling apm_ops.stop(), and there are | |
6687 | * paths to avoid running il4965_down() at all before leaving driver. | |
be663ab6 WYG |
6688 | * This (inexpensive) call *makes sure* device is reset. |
6689 | */ | |
46bc8d4b | 6690 | il_apm_stop(il); |
be663ab6 WYG |
6691 | |
6692 | /* make sure we flush any pending irq or | |
6693 | * tasklet for the driver | |
6694 | */ | |
46bc8d4b SG |
6695 | spin_lock_irqsave(&il->lock, flags); |
6696 | il_disable_interrupts(il); | |
6697 | spin_unlock_irqrestore(&il->lock, flags); | |
be663ab6 | 6698 | |
46bc8d4b | 6699 | il4965_synchronize_irq(il); |
be663ab6 | 6700 | |
46bc8d4b | 6701 | il4965_dealloc_ucode_pci(il); |
be663ab6 | 6702 | |
46bc8d4b SG |
6703 | if (il->rxq.bd) |
6704 | il4965_rx_queue_free(il, &il->rxq); | |
6705 | il4965_hw_txq_ctx_free(il); | |
be663ab6 | 6706 | |
46bc8d4b | 6707 | il_eeprom_free(il); |
be663ab6 | 6708 | |
be663ab6 | 6709 | /*netif_stop_queue(dev); */ |
46bc8d4b | 6710 | flush_workqueue(il->workqueue); |
be663ab6 | 6711 | |
e2ebc833 | 6712 | /* ieee80211_unregister_hw calls il_mac_stop, which flushes |
46bc8d4b | 6713 | * il->workqueue... so we can't take down the workqueue |
be663ab6 | 6714 | * until now... */ |
46bc8d4b SG |
6715 | destroy_workqueue(il->workqueue); |
6716 | il->workqueue = NULL; | |
be663ab6 | 6717 | |
46bc8d4b SG |
6718 | free_irq(il->pci_dev->irq, il); |
6719 | pci_disable_msi(il->pci_dev); | |
a5f16137 | 6720 | iounmap(il->hw_base); |
be663ab6 WYG |
6721 | pci_release_regions(pdev); |
6722 | pci_disable_device(pdev); | |
6723 | pci_set_drvdata(pdev, NULL); | |
6724 | ||
46bc8d4b | 6725 | il4965_uninit_drv(il); |
be663ab6 | 6726 | |
46bc8d4b | 6727 | dev_kfree_skb(il->beacon_skb); |
be663ab6 | 6728 | |
46bc8d4b | 6729 | ieee80211_free_hw(il->hw); |
be663ab6 WYG |
6730 | } |
6731 | ||
6732 | /* | |
6733 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
46bc8d4b | 6734 | * must be called under il->lock and mac access |
be663ab6 | 6735 | */ |
e7392364 SG |
6736 | void |
6737 | il4965_txq_set_sched(struct il_priv *il, u32 mask) | |
be663ab6 | 6738 | { |
d3175167 | 6739 | il_wr_prph(il, IL49_SCD_TXFACT, mask); |
be663ab6 WYG |
6740 | } |
6741 | ||
6742 | /***************************************************************************** | |
6743 | * | |
6744 | * driver and module entry point | |
6745 | * | |
6746 | *****************************************************************************/ | |
6747 | ||
6748 | /* Hardware specific file defines the PCI IDs table for that hardware module */ | |
e2ebc833 | 6749 | static DEFINE_PCI_DEVICE_TABLE(il4965_hw_card_ids) = { |
e2ebc833 SG |
6750 | {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)}, |
6751 | {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)}, | |
be663ab6 WYG |
6752 | {0} |
6753 | }; | |
e2ebc833 | 6754 | MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids); |
be663ab6 | 6755 | |
e2ebc833 | 6756 | static struct pci_driver il4965_driver = { |
be663ab6 | 6757 | .name = DRV_NAME, |
e2ebc833 SG |
6758 | .id_table = il4965_hw_card_ids, |
6759 | .probe = il4965_pci_probe, | |
6760 | .remove = __devexit_p(il4965_pci_remove), | |
6761 | .driver.pm = IL_LEGACY_PM_OPS, | |
be663ab6 WYG |
6762 | }; |
6763 | ||
e7392364 SG |
6764 | static int __init |
6765 | il4965_init(void) | |
be663ab6 WYG |
6766 | { |
6767 | ||
6768 | int ret; | |
6769 | pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n"); | |
6770 | pr_info(DRV_COPYRIGHT "\n"); | |
6771 | ||
e2ebc833 | 6772 | ret = il4965_rate_control_register(); |
be663ab6 WYG |
6773 | if (ret) { |
6774 | pr_err("Unable to register rate control algorithm: %d\n", ret); | |
6775 | return ret; | |
6776 | } | |
6777 | ||
e2ebc833 | 6778 | ret = pci_register_driver(&il4965_driver); |
be663ab6 WYG |
6779 | if (ret) { |
6780 | pr_err("Unable to initialize PCI module\n"); | |
6781 | goto error_register; | |
6782 | } | |
6783 | ||
6784 | return ret; | |
6785 | ||
6786 | error_register: | |
e2ebc833 | 6787 | il4965_rate_control_unregister(); |
be663ab6 WYG |
6788 | return ret; |
6789 | } | |
6790 | ||
e7392364 SG |
6791 | static void __exit |
6792 | il4965_exit(void) | |
be663ab6 | 6793 | { |
e2ebc833 SG |
6794 | pci_unregister_driver(&il4965_driver); |
6795 | il4965_rate_control_unregister(); | |
be663ab6 WYG |
6796 | } |
6797 | ||
e2ebc833 SG |
6798 | module_exit(il4965_exit); |
6799 | module_init(il4965_init); | |
be663ab6 | 6800 | |
d3175167 | 6801 | #ifdef CONFIG_IWLEGACY_DEBUG |
d2ddf621 | 6802 | module_param_named(debug, il_debug_level, uint, S_IRUGO | S_IWUSR); |
be663ab6 WYG |
6803 | MODULE_PARM_DESC(debug, "debug output mask"); |
6804 | #endif | |
6805 | ||
e2ebc833 | 6806 | module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, S_IRUGO); |
be663ab6 | 6807 | MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); |
e2ebc833 | 6808 | module_param_named(queues_num, il4965_mod_params.num_of_queues, int, S_IRUGO); |
be663ab6 | 6809 | MODULE_PARM_DESC(queues_num, "number of hw queues."); |
e2ebc833 | 6810 | module_param_named(11n_disable, il4965_mod_params.disable_11n, int, S_IRUGO); |
be663ab6 | 6811 | MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); |
e7392364 SG |
6812 | module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, int, |
6813 | S_IRUGO); | |
be663ab6 | 6814 | MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size"); |
e2ebc833 | 6815 | module_param_named(fw_restart, il4965_mod_params.restart_fw, int, S_IRUGO); |
be663ab6 | 6816 | MODULE_PARM_DESC(fw_restart, "restart firmware in case of error"); |