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4bc85c13 WYG |
1 | /****************************************************************************** |
2 | * | |
be663ab6 | 3 | * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. |
4bc85c13 WYG |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * Intel Linux Wireless <ilw@linux.intel.com> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | *****************************************************************************/ | |
26 | ||
27 | #include <linux/kernel.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/dma-mapping.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/sched.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/netdevice.h> | |
4bc85c13 WYG |
36 | #include <net/mac80211.h> |
37 | #include <linux/etherdevice.h> | |
38 | #include <asm/unaligned.h> | |
39 | ||
40 | #include "iwl-eeprom.h" | |
41 | #include "iwl-dev.h" | |
42 | #include "iwl-core.h" | |
43 | #include "iwl-io.h" | |
44 | #include "iwl-helpers.h" | |
be663ab6 | 45 | #include "iwl-4965-calib.h" |
4bc85c13 | 46 | #include "iwl-sta.h" |
be663ab6 WYG |
47 | #include "iwl-4965.h" |
48 | #include "iwl-4965-debugfs.h" | |
4bc85c13 | 49 | |
862d32e6 SG |
50 | #define IL_AC_UNSET -1 |
51 | ||
52 | /** | |
53 | * il_verify_inst_sparse - verify runtime uCode image in card vs. host, | |
54 | * using sample data 100 bytes apart. If these sample points are good, | |
55 | * it's a pretty good bet that everything between them is good, too. | |
56 | */ | |
57 | static int | |
58 | il4965_verify_inst_sparse(struct il_priv *il, __le32 *image, u32 len) | |
59 | { | |
60 | u32 val; | |
61 | int ret = 0; | |
62 | u32 errcnt = 0; | |
63 | u32 i; | |
64 | ||
65 | D_INFO("ucode inst image size is %u\n", len); | |
66 | ||
67 | for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) { | |
68 | /* read data comes through single port, auto-incr addr */ | |
69 | /* NOTE: Use the debugless read so we don't flood kernel log | |
70 | * if IL_DL_IO is set */ | |
71 | il_wr(il, HBUS_TARG_MEM_RADDR, | |
72 | i + IL4965_RTC_INST_LOWER_BOUND); | |
73 | val = _il_rd(il, HBUS_TARG_MEM_RDAT); | |
74 | if (val != le32_to_cpu(*image)) { | |
75 | ret = -EIO; | |
76 | errcnt++; | |
77 | if (errcnt >= 3) | |
78 | break; | |
79 | } | |
80 | } | |
81 | ||
82 | return ret; | |
83 | } | |
84 | ||
85 | /** | |
86 | * il4965_verify_inst_full - verify runtime uCode image in card vs. host, | |
87 | * looking at all data. | |
88 | */ | |
89 | static int il4965_verify_inst_full(struct il_priv *il, __le32 *image, | |
90 | u32 len) | |
91 | { | |
92 | u32 val; | |
93 | u32 save_len = len; | |
94 | int ret = 0; | |
95 | u32 errcnt; | |
96 | ||
97 | D_INFO("ucode inst image size is %u\n", len); | |
98 | ||
99 | il_wr(il, HBUS_TARG_MEM_RADDR, | |
100 | IL4965_RTC_INST_LOWER_BOUND); | |
101 | ||
102 | errcnt = 0; | |
103 | for (; len > 0; len -= sizeof(u32), image++) { | |
104 | /* read data comes through single port, auto-incr addr */ | |
105 | /* NOTE: Use the debugless read so we don't flood kernel log | |
106 | * if IL_DL_IO is set */ | |
107 | val = _il_rd(il, HBUS_TARG_MEM_RDAT); | |
108 | if (val != le32_to_cpu(*image)) { | |
109 | IL_ERR("uCode INST section is invalid at " | |
110 | "offset 0x%x, is 0x%x, s/b 0x%x\n", | |
111 | save_len - len, val, le32_to_cpu(*image)); | |
112 | ret = -EIO; | |
113 | errcnt++; | |
114 | if (errcnt >= 20) | |
115 | break; | |
116 | } | |
117 | } | |
118 | ||
119 | if (!errcnt) | |
120 | D_INFO( | |
121 | "ucode image in INSTRUCTION memory is good\n"); | |
122 | ||
123 | return ret; | |
124 | } | |
125 | ||
126 | /** | |
127 | * il4965_verify_ucode - determine which instruction image is in SRAM, | |
128 | * and verify its contents | |
129 | */ | |
130 | int il4965_verify_ucode(struct il_priv *il) | |
131 | { | |
132 | __le32 *image; | |
133 | u32 len; | |
134 | int ret; | |
135 | ||
136 | /* Try bootstrap */ | |
137 | image = (__le32 *)il->ucode_boot.v_addr; | |
138 | len = il->ucode_boot.len; | |
139 | ret = il4965_verify_inst_sparse(il, image, len); | |
140 | if (!ret) { | |
141 | D_INFO("Bootstrap uCode is good in inst SRAM\n"); | |
142 | return 0; | |
143 | } | |
144 | ||
145 | /* Try initialize */ | |
146 | image = (__le32 *)il->ucode_init.v_addr; | |
147 | len = il->ucode_init.len; | |
148 | ret = il4965_verify_inst_sparse(il, image, len); | |
149 | if (!ret) { | |
150 | D_INFO("Initialize uCode is good in inst SRAM\n"); | |
151 | return 0; | |
152 | } | |
153 | ||
154 | /* Try runtime/protocol */ | |
155 | image = (__le32 *)il->ucode_code.v_addr; | |
156 | len = il->ucode_code.len; | |
157 | ret = il4965_verify_inst_sparse(il, image, len); | |
158 | if (!ret) { | |
159 | D_INFO("Runtime uCode is good in inst SRAM\n"); | |
160 | return 0; | |
161 | } | |
162 | ||
163 | IL_ERR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n"); | |
164 | ||
165 | /* Since nothing seems to match, show first several data entries in | |
166 | * instruction SRAM, so maybe visual inspection will give a clue. | |
167 | * Selection of bootstrap image (vs. other images) is arbitrary. */ | |
168 | image = (__le32 *)il->ucode_boot.v_addr; | |
169 | len = il->ucode_boot.len; | |
170 | ret = il4965_verify_inst_full(il, image, len); | |
171 | ||
172 | return ret; | |
173 | } | |
174 | ||
56e7a8cc SG |
175 | /****************************************************************************** |
176 | * | |
177 | * EEPROM related functions | |
178 | * | |
179 | ******************************************************************************/ | |
180 | ||
181 | /* | |
182 | * The device's EEPROM semaphore prevents conflicts between driver and uCode | |
183 | * when accessing the EEPROM; each access is a series of pulses to/from the | |
184 | * EEPROM chip, not a single event, so even reads could conflict if they | |
185 | * weren't arbitrated by the semaphore. | |
186 | */ | |
187 | int il4965_eeprom_acquire_semaphore(struct il_priv *il) | |
188 | { | |
189 | u16 count; | |
190 | int ret; | |
191 | ||
192 | for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) { | |
193 | /* Request semaphore */ | |
194 | il_set_bit(il, CSR_HW_IF_CONFIG_REG, | |
195 | CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); | |
196 | ||
197 | /* See if we got it */ | |
198 | ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG, | |
199 | CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, | |
200 | CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, | |
201 | EEPROM_SEM_TIMEOUT); | |
202 | if (ret >= 0) | |
203 | return ret; | |
204 | } | |
205 | ||
206 | return ret; | |
207 | } | |
208 | ||
209 | void il4965_eeprom_release_semaphore(struct il_priv *il) | |
210 | { | |
211 | il_clear_bit(il, CSR_HW_IF_CONFIG_REG, | |
212 | CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); | |
213 | ||
214 | } | |
215 | ||
216 | int il4965_eeprom_check_version(struct il_priv *il) | |
217 | { | |
218 | u16 eeprom_ver; | |
219 | u16 calib_ver; | |
220 | ||
221 | eeprom_ver = il_eeprom_query16(il, EEPROM_VERSION); | |
222 | calib_ver = il_eeprom_query16(il, | |
223 | EEPROM_4965_CALIB_VERSION_OFFSET); | |
224 | ||
225 | if (eeprom_ver < il->cfg->eeprom_ver || | |
226 | calib_ver < il->cfg->eeprom_calib_ver) | |
227 | goto err; | |
228 | ||
229 | IL_INFO("device EEPROM VER=0x%x, CALIB=0x%x\n", | |
230 | eeprom_ver, calib_ver); | |
231 | ||
232 | return 0; | |
233 | err: | |
234 | IL_ERR("Unsupported (too old) EEPROM VER=0x%x < 0x%x " | |
235 | "CALIB=0x%x < 0x%x\n", | |
236 | eeprom_ver, il->cfg->eeprom_ver, | |
237 | calib_ver, il->cfg->eeprom_calib_ver); | |
238 | return -EINVAL; | |
239 | ||
240 | } | |
241 | ||
242 | void il4965_eeprom_get_mac(const struct il_priv *il, u8 *mac) | |
243 | { | |
244 | const u8 *addr = il_eeprom_query_addr(il, | |
245 | EEPROM_MAC_ADDRESS); | |
246 | memcpy(mac, addr, ETH_ALEN); | |
247 | } | |
248 | ||
fc19cbde SG |
249 | /* Send led command */ |
250 | static int | |
251 | il4965_send_led_cmd(struct il_priv *il, struct il_led_cmd *led_cmd) | |
252 | { | |
253 | struct il_host_cmd cmd = { | |
254 | .id = REPLY_LEDS_CMD, | |
255 | .len = sizeof(struct il_led_cmd), | |
256 | .data = led_cmd, | |
257 | .flags = CMD_ASYNC, | |
258 | .callback = NULL, | |
259 | }; | |
260 | u32 reg; | |
261 | ||
262 | reg = _il_rd(il, CSR_LED_REG); | |
263 | if (reg != (reg & CSR_LED_BSM_CTRL_MSK)) | |
264 | _il_wr(il, CSR_LED_REG, reg & CSR_LED_BSM_CTRL_MSK); | |
265 | ||
266 | return il_send_cmd(il, &cmd); | |
267 | } | |
268 | ||
269 | /* Set led register off */ | |
270 | void il4965_led_enable(struct il_priv *il) | |
271 | { | |
272 | _il_wr(il, CSR_LED_REG, CSR_LED_REG_TRUN_ON); | |
273 | } | |
274 | ||
275 | const struct il_led_ops il4965_led_ops = { | |
276 | .cmd = il4965_send_led_cmd, | |
277 | }; | |
278 | ||
46bc8d4b SG |
279 | static int il4965_send_tx_power(struct il_priv *il); |
280 | static int il4965_hw_get_temperature(struct il_priv *il); | |
4bc85c13 WYG |
281 | |
282 | /* Highest firmware API version supported */ | |
d3175167 | 283 | #define IL4965_UCODE_API_MAX 2 |
4bc85c13 WYG |
284 | |
285 | /* Lowest firmware API version supported */ | |
d3175167 | 286 | #define IL4965_UCODE_API_MIN 2 |
4bc85c13 | 287 | |
d3175167 SG |
288 | #define IL4965_FW_PRE "iwlwifi-4965-" |
289 | #define _IL4965_MODULE_FIRMWARE(api) IL4965_FW_PRE #api ".ucode" | |
290 | #define IL4965_MODULE_FIRMWARE(api) _IL4965_MODULE_FIRMWARE(api) | |
4bc85c13 WYG |
291 | |
292 | /* check contents of special bootstrap uCode SRAM */ | |
46bc8d4b | 293 | static int il4965_verify_bsm(struct il_priv *il) |
4bc85c13 | 294 | { |
46bc8d4b SG |
295 | __le32 *image = il->ucode_boot.v_addr; |
296 | u32 len = il->ucode_boot.len; | |
4bc85c13 WYG |
297 | u32 reg; |
298 | u32 val; | |
299 | ||
58de00a4 | 300 | D_INFO("Begin verify bsm\n"); |
4bc85c13 WYG |
301 | |
302 | /* verify BSM SRAM contents */ | |
db54eb57 | 303 | val = il_rd_prph(il, BSM_WR_DWCOUNT_REG); |
4bc85c13 WYG |
304 | for (reg = BSM_SRAM_LOWER_BOUND; |
305 | reg < BSM_SRAM_LOWER_BOUND + len; | |
306 | reg += sizeof(u32), image++) { | |
db54eb57 | 307 | val = il_rd_prph(il, reg); |
4bc85c13 | 308 | if (val != le32_to_cpu(*image)) { |
9406f797 | 309 | IL_ERR("BSM uCode verification failed at " |
4bc85c13 WYG |
310 | "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", |
311 | BSM_SRAM_LOWER_BOUND, | |
312 | reg - BSM_SRAM_LOWER_BOUND, len, | |
313 | val, le32_to_cpu(*image)); | |
314 | return -EIO; | |
315 | } | |
316 | } | |
317 | ||
58de00a4 | 318 | D_INFO("BSM bootstrap uCode image OK\n"); |
4bc85c13 WYG |
319 | |
320 | return 0; | |
321 | } | |
322 | ||
323 | /** | |
e2ebc833 | 324 | * il4965_load_bsm - Load bootstrap instructions |
4bc85c13 WYG |
325 | * |
326 | * BSM operation: | |
327 | * | |
328 | * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program | |
329 | * in special SRAM that does not power down during RFKILL. When powering back | |
330 | * up after power-saving sleeps (or during initial uCode load), the BSM loads | |
331 | * the bootstrap program into the on-board processor, and starts it. | |
332 | * | |
333 | * The bootstrap program loads (via DMA) instructions and data for a new | |
334 | * program from host DRAM locations indicated by the host driver in the | |
335 | * BSM_DRAM_* registers. Once the new program is loaded, it starts | |
336 | * automatically. | |
337 | * | |
338 | * When initializing the NIC, the host driver points the BSM to the | |
339 | * "initialize" uCode image. This uCode sets up some internal data, then | |
340 | * notifies host via "initialize alive" that it is complete. | |
341 | * | |
342 | * The host then replaces the BSM_DRAM_* pointer values to point to the | |
343 | * normal runtime uCode instructions and a backup uCode data cache buffer | |
344 | * (filled initially with starting data values for the on-board processor), | |
345 | * then triggers the "initialize" uCode to load and launch the runtime uCode, | |
346 | * which begins normal operation. | |
347 | * | |
348 | * When doing a power-save shutdown, runtime uCode saves data SRAM into | |
349 | * the backup data cache in DRAM before SRAM is powered down. | |
350 | * | |
351 | * When powering back up, the BSM loads the bootstrap program. This reloads | |
352 | * the runtime uCode instructions and the backup data cache into SRAM, | |
353 | * and re-launches the runtime uCode from where it left off. | |
354 | */ | |
46bc8d4b | 355 | static int il4965_load_bsm(struct il_priv *il) |
4bc85c13 | 356 | { |
46bc8d4b SG |
357 | __le32 *image = il->ucode_boot.v_addr; |
358 | u32 len = il->ucode_boot.len; | |
4bc85c13 WYG |
359 | dma_addr_t pinst; |
360 | dma_addr_t pdata; | |
361 | u32 inst_len; | |
362 | u32 data_len; | |
363 | int i; | |
364 | u32 done; | |
365 | u32 reg_offset; | |
366 | int ret; | |
367 | ||
58de00a4 | 368 | D_INFO("Begin load bsm\n"); |
4bc85c13 | 369 | |
46bc8d4b | 370 | il->ucode_type = UCODE_RT; |
4bc85c13 WYG |
371 | |
372 | /* make sure bootstrap program is no larger than BSM's SRAM size */ | |
d3175167 | 373 | if (len > IL49_MAX_BSM_SIZE) |
4bc85c13 WYG |
374 | return -EINVAL; |
375 | ||
376 | /* Tell bootstrap uCode where to find the "Initialize" uCode | |
377 | * in host DRAM ... host DRAM physical address bits 35:4 for 4965. | |
e2ebc833 | 378 | * NOTE: il_init_alive_start() will replace these values, |
4bc85c13 WYG |
379 | * after the "initialize" uCode has run, to point to |
380 | * runtime/protocol instructions and backup data cache. | |
381 | */ | |
46bc8d4b SG |
382 | pinst = il->ucode_init.p_addr >> 4; |
383 | pdata = il->ucode_init_data.p_addr >> 4; | |
384 | inst_len = il->ucode_init.len; | |
385 | data_len = il->ucode_init_data.len; | |
4bc85c13 | 386 | |
db54eb57 SG |
387 | il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst); |
388 | il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata); | |
389 | il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); | |
390 | il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); | |
4bc85c13 WYG |
391 | |
392 | /* Fill BSM memory with bootstrap instructions */ | |
393 | for (reg_offset = BSM_SRAM_LOWER_BOUND; | |
394 | reg_offset < BSM_SRAM_LOWER_BOUND + len; | |
395 | reg_offset += sizeof(u32), image++) | |
db54eb57 | 396 | _il_wr_prph(il, reg_offset, le32_to_cpu(*image)); |
4bc85c13 | 397 | |
46bc8d4b | 398 | ret = il4965_verify_bsm(il); |
4bc85c13 WYG |
399 | if (ret) |
400 | return ret; | |
401 | ||
402 | /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ | |
db54eb57 SG |
403 | il_wr_prph(il, BSM_WR_MEM_SRC_REG, 0x0); |
404 | il_wr_prph(il, | |
d3175167 | 405 | BSM_WR_MEM_DST_REG, IL49_RTC_INST_LOWER_BOUND); |
db54eb57 | 406 | il_wr_prph(il, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); |
4bc85c13 WYG |
407 | |
408 | /* Load bootstrap code into instruction SRAM now, | |
409 | * to prepare to load "initialize" uCode */ | |
db54eb57 | 410 | il_wr_prph(il, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START); |
4bc85c13 WYG |
411 | |
412 | /* Wait for load of bootstrap uCode to finish */ | |
413 | for (i = 0; i < 100; i++) { | |
db54eb57 | 414 | done = il_rd_prph(il, BSM_WR_CTRL_REG); |
4bc85c13 WYG |
415 | if (!(done & BSM_WR_CTRL_REG_BIT_START)) |
416 | break; | |
417 | udelay(10); | |
418 | } | |
419 | if (i < 100) | |
58de00a4 | 420 | D_INFO("BSM write complete, poll %d iterations\n", i); |
4bc85c13 | 421 | else { |
9406f797 | 422 | IL_ERR("BSM write did not complete!\n"); |
4bc85c13 WYG |
423 | return -EIO; |
424 | } | |
425 | ||
426 | /* Enable future boot loads whenever power management unit triggers it | |
427 | * (e.g. when powering back up after power-save shutdown) */ | |
db54eb57 | 428 | il_wr_prph(il, |
be663ab6 | 429 | BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN); |
4bc85c13 WYG |
430 | |
431 | ||
432 | return 0; | |
433 | } | |
434 | ||
435 | /** | |
e2ebc833 | 436 | * il4965_set_ucode_ptrs - Set uCode address location |
4bc85c13 WYG |
437 | * |
438 | * Tell initialization uCode where to find runtime uCode. | |
439 | * | |
440 | * BSM registers initially contain pointers to initialization uCode. | |
441 | * We need to replace them to load runtime uCode inst and data, | |
442 | * and to save runtime data when powering down. | |
443 | */ | |
46bc8d4b | 444 | static int il4965_set_ucode_ptrs(struct il_priv *il) |
4bc85c13 WYG |
445 | { |
446 | dma_addr_t pinst; | |
447 | dma_addr_t pdata; | |
448 | int ret = 0; | |
449 | ||
450 | /* bits 35:4 for 4965 */ | |
46bc8d4b SG |
451 | pinst = il->ucode_code.p_addr >> 4; |
452 | pdata = il->ucode_data_backup.p_addr >> 4; | |
4bc85c13 WYG |
453 | |
454 | /* Tell bootstrap uCode where to find image to load */ | |
db54eb57 SG |
455 | il_wr_prph(il, BSM_DRAM_INST_PTR_REG, pinst); |
456 | il_wr_prph(il, BSM_DRAM_DATA_PTR_REG, pdata); | |
457 | il_wr_prph(il, BSM_DRAM_DATA_BYTECOUNT_REG, | |
46bc8d4b | 458 | il->ucode_data.len); |
4bc85c13 WYG |
459 | |
460 | /* Inst byte count must be last to set up, bit 31 signals uCode | |
461 | * that all new ptr/size info is in place */ | |
db54eb57 | 462 | il_wr_prph(il, BSM_DRAM_INST_BYTECOUNT_REG, |
46bc8d4b | 463 | il->ucode_code.len | BSM_DRAM_INST_LOAD); |
58de00a4 | 464 | D_INFO("Runtime uCode pointers are set.\n"); |
4bc85c13 WYG |
465 | |
466 | return ret; | |
467 | } | |
468 | ||
469 | /** | |
e2ebc833 | 470 | * il4965_init_alive_start - Called after REPLY_ALIVE notification received |
4bc85c13 WYG |
471 | * |
472 | * Called after REPLY_ALIVE notification received from "initialize" uCode. | |
473 | * | |
474 | * The 4965 "initialize" ALIVE reply contains calibration data for: | |
46bc8d4b | 475 | * Voltage, temperature, and MIMO tx gain correction, now stored in il |
4bc85c13 WYG |
476 | * (3945 does not contain this data). |
477 | * | |
478 | * Tell "initialize" uCode to go ahead and load the runtime uCode. | |
479 | */ | |
46bc8d4b | 480 | static void il4965_init_alive_start(struct il_priv *il) |
4bc85c13 WYG |
481 | { |
482 | /* Bootstrap uCode has loaded initialize uCode ... verify inst image. | |
483 | * This is a paranoid check, because we would not have gotten the | |
484 | * "initialize" alive if code weren't properly loaded. */ | |
46bc8d4b | 485 | if (il4965_verify_ucode(il)) { |
4bc85c13 WYG |
486 | /* Runtime instruction load was bad; |
487 | * take it all the way back down so we can try again */ | |
58de00a4 | 488 | D_INFO("Bad \"initialize\" uCode load.\n"); |
4bc85c13 WYG |
489 | goto restart; |
490 | } | |
491 | ||
492 | /* Calculate temperature */ | |
46bc8d4b | 493 | il->temperature = il4965_hw_get_temperature(il); |
4bc85c13 WYG |
494 | |
495 | /* Send pointers to protocol/runtime uCode image ... init code will | |
496 | * load and launch runtime uCode, which will send us another "Alive" | |
497 | * notification. */ | |
58de00a4 | 498 | D_INFO("Initialization Alive received.\n"); |
46bc8d4b | 499 | if (il4965_set_ucode_ptrs(il)) { |
4bc85c13 WYG |
500 | /* Runtime instruction load won't happen; |
501 | * take it all the way back down so we can try again */ | |
58de00a4 | 502 | D_INFO("Couldn't set up uCode pointers.\n"); |
4bc85c13 WYG |
503 | goto restart; |
504 | } | |
505 | return; | |
506 | ||
507 | restart: | |
46bc8d4b | 508 | queue_work(il->workqueue, &il->restart); |
4bc85c13 WYG |
509 | } |
510 | ||
be663ab6 | 511 | static bool iw4965_is_ht40_channel(__le32 rxon_flags) |
4bc85c13 WYG |
512 | { |
513 | int chan_mod = le32_to_cpu(rxon_flags & RXON_FLG_CHANNEL_MODE_MSK) | |
514 | >> RXON_FLG_CHANNEL_MODE_POS; | |
232913b5 SG |
515 | return (chan_mod == CHANNEL_MODE_PURE_40 || |
516 | chan_mod == CHANNEL_MODE_MIXED); | |
4bc85c13 WYG |
517 | } |
518 | ||
46bc8d4b | 519 | static void il4965_nic_config(struct il_priv *il) |
4bc85c13 WYG |
520 | { |
521 | unsigned long flags; | |
522 | u16 radio_cfg; | |
523 | ||
46bc8d4b | 524 | spin_lock_irqsave(&il->lock, flags); |
4bc85c13 | 525 | |
46bc8d4b | 526 | radio_cfg = il_eeprom_query16(il, EEPROM_RADIO_CONFIG); |
4bc85c13 WYG |
527 | |
528 | /* write radio config values to register */ | |
529 | if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX) | |
46bc8d4b | 530 | il_set_bit(il, CSR_HW_IF_CONFIG_REG, |
4bc85c13 WYG |
531 | EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | |
532 | EEPROM_RF_CFG_STEP_MSK(radio_cfg) | | |
533 | EEPROM_RF_CFG_DASH_MSK(radio_cfg)); | |
534 | ||
535 | /* set CSR_HW_CONFIG_REG for uCode use */ | |
46bc8d4b | 536 | il_set_bit(il, CSR_HW_IF_CONFIG_REG, |
4bc85c13 WYG |
537 | CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | |
538 | CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); | |
539 | ||
46bc8d4b SG |
540 | il->calib_info = (struct il_eeprom_calib_info *) |
541 | il_eeprom_query_addr(il, | |
be663ab6 | 542 | EEPROM_4965_CALIB_TXPOWER_OFFSET); |
4bc85c13 | 543 | |
46bc8d4b | 544 | spin_unlock_irqrestore(&il->lock, flags); |
4bc85c13 WYG |
545 | } |
546 | ||
547 | /* Reset differential Rx gains in NIC to prepare for chain noise calibration. | |
548 | * Called after every association, but this runs only once! | |
549 | * ... once chain noise is calibrated the first time, it's good forever. */ | |
46bc8d4b | 550 | static void il4965_chain_noise_reset(struct il_priv *il) |
4bc85c13 | 551 | { |
46bc8d4b | 552 | struct il_chain_noise_data *data = &(il->chain_noise_data); |
4bc85c13 | 553 | |
232913b5 | 554 | if (data->state == IL_CHAIN_NOISE_ALIVE && |
46bc8d4b | 555 | il_is_any_associated(il)) { |
e2ebc833 | 556 | struct il_calib_diff_gain_cmd cmd; |
4bc85c13 WYG |
557 | |
558 | /* clear data for chain noise calibration algorithm */ | |
559 | data->chain_noise_a = 0; | |
560 | data->chain_noise_b = 0; | |
561 | data->chain_noise_c = 0; | |
562 | data->chain_signal_a = 0; | |
563 | data->chain_signal_b = 0; | |
564 | data->chain_signal_c = 0; | |
565 | data->beacon_count = 0; | |
566 | ||
567 | memset(&cmd, 0, sizeof(cmd)); | |
e2ebc833 | 568 | cmd.hdr.op_code = IL_PHY_CALIBRATE_DIFF_GAIN_CMD; |
4bc85c13 WYG |
569 | cmd.diff_gain_a = 0; |
570 | cmd.diff_gain_b = 0; | |
571 | cmd.diff_gain_c = 0; | |
46bc8d4b | 572 | if (il_send_cmd_pdu(il, REPLY_PHY_CALIBRATION_CMD, |
4bc85c13 | 573 | sizeof(cmd), &cmd)) |
9406f797 | 574 | IL_ERR( |
4bc85c13 | 575 | "Could not send REPLY_PHY_CALIBRATION_CMD\n"); |
e2ebc833 | 576 | data->state = IL_CHAIN_NOISE_ACCUMULATE; |
58de00a4 | 577 | D_CALIB("Run chain_noise_calibrate\n"); |
4bc85c13 WYG |
578 | } |
579 | } | |
580 | ||
e2ebc833 | 581 | static struct il_sensitivity_ranges il4965_sensitivity = { |
4bc85c13 WYG |
582 | .min_nrg_cck = 97, |
583 | .max_nrg_cck = 0, /* not used, set to 0 */ | |
584 | ||
585 | .auto_corr_min_ofdm = 85, | |
586 | .auto_corr_min_ofdm_mrc = 170, | |
587 | .auto_corr_min_ofdm_x1 = 105, | |
588 | .auto_corr_min_ofdm_mrc_x1 = 220, | |
589 | ||
590 | .auto_corr_max_ofdm = 120, | |
591 | .auto_corr_max_ofdm_mrc = 210, | |
592 | .auto_corr_max_ofdm_x1 = 140, | |
593 | .auto_corr_max_ofdm_mrc_x1 = 270, | |
594 | ||
595 | .auto_corr_min_cck = 125, | |
596 | .auto_corr_max_cck = 200, | |
597 | .auto_corr_min_cck_mrc = 200, | |
598 | .auto_corr_max_cck_mrc = 400, | |
599 | ||
600 | .nrg_th_cck = 100, | |
601 | .nrg_th_ofdm = 100, | |
602 | ||
603 | .barker_corr_th_min = 190, | |
604 | .barker_corr_th_min_mrc = 390, | |
605 | .nrg_th_cca = 62, | |
606 | }; | |
607 | ||
46bc8d4b | 608 | static void il4965_set_ct_threshold(struct il_priv *il) |
4bc85c13 WYG |
609 | { |
610 | /* want Kelvin */ | |
46bc8d4b | 611 | il->hw_params.ct_kill_threshold = |
4bc85c13 WYG |
612 | CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY); |
613 | } | |
614 | ||
615 | /** | |
e2ebc833 | 616 | * il4965_hw_set_hw_params |
4bc85c13 WYG |
617 | * |
618 | * Called when initializing driver | |
619 | */ | |
46bc8d4b | 620 | static int il4965_hw_set_hw_params(struct il_priv *il) |
4bc85c13 | 621 | { |
46bc8d4b | 622 | if (il->cfg->mod_params->num_of_queues >= IL_MIN_NUM_QUEUES && |
d3175167 | 623 | il->cfg->mod_params->num_of_queues <= IL49_NUM_QUEUES) |
46bc8d4b SG |
624 | il->cfg->base_params->num_of_queues = |
625 | il->cfg->mod_params->num_of_queues; | |
626 | ||
627 | il->hw_params.max_txq_num = il->cfg->base_params->num_of_queues; | |
628 | il->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM; | |
629 | il->hw_params.scd_bc_tbls_size = | |
630 | il->cfg->base_params->num_of_queues * | |
e2ebc833 | 631 | sizeof(struct il4965_scd_bc_tbl); |
46bc8d4b | 632 | il->hw_params.tfd_size = sizeof(struct il_tfd); |
d3175167 | 633 | il->hw_params.max_stations = IL4965_STATION_COUNT; |
7c2cde2e | 634 | il->ctx.bcast_sta_id = IL4965_BROADCAST_ID; |
d3175167 SG |
635 | il->hw_params.max_data_size = IL49_RTC_DATA_SIZE; |
636 | il->hw_params.max_inst_size = IL49_RTC_INST_SIZE; | |
46bc8d4b SG |
637 | il->hw_params.max_bsm_size = BSM_SRAM_SIZE; |
638 | il->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ); | |
4bc85c13 | 639 | |
46bc8d4b | 640 | il->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR; |
4bc85c13 | 641 | |
46bc8d4b SG |
642 | il->hw_params.tx_chains_num = il4965_num_of_ant(il->cfg->valid_tx_ant); |
643 | il->hw_params.rx_chains_num = il4965_num_of_ant(il->cfg->valid_rx_ant); | |
644 | il->hw_params.valid_tx_ant = il->cfg->valid_tx_ant; | |
645 | il->hw_params.valid_rx_ant = il->cfg->valid_rx_ant; | |
4bc85c13 | 646 | |
46bc8d4b | 647 | il4965_set_ct_threshold(il); |
4bc85c13 | 648 | |
46bc8d4b | 649 | il->hw_params.sens = &il4965_sensitivity; |
d3175167 | 650 | il->hw_params.beacon_time_tsf_bits = IL4965_EXT_BEACON_TIME_POS; |
4bc85c13 WYG |
651 | |
652 | return 0; | |
653 | } | |
654 | ||
e2ebc833 | 655 | static s32 il4965_math_div_round(s32 num, s32 denom, s32 *res) |
4bc85c13 WYG |
656 | { |
657 | s32 sign = 1; | |
658 | ||
659 | if (num < 0) { | |
660 | sign = -sign; | |
661 | num = -num; | |
662 | } | |
663 | if (denom < 0) { | |
664 | sign = -sign; | |
665 | denom = -denom; | |
666 | } | |
667 | *res = 1; | |
668 | *res = ((num * 2 + denom) / (denom * 2)) * sign; | |
669 | ||
670 | return 1; | |
671 | } | |
672 | ||
673 | /** | |
e2ebc833 | 674 | * il4965_get_voltage_compensation - Power supply voltage comp for txpower |
4bc85c13 WYG |
675 | * |
676 | * Determines power supply voltage compensation for txpower calculations. | |
0c2c8852 | 677 | * Returns number of 1/2-dB steps to subtract from gain table idx, |
4bc85c13 WYG |
678 | * to compensate for difference between power supply voltage during |
679 | * factory measurements, vs. current power supply voltage. | |
680 | * | |
681 | * Voltage indication is higher for lower voltage. | |
0c2c8852 | 682 | * Lower voltage requires more gain (lower gain table idx). |
4bc85c13 | 683 | */ |
e2ebc833 | 684 | static s32 il4965_get_voltage_compensation(s32 eeprom_voltage, |
4bc85c13 WYG |
685 | s32 current_voltage) |
686 | { | |
687 | s32 comp = 0; | |
688 | ||
232913b5 SG |
689 | if (TX_POWER_IL_ILLEGAL_VOLTAGE == eeprom_voltage || |
690 | TX_POWER_IL_ILLEGAL_VOLTAGE == current_voltage) | |
4bc85c13 WYG |
691 | return 0; |
692 | ||
e2ebc833 SG |
693 | il4965_math_div_round(current_voltage - eeprom_voltage, |
694 | TX_POWER_IL_VOLTAGE_CODES_PER_03V, &comp); | |
4bc85c13 WYG |
695 | |
696 | if (current_voltage > eeprom_voltage) | |
697 | comp *= 2; | |
698 | if ((comp < -2) || (comp > 2)) | |
699 | comp = 0; | |
700 | ||
701 | return comp; | |
702 | } | |
703 | ||
e2ebc833 | 704 | static s32 il4965_get_tx_atten_grp(u16 channel) |
4bc85c13 | 705 | { |
e2ebc833 SG |
706 | if (channel >= CALIB_IL_TX_ATTEN_GR5_FCH && |
707 | channel <= CALIB_IL_TX_ATTEN_GR5_LCH) | |
4bc85c13 WYG |
708 | return CALIB_CH_GROUP_5; |
709 | ||
e2ebc833 SG |
710 | if (channel >= CALIB_IL_TX_ATTEN_GR1_FCH && |
711 | channel <= CALIB_IL_TX_ATTEN_GR1_LCH) | |
4bc85c13 WYG |
712 | return CALIB_CH_GROUP_1; |
713 | ||
e2ebc833 SG |
714 | if (channel >= CALIB_IL_TX_ATTEN_GR2_FCH && |
715 | channel <= CALIB_IL_TX_ATTEN_GR2_LCH) | |
4bc85c13 WYG |
716 | return CALIB_CH_GROUP_2; |
717 | ||
e2ebc833 SG |
718 | if (channel >= CALIB_IL_TX_ATTEN_GR3_FCH && |
719 | channel <= CALIB_IL_TX_ATTEN_GR3_LCH) | |
4bc85c13 WYG |
720 | return CALIB_CH_GROUP_3; |
721 | ||
e2ebc833 SG |
722 | if (channel >= CALIB_IL_TX_ATTEN_GR4_FCH && |
723 | channel <= CALIB_IL_TX_ATTEN_GR4_LCH) | |
4bc85c13 WYG |
724 | return CALIB_CH_GROUP_4; |
725 | ||
8e638188 | 726 | return -EINVAL; |
4bc85c13 WYG |
727 | } |
728 | ||
46bc8d4b | 729 | static u32 il4965_get_sub_band(const struct il_priv *il, u32 channel) |
4bc85c13 WYG |
730 | { |
731 | s32 b = -1; | |
732 | ||
733 | for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) { | |
46bc8d4b | 734 | if (il->calib_info->band_info[b].ch_from == 0) |
4bc85c13 WYG |
735 | continue; |
736 | ||
232913b5 SG |
737 | if (channel >= il->calib_info->band_info[b].ch_from && |
738 | channel <= il->calib_info->band_info[b].ch_to) | |
4bc85c13 WYG |
739 | break; |
740 | } | |
741 | ||
742 | return b; | |
743 | } | |
744 | ||
e2ebc833 | 745 | static s32 il4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2) |
4bc85c13 WYG |
746 | { |
747 | s32 val; | |
748 | ||
749 | if (x2 == x1) | |
750 | return y1; | |
751 | else { | |
e2ebc833 | 752 | il4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val); |
4bc85c13 WYG |
753 | return val + y2; |
754 | } | |
755 | } | |
756 | ||
757 | /** | |
e2ebc833 | 758 | * il4965_interpolate_chan - Interpolate factory measurements for one channel |
4bc85c13 WYG |
759 | * |
760 | * Interpolates factory measurements from the two sample channels within a | |
761 | * sub-band, to apply to channel of interest. Interpolation is proportional to | |
762 | * differences in channel frequencies, which is proportional to differences | |
763 | * in channel number. | |
764 | */ | |
46bc8d4b | 765 | static int il4965_interpolate_chan(struct il_priv *il, u32 channel, |
e2ebc833 | 766 | struct il_eeprom_calib_ch_info *chan_info) |
4bc85c13 WYG |
767 | { |
768 | s32 s = -1; | |
769 | u32 c; | |
770 | u32 m; | |
e2ebc833 SG |
771 | const struct il_eeprom_calib_measure *m1; |
772 | const struct il_eeprom_calib_measure *m2; | |
773 | struct il_eeprom_calib_measure *omeas; | |
4bc85c13 WYG |
774 | u32 ch_i1; |
775 | u32 ch_i2; | |
776 | ||
46bc8d4b | 777 | s = il4965_get_sub_band(il, channel); |
4bc85c13 | 778 | if (s >= EEPROM_TX_POWER_BANDS) { |
9406f797 | 779 | IL_ERR("Tx Power can not find channel %d\n", channel); |
4bc85c13 WYG |
780 | return -1; |
781 | } | |
782 | ||
46bc8d4b SG |
783 | ch_i1 = il->calib_info->band_info[s].ch1.ch_num; |
784 | ch_i2 = il->calib_info->band_info[s].ch2.ch_num; | |
4bc85c13 WYG |
785 | chan_info->ch_num = (u8) channel; |
786 | ||
58de00a4 | 787 | D_TXPOWER("channel %d subband %d factory cal ch %d & %d\n", |
4bc85c13 WYG |
788 | channel, s, ch_i1, ch_i2); |
789 | ||
790 | for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) { | |
791 | for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) { | |
46bc8d4b | 792 | m1 = &(il->calib_info->band_info[s].ch1. |
4bc85c13 | 793 | measurements[c][m]); |
46bc8d4b | 794 | m2 = &(il->calib_info->band_info[s].ch2. |
4bc85c13 WYG |
795 | measurements[c][m]); |
796 | omeas = &(chan_info->measurements[c][m]); | |
797 | ||
798 | omeas->actual_pow = | |
e2ebc833 | 799 | (u8) il4965_interpolate_value(channel, ch_i1, |
4bc85c13 WYG |
800 | m1->actual_pow, |
801 | ch_i2, | |
802 | m2->actual_pow); | |
803 | omeas->gain_idx = | |
e2ebc833 | 804 | (u8) il4965_interpolate_value(channel, ch_i1, |
4bc85c13 WYG |
805 | m1->gain_idx, ch_i2, |
806 | m2->gain_idx); | |
807 | omeas->temperature = | |
e2ebc833 | 808 | (u8) il4965_interpolate_value(channel, ch_i1, |
4bc85c13 WYG |
809 | m1->temperature, |
810 | ch_i2, | |
811 | m2->temperature); | |
812 | omeas->pa_det = | |
e2ebc833 | 813 | (s8) il4965_interpolate_value(channel, ch_i1, |
4bc85c13 WYG |
814 | m1->pa_det, ch_i2, |
815 | m2->pa_det); | |
816 | ||
58de00a4 | 817 | D_TXPOWER( |
4bc85c13 WYG |
818 | "chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m, |
819 | m1->actual_pow, m2->actual_pow, omeas->actual_pow); | |
58de00a4 | 820 | D_TXPOWER( |
4bc85c13 WYG |
821 | "chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m, |
822 | m1->gain_idx, m2->gain_idx, omeas->gain_idx); | |
58de00a4 | 823 | D_TXPOWER( |
4bc85c13 WYG |
824 | "chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m, |
825 | m1->pa_det, m2->pa_det, omeas->pa_det); | |
58de00a4 | 826 | D_TXPOWER( |
4bc85c13 WYG |
827 | "chain %d meas %d T1=%d T2=%d T=%d\n", c, m, |
828 | m1->temperature, m2->temperature, | |
829 | omeas->temperature); | |
830 | } | |
831 | } | |
832 | ||
833 | return 0; | |
834 | } | |
835 | ||
836 | /* bit-rate-dependent table to prevent Tx distortion, in half-dB units, | |
837 | * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */ | |
838 | static s32 back_off_table[] = { | |
839 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */ | |
840 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */ | |
841 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */ | |
842 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */ | |
843 | 10 /* CCK */ | |
844 | }; | |
845 | ||
846 | /* Thermal compensation values for txpower for various frequency ranges ... | |
847 | * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */ | |
e2ebc833 | 848 | static struct il4965_txpower_comp_entry { |
4bc85c13 WYG |
849 | s32 degrees_per_05db_a; |
850 | s32 degrees_per_05db_a_denom; | |
851 | } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = { | |
852 | {9, 2}, /* group 0 5.2, ch 34-43 */ | |
853 | {4, 1}, /* group 1 5.2, ch 44-70 */ | |
854 | {4, 1}, /* group 2 5.2, ch 71-124 */ | |
855 | {4, 1}, /* group 3 5.2, ch 125-200 */ | |
856 | {3, 1} /* group 4 2.4, ch all */ | |
857 | }; | |
858 | ||
0c2c8852 | 859 | static s32 get_min_power_idx(s32 rate_power_idx, u32 band) |
4bc85c13 WYG |
860 | { |
861 | if (!band) { | |
0c2c8852 | 862 | if ((rate_power_idx & 7) <= 4) |
2d09b062 | 863 | return MIN_TX_GAIN_IDX_52GHZ_EXT; |
4bc85c13 | 864 | } |
2d09b062 | 865 | return MIN_TX_GAIN_IDX; |
4bc85c13 WYG |
866 | } |
867 | ||
868 | struct gain_entry { | |
869 | u8 dsp; | |
870 | u8 radio; | |
871 | }; | |
872 | ||
873 | static const struct gain_entry gain_table[2][108] = { | |
0c2c8852 | 874 | /* 5.2GHz power gain idx table */ |
4bc85c13 WYG |
875 | { |
876 | {123, 0x3F}, /* highest txpower */ | |
877 | {117, 0x3F}, | |
878 | {110, 0x3F}, | |
879 | {104, 0x3F}, | |
880 | {98, 0x3F}, | |
881 | {110, 0x3E}, | |
882 | {104, 0x3E}, | |
883 | {98, 0x3E}, | |
884 | {110, 0x3D}, | |
885 | {104, 0x3D}, | |
886 | {98, 0x3D}, | |
887 | {110, 0x3C}, | |
888 | {104, 0x3C}, | |
889 | {98, 0x3C}, | |
890 | {110, 0x3B}, | |
891 | {104, 0x3B}, | |
892 | {98, 0x3B}, | |
893 | {110, 0x3A}, | |
894 | {104, 0x3A}, | |
895 | {98, 0x3A}, | |
896 | {110, 0x39}, | |
897 | {104, 0x39}, | |
898 | {98, 0x39}, | |
899 | {110, 0x38}, | |
900 | {104, 0x38}, | |
901 | {98, 0x38}, | |
902 | {110, 0x37}, | |
903 | {104, 0x37}, | |
904 | {98, 0x37}, | |
905 | {110, 0x36}, | |
906 | {104, 0x36}, | |
907 | {98, 0x36}, | |
908 | {110, 0x35}, | |
909 | {104, 0x35}, | |
910 | {98, 0x35}, | |
911 | {110, 0x34}, | |
912 | {104, 0x34}, | |
913 | {98, 0x34}, | |
914 | {110, 0x33}, | |
915 | {104, 0x33}, | |
916 | {98, 0x33}, | |
917 | {110, 0x32}, | |
918 | {104, 0x32}, | |
919 | {98, 0x32}, | |
920 | {110, 0x31}, | |
921 | {104, 0x31}, | |
922 | {98, 0x31}, | |
923 | {110, 0x30}, | |
924 | {104, 0x30}, | |
925 | {98, 0x30}, | |
926 | {110, 0x25}, | |
927 | {104, 0x25}, | |
928 | {98, 0x25}, | |
929 | {110, 0x24}, | |
930 | {104, 0x24}, | |
931 | {98, 0x24}, | |
932 | {110, 0x23}, | |
933 | {104, 0x23}, | |
934 | {98, 0x23}, | |
935 | {110, 0x22}, | |
936 | {104, 0x18}, | |
937 | {98, 0x18}, | |
938 | {110, 0x17}, | |
939 | {104, 0x17}, | |
940 | {98, 0x17}, | |
941 | {110, 0x16}, | |
942 | {104, 0x16}, | |
943 | {98, 0x16}, | |
944 | {110, 0x15}, | |
945 | {104, 0x15}, | |
946 | {98, 0x15}, | |
947 | {110, 0x14}, | |
948 | {104, 0x14}, | |
949 | {98, 0x14}, | |
950 | {110, 0x13}, | |
951 | {104, 0x13}, | |
952 | {98, 0x13}, | |
953 | {110, 0x12}, | |
954 | {104, 0x08}, | |
955 | {98, 0x08}, | |
956 | {110, 0x07}, | |
957 | {104, 0x07}, | |
958 | {98, 0x07}, | |
959 | {110, 0x06}, | |
960 | {104, 0x06}, | |
961 | {98, 0x06}, | |
962 | {110, 0x05}, | |
963 | {104, 0x05}, | |
964 | {98, 0x05}, | |
965 | {110, 0x04}, | |
966 | {104, 0x04}, | |
967 | {98, 0x04}, | |
968 | {110, 0x03}, | |
969 | {104, 0x03}, | |
970 | {98, 0x03}, | |
971 | {110, 0x02}, | |
972 | {104, 0x02}, | |
973 | {98, 0x02}, | |
974 | {110, 0x01}, | |
975 | {104, 0x01}, | |
976 | {98, 0x01}, | |
977 | {110, 0x00}, | |
978 | {104, 0x00}, | |
979 | {98, 0x00}, | |
980 | {93, 0x00}, | |
981 | {88, 0x00}, | |
982 | {83, 0x00}, | |
983 | {78, 0x00}, | |
984 | }, | |
0c2c8852 | 985 | /* 2.4GHz power gain idx table */ |
4bc85c13 WYG |
986 | { |
987 | {110, 0x3f}, /* highest txpower */ | |
988 | {104, 0x3f}, | |
989 | {98, 0x3f}, | |
990 | {110, 0x3e}, | |
991 | {104, 0x3e}, | |
992 | {98, 0x3e}, | |
993 | {110, 0x3d}, | |
994 | {104, 0x3d}, | |
995 | {98, 0x3d}, | |
996 | {110, 0x3c}, | |
997 | {104, 0x3c}, | |
998 | {98, 0x3c}, | |
999 | {110, 0x3b}, | |
1000 | {104, 0x3b}, | |
1001 | {98, 0x3b}, | |
1002 | {110, 0x3a}, | |
1003 | {104, 0x3a}, | |
1004 | {98, 0x3a}, | |
1005 | {110, 0x39}, | |
1006 | {104, 0x39}, | |
1007 | {98, 0x39}, | |
1008 | {110, 0x38}, | |
1009 | {104, 0x38}, | |
1010 | {98, 0x38}, | |
1011 | {110, 0x37}, | |
1012 | {104, 0x37}, | |
1013 | {98, 0x37}, | |
1014 | {110, 0x36}, | |
1015 | {104, 0x36}, | |
1016 | {98, 0x36}, | |
1017 | {110, 0x35}, | |
1018 | {104, 0x35}, | |
1019 | {98, 0x35}, | |
1020 | {110, 0x34}, | |
1021 | {104, 0x34}, | |
1022 | {98, 0x34}, | |
1023 | {110, 0x33}, | |
1024 | {104, 0x33}, | |
1025 | {98, 0x33}, | |
1026 | {110, 0x32}, | |
1027 | {104, 0x32}, | |
1028 | {98, 0x32}, | |
1029 | {110, 0x31}, | |
1030 | {104, 0x31}, | |
1031 | {98, 0x31}, | |
1032 | {110, 0x30}, | |
1033 | {104, 0x30}, | |
1034 | {98, 0x30}, | |
1035 | {110, 0x6}, | |
1036 | {104, 0x6}, | |
1037 | {98, 0x6}, | |
1038 | {110, 0x5}, | |
1039 | {104, 0x5}, | |
1040 | {98, 0x5}, | |
1041 | {110, 0x4}, | |
1042 | {104, 0x4}, | |
1043 | {98, 0x4}, | |
1044 | {110, 0x3}, | |
1045 | {104, 0x3}, | |
1046 | {98, 0x3}, | |
1047 | {110, 0x2}, | |
1048 | {104, 0x2}, | |
1049 | {98, 0x2}, | |
1050 | {110, 0x1}, | |
1051 | {104, 0x1}, | |
1052 | {98, 0x1}, | |
1053 | {110, 0x0}, | |
1054 | {104, 0x0}, | |
1055 | {98, 0x0}, | |
1056 | {97, 0}, | |
1057 | {96, 0}, | |
1058 | {95, 0}, | |
1059 | {94, 0}, | |
1060 | {93, 0}, | |
1061 | {92, 0}, | |
1062 | {91, 0}, | |
1063 | {90, 0}, | |
1064 | {89, 0}, | |
1065 | {88, 0}, | |
1066 | {87, 0}, | |
1067 | {86, 0}, | |
1068 | {85, 0}, | |
1069 | {84, 0}, | |
1070 | {83, 0}, | |
1071 | {82, 0}, | |
1072 | {81, 0}, | |
1073 | {80, 0}, | |
1074 | {79, 0}, | |
1075 | {78, 0}, | |
1076 | {77, 0}, | |
1077 | {76, 0}, | |
1078 | {75, 0}, | |
1079 | {74, 0}, | |
1080 | {73, 0}, | |
1081 | {72, 0}, | |
1082 | {71, 0}, | |
1083 | {70, 0}, | |
1084 | {69, 0}, | |
1085 | {68, 0}, | |
1086 | {67, 0}, | |
1087 | {66, 0}, | |
1088 | {65, 0}, | |
1089 | {64, 0}, | |
1090 | {63, 0}, | |
1091 | {62, 0}, | |
1092 | {61, 0}, | |
1093 | {60, 0}, | |
1094 | {59, 0}, | |
1095 | } | |
1096 | }; | |
1097 | ||
46bc8d4b | 1098 | static int il4965_fill_txpower_tbl(struct il_priv *il, u8 band, u16 channel, |
4bc85c13 | 1099 | u8 is_ht40, u8 ctrl_chan_high, |
e2ebc833 | 1100 | struct il4965_tx_power_db *tx_power_tbl) |
4bc85c13 WYG |
1101 | { |
1102 | u8 saturation_power; | |
1103 | s32 target_power; | |
1104 | s32 user_target_power; | |
1105 | s32 power_limit; | |
1106 | s32 current_temp; | |
1107 | s32 reg_limit; | |
1108 | s32 current_regulatory; | |
1109 | s32 txatten_grp = CALIB_CH_GROUP_MAX; | |
1110 | int i; | |
1111 | int c; | |
e2ebc833 SG |
1112 | const struct il_channel_info *ch_info = NULL; |
1113 | struct il_eeprom_calib_ch_info ch_eeprom_info; | |
1114 | const struct il_eeprom_calib_measure *measurement; | |
4bc85c13 WYG |
1115 | s16 voltage; |
1116 | s32 init_voltage; | |
1117 | s32 voltage_compensation; | |
1118 | s32 degrees_per_05db_num; | |
1119 | s32 degrees_per_05db_denom; | |
1120 | s32 factory_temp; | |
1121 | s32 temperature_comp[2]; | |
0c2c8852 | 1122 | s32 factory_gain_idx[2]; |
4bc85c13 | 1123 | s32 factory_actual_pwr[2]; |
0c2c8852 | 1124 | s32 power_idx; |
4bc85c13 WYG |
1125 | |
1126 | /* tx_power_user_lmt is in dBm, convert to half-dBm (half-dB units | |
0c2c8852 | 1127 | * are used for idxing into txpower table) */ |
46bc8d4b | 1128 | user_target_power = 2 * il->tx_power_user_lmt; |
4bc85c13 WYG |
1129 | |
1130 | /* Get current (RXON) channel, band, width */ | |
58de00a4 | 1131 | D_TXPOWER("chan %d band %d is_ht40 %d\n", channel, band, |
4bc85c13 WYG |
1132 | is_ht40); |
1133 | ||
46bc8d4b | 1134 | ch_info = il_get_channel_info(il, il->band, channel); |
4bc85c13 | 1135 | |
e2ebc833 | 1136 | if (!il_is_channel_valid(ch_info)) |
4bc85c13 WYG |
1137 | return -EINVAL; |
1138 | ||
1139 | /* get txatten group, used to select 1) thermal txpower adjustment | |
1140 | * and 2) mimo txpower balance between Tx chains. */ | |
e2ebc833 | 1141 | txatten_grp = il4965_get_tx_atten_grp(channel); |
4bc85c13 | 1142 | if (txatten_grp < 0) { |
9406f797 | 1143 | IL_ERR("Can't find txatten group for channel %d.\n", |
4bc85c13 | 1144 | channel); |
5c30c76e | 1145 | return txatten_grp; |
4bc85c13 WYG |
1146 | } |
1147 | ||
58de00a4 | 1148 | D_TXPOWER("channel %d belongs to txatten group %d\n", |
4bc85c13 WYG |
1149 | channel, txatten_grp); |
1150 | ||
1151 | if (is_ht40) { | |
1152 | if (ctrl_chan_high) | |
1153 | channel -= 2; | |
1154 | else | |
1155 | channel += 2; | |
1156 | } | |
1157 | ||
1158 | /* hardware txpower limits ... | |
1159 | * saturation (clipping distortion) txpowers are in half-dBm */ | |
1160 | if (band) | |
46bc8d4b | 1161 | saturation_power = il->calib_info->saturation_power24; |
4bc85c13 | 1162 | else |
46bc8d4b | 1163 | saturation_power = il->calib_info->saturation_power52; |
4bc85c13 | 1164 | |
e2ebc833 SG |
1165 | if (saturation_power < IL_TX_POWER_SATURATION_MIN || |
1166 | saturation_power > IL_TX_POWER_SATURATION_MAX) { | |
4bc85c13 | 1167 | if (band) |
e2ebc833 | 1168 | saturation_power = IL_TX_POWER_DEFAULT_SATURATION_24; |
4bc85c13 | 1169 | else |
e2ebc833 | 1170 | saturation_power = IL_TX_POWER_DEFAULT_SATURATION_52; |
4bc85c13 WYG |
1171 | } |
1172 | ||
1173 | /* regulatory txpower limits ... reg_limit values are in half-dBm, | |
1174 | * max_power_avg values are in dBm, convert * 2 */ | |
1175 | if (is_ht40) | |
1176 | reg_limit = ch_info->ht40_max_power_avg * 2; | |
1177 | else | |
1178 | reg_limit = ch_info->max_power_avg * 2; | |
1179 | ||
e2ebc833 SG |
1180 | if ((reg_limit < IL_TX_POWER_REGULATORY_MIN) || |
1181 | (reg_limit > IL_TX_POWER_REGULATORY_MAX)) { | |
4bc85c13 | 1182 | if (band) |
e2ebc833 | 1183 | reg_limit = IL_TX_POWER_DEFAULT_REGULATORY_24; |
4bc85c13 | 1184 | else |
e2ebc833 | 1185 | reg_limit = IL_TX_POWER_DEFAULT_REGULATORY_52; |
4bc85c13 WYG |
1186 | } |
1187 | ||
1188 | /* Interpolate txpower calibration values for this channel, | |
1189 | * based on factory calibration tests on spaced channels. */ | |
46bc8d4b | 1190 | il4965_interpolate_chan(il, channel, &ch_eeprom_info); |
4bc85c13 WYG |
1191 | |
1192 | /* calculate tx gain adjustment based on power supply voltage */ | |
46bc8d4b SG |
1193 | voltage = le16_to_cpu(il->calib_info->voltage); |
1194 | init_voltage = (s32)le32_to_cpu(il->card_alive_init.voltage); | |
4bc85c13 | 1195 | voltage_compensation = |
e2ebc833 | 1196 | il4965_get_voltage_compensation(voltage, init_voltage); |
4bc85c13 | 1197 | |
58de00a4 | 1198 | D_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n", |
4bc85c13 WYG |
1199 | init_voltage, |
1200 | voltage, voltage_compensation); | |
1201 | ||
1202 | /* get current temperature (Celsius) */ | |
46bc8d4b SG |
1203 | current_temp = max(il->temperature, IL_TX_POWER_TEMPERATURE_MIN); |
1204 | current_temp = min(il->temperature, IL_TX_POWER_TEMPERATURE_MAX); | |
4bc85c13 WYG |
1205 | current_temp = KELVIN_TO_CELSIUS(current_temp); |
1206 | ||
1207 | /* select thermal txpower adjustment params, based on channel group | |
1208 | * (same frequency group used for mimo txatten adjustment) */ | |
1209 | degrees_per_05db_num = | |
1210 | tx_power_cmp_tble[txatten_grp].degrees_per_05db_a; | |
1211 | degrees_per_05db_denom = | |
1212 | tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom; | |
1213 | ||
1214 | /* get per-chain txpower values from factory measurements */ | |
1215 | for (c = 0; c < 2; c++) { | |
1216 | measurement = &ch_eeprom_info.measurements[c][1]; | |
1217 | ||
1218 | /* txgain adjustment (in half-dB steps) based on difference | |
1219 | * between factory and current temperature */ | |
1220 | factory_temp = measurement->temperature; | |
e2ebc833 | 1221 | il4965_math_div_round((current_temp - factory_temp) * |
4bc85c13 WYG |
1222 | degrees_per_05db_denom, |
1223 | degrees_per_05db_num, | |
1224 | &temperature_comp[c]); | |
1225 | ||
0c2c8852 | 1226 | factory_gain_idx[c] = measurement->gain_idx; |
4bc85c13 WYG |
1227 | factory_actual_pwr[c] = measurement->actual_pow; |
1228 | ||
58de00a4 SG |
1229 | D_TXPOWER("chain = %d\n", c); |
1230 | D_TXPOWER("fctry tmp %d, " | |
4bc85c13 WYG |
1231 | "curr tmp %d, comp %d steps\n", |
1232 | factory_temp, current_temp, | |
1233 | temperature_comp[c]); | |
1234 | ||
58de00a4 | 1235 | D_TXPOWER("fctry idx %d, fctry pwr %d\n", |
0c2c8852 | 1236 | factory_gain_idx[c], |
4bc85c13 WYG |
1237 | factory_actual_pwr[c]); |
1238 | } | |
1239 | ||
1240 | /* for each of 33 bit-rates (including 1 for CCK) */ | |
3b98c7f4 | 1241 | for (i = 0; i < POWER_TBL_NUM_ENTRIES; i++) { |
4bc85c13 | 1242 | u8 is_mimo_rate; |
e2ebc833 | 1243 | union il4965_tx_power_dual_stream tx_power; |
4bc85c13 WYG |
1244 | |
1245 | /* for mimo, reduce each chain's txpower by half | |
1246 | * (3dB, 6 steps), so total output power is regulatory | |
1247 | * compliant. */ | |
1248 | if (i & 0x8) { | |
1249 | current_regulatory = reg_limit - | |
e2ebc833 | 1250 | IL_TX_POWER_MIMO_REGULATORY_COMPENSATION; |
4bc85c13 WYG |
1251 | is_mimo_rate = 1; |
1252 | } else { | |
1253 | current_regulatory = reg_limit; | |
1254 | is_mimo_rate = 0; | |
1255 | } | |
1256 | ||
1257 | /* find txpower limit, either hardware or regulatory */ | |
1258 | power_limit = saturation_power - back_off_table[i]; | |
1259 | if (power_limit > current_regulatory) | |
1260 | power_limit = current_regulatory; | |
1261 | ||
1262 | /* reduce user's txpower request if necessary | |
1263 | * for this rate on this channel */ | |
1264 | target_power = user_target_power; | |
1265 | if (target_power > power_limit) | |
1266 | target_power = power_limit; | |
1267 | ||
58de00a4 | 1268 | D_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n", |
4bc85c13 WYG |
1269 | i, saturation_power - back_off_table[i], |
1270 | current_regulatory, user_target_power, | |
1271 | target_power); | |
1272 | ||
1273 | /* for each of 2 Tx chains (radio transmitters) */ | |
1274 | for (c = 0; c < 2; c++) { | |
1275 | s32 atten_value; | |
1276 | ||
1277 | if (is_mimo_rate) | |
1278 | atten_value = | |
46bc8d4b | 1279 | (s32)le32_to_cpu(il->card_alive_init. |
4bc85c13 WYG |
1280 | tx_atten[txatten_grp][c]); |
1281 | else | |
1282 | atten_value = 0; | |
1283 | ||
0c2c8852 SG |
1284 | /* calculate idx; higher idx means lower txpower */ |
1285 | power_idx = (u8) (factory_gain_idx[c] - | |
4bc85c13 WYG |
1286 | (target_power - |
1287 | factory_actual_pwr[c]) - | |
1288 | temperature_comp[c] - | |
1289 | voltage_compensation + | |
1290 | atten_value); | |
1291 | ||
0c2c8852 SG |
1292 | /* D_TXPOWER("calculated txpower idx %d\n", |
1293 | power_idx); */ | |
4bc85c13 | 1294 | |
0c2c8852 SG |
1295 | if (power_idx < get_min_power_idx(i, band)) |
1296 | power_idx = get_min_power_idx(i, band); | |
4bc85c13 | 1297 | |
0c2c8852 | 1298 | /* adjust 5 GHz idx to support negative idxes */ |
4bc85c13 | 1299 | if (!band) |
0c2c8852 | 1300 | power_idx += 9; |
4bc85c13 WYG |
1301 | |
1302 | /* CCK, rate 32, reduce txpower for CCK */ | |
3b98c7f4 | 1303 | if (i == POWER_TBL_CCK_ENTRY) |
0c2c8852 | 1304 | power_idx += |
e2ebc833 | 1305 | IL_TX_POWER_CCK_COMPENSATION_C_STEP; |
4bc85c13 WYG |
1306 | |
1307 | /* stay within the table! */ | |
0c2c8852 SG |
1308 | if (power_idx > 107) { |
1309 | IL_WARN("txpower idx %d > 107\n", | |
1310 | power_idx); | |
1311 | power_idx = 107; | |
4bc85c13 | 1312 | } |
0c2c8852 SG |
1313 | if (power_idx < 0) { |
1314 | IL_WARN("txpower idx %d < 0\n", | |
1315 | power_idx); | |
1316 | power_idx = 0; | |
4bc85c13 WYG |
1317 | } |
1318 | ||
1319 | /* fill txpower command for this rate/chain */ | |
1320 | tx_power.s.radio_tx_gain[c] = | |
0c2c8852 | 1321 | gain_table[band][power_idx].radio; |
4bc85c13 | 1322 | tx_power.s.dsp_predis_atten[c] = |
0c2c8852 | 1323 | gain_table[band][power_idx].dsp; |
4bc85c13 | 1324 | |
0c2c8852 | 1325 | D_TXPOWER("chain %d mimo %d idx %d " |
4bc85c13 | 1326 | "gain 0x%02x dsp %d\n", |
0c2c8852 | 1327 | c, atten_value, power_idx, |
4bc85c13 WYG |
1328 | tx_power.s.radio_tx_gain[c], |
1329 | tx_power.s.dsp_predis_atten[c]); | |
1330 | } /* for each chain */ | |
1331 | ||
1332 | tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw); | |
1333 | ||
1334 | } /* for each rate */ | |
1335 | ||
1336 | return 0; | |
1337 | } | |
1338 | ||
1339 | /** | |
e2ebc833 | 1340 | * il4965_send_tx_power - Configure the TXPOWER level user limit |
4bc85c13 WYG |
1341 | * |
1342 | * Uses the active RXON for channel, band, and characteristics (ht40, high) | |
46bc8d4b | 1343 | * The power limit is taken from il->tx_power_user_lmt. |
4bc85c13 | 1344 | */ |
46bc8d4b | 1345 | static int il4965_send_tx_power(struct il_priv *il) |
4bc85c13 | 1346 | { |
e2ebc833 | 1347 | struct il4965_txpowertable_cmd cmd = { 0 }; |
4bc85c13 WYG |
1348 | int ret; |
1349 | u8 band = 0; | |
1350 | bool is_ht40 = false; | |
1351 | u8 ctrl_chan_high = 0; | |
7c2cde2e | 1352 | struct il_rxon_context *ctx = &il->ctx; |
4bc85c13 | 1353 | |
46bc8d4b | 1354 | if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &il->status), |
4bc85c13 WYG |
1355 | "TX Power requested while scanning!\n")) |
1356 | return -EAGAIN; | |
1357 | ||
46bc8d4b | 1358 | band = il->band == IEEE80211_BAND_2GHZ; |
4bc85c13 | 1359 | |
be663ab6 | 1360 | is_ht40 = iw4965_is_ht40_channel(ctx->active.flags); |
4bc85c13 WYG |
1361 | |
1362 | if (is_ht40 && (ctx->active.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK)) | |
1363 | ctrl_chan_high = 1; | |
1364 | ||
1365 | cmd.band = band; | |
1366 | cmd.channel = ctx->active.channel; | |
1367 | ||
46bc8d4b | 1368 | ret = il4965_fill_txpower_tbl(il, band, |
4bc85c13 WYG |
1369 | le16_to_cpu(ctx->active.channel), |
1370 | is_ht40, ctrl_chan_high, &cmd.tx_power); | |
1371 | if (ret) | |
1372 | goto out; | |
1373 | ||
46bc8d4b | 1374 | ret = il_send_cmd_pdu(il, |
3b98c7f4 | 1375 | REPLY_TX_PWR_TBL_CMD, sizeof(cmd), &cmd); |
4bc85c13 WYG |
1376 | |
1377 | out: | |
1378 | return ret; | |
1379 | } | |
1380 | ||
46bc8d4b | 1381 | static int il4965_send_rxon_assoc(struct il_priv *il, |
e2ebc833 | 1382 | struct il_rxon_context *ctx) |
4bc85c13 WYG |
1383 | { |
1384 | int ret = 0; | |
e2ebc833 SG |
1385 | struct il4965_rxon_assoc_cmd rxon_assoc; |
1386 | const struct il_rxon_cmd *rxon1 = &ctx->staging; | |
1387 | const struct il_rxon_cmd *rxon2 = &ctx->active; | |
4bc85c13 | 1388 | |
232913b5 SG |
1389 | if (rxon1->flags == rxon2->flags && |
1390 | rxon1->filter_flags == rxon2->filter_flags && | |
1391 | rxon1->cck_basic_rates == rxon2->cck_basic_rates && | |
1392 | rxon1->ofdm_ht_single_stream_basic_rates == | |
1393 | rxon2->ofdm_ht_single_stream_basic_rates && | |
1394 | rxon1->ofdm_ht_dual_stream_basic_rates == | |
1395 | rxon2->ofdm_ht_dual_stream_basic_rates && | |
1396 | rxon1->rx_chain == rxon2->rx_chain && | |
1397 | rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates) { | |
58de00a4 | 1398 | D_INFO("Using current RXON_ASSOC. Not resending.\n"); |
4bc85c13 WYG |
1399 | return 0; |
1400 | } | |
1401 | ||
1402 | rxon_assoc.flags = ctx->staging.flags; | |
1403 | rxon_assoc.filter_flags = ctx->staging.filter_flags; | |
1404 | rxon_assoc.ofdm_basic_rates = ctx->staging.ofdm_basic_rates; | |
1405 | rxon_assoc.cck_basic_rates = ctx->staging.cck_basic_rates; | |
1406 | rxon_assoc.reserved = 0; | |
1407 | rxon_assoc.ofdm_ht_single_stream_basic_rates = | |
1408 | ctx->staging.ofdm_ht_single_stream_basic_rates; | |
1409 | rxon_assoc.ofdm_ht_dual_stream_basic_rates = | |
1410 | ctx->staging.ofdm_ht_dual_stream_basic_rates; | |
1411 | rxon_assoc.rx_chain_select_flags = ctx->staging.rx_chain; | |
1412 | ||
46bc8d4b | 1413 | ret = il_send_cmd_pdu_async(il, REPLY_RXON_ASSOC, |
4bc85c13 | 1414 | sizeof(rxon_assoc), &rxon_assoc, NULL); |
4bc85c13 WYG |
1415 | |
1416 | return ret; | |
1417 | } | |
1418 | ||
46bc8d4b | 1419 | static int il4965_commit_rxon(struct il_priv *il, struct il_rxon_context *ctx) |
4bc85c13 WYG |
1420 | { |
1421 | /* cast away the const for active_rxon in this function */ | |
e2ebc833 | 1422 | struct il_rxon_cmd *active_rxon = (void *)&ctx->active; |
4bc85c13 WYG |
1423 | int ret; |
1424 | bool new_assoc = | |
1425 | !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK); | |
1426 | ||
46bc8d4b | 1427 | if (!il_is_alive(il)) |
4bc85c13 WYG |
1428 | return -EBUSY; |
1429 | ||
1430 | if (!ctx->is_active) | |
1431 | return 0; | |
1432 | ||
1433 | /* always get timestamp with Rx frame */ | |
1434 | ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK; | |
1435 | ||
46bc8d4b | 1436 | ret = il_check_rxon_cmd(il, ctx); |
4bc85c13 | 1437 | if (ret) { |
9406f797 | 1438 | IL_ERR("Invalid RXON configuration. Not committing.\n"); |
4bc85c13 WYG |
1439 | return -EINVAL; |
1440 | } | |
1441 | ||
1442 | /* | |
1443 | * receive commit_rxon request | |
1444 | * abort any previous channel switch if still in process | |
1445 | */ | |
46bc8d4b | 1446 | if (test_bit(STATUS_CHANNEL_SWITCH_PENDING, &il->status) && |
232913b5 | 1447 | il->switch_channel != ctx->staging.channel) { |
58de00a4 | 1448 | D_11H("abort channel switch on %d\n", |
46bc8d4b SG |
1449 | le16_to_cpu(il->switch_channel)); |
1450 | il_chswitch_done(il, false); | |
4bc85c13 WYG |
1451 | } |
1452 | ||
1453 | /* If we don't need to send a full RXON, we can use | |
e2ebc833 | 1454 | * il_rxon_assoc_cmd which is used to reconfigure filter |
4bc85c13 | 1455 | * and other flags for the current radio configuration. */ |
46bc8d4b SG |
1456 | if (!il_full_rxon_required(il, ctx)) { |
1457 | ret = il_send_rxon_assoc(il, ctx); | |
4bc85c13 | 1458 | if (ret) { |
9406f797 | 1459 | IL_ERR("Error setting RXON_ASSOC (%d)\n", ret); |
4bc85c13 WYG |
1460 | return ret; |
1461 | } | |
1462 | ||
1463 | memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon)); | |
46bc8d4b | 1464 | il_print_rx_config_cmd(il, ctx); |
17e859a8 SG |
1465 | /* |
1466 | * We do not commit tx power settings while channel changing, | |
1467 | * do it now if tx power changed. | |
1468 | */ | |
46bc8d4b | 1469 | il_set_tx_power(il, il->tx_power_next, false); |
17e859a8 | 1470 | return 0; |
4bc85c13 WYG |
1471 | } |
1472 | ||
1473 | /* If we are currently associated and the new config requires | |
1474 | * an RXON_ASSOC and the new config wants the associated mask enabled, | |
1475 | * we must clear the associated from the active configuration | |
1476 | * before we apply the new config */ | |
e2ebc833 | 1477 | if (il_is_associated_ctx(ctx) && new_assoc) { |
58de00a4 | 1478 | D_INFO("Toggling associated bit on current RXON\n"); |
4bc85c13 WYG |
1479 | active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
1480 | ||
46bc8d4b | 1481 | ret = il_send_cmd_pdu(il, ctx->rxon_cmd, |
e2ebc833 | 1482 | sizeof(struct il_rxon_cmd), |
4bc85c13 WYG |
1483 | active_rxon); |
1484 | ||
1485 | /* If the mask clearing failed then we set | |
1486 | * active_rxon back to what it was previously */ | |
1487 | if (ret) { | |
1488 | active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; | |
9406f797 | 1489 | IL_ERR("Error clearing ASSOC_MSK (%d)\n", ret); |
4bc85c13 WYG |
1490 | return ret; |
1491 | } | |
46bc8d4b SG |
1492 | il_clear_ucode_stations(il, ctx); |
1493 | il_restore_stations(il, ctx); | |
1494 | ret = il4965_restore_default_wep_keys(il, ctx); | |
4bc85c13 | 1495 | if (ret) { |
9406f797 | 1496 | IL_ERR("Failed to restore WEP keys (%d)\n", ret); |
4bc85c13 WYG |
1497 | return ret; |
1498 | } | |
1499 | } | |
1500 | ||
58de00a4 | 1501 | D_INFO("Sending RXON\n" |
4bc85c13 WYG |
1502 | "* with%s RXON_FILTER_ASSOC_MSK\n" |
1503 | "* channel = %d\n" | |
1504 | "* bssid = %pM\n", | |
1505 | (new_assoc ? "" : "out"), | |
1506 | le16_to_cpu(ctx->staging.channel), | |
1507 | ctx->staging.bssid_addr); | |
1508 | ||
46bc8d4b SG |
1509 | il_set_rxon_hwcrypto(il, ctx, |
1510 | !il->cfg->mod_params->sw_crypto); | |
4bc85c13 WYG |
1511 | |
1512 | /* Apply the new configuration | |
1513 | * RXON unassoc clears the station table in uCode so restoration of | |
1514 | * stations is needed after it (the RXON command) completes | |
1515 | */ | |
1516 | if (!new_assoc) { | |
46bc8d4b | 1517 | ret = il_send_cmd_pdu(il, ctx->rxon_cmd, |
e2ebc833 | 1518 | sizeof(struct il_rxon_cmd), &ctx->staging); |
4bc85c13 | 1519 | if (ret) { |
9406f797 | 1520 | IL_ERR("Error setting new RXON (%d)\n", ret); |
4bc85c13 WYG |
1521 | return ret; |
1522 | } | |
58de00a4 | 1523 | D_INFO("Return from !new_assoc RXON.\n"); |
4bc85c13 | 1524 | memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon)); |
46bc8d4b SG |
1525 | il_clear_ucode_stations(il, ctx); |
1526 | il_restore_stations(il, ctx); | |
1527 | ret = il4965_restore_default_wep_keys(il, ctx); | |
4bc85c13 | 1528 | if (ret) { |
9406f797 | 1529 | IL_ERR("Failed to restore WEP keys (%d)\n", ret); |
4bc85c13 WYG |
1530 | return ret; |
1531 | } | |
1532 | } | |
1533 | if (new_assoc) { | |
46bc8d4b | 1534 | il->start_calib = 0; |
4bc85c13 WYG |
1535 | /* Apply the new configuration |
1536 | * RXON assoc doesn't clear the station table in uCode, | |
1537 | */ | |
46bc8d4b | 1538 | ret = il_send_cmd_pdu(il, ctx->rxon_cmd, |
e2ebc833 | 1539 | sizeof(struct il_rxon_cmd), &ctx->staging); |
4bc85c13 | 1540 | if (ret) { |
9406f797 | 1541 | IL_ERR("Error setting new RXON (%d)\n", ret); |
4bc85c13 WYG |
1542 | return ret; |
1543 | } | |
1544 | memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon)); | |
1545 | } | |
46bc8d4b | 1546 | il_print_rx_config_cmd(il, ctx); |
4bc85c13 | 1547 | |
46bc8d4b | 1548 | il4965_init_sensitivity(il); |
4bc85c13 WYG |
1549 | |
1550 | /* If we issue a new RXON command which required a tune then we must | |
1551 | * send a new TXPOWER command or we won't be able to Tx any frames */ | |
46bc8d4b | 1552 | ret = il_set_tx_power(il, il->tx_power_next, true); |
4bc85c13 | 1553 | if (ret) { |
9406f797 | 1554 | IL_ERR("Error sending TX power (%d)\n", ret); |
4bc85c13 WYG |
1555 | return ret; |
1556 | } | |
1557 | ||
1558 | return 0; | |
1559 | } | |
1560 | ||
46bc8d4b | 1561 | static int il4965_hw_channel_switch(struct il_priv *il, |
4bc85c13 WYG |
1562 | struct ieee80211_channel_switch *ch_switch) |
1563 | { | |
7c2cde2e | 1564 | struct il_rxon_context *ctx = &il->ctx; |
4bc85c13 WYG |
1565 | int rc; |
1566 | u8 band = 0; | |
1567 | bool is_ht40 = false; | |
1568 | u8 ctrl_chan_high = 0; | |
e2ebc833 SG |
1569 | struct il4965_channel_switch_cmd cmd; |
1570 | const struct il_channel_info *ch_info; | |
4bc85c13 WYG |
1571 | u32 switch_time_in_usec, ucode_switch_time; |
1572 | u16 ch; | |
1573 | u32 tsf_low; | |
1574 | u8 switch_count; | |
1575 | u16 beacon_interval = le16_to_cpu(ctx->timing.beacon_interval); | |
1576 | struct ieee80211_vif *vif = ctx->vif; | |
46bc8d4b | 1577 | band = il->band == IEEE80211_BAND_2GHZ; |
4bc85c13 | 1578 | |
be663ab6 | 1579 | is_ht40 = iw4965_is_ht40_channel(ctx->staging.flags); |
4bc85c13 WYG |
1580 | |
1581 | if (is_ht40 && | |
1582 | (ctx->staging.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK)) | |
1583 | ctrl_chan_high = 1; | |
1584 | ||
1585 | cmd.band = band; | |
1586 | cmd.expect_beacon = 0; | |
1587 | ch = ch_switch->channel->hw_value; | |
1588 | cmd.channel = cpu_to_le16(ch); | |
1589 | cmd.rxon_flags = ctx->staging.flags; | |
1590 | cmd.rxon_filter_flags = ctx->staging.filter_flags; | |
1591 | switch_count = ch_switch->count; | |
1592 | tsf_low = ch_switch->timestamp & 0x0ffffffff; | |
1593 | /* | |
1594 | * calculate the ucode channel switch time | |
1595 | * adding TSF as one of the factor for when to switch | |
1596 | */ | |
232913b5 | 1597 | if (il->ucode_beacon_time > tsf_low && beacon_interval) { |
46bc8d4b | 1598 | if (switch_count > ((il->ucode_beacon_time - tsf_low) / |
4bc85c13 | 1599 | beacon_interval)) { |
46bc8d4b | 1600 | switch_count -= (il->ucode_beacon_time - |
4bc85c13 WYG |
1601 | tsf_low) / beacon_interval; |
1602 | } else | |
1603 | switch_count = 0; | |
1604 | } | |
1605 | if (switch_count <= 1) | |
46bc8d4b | 1606 | cmd.switch_time = cpu_to_le32(il->ucode_beacon_time); |
4bc85c13 WYG |
1607 | else { |
1608 | switch_time_in_usec = | |
1609 | vif->bss_conf.beacon_int * switch_count * TIME_UNIT; | |
46bc8d4b | 1610 | ucode_switch_time = il_usecs_to_beacons(il, |
4bc85c13 WYG |
1611 | switch_time_in_usec, |
1612 | beacon_interval); | |
46bc8d4b SG |
1613 | cmd.switch_time = il_add_beacon_time(il, |
1614 | il->ucode_beacon_time, | |
4bc85c13 WYG |
1615 | ucode_switch_time, |
1616 | beacon_interval); | |
1617 | } | |
58de00a4 | 1618 | D_11H("uCode time for the switch is 0x%x\n", |
4bc85c13 | 1619 | cmd.switch_time); |
46bc8d4b | 1620 | ch_info = il_get_channel_info(il, il->band, ch); |
4bc85c13 | 1621 | if (ch_info) |
e2ebc833 | 1622 | cmd.expect_beacon = il_is_channel_radar(ch_info); |
4bc85c13 | 1623 | else { |
9406f797 | 1624 | IL_ERR("invalid channel switch from %u to %u\n", |
4bc85c13 WYG |
1625 | ctx->active.channel, ch); |
1626 | return -EFAULT; | |
1627 | } | |
1628 | ||
46bc8d4b | 1629 | rc = il4965_fill_txpower_tbl(il, band, ch, is_ht40, |
4bc85c13 WYG |
1630 | ctrl_chan_high, &cmd.tx_power); |
1631 | if (rc) { | |
58de00a4 | 1632 | D_11H("error:%d fill txpower_tbl\n", rc); |
4bc85c13 WYG |
1633 | return rc; |
1634 | } | |
1635 | ||
46bc8d4b | 1636 | return il_send_cmd_pdu(il, |
be663ab6 | 1637 | REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd); |
4bc85c13 WYG |
1638 | } |
1639 | ||
1640 | /** | |
e2ebc833 | 1641 | * il4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array |
4bc85c13 | 1642 | */ |
46bc8d4b | 1643 | static void il4965_txq_update_byte_cnt_tbl(struct il_priv *il, |
e2ebc833 | 1644 | struct il_tx_queue *txq, |
4bc85c13 WYG |
1645 | u16 byte_cnt) |
1646 | { | |
46bc8d4b | 1647 | struct il4965_scd_bc_tbl *scd_bc_tbl = il->scd_bc_tbls.addr; |
4bc85c13 WYG |
1648 | int txq_id = txq->q.id; |
1649 | int write_ptr = txq->q.write_ptr; | |
e2ebc833 | 1650 | int len = byte_cnt + IL_TX_CRC_SIZE + IL_TX_DELIMITER_SIZE; |
4bc85c13 WYG |
1651 | __le16 bc_ent; |
1652 | ||
1653 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); | |
1654 | ||
1655 | bc_ent = cpu_to_le16(len & 0xFFF); | |
1656 | /* Set up byte count within first 256 entries */ | |
1657 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
1658 | ||
1659 | /* If within first 64 entries, duplicate at end */ | |
1660 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
1661 | scd_bc_tbl[txq_id]. | |
1662 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
1663 | } | |
1664 | ||
1665 | /** | |
e2ebc833 | 1666 | * il4965_hw_get_temperature - return the calibrated temperature (in Kelvin) |
ebf0d90d | 1667 | * @stats: Provides the temperature reading from the uCode |
4bc85c13 | 1668 | * |
ebf0d90d | 1669 | * A return of <0 indicates bogus data in the stats |
4bc85c13 | 1670 | */ |
46bc8d4b | 1671 | static int il4965_hw_get_temperature(struct il_priv *il) |
4bc85c13 WYG |
1672 | { |
1673 | s32 temperature; | |
1674 | s32 vt; | |
1675 | s32 R1, R2, R3; | |
1676 | u32 R4; | |
1677 | ||
46bc8d4b | 1678 | if (test_bit(STATUS_TEMPERATURE, &il->status) && |
ebf0d90d | 1679 | (il->_4965.stats.flag & |
4bc85c13 | 1680 | STATISTICS_REPLY_FLG_HT40_MODE_MSK)) { |
58de00a4 | 1681 | D_TEMP("Running HT40 temperature calibration\n"); |
46bc8d4b SG |
1682 | R1 = (s32)le32_to_cpu(il->card_alive_init.therm_r1[1]); |
1683 | R2 = (s32)le32_to_cpu(il->card_alive_init.therm_r2[1]); | |
1684 | R3 = (s32)le32_to_cpu(il->card_alive_init.therm_r3[1]); | |
1685 | R4 = le32_to_cpu(il->card_alive_init.therm_r4[1]); | |
4bc85c13 | 1686 | } else { |
58de00a4 | 1687 | D_TEMP("Running temperature calibration\n"); |
46bc8d4b SG |
1688 | R1 = (s32)le32_to_cpu(il->card_alive_init.therm_r1[0]); |
1689 | R2 = (s32)le32_to_cpu(il->card_alive_init.therm_r2[0]); | |
1690 | R3 = (s32)le32_to_cpu(il->card_alive_init.therm_r3[0]); | |
1691 | R4 = le32_to_cpu(il->card_alive_init.therm_r4[0]); | |
4bc85c13 WYG |
1692 | } |
1693 | ||
1694 | /* | |
1695 | * Temperature is only 23 bits, so sign extend out to 32. | |
1696 | * | |
ebf0d90d | 1697 | * NOTE If we haven't received a stats notification yet |
4bc85c13 WYG |
1698 | * with an updated temperature, use R4 provided to us in the |
1699 | * "initialize" ALIVE response. | |
1700 | */ | |
46bc8d4b | 1701 | if (!test_bit(STATUS_TEMPERATURE, &il->status)) |
4bc85c13 WYG |
1702 | vt = sign_extend32(R4, 23); |
1703 | else | |
ebf0d90d | 1704 | vt = sign_extend32(le32_to_cpu(il->_4965.stats. |
4bc85c13 WYG |
1705 | general.common.temperature), 23); |
1706 | ||
58de00a4 | 1707 | D_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt); |
4bc85c13 WYG |
1708 | |
1709 | if (R3 == R1) { | |
9406f797 | 1710 | IL_ERR("Calibration conflict R1 == R3\n"); |
4bc85c13 WYG |
1711 | return -1; |
1712 | } | |
1713 | ||
1714 | /* Calculate temperature in degrees Kelvin, adjust by 97%. | |
1715 | * Add offset to center the adjustment around 0 degrees Centigrade. */ | |
1716 | temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2); | |
1717 | temperature /= (R3 - R1); | |
1718 | temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET; | |
1719 | ||
58de00a4 | 1720 | D_TEMP("Calibrated temperature: %dK, %dC\n", |
4bc85c13 WYG |
1721 | temperature, KELVIN_TO_CELSIUS(temperature)); |
1722 | ||
1723 | return temperature; | |
1724 | } | |
1725 | ||
1726 | /* Adjust Txpower only if temperature variance is greater than threshold. */ | |
e2ebc833 | 1727 | #define IL_TEMPERATURE_THRESHOLD 3 |
4bc85c13 WYG |
1728 | |
1729 | /** | |
e2ebc833 | 1730 | * il4965_is_temp_calib_needed - determines if new calibration is needed |
4bc85c13 WYG |
1731 | * |
1732 | * If the temperature changed has changed sufficiently, then a recalibration | |
1733 | * is needed. | |
1734 | * | |
46bc8d4b | 1735 | * Assumes caller will replace il->last_temperature once calibration |
4bc85c13 WYG |
1736 | * executed. |
1737 | */ | |
46bc8d4b | 1738 | static int il4965_is_temp_calib_needed(struct il_priv *il) |
4bc85c13 WYG |
1739 | { |
1740 | int temp_diff; | |
1741 | ||
46bc8d4b | 1742 | if (!test_bit(STATUS_STATISTICS, &il->status)) { |
ebf0d90d | 1743 | D_TEMP("Temperature not updated -- no stats.\n"); |
4bc85c13 WYG |
1744 | return 0; |
1745 | } | |
1746 | ||
46bc8d4b | 1747 | temp_diff = il->temperature - il->last_temperature; |
4bc85c13 WYG |
1748 | |
1749 | /* get absolute value */ | |
1750 | if (temp_diff < 0) { | |
58de00a4 | 1751 | D_POWER("Getting cooler, delta %d\n", temp_diff); |
4bc85c13 WYG |
1752 | temp_diff = -temp_diff; |
1753 | } else if (temp_diff == 0) | |
58de00a4 | 1754 | D_POWER("Temperature unchanged\n"); |
4bc85c13 | 1755 | else |
58de00a4 | 1756 | D_POWER("Getting warmer, delta %d\n", temp_diff); |
4bc85c13 | 1757 | |
e2ebc833 | 1758 | if (temp_diff < IL_TEMPERATURE_THRESHOLD) { |
58de00a4 | 1759 | D_POWER(" => thermal txpower calib not needed\n"); |
4bc85c13 WYG |
1760 | return 0; |
1761 | } | |
1762 | ||
58de00a4 | 1763 | D_POWER(" => thermal txpower calib needed\n"); |
4bc85c13 WYG |
1764 | |
1765 | return 1; | |
1766 | } | |
1767 | ||
46bc8d4b | 1768 | static void il4965_temperature_calib(struct il_priv *il) |
4bc85c13 WYG |
1769 | { |
1770 | s32 temp; | |
1771 | ||
46bc8d4b | 1772 | temp = il4965_hw_get_temperature(il); |
e2ebc833 | 1773 | if (IL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(temp)) |
4bc85c13 WYG |
1774 | return; |
1775 | ||
46bc8d4b SG |
1776 | if (il->temperature != temp) { |
1777 | if (il->temperature) | |
58de00a4 | 1778 | D_TEMP("Temperature changed " |
4bc85c13 | 1779 | "from %dC to %dC\n", |
46bc8d4b | 1780 | KELVIN_TO_CELSIUS(il->temperature), |
4bc85c13 WYG |
1781 | KELVIN_TO_CELSIUS(temp)); |
1782 | else | |
58de00a4 | 1783 | D_TEMP("Temperature " |
4bc85c13 WYG |
1784 | "initialized to %dC\n", |
1785 | KELVIN_TO_CELSIUS(temp)); | |
1786 | } | |
1787 | ||
46bc8d4b SG |
1788 | il->temperature = temp; |
1789 | set_bit(STATUS_TEMPERATURE, &il->status); | |
4bc85c13 | 1790 | |
46bc8d4b SG |
1791 | if (!il->disable_tx_power_cal && |
1792 | unlikely(!test_bit(STATUS_SCANNING, &il->status)) && | |
1793 | il4965_is_temp_calib_needed(il)) | |
1794 | queue_work(il->workqueue, &il->txpower_work); | |
4bc85c13 WYG |
1795 | } |
1796 | ||
e2ebc833 | 1797 | static u16 il4965_get_hcmd_size(u8 cmd_id, u16 len) |
4bc85c13 WYG |
1798 | { |
1799 | switch (cmd_id) { | |
1800 | case REPLY_RXON: | |
e2ebc833 | 1801 | return (u16) sizeof(struct il4965_rxon_cmd); |
4bc85c13 WYG |
1802 | default: |
1803 | return len; | |
1804 | } | |
1805 | } | |
1806 | ||
e2ebc833 | 1807 | static u16 il4965_build_addsta_hcmd(const struct il_addsta_cmd *cmd, |
be663ab6 | 1808 | u8 *data) |
4bc85c13 | 1809 | { |
e2ebc833 | 1810 | struct il4965_addsta_cmd *addsta = (struct il4965_addsta_cmd *)data; |
4bc85c13 WYG |
1811 | addsta->mode = cmd->mode; |
1812 | memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify)); | |
e2ebc833 | 1813 | memcpy(&addsta->key, &cmd->key, sizeof(struct il4965_keyinfo)); |
4bc85c13 WYG |
1814 | addsta->station_flags = cmd->station_flags; |
1815 | addsta->station_flags_msk = cmd->station_flags_msk; | |
1816 | addsta->tid_disable_tx = cmd->tid_disable_tx; | |
1817 | addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid; | |
1818 | addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid; | |
1819 | addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn; | |
1820 | addsta->sleep_tx_count = cmd->sleep_tx_count; | |
1821 | addsta->reserved1 = cpu_to_le16(0); | |
1822 | addsta->reserved2 = cpu_to_le16(0); | |
1823 | ||
e2ebc833 | 1824 | return (u16)sizeof(struct il4965_addsta_cmd); |
4bc85c13 WYG |
1825 | } |
1826 | ||
e2ebc833 | 1827 | static inline u32 il4965_get_scd_ssn(struct il4965_tx_resp *tx_resp) |
4bc85c13 WYG |
1828 | { |
1829 | return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN; | |
1830 | } | |
1831 | ||
1832 | /** | |
e2ebc833 | 1833 | * il4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue |
4bc85c13 | 1834 | */ |
46bc8d4b | 1835 | static int il4965_tx_status_reply_tx(struct il_priv *il, |
e2ebc833 SG |
1836 | struct il_ht_agg *agg, |
1837 | struct il4965_tx_resp *tx_resp, | |
4bc85c13 WYG |
1838 | int txq_id, u16 start_idx) |
1839 | { | |
1840 | u16 status; | |
1841 | struct agg_tx_status *frame_status = tx_resp->u.agg_status; | |
1842 | struct ieee80211_tx_info *info = NULL; | |
1843 | struct ieee80211_hdr *hdr = NULL; | |
1844 | u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); | |
1845 | int i, sh, idx; | |
1846 | u16 seq; | |
1847 | if (agg->wait_for_ba) | |
58de00a4 | 1848 | D_TX_REPLY("got tx response w/o block-ack\n"); |
4bc85c13 WYG |
1849 | |
1850 | agg->frame_count = tx_resp->frame_count; | |
1851 | agg->start_idx = start_idx; | |
1852 | agg->rate_n_flags = rate_n_flags; | |
1853 | agg->bitmap = 0; | |
1854 | ||
1855 | /* num frames attempted by Tx command */ | |
1856 | if (agg->frame_count == 1) { | |
1857 | /* Only one frame was attempted; no block-ack will arrive */ | |
1858 | status = le16_to_cpu(frame_status[0].status); | |
1859 | idx = start_idx; | |
1860 | ||
58de00a4 | 1861 | D_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", |
4bc85c13 WYG |
1862 | agg->frame_count, agg->start_idx, idx); |
1863 | ||
46bc8d4b | 1864 | info = IEEE80211_SKB_CB(il->txq[txq_id].txb[idx].skb); |
4bc85c13 WYG |
1865 | info->status.rates[0].count = tx_resp->failure_frame + 1; |
1866 | info->flags &= ~IEEE80211_TX_CTL_AMPDU; | |
e2ebc833 | 1867 | info->flags |= il4965_tx_status_to_mac80211(status); |
46bc8d4b | 1868 | il4965_hwrate_to_tx_control(il, rate_n_flags, info); |
4bc85c13 | 1869 | |
58de00a4 | 1870 | D_TX_REPLY("1 Frame 0x%x failure :%d\n", |
4bc85c13 | 1871 | status & 0xff, tx_resp->failure_frame); |
58de00a4 | 1872 | D_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags); |
4bc85c13 WYG |
1873 | |
1874 | agg->wait_for_ba = 0; | |
1875 | } else { | |
1876 | /* Two or more frames were attempted; expect block-ack */ | |
1877 | u64 bitmap = 0; | |
1878 | int start = agg->start_idx; | |
1879 | ||
6ce1dc45 | 1880 | /* Construct bit-map of pending frames within Tx win */ |
4bc85c13 WYG |
1881 | for (i = 0; i < agg->frame_count; i++) { |
1882 | u16 sc; | |
1883 | status = le16_to_cpu(frame_status[i].status); | |
1884 | seq = le16_to_cpu(frame_status[i].sequence); | |
2d09b062 | 1885 | idx = SEQ_TO_IDX(seq); |
4bc85c13 WYG |
1886 | txq_id = SEQ_TO_QUEUE(seq); |
1887 | ||
1888 | if (status & (AGG_TX_STATE_FEW_BYTES_MSK | | |
1889 | AGG_TX_STATE_ABORT_MSK)) | |
1890 | continue; | |
1891 | ||
58de00a4 | 1892 | D_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", |
4bc85c13 WYG |
1893 | agg->frame_count, txq_id, idx); |
1894 | ||
46bc8d4b | 1895 | hdr = il_tx_queue_get_hdr(il, txq_id, idx); |
4bc85c13 | 1896 | if (!hdr) { |
9406f797 | 1897 | IL_ERR( |
4bc85c13 WYG |
1898 | "BUG_ON idx doesn't point to valid skb" |
1899 | " idx=%d, txq_id=%d\n", idx, txq_id); | |
1900 | return -1; | |
1901 | } | |
1902 | ||
1903 | sc = le16_to_cpu(hdr->seq_ctrl); | |
1904 | if (idx != (SEQ_TO_SN(sc) & 0xff)) { | |
9406f797 | 1905 | IL_ERR( |
4bc85c13 WYG |
1906 | "BUG_ON idx doesn't match seq control" |
1907 | " idx=%d, seq_idx=%d, seq=%d\n", | |
1908 | idx, SEQ_TO_SN(sc), hdr->seq_ctrl); | |
1909 | return -1; | |
1910 | } | |
1911 | ||
58de00a4 | 1912 | D_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", |
4bc85c13 WYG |
1913 | i, idx, SEQ_TO_SN(sc)); |
1914 | ||
1915 | sh = idx - start; | |
1916 | if (sh > 64) { | |
1917 | sh = (start - idx) + 0xff; | |
1918 | bitmap = bitmap << sh; | |
1919 | sh = 0; | |
1920 | start = idx; | |
1921 | } else if (sh < -64) | |
1922 | sh = 0xff - (start - idx); | |
1923 | else if (sh < 0) { | |
1924 | sh = start - idx; | |
1925 | start = idx; | |
1926 | bitmap = bitmap << sh; | |
1927 | sh = 0; | |
1928 | } | |
1929 | bitmap |= 1ULL << sh; | |
58de00a4 | 1930 | D_TX_REPLY("start=%d bitmap=0x%llx\n", |
4bc85c13 WYG |
1931 | start, (unsigned long long)bitmap); |
1932 | } | |
1933 | ||
1934 | agg->bitmap = bitmap; | |
1935 | agg->start_idx = start; | |
58de00a4 | 1936 | D_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", |
4bc85c13 WYG |
1937 | agg->frame_count, agg->start_idx, |
1938 | (unsigned long long)agg->bitmap); | |
1939 | ||
1940 | if (bitmap) | |
1941 | agg->wait_for_ba = 1; | |
1942 | } | |
1943 | return 0; | |
1944 | } | |
1945 | ||
46bc8d4b | 1946 | static u8 il4965_find_station(struct il_priv *il, const u8 *addr) |
4bc85c13 WYG |
1947 | { |
1948 | int i; | |
1949 | int start = 0; | |
e2ebc833 | 1950 | int ret = IL_INVALID_STATION; |
4bc85c13 WYG |
1951 | unsigned long flags; |
1952 | ||
46bc8d4b | 1953 | if ((il->iw_mode == NL80211_IFTYPE_ADHOC)) |
e2ebc833 | 1954 | start = IL_STA_ID; |
4bc85c13 WYG |
1955 | |
1956 | if (is_broadcast_ether_addr(addr)) | |
7c2cde2e | 1957 | return il->ctx.bcast_sta_id; |
4bc85c13 | 1958 | |
46bc8d4b SG |
1959 | spin_lock_irqsave(&il->sta_lock, flags); |
1960 | for (i = start; i < il->hw_params.max_stations; i++) | |
1961 | if (il->stations[i].used && | |
1962 | (!compare_ether_addr(il->stations[i].sta.sta.addr, | |
4bc85c13 WYG |
1963 | addr))) { |
1964 | ret = i; | |
1965 | goto out; | |
1966 | } | |
1967 | ||
58de00a4 | 1968 | D_ASSOC("can not find STA %pM total %d\n", |
46bc8d4b | 1969 | addr, il->num_stations); |
4bc85c13 WYG |
1970 | |
1971 | out: | |
1972 | /* | |
1973 | * It may be possible that more commands interacting with stations | |
1974 | * arrive before we completed processing the adding of | |
1975 | * station | |
1976 | */ | |
e2ebc833 | 1977 | if (ret != IL_INVALID_STATION && |
46bc8d4b SG |
1978 | (!(il->stations[ret].used & IL_STA_UCODE_ACTIVE) || |
1979 | ((il->stations[ret].used & IL_STA_UCODE_ACTIVE) && | |
1980 | (il->stations[ret].used & IL_STA_UCODE_INPROGRESS)))) { | |
9406f797 | 1981 | IL_ERR("Requested station info for sta %d before ready.\n", |
4bc85c13 | 1982 | ret); |
e2ebc833 | 1983 | ret = IL_INVALID_STATION; |
4bc85c13 | 1984 | } |
46bc8d4b | 1985 | spin_unlock_irqrestore(&il->sta_lock, flags); |
4bc85c13 WYG |
1986 | return ret; |
1987 | } | |
1988 | ||
46bc8d4b | 1989 | static int il4965_get_ra_sta_id(struct il_priv *il, struct ieee80211_hdr *hdr) |
4bc85c13 | 1990 | { |
46bc8d4b | 1991 | if (il->iw_mode == NL80211_IFTYPE_STATION) { |
e2ebc833 | 1992 | return IL_AP_ID; |
4bc85c13 WYG |
1993 | } else { |
1994 | u8 *da = ieee80211_get_DA(hdr); | |
46bc8d4b | 1995 | return il4965_find_station(il, da); |
4bc85c13 WYG |
1996 | } |
1997 | } | |
1998 | ||
1999 | /** | |
e2ebc833 | 2000 | * il4965_rx_reply_tx - Handle standard (non-aggregation) Tx response |
4bc85c13 | 2001 | */ |
46bc8d4b | 2002 | static void il4965_rx_reply_tx(struct il_priv *il, |
b73bb5f1 | 2003 | struct il_rx_buf *rxb) |
4bc85c13 | 2004 | { |
dcae1c64 | 2005 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
4bc85c13 WYG |
2006 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
2007 | int txq_id = SEQ_TO_QUEUE(sequence); | |
0c2c8852 | 2008 | int idx = SEQ_TO_IDX(sequence); |
46bc8d4b | 2009 | struct il_tx_queue *txq = &il->txq[txq_id]; |
4bc85c13 WYG |
2010 | struct ieee80211_hdr *hdr; |
2011 | struct ieee80211_tx_info *info; | |
e2ebc833 | 2012 | struct il4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; |
4bc85c13 WYG |
2013 | u32 status = le32_to_cpu(tx_resp->u.status); |
2014 | int uninitialized_var(tid); | |
2015 | int sta_id; | |
2016 | int freed; | |
2017 | u8 *qc = NULL; | |
2018 | unsigned long flags; | |
2019 | ||
0c2c8852 SG |
2020 | if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) { |
2021 | IL_ERR("Read idx for DMA queue txq_id (%d) idx %d " | |
4bc85c13 | 2022 | "is out of range [0-%d] %d %d\n", txq_id, |
0c2c8852 | 2023 | idx, txq->q.n_bd, txq->q.write_ptr, |
4bc85c13 WYG |
2024 | txq->q.read_ptr); |
2025 | return; | |
2026 | } | |
2027 | ||
2028 | txq->time_stamp = jiffies; | |
2029 | info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb); | |
2030 | memset(&info->status, 0, sizeof(info->status)); | |
2031 | ||
0c2c8852 | 2032 | hdr = il_tx_queue_get_hdr(il, txq_id, idx); |
4bc85c13 WYG |
2033 | if (ieee80211_is_data_qos(hdr->frame_control)) { |
2034 | qc = ieee80211_get_qos_ctl(hdr); | |
2035 | tid = qc[0] & 0xf; | |
2036 | } | |
2037 | ||
46bc8d4b | 2038 | sta_id = il4965_get_ra_sta_id(il, hdr); |
e2ebc833 | 2039 | if (txq->sched_retry && unlikely(sta_id == IL_INVALID_STATION)) { |
9406f797 | 2040 | IL_ERR("Station not known\n"); |
4bc85c13 WYG |
2041 | return; |
2042 | } | |
2043 | ||
46bc8d4b | 2044 | spin_lock_irqsave(&il->sta_lock, flags); |
4bc85c13 | 2045 | if (txq->sched_retry) { |
e2ebc833 SG |
2046 | const u32 scd_ssn = il4965_get_scd_ssn(tx_resp); |
2047 | struct il_ht_agg *agg = NULL; | |
4bc85c13 WYG |
2048 | WARN_ON(!qc); |
2049 | ||
46bc8d4b | 2050 | agg = &il->stations[sta_id].tid[tid].agg; |
4bc85c13 | 2051 | |
0c2c8852 | 2052 | il4965_tx_status_reply_tx(il, agg, tx_resp, txq_id, idx); |
4bc85c13 WYG |
2053 | |
2054 | /* check if BAR is needed */ | |
e2ebc833 | 2055 | if ((tx_resp->frame_count == 1) && !il4965_is_tx_success(status)) |
4bc85c13 WYG |
2056 | info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; |
2057 | ||
2058 | if (txq->q.read_ptr != (scd_ssn & 0xff)) { | |
0c2c8852 | 2059 | idx = il_queue_dec_wrap(scd_ssn & 0xff, |
be663ab6 | 2060 | txq->q.n_bd); |
58de00a4 | 2061 | D_TX_REPLY("Retry scheduler reclaim scd_ssn " |
0c2c8852 SG |
2062 | "%d idx %d\n", scd_ssn , idx); |
2063 | freed = il4965_tx_queue_reclaim(il, txq_id, idx); | |
4bc85c13 | 2064 | if (qc) |
46bc8d4b | 2065 | il4965_free_tfds_in_queue(il, sta_id, |
4bc85c13 WYG |
2066 | tid, freed); |
2067 | ||
46bc8d4b | 2068 | if (il->mac80211_registered && |
232913b5 SG |
2069 | il_queue_space(&txq->q) > txq->q.low_mark && |
2070 | agg->state != IL_EMPTYING_HW_QUEUE_DELBA) | |
46bc8d4b | 2071 | il_wake_queue(il, txq); |
4bc85c13 WYG |
2072 | } |
2073 | } else { | |
2074 | info->status.rates[0].count = tx_resp->failure_frame + 1; | |
e2ebc833 | 2075 | info->flags |= il4965_tx_status_to_mac80211(status); |
46bc8d4b | 2076 | il4965_hwrate_to_tx_control(il, |
4bc85c13 WYG |
2077 | le32_to_cpu(tx_resp->rate_n_flags), |
2078 | info); | |
2079 | ||
58de00a4 | 2080 | D_TX_REPLY("TXQ %d status %s (0x%08x) " |
4bc85c13 WYG |
2081 | "rate_n_flags 0x%x retries %d\n", |
2082 | txq_id, | |
e2ebc833 | 2083 | il4965_get_tx_fail_reason(status), status, |
4bc85c13 WYG |
2084 | le32_to_cpu(tx_resp->rate_n_flags), |
2085 | tx_resp->failure_frame); | |
2086 | ||
0c2c8852 | 2087 | freed = il4965_tx_queue_reclaim(il, txq_id, idx); |
e2ebc833 | 2088 | if (qc && likely(sta_id != IL_INVALID_STATION)) |
46bc8d4b | 2089 | il4965_free_tfds_in_queue(il, sta_id, tid, freed); |
e2ebc833 | 2090 | else if (sta_id == IL_INVALID_STATION) |
58de00a4 | 2091 | D_TX_REPLY("Station not known\n"); |
4bc85c13 | 2092 | |
46bc8d4b | 2093 | if (il->mac80211_registered && |
232913b5 | 2094 | il_queue_space(&txq->q) > txq->q.low_mark) |
46bc8d4b | 2095 | il_wake_queue(il, txq); |
4bc85c13 | 2096 | } |
e2ebc833 | 2097 | if (qc && likely(sta_id != IL_INVALID_STATION)) |
46bc8d4b | 2098 | il4965_txq_check_empty(il, sta_id, tid, txq_id); |
4bc85c13 | 2099 | |
46bc8d4b | 2100 | il4965_check_abort_status(il, tx_resp->frame_count, status); |
4bc85c13 | 2101 | |
46bc8d4b | 2102 | spin_unlock_irqrestore(&il->sta_lock, flags); |
4bc85c13 WYG |
2103 | } |
2104 | ||
46bc8d4b | 2105 | static void il4965_rx_beacon_notif(struct il_priv *il, |
b73bb5f1 | 2106 | struct il_rx_buf *rxb) |
4bc85c13 | 2107 | { |
dcae1c64 | 2108 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
e2ebc833 | 2109 | struct il4965_beacon_notif *beacon = (void *)pkt->u.raw; |
be663ab6 | 2110 | u8 rate __maybe_unused = |
e2ebc833 | 2111 | il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); |
4bc85c13 | 2112 | |
58de00a4 | 2113 | D_RX("beacon status %#x, retries:%d ibssmgr:%d " |
4bc85c13 WYG |
2114 | "tsf:0x%.8x%.8x rate:%d\n", |
2115 | le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, | |
2116 | beacon->beacon_notify_hdr.failure_frame, | |
2117 | le32_to_cpu(beacon->ibss_mgr_status), | |
2118 | le32_to_cpu(beacon->high_tsf), | |
2119 | le32_to_cpu(beacon->low_tsf), rate); | |
4bc85c13 | 2120 | |
46bc8d4b | 2121 | il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status); |
4bc85c13 WYG |
2122 | } |
2123 | ||
4bc85c13 | 2124 | /* Set up 4965-specific Rx frame reply handlers */ |
46bc8d4b | 2125 | static void il4965_rx_handler_setup(struct il_priv *il) |
4bc85c13 WYG |
2126 | { |
2127 | /* Legacy Rx frames */ | |
46bc8d4b | 2128 | il->rx_handlers[REPLY_RX] = il4965_rx_reply_rx; |
4bc85c13 | 2129 | /* Tx response */ |
46bc8d4b SG |
2130 | il->rx_handlers[REPLY_TX] = il4965_rx_reply_tx; |
2131 | il->rx_handlers[BEACON_NOTIFICATION] = il4965_rx_beacon_notif; | |
4bc85c13 WYG |
2132 | } |
2133 | ||
e2ebc833 SG |
2134 | static struct il_hcmd_ops il4965_hcmd = { |
2135 | .rxon_assoc = il4965_send_rxon_assoc, | |
2136 | .commit_rxon = il4965_commit_rxon, | |
2137 | .set_rxon_chain = il4965_set_rxon_chain, | |
4bc85c13 WYG |
2138 | }; |
2139 | ||
46bc8d4b | 2140 | static void il4965_post_scan(struct il_priv *il) |
4bc85c13 | 2141 | { |
7c2cde2e | 2142 | struct il_rxon_context *ctx = &il->ctx; |
4bc85c13 WYG |
2143 | |
2144 | /* | |
2145 | * Since setting the RXON may have been deferred while | |
2146 | * performing the scan, fire one off if needed | |
2147 | */ | |
2148 | if (memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging))) | |
46bc8d4b | 2149 | il_commit_rxon(il, ctx); |
4bc85c13 WYG |
2150 | } |
2151 | ||
46bc8d4b | 2152 | static void il4965_post_associate(struct il_priv *il) |
4bc85c13 | 2153 | { |
7c2cde2e | 2154 | struct il_rxon_context *ctx = &il->ctx; |
4bc85c13 WYG |
2155 | struct ieee80211_vif *vif = ctx->vif; |
2156 | struct ieee80211_conf *conf = NULL; | |
2157 | int ret = 0; | |
2158 | ||
46bc8d4b | 2159 | if (!vif || !il->is_open) |
4bc85c13 WYG |
2160 | return; |
2161 | ||
46bc8d4b | 2162 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) |
4bc85c13 WYG |
2163 | return; |
2164 | ||
46bc8d4b | 2165 | il_scan_cancel_timeout(il, 200); |
4bc85c13 | 2166 | |
46bc8d4b | 2167 | conf = il_ieee80211_get_hw_conf(il->hw); |
4bc85c13 WYG |
2168 | |
2169 | ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
46bc8d4b | 2170 | il_commit_rxon(il, ctx); |
4bc85c13 | 2171 | |
46bc8d4b | 2172 | ret = il_send_rxon_timing(il, ctx); |
4bc85c13 | 2173 | if (ret) |
9406f797 | 2174 | IL_WARN("RXON timing - " |
4bc85c13 WYG |
2175 | "Attempting to continue.\n"); |
2176 | ||
2177 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
2178 | ||
46bc8d4b | 2179 | il_set_rxon_ht(il, &il->current_ht_config); |
4bc85c13 | 2180 | |
46bc8d4b SG |
2181 | if (il->cfg->ops->hcmd->set_rxon_chain) |
2182 | il->cfg->ops->hcmd->set_rxon_chain(il, ctx); | |
4bc85c13 WYG |
2183 | |
2184 | ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid); | |
2185 | ||
58de00a4 | 2186 | D_ASSOC("assoc id %d beacon interval %d\n", |
4bc85c13 WYG |
2187 | vif->bss_conf.aid, vif->bss_conf.beacon_int); |
2188 | ||
2189 | if (vif->bss_conf.use_short_preamble) | |
2190 | ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
2191 | else | |
2192 | ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2193 | ||
2194 | if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) { | |
2195 | if (vif->bss_conf.use_short_slot) | |
2196 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
2197 | else | |
2198 | ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
2199 | } | |
2200 | ||
46bc8d4b | 2201 | il_commit_rxon(il, ctx); |
4bc85c13 | 2202 | |
58de00a4 | 2203 | D_ASSOC("Associated as %d to: %pM\n", |
4bc85c13 WYG |
2204 | vif->bss_conf.aid, ctx->active.bssid_addr); |
2205 | ||
2206 | switch (vif->type) { | |
2207 | case NL80211_IFTYPE_STATION: | |
2208 | break; | |
2209 | case NL80211_IFTYPE_ADHOC: | |
46bc8d4b | 2210 | il4965_send_beacon_cmd(il); |
4bc85c13 WYG |
2211 | break; |
2212 | default: | |
9406f797 | 2213 | IL_ERR("%s Should not be called in %d mode\n", |
4bc85c13 WYG |
2214 | __func__, vif->type); |
2215 | break; | |
2216 | } | |
2217 | ||
2218 | /* the chain noise calibration will enabled PM upon completion | |
2219 | * If chain noise has already been run, then we need to enable | |
2220 | * power management here */ | |
46bc8d4b SG |
2221 | if (il->chain_noise_data.state == IL_CHAIN_NOISE_DONE) |
2222 | il_power_update_mode(il, false); | |
4bc85c13 WYG |
2223 | |
2224 | /* Enable Rx differential gain and sensitivity calibrations */ | |
46bc8d4b SG |
2225 | il4965_chain_noise_reset(il); |
2226 | il->start_calib = 1; | |
4bc85c13 WYG |
2227 | } |
2228 | ||
46bc8d4b | 2229 | static void il4965_config_ap(struct il_priv *il) |
4bc85c13 | 2230 | { |
7c2cde2e | 2231 | struct il_rxon_context *ctx = &il->ctx; |
4bc85c13 WYG |
2232 | struct ieee80211_vif *vif = ctx->vif; |
2233 | int ret = 0; | |
2234 | ||
46bc8d4b | 2235 | lockdep_assert_held(&il->mutex); |
4bc85c13 | 2236 | |
46bc8d4b | 2237 | if (test_bit(STATUS_EXIT_PENDING, &il->status)) |
4bc85c13 WYG |
2238 | return; |
2239 | ||
2240 | /* The following should be done only at AP bring up */ | |
e2ebc833 | 2241 | if (!il_is_associated_ctx(ctx)) { |
4bc85c13 WYG |
2242 | |
2243 | /* RXON - unassoc (to set timing command) */ | |
2244 | ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
46bc8d4b | 2245 | il_commit_rxon(il, ctx); |
4bc85c13 WYG |
2246 | |
2247 | /* RXON Timing */ | |
46bc8d4b | 2248 | ret = il_send_rxon_timing(il, ctx); |
4bc85c13 | 2249 | if (ret) |
9406f797 | 2250 | IL_WARN("RXON timing failed - " |
4bc85c13 WYG |
2251 | "Attempting to continue.\n"); |
2252 | ||
2253 | /* AP has all antennas */ | |
46bc8d4b SG |
2254 | il->chain_noise_data.active_chains = |
2255 | il->hw_params.valid_rx_ant; | |
2256 | il_set_rxon_ht(il, &il->current_ht_config); | |
2257 | if (il->cfg->ops->hcmd->set_rxon_chain) | |
2258 | il->cfg->ops->hcmd->set_rxon_chain(il, ctx); | |
4bc85c13 WYG |
2259 | |
2260 | ctx->staging.assoc_id = 0; | |
2261 | ||
2262 | if (vif->bss_conf.use_short_preamble) | |
2263 | ctx->staging.flags |= | |
2264 | RXON_FLG_SHORT_PREAMBLE_MSK; | |
2265 | else | |
2266 | ctx->staging.flags &= | |
2267 | ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
2268 | ||
2269 | if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) { | |
2270 | if (vif->bss_conf.use_short_slot) | |
2271 | ctx->staging.flags |= | |
2272 | RXON_FLG_SHORT_SLOT_MSK; | |
2273 | else | |
2274 | ctx->staging.flags &= | |
2275 | ~RXON_FLG_SHORT_SLOT_MSK; | |
2276 | } | |
2277 | /* need to send beacon cmd before committing assoc RXON! */ | |
46bc8d4b | 2278 | il4965_send_beacon_cmd(il); |
4bc85c13 WYG |
2279 | /* restore RXON assoc */ |
2280 | ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; | |
46bc8d4b | 2281 | il_commit_rxon(il, ctx); |
4bc85c13 | 2282 | } |
46bc8d4b | 2283 | il4965_send_beacon_cmd(il); |
4bc85c13 WYG |
2284 | } |
2285 | ||
e2ebc833 SG |
2286 | static struct il_hcmd_utils_ops il4965_hcmd_utils = { |
2287 | .get_hcmd_size = il4965_get_hcmd_size, | |
2288 | .build_addsta_hcmd = il4965_build_addsta_hcmd, | |
2289 | .request_scan = il4965_request_scan, | |
2290 | .post_scan = il4965_post_scan, | |
4bc85c13 WYG |
2291 | }; |
2292 | ||
e2ebc833 SG |
2293 | static struct il_lib_ops il4965_lib = { |
2294 | .set_hw_params = il4965_hw_set_hw_params, | |
2295 | .txq_update_byte_cnt_tbl = il4965_txq_update_byte_cnt_tbl, | |
2296 | .txq_attach_buf_to_tfd = il4965_hw_txq_attach_buf_to_tfd, | |
2297 | .txq_free_tfd = il4965_hw_txq_free_tfd, | |
2298 | .txq_init = il4965_hw_tx_queue_init, | |
2299 | .rx_handler_setup = il4965_rx_handler_setup, | |
2300 | .is_valid_rtc_data_addr = il4965_hw_valid_rtc_data_addr, | |
2301 | .init_alive_start = il4965_init_alive_start, | |
2302 | .load_ucode = il4965_load_bsm, | |
2303 | .dump_nic_error_log = il4965_dump_nic_error_log, | |
2304 | .dump_fh = il4965_dump_fh, | |
2305 | .set_channel_switch = il4965_hw_channel_switch, | |
4bc85c13 | 2306 | .apm_ops = { |
e2ebc833 SG |
2307 | .init = il_apm_init, |
2308 | .config = il4965_nic_config, | |
4bc85c13 WYG |
2309 | }, |
2310 | .eeprom_ops = { | |
2311 | .regulatory_bands = { | |
2312 | EEPROM_REGULATORY_BAND_1_CHANNELS, | |
2313 | EEPROM_REGULATORY_BAND_2_CHANNELS, | |
2314 | EEPROM_REGULATORY_BAND_3_CHANNELS, | |
2315 | EEPROM_REGULATORY_BAND_4_CHANNELS, | |
2316 | EEPROM_REGULATORY_BAND_5_CHANNELS, | |
2317 | EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS, | |
2318 | EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS | |
2319 | }, | |
e2ebc833 SG |
2320 | .acquire_semaphore = il4965_eeprom_acquire_semaphore, |
2321 | .release_semaphore = il4965_eeprom_release_semaphore, | |
4bc85c13 | 2322 | }, |
e2ebc833 SG |
2323 | .send_tx_power = il4965_send_tx_power, |
2324 | .update_chain_flags = il4965_update_chain_flags, | |
4bc85c13 | 2325 | .temp_ops = { |
e2ebc833 | 2326 | .temperature = il4965_temperature_calib, |
4bc85c13 WYG |
2327 | }, |
2328 | .debugfs_ops = { | |
e2ebc833 SG |
2329 | .rx_stats_read = il4965_ucode_rx_stats_read, |
2330 | .tx_stats_read = il4965_ucode_tx_stats_read, | |
2331 | .general_stats_read = il4965_ucode_general_stats_read, | |
4bc85c13 | 2332 | }, |
4bc85c13 WYG |
2333 | }; |
2334 | ||
e2ebc833 SG |
2335 | static const struct il_legacy_ops il4965_legacy_ops = { |
2336 | .post_associate = il4965_post_associate, | |
2337 | .config_ap = il4965_config_ap, | |
2338 | .manage_ibss_station = il4965_manage_ibss_station, | |
2339 | .update_bcast_stations = il4965_update_bcast_stations, | |
4bc85c13 WYG |
2340 | }; |
2341 | ||
e2ebc833 SG |
2342 | struct ieee80211_ops il4965_hw_ops = { |
2343 | .tx = il4965_mac_tx, | |
2344 | .start = il4965_mac_start, | |
2345 | .stop = il4965_mac_stop, | |
2346 | .add_interface = il_mac_add_interface, | |
2347 | .remove_interface = il_mac_remove_interface, | |
2348 | .change_interface = il_mac_change_interface, | |
2349 | .config = il_mac_config, | |
2350 | .configure_filter = il4965_configure_filter, | |
2351 | .set_key = il4965_mac_set_key, | |
2352 | .update_tkip_key = il4965_mac_update_tkip_key, | |
2353 | .conf_tx = il_mac_conf_tx, | |
2354 | .reset_tsf = il_mac_reset_tsf, | |
2355 | .bss_info_changed = il_mac_bss_info_changed, | |
2356 | .ampdu_action = il4965_mac_ampdu_action, | |
2357 | .hw_scan = il_mac_hw_scan, | |
2358 | .sta_add = il4965_mac_sta_add, | |
2359 | .sta_remove = il_mac_sta_remove, | |
2360 | .channel_switch = il4965_mac_channel_switch, | |
2361 | .tx_last_beacon = il_mac_tx_last_beacon, | |
4bc85c13 WYG |
2362 | }; |
2363 | ||
e2ebc833 SG |
2364 | static const struct il_ops il4965_ops = { |
2365 | .lib = &il4965_lib, | |
2366 | .hcmd = &il4965_hcmd, | |
2367 | .utils = &il4965_hcmd_utils, | |
2368 | .led = &il4965_led_ops, | |
2369 | .legacy = &il4965_legacy_ops, | |
2370 | .ieee80211_ops = &il4965_hw_ops, | |
4bc85c13 WYG |
2371 | }; |
2372 | ||
e2ebc833 | 2373 | static struct il_base_params il4965_base_params = { |
d3175167 SG |
2374 | .eeprom_size = IL4965_EEPROM_IMG_SIZE, |
2375 | .num_of_queues = IL49_NUM_QUEUES, | |
2376 | .num_of_ampdu_queues = IL49_NUM_AMPDU_QUEUES, | |
4bc85c13 WYG |
2377 | .pll_cfg_val = 0, |
2378 | .set_l0s = true, | |
2379 | .use_bsm = true, | |
4bc85c13 | 2380 | .led_compensation = 61, |
d3175167 | 2381 | .chain_noise_num_beacons = IL4965_CAL_NUM_BEACONS, |
e2ebc833 | 2382 | .wd_timeout = IL_DEF_WD_TIMEOUT, |
4bc85c13 | 2383 | .temperature_kelvin = true, |
4bc85c13 WYG |
2384 | .ucode_tracing = true, |
2385 | .sensitivity_calib_by_driver = true, | |
2386 | .chain_noise_calib_by_driver = true, | |
4bc85c13 WYG |
2387 | }; |
2388 | ||
e2ebc833 | 2389 | struct il_cfg il4965_cfg = { |
4bc85c13 | 2390 | .name = "Intel(R) Wireless WiFi Link 4965AGN", |
d3175167 SG |
2391 | .fw_name_pre = IL4965_FW_PRE, |
2392 | .ucode_api_max = IL4965_UCODE_API_MAX, | |
2393 | .ucode_api_min = IL4965_UCODE_API_MIN, | |
e2ebc833 | 2394 | .sku = IL_SKU_A|IL_SKU_G|IL_SKU_N, |
4bc85c13 WYG |
2395 | .valid_tx_ant = ANT_AB, |
2396 | .valid_rx_ant = ANT_ABC, | |
2397 | .eeprom_ver = EEPROM_4965_EEPROM_VERSION, | |
2398 | .eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION, | |
e2ebc833 SG |
2399 | .ops = &il4965_ops, |
2400 | .mod_params = &il4965_mod_params, | |
2401 | .base_params = &il4965_base_params, | |
2402 | .led_mode = IL_LED_BLINK, | |
4bc85c13 WYG |
2403 | /* |
2404 | * Force use of chains B and C for scan RX on 5 GHz band | |
2405 | * because the device has off-channel reception on chain A. | |
2406 | */ | |
2407 | .scan_rx_antennas[IEEE80211_BAND_5GHZ] = ANT_BC, | |
2408 | }; | |
2409 | ||
2410 | /* Module firmware */ | |
d3175167 | 2411 | MODULE_FIRMWARE(IL4965_MODULE_FIRMWARE(IL4965_UCODE_API_MAX)); |