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iwlegacy: merge il_lib_ops into il_ops
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / common.c
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/etherdevice.h>
32#include <linux/sched.h>
33#include <linux/slab.h>
0cdc2136
SG		 34#include <linux/types.h>
35#include <linux/lockdep.h>
36#include <linux/init.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/skbuff.h>
be663ab6
WYG		 41#include <net/mac80211.h>
42
98613be0 43#include "common.h"
be663ab6 44
17d4eca6
SG		 45int
46_il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout)
47{
48 const int interval = 10; /* microseconds */
49 int t = 0;
50
51 do {
52 if ((_il_rd(il, addr) & mask) == (bits & mask))
53 return t;
54 udelay(interval);
55 t += interval;
56 } while (t < timeout);
57
58 return -ETIMEDOUT;
59}
60EXPORT_SYMBOL(_il_poll_bit);
61
62void
63il_set_bit(struct il_priv *p, u32 r, u32 m)
64{
65 unsigned long reg_flags;
66
67 spin_lock_irqsave(&p->reg_lock, reg_flags);
68 _il_set_bit(p, r, m);
69 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
70}
71EXPORT_SYMBOL(il_set_bit);
72
73void
74il_clear_bit(struct il_priv *p, u32 r, u32 m)
75{
76 unsigned long reg_flags;
77
78 spin_lock_irqsave(&p->reg_lock, reg_flags);
79 _il_clear_bit(p, r, m);
80 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
81}
82EXPORT_SYMBOL(il_clear_bit);
83
1e0f32a4 84bool
17d4eca6
SG		 85_il_grab_nic_access(struct il_priv *il)
86{
87 int ret;
88 u32 val;
89
90 /* this bit wakes up the NIC */
91 _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
92
93 /*
94 * These bits say the device is running, and should keep running for
95 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
96 * but they do not indicate that embedded SRAM is restored yet;
97 * 3945 and 4965 have volatile SRAM, and must save/restore contents
98 * to/from host DRAM when sleeping/waking for power-saving.
99 * Each direction takes approximately 1/4 millisecond; with this
100 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
101 * series of register accesses are expected (e.g. reading Event Log),
102 * to keep device from sleeping.
103 *
104 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
105 * SRAM is okay/restored. We don't check that here because this call
106 * is just for hardware register access; but GP1 MAC_SLEEP check is a
107 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
108 *
109 */
110 ret =
111 _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
112 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
113 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
b6603036 114 if (unlikely(ret < 0)) {
17d4eca6 115 val = _il_rd(il, CSR_GP_CNTRL);
b6603036
SG		 116 WARN_ONCE(1, "Timeout waiting for ucode processor access "
117 "(CSR_GP_CNTRL 0x%08x)\n", val);
17d4eca6 118 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1e0f32a4 119 return false;
17d4eca6
SG		 120 }
121
1e0f32a4 122 return true;
17d4eca6
SG		 123}
124EXPORT_SYMBOL_GPL(_il_grab_nic_access);
125
126int
127il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout)
128{
129 const int interval = 10; /* microseconds */
130 int t = 0;
131
132 do {
133 if ((il_rd(il, addr) & mask) == mask)
134 return t;
135 udelay(interval);
136 t += interval;
137 } while (t < timeout);
138
139 return -ETIMEDOUT;
140}
141EXPORT_SYMBOL(il_poll_bit);
142
143u32
144il_rd_prph(struct il_priv *il, u32 reg)
145{
146 unsigned long reg_flags;
147 u32 val;
148
149 spin_lock_irqsave(&il->reg_lock, reg_flags);
150 _il_grab_nic_access(il);
151 val = _il_rd_prph(il, reg);
152 _il_release_nic_access(il);
153 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
154 return val;
155}
156EXPORT_SYMBOL(il_rd_prph);
157
158void
159il_wr_prph(struct il_priv *il, u32 addr, u32 val)
160{
161 unsigned long reg_flags;
162
163 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4 164 if (likely(_il_grab_nic_access(il))) {
17d4eca6
SG		 165 _il_wr_prph(il, addr, val);
166 _il_release_nic_access(il);
167 }
168 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
169}
170EXPORT_SYMBOL(il_wr_prph);
171
172u32
173il_read_targ_mem(struct il_priv *il, u32 addr)
174{
175 unsigned long reg_flags;
176 u32 value;
177
178 spin_lock_irqsave(&il->reg_lock, reg_flags);
179 _il_grab_nic_access(il);
180
181 _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
17d4eca6
SG		 182 value = _il_rd(il, HBUS_TARG_MEM_RDAT);
183
184 _il_release_nic_access(il);
185 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
186 return value;
187}
188EXPORT_SYMBOL(il_read_targ_mem);
189
190void
191il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
192{
193 unsigned long reg_flags;
194
195 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4 196 if (likely(_il_grab_nic_access(il))) {
17d4eca6 197 _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
17d4eca6
SG		 198 _il_wr(il, HBUS_TARG_MEM_WDAT, val);
199 _il_release_nic_access(il);
200 }
201 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
202}
203EXPORT_SYMBOL(il_write_targ_mem);
204
e7392364
SG		 205const char *
206il_get_cmd_string(u8 cmd)
0cdc2136
SG		 207{
208 switch (cmd) {
209 IL_CMD(N_ALIVE);
210 IL_CMD(N_ERROR);
211 IL_CMD(C_RXON);
212 IL_CMD(C_RXON_ASSOC);
213 IL_CMD(C_QOS_PARAM);
214 IL_CMD(C_RXON_TIMING);
215 IL_CMD(C_ADD_STA);
216 IL_CMD(C_REM_STA);
217 IL_CMD(C_WEPKEY);
218 IL_CMD(N_3945_RX);
219 IL_CMD(C_TX);
220 IL_CMD(C_RATE_SCALE);
221 IL_CMD(C_LEDS);
222 IL_CMD(C_TX_LINK_QUALITY_CMD);
223 IL_CMD(C_CHANNEL_SWITCH);
224 IL_CMD(N_CHANNEL_SWITCH);
225 IL_CMD(C_SPECTRUM_MEASUREMENT);
226 IL_CMD(N_SPECTRUM_MEASUREMENT);
227 IL_CMD(C_POWER_TBL);
228 IL_CMD(N_PM_SLEEP);
229 IL_CMD(N_PM_DEBUG_STATS);
230 IL_CMD(C_SCAN);
231 IL_CMD(C_SCAN_ABORT);
232 IL_CMD(N_SCAN_START);
233 IL_CMD(N_SCAN_RESULTS);
234 IL_CMD(N_SCAN_COMPLETE);
235 IL_CMD(N_BEACON);
236 IL_CMD(C_TX_BEACON);
237 IL_CMD(C_TX_PWR_TBL);
238 IL_CMD(C_BT_CONFIG);
239 IL_CMD(C_STATS);
240 IL_CMD(N_STATS);
241 IL_CMD(N_CARD_STATE);
242 IL_CMD(N_MISSED_BEACONS);
243 IL_CMD(C_CT_KILL_CONFIG);
244 IL_CMD(C_SENSITIVITY);
245 IL_CMD(C_PHY_CALIBRATION);
246 IL_CMD(N_RX_PHY);
247 IL_CMD(N_RX_MPDU);
248 IL_CMD(N_RX);
249 IL_CMD(N_COMPRESSED_BA);
250 default:
251 return "UNKNOWN";
252
253 }
254}
255EXPORT_SYMBOL(il_get_cmd_string);
256
257#define HOST_COMPLETE_TIMEOUT (HZ / 2)
258
e7392364
SG		 259static void
260il_generic_cmd_callback(struct il_priv *il, struct il_device_cmd *cmd,
261 struct il_rx_pkt *pkt)
0cdc2136
SG		 262{
263 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
264 IL_ERR("Bad return from %s (0x%08X)\n",
e7392364 265 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
0cdc2136
SG		 266 return;
267 }
0cdc2136
SG		 268#ifdef CONFIG_IWLEGACY_DEBUG
269 switch (cmd->hdr.cmd) {
270 case C_TX_LINK_QUALITY_CMD:
271 case C_SENSITIVITY:
272 D_HC_DUMP("back from %s (0x%08X)\n",
e7392364 273 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
0cdc2136
SG		 274 break;
275 default:
e7392364
SG		 276 D_HC("back from %s (0x%08X)\n", il_get_cmd_string(cmd->hdr.cmd),
277 pkt->hdr.flags);
0cdc2136
SG		 278 }
279#endif
280}
281
282static int
283il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd)
284{
285 int ret;
286
287 BUG_ON(!(cmd->flags & CMD_ASYNC));
288
289 /* An asynchronous command can not expect an SKB to be set. */
290 BUG_ON(cmd->flags & CMD_WANT_SKB);
291
292 /* Assign a generic callback if one is not provided */
293 if (!cmd->callback)
294 cmd->callback = il_generic_cmd_callback;
295
296 if (test_bit(S_EXIT_PENDING, &il->status))
297 return -EBUSY;
298
299 ret = il_enqueue_hcmd(il, cmd);
300 if (ret < 0) {
301 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
e7392364 302 il_get_cmd_string(cmd->id), ret);
0cdc2136
SG		 303 return ret;
304 }
305 return 0;
306}
307
e7392364
SG		 308int
309il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG		 310{
311 int cmd_idx;
312 int ret;
313
314 lockdep_assert_held(&il->mutex);
315
316 BUG_ON(cmd->flags & CMD_ASYNC);
317
e7392364 318 /* A synchronous command can not have a callback set. */
0cdc2136
SG		 319 BUG_ON(cmd->callback);
320
321 D_INFO("Attempting to send sync command %s\n",
e7392364 322 il_get_cmd_string(cmd->id));
0cdc2136
SG		 323
324 set_bit(S_HCMD_ACTIVE, &il->status);
325 D_INFO("Setting HCMD_ACTIVE for command %s\n",
e7392364 326 il_get_cmd_string(cmd->id));
0cdc2136
SG		 327
328 cmd_idx = il_enqueue_hcmd(il, cmd);
329 if (cmd_idx < 0) {
330 ret = cmd_idx;
331 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
e7392364 332 il_get_cmd_string(cmd->id), ret);
0cdc2136
SG		 333 goto out;
334 }
335
336 ret = wait_event_timeout(il->wait_command_queue,
e7392364
SG		 337 !test_bit(S_HCMD_ACTIVE, &il->status),
338 HOST_COMPLETE_TIMEOUT);
0cdc2136
SG		 339 if (!ret) {
340 if (test_bit(S_HCMD_ACTIVE, &il->status)) {
e7392364
SG		 341 IL_ERR("Error sending %s: time out after %dms.\n",
342 il_get_cmd_string(cmd->id),
343 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
0cdc2136
SG		 344
345 clear_bit(S_HCMD_ACTIVE, &il->status);
e7392364
SG		 346 D_INFO("Clearing HCMD_ACTIVE for command %s\n",
347 il_get_cmd_string(cmd->id));
0cdc2136
SG		 348 ret = -ETIMEDOUT;
349 goto cancel;
350 }
351 }
352
353 if (test_bit(S_RF_KILL_HW, &il->status)) {
354 IL_ERR("Command %s aborted: RF KILL Switch\n",
e7392364 355 il_get_cmd_string(cmd->id));
0cdc2136
SG		 356 ret = -ECANCELED;
357 goto fail;
358 }
359 if (test_bit(S_FW_ERROR, &il->status)) {
360 IL_ERR("Command %s failed: FW Error\n",
e7392364 361 il_get_cmd_string(cmd->id));
0cdc2136
SG		 362 ret = -EIO;
363 goto fail;
364 }
365 if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
366 IL_ERR("Error: Response NULL in '%s'\n",
e7392364 367 il_get_cmd_string(cmd->id));
0cdc2136
SG		 368 ret = -EIO;
369 goto cancel;
370 }
371
372 ret = 0;
373 goto out;
374
375cancel:
376 if (cmd->flags & CMD_WANT_SKB) {
377 /*
378 * Cancel the CMD_WANT_SKB flag for the cmd in the
379 * TX cmd queue. Otherwise in case the cmd comes
380 * in later, it will possibly set an invalid
381 * address (cmd->meta.source).
382 */
e7392364 383 il->txq[il->cmd_queue].meta[cmd_idx].flags &= ~CMD_WANT_SKB;
0cdc2136
SG		 384 }
385fail:
386 if (cmd->reply_page) {
387 il_free_pages(il, cmd->reply_page);
388 cmd->reply_page = 0;
389 }
390out:
391 return ret;
392}
393EXPORT_SYMBOL(il_send_cmd_sync);
394
e7392364
SG		 395int
396il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG		 397{
398 if (cmd->flags & CMD_ASYNC)
399 return il_send_cmd_async(il, cmd);
400
401 return il_send_cmd_sync(il, cmd);
402}
403EXPORT_SYMBOL(il_send_cmd);
404
405int
406il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data)
407{
408 struct il_host_cmd cmd = {
409 .id = id,
410 .len = len,
411 .data = data,
412 };
413
414 return il_send_cmd_sync(il, &cmd);
415}
416EXPORT_SYMBOL(il_send_cmd_pdu);
417
e7392364
SG		 418int
419il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1722f8e1
SG		 420 void (*callback) (struct il_priv *il,
421 struct il_device_cmd *cmd,
422 struct il_rx_pkt *pkt))
0cdc2136
SG		 423{
424 struct il_host_cmd cmd = {
425 .id = id,
426 .len = len,
427 .data = data,
428 };
429
430 cmd.flags |= CMD_ASYNC;
431 cmd.callback = callback;
432
433 return il_send_cmd_async(il, &cmd);
434}
435EXPORT_SYMBOL(il_send_cmd_pdu_async);
436
437/* default: IL_LED_BLINK(0) using blinking idx table */
438static int led_mode;
439module_param(led_mode, int, S_IRUGO);
e7392364
SG		 440MODULE_PARM_DESC(led_mode,
441 "0=system default, " "1=On(RF On)/Off(RF Off), 2=blinking");
0cdc2136
SG		 442
443/* Throughput OFF time(ms) ON time (ms)
444 * >300 25 25
445 * >200 to 300 40 40
446 * >100 to 200 55 55
447 * >70 to 100 65 65
448 * >50 to 70 75 75
449 * >20 to 50 85 85
450 * >10 to 20 95 95
451 * >5 to 10 110 110
452 * >1 to 5 130 130
453 * >0 to 1 167 167
454 * <=0 SOLID ON
455 */
456static const struct ieee80211_tpt_blink il_blink[] = {
1722f8e1
SG		 457 {.throughput = 0, .blink_time = 334},
458 {.throughput = 1 * 1024 - 1, .blink_time = 260},
459 {.throughput = 5 * 1024 - 1, .blink_time = 220},
460 {.throughput = 10 * 1024 - 1, .blink_time = 190},
461 {.throughput = 20 * 1024 - 1, .blink_time = 170},
462 {.throughput = 50 * 1024 - 1, .blink_time = 150},
463 {.throughput = 70 * 1024 - 1, .blink_time = 130},
464 {.throughput = 100 * 1024 - 1, .blink_time = 110},
465 {.throughput = 200 * 1024 - 1, .blink_time = 80},
466 {.throughput = 300 * 1024 - 1, .blink_time = 50},
0cdc2136
SG		 467};
468
469/*
470 * Adjust led blink rate to compensate on a MAC Clock difference on every HW
471 * Led blink rate analysis showed an average deviation of 0% on 3945,
472 * 5% on 4965 HW.
473 * Need to compensate on the led on/off time per HW according to the deviation
474 * to achieve the desired led frequency
475 * The calculation is: (100-averageDeviation)/100 * blinkTime
476 * For code efficiency the calculation will be:
477 * compensation = (100 - averageDeviation) * 64 / 100
478 * NewBlinkTime = (compensation * BlinkTime) / 64
479 */
e7392364
SG		 480static inline u8
481il_blink_compensation(struct il_priv *il, u8 time, u16 compensation)
0cdc2136
SG		 482{
483 if (!compensation) {
484 IL_ERR("undefined blink compensation: "
e7392364 485 "use pre-defined blinking time\n");
0cdc2136
SG		 486 return time;
487 }
488
e7392364 489 return (u8) ((time * compensation) >> 6);
0cdc2136
SG		 490}
491
492/* Set led pattern command */
e7392364
SG		 493static int
494il_led_cmd(struct il_priv *il, unsigned long on, unsigned long off)
0cdc2136
SG		 495{
496 struct il_led_cmd led_cmd = {
497 .id = IL_LED_LINK,
498 .interval = IL_DEF_LED_INTRVL
499 };
500 int ret;
501
502 if (!test_bit(S_READY, &il->status))
503 return -EBUSY;
504
505 if (il->blink_on == on && il->blink_off == off)
506 return 0;
507
508 if (off == 0) {
509 /* led is SOLID_ON */
510 on = IL_LED_SOLID;
511 }
512
513 D_LED("Led blink time compensation=%u\n",
89ef1ed2 514 il->cfg->led_compensation);
e7392364
SG		 515 led_cmd.on =
516 il_blink_compensation(il, on,
89ef1ed2 517 il->cfg->led_compensation);
e7392364
SG		 518 led_cmd.off =
519 il_blink_compensation(il, off,
89ef1ed2 520 il->cfg->led_compensation);
0cdc2136 521
c39ae9fd 522 ret = il->ops->led->cmd(il, &led_cmd);
0cdc2136
SG		 523 if (!ret) {
524 il->blink_on = on;
525 il->blink_off = off;
526 }
527 return ret;
528}
529
e7392364
SG		 530static void
531il_led_brightness_set(struct led_classdev *led_cdev,
532 enum led_brightness brightness)
0cdc2136
SG		 533{
534 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
535 unsigned long on = 0;
536
537 if (brightness > 0)
538 on = IL_LED_SOLID;
539
540 il_led_cmd(il, on, 0);
541}
542
e7392364
SG		 543static int
544il_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on,
545 unsigned long *delay_off)
0cdc2136
SG		 546{
547 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
548
549 return il_led_cmd(il, *delay_on, *delay_off);
550}
551
e7392364
SG		 552void
553il_leds_init(struct il_priv *il)
0cdc2136
SG		 554{
555 int mode = led_mode;
556 int ret;
557
558 if (mode == IL_LED_DEFAULT)
559 mode = il->cfg->led_mode;
560
e7392364
SG		 561 il->led.name =
562 kasprintf(GFP_KERNEL, "%s-led", wiphy_name(il->hw->wiphy));
0cdc2136
SG		 563 il->led.brightness_set = il_led_brightness_set;
564 il->led.blink_set = il_led_blink_set;
565 il->led.max_brightness = 1;
566
567 switch (mode) {
568 case IL_LED_DEFAULT:
569 WARN_ON(1);
570 break;
571 case IL_LED_BLINK:
572 il->led.default_trigger =
e7392364
SG		 573 ieee80211_create_tpt_led_trigger(il->hw,
574 IEEE80211_TPT_LEDTRIG_FL_CONNECTED,
575 il_blink,
576 ARRAY_SIZE(il_blink));
0cdc2136
SG		 577 break;
578 case IL_LED_RF_STATE:
e7392364 579 il->led.default_trigger = ieee80211_get_radio_led_name(il->hw);
0cdc2136
SG		 580 break;
581 }
582
583 ret = led_classdev_register(&il->pci_dev->dev, &il->led);
584 if (ret) {
585 kfree(il->led.name);
586 return;
587 }
588
589 il->led_registered = true;
590}
591EXPORT_SYMBOL(il_leds_init);
592
e7392364
SG		 593void
594il_leds_exit(struct il_priv *il)
0cdc2136
SG		 595{
596 if (!il->led_registered)
597 return;
598
599 led_classdev_unregister(&il->led);
600 kfree(il->led.name);
601}
602EXPORT_SYMBOL(il_leds_exit);
603
604/************************** EEPROM BANDS ****************************
605 *
606 * The il_eeprom_band definitions below provide the mapping from the
607 * EEPROM contents to the specific channel number supported for each
608 * band.
609 *
610 * For example, il_priv->eeprom.band_3_channels[4] from the band_3
611 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
612 * The specific geography and calibration information for that channel
613 * is contained in the eeprom map itself.
614 *
615 * During init, we copy the eeprom information and channel map
616 * information into il->channel_info_24/52 and il->channel_map_24/52
617 *
618 * channel_map_24/52 provides the idx in the channel_info array for a
619 * given channel. We have to have two separate maps as there is channel
620 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
621 * band_2
622 *
623 * A value of 0xff stored in the channel_map indicates that the channel
624 * is not supported by the hardware at all.
625 *
626 * A value of 0xfe in the channel_map indicates that the channel is not
627 * valid for Tx with the current hardware. This means that
628 * while the system can tune and receive on a given channel, it may not
629 * be able to associate or transmit any frames on that
630 * channel. There is no corresponding channel information for that
631 * entry.
632 *
633 *********************************************************************/
634
635/* 2.4 GHz */
636const u8 il_eeprom_band_1[14] = {
637 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
638};
639
640/* 5.2 GHz bands */
641static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */
642 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
643};
644
645static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */
646 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
647};
648
649static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */
650 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
651};
652
653static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */
654 145, 149, 153, 157, 161, 165
655};
656
e7392364 657static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */
0cdc2136
SG		 658 1, 2, 3, 4, 5, 6, 7
659};
660
e7392364 661static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */
0cdc2136
SG		 662 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
663};
664
665/******************************************************************************
666 *
667 * EEPROM related functions
668 *
669******************************************************************************/
670
e7392364
SG		 671static int
672il_eeprom_verify_signature(struct il_priv *il)
0cdc2136
SG		 673{
674 u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
675 int ret = 0;
676
677 D_EEPROM("EEPROM signature=0x%08x\n", gp);
678 switch (gp) {
679 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
680 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
681 break;
682 default:
e7392364 683 IL_ERR("bad EEPROM signature," "EEPROM_GP=0x%08x\n", gp);
0cdc2136
SG		 684 ret = -ENOENT;
685 break;
686 }
687 return ret;
688}
689
e7392364
SG		 690const u8 *
691il_eeprom_query_addr(const struct il_priv *il, size_t offset)
0cdc2136 692{
89ef1ed2 693 BUG_ON(offset >= il->cfg->eeprom_size);
0cdc2136
SG		 694 return &il->eeprom[offset];
695}
696EXPORT_SYMBOL(il_eeprom_query_addr);
697
e7392364 698u16
1722f8e1 699il_eeprom_query16(const struct il_priv *il, size_t offset)
0cdc2136
SG		 700{
701 if (!il->eeprom)
702 return 0;
e7392364 703 return (u16) il->eeprom[offset] | ((u16) il->eeprom[offset + 1] << 8);
0cdc2136
SG		 704}
705EXPORT_SYMBOL(il_eeprom_query16);
706
707/**
708 * il_eeprom_init - read EEPROM contents
709 *
710 * Load the EEPROM contents from adapter into il->eeprom
711 *
712 * NOTE: This routine uses the non-debug IO access functions.
713 */
e7392364
SG		 714int
715il_eeprom_init(struct il_priv *il)
0cdc2136
SG		 716{
717 __le16 *e;
718 u32 gp = _il_rd(il, CSR_EEPROM_GP);
719 int sz;
720 int ret;
721 u16 addr;
722
723 /* allocate eeprom */
89ef1ed2 724 sz = il->cfg->eeprom_size;
0cdc2136
SG		 725 D_EEPROM("NVM size = %d\n", sz);
726 il->eeprom = kzalloc(sz, GFP_KERNEL);
727 if (!il->eeprom) {
728 ret = -ENOMEM;
729 goto alloc_err;
730 }
e7392364 731 e = (__le16 *) il->eeprom;
0cdc2136 732
1600b875 733 il->ops->apm_init(il);
0cdc2136
SG		 734
735 ret = il_eeprom_verify_signature(il);
736 if (ret < 0) {
737 IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
738 ret = -ENOENT;
739 goto err;
740 }
741
742 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
1600b875 743 ret = il->ops->eeprom_acquire_semaphore(il);
0cdc2136
SG		 744 if (ret < 0) {
745 IL_ERR("Failed to acquire EEPROM semaphore.\n");
746 ret = -ENOENT;
747 goto err;
748 }
749
750 /* eeprom is an array of 16bit values */
751 for (addr = 0; addr < sz; addr += sizeof(u16)) {
752 u32 r;
753
754 _il_wr(il, CSR_EEPROM_REG,
e7392364 755 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
0cdc2136 756
e7392364
SG		 757 ret =
758 _il_poll_bit(il, CSR_EEPROM_REG,
759 CSR_EEPROM_REG_READ_VALID_MSK,
760 CSR_EEPROM_REG_READ_VALID_MSK,
761 IL_EEPROM_ACCESS_TIMEOUT);
0cdc2136 762 if (ret < 0) {
e7392364 763 IL_ERR("Time out reading EEPROM[%d]\n", addr);
0cdc2136
SG		 764 goto done;
765 }
766 r = _il_rd(il, CSR_EEPROM_REG);
767 e[addr / 2] = cpu_to_le16(r >> 16);
768 }
769
e7392364
SG		 770 D_EEPROM("NVM Type: %s, version: 0x%x\n", "EEPROM",
771 il_eeprom_query16(il, EEPROM_VERSION));
0cdc2136
SG		 772
773 ret = 0;
774done:
1600b875 775 il->ops->eeprom_release_semaphore(il);
0cdc2136
SG		 776
777err:
778 if (ret)
779 il_eeprom_free(il);
780 /* Reset chip to save power until we load uCode during "up". */
781 il_apm_stop(il);
782alloc_err:
783 return ret;
784}
785EXPORT_SYMBOL(il_eeprom_init);
786
e7392364
SG		 787void
788il_eeprom_free(struct il_priv *il)
0cdc2136
SG		 789{
790 kfree(il->eeprom);
791 il->eeprom = NULL;
792}
793EXPORT_SYMBOL(il_eeprom_free);
794
e7392364
SG		 795static void
796il_init_band_reference(const struct il_priv *il, int eep_band,
797 int *eeprom_ch_count,
798 const struct il_eeprom_channel **eeprom_ch_info,
1722f8e1 799 const u8 **eeprom_ch_idx)
0cdc2136 800{
93a984a4
SG		 801 u32 offset = il->cfg->regulatory_bands[eep_band - 1];
802
0cdc2136
SG		 803 switch (eep_band) {
804 case 1: /* 2.4GHz band */
805 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1);
e7392364
SG		 806 *eeprom_ch_info =
807 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
808 offset);
0cdc2136
SG		 809 *eeprom_ch_idx = il_eeprom_band_1;
810 break;
811 case 2: /* 4.9GHz band */
812 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2);
e7392364
SG		 813 *eeprom_ch_info =
814 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
815 offset);
0cdc2136
SG		 816 *eeprom_ch_idx = il_eeprom_band_2;
817 break;
818 case 3: /* 5.2GHz band */
819 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3);
e7392364
SG		 820 *eeprom_ch_info =
821 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
822 offset);
0cdc2136
SG		 823 *eeprom_ch_idx = il_eeprom_band_3;
824 break;
825 case 4: /* 5.5GHz band */
826 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4);
e7392364
SG		 827 *eeprom_ch_info =
828 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
829 offset);
0cdc2136
SG		 830 *eeprom_ch_idx = il_eeprom_band_4;
831 break;
832 case 5: /* 5.7GHz band */
833 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5);
e7392364
SG		 834 *eeprom_ch_info =
835 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
836 offset);
0cdc2136
SG		 837 *eeprom_ch_idx = il_eeprom_band_5;
838 break;
839 case 6: /* 2.4GHz ht40 channels */
840 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6);
e7392364
SG		 841 *eeprom_ch_info =
842 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
843 offset);
0cdc2136
SG		 844 *eeprom_ch_idx = il_eeprom_band_6;
845 break;
846 case 7: /* 5 GHz ht40 channels */
847 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7);
e7392364
SG		 848 *eeprom_ch_info =
849 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
850 offset);
0cdc2136
SG		 851 *eeprom_ch_idx = il_eeprom_band_7;
852 break;
853 default:
854 BUG();
855 }
856}
857
858#define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
859 ? # x " " : "")
860/**
861 * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il.
862 *
863 * Does not set up a command, or touch hardware.
864 */
e7392364
SG		 865static int
866il_mod_ht40_chan_info(struct il_priv *il, enum ieee80211_band band, u16 channel,
867 const struct il_eeprom_channel *eeprom_ch,
868 u8 clear_ht40_extension_channel)
0cdc2136
SG		 869{
870 struct il_channel_info *ch_info;
871
e7392364
SG		 872 ch_info =
873 (struct il_channel_info *)il_get_channel_info(il, band, channel);
0cdc2136
SG		 874
875 if (!il_is_channel_valid(ch_info))
876 return -1;
877
878 D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
e7392364
SG		 879 " Ad-Hoc %ssupported\n", ch_info->channel,
880 il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
881 CHECK_AND_PRINT(IBSS), CHECK_AND_PRINT(ACTIVE),
882 CHECK_AND_PRINT(RADAR), CHECK_AND_PRINT(WIDE),
883 CHECK_AND_PRINT(DFS), eeprom_ch->flags,
884 eeprom_ch->max_power_avg,
885 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) &&
886 !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" : "not ");
0cdc2136
SG		 887
888 ch_info->ht40_eeprom = *eeprom_ch;
889 ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
890 ch_info->ht40_flags = eeprom_ch->flags;
891 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
892 ch_info->ht40_extension_channel &=
e7392364 893 ~clear_ht40_extension_channel;
0cdc2136
SG		 894
895 return 0;
896}
897
898#define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
899 ? # x " " : "")
900
901/**
902 * il_init_channel_map - Set up driver's info for all possible channels
903 */
e7392364
SG		 904int
905il_init_channel_map(struct il_priv *il)
0cdc2136
SG		 906{
907 int eeprom_ch_count = 0;
908 const u8 *eeprom_ch_idx = NULL;
909 const struct il_eeprom_channel *eeprom_ch_info = NULL;
910 int band, ch;
911 struct il_channel_info *ch_info;
912
913 if (il->channel_count) {
914 D_EEPROM("Channel map already initialized.\n");
915 return 0;
916 }
917
918 D_EEPROM("Initializing regulatory info from EEPROM\n");
919
920 il->channel_count =
e7392364
SG		 921 ARRAY_SIZE(il_eeprom_band_1) + ARRAY_SIZE(il_eeprom_band_2) +
922 ARRAY_SIZE(il_eeprom_band_3) + ARRAY_SIZE(il_eeprom_band_4) +
0cdc2136
SG		 923 ARRAY_SIZE(il_eeprom_band_5);
924
e7392364 925 D_EEPROM("Parsing data for %d channels.\n", il->channel_count);
0cdc2136 926
e7392364
SG		 927 il->channel_info =
928 kzalloc(sizeof(struct il_channel_info) * il->channel_count,
929 GFP_KERNEL);
0cdc2136
SG		 930 if (!il->channel_info) {
931 IL_ERR("Could not allocate channel_info\n");
932 il->channel_count = 0;
933 return -ENOMEM;
934 }
935
936 ch_info = il->channel_info;
937
938 /* Loop through the 5 EEPROM bands adding them in order to the
939 * channel map we maintain (that contains additional information than
940 * what just in the EEPROM) */
941 for (band = 1; band <= 5; band++) {
942
943 il_init_band_reference(il, band, &eeprom_ch_count,
e7392364 944 &eeprom_ch_info, &eeprom_ch_idx);
0cdc2136
SG		 945
946 /* Loop through each band adding each of the channels */
947 for (ch = 0; ch < eeprom_ch_count; ch++) {
948 ch_info->channel = eeprom_ch_idx[ch];
e7392364
SG		 949 ch_info->band =
950 (band ==
951 1) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
0cdc2136
SG		 952
953 /* permanently store EEPROM's channel regulatory flags
954 * and max power in channel info database. */
955 ch_info->eeprom = eeprom_ch_info[ch];
956
957 /* Copy the run-time flags so they are there even on
958 * invalid channels */
959 ch_info->flags = eeprom_ch_info[ch].flags;
960 /* First write that ht40 is not enabled, and then enable
961 * one by one */
962 ch_info->ht40_extension_channel =
e7392364 963 IEEE80211_CHAN_NO_HT40;
0cdc2136
SG		 964
965 if (!(il_is_channel_valid(ch_info))) {
e7392364
SG		 966 D_EEPROM("Ch. %d Flags %x [%sGHz] - "
967 "No traffic\n", ch_info->channel,
968 ch_info->flags,
969 il_is_channel_a_band(ch_info) ? "5.2" :
970 "2.4");
0cdc2136
SG		 971 ch_info++;
972 continue;
973 }
974
975 /* Initialize regulatory-based run-time data */
976 ch_info->max_power_avg = ch_info->curr_txpow =
977 eeprom_ch_info[ch].max_power_avg;
978 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
979 ch_info->min_power = 0;
980
e7392364
SG		 981 D_EEPROM("Ch. %d [%sGHz] " "%s%s%s%s%s%s(0x%02x %ddBm):"
982 " Ad-Hoc %ssupported\n", ch_info->channel,
983 il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
984 CHECK_AND_PRINT_I(VALID),
985 CHECK_AND_PRINT_I(IBSS),
986 CHECK_AND_PRINT_I(ACTIVE),
987 CHECK_AND_PRINT_I(RADAR),
988 CHECK_AND_PRINT_I(WIDE),
989 CHECK_AND_PRINT_I(DFS),
990 eeprom_ch_info[ch].flags,
991 eeprom_ch_info[ch].max_power_avg,
992 ((eeprom_ch_info[ch].
993 flags & EEPROM_CHANNEL_IBSS) &&
994 !(eeprom_ch_info[ch].
995 flags & EEPROM_CHANNEL_RADAR)) ? "" :
996 "not ");
0cdc2136
SG		 997
998 ch_info++;
999 }
1000 }
1001
1002 /* Check if we do have HT40 channels */
93a984a4
SG		 1003 if (il->cfg->regulatory_bands[5] == EEPROM_REGULATORY_BAND_NO_HT40 &&
1004 il->cfg->regulatory_bands[6] == EEPROM_REGULATORY_BAND_NO_HT40)
0cdc2136
SG		 1005 return 0;
1006
1007 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
1008 for (band = 6; band <= 7; band++) {
1009 enum ieee80211_band ieeeband;
1010
1011 il_init_band_reference(il, band, &eeprom_ch_count,
e7392364 1012 &eeprom_ch_info, &eeprom_ch_idx);
0cdc2136
SG		 1013
1014 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
1015 ieeeband =
e7392364 1016 (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
0cdc2136
SG		 1017
1018 /* Loop through each band adding each of the channels */
1019 for (ch = 0; ch < eeprom_ch_count; ch++) {
1020 /* Set up driver's info for lower half */
e7392364
SG		 1021 il_mod_ht40_chan_info(il, ieeeband, eeprom_ch_idx[ch],
1022 &eeprom_ch_info[ch],
1023 IEEE80211_CHAN_NO_HT40PLUS);
0cdc2136
SG		 1024
1025 /* Set up driver's info for upper half */
1026 il_mod_ht40_chan_info(il, ieeeband,
e7392364
SG		 1027 eeprom_ch_idx[ch] + 4,
1028 &eeprom_ch_info[ch],
1029 IEEE80211_CHAN_NO_HT40MINUS);
0cdc2136
SG		 1030 }
1031 }
1032
1033 return 0;
1034}
1035EXPORT_SYMBOL(il_init_channel_map);
1036
1037/*
1038 * il_free_channel_map - undo allocations in il_init_channel_map
1039 */
e7392364
SG		 1040void
1041il_free_channel_map(struct il_priv *il)
0cdc2136
SG		 1042{
1043 kfree(il->channel_info);
1044 il->channel_count = 0;
1045}
1046EXPORT_SYMBOL(il_free_channel_map);
1047
1048/**
1049 * il_get_channel_info - Find driver's ilate channel info
1050 *
1051 * Based on band and channel number.
1052 */
e7392364
SG		 1053const struct il_channel_info *
1054il_get_channel_info(const struct il_priv *il, enum ieee80211_band band,
1055 u16 channel)
0cdc2136
SG		 1056{
1057 int i;
1058
1059 switch (band) {
1060 case IEEE80211_BAND_5GHZ:
1061 for (i = 14; i < il->channel_count; i++) {
1062 if (il->channel_info[i].channel == channel)
1063 return &il->channel_info[i];
1064 }
1065 break;
1066 case IEEE80211_BAND_2GHZ:
1067 if (channel >= 1 && channel <= 14)
1068 return &il->channel_info[channel - 1];
1069 break;
1070 default:
1071 BUG();
1072 }
1073
1074 return NULL;
1075}
1076EXPORT_SYMBOL(il_get_channel_info);
1077
1078/*
1079 * Setting power level allows the card to go to sleep when not busy.
1080 *
1081 * We calculate a sleep command based on the required latency, which
1082 * we get from mac80211. In order to handle thermal throttling, we can
1083 * also use pre-defined power levels.
1084 */
1085
1086/*
1087 * This defines the old power levels. They are still used by default
1088 * (level 1) and for thermal throttle (levels 3 through 5)
1089 */
1090
1091struct il_power_vec_entry {
1092 struct il_powertable_cmd cmd;
e7392364 1093 u8 no_dtim; /* number of skip dtim */
0cdc2136
SG		 1094};
1095
e7392364
SG		 1096static void
1097il_power_sleep_cam_cmd(struct il_priv *il, struct il_powertable_cmd *cmd)
0cdc2136
SG		 1098{
1099 memset(cmd, 0, sizeof(*cmd));
1100
1101 if (il->power_data.pci_pm)
1102 cmd->flags |= IL_POWER_PCI_PM_MSK;
1103
1104 D_POWER("Sleep command for CAM\n");
1105}
1106
1107static int
1108il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd)
1109{
1110 D_POWER("Sending power/sleep command\n");
1111 D_POWER("Flags value = 0x%08X\n", cmd->flags);
e7392364
SG		 1112 D_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1113 D_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1114 D_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1115 le32_to_cpu(cmd->sleep_interval[0]),
1116 le32_to_cpu(cmd->sleep_interval[1]),
1117 le32_to_cpu(cmd->sleep_interval[2]),
1118 le32_to_cpu(cmd->sleep_interval[3]),
1119 le32_to_cpu(cmd->sleep_interval[4]));
0cdc2136
SG		 1120
1121 return il_send_cmd_pdu(il, C_POWER_TBL,
e7392364 1122 sizeof(struct il_powertable_cmd), cmd);
0cdc2136
SG		 1123}
1124
1125int
e7392364 1126il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd, bool force)
0cdc2136
SG		 1127{
1128 int ret;
1129 bool update_chains;
1130
1131 lockdep_assert_held(&il->mutex);
1132
1133 /* Don't update the RX chain when chain noise calibration is running */
1134 update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE ||
e7392364 1135 il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE;
0cdc2136
SG		 1136
1137 if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
1138 return 0;
1139
1140 if (!il_is_ready_rf(il))
1141 return -EIO;
1142
1143 /* scan complete use sleep_power_next, need to be updated */
1144 memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
1145 if (test_bit(S_SCANNING, &il->status) && !force) {
1146 D_INFO("Defer power set mode while scanning\n");
1147 return 0;
1148 }
1149
1150 if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)
1151 set_bit(S_POWER_PMI, &il->status);
1152
1153 ret = il_set_power(il, cmd);
1154 if (!ret) {
1155 if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK))
1156 clear_bit(S_POWER_PMI, &il->status);
1157
1600b875
SG		 1158 if (il->ops->update_chain_flags && update_chains)
1159 il->ops->update_chain_flags(il);
1160 else if (il->ops->update_chain_flags)
e7392364
SG		 1161 D_POWER("Cannot update the power, chain noise "
1162 "calibration running: %d\n",
1163 il->chain_noise_data.state);
0cdc2136
SG		 1164
1165 memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd));
1166 } else
1167 IL_ERR("set power fail, ret = %d", ret);
1168
1169 return ret;
1170}
1171
e7392364
SG		 1172int
1173il_power_update_mode(struct il_priv *il, bool force)
0cdc2136
SG		 1174{
1175 struct il_powertable_cmd cmd;
1176
1177 il_power_sleep_cam_cmd(il, &cmd);
1178 return il_power_set_mode(il, &cmd, force);
1179}
1180EXPORT_SYMBOL(il_power_update_mode);
1181
1182/* initialize to default */
e7392364
SG		 1183void
1184il_power_initialize(struct il_priv *il)
0cdc2136
SG		 1185{
1186 u16 lctl = il_pcie_link_ctl(il);
1187
1188 il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
1189
1190 il->power_data.debug_sleep_level_override = -1;
1191
e7392364 1192 memset(&il->power_data.sleep_cmd, 0, sizeof(il->power_data.sleep_cmd));
0cdc2136
SG		 1193}
1194EXPORT_SYMBOL(il_power_initialize);
1195
1196/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
1197 * sending probe req. This should be set long enough to hear probe responses
1198 * from more than one AP. */
e7392364 1199#define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
0cdc2136
SG		 1200#define IL_ACTIVE_DWELL_TIME_52 (20)
1201
1202#define IL_ACTIVE_DWELL_FACTOR_24GHZ (3)
1203#define IL_ACTIVE_DWELL_FACTOR_52GHZ (2)
1204
1205/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
1206 * Must be set longer than active dwell time.
1207 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
e7392364 1208#define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
0cdc2136
SG		 1209#define IL_PASSIVE_DWELL_TIME_52 (10)
1210#define IL_PASSIVE_DWELL_BASE (100)
1211#define IL_CHANNEL_TUNE_TIME 5
1212
e7392364
SG		 1213static int
1214il_send_scan_abort(struct il_priv *il)
0cdc2136
SG		 1215{
1216 int ret;
1217 struct il_rx_pkt *pkt;
1218 struct il_host_cmd cmd = {
1219 .id = C_SCAN_ABORT,
1220 .flags = CMD_WANT_SKB,
1221 };
1222
1223 /* Exit instantly with error when device is not ready
1224 * to receive scan abort command or it does not perform
1225 * hardware scan currently */
1226 if (!test_bit(S_READY, &il->status) ||
1227 !test_bit(S_GEO_CONFIGURED, &il->status) ||
1228 !test_bit(S_SCAN_HW, &il->status) ||
1229 test_bit(S_FW_ERROR, &il->status) ||
1230 test_bit(S_EXIT_PENDING, &il->status))
1231 return -EIO;
1232
1233 ret = il_send_cmd_sync(il, &cmd);
1234 if (ret)
1235 return ret;
1236
1237 pkt = (struct il_rx_pkt *)cmd.reply_page;
1238 if (pkt->u.status != CAN_ABORT_STATUS) {
1239 /* The scan abort will return 1 for success or
1240 * 2 for "failure". A failure condition can be
1241 * due to simply not being in an active scan which
1242 * can occur if we send the scan abort before we
1243 * the microcode has notified us that a scan is
1244 * completed. */
1245 D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status);
1246 ret = -EIO;
1247 }
1248
1249 il_free_pages(il, cmd.reply_page);
1250 return ret;
1251}
1252
e7392364
SG		 1253static void
1254il_complete_scan(struct il_priv *il, bool aborted)
0cdc2136
SG		 1255{
1256 /* check if scan was requested from mac80211 */
1257 if (il->scan_request) {
1258 D_SCAN("Complete scan in mac80211\n");
1259 ieee80211_scan_completed(il->hw, aborted);
1260 }
1261
1262 il->scan_vif = NULL;
1263 il->scan_request = NULL;
1264}
1265
e7392364
SG		 1266void
1267il_force_scan_end(struct il_priv *il)
0cdc2136
SG		 1268{
1269 lockdep_assert_held(&il->mutex);
1270
1271 if (!test_bit(S_SCANNING, &il->status)) {
1272 D_SCAN("Forcing scan end while not scanning\n");
1273 return;
1274 }
1275
1276 D_SCAN("Forcing scan end\n");
1277 clear_bit(S_SCANNING, &il->status);
1278 clear_bit(S_SCAN_HW, &il->status);
1279 clear_bit(S_SCAN_ABORTING, &il->status);
1280 il_complete_scan(il, true);
1281}
1282
e7392364
SG		 1283static void
1284il_do_scan_abort(struct il_priv *il)
0cdc2136
SG		 1285{
1286 int ret;
1287
1288 lockdep_assert_held(&il->mutex);
1289
1290 if (!test_bit(S_SCANNING, &il->status)) {
1291 D_SCAN("Not performing scan to abort\n");
1292 return;
1293 }
1294
1295 if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) {
1296 D_SCAN("Scan abort in progress\n");
1297 return;
1298 }
1299
1300 ret = il_send_scan_abort(il);
1301 if (ret) {
1302 D_SCAN("Send scan abort failed %d\n", ret);
1303 il_force_scan_end(il);
1304 } else
1305 D_SCAN("Successfully send scan abort\n");
1306}
1307
1308/**
1309 * il_scan_cancel - Cancel any currently executing HW scan
1310 */
e7392364
SG		 1311int
1312il_scan_cancel(struct il_priv *il)
0cdc2136
SG		 1313{
1314 D_SCAN("Queuing abort scan\n");
1315 queue_work(il->workqueue, &il->abort_scan);
1316 return 0;
1317}
1318EXPORT_SYMBOL(il_scan_cancel);
1319
1320/**
1321 * il_scan_cancel_timeout - Cancel any currently executing HW scan
1322 * @ms: amount of time to wait (in milliseconds) for scan to abort
1323 *
1324 */
e7392364
SG		 1325int
1326il_scan_cancel_timeout(struct il_priv *il, unsigned long ms)
0cdc2136
SG		 1327{
1328 unsigned long timeout = jiffies + msecs_to_jiffies(ms);
1329
1330 lockdep_assert_held(&il->mutex);
1331
1332 D_SCAN("Scan cancel timeout\n");
1333
1334 il_do_scan_abort(il);
1335
1336 while (time_before_eq(jiffies, timeout)) {
1337 if (!test_bit(S_SCAN_HW, &il->status))
1338 break;
1339 msleep(20);
1340 }
1341
1342 return test_bit(S_SCAN_HW, &il->status);
1343}
1344EXPORT_SYMBOL(il_scan_cancel_timeout);
1345
1346/* Service response to C_SCAN (0x80) */
e7392364
SG		 1347static void
1348il_hdl_scan(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1349{
1350#ifdef CONFIG_IWLEGACY_DEBUG
1351 struct il_rx_pkt *pkt = rxb_addr(rxb);
1352 struct il_scanreq_notification *notif =
1353 (struct il_scanreq_notification *)pkt->u.raw;
1354
1355 D_SCAN("Scan request status = 0x%x\n", notif->status);
1356#endif
1357}
1358
1359/* Service N_SCAN_START (0x82) */
e7392364
SG		 1360static void
1361il_hdl_scan_start(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1362{
1363 struct il_rx_pkt *pkt = rxb_addr(rxb);
1364 struct il_scanstart_notification *notif =
1365 (struct il_scanstart_notification *)pkt->u.raw;
1366 il->scan_start_tsf = le32_to_cpu(notif->tsf_low);
e7392364
SG		 1367 D_SCAN("Scan start: " "%d [802.11%s] "
1368 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", notif->channel,
1369 notif->band ? "bg" : "a", le32_to_cpu(notif->tsf_high),
1370 le32_to_cpu(notif->tsf_low), notif->status, notif->beacon_timer);
0cdc2136
SG		 1371}
1372
1373/* Service N_SCAN_RESULTS (0x83) */
e7392364
SG		 1374static void
1375il_hdl_scan_results(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1376{
1377#ifdef CONFIG_IWLEGACY_DEBUG
1378 struct il_rx_pkt *pkt = rxb_addr(rxb);
1379 struct il_scanresults_notification *notif =
1380 (struct il_scanresults_notification *)pkt->u.raw;
1381
e7392364
SG		 1382 D_SCAN("Scan ch.res: " "%d [802.11%s] " "(TSF: 0x%08X:%08X) - %d "
1383 "elapsed=%lu usec\n", notif->channel, notif->band ? "bg" : "a",
1384 le32_to_cpu(notif->tsf_high), le32_to_cpu(notif->tsf_low),
1385 le32_to_cpu(notif->stats[0]),
1386 le32_to_cpu(notif->tsf_low) - il->scan_start_tsf);
0cdc2136
SG		 1387#endif
1388}
1389
1390/* Service N_SCAN_COMPLETE (0x84) */
e7392364
SG		 1391static void
1392il_hdl_scan_complete(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1393{
1394
1395#ifdef CONFIG_IWLEGACY_DEBUG
1396 struct il_rx_pkt *pkt = rxb_addr(rxb);
1397 struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
1398#endif
1399
e7392364
SG		 1400 D_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
1401 scan_notif->scanned_channels, scan_notif->tsf_low,
1402 scan_notif->tsf_high, scan_notif->status);
0cdc2136
SG		 1403
1404 /* The HW is no longer scanning */
1405 clear_bit(S_SCAN_HW, &il->status);
1406
1407 D_SCAN("Scan on %sGHz took %dms\n",
e7392364
SG		 1408 (il->scan_band == IEEE80211_BAND_2GHZ) ? "2.4" : "5.2",
1409 jiffies_to_msecs(jiffies - il->scan_start));
0cdc2136
SG		 1410
1411 queue_work(il->workqueue, &il->scan_completed);
1412}
1413
e7392364
SG		 1414void
1415il_setup_rx_scan_handlers(struct il_priv *il)
0cdc2136
SG		 1416{
1417 /* scan handlers */
1418 il->handlers[C_SCAN] = il_hdl_scan;
e7392364
SG		 1419 il->handlers[N_SCAN_START] = il_hdl_scan_start;
1420 il->handlers[N_SCAN_RESULTS] = il_hdl_scan_results;
1421 il->handlers[N_SCAN_COMPLETE] = il_hdl_scan_complete;
0cdc2136
SG		 1422}
1423EXPORT_SYMBOL(il_setup_rx_scan_handlers);
1424
e7392364
SG		 1425inline u16
1426il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1427 u8 n_probes)
0cdc2136
SG		 1428{
1429 if (band == IEEE80211_BAND_5GHZ)
1430 return IL_ACTIVE_DWELL_TIME_52 +
e7392364 1431 IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
0cdc2136
SG		 1432 else
1433 return IL_ACTIVE_DWELL_TIME_24 +
e7392364 1434 IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
0cdc2136
SG		 1435}
1436EXPORT_SYMBOL(il_get_active_dwell_time);
1437
e7392364 1438u16
1722f8e1
SG		 1439il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1440 struct ieee80211_vif *vif)
0cdc2136 1441{
0cdc2136
SG		 1442 u16 value;
1443
e7392364
SG		 1444 u16 passive =
1445 (band ==
1446 IEEE80211_BAND_2GHZ) ? IL_PASSIVE_DWELL_BASE +
1447 IL_PASSIVE_DWELL_TIME_24 : IL_PASSIVE_DWELL_BASE +
1448 IL_PASSIVE_DWELL_TIME_52;
0cdc2136
SG		 1449
1450 if (il_is_any_associated(il)) {
1451 /*
1452 * If we're associated, we clamp the maximum passive
1453 * dwell time to be 98% of the smallest beacon interval
1454 * (minus 2 * channel tune time)
1455 */
83007196 1456 value = il->vif ? il->vif->bss_conf.beacon_int : 0;
0cdc2136
SG		 1457 if (value > IL_PASSIVE_DWELL_BASE || !value)
1458 value = IL_PASSIVE_DWELL_BASE;
1459 value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2;
1460 passive = min(value, passive);
1461 }
1462
1463 return passive;
1464}
1465EXPORT_SYMBOL(il_get_passive_dwell_time);
1466
e7392364
SG		 1467void
1468il_init_scan_params(struct il_priv *il)
0cdc2136
SG		 1469{
1470 u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1;
1471 if (!il->scan_tx_ant[IEEE80211_BAND_5GHZ])
1472 il->scan_tx_ant[IEEE80211_BAND_5GHZ] = ant_idx;
1473 if (!il->scan_tx_ant[IEEE80211_BAND_2GHZ])
1474 il->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx;
1475}
1476EXPORT_SYMBOL(il_init_scan_params);
1477
e7392364
SG		 1478static int
1479il_scan_initiate(struct il_priv *il, struct ieee80211_vif *vif)
0cdc2136
SG		 1480{
1481 int ret;
1482
1483 lockdep_assert_held(&il->mutex);
1484
c39ae9fd 1485 if (WARN_ON(!il->ops->utils->request_scan))
0cdc2136
SG		 1486 return -EOPNOTSUPP;
1487
1488 cancel_delayed_work(&il->scan_check);
1489
1490 if (!il_is_ready_rf(il)) {
1491 IL_WARN("Request scan called when driver not ready.\n");
1492 return -EIO;
1493 }
1494
1495 if (test_bit(S_SCAN_HW, &il->status)) {
e7392364 1496 D_SCAN("Multiple concurrent scan requests in parallel.\n");
0cdc2136
SG		 1497 return -EBUSY;
1498 }
1499
1500 if (test_bit(S_SCAN_ABORTING, &il->status)) {
1501 D_SCAN("Scan request while abort pending.\n");
1502 return -EBUSY;
1503 }
1504
1505 D_SCAN("Starting scan...\n");
1506
1507 set_bit(S_SCANNING, &il->status);
1508 il->scan_start = jiffies;
1509
c39ae9fd 1510 ret = il->ops->utils->request_scan(il, vif);
0cdc2136
SG		 1511 if (ret) {
1512 clear_bit(S_SCANNING, &il->status);
1513 return ret;
1514 }
1515
1516 queue_delayed_work(il->workqueue, &il->scan_check,
1517 IL_SCAN_CHECK_WATCHDOG);
1518
1519 return 0;
1520}
1521
e7392364
SG		 1522int
1523il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1524 struct cfg80211_scan_request *req)
0cdc2136
SG		 1525{
1526 struct il_priv *il = hw->priv;
1527 int ret;
1528
1529 D_MAC80211("enter\n");
1530
1531 if (req->n_channels == 0)
1532 return -EINVAL;
1533
1534 mutex_lock(&il->mutex);
1535
1536 if (test_bit(S_SCANNING, &il->status)) {
1537 D_SCAN("Scan already in progress.\n");
1538 ret = -EAGAIN;
1539 goto out_unlock;
1540 }
1541
1542 /* mac80211 will only ask for one band at a time */
1543 il->scan_request = req;
1544 il->scan_vif = vif;
1545 il->scan_band = req->channels[0]->band;
1546
1547 ret = il_scan_initiate(il, vif);
1548
1549 D_MAC80211("leave\n");
1550
1551out_unlock:
1552 mutex_unlock(&il->mutex);
1553
1554 return ret;
1555}
1556EXPORT_SYMBOL(il_mac_hw_scan);
1557
e7392364
SG		 1558static void
1559il_bg_scan_check(struct work_struct *data)
0cdc2136
SG		 1560{
1561 struct il_priv *il =
1562 container_of(data, struct il_priv, scan_check.work);
1563
1564 D_SCAN("Scan check work\n");
1565
1566 /* Since we are here firmware does not finish scan and
1567 * most likely is in bad shape, so we don't bother to
1568 * send abort command, just force scan complete to mac80211 */
1569 mutex_lock(&il->mutex);
1570 il_force_scan_end(il);
1571 mutex_unlock(&il->mutex);
1572}
1573
1574/**
1575 * il_fill_probe_req - fill in all required fields and IE for probe request
1576 */
1577
1578u16
1579il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1722f8e1 1580 const u8 *ta, const u8 *ies, int ie_len, int left)
0cdc2136
SG		 1581{
1582 int len = 0;
1583 u8 *pos = NULL;
1584
1585 /* Make sure there is enough space for the probe request,
1586 * two mandatory IEs and the data */
1587 left -= 24;
1588 if (left < 0)
1589 return 0;
1590
1591 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
1592 memcpy(frame->da, il_bcast_addr, ETH_ALEN);
1593 memcpy(frame->sa, ta, ETH_ALEN);
1594 memcpy(frame->bssid, il_bcast_addr, ETH_ALEN);
1595 frame->seq_ctrl = 0;
1596
1597 len += 24;
1598
1599 /* ...next IE... */
1600 pos = &frame->u.probe_req.variable[0];
1601
1602 /* fill in our indirect SSID IE */
1603 left -= 2;
1604 if (left < 0)
1605 return 0;
1606 *pos++ = WLAN_EID_SSID;
1607 *pos++ = 0;
1608
1609 len += 2;
1610
1611 if (WARN_ON(left < ie_len))
1612 return len;
1613
1614 if (ies && ie_len) {
1615 memcpy(pos, ies, ie_len);
1616 len += ie_len;
1617 }
1618
e7392364 1619 return (u16) len;
0cdc2136
SG		 1620}
1621EXPORT_SYMBOL(il_fill_probe_req);
1622
e7392364
SG		 1623static void
1624il_bg_abort_scan(struct work_struct *work)
0cdc2136
SG		 1625{
1626 struct il_priv *il = container_of(work, struct il_priv, abort_scan);
1627
1628 D_SCAN("Abort scan work\n");
1629
1630 /* We keep scan_check work queued in case when firmware will not
1631 * report back scan completed notification */
1632 mutex_lock(&il->mutex);
1633 il_scan_cancel_timeout(il, 200);
1634 mutex_unlock(&il->mutex);
1635}
1636
e7392364
SG		 1637static void
1638il_bg_scan_completed(struct work_struct *work)
0cdc2136 1639{
e7392364 1640 struct il_priv *il = container_of(work, struct il_priv, scan_completed);
0cdc2136
SG		 1641 bool aborted;
1642
1643 D_SCAN("Completed scan.\n");
1644
1645 cancel_delayed_work(&il->scan_check);
1646
1647 mutex_lock(&il->mutex);
1648
1649 aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status);
1650 if (aborted)
1651 D_SCAN("Aborted scan completed.\n");
1652
1653 if (!test_and_clear_bit(S_SCANNING, &il->status)) {
1654 D_SCAN("Scan already completed.\n");
1655 goto out_settings;
1656 }
1657
1658 il_complete_scan(il, aborted);
1659
1660out_settings:
1661 /* Can we still talk to firmware ? */
1662 if (!il_is_ready_rf(il))
1663 goto out;
1664
1665 /*
1666 * We do not commit power settings while scan is pending,
1667 * do it now if the settings changed.
1668 */
1669 il_power_set_mode(il, &il->power_data.sleep_cmd_next, false);
1670 il_set_tx_power(il, il->tx_power_next, false);
1671
c39ae9fd 1672 il->ops->utils->post_scan(il);
0cdc2136
SG		 1673
1674out:
1675 mutex_unlock(&il->mutex);
1676}
1677
e7392364
SG		 1678void
1679il_setup_scan_deferred_work(struct il_priv *il)
0cdc2136
SG		 1680{
1681 INIT_WORK(&il->scan_completed, il_bg_scan_completed);
1682 INIT_WORK(&il->abort_scan, il_bg_abort_scan);
1683 INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check);
1684}
1685EXPORT_SYMBOL(il_setup_scan_deferred_work);
1686
e7392364
SG		 1687void
1688il_cancel_scan_deferred_work(struct il_priv *il)
0cdc2136
SG		 1689{
1690 cancel_work_sync(&il->abort_scan);
1691 cancel_work_sync(&il->scan_completed);
1692
1693 if (cancel_delayed_work_sync(&il->scan_check)) {
1694 mutex_lock(&il->mutex);
1695 il_force_scan_end(il);
1696 mutex_unlock(&il->mutex);
1697 }
1698}
1699EXPORT_SYMBOL(il_cancel_scan_deferred_work);
1700
1701/* il->sta_lock must be held */
e7392364
SG		 1702static void
1703il_sta_ucode_activate(struct il_priv *il, u8 sta_id)
0cdc2136
SG		 1704{
1705
1706 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE))
e7392364
SG		 1707 IL_ERR("ACTIVATE a non DRIVER active station id %u addr %pM\n",
1708 sta_id, il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1709
1710 if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) {
e7392364
SG		 1711 D_ASSOC("STA id %u addr %pM already present"
1712 " in uCode (according to driver)\n", sta_id,
1713 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1714 } else {
1715 il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE;
e7392364
SG		 1716 D_ASSOC("Added STA id %u addr %pM to uCode\n", sta_id,
1717 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1718 }
1719}
1720
e7392364
SG		 1721static int
1722il_process_add_sta_resp(struct il_priv *il, struct il_addsta_cmd *addsta,
1723 struct il_rx_pkt *pkt, bool sync)
0cdc2136
SG		 1724{
1725 u8 sta_id = addsta->sta.sta_id;
1726 unsigned long flags;
1727 int ret = -EIO;
1728
1729 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
e7392364 1730 IL_ERR("Bad return from C_ADD_STA (0x%08X)\n", pkt->hdr.flags);
0cdc2136
SG		 1731 return ret;
1732 }
1733
e7392364 1734 D_INFO("Processing response for adding station %u\n", sta_id);
0cdc2136
SG		 1735
1736 spin_lock_irqsave(&il->sta_lock, flags);
1737
1738 switch (pkt->u.add_sta.status) {
1739 case ADD_STA_SUCCESS_MSK:
1740 D_INFO("C_ADD_STA PASSED\n");
1741 il_sta_ucode_activate(il, sta_id);
1742 ret = 0;
1743 break;
1744 case ADD_STA_NO_ROOM_IN_TBL:
e7392364 1745 IL_ERR("Adding station %d failed, no room in table.\n", sta_id);
0cdc2136
SG		 1746 break;
1747 case ADD_STA_NO_BLOCK_ACK_RESOURCE:
e7392364
SG		 1748 IL_ERR("Adding station %d failed, no block ack resource.\n",
1749 sta_id);
0cdc2136
SG		 1750 break;
1751 case ADD_STA_MODIFY_NON_EXIST_STA:
1752 IL_ERR("Attempting to modify non-existing station %d\n",
e7392364 1753 sta_id);
0cdc2136
SG		 1754 break;
1755 default:
e7392364 1756 D_ASSOC("Received C_ADD_STA:(0x%08X)\n", pkt->u.add_sta.status);
0cdc2136
SG		 1757 break;
1758 }
1759
1760 D_INFO("%s station id %u addr %pM\n",
e7392364
SG		 1761 il->stations[sta_id].sta.mode ==
1762 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", sta_id,
1763 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1764
1765 /*
1766 * XXX: The MAC address in the command buffer is often changed from
1767 * the original sent to the device. That is, the MAC address
1768 * written to the command buffer often is not the same MAC address
1769 * read from the command buffer when the command returns. This
1770 * issue has not yet been resolved and this debugging is left to
1771 * observe the problem.
1772 */
1773 D_INFO("%s station according to cmd buffer %pM\n",
e7392364
SG		 1774 il->stations[sta_id].sta.mode ==
1775 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", addsta->sta.addr);
0cdc2136
SG		 1776 spin_unlock_irqrestore(&il->sta_lock, flags);
1777
1778 return ret;
1779}
1780
e7392364
SG		 1781static void
1782il_add_sta_callback(struct il_priv *il, struct il_device_cmd *cmd,
1783 struct il_rx_pkt *pkt)
0cdc2136 1784{
e7392364 1785 struct il_addsta_cmd *addsta = (struct il_addsta_cmd *)cmd->cmd.payload;
0cdc2136
SG		 1786
1787 il_process_add_sta_resp(il, addsta, pkt, false);
1788
1789}
1790
e7392364
SG		 1791int
1792il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags)
0cdc2136
SG		 1793{
1794 struct il_rx_pkt *pkt = NULL;
1795 int ret = 0;
1796 u8 data[sizeof(*sta)];
1797 struct il_host_cmd cmd = {
1798 .id = C_ADD_STA,
1799 .flags = flags,
1800 .data = data,
1801 };
1802 u8 sta_id __maybe_unused = sta->sta.sta_id;
1803
e7392364
SG		 1804 D_INFO("Adding sta %u (%pM) %ssynchronously\n", sta_id, sta->sta.addr,
1805 flags & CMD_ASYNC ? "a" : "");
0cdc2136
SG		 1806
1807 if (flags & CMD_ASYNC)
1808 cmd.callback = il_add_sta_callback;
1809 else {
1810 cmd.flags |= CMD_WANT_SKB;
1811 might_sleep();
1812 }
1813
c39ae9fd 1814 cmd.len = il->ops->utils->build_addsta_hcmd(sta, data);
0cdc2136
SG		 1815 ret = il_send_cmd(il, &cmd);
1816
1817 if (ret || (flags & CMD_ASYNC))
1818 return ret;
1819
1820 if (ret == 0) {
1821 pkt = (struct il_rx_pkt *)cmd.reply_page;
1822 ret = il_process_add_sta_resp(il, sta, pkt, true);
1823 }
1824 il_free_pages(il, cmd.reply_page);
1825
1826 return ret;
1827}
1828EXPORT_SYMBOL(il_send_add_sta);
1829
e7392364 1830static void
83007196 1831il_set_ht_add_station(struct il_priv *il, u8 idx, struct ieee80211_sta *sta)
0cdc2136
SG		 1832{
1833 struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->ht_cap;
1834 __le32 sta_flags;
1835 u8 mimo_ps_mode;
1836
1837 if (!sta || !sta_ht_inf->ht_supported)
1838 goto done;
1839
1840 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_SM_PS) >> 2;
1841 D_ASSOC("spatial multiplexing power save mode: %s\n",
1722f8e1
SG		 1842 (mimo_ps_mode == WLAN_HT_CAP_SM_PS_STATIC) ? "static" :
1843 (mimo_ps_mode == WLAN_HT_CAP_SM_PS_DYNAMIC) ? "dynamic" :
1844 "disabled");
0cdc2136
SG		 1845
1846 sta_flags = il->stations[idx].sta.station_flags;
1847
1848 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
1849
1850 switch (mimo_ps_mode) {
1851 case WLAN_HT_CAP_SM_PS_STATIC:
1852 sta_flags |= STA_FLG_MIMO_DIS_MSK;
1853 break;
1854 case WLAN_HT_CAP_SM_PS_DYNAMIC:
1855 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
1856 break;
1857 case WLAN_HT_CAP_SM_PS_DISABLED:
1858 break;
1859 default:
1860 IL_WARN("Invalid MIMO PS mode %d\n", mimo_ps_mode);
1861 break;
1862 }
1863
e7392364
SG		 1864 sta_flags |=
1865 cpu_to_le32((u32) sta_ht_inf->
1866 ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
0cdc2136 1867
e7392364
SG		 1868 sta_flags |=
1869 cpu_to_le32((u32) sta_ht_inf->
1870 ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
0cdc2136 1871
83007196 1872 if (il_is_ht40_tx_allowed(il, &sta->ht_cap))
0cdc2136
SG		 1873 sta_flags |= STA_FLG_HT40_EN_MSK;
1874 else
1875 sta_flags &= ~STA_FLG_HT40_EN_MSK;
1876
1877 il->stations[idx].sta.station_flags = sta_flags;
e7392364 1878done:
0cdc2136
SG		 1879 return;
1880}
1881
1882/**
1883 * il_prep_station - Prepare station information for addition
1884 *
1885 * should be called with sta_lock held
1886 */
e7392364 1887u8
83007196
SG		 1888il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
1889 struct ieee80211_sta *sta)
0cdc2136
SG		 1890{
1891 struct il_station_entry *station;
1892 int i;
1893 u8 sta_id = IL_INVALID_STATION;
1894 u16 rate;
1895
1896 if (is_ap)
8f9e5645 1897 sta_id = IL_AP_ID;
0cdc2136 1898 else if (is_broadcast_ether_addr(addr))
b16db50a 1899 sta_id = il->hw_params.bcast_id;
0cdc2136
SG		 1900 else
1901 for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) {
e7392364
SG		 1902 if (!compare_ether_addr
1903 (il->stations[i].sta.sta.addr, addr)) {
0cdc2136
SG		 1904 sta_id = i;
1905 break;
1906 }
1907
1908 if (!il->stations[i].used &&
1909 sta_id == IL_INVALID_STATION)
1910 sta_id = i;
1911 }
1912
1913 /*
1914 * These two conditions have the same outcome, but keep them
1915 * separate
1916 */
1917 if (unlikely(sta_id == IL_INVALID_STATION))
1918 return sta_id;
1919
1920 /*
1921 * uCode is not able to deal with multiple requests to add a
1922 * station. Keep track if one is in progress so that we do not send
1923 * another.
1924 */
1925 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
e7392364 1926 D_INFO("STA %d already in process of being added.\n", sta_id);
0cdc2136
SG		 1927 return sta_id;
1928 }
1929
1930 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
1931 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) &&
1932 !compare_ether_addr(il->stations[sta_id].sta.sta.addr, addr)) {
e7392364
SG		 1933 D_ASSOC("STA %d (%pM) already added, not adding again.\n",
1934 sta_id, addr);
0cdc2136
SG		 1935 return sta_id;
1936 }
1937
1938 station = &il->stations[sta_id];
1939 station->used = IL_STA_DRIVER_ACTIVE;
e7392364 1940 D_ASSOC("Add STA to driver ID %d: %pM\n", sta_id, addr);
0cdc2136
SG		 1941 il->num_stations++;
1942
1943 /* Set up the C_ADD_STA command to send to device */
1944 memset(&station->sta, 0, sizeof(struct il_addsta_cmd));
1945 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
1946 station->sta.mode = 0;
1947 station->sta.sta.sta_id = sta_id;
fd6415bc 1948 station->sta.station_flags = 0;
0cdc2136 1949
0cdc2136
SG		 1950 /*
1951 * OK to call unconditionally, since local stations (IBSS BSSID
1952 * STA and broadcast STA) pass in a NULL sta, and mac80211
1953 * doesn't allow HT IBSS.
1954 */
83007196 1955 il_set_ht_add_station(il, sta_id, sta);
0cdc2136
SG		 1956
1957 /* 3945 only */
e7392364 1958 rate = (il->band == IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP : RATE_1M_PLCP;
0cdc2136
SG		 1959 /* Turn on both antennas for the station... */
1960 station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK);
1961
1962 return sta_id;
1963
1964}
1965EXPORT_SYMBOL_GPL(il_prep_station);
1966
1967#define STA_WAIT_TIMEOUT (HZ/2)
1968
1969/**
1970 * il_add_station_common -
1971 */
1972int
83007196
SG		 1973il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
1974 struct ieee80211_sta *sta, u8 *sta_id_r)
0cdc2136
SG		 1975{
1976 unsigned long flags_spin;
1977 int ret = 0;
1978 u8 sta_id;
1979 struct il_addsta_cmd sta_cmd;
1980
1981 *sta_id_r = 0;
1982 spin_lock_irqsave(&il->sta_lock, flags_spin);
83007196 1983 sta_id = il_prep_station(il, addr, is_ap, sta);
0cdc2136 1984 if (sta_id == IL_INVALID_STATION) {
e7392364 1985 IL_ERR("Unable to prepare station %pM for addition\n", addr);
0cdc2136
SG		 1986 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
1987 return -EINVAL;
1988 }
1989
1990 /*
1991 * uCode is not able to deal with multiple requests to add a
1992 * station. Keep track if one is in progress so that we do not send
1993 * another.
1994 */
1995 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
e7392364 1996 D_INFO("STA %d already in process of being added.\n", sta_id);
0cdc2136
SG		 1997 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
1998 return -EEXIST;
1999 }
2000
2001 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
2002 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
e7392364 2003 D_ASSOC("STA %d (%pM) already added, not adding again.\n",
0cdc2136
SG		 2004 sta_id, addr);
2005 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2006 return -EEXIST;
2007 }
2008
2009 il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS;
2010 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 2011 sizeof(struct il_addsta_cmd));
0cdc2136
SG		 2012 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2013
2014 /* Add station to device's station table */
2015 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2016 if (ret) {
2017 spin_lock_irqsave(&il->sta_lock, flags_spin);
2018 IL_ERR("Adding station %pM failed.\n",
e7392364 2019 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 2020 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
2021 il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
2022 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2023 }
2024 *sta_id_r = sta_id;
2025 return ret;
2026}
2027EXPORT_SYMBOL(il_add_station_common);
2028
2029/**
2030 * il_sta_ucode_deactivate - deactivate ucode status for a station
2031 *
2032 * il->sta_lock must be held
2033 */
e7392364
SG		 2034static void
2035il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id)
0cdc2136
SG		 2036{
2037 /* Ucode must be active and driver must be non active */
e7392364
SG		 2038 if ((il->stations[sta_id].
2039 used & (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) !=
2040 IL_STA_UCODE_ACTIVE)
0cdc2136
SG		 2041 IL_ERR("removed non active STA %u\n", sta_id);
2042
2043 il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE;
2044
2045 memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry));
2046 D_ASSOC("Removed STA %u\n", sta_id);
2047}
2048
e7392364
SG		 2049static int
2050il_send_remove_station(struct il_priv *il, const u8 * addr, int sta_id,
2051 bool temporary)
0cdc2136
SG		 2052{
2053 struct il_rx_pkt *pkt;
2054 int ret;
2055
2056 unsigned long flags_spin;
2057 struct il_rem_sta_cmd rm_sta_cmd;
2058
2059 struct il_host_cmd cmd = {
2060 .id = C_REM_STA,
2061 .len = sizeof(struct il_rem_sta_cmd),
2062 .flags = CMD_SYNC,
2063 .data = &rm_sta_cmd,
2064 };
2065
2066 memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd));
2067 rm_sta_cmd.num_sta = 1;
2068 memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN);
2069
2070 cmd.flags |= CMD_WANT_SKB;
2071
2072 ret = il_send_cmd(il, &cmd);
2073
2074 if (ret)
2075 return ret;
2076
2077 pkt = (struct il_rx_pkt *)cmd.reply_page;
2078 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
e7392364 2079 IL_ERR("Bad return from C_REM_STA (0x%08X)\n", pkt->hdr.flags);
0cdc2136
SG		 2080 ret = -EIO;
2081 }
2082
2083 if (!ret) {
2084 switch (pkt->u.rem_sta.status) {
2085 case REM_STA_SUCCESS_MSK:
2086 if (!temporary) {
2087 spin_lock_irqsave(&il->sta_lock, flags_spin);
2088 il_sta_ucode_deactivate(il, sta_id);
2089 spin_unlock_irqrestore(&il->sta_lock,
e7392364 2090 flags_spin);
0cdc2136
SG		 2091 }
2092 D_ASSOC("C_REM_STA PASSED\n");
2093 break;
2094 default:
2095 ret = -EIO;
2096 IL_ERR("C_REM_STA failed\n");
2097 break;
2098 }
2099 }
2100 il_free_pages(il, cmd.reply_page);
2101
2102 return ret;
2103}
2104
2105/**
2106 * il_remove_station - Remove driver's knowledge of station.
2107 */
e7392364
SG		 2108int
2109il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr)
0cdc2136
SG		 2110{
2111 unsigned long flags;
2112
2113 if (!il_is_ready(il)) {
e7392364
SG		 2114 D_INFO("Unable to remove station %pM, device not ready.\n",
2115 addr);
0cdc2136
SG		 2116 /*
2117 * It is typical for stations to be removed when we are
2118 * going down. Return success since device will be down
2119 * soon anyway
2120 */
2121 return 0;
2122 }
2123
e7392364 2124 D_ASSOC("Removing STA from driver:%d %pM\n", sta_id, addr);
0cdc2136
SG		 2125
2126 if (WARN_ON(sta_id == IL_INVALID_STATION))
2127 return -EINVAL;
2128
2129 spin_lock_irqsave(&il->sta_lock, flags);
2130
2131 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) {
e7392364 2132 D_INFO("Removing %pM but non DRIVER active\n", addr);
0cdc2136
SG		 2133 goto out_err;
2134 }
2135
2136 if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
e7392364 2137 D_INFO("Removing %pM but non UCODE active\n", addr);
0cdc2136
SG		 2138 goto out_err;
2139 }
2140
2141 if (il->stations[sta_id].used & IL_STA_LOCAL) {
2142 kfree(il->stations[sta_id].lq);
2143 il->stations[sta_id].lq = NULL;
2144 }
2145
2146 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
2147
2148 il->num_stations--;
2149
2150 BUG_ON(il->num_stations < 0);
2151
2152 spin_unlock_irqrestore(&il->sta_lock, flags);
2153
2154 return il_send_remove_station(il, addr, sta_id, false);
2155out_err:
2156 spin_unlock_irqrestore(&il->sta_lock, flags);
2157 return -EINVAL;
2158}
2159EXPORT_SYMBOL_GPL(il_remove_station);
2160
2161/**
2162 * il_clear_ucode_stations - clear ucode station table bits
2163 *
2164 * This function clears all the bits in the driver indicating
2165 * which stations are active in the ucode. Call when something
2166 * other than explicit station management would cause this in
2167 * the ucode, e.g. unassociated RXON.
2168 */
e7392364 2169void
83007196 2170il_clear_ucode_stations(struct il_priv *il)
0cdc2136
SG		 2171{
2172 int i;
2173 unsigned long flags_spin;
2174 bool cleared = false;
2175
2176 D_INFO("Clearing ucode stations in driver\n");
2177
2178 spin_lock_irqsave(&il->sta_lock, flags_spin);
2179 for (i = 0; i < il->hw_params.max_stations; i++) {
0cdc2136 2180 if (il->stations[i].used & IL_STA_UCODE_ACTIVE) {
e7392364 2181 D_INFO("Clearing ucode active for station %d\n", i);
0cdc2136
SG		 2182 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2183 cleared = true;
2184 }
2185 }
2186 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2187
2188 if (!cleared)
e7392364 2189 D_INFO("No active stations found to be cleared\n");
0cdc2136
SG		 2190}
2191EXPORT_SYMBOL(il_clear_ucode_stations);
2192
2193/**
2194 * il_restore_stations() - Restore driver known stations to device
2195 *
2196 * All stations considered active by driver, but not present in ucode, is
2197 * restored.
2198 *
2199 * Function sleeps.
2200 */
2201void
83007196 2202il_restore_stations(struct il_priv *il)
0cdc2136
SG		 2203{
2204 struct il_addsta_cmd sta_cmd;
2205 struct il_link_quality_cmd lq;
2206 unsigned long flags_spin;
2207 int i;
2208 bool found = false;
2209 int ret;
2210 bool send_lq;
2211
2212 if (!il_is_ready(il)) {
e7392364 2213 D_INFO("Not ready yet, not restoring any stations.\n");
0cdc2136
SG		 2214 return;
2215 }
2216
2217 D_ASSOC("Restoring all known stations ... start.\n");
2218 spin_lock_irqsave(&il->sta_lock, flags_spin);
2219 for (i = 0; i < il->hw_params.max_stations; i++) {
0cdc2136
SG		 2220 if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) &&
2221 !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) {
2222 D_ASSOC("Restoring sta %pM\n",
e7392364 2223 il->stations[i].sta.sta.addr);
0cdc2136
SG		 2224 il->stations[i].sta.mode = 0;
2225 il->stations[i].used |= IL_STA_UCODE_INPROGRESS;
2226 found = true;
2227 }
2228 }
2229
2230 for (i = 0; i < il->hw_params.max_stations; i++) {
2231 if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) {
2232 memcpy(&sta_cmd, &il->stations[i].sta,
2233 sizeof(struct il_addsta_cmd));
2234 send_lq = false;
2235 if (il->stations[i].lq) {
2236 memcpy(&lq, il->stations[i].lq,
2237 sizeof(struct il_link_quality_cmd));
2238 send_lq = true;
2239 }
2240 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2241 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2242 if (ret) {
2243 spin_lock_irqsave(&il->sta_lock, flags_spin);
2244 IL_ERR("Adding station %pM failed.\n",
e7392364
SG		 2245 il->stations[i].sta.sta.addr);
2246 il->stations[i].used &= ~IL_STA_DRIVER_ACTIVE;
0cdc2136 2247 il->stations[i].used &=
e7392364 2248 ~IL_STA_UCODE_INPROGRESS;
0cdc2136 2249 spin_unlock_irqrestore(&il->sta_lock,
e7392364 2250 flags_spin);
0cdc2136
SG		 2251 }
2252 /*
2253 * Rate scaling has already been initialized, send
2254 * current LQ command
2255 */
2256 if (send_lq)
83007196 2257 il_send_lq_cmd(il, &lq, CMD_SYNC, true);
0cdc2136
SG		 2258 spin_lock_irqsave(&il->sta_lock, flags_spin);
2259 il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS;
2260 }
2261 }
2262
2263 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2264 if (!found)
2265 D_INFO("Restoring all known stations"
e7392364 2266 " .... no stations to be restored.\n");
0cdc2136 2267 else
e7392364 2268 D_INFO("Restoring all known stations" " .... complete.\n");
0cdc2136
SG		 2269}
2270EXPORT_SYMBOL(il_restore_stations);
2271
e7392364
SG		 2272int
2273il_get_free_ucode_key_idx(struct il_priv *il)
0cdc2136
SG		 2274{
2275 int i;
2276
2277 for (i = 0; i < il->sta_key_max_num; i++)
2278 if (!test_and_set_bit(i, &il->ucode_key_table))
2279 return i;
2280
2281 return WEP_INVALID_OFFSET;
2282}
2283EXPORT_SYMBOL(il_get_free_ucode_key_idx);
2284
e7392364
SG		 2285void
2286il_dealloc_bcast_stations(struct il_priv *il)
0cdc2136
SG		 2287{
2288 unsigned long flags;
2289 int i;
2290
2291 spin_lock_irqsave(&il->sta_lock, flags);
2292 for (i = 0; i < il->hw_params.max_stations; i++) {
2293 if (!(il->stations[i].used & IL_STA_BCAST))
2294 continue;
2295
2296 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2297 il->num_stations--;
2298 BUG_ON(il->num_stations < 0);
2299 kfree(il->stations[i].lq);
2300 il->stations[i].lq = NULL;
2301 }
2302 spin_unlock_irqrestore(&il->sta_lock, flags);
2303}
2304EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations);
2305
2306#ifdef CONFIG_IWLEGACY_DEBUG
e7392364
SG		 2307static void
2308il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG		 2309{
2310 int i;
2311 D_RATE("lq station id 0x%x\n", lq->sta_id);
e7392364
SG		 2312 D_RATE("lq ant 0x%X 0x%X\n", lq->general_params.single_stream_ant_msk,
2313 lq->general_params.dual_stream_ant_msk);
0cdc2136
SG		 2314
2315 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
e7392364 2316 D_RATE("lq idx %d 0x%X\n", i, lq->rs_table[i].rate_n_flags);
0cdc2136
SG		 2317}
2318#else
e7392364
SG		 2319static inline void
2320il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG		 2321{
2322}
2323#endif
2324
2325/**
2326 * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity
2327 *
2328 * It sometimes happens when a HT rate has been in use and we
2329 * loose connectivity with AP then mac80211 will first tell us that the
2330 * current channel is not HT anymore before removing the station. In such a
2331 * scenario the RXON flags will be updated to indicate we are not
2332 * communicating HT anymore, but the LQ command may still contain HT rates.
2333 * Test for this to prevent driver from sending LQ command between the time
2334 * RXON flags are updated and when LQ command is updated.
2335 */
e7392364 2336static bool
83007196 2337il_is_lq_table_valid(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG		 2338{
2339 int i;
2340
1c03c462 2341 if (il->ht.enabled)
0cdc2136
SG		 2342 return true;
2343
c8b03958 2344 D_INFO("Channel %u is not an HT channel\n", il->active.channel);
0cdc2136 2345 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
e7392364
SG		 2346 if (le32_to_cpu(lq->rs_table[i].rate_n_flags) & RATE_MCS_HT_MSK) {
2347 D_INFO("idx %d of LQ expects HT channel\n", i);
0cdc2136
SG		 2348 return false;
2349 }
2350 }
2351 return true;
2352}
2353
2354/**
2355 * il_send_lq_cmd() - Send link quality command
2356 * @init: This command is sent as part of station initialization right
2357 * after station has been added.
2358 *
2359 * The link quality command is sent as the last step of station creation.
2360 * This is the special case in which init is set and we call a callback in
2361 * this case to clear the state indicating that station creation is in
2362 * progress.
2363 */
e7392364 2364int
83007196
SG		 2365il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2366 u8 flags, bool init)
0cdc2136
SG		 2367{
2368 int ret = 0;
2369 unsigned long flags_spin;
2370
2371 struct il_host_cmd cmd = {
2372 .id = C_TX_LINK_QUALITY_CMD,
2373 .len = sizeof(struct il_link_quality_cmd),
2374 .flags = flags,
2375 .data = lq,
2376 };
2377
2378 if (WARN_ON(lq->sta_id == IL_INVALID_STATION))
2379 return -EINVAL;
2380
0cdc2136
SG		 2381 spin_lock_irqsave(&il->sta_lock, flags_spin);
2382 if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) {
2383 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2384 return -EINVAL;
2385 }
2386 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2387
2388 il_dump_lq_cmd(il, lq);
2389 BUG_ON(init && (cmd.flags & CMD_ASYNC));
2390
83007196 2391 if (il_is_lq_table_valid(il, lq))
0cdc2136
SG		 2392 ret = il_send_cmd(il, &cmd);
2393 else
2394 ret = -EINVAL;
2395
2396 if (cmd.flags & CMD_ASYNC)
2397 return ret;
2398
2399 if (init) {
2400 D_INFO("init LQ command complete,"
e7392364
SG		 2401 " clearing sta addition status for sta %d\n",
2402 lq->sta_id);
0cdc2136
SG		 2403 spin_lock_irqsave(&il->sta_lock, flags_spin);
2404 il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
2405 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2406 }
2407 return ret;
2408}
2409EXPORT_SYMBOL(il_send_lq_cmd);
2410
e7392364
SG		 2411int
2412il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2413 struct ieee80211_sta *sta)
0cdc2136
SG		 2414{
2415 struct il_priv *il = hw->priv;
2416 struct il_station_priv_common *sta_common = (void *)sta->drv_priv;
2417 int ret;
2418
e7392364 2419 D_INFO("received request to remove station %pM\n", sta->addr);
0cdc2136 2420 mutex_lock(&il->mutex);
e7392364 2421 D_INFO("proceeding to remove station %pM\n", sta->addr);
0cdc2136
SG		 2422 ret = il_remove_station(il, sta_common->sta_id, sta->addr);
2423 if (ret)
e7392364 2424 IL_ERR("Error removing station %pM\n", sta->addr);
0cdc2136
SG		 2425 mutex_unlock(&il->mutex);
2426 return ret;
2427}
2428EXPORT_SYMBOL(il_mac_sta_remove);
2429
2430/************************** RX-FUNCTIONS ****************************/
2431/*
2432 * Rx theory of operation
2433 *
2434 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
2435 * each of which point to Receive Buffers to be filled by the NIC. These get
2436 * used not only for Rx frames, but for any command response or notification
2437 * from the NIC. The driver and NIC manage the Rx buffers by means
2438 * of idxes into the circular buffer.
2439 *
2440 * Rx Queue Indexes
2441 * The host/firmware share two idx registers for managing the Rx buffers.
2442 *
2443 * The READ idx maps to the first position that the firmware may be writing
2444 * to -- the driver can read up to (but not including) this position and get
2445 * good data.
2446 * The READ idx is managed by the firmware once the card is enabled.
2447 *
2448 * The WRITE idx maps to the last position the driver has read from -- the
2449 * position preceding WRITE is the last slot the firmware can place a packet.
2450 *
2451 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
2452 * WRITE = READ.
2453 *
2454 * During initialization, the host sets up the READ queue position to the first
2455 * IDX position, and WRITE to the last (READ - 1 wrapped)
2456 *
2457 * When the firmware places a packet in a buffer, it will advance the READ idx
2458 * and fire the RX interrupt. The driver can then query the READ idx and
2459 * process as many packets as possible, moving the WRITE idx forward as it
2460 * resets the Rx queue buffers with new memory.
2461 *
2462 * The management in the driver is as follows:
2463 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
2464 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
2465 * to replenish the iwl->rxq->rx_free.
2466 * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the
2467 * iwl->rxq is replenished and the READ IDX is updated (updating the
2468 * 'processed' and 'read' driver idxes as well)
2469 * + A received packet is processed and handed to the kernel network stack,
2470 * detached from the iwl->rxq. The driver 'processed' idx is updated.
2471 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
2472 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
2473 * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
2474 * were enough free buffers and RX_STALLED is set it is cleared.
2475 *
2476 *
2477 * Driver sequence:
2478 *
2479 * il_rx_queue_alloc() Allocates rx_free
2480 * il_rx_replenish() Replenishes rx_free list from rx_used, and calls
2481 * il_rx_queue_restock
2482 * il_rx_queue_restock() Moves available buffers from rx_free into Rx
2483 * queue, updates firmware pointers, and updates
2484 * the WRITE idx. If insufficient rx_free buffers
2485 * are available, schedules il_rx_replenish
2486 *
2487 * -- enable interrupts --
2488 * ISR - il_rx() Detach il_rx_bufs from pool up to the
2489 * READ IDX, detaching the SKB from the pool.
2490 * Moves the packet buffer from queue to rx_used.
2491 * Calls il_rx_queue_restock to refill any empty
2492 * slots.
2493 * ...
2494 *
2495 */
2496
2497/**
2498 * il_rx_queue_space - Return number of free slots available in queue.
2499 */
e7392364
SG		 2500int
2501il_rx_queue_space(const struct il_rx_queue *q)
0cdc2136
SG		 2502{
2503 int s = q->read - q->write;
2504 if (s <= 0)
2505 s += RX_QUEUE_SIZE;
2506 /* keep some buffer to not confuse full and empty queue */
2507 s -= 2;
2508 if (s < 0)
2509 s = 0;
2510 return s;
2511}
2512EXPORT_SYMBOL(il_rx_queue_space);
2513
2514/**
2515 * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue
2516 */
2517void
e7392364 2518il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q)
0cdc2136
SG		 2519{
2520 unsigned long flags;
2521 u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg;
2522 u32 reg;
2523
2524 spin_lock_irqsave(&q->lock, flags);
2525
2526 if (q->need_update == 0)
2527 goto exit_unlock;
2528
2529 /* If power-saving is in use, make sure device is awake */
2530 if (test_bit(S_POWER_PMI, &il->status)) {
2531 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2532
2533 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
e7392364
SG		 2534 D_INFO("Rx queue requesting wakeup," " GP1 = 0x%x\n",
2535 reg);
0cdc2136 2536 il_set_bit(il, CSR_GP_CNTRL,
e7392364 2537 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
0cdc2136
SG		 2538 goto exit_unlock;
2539 }
2540
2541 q->write_actual = (q->write & ~0x7);
e7392364 2542 il_wr(il, rx_wrt_ptr_reg, q->write_actual);
0cdc2136 2543
e7392364 2544 /* Else device is assumed to be awake */
0cdc2136
SG		 2545 } else {
2546 /* Device expects a multiple of 8 */
2547 q->write_actual = (q->write & ~0x7);
e7392364 2548 il_wr(il, rx_wrt_ptr_reg, q->write_actual);
0cdc2136
SG		 2549 }
2550
2551 q->need_update = 0;
2552
e7392364 2553exit_unlock:
0cdc2136
SG		 2554 spin_unlock_irqrestore(&q->lock, flags);
2555}
2556EXPORT_SYMBOL(il_rx_queue_update_write_ptr);
2557
e7392364
SG		 2558int
2559il_rx_queue_alloc(struct il_priv *il)
0cdc2136
SG		 2560{
2561 struct il_rx_queue *rxq = &il->rxq;
2562 struct device *dev = &il->pci_dev->dev;
2563 int i;
2564
2565 spin_lock_init(&rxq->lock);
2566 INIT_LIST_HEAD(&rxq->rx_free);
2567 INIT_LIST_HEAD(&rxq->rx_used);
2568
2569 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
e7392364
SG		 2570 rxq->bd =
2571 dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
2572 GFP_KERNEL);
0cdc2136
SG		 2573 if (!rxq->bd)
2574 goto err_bd;
2575
e7392364
SG		 2576 rxq->rb_stts =
2577 dma_alloc_coherent(dev, sizeof(struct il_rb_status),
2578 &rxq->rb_stts_dma, GFP_KERNEL);
0cdc2136
SG		 2579 if (!rxq->rb_stts)
2580 goto err_rb;
2581
2582 /* Fill the rx_used queue with _all_ of the Rx buffers */
2583 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
2584 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
2585
2586 /* Set us so that we have processed and used all buffers, but have
2587 * not restocked the Rx queue with fresh buffers */
2588 rxq->read = rxq->write = 0;
2589 rxq->write_actual = 0;
2590 rxq->free_count = 0;
2591 rxq->need_update = 0;
2592 return 0;
2593
2594err_rb:
2595 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
2596 rxq->bd_dma);
2597err_bd:
2598 return -ENOMEM;
2599}
e7392364 2600EXPORT_SYMBOL(il_rx_queue_alloc);
0cdc2136 2601
e7392364
SG		 2602void
2603il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 2604{
2605 struct il_rx_pkt *pkt = rxb_addr(rxb);
2606 struct il_spectrum_notification *report = &(pkt->u.spectrum_notif);
2607
2608 if (!report->state) {
e7392364 2609 D_11H("Spectrum Measure Notification: Start\n");
0cdc2136
SG		 2610 return;
2611 }
2612
2613 memcpy(&il->measure_report, report, sizeof(*report));
2614 il->measurement_status |= MEASUREMENT_READY;
2615}
2616EXPORT_SYMBOL(il_hdl_spectrum_measurement);
2617
2618/*
2619 * returns non-zero if packet should be dropped
2620 */
e7392364
SG		 2621int
2622il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
2623 u32 decrypt_res, struct ieee80211_rx_status *stats)
0cdc2136
SG		 2624{
2625 u16 fc = le16_to_cpu(hdr->frame_control);
2626
2627 /*
2628 * All contexts have the same setting here due to it being
2629 * a module parameter, so OK to check any context.
2630 */
c8b03958 2631 if (il->active.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
0cdc2136
SG		 2632 return 0;
2633
2634 if (!(fc & IEEE80211_FCTL_PROTECTED))
2635 return 0;
2636
2637 D_RX("decrypt_res:0x%x\n", decrypt_res);
2638 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2639 case RX_RES_STATUS_SEC_TYPE_TKIP:
2640 /* The uCode has got a bad phase 1 Key, pushes the packet.
2641 * Decryption will be done in SW. */
2642 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2643 RX_RES_STATUS_BAD_KEY_TTAK)
2644 break;
2645
2646 case RX_RES_STATUS_SEC_TYPE_WEP:
2647 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2648 RX_RES_STATUS_BAD_ICV_MIC) {
2649 /* bad ICV, the packet is destroyed since the
2650 * decryption is inplace, drop it */
2651 D_RX("Packet destroyed\n");
2652 return -1;
2653 }
2654 case RX_RES_STATUS_SEC_TYPE_CCMP:
2655 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2656 RX_RES_STATUS_DECRYPT_OK) {
2657 D_RX("hw decrypt successfully!!!\n");
2658 stats->flag |= RX_FLAG_DECRYPTED;
2659 }
2660 break;
2661
2662 default:
2663 break;
2664 }
2665 return 0;
2666}
2667EXPORT_SYMBOL(il_set_decrypted_flag);
2668
2669/**
2670 * il_txq_update_write_ptr - Send new write idx to hardware
2671 */
2672void
2673il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq)
2674{
2675 u32 reg = 0;
2676 int txq_id = txq->q.id;
2677
2678 if (txq->need_update == 0)
2679 return;
2680
2681 /* if we're trying to save power */
2682 if (test_bit(S_POWER_PMI, &il->status)) {
2683 /* wake up nic if it's powered down ...
2684 * uCode will wake up, and interrupt us again, so next
2685 * time we'll skip this part. */
2686 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2687
2688 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
e7392364
SG		 2689 D_INFO("Tx queue %d requesting wakeup," " GP1 = 0x%x\n",
2690 txq_id, reg);
0cdc2136 2691 il_set_bit(il, CSR_GP_CNTRL,
e7392364 2692 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
0cdc2136
SG		 2693 return;
2694 }
2695
e7392364 2696 il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
0cdc2136
SG		 2697
2698 /*
2699 * else not in power-save mode,
2700 * uCode will never sleep when we're
2701 * trying to tx (during RFKILL, we're not trying to tx).
2702 */
2703 } else
e7392364 2704 _il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
0cdc2136
SG		 2705 txq->need_update = 0;
2706}
2707EXPORT_SYMBOL(il_txq_update_write_ptr);
2708
2709/**
2710 * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
2711 */
e7392364
SG		 2712void
2713il_tx_queue_unmap(struct il_priv *il, int txq_id)
0cdc2136
SG		 2714{
2715 struct il_tx_queue *txq = &il->txq[txq_id];
2716 struct il_queue *q = &txq->q;
2717
2718 if (q->n_bd == 0)
2719 return;
2720
2721 while (q->write_ptr != q->read_ptr) {
1600b875 2722 il->ops->txq_free_tfd(il, txq);
0cdc2136
SG		 2723 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2724 }
2725}
2726EXPORT_SYMBOL(il_tx_queue_unmap);
2727
2728/**
2729 * il_tx_queue_free - Deallocate DMA queue.
2730 * @txq: Transmit queue to deallocate.
2731 *
2732 * Empty queue by removing and destroying all BD's.
2733 * Free all buffers.
2734 * 0-fill, but do not free "txq" descriptor structure.
2735 */
e7392364
SG		 2736void
2737il_tx_queue_free(struct il_priv *il, int txq_id)
0cdc2136
SG		 2738{
2739 struct il_tx_queue *txq = &il->txq[txq_id];
2740 struct device *dev = &il->pci_dev->dev;
2741 int i;
2742
2743 il_tx_queue_unmap(il, txq_id);
2744
2745 /* De-alloc array of command/tx buffers */
2746 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
2747 kfree(txq->cmd[i]);
2748
2749 /* De-alloc circular buffer of TFDs */
2750 if (txq->q.n_bd)
e7392364
SG		 2751 dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
2752 txq->tfds, txq->q.dma_addr);
0cdc2136
SG		 2753
2754 /* De-alloc array of per-TFD driver data */
00ea99e1
SG		 2755 kfree(txq->skbs);
2756 txq->skbs = NULL;
0cdc2136
SG		 2757
2758 /* deallocate arrays */
2759 kfree(txq->cmd);
2760 kfree(txq->meta);
2761 txq->cmd = NULL;
2762 txq->meta = NULL;
2763
2764 /* 0-fill queue descriptor structure */
2765 memset(txq, 0, sizeof(*txq));
2766}
2767EXPORT_SYMBOL(il_tx_queue_free);
2768
2769/**
2770 * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
2771 */
e7392364
SG		 2772void
2773il_cmd_queue_unmap(struct il_priv *il)
0cdc2136
SG		 2774{
2775 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2776 struct il_queue *q = &txq->q;
2777 int i;
2778
2779 if (q->n_bd == 0)
2780 return;
2781
2782 while (q->read_ptr != q->write_ptr) {
2783 i = il_get_cmd_idx(q, q->read_ptr, 0);
2784
2785 if (txq->meta[i].flags & CMD_MAPPED) {
2786 pci_unmap_single(il->pci_dev,
2787 dma_unmap_addr(&txq->meta[i], mapping),
2788 dma_unmap_len(&txq->meta[i], len),
2789 PCI_DMA_BIDIRECTIONAL);
2790 txq->meta[i].flags = 0;
2791 }
2792
2793 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2794 }
2795
2796 i = q->n_win;
2797 if (txq->meta[i].flags & CMD_MAPPED) {
2798 pci_unmap_single(il->pci_dev,
2799 dma_unmap_addr(&txq->meta[i], mapping),
2800 dma_unmap_len(&txq->meta[i], len),
2801 PCI_DMA_BIDIRECTIONAL);
2802 txq->meta[i].flags = 0;
2803 }
2804}
2805EXPORT_SYMBOL(il_cmd_queue_unmap);
2806
2807/**
2808 * il_cmd_queue_free - Deallocate DMA queue.
2809 * @txq: Transmit queue to deallocate.
2810 *
2811 * Empty queue by removing and destroying all BD's.
2812 * Free all buffers.
2813 * 0-fill, but do not free "txq" descriptor structure.
2814 */
e7392364
SG		 2815void
2816il_cmd_queue_free(struct il_priv *il)
0cdc2136
SG		 2817{
2818 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2819 struct device *dev = &il->pci_dev->dev;
2820 int i;
2821
2822 il_cmd_queue_unmap(il);
2823
2824 /* De-alloc array of command/tx buffers */
2825 for (i = 0; i <= TFD_CMD_SLOTS; i++)
2826 kfree(txq->cmd[i]);
2827
2828 /* De-alloc circular buffer of TFDs */
2829 if (txq->q.n_bd)
2830 dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
2831 txq->tfds, txq->q.dma_addr);
2832
2833 /* deallocate arrays */
2834 kfree(txq->cmd);
2835 kfree(txq->meta);
2836 txq->cmd = NULL;
2837 txq->meta = NULL;
2838
2839 /* 0-fill queue descriptor structure */
2840 memset(txq, 0, sizeof(*txq));
2841}
2842EXPORT_SYMBOL(il_cmd_queue_free);
2843
2844/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
2845 * DMA services
2846 *
2847 * Theory of operation
2848 *
2849 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
2850 * of buffer descriptors, each of which points to one or more data buffers for
2851 * the device to read from or fill. Driver and device exchange status of each
2852 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
2853 * entries in each circular buffer, to protect against confusing empty and full
2854 * queue states.
2855 *
2856 * The device reads or writes the data in the queues via the device's several
2857 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
2858 *
2859 * For Tx queue, there are low mark and high mark limits. If, after queuing
2860 * the packet for Tx, free space become < low mark, Tx queue stopped. When
2861 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
2862 * Tx queue resumed.
2863 *
2864 * See more detailed info in 4965.h.
2865 ***************************************************/
2866
e7392364
SG		 2867int
2868il_queue_space(const struct il_queue *q)
0cdc2136
SG		 2869{
2870 int s = q->read_ptr - q->write_ptr;
2871
2872 if (q->read_ptr > q->write_ptr)
2873 s -= q->n_bd;
2874
2875 if (s <= 0)
2876 s += q->n_win;
2877 /* keep some reserve to not confuse empty and full situations */
2878 s -= 2;
2879 if (s < 0)
2880 s = 0;
2881 return s;
2882}
2883EXPORT_SYMBOL(il_queue_space);
2884
2885
2886/**
2887 * il_queue_init - Initialize queue's high/low-water and read/write idxes
2888 */
e7392364
SG		 2889static int
2890il_queue_init(struct il_priv *il, struct il_queue *q, int count, int slots_num,
2891 u32 id)
0cdc2136
SG		 2892{
2893 q->n_bd = count;
2894 q->n_win = slots_num;
2895 q->id = id;
2896
2897 /* count must be power-of-two size, otherwise il_queue_inc_wrap
2898 * and il_queue_dec_wrap are broken. */
2899 BUG_ON(!is_power_of_2(count));
2900
2901 /* slots_num must be power-of-two size, otherwise
2902 * il_get_cmd_idx is broken. */
2903 BUG_ON(!is_power_of_2(slots_num));
2904
2905 q->low_mark = q->n_win / 4;
2906 if (q->low_mark < 4)
2907 q->low_mark = 4;
2908
2909 q->high_mark = q->n_win / 8;
2910 if (q->high_mark < 2)
2911 q->high_mark = 2;
2912
2913 q->write_ptr = q->read_ptr = 0;
2914
2915 return 0;
2916}
2917
2918/**
2919 * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
2920 */
e7392364
SG		 2921static int
2922il_tx_queue_alloc(struct il_priv *il, struct il_tx_queue *txq, u32 id)
0cdc2136
SG		 2923{
2924 struct device *dev = &il->pci_dev->dev;
2925 size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
2926
2927 /* Driver ilate data, only for Tx (not command) queues,
2928 * not shared with device. */
2929 if (id != il->cmd_queue) {
00ea99e1
SG		 2930 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(struct skb *),
2931 GFP_KERNEL);
2932 if (!txq->skbs) {
2933 IL_ERR("Fail to alloc skbs\n");
0cdc2136
SG		 2934 goto error;
2935 }
00ea99e1
SG		 2936 } else
2937 txq->skbs = NULL;
0cdc2136
SG		 2938
2939 /* Circular buffer of transmit frame descriptors (TFDs),
2940 * shared with device */
e7392364
SG		 2941 txq->tfds =
2942 dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, GFP_KERNEL);
0cdc2136 2943 if (!txq->tfds) {
00ea99e1 2944 IL_ERR("Fail to alloc TFDs\n");
0cdc2136
SG		 2945 goto error;
2946 }
2947 txq->q.id = id;
2948
2949 return 0;
2950
e7392364 2951error:
00ea99e1
SG		 2952 kfree(txq->skbs);
2953 txq->skbs = NULL;
0cdc2136
SG		 2954
2955 return -ENOMEM;
2956}
2957
2958/**
2959 * il_tx_queue_init - Allocate and initialize one tx/cmd queue
2960 */
e7392364
SG		 2961int
2962il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
2963 u32 txq_id)
0cdc2136
SG		 2964{
2965 int i, len;
2966 int ret;
2967 int actual_slots = slots_num;
2968
2969 /*
2970 * Alloc buffer array for commands (Tx or other types of commands).
2971 * For the command queue (#4/#9), allocate command space + one big
2972 * command for scan, since scan command is very huge; the system will
2973 * not have two scans at the same time, so only one is needed.
2974 * For normal Tx queues (all other queues), no super-size command
2975 * space is needed.
2976 */
2977 if (txq_id == il->cmd_queue)
2978 actual_slots++;
2979
e7392364
SG		 2980 txq->meta =
2981 kzalloc(sizeof(struct il_cmd_meta) * actual_slots, GFP_KERNEL);
2982 txq->cmd =
2983 kzalloc(sizeof(struct il_device_cmd *) * actual_slots, GFP_KERNEL);
0cdc2136
SG		 2984
2985 if (!txq->meta || !txq->cmd)
2986 goto out_free_arrays;
2987
2988 len = sizeof(struct il_device_cmd);
2989 for (i = 0; i < actual_slots; i++) {
2990 /* only happens for cmd queue */
2991 if (i == slots_num)
2992 len = IL_MAX_CMD_SIZE;
2993
2994 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
2995 if (!txq->cmd[i])
2996 goto err;
2997 }
2998
2999 /* Alloc driver data array and TFD circular buffer */
3000 ret = il_tx_queue_alloc(il, txq, txq_id);
3001 if (ret)
3002 goto err;
3003
3004 txq->need_update = 0;
3005
3006 /*
3007 * For the default queues 0-3, set up the swq_id
3008 * already -- all others need to get one later
3009 * (if they need one at all).
3010 */
3011 if (txq_id < 4)
3012 il_set_swq_id(txq, txq_id, txq_id);
3013
3014 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
3015 * il_queue_inc_wrap and il_queue_dec_wrap are broken. */
3016 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
3017
3018 /* Initialize queue's high/low-water marks, and head/tail idxes */
e7392364 3019 il_queue_init(il, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
0cdc2136
SG		 3020
3021 /* Tell device where to find queue */
1600b875 3022 il->ops->txq_init(il, txq);
0cdc2136
SG		 3023
3024 return 0;
3025err:
3026 for (i = 0; i < actual_slots; i++)
3027 kfree(txq->cmd[i]);
3028out_free_arrays:
3029 kfree(txq->meta);
3030 kfree(txq->cmd);
3031
3032 return -ENOMEM;
3033}
3034EXPORT_SYMBOL(il_tx_queue_init);
3035
e7392364
SG		 3036void
3037il_tx_queue_reset(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
3038 u32 txq_id)
0cdc2136
SG		 3039{
3040 int actual_slots = slots_num;
3041
3042 if (txq_id == il->cmd_queue)
3043 actual_slots++;
3044
3045 memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots);
3046
3047 txq->need_update = 0;
3048
3049 /* Initialize queue's high/low-water marks, and head/tail idxes */
e7392364 3050 il_queue_init(il, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
0cdc2136
SG		 3051
3052 /* Tell device where to find queue */
1600b875 3053 il->ops->txq_init(il, txq);
0cdc2136
SG		 3054}
3055EXPORT_SYMBOL(il_tx_queue_reset);
3056
3057/*************** HOST COMMAND QUEUE FUNCTIONS *****/
3058
3059/**
3060 * il_enqueue_hcmd - enqueue a uCode command
3061 * @il: device ilate data point
3062 * @cmd: a point to the ucode command structure
3063 *
3064 * The function returns < 0 values to indicate the operation is
3065 * failed. On success, it turns the idx (> 0) of command in the
3066 * command queue.
3067 */
e7392364
SG		 3068int
3069il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG		 3070{
3071 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
3072 struct il_queue *q = &txq->q;
3073 struct il_device_cmd *out_cmd;
3074 struct il_cmd_meta *out_meta;
3075 dma_addr_t phys_addr;
3076 unsigned long flags;
3077 int len;
3078 u32 idx;
3079 u16 fix_size;
3080
c39ae9fd 3081 cmd->len = il->ops->utils->get_hcmd_size(cmd->id, cmd->len);
e7392364 3082 fix_size = (u16) (cmd->len + sizeof(out_cmd->hdr));
0cdc2136
SG		 3083
3084 /* If any of the command structures end up being larger than
3085 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
3086 * we will need to increase the size of the TFD entries
3087 * Also, check to see if command buffer should not exceed the size
3088 * of device_cmd and max_cmd_size. */
3089 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
3090 !(cmd->flags & CMD_SIZE_HUGE));
3091 BUG_ON(fix_size > IL_MAX_CMD_SIZE);
3092
3093 if (il_is_rfkill(il) || il_is_ctkill(il)) {
3094 IL_WARN("Not sending command - %s KILL\n",
e7392364 3095 il_is_rfkill(il) ? "RF" : "CT");
0cdc2136
SG		 3096 return -EIO;
3097 }
3098
3099 spin_lock_irqsave(&il->hcmd_lock, flags);
3100
3101 if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
3102 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3103
3104 IL_ERR("Restarting adapter due to command queue full\n");
3105 queue_work(il->workqueue, &il->restart);
3106 return -ENOSPC;
3107 }
3108
3109 idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
3110 out_cmd = txq->cmd[idx];
3111 out_meta = &txq->meta[idx];
3112
3113 if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
3114 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3115 return -ENOSPC;
3116 }
3117
3118 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
3119 out_meta->flags = cmd->flags | CMD_MAPPED;
3120 if (cmd->flags & CMD_WANT_SKB)
3121 out_meta->source = cmd;
3122 if (cmd->flags & CMD_ASYNC)
3123 out_meta->callback = cmd->callback;
3124
3125 out_cmd->hdr.cmd = cmd->id;
3126 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
3127
3128 /* At this point, the out_cmd now has all of the incoming cmd
3129 * information */
3130
3131 out_cmd->hdr.flags = 0;
e7392364
SG		 3132 out_cmd->hdr.sequence =
3133 cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) | IDX_TO_SEQ(q->write_ptr));
0cdc2136
SG		 3134 if (cmd->flags & CMD_SIZE_HUGE)
3135 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
3136 len = sizeof(struct il_device_cmd);
3137 if (idx == TFD_CMD_SLOTS)
3138 len = IL_MAX_CMD_SIZE;
3139
3140#ifdef CONFIG_IWLEGACY_DEBUG
3141 switch (out_cmd->hdr.cmd) {
3142 case C_TX_LINK_QUALITY_CMD:
3143 case C_SENSITIVITY:
e7392364
SG		 3144 D_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
3145 "%d bytes at %d[%d]:%d\n",
3146 il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
3147 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
3148 q->write_ptr, idx, il->cmd_queue);
0cdc2136
SG		 3149 break;
3150 default:
3151 D_HC("Sending command %s (#%x), seq: 0x%04X, "
e7392364
SG		 3152 "%d bytes at %d[%d]:%d\n",
3153 il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
3154 le16_to_cpu(out_cmd->hdr.sequence), fix_size, q->write_ptr,
3155 idx, il->cmd_queue);
0cdc2136
SG		 3156 }
3157#endif
3158 txq->need_update = 1;
3159
1600b875 3160 if (il->ops->txq_update_byte_cnt_tbl)
0cdc2136 3161 /* Set up entry in queue's byte count circular buffer */
1600b875 3162 il->ops->txq_update_byte_cnt_tbl(il, txq, 0);
0cdc2136 3163
e7392364
SG		 3164 phys_addr =
3165 pci_map_single(il->pci_dev, &out_cmd->hdr, fix_size,
3166 PCI_DMA_BIDIRECTIONAL);
0cdc2136
SG		 3167 dma_unmap_addr_set(out_meta, mapping, phys_addr);
3168 dma_unmap_len_set(out_meta, len, fix_size);
3169
1600b875 3170 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, fix_size, 1,
c39ae9fd 3171 U32_PAD(cmd->len));
0cdc2136
SG		 3172
3173 /* Increment and update queue's write idx */
3174 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
3175 il_txq_update_write_ptr(il, txq);
3176
3177 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3178 return idx;
3179}
3180
3181/**
3182 * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
3183 *
3184 * When FW advances 'R' idx, all entries between old and new 'R' idx
3185 * need to be reclaimed. As result, some free space forms. If there is
3186 * enough free space (> low mark), wake the stack that feeds us.
3187 */
e7392364
SG		 3188static void
3189il_hcmd_queue_reclaim(struct il_priv *il, int txq_id, int idx, int cmd_idx)
0cdc2136
SG		 3190{
3191 struct il_tx_queue *txq = &il->txq[txq_id];
3192 struct il_queue *q = &txq->q;
3193 int nfreed = 0;
3194
3195 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
3196 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
e7392364
SG		 3197 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
3198 q->write_ptr, q->read_ptr);
0cdc2136
SG		 3199 return;
3200 }
3201
3202 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
3203 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3204
3205 if (nfreed++ > 0) {
3206 IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx,
e7392364 3207 q->write_ptr, q->read_ptr);
0cdc2136
SG		 3208 queue_work(il->workqueue, &il->restart);
3209 }
3210
3211 }
3212}
3213
3214/**
3215 * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
3216 * @rxb: Rx buffer to reclaim
3217 *
3218 * If an Rx buffer has an async callback associated with it the callback
3219 * will be executed. The attached skb (if present) will only be freed
3220 * if the callback returns 1
3221 */
3222void
3223il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb)
3224{
3225 struct il_rx_pkt *pkt = rxb_addr(rxb);
3226 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3227 int txq_id = SEQ_TO_QUEUE(sequence);
3228 int idx = SEQ_TO_IDX(sequence);
3229 int cmd_idx;
3230 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
3231 struct il_device_cmd *cmd;
3232 struct il_cmd_meta *meta;
3233 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
3234 unsigned long flags;
3235
3236 /* If a Tx command is being handled and it isn't in the actual
3237 * command queue then there a command routing bug has been introduced
3238 * in the queue management code. */
e7392364
SG		 3239 if (WARN
3240 (txq_id != il->cmd_queue,
3241 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
3242 txq_id, il->cmd_queue, sequence, il->txq[il->cmd_queue].q.read_ptr,
3243 il->txq[il->cmd_queue].q.write_ptr)) {
0cdc2136
SG		 3244 il_print_hex_error(il, pkt, 32);
3245 return;
3246 }
3247
3248 cmd_idx = il_get_cmd_idx(&txq->q, idx, huge);
3249 cmd = txq->cmd[cmd_idx];
3250 meta = &txq->meta[cmd_idx];
3251
3252 txq->time_stamp = jiffies;
3253
e7392364
SG		 3254 pci_unmap_single(il->pci_dev, dma_unmap_addr(meta, mapping),
3255 dma_unmap_len(meta, len), PCI_DMA_BIDIRECTIONAL);
0cdc2136
SG		 3256
3257 /* Input error checking is done when commands are added to queue. */
3258 if (meta->flags & CMD_WANT_SKB) {
3259 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
3260 rxb->page = NULL;
3261 } else if (meta->callback)
3262 meta->callback(il, cmd, pkt);
3263
3264 spin_lock_irqsave(&il->hcmd_lock, flags);
3265
3266 il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx);
3267
3268 if (!(meta->flags & CMD_ASYNC)) {
3269 clear_bit(S_HCMD_ACTIVE, &il->status);
3270 D_INFO("Clearing HCMD_ACTIVE for command %s\n",
e7392364 3271 il_get_cmd_string(cmd->hdr.cmd));
0cdc2136
SG		 3272 wake_up(&il->wait_command_queue);
3273 }
3274
3275 /* Mark as unmapped */
3276 meta->flags = 0;
3277
3278 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3279}
3280EXPORT_SYMBOL(il_tx_cmd_complete);
be663ab6
WYG		 3281
3282MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965");
3283MODULE_VERSION(IWLWIFI_VERSION);
3284MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
3285MODULE_LICENSE("GPL");
3286
3287/*
3288 * set bt_coex_active to true, uCode will do kill/defer
3289 * every time the priority line is asserted (BT is sending signals on the
3290 * priority line in the PCIx).
3291 * set bt_coex_active to false, uCode will ignore the BT activity and
3292 * perform the normal operation
3293 *
3294 * User might experience transmit issue on some platform due to WiFi/BT
3295 * co-exist problem. The possible behaviors are:
3296 * Able to scan and finding all the available AP
3297 * Not able to associate with any AP
3298 * On those platforms, WiFi communication can be restored by set
3299 * "bt_coex_active" module parameter to "false"
3300 *
3301 * default: bt_coex_active = true (BT_COEX_ENABLE)
3302 */
ef33417d 3303static bool bt_coex_active = true;
be663ab6
WYG		 3304module_param(bt_coex_active, bool, S_IRUGO);
3305MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
3306
d2ddf621
SG		 3307u32 il_debug_level;
3308EXPORT_SYMBOL(il_debug_level);
be663ab6 3309
d2ddf621 3310const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
e7392364 3311EXPORT_SYMBOL(il_bcast_addr);
be663ab6 3312
e7392364
SG		 3313#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
3314#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
3315static void
3316il_init_ht_hw_capab(const struct il_priv *il,
3317 struct ieee80211_sta_ht_cap *ht_info,
3318 enum ieee80211_band band)
be663ab6
WYG		 3319{
3320 u16 max_bit_rate = 0;
46bc8d4b
SG		 3321 u8 rx_chains_num = il->hw_params.rx_chains_num;
3322 u8 tx_chains_num = il->hw_params.tx_chains_num;
be663ab6
WYG		 3323
3324 ht_info->cap = 0;
3325 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
3326
3327 ht_info->ht_supported = true;
3328
3329 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
3330 max_bit_rate = MAX_BIT_RATE_20_MHZ;
46bc8d4b 3331 if (il->hw_params.ht40_channel & BIT(band)) {
be663ab6
WYG		 3332 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
3333 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
3334 ht_info->mcs.rx_mask[4] = 0x01;
3335 max_bit_rate = MAX_BIT_RATE_40_MHZ;
3336 }
3337
46bc8d4b 3338 if (il->cfg->mod_params->amsdu_size_8K)
be663ab6
WYG		 3339 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
3340
3341 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3342 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3343
3344 ht_info->mcs.rx_mask[0] = 0xFF;
3345 if (rx_chains_num >= 2)
3346 ht_info->mcs.rx_mask[1] = 0xFF;
3347 if (rx_chains_num >= 3)
3348 ht_info->mcs.rx_mask[2] = 0xFF;
3349
3350 /* Highest supported Rx data rate */
3351 max_bit_rate *= rx_chains_num;
3352 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
3353 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
3354
3355 /* Tx MCS capabilities */
3356 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
3357 if (tx_chains_num != rx_chains_num) {
3358 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
e7392364
SG		 3359 ht_info->mcs.tx_params |=
3360 ((tx_chains_num -
3361 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
be663ab6
WYG		 3362 }
3363}
3364
3365/**
e2ebc833 3366 * il_init_geos - Initialize mac80211's geo/channel info based from eeprom
be663ab6 3367 */
e7392364
SG		 3368int
3369il_init_geos(struct il_priv *il)
be663ab6 3370{
e2ebc833 3371 struct il_channel_info *ch;
be663ab6
WYG		 3372 struct ieee80211_supported_band *sband;
3373 struct ieee80211_channel *channels;
3374 struct ieee80211_channel *geo_ch;
3375 struct ieee80211_rate *rates;
3376 int i = 0;
332704a5 3377 s8 max_tx_power = 0;
be663ab6 3378
46bc8d4b
SG		 3379 if (il->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
3380 il->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
58de00a4 3381 D_INFO("Geography modes already initialized.\n");
a6766ccd 3382 set_bit(S_GEO_CONFIGURED, &il->status);
be663ab6
WYG		 3383 return 0;
3384 }
3385
e7392364
SG		 3386 channels =
3387 kzalloc(sizeof(struct ieee80211_channel) * il->channel_count,
3388 GFP_KERNEL);
be663ab6
WYG		 3389 if (!channels)
3390 return -ENOMEM;
3391
e7392364
SG		 3392 rates =
3393 kzalloc((sizeof(struct ieee80211_rate) * RATE_COUNT_LEGACY),
3394 GFP_KERNEL);
be663ab6
WYG		 3395 if (!rates) {
3396 kfree(channels);
3397 return -ENOMEM;
3398 }
3399
3400 /* 5.2GHz channels start after the 2.4GHz channels */
46bc8d4b 3401 sband = &il->bands[IEEE80211_BAND_5GHZ];
d2ddf621 3402 sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)];
be663ab6 3403 /* just OFDM */
e2ebc833 3404 sband->bitrates = &rates[IL_FIRST_OFDM_RATE];
2eb05816 3405 sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE;
be663ab6 3406
46bc8d4b 3407 if (il->cfg->sku & IL_SKU_N)
e7392364 3408 il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_5GHZ);
be663ab6 3409
46bc8d4b 3410 sband = &il->bands[IEEE80211_BAND_2GHZ];
be663ab6
WYG		 3411 sband->channels = channels;
3412 /* OFDM & CCK */
3413 sband->bitrates = rates;
2eb05816 3414 sband->n_bitrates = RATE_COUNT_LEGACY;
be663ab6 3415
46bc8d4b 3416 if (il->cfg->sku & IL_SKU_N)
e7392364 3417 il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_2GHZ);
be663ab6 3418
46bc8d4b
SG		 3419 il->ieee_channels = channels;
3420 il->ieee_rates = rates;
be663ab6 3421
e7392364 3422 for (i = 0; i < il->channel_count; i++) {
46bc8d4b 3423 ch = &il->channel_info[i];
be663ab6 3424
e2ebc833 3425 if (!il_is_channel_valid(ch))
be663ab6
WYG		 3426 continue;
3427
46bc8d4b 3428 sband = &il->bands[ch->band];
be663ab6
WYG		 3429
3430 geo_ch = &sband->channels[sband->n_channels++];
3431
3432 geo_ch->center_freq =
e7392364 3433 ieee80211_channel_to_frequency(ch->channel, ch->band);
be663ab6
WYG		 3434 geo_ch->max_power = ch->max_power_avg;
3435 geo_ch->max_antenna_gain = 0xff;
3436 geo_ch->hw_value = ch->channel;
3437
e2ebc833 3438 if (il_is_channel_valid(ch)) {
be663ab6
WYG		 3439 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
3440 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
3441
3442 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
3443 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
3444
3445 if (ch->flags & EEPROM_CHANNEL_RADAR)
3446 geo_ch->flags |= IEEE80211_CHAN_RADAR;
3447
3448 geo_ch->flags |= ch->ht40_extension_channel;
3449
332704a5
SG		 3450 if (ch->max_power_avg > max_tx_power)
3451 max_tx_power = ch->max_power_avg;
be663ab6
WYG		 3452 } else {
3453 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
3454 }
3455
e7392364
SG		 3456 D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", ch->channel,
3457 geo_ch->center_freq,
3458 il_is_channel_a_band(ch) ? "5.2" : "2.4",
3459 geo_ch->
3460 flags & IEEE80211_CHAN_DISABLED ? "restricted" : "valid",
3461 geo_ch->flags);
be663ab6
WYG		 3462 }
3463
46bc8d4b
SG		 3464 il->tx_power_device_lmt = max_tx_power;
3465 il->tx_power_user_lmt = max_tx_power;
3466 il->tx_power_next = max_tx_power;
332704a5 3467
232913b5
SG		 3468 if (il->bands[IEEE80211_BAND_5GHZ].n_channels == 0 &&
3469 (il->cfg->sku & IL_SKU_A)) {
9406f797 3470 IL_INFO("Incorrectly detected BG card as ABG. "
be663ab6 3471 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
e7392364 3472 il->pci_dev->device, il->pci_dev->subsystem_device);
46bc8d4b 3473 il->cfg->sku &= ~IL_SKU_A;
be663ab6
WYG		 3474 }
3475
9406f797 3476 IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n",
e7392364
SG		 3477 il->bands[IEEE80211_BAND_2GHZ].n_channels,
3478 il->bands[IEEE80211_BAND_5GHZ].n_channels);
be663ab6 3479
a6766ccd 3480 set_bit(S_GEO_CONFIGURED, &il->status);
be663ab6
WYG		 3481
3482 return 0;
3483}
e2ebc833 3484EXPORT_SYMBOL(il_init_geos);
be663ab6
WYG		 3485
3486/*
e2ebc833 3487 * il_free_geos - undo allocations in il_init_geos
be663ab6 3488 */
e7392364
SG		 3489void
3490il_free_geos(struct il_priv *il)
be663ab6 3491{
46bc8d4b
SG		 3492 kfree(il->ieee_channels);
3493 kfree(il->ieee_rates);
a6766ccd 3494 clear_bit(S_GEO_CONFIGURED, &il->status);
be663ab6 3495}
e2ebc833 3496EXPORT_SYMBOL(il_free_geos);
be663ab6 3497
e7392364
SG		 3498static bool
3499il_is_channel_extension(struct il_priv *il, enum ieee80211_band band,
3500 u16 channel, u8 extension_chan_offset)
be663ab6 3501{
e2ebc833 3502 const struct il_channel_info *ch_info;
be663ab6 3503
46bc8d4b 3504 ch_info = il_get_channel_info(il, band, channel);
e2ebc833 3505 if (!il_is_channel_valid(ch_info))
be663ab6
WYG		 3506 return false;
3507
3508 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
e7392364
SG		 3509 return !(ch_info->
3510 ht40_extension_channel & IEEE80211_CHAN_NO_HT40PLUS);
be663ab6 3511 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
e7392364
SG		 3512 return !(ch_info->
3513 ht40_extension_channel & IEEE80211_CHAN_NO_HT40MINUS);
be663ab6
WYG		 3514
3515 return false;
3516}
3517
e7392364 3518bool
83007196 3519il_is_ht40_tx_allowed(struct il_priv *il, struct ieee80211_sta_ht_cap *ht_cap)
be663ab6 3520{
1c03c462 3521 if (!il->ht.enabled || !il->ht.is_40mhz)
be663ab6
WYG		 3522 return false;
3523
3524 /*
3525 * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
3526 * the bit will not set if it is pure 40MHz case
3527 */
3528 if (ht_cap && !ht_cap->ht_supported)
3529 return false;
3530
d3175167 3531#ifdef CONFIG_IWLEGACY_DEBUGFS
46bc8d4b 3532 if (il->disable_ht40)
be663ab6
WYG		 3533 return false;
3534#endif
3535
46bc8d4b 3536 return il_is_channel_extension(il, il->band,
c8b03958 3537 le16_to_cpu(il->staging.channel),
1c03c462 3538 il->ht.extension_chan_offset);
be663ab6 3539}
e2ebc833 3540EXPORT_SYMBOL(il_is_ht40_tx_allowed);
be663ab6 3541
e7392364
SG		 3542static u16
3543il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
be663ab6
WYG		 3544{
3545 u16 new_val;
3546 u16 beacon_factor;
3547
3548 /*
3549 * If mac80211 hasn't given us a beacon interval, program
3550 * the default into the device.
3551 */
3552 if (!beacon_val)
3553 return DEFAULT_BEACON_INTERVAL;
3554
3555 /*
3556 * If the beacon interval we obtained from the peer
3557 * is too large, we'll have to wake up more often
3558 * (and in IBSS case, we'll beacon too much)
3559 *
3560 * For example, if max_beacon_val is 4096, and the
3561 * requested beacon interval is 7000, we'll have to
3562 * use 3500 to be able to wake up on the beacons.
3563 *
3564 * This could badly influence beacon detection stats.
3565 */
3566
3567 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
3568 new_val = beacon_val / beacon_factor;
3569
3570 if (!new_val)
3571 new_val = max_beacon_val;
3572
3573 return new_val;
3574}
3575
3576int
83007196 3577il_send_rxon_timing(struct il_priv *il)
be663ab6
WYG		 3578{
3579 u64 tsf;
3580 s32 interval_tm, rem;
3581 struct ieee80211_conf *conf = NULL;
3582 u16 beacon_int;
83007196 3583 struct ieee80211_vif *vif = il->vif;
be663ab6 3584
6278ddab 3585 conf = &il->hw->conf;
be663ab6 3586
46bc8d4b 3587 lockdep_assert_held(&il->mutex);
be663ab6 3588
c8b03958 3589 memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd));
be663ab6 3590
c8b03958
SG		 3591 il->timing.timestamp = cpu_to_le64(il->timestamp);
3592 il->timing.listen_interval = cpu_to_le16(conf->listen_interval);
be663ab6
WYG		 3593
3594 beacon_int = vif ? vif->bss_conf.beacon_int : 0;
3595
3596 /*
6ce1dc45 3597 * TODO: For IBSS we need to get atim_win from mac80211,
e7392364 3598 * for now just always use 0
be663ab6 3599 */
c8b03958 3600 il->timing.atim_win = 0;
be663ab6 3601
e7392364
SG		 3602 beacon_int =
3603 il_adjust_beacon_interval(beacon_int,
3604 il->hw_params.max_beacon_itrvl *
3605 TIME_UNIT);
c8b03958 3606 il->timing.beacon_interval = cpu_to_le16(beacon_int);
be663ab6 3607
e7392364 3608 tsf = il->timestamp; /* tsf is modifed by do_div: copy it */
be663ab6
WYG		 3609 interval_tm = beacon_int * TIME_UNIT;
3610 rem = do_div(tsf, interval_tm);
c8b03958 3611 il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
be663ab6 3612
c8b03958 3613 il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1;
be663ab6 3614
e7392364 3615 D_ASSOC("beacon interval %d beacon timer %d beacon tim %d\n",
c8b03958
SG		 3616 le16_to_cpu(il->timing.beacon_interval),
3617 le32_to_cpu(il->timing.beacon_init_val),
3618 le16_to_cpu(il->timing.atim_win));
be663ab6 3619
63d0f0c5 3620 return il_send_cmd_pdu(il, C_RXON_TIMING, sizeof(il->timing),
c8b03958 3621 &il->timing);
be663ab6 3622}
e2ebc833 3623EXPORT_SYMBOL(il_send_rxon_timing);
be663ab6
WYG		 3624
3625void
83007196 3626il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt)
be663ab6 3627{
c8b03958 3628 struct il_rxon_cmd *rxon = &il->staging;
be663ab6
WYG		 3629
3630 if (hw_decrypt)
3631 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
3632 else
3633 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
3634
3635}
e2ebc833 3636EXPORT_SYMBOL(il_set_rxon_hwcrypto);
be663ab6
WYG		 3637
3638/* validate RXON structure is valid */
3639int
83007196 3640il_check_rxon_cmd(struct il_priv *il)
be663ab6 3641{
c8b03958 3642 struct il_rxon_cmd *rxon = &il->staging;
be663ab6
WYG		 3643 bool error = false;
3644
3645 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
3646 if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
9406f797 3647 IL_WARN("check 2.4G: wrong narrow\n");
be663ab6
WYG		 3648 error = true;
3649 }
3650 if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
9406f797 3651 IL_WARN("check 2.4G: wrong radar\n");
be663ab6
WYG		 3652 error = true;
3653 }
3654 } else {
3655 if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
9406f797 3656 IL_WARN("check 5.2G: not short slot!\n");
be663ab6
WYG		 3657 error = true;
3658 }
3659 if (rxon->flags & RXON_FLG_CCK_MSK) {
9406f797 3660 IL_WARN("check 5.2G: CCK!\n");
be663ab6
WYG		 3661 error = true;
3662 }
3663 }
3664 if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
9406f797 3665 IL_WARN("mac/bssid mcast!\n");
be663ab6
WYG		 3666 error = true;
3667 }
3668
3669 /* make sure basic rates 6Mbps and 1Mbps are supported */
2eb05816
SG		 3670 if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 &&
3671 (rxon->cck_basic_rates & RATE_1M_MASK) == 0) {
9406f797 3672 IL_WARN("neither 1 nor 6 are basic\n");
be663ab6
WYG		 3673 error = true;
3674 }
3675
3676 if (le16_to_cpu(rxon->assoc_id) > 2007) {
9406f797 3677 IL_WARN("aid > 2007\n");
be663ab6
WYG		 3678 error = true;
3679 }
3680
e7392364
SG		 3681 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) ==
3682 (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
9406f797 3683 IL_WARN("CCK and short slot\n");
be663ab6
WYG		 3684 error = true;
3685 }
3686
e7392364
SG		 3687 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) ==
3688 (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
9406f797 3689 IL_WARN("CCK and auto detect");
be663ab6
WYG		 3690 error = true;
3691 }
3692
e7392364
SG		 3693 if ((rxon->
3694 flags & (RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK)) ==
3695 RXON_FLG_TGG_PROTECT_MSK) {
9406f797 3696 IL_WARN("TGg but no auto-detect\n");
be663ab6
WYG		 3697 error = true;
3698 }
3699
3700 if (error)
e7392364 3701 IL_WARN("Tuning to channel %d\n", le16_to_cpu(rxon->channel));
be663ab6
WYG		 3702
3703 if (error) {
9406f797 3704 IL_ERR("Invalid RXON\n");
be663ab6
WYG		 3705 return -EINVAL;
3706 }
3707 return 0;
3708}
e2ebc833 3709EXPORT_SYMBOL(il_check_rxon_cmd);
be663ab6
WYG		 3710
3711/**
e2ebc833 3712 * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
46bc8d4b 3713 * @il: staging_rxon is compared to active_rxon
be663ab6
WYG		 3714 *
3715 * If the RXON structure is changing enough to require a new tune,
3716 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
3717 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
3718 */
e7392364 3719int
83007196 3720il_full_rxon_required(struct il_priv *il)
be663ab6 3721{
c8b03958
SG		 3722 const struct il_rxon_cmd *staging = &il->staging;
3723 const struct il_rxon_cmd *active = &il->active;
be663ab6
WYG		 3724
3725#define CHK(cond) \
3726 if ((cond)) { \
58de00a4 3727 D_INFO("need full RXON - " #cond "\n"); \
be663ab6
WYG		 3728 return 1; \
3729 }
3730
3731#define CHK_NEQ(c1, c2) \
3732 if ((c1) != (c2)) { \
58de00a4 3733 D_INFO("need full RXON - " \
be663ab6
WYG		 3734 #c1 " != " #c2 " - %d != %d\n", \
3735 (c1), (c2)); \
3736 return 1; \
3737 }
3738
3739 /* These items are only settable from the full RXON command */
c8b03958 3740 CHK(!il_is_associated(il));
be663ab6
WYG		 3741 CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr));
3742 CHK(compare_ether_addr(staging->node_addr, active->node_addr));
e7392364
SG		 3743 CHK(compare_ether_addr
3744 (staging->wlap_bssid_addr, active->wlap_bssid_addr));
be663ab6
WYG		 3745 CHK_NEQ(staging->dev_type, active->dev_type);
3746 CHK_NEQ(staging->channel, active->channel);
3747 CHK_NEQ(staging->air_propagation, active->air_propagation);
3748 CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
3749 active->ofdm_ht_single_stream_basic_rates);
3750 CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
3751 active->ofdm_ht_dual_stream_basic_rates);
3752 CHK_NEQ(staging->assoc_id, active->assoc_id);
3753
3754 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
3755 * be updated with the RXON_ASSOC command -- however only some
3756 * flag transitions are allowed using RXON_ASSOC */
3757
3758 /* Check if we are not switching bands */
3759 CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
3760 active->flags & RXON_FLG_BAND_24G_MSK);
3761
3762 /* Check if we are switching association toggle */
3763 CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
3764 active->filter_flags & RXON_FILTER_ASSOC_MSK);
3765
3766#undef CHK
3767#undef CHK_NEQ
3768
3769 return 0;
3770}
e2ebc833 3771EXPORT_SYMBOL(il_full_rxon_required);
be663ab6 3772
e7392364 3773u8
83007196 3774il_get_lowest_plcp(struct il_priv *il)
be663ab6
WYG		 3775{
3776 /*
3777 * Assign the lowest rate -- should really get this from
3778 * the beacon skb from mac80211.
3779 */
c8b03958 3780 if (il->staging.flags & RXON_FLG_BAND_24G_MSK)
2eb05816 3781 return RATE_1M_PLCP;
be663ab6 3782 else
2eb05816 3783 return RATE_6M_PLCP;
be663ab6 3784}
e2ebc833 3785EXPORT_SYMBOL(il_get_lowest_plcp);
be663ab6 3786
e7392364 3787static void
83007196 3788_il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
be663ab6 3789{
c8b03958 3790 struct il_rxon_cmd *rxon = &il->staging;
be663ab6 3791
1c03c462 3792 if (!il->ht.enabled) {
e7392364
SG		 3793 rxon->flags &=
3794 ~(RXON_FLG_CHANNEL_MODE_MSK |
3795 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | RXON_FLG_HT40_PROT_MSK
3796 | RXON_FLG_HT_PROT_MSK);
be663ab6
WYG		 3797 return;
3798 }
3799
e7392364 3800 rxon->flags |=
1c03c462 3801 cpu_to_le32(il->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS);
be663ab6
WYG		 3802
3803 /* Set up channel bandwidth:
3804 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
3805 /* clear the HT channel mode before set the mode */
e7392364
SG		 3806 rxon->flags &=
3807 ~(RXON_FLG_CHANNEL_MODE_MSK | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
83007196 3808 if (il_is_ht40_tx_allowed(il, NULL)) {
be663ab6 3809 /* pure ht40 */
1c03c462 3810 if (il->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
be663ab6
WYG		 3811 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
3812 /* Note: control channel is opposite of extension channel */
1c03c462 3813 switch (il->ht.extension_chan_offset) {
be663ab6
WYG		 3814 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3815 rxon->flags &=
e7392364 3816 ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG		 3817 break;
3818 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
e7392364 3819 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG		 3820 break;
3821 }
3822 } else {
3823 /* Note: control channel is opposite of extension channel */
1c03c462 3824 switch (il->ht.extension_chan_offset) {
be663ab6
WYG		 3825 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3826 rxon->flags &=
e7392364 3827 ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
be663ab6
WYG		 3828 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3829 break;
3830 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
e7392364 3831 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG		 3832 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3833 break;
3834 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
3835 default:
3836 /* channel location only valid if in Mixed mode */
e7392364 3837 IL_ERR("invalid extension channel offset\n");
be663ab6
WYG		 3838 break;
3839 }
3840 }
3841 } else {
3842 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
3843 }
3844
c39ae9fd
SG		 3845 if (il->ops->hcmd->set_rxon_chain)
3846 il->ops->hcmd->set_rxon_chain(il);
be663ab6 3847
58de00a4 3848 D_ASSOC("rxon flags 0x%X operation mode :0x%X "
e7392364 3849 "extension channel offset 0x%x\n", le32_to_cpu(rxon->flags),
1c03c462 3850 il->ht.protection, il->ht.extension_chan_offset);
be663ab6
WYG		 3851}
3852
e7392364
SG		 3853void
3854il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
be663ab6 3855{
83007196 3856 _il_set_rxon_ht(il, ht_conf);
be663ab6 3857}
e2ebc833 3858EXPORT_SYMBOL(il_set_rxon_ht);
be663ab6
WYG		 3859
3860/* Return valid, unused, channel for a passive scan to reset the RF */
e7392364
SG		 3861u8
3862il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band)
be663ab6 3863{
e2ebc833 3864 const struct il_channel_info *ch_info;
be663ab6
WYG		 3865 int i;
3866 u8 channel = 0;
3867 u8 min, max;
be663ab6
WYG		 3868
3869 if (band == IEEE80211_BAND_5GHZ) {
3870 min = 14;
46bc8d4b 3871 max = il->channel_count;
be663ab6
WYG		 3872 } else {
3873 min = 0;
3874 max = 14;
3875 }
3876
3877 for (i = min; i < max; i++) {
17d6e557 3878 channel = il->channel_info[i].channel;
c8b03958 3879 if (channel == le16_to_cpu(il->staging.channel))
be663ab6
WYG		 3880 continue;
3881
46bc8d4b 3882 ch_info = il_get_channel_info(il, band, channel);
e2ebc833 3883 if (il_is_channel_valid(ch_info))
be663ab6
WYG		 3884 break;
3885 }
3886
3887 return channel;
3888}
e2ebc833 3889EXPORT_SYMBOL(il_get_single_channel_number);
be663ab6
WYG		 3890
3891/**
e2ebc833 3892 * il_set_rxon_channel - Set the band and channel values in staging RXON
be663ab6
WYG		 3893 * @ch: requested channel as a pointer to struct ieee80211_channel
3894
3895 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
3896 * in the staging RXON flag structure based on the ch->band
3897 */
3898int
83007196 3899il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch)
be663ab6
WYG		 3900{
3901 enum ieee80211_band band = ch->band;
3902 u16 channel = ch->hw_value;
3903
c8b03958 3904 if (le16_to_cpu(il->staging.channel) == channel && il->band == band)
be663ab6
WYG		 3905 return 0;
3906
c8b03958 3907 il->staging.channel = cpu_to_le16(channel);
be663ab6 3908 if (band == IEEE80211_BAND_5GHZ)
c8b03958 3909 il->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
be663ab6 3910 else
c8b03958 3911 il->staging.flags |= RXON_FLG_BAND_24G_MSK;
be663ab6 3912
46bc8d4b 3913 il->band = band;
be663ab6 3914
58de00a4 3915 D_INFO("Staging channel set to %d [%d]\n", channel, band);
be663ab6
WYG		 3916
3917 return 0;
3918}
e2ebc833 3919EXPORT_SYMBOL(il_set_rxon_channel);
be663ab6 3920
e7392364 3921void
83007196
SG		 3922il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band,
3923 struct ieee80211_vif *vif)
be663ab6
WYG		 3924{
3925 if (band == IEEE80211_BAND_5GHZ) {
c8b03958 3926 il->staging.flags &=
e7392364
SG		 3927 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
3928 RXON_FLG_CCK_MSK);
c8b03958 3929 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3930 } else {
e2ebc833 3931 /* Copied from il_post_associate() */
be663ab6 3932 if (vif && vif->bss_conf.use_short_slot)
c8b03958 3933 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3934 else
c8b03958 3935 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3936
c8b03958
SG		 3937 il->staging.flags |= RXON_FLG_BAND_24G_MSK;
3938 il->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
3939 il->staging.flags &= ~RXON_FLG_CCK_MSK;
be663ab6
WYG		 3940 }
3941}
e2ebc833 3942EXPORT_SYMBOL(il_set_flags_for_band);
be663ab6
WYG		 3943
3944/*
3945 * initialize rxon structure with default values from eeprom
3946 */
e7392364 3947void
83007196 3948il_connection_init_rx_config(struct il_priv *il)
be663ab6 3949{
e2ebc833 3950 const struct il_channel_info *ch_info;
be663ab6 3951
c8b03958 3952 memset(&il->staging, 0, sizeof(il->staging));
be663ab6 3953
83007196 3954 if (!il->vif) {
0f8b90f5 3955 il->staging.dev_type = RXON_DEV_TYPE_ESS;
83007196
SG		 3956 } else if (il->vif->type == NL80211_IFTYPE_STATION) {
3957 il->staging.dev_type = RXON_DEV_TYPE_ESS;
3958 il->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
3959 } else if (il->vif->type == NL80211_IFTYPE_ADHOC) {
3960 il->staging.dev_type = RXON_DEV_TYPE_IBSS;
3961 il->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
3962 il->staging.filter_flags =
3963 RXON_FILTER_BCON_AWARE_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
3964 } else {
3965 IL_ERR("Unsupported interface type %d\n", il->vif->type);
3966 return;
3967 }
be663ab6
WYG		 3968
3969#if 0
3970 /* TODO: Figure out when short_preamble would be set and cache from
3971 * that */
46bc8d4b 3972 if (!hw_to_local(il->hw)->short_preamble)
c8b03958 3973 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6 3974 else
c8b03958 3975 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6
WYG		 3976#endif
3977
e7392364 3978 ch_info =
c8b03958 3979 il_get_channel_info(il, il->band, le16_to_cpu(il->active.channel));
be663ab6
WYG		 3980
3981 if (!ch_info)
46bc8d4b 3982 ch_info = &il->channel_info[0];
be663ab6 3983
c8b03958 3984 il->staging.channel = cpu_to_le16(ch_info->channel);
46bc8d4b 3985 il->band = ch_info->band;
be663ab6 3986
83007196 3987 il_set_flags_for_band(il, il->band, il->vif);
be663ab6 3988
c8b03958 3989 il->staging.ofdm_basic_rates =
e2ebc833 3990 (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
c8b03958 3991 il->staging.cck_basic_rates =
e2ebc833 3992 (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
be663ab6
WYG		 3993
3994 /* clear both MIX and PURE40 mode flag */
c8b03958 3995 il->staging.flags &=
e7392364 3996 ~(RXON_FLG_CHANNEL_MODE_MIXED | RXON_FLG_CHANNEL_MODE_PURE_40);
83007196
SG		 3997 if (il->vif)
3998 memcpy(il->staging.node_addr, il->vif->addr, ETH_ALEN);
be663ab6 3999
c8b03958
SG		 4000 il->staging.ofdm_ht_single_stream_basic_rates = 0xff;
4001 il->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
be663ab6 4002}
e2ebc833 4003EXPORT_SYMBOL(il_connection_init_rx_config);
be663ab6 4004
e7392364
SG		 4005void
4006il_set_rate(struct il_priv *il)
be663ab6
WYG		 4007{
4008 const struct ieee80211_supported_band *hw = NULL;
4009 struct ieee80211_rate *rate;
be663ab6
WYG		 4010 int i;
4011
46bc8d4b 4012 hw = il_get_hw_mode(il, il->band);
be663ab6 4013 if (!hw) {
9406f797 4014 IL_ERR("Failed to set rate: unable to get hw mode\n");
be663ab6
WYG		 4015 return;
4016 }
4017
46bc8d4b 4018 il->active_rate = 0;
be663ab6
WYG		 4019
4020 for (i = 0; i < hw->n_bitrates; i++) {
4021 rate = &(hw->bitrates[i]);
2eb05816 4022 if (rate->hw_value < RATE_COUNT_LEGACY)
46bc8d4b 4023 il->active_rate |= (1 << rate->hw_value);
be663ab6
WYG		 4024 }
4025
58de00a4 4026 D_RATE("Set active_rate = %0x\n", il->active_rate);
be663ab6 4027
c8b03958 4028 il->staging.cck_basic_rates =
e7392364 4029 (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
be663ab6 4030
c8b03958 4031 il->staging.ofdm_basic_rates =
e7392364 4032 (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
be663ab6 4033}
e2ebc833 4034EXPORT_SYMBOL(il_set_rate);
be663ab6 4035
e7392364
SG		 4036void
4037il_chswitch_done(struct il_priv *il, bool is_success)
be663ab6 4038{
a6766ccd 4039 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4040 return;
4041
a6766ccd 4042 if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
83007196 4043 ieee80211_chswitch_done(il->vif, is_success);
be663ab6 4044}
e2ebc833 4045EXPORT_SYMBOL(il_chswitch_done);
be663ab6 4046
e7392364
SG		 4047void
4048il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4049{
dcae1c64 4050 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4051 struct il_csa_notification *csa = &(pkt->u.csa_notif);
c8b03958 4052 struct il_rxon_cmd *rxon = (void *)&il->active;
be663ab6 4053
a6766ccd 4054 if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
51e65257
SG		 4055 return;
4056
46bc8d4b 4057 if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) {
51e65257 4058 rxon->channel = csa->channel;
c8b03958 4059 il->staging.channel = csa->channel;
e7392364 4060 D_11H("CSA notif: channel %d\n", le16_to_cpu(csa->channel));
46bc8d4b 4061 il_chswitch_done(il, true);
51e65257 4062 } else {
9406f797 4063 IL_ERR("CSA notif (fail) : channel %d\n",
e7392364 4064 le16_to_cpu(csa->channel));
46bc8d4b 4065 il_chswitch_done(il, false);
be663ab6
WYG		 4066 }
4067}
d2dfb33e 4068EXPORT_SYMBOL(il_hdl_csa);
be663ab6 4069
d3175167 4070#ifdef CONFIG_IWLEGACY_DEBUG
e7392364 4071void
83007196 4072il_print_rx_config_cmd(struct il_priv *il)
be663ab6 4073{
c8b03958 4074 struct il_rxon_cmd *rxon = &il->staging;
be663ab6 4075
58de00a4 4076 D_RADIO("RX CONFIG:\n");
46bc8d4b 4077 il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e7392364 4078 D_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
58de00a4 4079 D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
e7392364 4080 D_RADIO("u32 filter_flags: 0x%08x\n", le32_to_cpu(rxon->filter_flags));
58de00a4 4081 D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
e7392364
SG		 4082 D_RADIO("u8 ofdm_basic_rates: 0x%02x\n", rxon->ofdm_basic_rates);
4083 D_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
58de00a4
SG		 4084 D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
4085 D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
e7392364 4086 D_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
be663ab6 4087}
e2ebc833 4088EXPORT_SYMBOL(il_print_rx_config_cmd);
be663ab6
WYG		 4089#endif
4090/**
e2ebc833 4091 * il_irq_handle_error - called for HW or SW error interrupt from card
be663ab6 4092 */
e7392364
SG		 4093void
4094il_irq_handle_error(struct il_priv *il)
be663ab6 4095{
e2ebc833 4096 /* Set the FW error flag -- cleared on il_down */
a6766ccd 4097 set_bit(S_FW_ERROR, &il->status);
be663ab6
WYG		 4098
4099 /* Cancel currently queued command. */
a6766ccd 4100 clear_bit(S_HCMD_ACTIVE, &il->status);
be663ab6 4101
e7392364 4102 IL_ERR("Loaded firmware version: %s\n", il->hw->wiphy->fw_version);
be663ab6 4103
1600b875
SG		 4104 il->ops->dump_nic_error_log(il);
4105 if (il->ops->dump_fh)
4106 il->ops->dump_fh(il, NULL, false);
d3175167 4107#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4108 if (il_get_debug_level(il) & IL_DL_FW_ERRORS)
83007196 4109 il_print_rx_config_cmd(il);
be663ab6
WYG		 4110#endif
4111
46bc8d4b 4112 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4113
4114 /* Keep the restart process from trying to send host
4115 * commands by clearing the INIT status bit */
a6766ccd 4116 clear_bit(S_READY, &il->status);
be663ab6 4117
a6766ccd 4118 if (!test_bit(S_EXIT_PENDING, &il->status)) {
58de00a4 4119 IL_DBG(IL_DL_FW_ERRORS,
e7392364 4120 "Restarting adapter due to uCode error.\n");
be663ab6 4121
46bc8d4b
SG		 4122 if (il->cfg->mod_params->restart_fw)
4123 queue_work(il->workqueue, &il->restart);
be663ab6
WYG		 4124 }
4125}
e2ebc833 4126EXPORT_SYMBOL(il_irq_handle_error);
be663ab6 4127
e7392364
SG		 4128static int
4129il_apm_stop_master(struct il_priv *il)
be663ab6
WYG		 4130{
4131 int ret = 0;
4132
4133 /* stop device's busmaster DMA activity */
46bc8d4b 4134 il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
be663ab6 4135
e7392364
SG		 4136 ret =
4137 _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
4138 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
be663ab6 4139 if (ret)
9406f797 4140 IL_WARN("Master Disable Timed Out, 100 usec\n");
be663ab6 4141
58de00a4 4142 D_INFO("stop master\n");
be663ab6
WYG		 4143
4144 return ret;
4145}
4146
e7392364
SG		 4147void
4148il_apm_stop(struct il_priv *il)
be663ab6 4149{
58de00a4 4150 D_INFO("Stop card, put in low power state\n");
be663ab6
WYG		 4151
4152 /* Stop device's DMA activity */
46bc8d4b 4153 il_apm_stop_master(il);
be663ab6
WYG		 4154
4155 /* Reset the entire device */
46bc8d4b 4156 il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
be663ab6
WYG		 4157
4158 udelay(10);
4159
4160 /*
4161 * Clear "initialization complete" bit to move adapter from
4162 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
4163 */
e7392364 4164 il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
be663ab6 4165}
e7392364 4166EXPORT_SYMBOL(il_apm_stop);
be663ab6
WYG		 4167
4168/*
4169 * Start up NIC's basic functionality after it has been reset
e2ebc833 4170 * (e.g. after platform boot, or shutdown via il_apm_stop())
be663ab6
WYG		 4171 * NOTE: This does not load uCode nor start the embedded processor
4172 */
e7392364
SG		 4173int
4174il_apm_init(struct il_priv *il)
be663ab6
WYG		 4175{
4176 int ret = 0;
4177 u16 lctl;
4178
58de00a4 4179 D_INFO("Init card's basic functions\n");
be663ab6
WYG		 4180
4181 /*
4182 * Use "set_bit" below rather than "write", to preserve any hardware
4183 * bits already set by default after reset.
4184 */
4185
4186 /* Disable L0S exit timer (platform NMI Work/Around) */
46bc8d4b 4187 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
e7392364 4188 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
be663ab6
WYG		 4189
4190 /*
4191 * Disable L0s without affecting L1;
4192 * don't wait for ICH L0s (ICH bug W/A)
4193 */
46bc8d4b 4194 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
e7392364 4195 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
be663ab6
WYG		 4196
4197 /* Set FH wait threshold to maximum (HW error during stress W/A) */
e7392364 4198 il_set_bit(il, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
be663ab6
WYG		 4199
4200 /*
4201 * Enable HAP INTA (interrupt from management bus) to
4202 * wake device's PCI Express link L1a -> L0s
25985edc 4203 * NOTE: This is no-op for 3945 (non-existent bit)
be663ab6 4204 */
46bc8d4b 4205 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 4206 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
be663ab6
WYG		 4207
4208 /*
4209 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
4210 * Check if BIOS (or OS) enabled L1-ASPM on this device.
4211 * If so (likely), disable L0S, so device moves directly L0->L1;
4212 * costs negligible amount of power savings.
4213 * If not (unlikely), enable L0S, so there is at least some
4214 * power savings, even without L1.
4215 */
89ef1ed2 4216 if (il->cfg->set_l0s) {
46bc8d4b 4217 lctl = il_pcie_link_ctl(il);
be663ab6 4218 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
e7392364 4219 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
be663ab6 4220 /* L1-ASPM enabled; disable(!) L0S */
46bc8d4b 4221 il_set_bit(il, CSR_GIO_REG,
e7392364 4222 CSR_GIO_REG_VAL_L0S_ENABLED);
58de00a4 4223 D_POWER("L1 Enabled; Disabling L0S\n");
be663ab6
WYG		 4224 } else {
4225 /* L1-ASPM disabled; enable(!) L0S */
46bc8d4b 4226 il_clear_bit(il, CSR_GIO_REG,
e7392364 4227 CSR_GIO_REG_VAL_L0S_ENABLED);
58de00a4 4228 D_POWER("L1 Disabled; Enabling L0S\n");
be663ab6
WYG		 4229 }
4230 }
4231
4232 /* Configure analog phase-lock-loop before activating to D0A */
89ef1ed2 4233 if (il->cfg->pll_cfg_val)
46bc8d4b 4234 il_set_bit(il, CSR_ANA_PLL_CFG,
89ef1ed2 4235 il->cfg->pll_cfg_val);
be663ab6
WYG		 4236
4237 /*
4238 * Set "initialization complete" bit to move adapter from
4239 * D0U* --> D0A* (powered-up active) state.
4240 */
46bc8d4b 4241 il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
be663ab6
WYG		 4242
4243 /*
4244 * Wait for clock stabilization; once stabilized, access to
db54eb57 4245 * device-internal resources is supported, e.g. il_wr_prph()
be663ab6
WYG		 4246 * and accesses to uCode SRAM.
4247 */
e7392364
SG		 4248 ret =
4249 _il_poll_bit(il, CSR_GP_CNTRL,
4250 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
4251 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
be663ab6 4252 if (ret < 0) {
58de00a4 4253 D_INFO("Failed to init the card\n");
be663ab6
WYG		 4254 goto out;
4255 }
4256
4257 /*
4258 * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
4259 * BSM (Boostrap State Machine) is only in 3945 and 4965.
4260 *
4261 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
4262 * do not disable clocks. This preserves any hardware bits already
4263 * set by default in "CLK_CTRL_REG" after reset.
4264 */
89ef1ed2 4265 if (il->cfg->use_bsm)
db54eb57 4266 il_wr_prph(il, APMG_CLK_EN_REG,
e7392364 4267 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
be663ab6 4268 else
e7392364 4269 il_wr_prph(il, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
be663ab6
WYG		 4270 udelay(20);
4271
4272 /* Disable L1-Active */
46bc8d4b 4273 il_set_bits_prph(il, APMG_PCIDEV_STT_REG,
e7392364 4274 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
be663ab6
WYG		 4275
4276out:
4277 return ret;
4278}
e7392364 4279EXPORT_SYMBOL(il_apm_init);
be663ab6 4280
e7392364
SG		 4281int
4282il_set_tx_power(struct il_priv *il, s8 tx_power, bool force)
be663ab6
WYG		 4283{
4284 int ret;
4285 s8 prev_tx_power;
43f12d47 4286 bool defer;
be663ab6 4287
46bc8d4b 4288 lockdep_assert_held(&il->mutex);
be663ab6 4289
46bc8d4b 4290 if (il->tx_power_user_lmt == tx_power && !force)
be663ab6
WYG		 4291 return 0;
4292
1600b875 4293 if (!il->ops->send_tx_power)
be663ab6
WYG		 4294 return -EOPNOTSUPP;
4295
332704a5
SG		 4296 /* 0 dBm mean 1 milliwatt */
4297 if (tx_power < 0) {
e7392364 4298 IL_WARN("Requested user TXPOWER %d below 1 mW.\n", tx_power);
be663ab6
WYG		 4299 return -EINVAL;
4300 }
4301
46bc8d4b 4302 if (tx_power > il->tx_power_device_lmt) {
e7392364
SG		 4303 IL_WARN("Requested user TXPOWER %d above upper limit %d.\n",
4304 tx_power, il->tx_power_device_lmt);
be663ab6
WYG		 4305 return -EINVAL;
4306 }
4307
46bc8d4b 4308 if (!il_is_ready_rf(il))
be663ab6
WYG		 4309 return -EIO;
4310
43f12d47
SG		 4311 /* scan complete and commit_rxon use tx_power_next value,
4312 * it always need to be updated for newest request */
46bc8d4b 4313 il->tx_power_next = tx_power;
43f12d47
SG		 4314
4315 /* do not set tx power when scanning or channel changing */
a6766ccd 4316 defer = test_bit(S_SCANNING, &il->status) ||
c8b03958 4317 memcmp(&il->active, &il->staging, sizeof(il->staging));
43f12d47 4318 if (defer && !force) {
58de00a4 4319 D_INFO("Deferring tx power set\n");
be663ab6
WYG		 4320 return 0;
4321 }
4322
46bc8d4b
SG		 4323 prev_tx_power = il->tx_power_user_lmt;
4324 il->tx_power_user_lmt = tx_power;
be663ab6 4325
1600b875 4326 ret = il->ops->send_tx_power(il);
be663ab6
WYG		 4327
4328 /* if fail to set tx_power, restore the orig. tx power */
4329 if (ret) {
46bc8d4b
SG		 4330 il->tx_power_user_lmt = prev_tx_power;
4331 il->tx_power_next = prev_tx_power;
be663ab6
WYG		 4332 }
4333 return ret;
4334}
e2ebc833 4335EXPORT_SYMBOL(il_set_tx_power);
be663ab6 4336
e7392364
SG		 4337void
4338il_send_bt_config(struct il_priv *il)
be663ab6 4339{
e2ebc833 4340 struct il_bt_cmd bt_cmd = {
be663ab6
WYG		 4341 .lead_time = BT_LEAD_TIME_DEF,
4342 .max_kill = BT_MAX_KILL_DEF,
4343 .kill_ack_mask = 0,
4344 .kill_cts_mask = 0,
4345 };
4346
4347 if (!bt_coex_active)
4348 bt_cmd.flags = BT_COEX_DISABLE;
4349 else
4350 bt_cmd.flags = BT_COEX_ENABLE;
4351
58de00a4 4352 D_INFO("BT coex %s\n",
e7392364 4353 (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
be663ab6 4354
e7392364 4355 if (il_send_cmd_pdu(il, C_BT_CONFIG, sizeof(struct il_bt_cmd), &bt_cmd))
9406f797 4356 IL_ERR("failed to send BT Coex Config\n");
be663ab6 4357}
e2ebc833 4358EXPORT_SYMBOL(il_send_bt_config);
be663ab6 4359
e7392364
SG		 4360int
4361il_send_stats_request(struct il_priv *il, u8 flags, bool clear)
be663ab6 4362{
ebf0d90d 4363 struct il_stats_cmd stats_cmd = {
e7392364 4364 .configuration_flags = clear ? IL_STATS_CONF_CLEAR_STATS : 0,
be663ab6
WYG		 4365 };
4366
4367 if (flags & CMD_ASYNC)
e7392364
SG		 4368 return il_send_cmd_pdu_async(il, C_STATS, sizeof(struct il_stats_cmd),
4369 &stats_cmd, NULL);
be663ab6 4370 else
e7392364
SG		 4371 return il_send_cmd_pdu(il, C_STATS, sizeof(struct il_stats_cmd),
4372 &stats_cmd);
be663ab6 4373}
ebf0d90d 4374EXPORT_SYMBOL(il_send_stats_request);
be663ab6 4375
e7392364
SG		 4376void
4377il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4378{
d3175167 4379#ifdef CONFIG_IWLEGACY_DEBUG
dcae1c64 4380 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4381 struct il_sleep_notification *sleep = &(pkt->u.sleep_notif);
58de00a4 4382 D_RX("sleep mode: %d, src: %d\n",
1722f8e1 4383 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
be663ab6
WYG		 4384#endif
4385}
d2dfb33e 4386EXPORT_SYMBOL(il_hdl_pm_sleep);
be663ab6 4387
e7392364
SG		 4388void
4389il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4390{
dcae1c64 4391 struct il_rx_pkt *pkt = rxb_addr(rxb);
e94a4099 4392 u32 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
e7392364
SG		 4393 D_RADIO("Dumping %d bytes of unhandled notification for %s:\n", len,
4394 il_get_cmd_string(pkt->hdr.cmd));
46bc8d4b 4395 il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len);
be663ab6 4396}
d2dfb33e 4397EXPORT_SYMBOL(il_hdl_pm_debug_stats);
be663ab6 4398
e7392364
SG		 4399void
4400il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4401{
dcae1c64 4402 struct il_rx_pkt *pkt = rxb_addr(rxb);
be663ab6 4403
9406f797 4404 IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) "
e7392364
SG		 4405 "seq 0x%04X ser 0x%08X\n",
4406 le32_to_cpu(pkt->u.err_resp.error_type),
4407 il_get_cmd_string(pkt->u.err_resp.cmd_id),
4408 pkt->u.err_resp.cmd_id,
4409 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
4410 le32_to_cpu(pkt->u.err_resp.error_info));
be663ab6 4411}
6e9848b4 4412EXPORT_SYMBOL(il_hdl_error);
be663ab6 4413
e7392364
SG		 4414void
4415il_clear_isr_stats(struct il_priv *il)
be663ab6 4416{
46bc8d4b 4417 memset(&il->isr_stats, 0, sizeof(il->isr_stats));
be663ab6
WYG		 4418}
4419
e7392364
SG		 4420int
4421il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
4422 const struct ieee80211_tx_queue_params *params)
be663ab6 4423{
46bc8d4b 4424 struct il_priv *il = hw->priv;
be663ab6
WYG		 4425 unsigned long flags;
4426 int q;
4427
58de00a4 4428 D_MAC80211("enter\n");
be663ab6 4429
46bc8d4b 4430 if (!il_is_ready_rf(il)) {
58de00a4 4431 D_MAC80211("leave - RF not ready\n");
be663ab6
WYG		 4432 return -EIO;
4433 }
4434
4435 if (queue >= AC_NUM) {
58de00a4 4436 D_MAC80211("leave - queue >= AC_NUM %d\n", queue);
be663ab6
WYG		 4437 return 0;
4438 }
4439
4440 q = AC_NUM - 1 - queue;
4441
46bc8d4b 4442 spin_lock_irqsave(&il->lock, flags);
be663ab6 4443
8d44f2bd 4444 il->qos_data.def_qos_parm.ac[q].cw_min =
e7392364 4445 cpu_to_le16(params->cw_min);
8d44f2bd 4446 il->qos_data.def_qos_parm.ac[q].cw_max =
e7392364 4447 cpu_to_le16(params->cw_max);
8d44f2bd
SG		 4448 il->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
4449 il->qos_data.def_qos_parm.ac[q].edca_txop =
e7392364 4450 cpu_to_le16((params->txop * 32));
be663ab6 4451
8d44f2bd 4452 il->qos_data.def_qos_parm.ac[q].reserved1 = 0;
be663ab6 4453
46bc8d4b 4454 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 4455
58de00a4 4456 D_MAC80211("leave\n");
be663ab6
WYG		 4457 return 0;
4458}
e2ebc833 4459EXPORT_SYMBOL(il_mac_conf_tx);
be663ab6 4460
e7392364
SG		 4461int
4462il_mac_tx_last_beacon(struct ieee80211_hw *hw)
be663ab6 4463{
46bc8d4b 4464 struct il_priv *il = hw->priv;
be663ab6 4465
46bc8d4b 4466 return il->ibss_manager == IL_IBSS_MANAGER;
be663ab6 4467}
e2ebc833 4468EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon);
be663ab6
WYG		 4469
4470static int
83007196 4471il_set_mode(struct il_priv *il)
be663ab6 4472{
83007196 4473 il_connection_init_rx_config(il);
be663ab6 4474
c39ae9fd
SG		 4475 if (il->ops->hcmd->set_rxon_chain)
4476 il->ops->hcmd->set_rxon_chain(il);
be663ab6 4477
83007196 4478 return il_commit_rxon(il);
be663ab6
WYG		 4479}
4480
be663ab6 4481int
e2ebc833 4482il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 4483{
46bc8d4b 4484 struct il_priv *il = hw->priv;
be663ab6
WYG		 4485 int err;
4486
e7392364 4487 D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
be663ab6 4488
46bc8d4b 4489 mutex_lock(&il->mutex);
be663ab6 4490
46bc8d4b 4491 if (!il_is_ready_rf(il)) {
9406f797 4492 IL_WARN("Try to add interface when device not ready\n");
be663ab6
WYG		 4493 err = -EINVAL;
4494 goto out;
4495 }
4496
83007196 4497 if (il->vif) {
be663ab6
WYG		 4498 err = -EOPNOTSUPP;
4499 goto out;
4500 }
4501
83007196 4502 il->vif = vif;
20c47eba 4503 il->iw_mode = vif->type;
be663ab6 4504
83007196 4505 err = il_set_mode(il);
17d6e557 4506 if (err) {
83007196 4507 il->vif = NULL;
17d6e557
SG		 4508 il->iw_mode = NL80211_IFTYPE_STATION;
4509 }
be663ab6 4510
e7392364 4511out:
46bc8d4b 4512 mutex_unlock(&il->mutex);
be663ab6 4513
58de00a4 4514 D_MAC80211("leave\n");
be663ab6
WYG		 4515 return err;
4516}
e2ebc833 4517EXPORT_SYMBOL(il_mac_add_interface);
be663ab6 4518
e7392364
SG		 4519static void
4520il_teardown_interface(struct il_priv *il, struct ieee80211_vif *vif,
4521 bool mode_change)
be663ab6 4522{
46bc8d4b 4523 lockdep_assert_held(&il->mutex);
be663ab6 4524
46bc8d4b
SG		 4525 if (il->scan_vif == vif) {
4526 il_scan_cancel_timeout(il, 200);
4527 il_force_scan_end(il);
be663ab6
WYG		 4528 }
4529
dee9a09e 4530 if (!mode_change)
83007196 4531 il_set_mode(il);
dee9a09e 4532
be663ab6
WYG		 4533}
4534
e7392364
SG		 4535void
4536il_mac_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 4537{
46bc8d4b 4538 struct il_priv *il = hw->priv;
be663ab6 4539
58de00a4 4540 D_MAC80211("enter\n");
be663ab6 4541
46bc8d4b 4542 mutex_lock(&il->mutex);
be663ab6 4543
83007196
SG		 4544 WARN_ON(il->vif != vif);
4545 il->vif = NULL;
be663ab6 4546
46bc8d4b 4547 il_teardown_interface(il, vif, false);
be663ab6 4548
46bc8d4b
SG		 4549 memset(il->bssid, 0, ETH_ALEN);
4550 mutex_unlock(&il->mutex);
be663ab6 4551
58de00a4 4552 D_MAC80211("leave\n");
be663ab6
WYG		 4553
4554}
e2ebc833 4555EXPORT_SYMBOL(il_mac_remove_interface);
be663ab6 4556
e7392364
SG		 4557int
4558il_alloc_txq_mem(struct il_priv *il)
be663ab6 4559{
46bc8d4b 4560 if (!il->txq)
e7392364
SG		 4561 il->txq =
4562 kzalloc(sizeof(struct il_tx_queue) *
89ef1ed2 4563 il->cfg->num_of_queues, GFP_KERNEL);
46bc8d4b 4564 if (!il->txq) {
9406f797 4565 IL_ERR("Not enough memory for txq\n");
be663ab6
WYG		 4566 return -ENOMEM;
4567 }
4568 return 0;
4569}
e2ebc833 4570EXPORT_SYMBOL(il_alloc_txq_mem);
be663ab6 4571
e7392364
SG		 4572void
4573il_txq_mem(struct il_priv *il)
be663ab6 4574{
46bc8d4b
SG		 4575 kfree(il->txq);
4576 il->txq = NULL;
be663ab6 4577}
e2ebc833 4578EXPORT_SYMBOL(il_txq_mem);
be663ab6 4579
d3175167 4580#ifdef CONFIG_IWLEGACY_DEBUGFS
be663ab6 4581
e2ebc833 4582#define IL_TRAFFIC_DUMP_SIZE (IL_TRAFFIC_ENTRY_SIZE * IL_TRAFFIC_ENTRIES)
be663ab6 4583
e7392364
SG		 4584void
4585il_reset_traffic_log(struct il_priv *il)
be663ab6 4586{
46bc8d4b
SG		 4587 il->tx_traffic_idx = 0;
4588 il->rx_traffic_idx = 0;
4589 if (il->tx_traffic)
4590 memset(il->tx_traffic, 0, IL_TRAFFIC_DUMP_SIZE);
4591 if (il->rx_traffic)
4592 memset(il->rx_traffic, 0, IL_TRAFFIC_DUMP_SIZE);
be663ab6
WYG		 4593}
4594
e7392364
SG		 4595int
4596il_alloc_traffic_mem(struct il_priv *il)
be663ab6 4597{
e2ebc833 4598 u32 traffic_size = IL_TRAFFIC_DUMP_SIZE;
be663ab6 4599
d2ddf621 4600 if (il_debug_level & IL_DL_TX) {
46bc8d4b 4601 if (!il->tx_traffic) {
e7392364 4602 il->tx_traffic = kzalloc(traffic_size, GFP_KERNEL);
46bc8d4b 4603 if (!il->tx_traffic)
be663ab6
WYG		 4604 return -ENOMEM;
4605 }
4606 }
d2ddf621 4607 if (il_debug_level & IL_DL_RX) {
46bc8d4b 4608 if (!il->rx_traffic) {
e7392364 4609 il->rx_traffic = kzalloc(traffic_size, GFP_KERNEL);
46bc8d4b 4610 if (!il->rx_traffic)
be663ab6
WYG		 4611 return -ENOMEM;
4612 }
4613 }
46bc8d4b 4614 il_reset_traffic_log(il);
be663ab6
WYG		 4615 return 0;
4616}
e2ebc833 4617EXPORT_SYMBOL(il_alloc_traffic_mem);
be663ab6 4618
e7392364
SG		 4619void
4620il_free_traffic_mem(struct il_priv *il)
be663ab6 4621{
46bc8d4b
SG		 4622 kfree(il->tx_traffic);
4623 il->tx_traffic = NULL;
be663ab6 4624
46bc8d4b
SG		 4625 kfree(il->rx_traffic);
4626 il->rx_traffic = NULL;
be663ab6 4627}
e2ebc833 4628EXPORT_SYMBOL(il_free_traffic_mem);
be663ab6 4629
e7392364
SG		 4630void
4631il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
4632 struct ieee80211_hdr *header)
be663ab6
WYG		 4633{
4634 __le16 fc;
4635 u16 len;
4636
d2ddf621 4637 if (likely(!(il_debug_level & IL_DL_TX)))
be663ab6
WYG		 4638 return;
4639
46bc8d4b 4640 if (!il->tx_traffic)
be663ab6
WYG		 4641 return;
4642
4643 fc = header->frame_control;
4644 if (ieee80211_is_data(fc)) {
e7392364
SG		 4645 len =
4646 (length >
4647 IL_TRAFFIC_ENTRY_SIZE) ? IL_TRAFFIC_ENTRY_SIZE : length;
46bc8d4b 4648 memcpy((il->tx_traffic +
e7392364
SG		 4649 (il->tx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)), header,
4650 len);
46bc8d4b 4651 il->tx_traffic_idx =
e7392364 4652 (il->tx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES;
be663ab6
WYG		 4653 }
4654}
e2ebc833 4655EXPORT_SYMBOL(il_dbg_log_tx_data_frame);
be663ab6 4656
e7392364
SG		 4657void
4658il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
4659 struct ieee80211_hdr *header)
be663ab6
WYG		 4660{
4661 __le16 fc;
4662 u16 len;
4663
d2ddf621 4664 if (likely(!(il_debug_level & IL_DL_RX)))
be663ab6
WYG		 4665 return;
4666
46bc8d4b 4667 if (!il->rx_traffic)
be663ab6
WYG		 4668 return;
4669
4670 fc = header->frame_control;
4671 if (ieee80211_is_data(fc)) {
e7392364
SG		 4672 len =
4673 (length >
4674 IL_TRAFFIC_ENTRY_SIZE) ? IL_TRAFFIC_ENTRY_SIZE : length;
46bc8d4b 4675 memcpy((il->rx_traffic +
e7392364
SG		 4676 (il->rx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)), header,
4677 len);
46bc8d4b 4678 il->rx_traffic_idx =
e7392364 4679 (il->rx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES;
be663ab6
WYG		 4680 }
4681}
e2ebc833 4682EXPORT_SYMBOL(il_dbg_log_rx_data_frame);
be663ab6 4683
e7392364
SG		 4684const char *
4685il_get_mgmt_string(int cmd)
be663ab6
WYG		 4686{
4687 switch (cmd) {
e2ebc833
SG		 4688 IL_CMD(MANAGEMENT_ASSOC_REQ);
4689 IL_CMD(MANAGEMENT_ASSOC_RESP);
4690 IL_CMD(MANAGEMENT_REASSOC_REQ);
4691 IL_CMD(MANAGEMENT_REASSOC_RESP);
4692 IL_CMD(MANAGEMENT_PROBE_REQ);
4693 IL_CMD(MANAGEMENT_PROBE_RESP);
4694 IL_CMD(MANAGEMENT_BEACON);
4695 IL_CMD(MANAGEMENT_ATIM);
4696 IL_CMD(MANAGEMENT_DISASSOC);
4697 IL_CMD(MANAGEMENT_AUTH);
4698 IL_CMD(MANAGEMENT_DEAUTH);
4699 IL_CMD(MANAGEMENT_ACTION);
be663ab6
WYG		 4700 default:
4701 return "UNKNOWN";
4702
4703 }
4704}
4705
e7392364
SG		 4706const char *
4707il_get_ctrl_string(int cmd)
be663ab6
WYG		 4708{
4709 switch (cmd) {
e2ebc833
SG		 4710 IL_CMD(CONTROL_BACK_REQ);
4711 IL_CMD(CONTROL_BACK);
4712 IL_CMD(CONTROL_PSPOLL);
4713 IL_CMD(CONTROL_RTS);
4714 IL_CMD(CONTROL_CTS);
4715 IL_CMD(CONTROL_ACK);
4716 IL_CMD(CONTROL_CFEND);
4717 IL_CMD(CONTROL_CFENDACK);
be663ab6
WYG		 4718 default:
4719 return "UNKNOWN";
4720
4721 }
4722}
4723
e7392364
SG		 4724void
4725il_clear_traffic_stats(struct il_priv *il)
be663ab6 4726{
46bc8d4b
SG		 4727 memset(&il->tx_stats, 0, sizeof(struct traffic_stats));
4728 memset(&il->rx_stats, 0, sizeof(struct traffic_stats));
be663ab6
WYG		 4729}
4730
4731/*
d3175167 4732 * if CONFIG_IWLEGACY_DEBUGFS defined,
e2ebc833 4733 * il_update_stats function will
be663ab6 4734 * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass
ebf0d90d 4735 * Use debugFs to display the rx/rx_stats
d3175167 4736 * if CONFIG_IWLEGACY_DEBUGFS not being defined, then no MGMT and CTRL
be663ab6 4737 * information will be recorded, but DATA pkt still will be recorded
e2ebc833 4738 * for the reason of il_led.c need to control the led blinking based on
be663ab6
WYG		 4739 * number of tx and rx data.
4740 *
4741 */
4742void
46bc8d4b 4743il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
be663ab6 4744{
e7392364 4745 struct traffic_stats *stats;
be663ab6
WYG		 4746
4747 if (is_tx)
46bc8d4b 4748 stats = &il->tx_stats;
be663ab6 4749 else
46bc8d4b 4750 stats = &il->rx_stats;
be663ab6
WYG		 4751
4752 if (ieee80211_is_mgmt(fc)) {
4753 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
4754 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
4755 stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
4756 break;
4757 case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
4758 stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
4759 break;
4760 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
4761 stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
4762 break;
4763 case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
4764 stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
4765 break;
4766 case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
4767 stats->mgmt[MANAGEMENT_PROBE_REQ]++;
4768 break;
4769 case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
4770 stats->mgmt[MANAGEMENT_PROBE_RESP]++;
4771 break;
4772 case cpu_to_le16(IEEE80211_STYPE_BEACON):
4773 stats->mgmt[MANAGEMENT_BEACON]++;
4774 break;
4775 case cpu_to_le16(IEEE80211_STYPE_ATIM):
4776 stats->mgmt[MANAGEMENT_ATIM]++;
4777 break;
4778 case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
4779 stats->mgmt[MANAGEMENT_DISASSOC]++;
4780 break;
4781 case cpu_to_le16(IEEE80211_STYPE_AUTH):
4782 stats->mgmt[MANAGEMENT_AUTH]++;
4783 break;
4784 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
4785 stats->mgmt[MANAGEMENT_DEAUTH]++;
4786 break;
4787 case cpu_to_le16(IEEE80211_STYPE_ACTION):
4788 stats->mgmt[MANAGEMENT_ACTION]++;
4789 break;
4790 }
4791 } else if (ieee80211_is_ctl(fc)) {
4792 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
4793 case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
4794 stats->ctrl[CONTROL_BACK_REQ]++;
4795 break;
4796 case cpu_to_le16(IEEE80211_STYPE_BACK):
4797 stats->ctrl[CONTROL_BACK]++;
4798 break;
4799 case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
4800 stats->ctrl[CONTROL_PSPOLL]++;
4801 break;
4802 case cpu_to_le16(IEEE80211_STYPE_RTS):
4803 stats->ctrl[CONTROL_RTS]++;
4804 break;
4805 case cpu_to_le16(IEEE80211_STYPE_CTS):
4806 stats->ctrl[CONTROL_CTS]++;
4807 break;
4808 case cpu_to_le16(IEEE80211_STYPE_ACK):
4809 stats->ctrl[CONTROL_ACK]++;
4810 break;
4811 case cpu_to_le16(IEEE80211_STYPE_CFEND):
4812 stats->ctrl[CONTROL_CFEND]++;
4813 break;
4814 case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
4815 stats->ctrl[CONTROL_CFENDACK]++;
4816 break;
4817 }
4818 } else {
4819 /* data */
4820 stats->data_cnt++;
4821 stats->data_bytes += len;
4822 }
4823}
e2ebc833 4824EXPORT_SYMBOL(il_update_stats);
be663ab6
WYG		 4825#endif
4826
e7392364
SG		 4827int
4828il_force_reset(struct il_priv *il, bool external)
be663ab6 4829{
e2ebc833 4830 struct il_force_reset *force_reset;
be663ab6 4831
a6766ccd 4832 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4833 return -EINVAL;
4834
46bc8d4b 4835 force_reset = &il->force_reset;
be663ab6
WYG		 4836 force_reset->reset_request_count++;
4837 if (!external) {
4838 if (force_reset->last_force_reset_jiffies &&
4839 time_after(force_reset->last_force_reset_jiffies +
e7392364 4840 force_reset->reset_duration, jiffies)) {
58de00a4 4841 D_INFO("force reset rejected\n");
be663ab6
WYG		 4842 force_reset->reset_reject_count++;
4843 return -EAGAIN;
4844 }
4845 }
4846 force_reset->reset_success_count++;
4847 force_reset->last_force_reset_jiffies = jiffies;
dd6d2a8a
SG		 4848
4849 /*
4850 * if the request is from external(ex: debugfs),
4851 * then always perform the request in regardless the module
4852 * parameter setting
4853 * if the request is from internal (uCode error or driver
4854 * detect failure), then fw_restart module parameter
4855 * need to be check before performing firmware reload
4856 */
4857
46bc8d4b 4858 if (!external && !il->cfg->mod_params->restart_fw) {
58de00a4 4859 D_INFO("Cancel firmware reload based on "
e7392364 4860 "module parameter setting\n");
dd6d2a8a 4861 return 0;
be663ab6 4862 }
dd6d2a8a 4863
9406f797 4864 IL_ERR("On demand firmware reload\n");
dd6d2a8a 4865
e2ebc833 4866 /* Set the FW error flag -- cleared on il_down */
a6766ccd 4867 set_bit(S_FW_ERROR, &il->status);
46bc8d4b 4868 wake_up(&il->wait_command_queue);
dd6d2a8a
SG		 4869 /*
4870 * Keep the restart process from trying to send host
4871 * commands by clearing the INIT status bit
4872 */
a6766ccd 4873 clear_bit(S_READY, &il->status);
46bc8d4b 4874 queue_work(il->workqueue, &il->restart);
dd6d2a8a 4875
be663ab6
WYG		 4876 return 0;
4877}
4878
4879int
e7392364 4880il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
be663ab6
WYG		 4881 enum nl80211_iftype newtype, bool newp2p)
4882{
46bc8d4b 4883 struct il_priv *il = hw->priv;
be663ab6
WYG		 4884 int err;
4885
8c9c48d5
SG		 4886 if (newp2p)
4887 return -EOPNOTSUPP;
be663ab6 4888
46bc8d4b 4889 mutex_lock(&il->mutex);
be663ab6 4890
83007196 4891 if (!il->vif || !il_is_ready_rf(il)) {
ffd8c746
JB		 4892 /*
4893 * Huh? But wait ... this can maybe happen when
4894 * we're in the middle of a firmware restart!
4895 */
4896 err = -EBUSY;
4897 goto out;
4898 }
4899
be663ab6 4900 /* success */
46bc8d4b 4901 il_teardown_interface(il, vif, true);
be663ab6 4902 vif->type = newtype;
8c9c48d5 4903 vif->p2p = false;
83007196 4904 err = il_set_mode(il);
be663ab6
WYG		 4905 WARN_ON(err);
4906 /*
4907 * We've switched internally, but submitting to the
4908 * device may have failed for some reason. Mask this
4909 * error, because otherwise mac80211 will not switch
4910 * (and set the interface type back) and we'll be
4911 * out of sync with it.
4912 */
4913 err = 0;
4914
e7392364 4915out:
46bc8d4b 4916 mutex_unlock(&il->mutex);
be663ab6
WYG		 4917 return err;
4918}
e2ebc833 4919EXPORT_SYMBOL(il_mac_change_interface);
be663ab6
WYG		 4920
4921/*
4922 * On every watchdog tick we check (latest) time stamp. If it does not
4923 * change during timeout period and queue is not empty we reset firmware.
4924 */
e7392364
SG		 4925static int
4926il_check_stuck_queue(struct il_priv *il, int cnt)
be663ab6 4927{
46bc8d4b 4928 struct il_tx_queue *txq = &il->txq[cnt];
e2ebc833 4929 struct il_queue *q = &txq->q;
be663ab6
WYG		 4930 unsigned long timeout;
4931 int ret;
4932
4933 if (q->read_ptr == q->write_ptr) {
4934 txq->time_stamp = jiffies;
4935 return 0;
4936 }
4937
e7392364
SG		 4938 timeout =
4939 txq->time_stamp +
89ef1ed2 4940 msecs_to_jiffies(il->cfg->wd_timeout);
be663ab6
WYG		 4941
4942 if (time_after(jiffies, timeout)) {
e7392364 4943 IL_ERR("Queue %d stuck for %u ms.\n", q->id,
89ef1ed2 4944 il->cfg->wd_timeout);
46bc8d4b 4945 ret = il_force_reset(il, false);
be663ab6
WYG		 4946 return (ret == -EAGAIN) ? 0 : 1;
4947 }
4948
4949 return 0;
4950}
4951
4952/*
4953 * Making watchdog tick be a quarter of timeout assure we will
4954 * discover the queue hung between timeout and 1.25*timeout
4955 */
e2ebc833 4956#define IL_WD_TICK(timeout) ((timeout) / 4)
be663ab6
WYG		 4957
4958/*
4959 * Watchdog timer callback, we check each tx queue for stuck, if if hung
4960 * we reset the firmware. If everything is fine just rearm the timer.
4961 */
e7392364
SG		 4962void
4963il_bg_watchdog(unsigned long data)
be663ab6 4964{
46bc8d4b 4965 struct il_priv *il = (struct il_priv *)data;
be663ab6
WYG		 4966 int cnt;
4967 unsigned long timeout;
4968
a6766ccd 4969 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4970 return;
4971
89ef1ed2 4972 timeout = il->cfg->wd_timeout;
be663ab6
WYG		 4973 if (timeout == 0)
4974 return;
4975
4976 /* monitor and check for stuck cmd queue */
46bc8d4b 4977 if (il_check_stuck_queue(il, il->cmd_queue))
be663ab6
WYG		 4978 return;
4979
4980 /* monitor and check for other stuck queues */
46bc8d4b
SG		 4981 if (il_is_any_associated(il)) {
4982 for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) {
be663ab6 4983 /* skip as we already checked the command queue */
46bc8d4b 4984 if (cnt == il->cmd_queue)
be663ab6 4985 continue;
46bc8d4b 4986 if (il_check_stuck_queue(il, cnt))
be663ab6
WYG		 4987 return;
4988 }
4989 }
4990
e7392364
SG		 4991 mod_timer(&il->watchdog,
4992 jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
be663ab6 4993}
e2ebc833 4994EXPORT_SYMBOL(il_bg_watchdog);
be663ab6 4995
e7392364
SG		 4996void
4997il_setup_watchdog(struct il_priv *il)
be663ab6 4998{
89ef1ed2 4999 unsigned int timeout = il->cfg->wd_timeout;
be663ab6
WYG		 5000
5001 if (timeout)
46bc8d4b 5002 mod_timer(&il->watchdog,
e2ebc833 5003 jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
be663ab6 5004 else
46bc8d4b 5005 del_timer(&il->watchdog);
be663ab6 5006}
e2ebc833 5007EXPORT_SYMBOL(il_setup_watchdog);
be663ab6
WYG		 5008
5009/*
5010 * extended beacon time format
5011 * time in usec will be changed into a 32-bit value in extended:internal format
5012 * the extended part is the beacon counts
5013 * the internal part is the time in usec within one beacon interval
5014 */
5015u32
e7392364 5016il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval)
be663ab6
WYG		 5017{
5018 u32 quot;
5019 u32 rem;
5020 u32 interval = beacon_interval * TIME_UNIT;
5021
5022 if (!interval || !usec)
5023 return 0;
5024
e7392364
SG		 5025 quot =
5026 (usec /
5027 interval) & (il_beacon_time_mask_high(il,
5028 il->hw_params.
5029 beacon_time_tsf_bits) >> il->
5030 hw_params.beacon_time_tsf_bits);
5031 rem =
5032 (usec % interval) & il_beacon_time_mask_low(il,
5033 il->hw_params.
5034 beacon_time_tsf_bits);
be663ab6 5035
46bc8d4b 5036 return (quot << il->hw_params.beacon_time_tsf_bits) + rem;
be663ab6 5037}
e2ebc833 5038EXPORT_SYMBOL(il_usecs_to_beacons);
be663ab6
WYG		 5039
5040/* base is usually what we get from ucode with each received frame,
5041 * the same as HW timer counter counting down
5042 */
e7392364 5043__le32
1722f8e1 5044il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
e7392364 5045 u32 beacon_interval)
be663ab6 5046{
46bc8d4b 5047 u32 base_low = base & il_beacon_time_mask_low(il,
e7392364
SG		 5048 il->hw_params.
5049 beacon_time_tsf_bits);
46bc8d4b 5050 u32 addon_low = addon & il_beacon_time_mask_low(il,
e7392364
SG		 5051 il->hw_params.
5052 beacon_time_tsf_bits);
be663ab6 5053 u32 interval = beacon_interval * TIME_UNIT;
46bc8d4b 5054 u32 res = (base & il_beacon_time_mask_high(il,
e7392364
SG		 5055 il->hw_params.
5056 beacon_time_tsf_bits)) +
5057 (addon & il_beacon_time_mask_high(il,
5058 il->hw_params.
5059 beacon_time_tsf_bits));
be663ab6
WYG		 5060
5061 if (base_low > addon_low)
5062 res += base_low - addon_low;
5063 else if (base_low < addon_low) {
5064 res += interval + base_low - addon_low;
46bc8d4b 5065 res += (1 << il->hw_params.beacon_time_tsf_bits);
be663ab6 5066 } else
46bc8d4b 5067 res += (1 << il->hw_params.beacon_time_tsf_bits);
be663ab6
WYG		 5068
5069 return cpu_to_le32(res);
5070}
e2ebc833 5071EXPORT_SYMBOL(il_add_beacon_time);
be663ab6
WYG		 5072
5073#ifdef CONFIG_PM
5074
e7392364
SG		 5075int
5076il_pci_suspend(struct device *device)
be663ab6
WYG		 5077{
5078 struct pci_dev *pdev = to_pci_dev(device);
46bc8d4b 5079 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 5080
5081 /*
5082 * This function is called when system goes into suspend state
e2ebc833
SG		 5083 * mac80211 will call il_mac_stop() from the mac80211 suspend function
5084 * first but since il_mac_stop() has no knowledge of who the caller is,
be663ab6
WYG		 5085 * it will not call apm_ops.stop() to stop the DMA operation.
5086 * Calling apm_ops.stop here to make sure we stop the DMA.
5087 */
46bc8d4b 5088 il_apm_stop(il);
be663ab6
WYG		 5089
5090 return 0;
5091}
e2ebc833 5092EXPORT_SYMBOL(il_pci_suspend);
be663ab6 5093
e7392364
SG		 5094int
5095il_pci_resume(struct device *device)
be663ab6
WYG		 5096{
5097 struct pci_dev *pdev = to_pci_dev(device);
46bc8d4b 5098 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 5099 bool hw_rfkill = false;
5100
5101 /*
5102 * We disable the RETRY_TIMEOUT register (0x41) to keep
5103 * PCI Tx retries from interfering with C3 CPU state.
5104 */
5105 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
5106
46bc8d4b 5107 il_enable_interrupts(il);
be663ab6 5108
e7392364 5109 if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
be663ab6
WYG		 5110 hw_rfkill = true;
5111
5112 if (hw_rfkill)
a6766ccd 5113 set_bit(S_RF_KILL_HW, &il->status);
be663ab6 5114 else
a6766ccd 5115 clear_bit(S_RF_KILL_HW, &il->status);
be663ab6 5116
46bc8d4b 5117 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill);
be663ab6
WYG		 5118
5119 return 0;
5120}
e2ebc833 5121EXPORT_SYMBOL(il_pci_resume);
be663ab6 5122
e2ebc833
SG		 5123const struct dev_pm_ops il_pm_ops = {
5124 .suspend = il_pci_suspend,
5125 .resume = il_pci_resume,
5126 .freeze = il_pci_suspend,
5127 .thaw = il_pci_resume,
5128 .poweroff = il_pci_suspend,
5129 .restore = il_pci_resume,
be663ab6 5130};
e2ebc833 5131EXPORT_SYMBOL(il_pm_ops);
be663ab6
WYG		 5132
5133#endif /* CONFIG_PM */
5134
5135static void
83007196 5136il_update_qos(struct il_priv *il)
be663ab6 5137{
a6766ccd 5138 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5139 return;
5140
8d44f2bd 5141 il->qos_data.def_qos_parm.qos_flags = 0;
be663ab6 5142
8d44f2bd
SG		 5143 if (il->qos_data.qos_active)
5144 il->qos_data.def_qos_parm.qos_flags |=
e7392364 5145 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
be663ab6 5146
1c03c462 5147 if (il->ht.enabled)
8d44f2bd 5148 il->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
be663ab6 5149
58de00a4 5150 D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
8d44f2bd 5151 il->qos_data.qos_active, il->qos_data.def_qos_parm.qos_flags);
be663ab6 5152
b96ed60c 5153 il_send_cmd_pdu_async(il, C_QOS_PARAM, sizeof(struct il_qosparam_cmd),
8d44f2bd 5154 &il->qos_data.def_qos_parm, NULL);
be663ab6
WYG		 5155}
5156
5157/**
e2ebc833 5158 * il_mac_config - mac80211 config callback
be663ab6 5159 */
e7392364
SG		 5160int
5161il_mac_config(struct ieee80211_hw *hw, u32 changed)
be663ab6 5162{
46bc8d4b 5163 struct il_priv *il = hw->priv;
e2ebc833 5164 const struct il_channel_info *ch_info;
be663ab6
WYG		 5165 struct ieee80211_conf *conf = &hw->conf;
5166 struct ieee80211_channel *channel = conf->channel;
46bc8d4b 5167 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6
WYG		 5168 unsigned long flags = 0;
5169 int ret = 0;
5170 u16 ch;
5171 int scan_active = 0;
7c2cde2e 5172 bool ht_changed = false;
be663ab6 5173
c39ae9fd 5174 if (WARN_ON(!il->ops->legacy))
be663ab6
WYG		 5175 return -EOPNOTSUPP;
5176
46bc8d4b 5177 mutex_lock(&il->mutex);
be663ab6 5178
e7392364
SG		 5179 D_MAC80211("enter to channel %d changed 0x%X\n", channel->hw_value,
5180 changed);
be663ab6 5181
a6766ccd 5182 if (unlikely(test_bit(S_SCANNING, &il->status))) {
be663ab6 5183 scan_active = 1;
58de00a4 5184 D_MAC80211("scan active\n");
be663ab6
WYG		 5185 }
5186
e7392364
SG		 5187 if (changed &
5188 (IEEE80211_CONF_CHANGE_SMPS | IEEE80211_CONF_CHANGE_CHANNEL)) {
be663ab6 5189 /* mac80211 uses static for non-HT which is what we want */
46bc8d4b 5190 il->current_ht_config.smps = conf->smps_mode;
be663ab6
WYG		 5191
5192 /*
5193 * Recalculate chain counts.
5194 *
5195 * If monitor mode is enabled then mac80211 will
5196 * set up the SM PS mode to OFF if an HT channel is
5197 * configured.
5198 */
c39ae9fd
SG		 5199 if (il->ops->hcmd->set_rxon_chain)
5200 il->ops->hcmd->set_rxon_chain(il);
be663ab6
WYG		 5201 }
5202
5203 /* during scanning mac80211 will delay channel setting until
5204 * scan finish with changed = 0
5205 */
5206 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
17d6e557 5207
be663ab6
WYG		 5208 if (scan_active)
5209 goto set_ch_out;
5210
5211 ch = channel->hw_value;
46bc8d4b 5212 ch_info = il_get_channel_info(il, channel->band, ch);
e2ebc833 5213 if (!il_is_channel_valid(ch_info)) {
58de00a4 5214 D_MAC80211("leave - invalid channel\n");
be663ab6
WYG		 5215 ret = -EINVAL;
5216 goto set_ch_out;
5217 }
5218
46bc8d4b 5219 if (il->iw_mode == NL80211_IFTYPE_ADHOC &&
e2ebc833 5220 !il_is_channel_ibss(ch_info)) {
58de00a4 5221 D_MAC80211("leave - not IBSS channel\n");
eb85de3f
SG		 5222 ret = -EINVAL;
5223 goto set_ch_out;
5224 }
5225
46bc8d4b 5226 spin_lock_irqsave(&il->lock, flags);
be663ab6 5227
17d6e557 5228 /* Configure HT40 channels */
1c03c462
SG		 5229 if (il->ht.enabled != conf_is_ht(conf)) {
5230 il->ht.enabled = conf_is_ht(conf);
17d6e557
SG		 5231 ht_changed = true;
5232 }
1c03c462 5233 if (il->ht.enabled) {
17d6e557 5234 if (conf_is_ht40_minus(conf)) {
1c03c462 5235 il->ht.extension_chan_offset =
e7392364 5236 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
1c03c462 5237 il->ht.is_40mhz = true;
17d6e557 5238 } else if (conf_is_ht40_plus(conf)) {
1c03c462 5239 il->ht.extension_chan_offset =
e7392364 5240 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
1c03c462 5241 il->ht.is_40mhz = true;
17d6e557 5242 } else {
1c03c462 5243 il->ht.extension_chan_offset =
e7392364 5244 IEEE80211_HT_PARAM_CHA_SEC_NONE;
1c03c462 5245 il->ht.is_40mhz = false;
17d6e557
SG		 5246 }
5247 } else
1c03c462 5248 il->ht.is_40mhz = false;
be663ab6 5249
17d6e557
SG		 5250 /*
5251 * Default to no protection. Protection mode will
5252 * later be set from BSS config in il_ht_conf
5253 */
1c03c462 5254 il->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
be663ab6 5255
17d6e557
SG		 5256 /* if we are switching from ht to 2.4 clear flags
5257 * from any ht related info since 2.4 does not
5258 * support ht */
c8b03958
SG		 5259 if ((le16_to_cpu(il->staging.channel) != ch))
5260 il->staging.flags = 0;
be663ab6 5261
83007196 5262 il_set_rxon_channel(il, channel);
17d6e557 5263 il_set_rxon_ht(il, ht_conf);
be663ab6 5264
83007196 5265 il_set_flags_for_band(il, channel->band, il->vif);
be663ab6 5266
46bc8d4b 5267 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5268
c39ae9fd
SG		 5269 if (il->ops->legacy->update_bcast_stations)
5270 ret = il->ops->legacy->update_bcast_stations(il);
be663ab6 5271
e7392364 5272set_ch_out:
be663ab6
WYG		 5273 /* The list of supported rates and rate mask can be different
5274 * for each band; since the band may have changed, reset
5275 * the rate mask to what mac80211 lists */
46bc8d4b 5276 il_set_rate(il);
be663ab6
WYG		 5277 }
5278
e7392364 5279 if (changed & (IEEE80211_CONF_CHANGE_PS | IEEE80211_CONF_CHANGE_IDLE)) {
46bc8d4b 5280 ret = il_power_update_mode(il, false);
be663ab6 5281 if (ret)
58de00a4 5282 D_MAC80211("Error setting sleep level\n");
be663ab6
WYG		 5283 }
5284
5285 if (changed & IEEE80211_CONF_CHANGE_POWER) {
e7392364
SG		 5286 D_MAC80211("TX Power old=%d new=%d\n", il->tx_power_user_lmt,
5287 conf->power_level);
be663ab6 5288
46bc8d4b 5289 il_set_tx_power(il, conf->power_level, false);
be663ab6
WYG		 5290 }
5291
46bc8d4b 5292 if (!il_is_ready(il)) {
58de00a4 5293 D_MAC80211("leave - not ready\n");
be663ab6
WYG		 5294 goto out;
5295 }
5296
5297 if (scan_active)
5298 goto out;
5299
c8b03958 5300 if (memcmp(&il->active, &il->staging, sizeof(il->staging)))
83007196 5301 il_commit_rxon(il);
17d6e557
SG		 5302 else
5303 D_INFO("Not re-sending same RXON configuration.\n");
5304 if (ht_changed)
83007196 5305 il_update_qos(il);
be663ab6
WYG		 5306
5307out:
58de00a4 5308 D_MAC80211("leave\n");
46bc8d4b 5309 mutex_unlock(&il->mutex);
be663ab6
WYG		 5310 return ret;
5311}
e2ebc833 5312EXPORT_SYMBOL(il_mac_config);
be663ab6 5313
e7392364
SG		 5314void
5315il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 5316{
46bc8d4b 5317 struct il_priv *il = hw->priv;
be663ab6 5318 unsigned long flags;
be663ab6 5319
c39ae9fd 5320 if (WARN_ON(!il->ops->legacy))
be663ab6
WYG		 5321 return;
5322
46bc8d4b 5323 mutex_lock(&il->mutex);
58de00a4 5324 D_MAC80211("enter\n");
be663ab6 5325
46bc8d4b
SG		 5326 spin_lock_irqsave(&il->lock, flags);
5327 memset(&il->current_ht_config, 0, sizeof(struct il_ht_config));
5328 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5329
46bc8d4b 5330 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 5331
5332 /* new association get rid of ibss beacon skb */
46bc8d4b
SG		 5333 if (il->beacon_skb)
5334 dev_kfree_skb(il->beacon_skb);
be663ab6 5335
46bc8d4b 5336 il->beacon_skb = NULL;
be663ab6 5337
46bc8d4b 5338 il->timestamp = 0;
be663ab6 5339
46bc8d4b 5340 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5341
46bc8d4b
SG		 5342 il_scan_cancel_timeout(il, 100);
5343 if (!il_is_ready_rf(il)) {
58de00a4 5344 D_MAC80211("leave - not ready\n");
46bc8d4b 5345 mutex_unlock(&il->mutex);
be663ab6
WYG		 5346 return;
5347 }
5348
5349 /* we are restarting association process
5350 * clear RXON_FILTER_ASSOC_MSK bit
5351 */
c8b03958 5352 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
83007196 5353 il_commit_rxon(il);
be663ab6 5354
46bc8d4b 5355 il_set_rate(il);
be663ab6 5356
46bc8d4b 5357 mutex_unlock(&il->mutex);
be663ab6 5358
58de00a4 5359 D_MAC80211("leave\n");
be663ab6 5360}
e2ebc833 5361EXPORT_SYMBOL(il_mac_reset_tsf);
be663ab6 5362
e7392364
SG		 5363static void
5364il_ht_conf(struct il_priv *il, struct ieee80211_vif *vif)
be663ab6 5365{
46bc8d4b 5366 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6
WYG		 5367 struct ieee80211_sta *sta;
5368 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
be663ab6 5369
58de00a4 5370 D_ASSOC("enter:\n");
be663ab6 5371
1c03c462 5372 if (!il->ht.enabled)
be663ab6
WYG		 5373 return;
5374
1c03c462 5375 il->ht.protection =
e7392364 5376 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
1c03c462 5377 il->ht.non_gf_sta_present =
e7392364
SG		 5378 !!(bss_conf->
5379 ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
be663ab6
WYG		 5380
5381 ht_conf->single_chain_sufficient = false;
5382
5383 switch (vif->type) {
5384 case NL80211_IFTYPE_STATION:
5385 rcu_read_lock();
5386 sta = ieee80211_find_sta(vif, bss_conf->bssid);
5387 if (sta) {
5388 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
5389 int maxstreams;
5390
e7392364
SG		 5391 maxstreams =
5392 (ht_cap->mcs.
5393 tx_params & IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
5394 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
be663ab6
WYG		 5395 maxstreams += 1;
5396
232913b5
SG		 5397 if (ht_cap->mcs.rx_mask[1] == 0 &&
5398 ht_cap->mcs.rx_mask[2] == 0)
be663ab6
WYG		 5399 ht_conf->single_chain_sufficient = true;
5400 if (maxstreams <= 1)
5401 ht_conf->single_chain_sufficient = true;
5402 } else {
5403 /*
5404 * If at all, this can only happen through a race
5405 * when the AP disconnects us while we're still
5406 * setting up the connection, in that case mac80211
5407 * will soon tell us about that.
5408 */
5409 ht_conf->single_chain_sufficient = true;
5410 }
5411 rcu_read_unlock();
5412 break;
5413 case NL80211_IFTYPE_ADHOC:
5414 ht_conf->single_chain_sufficient = true;
5415 break;
5416 default:
5417 break;
5418 }
5419
58de00a4 5420 D_ASSOC("leave\n");
be663ab6
WYG		 5421}
5422
e7392364
SG		 5423static inline void
5424il_set_no_assoc(struct il_priv *il, struct ieee80211_vif *vif)
be663ab6 5425{
be663ab6
WYG		 5426 /*
5427 * inform the ucode that there is no longer an
5428 * association and that no more packets should be
5429 * sent
5430 */
c8b03958
SG		 5431 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5432 il->staging.assoc_id = 0;
83007196 5433 il_commit_rxon(il);
be663ab6
WYG		 5434}
5435
e7392364
SG		 5436static void
5437il_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 5438{
46bc8d4b 5439 struct il_priv *il = hw->priv;
be663ab6
WYG		 5440 unsigned long flags;
5441 __le64 timestamp;
5442 struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
5443
5444 if (!skb)
5445 return;
5446
58de00a4 5447 D_MAC80211("enter\n");
be663ab6 5448
46bc8d4b 5449 lockdep_assert_held(&il->mutex);
be663ab6 5450
83007196
SG		 5451 if (!il->beacon_enabled) {
5452 IL_ERR("update beacon with no beaconing enabled\n");
be663ab6
WYG		 5453 dev_kfree_skb(skb);
5454 return;
5455 }
5456
46bc8d4b 5457 spin_lock_irqsave(&il->lock, flags);
be663ab6 5458
46bc8d4b
SG		 5459 if (il->beacon_skb)
5460 dev_kfree_skb(il->beacon_skb);
be663ab6 5461
46bc8d4b 5462 il->beacon_skb = skb;
be663ab6
WYG		 5463
5464 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
46bc8d4b 5465 il->timestamp = le64_to_cpu(timestamp);
be663ab6 5466
58de00a4 5467 D_MAC80211("leave\n");
46bc8d4b 5468 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5469
46bc8d4b 5470 if (!il_is_ready_rf(il)) {
58de00a4 5471 D_MAC80211("leave - RF not ready\n");
be663ab6
WYG		 5472 return;
5473 }
5474
c39ae9fd 5475 il->ops->legacy->post_associate(il);
be663ab6
WYG		 5476}
5477
e7392364
SG		 5478void
5479il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5480 struct ieee80211_bss_conf *bss_conf, u32 changes)
be663ab6 5481{
46bc8d4b 5482 struct il_priv *il = hw->priv;
be663ab6
WYG		 5483 int ret;
5484
c39ae9fd 5485 if (WARN_ON(!il->ops->legacy))
be663ab6
WYG		 5486 return;
5487
58de00a4 5488 D_MAC80211("changes = 0x%X\n", changes);
be663ab6 5489
46bc8d4b 5490 mutex_lock(&il->mutex);
be663ab6 5491
46bc8d4b
SG		 5492 if (!il_is_alive(il)) {
5493 mutex_unlock(&il->mutex);
28a6e577
SG		 5494 return;
5495 }
5496
be663ab6
WYG		 5497 if (changes & BSS_CHANGED_QOS) {
5498 unsigned long flags;
5499
46bc8d4b 5500 spin_lock_irqsave(&il->lock, flags);
8d44f2bd 5501 il->qos_data.qos_active = bss_conf->qos;
83007196 5502 il_update_qos(il);
46bc8d4b 5503 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5504 }
5505
5506 if (changes & BSS_CHANGED_BEACON_ENABLED) {
83007196 5507 /* FIXME: can we remove beacon_enabled ? */
be663ab6 5508 if (vif->bss_conf.enable_beacon)
83007196 5509 il->beacon_enabled = true;
be663ab6 5510 else
83007196 5511 il->beacon_enabled = false;
be663ab6
WYG		 5512 }
5513
5514 if (changes & BSS_CHANGED_BSSID) {
58de00a4 5515 D_MAC80211("BSSID %pM\n", bss_conf->bssid);
be663ab6
WYG		 5516
5517 /*
5518 * If there is currently a HW scan going on in the
5519 * background then we need to cancel it else the RXON
5520 * below/in post_associate will fail.
5521 */
46bc8d4b 5522 if (il_scan_cancel_timeout(il, 100)) {
e7392364
SG		 5523 IL_WARN("Aborted scan still in progress after 100ms\n");
5524 D_MAC80211("leaving - scan abort failed.\n");
46bc8d4b 5525 mutex_unlock(&il->mutex);
be663ab6
WYG		 5526 return;
5527 }
5528
5529 /* mac80211 only sets assoc when in STATION mode */
5530 if (vif->type == NL80211_IFTYPE_ADHOC || bss_conf->assoc) {
c8b03958 5531 memcpy(il->staging.bssid_addr, bss_conf->bssid,
e7392364 5532 ETH_ALEN);
be663ab6
WYG		 5533
5534 /* currently needed in a few places */
46bc8d4b 5535 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
be663ab6 5536 } else {
c8b03958 5537 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
be663ab6
WYG		 5538 }
5539
5540 }
5541
5542 /*
5543 * This needs to be after setting the BSSID in case
5544 * mac80211 decides to do both changes at once because
5545 * it will invoke post_associate.
5546 */
232913b5 5547 if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON))
e2ebc833 5548 il_beacon_update(hw, vif);
be663ab6
WYG		 5549
5550 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
e7392364 5551 D_MAC80211("ERP_PREAMBLE %d\n", bss_conf->use_short_preamble);
be663ab6 5552 if (bss_conf->use_short_preamble)
c8b03958 5553 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6 5554 else
c8b03958 5555 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6
WYG		 5556 }
5557
5558 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
e7392364 5559 D_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
232913b5 5560 if (bss_conf->use_cts_prot && il->band != IEEE80211_BAND_5GHZ)
c8b03958 5561 il->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
be663ab6 5562 else
c8b03958 5563 il->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
be663ab6 5564 if (bss_conf->use_cts_prot)
c8b03958 5565 il->staging.flags |= RXON_FLG_SELF_CTS_EN;
be663ab6 5566 else
c8b03958 5567 il->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
be663ab6
WYG		 5568 }
5569
5570 if (changes & BSS_CHANGED_BASIC_RATES) {
5571 /* XXX use this information
5572 *
e2ebc833 5573 * To do that, remove code from il_set_rate() and put something
be663ab6
WYG		 5574 * like this here:
5575 *
e7392364 5576 if (A-band)
c8b03958 5577 il->staging.ofdm_basic_rates =
e7392364
SG		 5578 bss_conf->basic_rates;
5579 else
c8b03958 5580 il->staging.ofdm_basic_rates =
e7392364 5581 bss_conf->basic_rates >> 4;
c8b03958 5582 il->staging.cck_basic_rates =
e7392364 5583 bss_conf->basic_rates & 0xF;
be663ab6
WYG		 5584 */
5585 }
5586
5587 if (changes & BSS_CHANGED_HT) {
46bc8d4b 5588 il_ht_conf(il, vif);
be663ab6 5589
c39ae9fd
SG		 5590 if (il->ops->hcmd->set_rxon_chain)
5591 il->ops->hcmd->set_rxon_chain(il);
be663ab6
WYG		 5592 }
5593
5594 if (changes & BSS_CHANGED_ASSOC) {
58de00a4 5595 D_MAC80211("ASSOC %d\n", bss_conf->assoc);
be663ab6 5596 if (bss_conf->assoc) {
46bc8d4b 5597 il->timestamp = bss_conf->timestamp;
be663ab6 5598
46bc8d4b 5599 if (!il_is_rfkill(il))
c39ae9fd 5600 il->ops->legacy->post_associate(il);
be663ab6 5601 } else
46bc8d4b 5602 il_set_no_assoc(il, vif);
be663ab6
WYG		 5603 }
5604
c8b03958 5605 if (changes && il_is_associated(il) && bss_conf->aid) {
e7392364 5606 D_MAC80211("Changes (%#x) while associated\n", changes);
83007196 5607 ret = il_send_rxon_assoc(il);
be663ab6
WYG		 5608 if (!ret) {
5609 /* Sync active_rxon with latest change. */
c8b03958 5610 memcpy((void *)&il->active, &il->staging,
e7392364 5611 sizeof(struct il_rxon_cmd));
be663ab6
WYG		 5612 }
5613 }
5614
5615 if (changes & BSS_CHANGED_BEACON_ENABLED) {
5616 if (vif->bss_conf.enable_beacon) {
c8b03958 5617 memcpy(il->staging.bssid_addr, bss_conf->bssid,
e7392364 5618 ETH_ALEN);
46bc8d4b 5619 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
c39ae9fd 5620 il->ops->legacy->config_ap(il);
be663ab6 5621 } else
46bc8d4b 5622 il_set_no_assoc(il, vif);
be663ab6
WYG		 5623 }
5624
5625 if (changes & BSS_CHANGED_IBSS) {
e7392364 5626 ret =
c39ae9fd
SG		 5627 il->ops->legacy->manage_ibss_station(il, vif,
5628 bss_conf->ibss_joined);
be663ab6 5629 if (ret)
9406f797 5630 IL_ERR("failed to %s IBSS station %pM\n",
e7392364
SG		 5631 bss_conf->ibss_joined ? "add" : "remove",
5632 bss_conf->bssid);
be663ab6
WYG		 5633 }
5634
46bc8d4b 5635 mutex_unlock(&il->mutex);
be663ab6 5636
58de00a4 5637 D_MAC80211("leave\n");
be663ab6 5638}
e2ebc833 5639EXPORT_SYMBOL(il_mac_bss_info_changed);
be663ab6 5640
e7392364
SG		 5641irqreturn_t
5642il_isr(int irq, void *data)
be663ab6 5643{
46bc8d4b 5644 struct il_priv *il = data;
be663ab6
WYG		 5645 u32 inta, inta_mask;
5646 u32 inta_fh;
5647 unsigned long flags;
46bc8d4b 5648 if (!il)
be663ab6
WYG		 5649 return IRQ_NONE;
5650
46bc8d4b 5651 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 5652
5653 /* Disable (but don't clear!) interrupts here to avoid
5654 * back-to-back ISRs and sporadic interrupts from our NIC.
5655 * If we have something to service, the tasklet will re-enable ints.
5656 * If we *don't* have something, we'll re-enable before leaving here. */
e7392364 5657 inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */
841b2cca 5658 _il_wr(il, CSR_INT_MASK, 0x00000000);
be663ab6
WYG		 5659
5660 /* Discover which interrupts are active/pending */
841b2cca
SG		 5661 inta = _il_rd(il, CSR_INT);
5662 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
be663ab6
WYG		 5663
5664 /* Ignore interrupt if there's nothing in NIC to service.
5665 * This may be due to IRQ shared with another device,
5666 * or due to sporadic interrupts thrown from our NIC. */
5667 if (!inta && !inta_fh) {
e7392364 5668 D_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
be663ab6
WYG		 5669 goto none;
5670 }
5671
232913b5 5672 if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) {
be663ab6
WYG		 5673 /* Hardware disappeared. It might have already raised
5674 * an interrupt */
9406f797 5675 IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta);
be663ab6
WYG		 5676 goto unplugged;
5677 }
5678
e7392364
SG		 5679 D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, inta_mask,
5680 inta_fh);
be663ab6
WYG		 5681
5682 inta &= ~CSR_INT_BIT_SCD;
5683
e2ebc833 5684 /* il_irq_tasklet() will service interrupts and re-enable them */
be663ab6 5685 if (likely(inta || inta_fh))
46bc8d4b 5686 tasklet_schedule(&il->irq_tasklet);
be663ab6
WYG		 5687
5688unplugged:
46bc8d4b 5689 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5690 return IRQ_HANDLED;
5691
5692none:
5693 /* re-enable interrupts here since we don't have anything to service. */
93fd74e3 5694 /* only Re-enable if disabled by irq */
a6766ccd 5695 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b
SG		 5696 il_enable_interrupts(il);
5697 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5698 return IRQ_NONE;
5699}
e2ebc833 5700EXPORT_SYMBOL(il_isr);
be663ab6
WYG		 5701
5702/*
e2ebc833 5703 * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
be663ab6
WYG		 5704 * function.
5705 */
e7392364
SG		 5706void
5707il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1722f8e1 5708 __le16 fc, __le32 *tx_flags)
be663ab6
WYG		 5709{
5710 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
5711 *tx_flags |= TX_CMD_FLG_RTS_MSK;
5712 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
5713 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5714
5715 if (!ieee80211_is_mgmt(fc))
5716 return;
5717
5718 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
5719 case cpu_to_le16(IEEE80211_STYPE_AUTH):
5720 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
5721 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
5722 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
5723 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5724 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5725 break;
5726 }
e7392364
SG		 5727 } else if (info->control.rates[0].
5728 flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
be663ab6
WYG		 5729 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5730 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5731 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5732 }
5733}
e2ebc833 5734EXPORT_SYMBOL(il_tx_cmd_protection);
Linux kernel - Deliverables
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