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iwlegacy: use writeb,writel,readl directly
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / common.c
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/etherdevice.h>
32#include <linux/sched.h>
33#include <linux/slab.h>
0cdc2136
SG		 34#include <linux/types.h>
35#include <linux/lockdep.h>
36#include <linux/init.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/skbuff.h>
be663ab6
WYG		 41#include <net/mac80211.h>
42
98613be0 43#include "common.h"
be663ab6 44
17d4eca6
SG		 45int
46_il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout)
47{
48 const int interval = 10; /* microseconds */
49 int t = 0;
50
51 do {
52 if ((_il_rd(il, addr) & mask) == (bits & mask))
53 return t;
54 udelay(interval);
55 t += interval;
56 } while (t < timeout);
57
58 return -ETIMEDOUT;
59}
60EXPORT_SYMBOL(_il_poll_bit);
61
62void
63il_set_bit(struct il_priv *p, u32 r, u32 m)
64{
65 unsigned long reg_flags;
66
67 spin_lock_irqsave(&p->reg_lock, reg_flags);
68 _il_set_bit(p, r, m);
69 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
70}
71EXPORT_SYMBOL(il_set_bit);
72
73void
74il_clear_bit(struct il_priv *p, u32 r, u32 m)
75{
76 unsigned long reg_flags;
77
78 spin_lock_irqsave(&p->reg_lock, reg_flags);
79 _il_clear_bit(p, r, m);
80 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
81}
82EXPORT_SYMBOL(il_clear_bit);
83
1e0f32a4 84bool
17d4eca6
SG		 85_il_grab_nic_access(struct il_priv *il)
86{
87 int ret;
88 u32 val;
89
90 /* this bit wakes up the NIC */
91 _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
92
93 /*
94 * These bits say the device is running, and should keep running for
95 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
96 * but they do not indicate that embedded SRAM is restored yet;
97 * 3945 and 4965 have volatile SRAM, and must save/restore contents
98 * to/from host DRAM when sleeping/waking for power-saving.
99 * Each direction takes approximately 1/4 millisecond; with this
100 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
101 * series of register accesses are expected (e.g. reading Event Log),
102 * to keep device from sleeping.
103 *
104 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
105 * SRAM is okay/restored. We don't check that here because this call
106 * is just for hardware register access; but GP1 MAC_SLEEP check is a
107 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
108 *
109 */
110 ret =
111 _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
112 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
113 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
b6603036 114 if (unlikely(ret < 0)) {
17d4eca6 115 val = _il_rd(il, CSR_GP_CNTRL);
b6603036
SG		 116 WARN_ONCE(1, "Timeout waiting for ucode processor access "
117 "(CSR_GP_CNTRL 0x%08x)\n", val);
17d4eca6 118 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1e0f32a4 119 return false;
17d4eca6
SG		 120 }
121
1e0f32a4 122 return true;
17d4eca6
SG		 123}
124EXPORT_SYMBOL_GPL(_il_grab_nic_access);
125
126int
127il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout)
128{
129 const int interval = 10; /* microseconds */
130 int t = 0;
131
132 do {
133 if ((il_rd(il, addr) & mask) == mask)
134 return t;
135 udelay(interval);
136 t += interval;
137 } while (t < timeout);
138
139 return -ETIMEDOUT;
140}
141EXPORT_SYMBOL(il_poll_bit);
142
143u32
144il_rd_prph(struct il_priv *il, u32 reg)
145{
146 unsigned long reg_flags;
147 u32 val;
148
149 spin_lock_irqsave(&il->reg_lock, reg_flags);
150 _il_grab_nic_access(il);
151 val = _il_rd_prph(il, reg);
152 _il_release_nic_access(il);
153 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
154 return val;
155}
156EXPORT_SYMBOL(il_rd_prph);
157
158void
159il_wr_prph(struct il_priv *il, u32 addr, u32 val)
160{
161 unsigned long reg_flags;
162
163 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4 164 if (likely(_il_grab_nic_access(il))) {
17d4eca6
SG		 165 _il_wr_prph(il, addr, val);
166 _il_release_nic_access(il);
167 }
168 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
169}
170EXPORT_SYMBOL(il_wr_prph);
171
172u32
173il_read_targ_mem(struct il_priv *il, u32 addr)
174{
175 unsigned long reg_flags;
176 u32 value;
177
178 spin_lock_irqsave(&il->reg_lock, reg_flags);
179 _il_grab_nic_access(il);
180
181 _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
17d4eca6
SG		 182 value = _il_rd(il, HBUS_TARG_MEM_RDAT);
183
184 _il_release_nic_access(il);
185 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
186 return value;
187}
188EXPORT_SYMBOL(il_read_targ_mem);
189
190void
191il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
192{
193 unsigned long reg_flags;
194
195 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4 196 if (likely(_il_grab_nic_access(il))) {
17d4eca6 197 _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
17d4eca6
SG		 198 _il_wr(il, HBUS_TARG_MEM_WDAT, val);
199 _il_release_nic_access(il);
200 }
201 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
202}
203EXPORT_SYMBOL(il_write_targ_mem);
204
e7392364
SG		 205const char *
206il_get_cmd_string(u8 cmd)
0cdc2136
SG		 207{
208 switch (cmd) {
209 IL_CMD(N_ALIVE);
210 IL_CMD(N_ERROR);
211 IL_CMD(C_RXON);
212 IL_CMD(C_RXON_ASSOC);
213 IL_CMD(C_QOS_PARAM);
214 IL_CMD(C_RXON_TIMING);
215 IL_CMD(C_ADD_STA);
216 IL_CMD(C_REM_STA);
217 IL_CMD(C_WEPKEY);
218 IL_CMD(N_3945_RX);
219 IL_CMD(C_TX);
220 IL_CMD(C_RATE_SCALE);
221 IL_CMD(C_LEDS);
222 IL_CMD(C_TX_LINK_QUALITY_CMD);
223 IL_CMD(C_CHANNEL_SWITCH);
224 IL_CMD(N_CHANNEL_SWITCH);
225 IL_CMD(C_SPECTRUM_MEASUREMENT);
226 IL_CMD(N_SPECTRUM_MEASUREMENT);
227 IL_CMD(C_POWER_TBL);
228 IL_CMD(N_PM_SLEEP);
229 IL_CMD(N_PM_DEBUG_STATS);
230 IL_CMD(C_SCAN);
231 IL_CMD(C_SCAN_ABORT);
232 IL_CMD(N_SCAN_START);
233 IL_CMD(N_SCAN_RESULTS);
234 IL_CMD(N_SCAN_COMPLETE);
235 IL_CMD(N_BEACON);
236 IL_CMD(C_TX_BEACON);
237 IL_CMD(C_TX_PWR_TBL);
238 IL_CMD(C_BT_CONFIG);
239 IL_CMD(C_STATS);
240 IL_CMD(N_STATS);
241 IL_CMD(N_CARD_STATE);
242 IL_CMD(N_MISSED_BEACONS);
243 IL_CMD(C_CT_KILL_CONFIG);
244 IL_CMD(C_SENSITIVITY);
245 IL_CMD(C_PHY_CALIBRATION);
246 IL_CMD(N_RX_PHY);
247 IL_CMD(N_RX_MPDU);
248 IL_CMD(N_RX);
249 IL_CMD(N_COMPRESSED_BA);
250 default:
251 return "UNKNOWN";
252
253 }
254}
255EXPORT_SYMBOL(il_get_cmd_string);
256
257#define HOST_COMPLETE_TIMEOUT (HZ / 2)
258
e7392364
SG		 259static void
260il_generic_cmd_callback(struct il_priv *il, struct il_device_cmd *cmd,
261 struct il_rx_pkt *pkt)
0cdc2136
SG		 262{
263 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
264 IL_ERR("Bad return from %s (0x%08X)\n",
e7392364 265 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
0cdc2136
SG		 266 return;
267 }
0cdc2136
SG		 268#ifdef CONFIG_IWLEGACY_DEBUG
269 switch (cmd->hdr.cmd) {
270 case C_TX_LINK_QUALITY_CMD:
271 case C_SENSITIVITY:
272 D_HC_DUMP("back from %s (0x%08X)\n",
e7392364 273 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
0cdc2136
SG		 274 break;
275 default:
e7392364
SG		 276 D_HC("back from %s (0x%08X)\n", il_get_cmd_string(cmd->hdr.cmd),
277 pkt->hdr.flags);
0cdc2136
SG		 278 }
279#endif
280}
281
282static int
283il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd)
284{
285 int ret;
286
287 BUG_ON(!(cmd->flags & CMD_ASYNC));
288
289 /* An asynchronous command can not expect an SKB to be set. */
290 BUG_ON(cmd->flags & CMD_WANT_SKB);
291
292 /* Assign a generic callback if one is not provided */
293 if (!cmd->callback)
294 cmd->callback = il_generic_cmd_callback;
295
296 if (test_bit(S_EXIT_PENDING, &il->status))
297 return -EBUSY;
298
299 ret = il_enqueue_hcmd(il, cmd);
300 if (ret < 0) {
301 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
e7392364 302 il_get_cmd_string(cmd->id), ret);
0cdc2136
SG		 303 return ret;
304 }
305 return 0;
306}
307
e7392364
SG		 308int
309il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG		 310{
311 int cmd_idx;
312 int ret;
313
314 lockdep_assert_held(&il->mutex);
315
316 BUG_ON(cmd->flags & CMD_ASYNC);
317
e7392364 318 /* A synchronous command can not have a callback set. */
0cdc2136
SG		 319 BUG_ON(cmd->callback);
320
321 D_INFO("Attempting to send sync command %s\n",
e7392364 322 il_get_cmd_string(cmd->id));
0cdc2136
SG		 323
324 set_bit(S_HCMD_ACTIVE, &il->status);
325 D_INFO("Setting HCMD_ACTIVE for command %s\n",
e7392364 326 il_get_cmd_string(cmd->id));
0cdc2136
SG		 327
328 cmd_idx = il_enqueue_hcmd(il, cmd);
329 if (cmd_idx < 0) {
330 ret = cmd_idx;
331 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
e7392364 332 il_get_cmd_string(cmd->id), ret);
0cdc2136
SG		 333 goto out;
334 }
335
336 ret = wait_event_timeout(il->wait_command_queue,
e7392364
SG		 337 !test_bit(S_HCMD_ACTIVE, &il->status),
338 HOST_COMPLETE_TIMEOUT);
0cdc2136
SG		 339 if (!ret) {
340 if (test_bit(S_HCMD_ACTIVE, &il->status)) {
e7392364
SG		 341 IL_ERR("Error sending %s: time out after %dms.\n",
342 il_get_cmd_string(cmd->id),
343 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
0cdc2136
SG		 344
345 clear_bit(S_HCMD_ACTIVE, &il->status);
e7392364
SG		 346 D_INFO("Clearing HCMD_ACTIVE for command %s\n",
347 il_get_cmd_string(cmd->id));
0cdc2136
SG		 348 ret = -ETIMEDOUT;
349 goto cancel;
350 }
351 }
352
353 if (test_bit(S_RF_KILL_HW, &il->status)) {
354 IL_ERR("Command %s aborted: RF KILL Switch\n",
e7392364 355 il_get_cmd_string(cmd->id));
0cdc2136
SG		 356 ret = -ECANCELED;
357 goto fail;
358 }
359 if (test_bit(S_FW_ERROR, &il->status)) {
360 IL_ERR("Command %s failed: FW Error\n",
e7392364 361 il_get_cmd_string(cmd->id));
0cdc2136
SG		 362 ret = -EIO;
363 goto fail;
364 }
365 if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
366 IL_ERR("Error: Response NULL in '%s'\n",
e7392364 367 il_get_cmd_string(cmd->id));
0cdc2136
SG		 368 ret = -EIO;
369 goto cancel;
370 }
371
372 ret = 0;
373 goto out;
374
375cancel:
376 if (cmd->flags & CMD_WANT_SKB) {
377 /*
378 * Cancel the CMD_WANT_SKB flag for the cmd in the
379 * TX cmd queue. Otherwise in case the cmd comes
380 * in later, it will possibly set an invalid
381 * address (cmd->meta.source).
382 */
e7392364 383 il->txq[il->cmd_queue].meta[cmd_idx].flags &= ~CMD_WANT_SKB;
0cdc2136
SG		 384 }
385fail:
386 if (cmd->reply_page) {
387 il_free_pages(il, cmd->reply_page);
388 cmd->reply_page = 0;
389 }
390out:
391 return ret;
392}
393EXPORT_SYMBOL(il_send_cmd_sync);
394
e7392364
SG		 395int
396il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG		 397{
398 if (cmd->flags & CMD_ASYNC)
399 return il_send_cmd_async(il, cmd);
400
401 return il_send_cmd_sync(il, cmd);
402}
403EXPORT_SYMBOL(il_send_cmd);
404
405int
406il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data)
407{
408 struct il_host_cmd cmd = {
409 .id = id,
410 .len = len,
411 .data = data,
412 };
413
414 return il_send_cmd_sync(il, &cmd);
415}
416EXPORT_SYMBOL(il_send_cmd_pdu);
417
e7392364
SG		 418int
419il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1722f8e1
SG		 420 void (*callback) (struct il_priv *il,
421 struct il_device_cmd *cmd,
422 struct il_rx_pkt *pkt))
0cdc2136
SG		 423{
424 struct il_host_cmd cmd = {
425 .id = id,
426 .len = len,
427 .data = data,
428 };
429
430 cmd.flags |= CMD_ASYNC;
431 cmd.callback = callback;
432
433 return il_send_cmd_async(il, &cmd);
434}
435EXPORT_SYMBOL(il_send_cmd_pdu_async);
436
437/* default: IL_LED_BLINK(0) using blinking idx table */
438static int led_mode;
439module_param(led_mode, int, S_IRUGO);
e7392364
SG		 440MODULE_PARM_DESC(led_mode,
441 "0=system default, " "1=On(RF On)/Off(RF Off), 2=blinking");
0cdc2136
SG		 442
443/* Throughput OFF time(ms) ON time (ms)
444 * >300 25 25
445 * >200 to 300 40 40
446 * >100 to 200 55 55
447 * >70 to 100 65 65
448 * >50 to 70 75 75
449 * >20 to 50 85 85
450 * >10 to 20 95 95
451 * >5 to 10 110 110
452 * >1 to 5 130 130
453 * >0 to 1 167 167
454 * <=0 SOLID ON
455 */
456static const struct ieee80211_tpt_blink il_blink[] = {
1722f8e1
SG		 457 {.throughput = 0, .blink_time = 334},
458 {.throughput = 1 * 1024 - 1, .blink_time = 260},
459 {.throughput = 5 * 1024 - 1, .blink_time = 220},
460 {.throughput = 10 * 1024 - 1, .blink_time = 190},
461 {.throughput = 20 * 1024 - 1, .blink_time = 170},
462 {.throughput = 50 * 1024 - 1, .blink_time = 150},
463 {.throughput = 70 * 1024 - 1, .blink_time = 130},
464 {.throughput = 100 * 1024 - 1, .blink_time = 110},
465 {.throughput = 200 * 1024 - 1, .blink_time = 80},
466 {.throughput = 300 * 1024 - 1, .blink_time = 50},
0cdc2136
SG		 467};
468
469/*
470 * Adjust led blink rate to compensate on a MAC Clock difference on every HW
471 * Led blink rate analysis showed an average deviation of 0% on 3945,
472 * 5% on 4965 HW.
473 * Need to compensate on the led on/off time per HW according to the deviation
474 * to achieve the desired led frequency
475 * The calculation is: (100-averageDeviation)/100 * blinkTime
476 * For code efficiency the calculation will be:
477 * compensation = (100 - averageDeviation) * 64 / 100
478 * NewBlinkTime = (compensation * BlinkTime) / 64
479 */
e7392364
SG		 480static inline u8
481il_blink_compensation(struct il_priv *il, u8 time, u16 compensation)
0cdc2136
SG		 482{
483 if (!compensation) {
484 IL_ERR("undefined blink compensation: "
e7392364 485 "use pre-defined blinking time\n");
0cdc2136
SG		 486 return time;
487 }
488
e7392364 489 return (u8) ((time * compensation) >> 6);
0cdc2136
SG		 490}
491
492/* Set led pattern command */
e7392364
SG		 493static int
494il_led_cmd(struct il_priv *il, unsigned long on, unsigned long off)
0cdc2136
SG		 495{
496 struct il_led_cmd led_cmd = {
497 .id = IL_LED_LINK,
498 .interval = IL_DEF_LED_INTRVL
499 };
500 int ret;
501
502 if (!test_bit(S_READY, &il->status))
503 return -EBUSY;
504
505 if (il->blink_on == on && il->blink_off == off)
506 return 0;
507
508 if (off == 0) {
509 /* led is SOLID_ON */
510 on = IL_LED_SOLID;
511 }
512
513 D_LED("Led blink time compensation=%u\n",
89ef1ed2 514 il->cfg->led_compensation);
e7392364
SG		 515 led_cmd.on =
516 il_blink_compensation(il, on,
89ef1ed2 517 il->cfg->led_compensation);
e7392364
SG		 518 led_cmd.off =
519 il_blink_compensation(il, off,
89ef1ed2 520 il->cfg->led_compensation);
0cdc2136 521
c39ae9fd 522 ret = il->ops->led->cmd(il, &led_cmd);
0cdc2136
SG		 523 if (!ret) {
524 il->blink_on = on;
525 il->blink_off = off;
526 }
527 return ret;
528}
529
e7392364
SG		 530static void
531il_led_brightness_set(struct led_classdev *led_cdev,
532 enum led_brightness brightness)
0cdc2136
SG		 533{
534 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
535 unsigned long on = 0;
536
537 if (brightness > 0)
538 on = IL_LED_SOLID;
539
540 il_led_cmd(il, on, 0);
541}
542
e7392364
SG		 543static int
544il_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on,
545 unsigned long *delay_off)
0cdc2136
SG		 546{
547 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
548
549 return il_led_cmd(il, *delay_on, *delay_off);
550}
551
e7392364
SG		 552void
553il_leds_init(struct il_priv *il)
0cdc2136
SG		 554{
555 int mode = led_mode;
556 int ret;
557
558 if (mode == IL_LED_DEFAULT)
559 mode = il->cfg->led_mode;
560
e7392364
SG		 561 il->led.name =
562 kasprintf(GFP_KERNEL, "%s-led", wiphy_name(il->hw->wiphy));
0cdc2136
SG		 563 il->led.brightness_set = il_led_brightness_set;
564 il->led.blink_set = il_led_blink_set;
565 il->led.max_brightness = 1;
566
567 switch (mode) {
568 case IL_LED_DEFAULT:
569 WARN_ON(1);
570 break;
571 case IL_LED_BLINK:
572 il->led.default_trigger =
e7392364
SG		 573 ieee80211_create_tpt_led_trigger(il->hw,
574 IEEE80211_TPT_LEDTRIG_FL_CONNECTED,
575 il_blink,
576 ARRAY_SIZE(il_blink));
0cdc2136
SG		 577 break;
578 case IL_LED_RF_STATE:
e7392364 579 il->led.default_trigger = ieee80211_get_radio_led_name(il->hw);
0cdc2136
SG		 580 break;
581 }
582
583 ret = led_classdev_register(&il->pci_dev->dev, &il->led);
584 if (ret) {
585 kfree(il->led.name);
586 return;
587 }
588
589 il->led_registered = true;
590}
591EXPORT_SYMBOL(il_leds_init);
592
e7392364
SG		 593void
594il_leds_exit(struct il_priv *il)
0cdc2136
SG		 595{
596 if (!il->led_registered)
597 return;
598
599 led_classdev_unregister(&il->led);
600 kfree(il->led.name);
601}
602EXPORT_SYMBOL(il_leds_exit);
603
604/************************** EEPROM BANDS ****************************
605 *
606 * The il_eeprom_band definitions below provide the mapping from the
607 * EEPROM contents to the specific channel number supported for each
608 * band.
609 *
610 * For example, il_priv->eeprom.band_3_channels[4] from the band_3
611 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
612 * The specific geography and calibration information for that channel
613 * is contained in the eeprom map itself.
614 *
615 * During init, we copy the eeprom information and channel map
616 * information into il->channel_info_24/52 and il->channel_map_24/52
617 *
618 * channel_map_24/52 provides the idx in the channel_info array for a
619 * given channel. We have to have two separate maps as there is channel
620 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
621 * band_2
622 *
623 * A value of 0xff stored in the channel_map indicates that the channel
624 * is not supported by the hardware at all.
625 *
626 * A value of 0xfe in the channel_map indicates that the channel is not
627 * valid for Tx with the current hardware. This means that
628 * while the system can tune and receive on a given channel, it may not
629 * be able to associate or transmit any frames on that
630 * channel. There is no corresponding channel information for that
631 * entry.
632 *
633 *********************************************************************/
634
635/* 2.4 GHz */
636const u8 il_eeprom_band_1[14] = {
637 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
638};
639
640/* 5.2 GHz bands */
641static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */
642 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
643};
644
645static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */
646 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
647};
648
649static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */
650 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
651};
652
653static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */
654 145, 149, 153, 157, 161, 165
655};
656
e7392364 657static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */
0cdc2136
SG		 658 1, 2, 3, 4, 5, 6, 7
659};
660
e7392364 661static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */
0cdc2136
SG		 662 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
663};
664
665/******************************************************************************
666 *
667 * EEPROM related functions
668 *
669******************************************************************************/
670
e7392364
SG		 671static int
672il_eeprom_verify_signature(struct il_priv *il)
0cdc2136
SG		 673{
674 u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
675 int ret = 0;
676
677 D_EEPROM("EEPROM signature=0x%08x\n", gp);
678 switch (gp) {
679 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
680 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
681 break;
682 default:
e7392364 683 IL_ERR("bad EEPROM signature," "EEPROM_GP=0x%08x\n", gp);
0cdc2136
SG		 684 ret = -ENOENT;
685 break;
686 }
687 return ret;
688}
689
e7392364
SG		 690const u8 *
691il_eeprom_query_addr(const struct il_priv *il, size_t offset)
0cdc2136 692{
89ef1ed2 693 BUG_ON(offset >= il->cfg->eeprom_size);
0cdc2136
SG		 694 return &il->eeprom[offset];
695}
696EXPORT_SYMBOL(il_eeprom_query_addr);
697
e7392364 698u16
1722f8e1 699il_eeprom_query16(const struct il_priv *il, size_t offset)
0cdc2136
SG		 700{
701 if (!il->eeprom)
702 return 0;
e7392364 703 return (u16) il->eeprom[offset] | ((u16) il->eeprom[offset + 1] << 8);
0cdc2136
SG		 704}
705EXPORT_SYMBOL(il_eeprom_query16);
706
707/**
708 * il_eeprom_init - read EEPROM contents
709 *
710 * Load the EEPROM contents from adapter into il->eeprom
711 *
712 * NOTE: This routine uses the non-debug IO access functions.
713 */
e7392364
SG		 714int
715il_eeprom_init(struct il_priv *il)
0cdc2136
SG		 716{
717 __le16 *e;
718 u32 gp = _il_rd(il, CSR_EEPROM_GP);
719 int sz;
720 int ret;
721 u16 addr;
722
723 /* allocate eeprom */
89ef1ed2 724 sz = il->cfg->eeprom_size;
0cdc2136
SG		 725 D_EEPROM("NVM size = %d\n", sz);
726 il->eeprom = kzalloc(sz, GFP_KERNEL);
727 if (!il->eeprom) {
728 ret = -ENOMEM;
729 goto alloc_err;
730 }
e7392364 731 e = (__le16 *) il->eeprom;
0cdc2136 732
c39ae9fd 733 il->ops->lib->apm_ops.init(il);
0cdc2136
SG		 734
735 ret = il_eeprom_verify_signature(il);
736 if (ret < 0) {
737 IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
738 ret = -ENOENT;
739 goto err;
740 }
741
742 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
c39ae9fd 743 ret = il->ops->lib->eeprom_ops.acquire_semaphore(il);
0cdc2136
SG		 744 if (ret < 0) {
745 IL_ERR("Failed to acquire EEPROM semaphore.\n");
746 ret = -ENOENT;
747 goto err;
748 }
749
750 /* eeprom is an array of 16bit values */
751 for (addr = 0; addr < sz; addr += sizeof(u16)) {
752 u32 r;
753
754 _il_wr(il, CSR_EEPROM_REG,
e7392364 755 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
0cdc2136 756
e7392364
SG		 757 ret =
758 _il_poll_bit(il, CSR_EEPROM_REG,
759 CSR_EEPROM_REG_READ_VALID_MSK,
760 CSR_EEPROM_REG_READ_VALID_MSK,
761 IL_EEPROM_ACCESS_TIMEOUT);
0cdc2136 762 if (ret < 0) {
e7392364 763 IL_ERR("Time out reading EEPROM[%d]\n", addr);
0cdc2136
SG		 764 goto done;
765 }
766 r = _il_rd(il, CSR_EEPROM_REG);
767 e[addr / 2] = cpu_to_le16(r >> 16);
768 }
769
e7392364
SG		 770 D_EEPROM("NVM Type: %s, version: 0x%x\n", "EEPROM",
771 il_eeprom_query16(il, EEPROM_VERSION));
0cdc2136
SG		 772
773 ret = 0;
774done:
c39ae9fd 775 il->ops->lib->eeprom_ops.release_semaphore(il);
0cdc2136
SG		 776
777err:
778 if (ret)
779 il_eeprom_free(il);
780 /* Reset chip to save power until we load uCode during "up". */
781 il_apm_stop(il);
782alloc_err:
783 return ret;
784}
785EXPORT_SYMBOL(il_eeprom_init);
786
e7392364
SG		 787void
788il_eeprom_free(struct il_priv *il)
0cdc2136
SG		 789{
790 kfree(il->eeprom);
791 il->eeprom = NULL;
792}
793EXPORT_SYMBOL(il_eeprom_free);
794
e7392364
SG		 795static void
796il_init_band_reference(const struct il_priv *il, int eep_band,
797 int *eeprom_ch_count,
798 const struct il_eeprom_channel **eeprom_ch_info,
1722f8e1 799 const u8 **eeprom_ch_idx)
0cdc2136 800{
e7392364 801 u32 offset =
c39ae9fd 802 il->ops->lib->eeprom_ops.regulatory_bands[eep_band - 1];
0cdc2136
SG		 803 switch (eep_band) {
804 case 1: /* 2.4GHz band */
805 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1);
e7392364
SG		 806 *eeprom_ch_info =
807 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
808 offset);
0cdc2136
SG		 809 *eeprom_ch_idx = il_eeprom_band_1;
810 break;
811 case 2: /* 4.9GHz band */
812 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2);
e7392364
SG		 813 *eeprom_ch_info =
814 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
815 offset);
0cdc2136
SG		 816 *eeprom_ch_idx = il_eeprom_band_2;
817 break;
818 case 3: /* 5.2GHz band */
819 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3);
e7392364
SG		 820 *eeprom_ch_info =
821 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
822 offset);
0cdc2136
SG		 823 *eeprom_ch_idx = il_eeprom_band_3;
824 break;
825 case 4: /* 5.5GHz band */
826 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4);
e7392364
SG		 827 *eeprom_ch_info =
828 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
829 offset);
0cdc2136
SG		 830 *eeprom_ch_idx = il_eeprom_band_4;
831 break;
832 case 5: /* 5.7GHz band */
833 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5);
e7392364
SG		 834 *eeprom_ch_info =
835 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
836 offset);
0cdc2136
SG		 837 *eeprom_ch_idx = il_eeprom_band_5;
838 break;
839 case 6: /* 2.4GHz ht40 channels */
840 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6);
e7392364
SG		 841 *eeprom_ch_info =
842 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
843 offset);
0cdc2136
SG		 844 *eeprom_ch_idx = il_eeprom_band_6;
845 break;
846 case 7: /* 5 GHz ht40 channels */
847 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7);
e7392364
SG		 848 *eeprom_ch_info =
849 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
850 offset);
0cdc2136
SG		 851 *eeprom_ch_idx = il_eeprom_band_7;
852 break;
853 default:
854 BUG();
855 }
856}
857
858#define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
859 ? # x " " : "")
860/**
861 * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il.
862 *
863 * Does not set up a command, or touch hardware.
864 */
e7392364
SG		 865static int
866il_mod_ht40_chan_info(struct il_priv *il, enum ieee80211_band band, u16 channel,
867 const struct il_eeprom_channel *eeprom_ch,
868 u8 clear_ht40_extension_channel)
0cdc2136
SG		 869{
870 struct il_channel_info *ch_info;
871
e7392364
SG		 872 ch_info =
873 (struct il_channel_info *)il_get_channel_info(il, band, channel);
0cdc2136
SG		 874
875 if (!il_is_channel_valid(ch_info))
876 return -1;
877
878 D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
e7392364
SG		 879 " Ad-Hoc %ssupported\n", ch_info->channel,
880 il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
881 CHECK_AND_PRINT(IBSS), CHECK_AND_PRINT(ACTIVE),
882 CHECK_AND_PRINT(RADAR), CHECK_AND_PRINT(WIDE),
883 CHECK_AND_PRINT(DFS), eeprom_ch->flags,
884 eeprom_ch->max_power_avg,
885 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) &&
886 !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" : "not ");
0cdc2136
SG		 887
888 ch_info->ht40_eeprom = *eeprom_ch;
889 ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
890 ch_info->ht40_flags = eeprom_ch->flags;
891 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
892 ch_info->ht40_extension_channel &=
e7392364 893 ~clear_ht40_extension_channel;
0cdc2136
SG		 894
895 return 0;
896}
897
898#define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
899 ? # x " " : "")
900
901/**
902 * il_init_channel_map - Set up driver's info for all possible channels
903 */
e7392364
SG		 904int
905il_init_channel_map(struct il_priv *il)
0cdc2136
SG		 906{
907 int eeprom_ch_count = 0;
908 const u8 *eeprom_ch_idx = NULL;
909 const struct il_eeprom_channel *eeprom_ch_info = NULL;
910 int band, ch;
911 struct il_channel_info *ch_info;
912
913 if (il->channel_count) {
914 D_EEPROM("Channel map already initialized.\n");
915 return 0;
916 }
917
918 D_EEPROM("Initializing regulatory info from EEPROM\n");
919
920 il->channel_count =
e7392364
SG		 921 ARRAY_SIZE(il_eeprom_band_1) + ARRAY_SIZE(il_eeprom_band_2) +
922 ARRAY_SIZE(il_eeprom_band_3) + ARRAY_SIZE(il_eeprom_band_4) +
0cdc2136
SG		 923 ARRAY_SIZE(il_eeprom_band_5);
924
e7392364 925 D_EEPROM("Parsing data for %d channels.\n", il->channel_count);
0cdc2136 926
e7392364
SG		 927 il->channel_info =
928 kzalloc(sizeof(struct il_channel_info) * il->channel_count,
929 GFP_KERNEL);
0cdc2136
SG		 930 if (!il->channel_info) {
931 IL_ERR("Could not allocate channel_info\n");
932 il->channel_count = 0;
933 return -ENOMEM;
934 }
935
936 ch_info = il->channel_info;
937
938 /* Loop through the 5 EEPROM bands adding them in order to the
939 * channel map we maintain (that contains additional information than
940 * what just in the EEPROM) */
941 for (band = 1; band <= 5; band++) {
942
943 il_init_band_reference(il, band, &eeprom_ch_count,
e7392364 944 &eeprom_ch_info, &eeprom_ch_idx);
0cdc2136
SG		 945
946 /* Loop through each band adding each of the channels */
947 for (ch = 0; ch < eeprom_ch_count; ch++) {
948 ch_info->channel = eeprom_ch_idx[ch];
e7392364
SG		 949 ch_info->band =
950 (band ==
951 1) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
0cdc2136
SG		 952
953 /* permanently store EEPROM's channel regulatory flags
954 * and max power in channel info database. */
955 ch_info->eeprom = eeprom_ch_info[ch];
956
957 /* Copy the run-time flags so they are there even on
958 * invalid channels */
959 ch_info->flags = eeprom_ch_info[ch].flags;
960 /* First write that ht40 is not enabled, and then enable
961 * one by one */
962 ch_info->ht40_extension_channel =
e7392364 963 IEEE80211_CHAN_NO_HT40;
0cdc2136
SG		 964
965 if (!(il_is_channel_valid(ch_info))) {
e7392364
SG		 966 D_EEPROM("Ch. %d Flags %x [%sGHz] - "
967 "No traffic\n", ch_info->channel,
968 ch_info->flags,
969 il_is_channel_a_band(ch_info) ? "5.2" :
970 "2.4");
0cdc2136
SG		 971 ch_info++;
972 continue;
973 }
974
975 /* Initialize regulatory-based run-time data */
976 ch_info->max_power_avg = ch_info->curr_txpow =
977 eeprom_ch_info[ch].max_power_avg;
978 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
979 ch_info->min_power = 0;
980
e7392364
SG		 981 D_EEPROM("Ch. %d [%sGHz] " "%s%s%s%s%s%s(0x%02x %ddBm):"
982 " Ad-Hoc %ssupported\n", ch_info->channel,
983 il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
984 CHECK_AND_PRINT_I(VALID),
985 CHECK_AND_PRINT_I(IBSS),
986 CHECK_AND_PRINT_I(ACTIVE),
987 CHECK_AND_PRINT_I(RADAR),
988 CHECK_AND_PRINT_I(WIDE),
989 CHECK_AND_PRINT_I(DFS),
990 eeprom_ch_info[ch].flags,
991 eeprom_ch_info[ch].max_power_avg,
992 ((eeprom_ch_info[ch].
993 flags & EEPROM_CHANNEL_IBSS) &&
994 !(eeprom_ch_info[ch].
995 flags & EEPROM_CHANNEL_RADAR)) ? "" :
996 "not ");
0cdc2136
SG		 997
998 ch_info++;
999 }
1000 }
1001
1002 /* Check if we do have HT40 channels */
c39ae9fd 1003 if (il->ops->lib->eeprom_ops.regulatory_bands[5] ==
0cdc2136 1004 EEPROM_REGULATORY_BAND_NO_HT40 &&
c39ae9fd 1005 il->ops->lib->eeprom_ops.regulatory_bands[6] ==
0cdc2136
SG		 1006 EEPROM_REGULATORY_BAND_NO_HT40)
1007 return 0;
1008
1009 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
1010 for (band = 6; band <= 7; band++) {
1011 enum ieee80211_band ieeeband;
1012
1013 il_init_band_reference(il, band, &eeprom_ch_count,
e7392364 1014 &eeprom_ch_info, &eeprom_ch_idx);
0cdc2136
SG		 1015
1016 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
1017 ieeeband =
e7392364 1018 (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
0cdc2136
SG		 1019
1020 /* Loop through each band adding each of the channels */
1021 for (ch = 0; ch < eeprom_ch_count; ch++) {
1022 /* Set up driver's info for lower half */
e7392364
SG		 1023 il_mod_ht40_chan_info(il, ieeeband, eeprom_ch_idx[ch],
1024 &eeprom_ch_info[ch],
1025 IEEE80211_CHAN_NO_HT40PLUS);
0cdc2136
SG		 1026
1027 /* Set up driver's info for upper half */
1028 il_mod_ht40_chan_info(il, ieeeband,
e7392364
SG		 1029 eeprom_ch_idx[ch] + 4,
1030 &eeprom_ch_info[ch],
1031 IEEE80211_CHAN_NO_HT40MINUS);
0cdc2136
SG		 1032 }
1033 }
1034
1035 return 0;
1036}
1037EXPORT_SYMBOL(il_init_channel_map);
1038
1039/*
1040 * il_free_channel_map - undo allocations in il_init_channel_map
1041 */
e7392364
SG		 1042void
1043il_free_channel_map(struct il_priv *il)
0cdc2136
SG		 1044{
1045 kfree(il->channel_info);
1046 il->channel_count = 0;
1047}
1048EXPORT_SYMBOL(il_free_channel_map);
1049
1050/**
1051 * il_get_channel_info - Find driver's ilate channel info
1052 *
1053 * Based on band and channel number.
1054 */
e7392364
SG		 1055const struct il_channel_info *
1056il_get_channel_info(const struct il_priv *il, enum ieee80211_band band,
1057 u16 channel)
0cdc2136
SG		 1058{
1059 int i;
1060
1061 switch (band) {
1062 case IEEE80211_BAND_5GHZ:
1063 for (i = 14; i < il->channel_count; i++) {
1064 if (il->channel_info[i].channel == channel)
1065 return &il->channel_info[i];
1066 }
1067 break;
1068 case IEEE80211_BAND_2GHZ:
1069 if (channel >= 1 && channel <= 14)
1070 return &il->channel_info[channel - 1];
1071 break;
1072 default:
1073 BUG();
1074 }
1075
1076 return NULL;
1077}
1078EXPORT_SYMBOL(il_get_channel_info);
1079
1080/*
1081 * Setting power level allows the card to go to sleep when not busy.
1082 *
1083 * We calculate a sleep command based on the required latency, which
1084 * we get from mac80211. In order to handle thermal throttling, we can
1085 * also use pre-defined power levels.
1086 */
1087
1088/*
1089 * This defines the old power levels. They are still used by default
1090 * (level 1) and for thermal throttle (levels 3 through 5)
1091 */
1092
1093struct il_power_vec_entry {
1094 struct il_powertable_cmd cmd;
e7392364 1095 u8 no_dtim; /* number of skip dtim */
0cdc2136
SG		 1096};
1097
e7392364
SG		 1098static void
1099il_power_sleep_cam_cmd(struct il_priv *il, struct il_powertable_cmd *cmd)
0cdc2136
SG		 1100{
1101 memset(cmd, 0, sizeof(*cmd));
1102
1103 if (il->power_data.pci_pm)
1104 cmd->flags |= IL_POWER_PCI_PM_MSK;
1105
1106 D_POWER("Sleep command for CAM\n");
1107}
1108
1109static int
1110il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd)
1111{
1112 D_POWER("Sending power/sleep command\n");
1113 D_POWER("Flags value = 0x%08X\n", cmd->flags);
e7392364
SG		 1114 D_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1115 D_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1116 D_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1117 le32_to_cpu(cmd->sleep_interval[0]),
1118 le32_to_cpu(cmd->sleep_interval[1]),
1119 le32_to_cpu(cmd->sleep_interval[2]),
1120 le32_to_cpu(cmd->sleep_interval[3]),
1121 le32_to_cpu(cmd->sleep_interval[4]));
0cdc2136
SG		 1122
1123 return il_send_cmd_pdu(il, C_POWER_TBL,
e7392364 1124 sizeof(struct il_powertable_cmd), cmd);
0cdc2136
SG		 1125}
1126
1127int
e7392364 1128il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd, bool force)
0cdc2136
SG		 1129{
1130 int ret;
1131 bool update_chains;
1132
1133 lockdep_assert_held(&il->mutex);
1134
1135 /* Don't update the RX chain when chain noise calibration is running */
1136 update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE ||
e7392364 1137 il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE;
0cdc2136
SG		 1138
1139 if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
1140 return 0;
1141
1142 if (!il_is_ready_rf(il))
1143 return -EIO;
1144
1145 /* scan complete use sleep_power_next, need to be updated */
1146 memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
1147 if (test_bit(S_SCANNING, &il->status) && !force) {
1148 D_INFO("Defer power set mode while scanning\n");
1149 return 0;
1150 }
1151
1152 if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)
1153 set_bit(S_POWER_PMI, &il->status);
1154
1155 ret = il_set_power(il, cmd);
1156 if (!ret) {
1157 if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK))
1158 clear_bit(S_POWER_PMI, &il->status);
1159
c39ae9fd
SG		 1160 if (il->ops->lib->update_chain_flags && update_chains)
1161 il->ops->lib->update_chain_flags(il);
1162 else if (il->ops->lib->update_chain_flags)
e7392364
SG		 1163 D_POWER("Cannot update the power, chain noise "
1164 "calibration running: %d\n",
1165 il->chain_noise_data.state);
0cdc2136
SG		 1166
1167 memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd));
1168 } else
1169 IL_ERR("set power fail, ret = %d", ret);
1170
1171 return ret;
1172}
1173
e7392364
SG		 1174int
1175il_power_update_mode(struct il_priv *il, bool force)
0cdc2136
SG		 1176{
1177 struct il_powertable_cmd cmd;
1178
1179 il_power_sleep_cam_cmd(il, &cmd);
1180 return il_power_set_mode(il, &cmd, force);
1181}
1182EXPORT_SYMBOL(il_power_update_mode);
1183
1184/* initialize to default */
e7392364
SG		 1185void
1186il_power_initialize(struct il_priv *il)
0cdc2136
SG		 1187{
1188 u16 lctl = il_pcie_link_ctl(il);
1189
1190 il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
1191
1192 il->power_data.debug_sleep_level_override = -1;
1193
e7392364 1194 memset(&il->power_data.sleep_cmd, 0, sizeof(il->power_data.sleep_cmd));
0cdc2136
SG		 1195}
1196EXPORT_SYMBOL(il_power_initialize);
1197
1198/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
1199 * sending probe req. This should be set long enough to hear probe responses
1200 * from more than one AP. */
e7392364 1201#define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
0cdc2136
SG		 1202#define IL_ACTIVE_DWELL_TIME_52 (20)
1203
1204#define IL_ACTIVE_DWELL_FACTOR_24GHZ (3)
1205#define IL_ACTIVE_DWELL_FACTOR_52GHZ (2)
1206
1207/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
1208 * Must be set longer than active dwell time.
1209 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
e7392364 1210#define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
0cdc2136
SG		 1211#define IL_PASSIVE_DWELL_TIME_52 (10)
1212#define IL_PASSIVE_DWELL_BASE (100)
1213#define IL_CHANNEL_TUNE_TIME 5
1214
e7392364
SG		 1215static int
1216il_send_scan_abort(struct il_priv *il)
0cdc2136
SG		 1217{
1218 int ret;
1219 struct il_rx_pkt *pkt;
1220 struct il_host_cmd cmd = {
1221 .id = C_SCAN_ABORT,
1222 .flags = CMD_WANT_SKB,
1223 };
1224
1225 /* Exit instantly with error when device is not ready
1226 * to receive scan abort command or it does not perform
1227 * hardware scan currently */
1228 if (!test_bit(S_READY, &il->status) ||
1229 !test_bit(S_GEO_CONFIGURED, &il->status) ||
1230 !test_bit(S_SCAN_HW, &il->status) ||
1231 test_bit(S_FW_ERROR, &il->status) ||
1232 test_bit(S_EXIT_PENDING, &il->status))
1233 return -EIO;
1234
1235 ret = il_send_cmd_sync(il, &cmd);
1236 if (ret)
1237 return ret;
1238
1239 pkt = (struct il_rx_pkt *)cmd.reply_page;
1240 if (pkt->u.status != CAN_ABORT_STATUS) {
1241 /* The scan abort will return 1 for success or
1242 * 2 for "failure". A failure condition can be
1243 * due to simply not being in an active scan which
1244 * can occur if we send the scan abort before we
1245 * the microcode has notified us that a scan is
1246 * completed. */
1247 D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status);
1248 ret = -EIO;
1249 }
1250
1251 il_free_pages(il, cmd.reply_page);
1252 return ret;
1253}
1254
e7392364
SG		 1255static void
1256il_complete_scan(struct il_priv *il, bool aborted)
0cdc2136
SG		 1257{
1258 /* check if scan was requested from mac80211 */
1259 if (il->scan_request) {
1260 D_SCAN("Complete scan in mac80211\n");
1261 ieee80211_scan_completed(il->hw, aborted);
1262 }
1263
1264 il->scan_vif = NULL;
1265 il->scan_request = NULL;
1266}
1267
e7392364
SG		 1268void
1269il_force_scan_end(struct il_priv *il)
0cdc2136
SG		 1270{
1271 lockdep_assert_held(&il->mutex);
1272
1273 if (!test_bit(S_SCANNING, &il->status)) {
1274 D_SCAN("Forcing scan end while not scanning\n");
1275 return;
1276 }
1277
1278 D_SCAN("Forcing scan end\n");
1279 clear_bit(S_SCANNING, &il->status);
1280 clear_bit(S_SCAN_HW, &il->status);
1281 clear_bit(S_SCAN_ABORTING, &il->status);
1282 il_complete_scan(il, true);
1283}
1284
e7392364
SG		 1285static void
1286il_do_scan_abort(struct il_priv *il)
0cdc2136
SG		 1287{
1288 int ret;
1289
1290 lockdep_assert_held(&il->mutex);
1291
1292 if (!test_bit(S_SCANNING, &il->status)) {
1293 D_SCAN("Not performing scan to abort\n");
1294 return;
1295 }
1296
1297 if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) {
1298 D_SCAN("Scan abort in progress\n");
1299 return;
1300 }
1301
1302 ret = il_send_scan_abort(il);
1303 if (ret) {
1304 D_SCAN("Send scan abort failed %d\n", ret);
1305 il_force_scan_end(il);
1306 } else
1307 D_SCAN("Successfully send scan abort\n");
1308}
1309
1310/**
1311 * il_scan_cancel - Cancel any currently executing HW scan
1312 */
e7392364
SG		 1313int
1314il_scan_cancel(struct il_priv *il)
0cdc2136
SG		 1315{
1316 D_SCAN("Queuing abort scan\n");
1317 queue_work(il->workqueue, &il->abort_scan);
1318 return 0;
1319}
1320EXPORT_SYMBOL(il_scan_cancel);
1321
1322/**
1323 * il_scan_cancel_timeout - Cancel any currently executing HW scan
1324 * @ms: amount of time to wait (in milliseconds) for scan to abort
1325 *
1326 */
e7392364
SG		 1327int
1328il_scan_cancel_timeout(struct il_priv *il, unsigned long ms)
0cdc2136
SG		 1329{
1330 unsigned long timeout = jiffies + msecs_to_jiffies(ms);
1331
1332 lockdep_assert_held(&il->mutex);
1333
1334 D_SCAN("Scan cancel timeout\n");
1335
1336 il_do_scan_abort(il);
1337
1338 while (time_before_eq(jiffies, timeout)) {
1339 if (!test_bit(S_SCAN_HW, &il->status))
1340 break;
1341 msleep(20);
1342 }
1343
1344 return test_bit(S_SCAN_HW, &il->status);
1345}
1346EXPORT_SYMBOL(il_scan_cancel_timeout);
1347
1348/* Service response to C_SCAN (0x80) */
e7392364
SG		 1349static void
1350il_hdl_scan(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1351{
1352#ifdef CONFIG_IWLEGACY_DEBUG
1353 struct il_rx_pkt *pkt = rxb_addr(rxb);
1354 struct il_scanreq_notification *notif =
1355 (struct il_scanreq_notification *)pkt->u.raw;
1356
1357 D_SCAN("Scan request status = 0x%x\n", notif->status);
1358#endif
1359}
1360
1361/* Service N_SCAN_START (0x82) */
e7392364
SG		 1362static void
1363il_hdl_scan_start(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1364{
1365 struct il_rx_pkt *pkt = rxb_addr(rxb);
1366 struct il_scanstart_notification *notif =
1367 (struct il_scanstart_notification *)pkt->u.raw;
1368 il->scan_start_tsf = le32_to_cpu(notif->tsf_low);
e7392364
SG		 1369 D_SCAN("Scan start: " "%d [802.11%s] "
1370 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", notif->channel,
1371 notif->band ? "bg" : "a", le32_to_cpu(notif->tsf_high),
1372 le32_to_cpu(notif->tsf_low), notif->status, notif->beacon_timer);
0cdc2136
SG		 1373}
1374
1375/* Service N_SCAN_RESULTS (0x83) */
e7392364
SG		 1376static void
1377il_hdl_scan_results(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1378{
1379#ifdef CONFIG_IWLEGACY_DEBUG
1380 struct il_rx_pkt *pkt = rxb_addr(rxb);
1381 struct il_scanresults_notification *notif =
1382 (struct il_scanresults_notification *)pkt->u.raw;
1383
e7392364
SG		 1384 D_SCAN("Scan ch.res: " "%d [802.11%s] " "(TSF: 0x%08X:%08X) - %d "
1385 "elapsed=%lu usec\n", notif->channel, notif->band ? "bg" : "a",
1386 le32_to_cpu(notif->tsf_high), le32_to_cpu(notif->tsf_low),
1387 le32_to_cpu(notif->stats[0]),
1388 le32_to_cpu(notif->tsf_low) - il->scan_start_tsf);
0cdc2136
SG		 1389#endif
1390}
1391
1392/* Service N_SCAN_COMPLETE (0x84) */
e7392364
SG		 1393static void
1394il_hdl_scan_complete(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1395{
1396
1397#ifdef CONFIG_IWLEGACY_DEBUG
1398 struct il_rx_pkt *pkt = rxb_addr(rxb);
1399 struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
1400#endif
1401
e7392364
SG		 1402 D_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
1403 scan_notif->scanned_channels, scan_notif->tsf_low,
1404 scan_notif->tsf_high, scan_notif->status);
0cdc2136
SG		 1405
1406 /* The HW is no longer scanning */
1407 clear_bit(S_SCAN_HW, &il->status);
1408
1409 D_SCAN("Scan on %sGHz took %dms\n",
e7392364
SG		 1410 (il->scan_band == IEEE80211_BAND_2GHZ) ? "2.4" : "5.2",
1411 jiffies_to_msecs(jiffies - il->scan_start));
0cdc2136
SG		 1412
1413 queue_work(il->workqueue, &il->scan_completed);
1414}
1415
e7392364
SG		 1416void
1417il_setup_rx_scan_handlers(struct il_priv *il)
0cdc2136
SG		 1418{
1419 /* scan handlers */
1420 il->handlers[C_SCAN] = il_hdl_scan;
e7392364
SG		 1421 il->handlers[N_SCAN_START] = il_hdl_scan_start;
1422 il->handlers[N_SCAN_RESULTS] = il_hdl_scan_results;
1423 il->handlers[N_SCAN_COMPLETE] = il_hdl_scan_complete;
0cdc2136
SG		 1424}
1425EXPORT_SYMBOL(il_setup_rx_scan_handlers);
1426
e7392364
SG		 1427inline u16
1428il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1429 u8 n_probes)
0cdc2136
SG		 1430{
1431 if (band == IEEE80211_BAND_5GHZ)
1432 return IL_ACTIVE_DWELL_TIME_52 +
e7392364 1433 IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
0cdc2136
SG		 1434 else
1435 return IL_ACTIVE_DWELL_TIME_24 +
e7392364 1436 IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
0cdc2136
SG		 1437}
1438EXPORT_SYMBOL(il_get_active_dwell_time);
1439
e7392364 1440u16
1722f8e1
SG		 1441il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1442 struct ieee80211_vif *vif)
0cdc2136 1443{
0cdc2136
SG		 1444 u16 value;
1445
e7392364
SG		 1446 u16 passive =
1447 (band ==
1448 IEEE80211_BAND_2GHZ) ? IL_PASSIVE_DWELL_BASE +
1449 IL_PASSIVE_DWELL_TIME_24 : IL_PASSIVE_DWELL_BASE +
1450 IL_PASSIVE_DWELL_TIME_52;
0cdc2136
SG		 1451
1452 if (il_is_any_associated(il)) {
1453 /*
1454 * If we're associated, we clamp the maximum passive
1455 * dwell time to be 98% of the smallest beacon interval
1456 * (minus 2 * channel tune time)
1457 */
83007196 1458 value = il->vif ? il->vif->bss_conf.beacon_int : 0;
0cdc2136
SG		 1459 if (value > IL_PASSIVE_DWELL_BASE || !value)
1460 value = IL_PASSIVE_DWELL_BASE;
1461 value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2;
1462 passive = min(value, passive);
1463 }
1464
1465 return passive;
1466}
1467EXPORT_SYMBOL(il_get_passive_dwell_time);
1468
e7392364
SG		 1469void
1470il_init_scan_params(struct il_priv *il)
0cdc2136
SG		 1471{
1472 u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1;
1473 if (!il->scan_tx_ant[IEEE80211_BAND_5GHZ])
1474 il->scan_tx_ant[IEEE80211_BAND_5GHZ] = ant_idx;
1475 if (!il->scan_tx_ant[IEEE80211_BAND_2GHZ])
1476 il->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx;
1477}
1478EXPORT_SYMBOL(il_init_scan_params);
1479
e7392364
SG		 1480static int
1481il_scan_initiate(struct il_priv *il, struct ieee80211_vif *vif)
0cdc2136
SG		 1482{
1483 int ret;
1484
1485 lockdep_assert_held(&il->mutex);
1486
c39ae9fd 1487 if (WARN_ON(!il->ops->utils->request_scan))
0cdc2136
SG		 1488 return -EOPNOTSUPP;
1489
1490 cancel_delayed_work(&il->scan_check);
1491
1492 if (!il_is_ready_rf(il)) {
1493 IL_WARN("Request scan called when driver not ready.\n");
1494 return -EIO;
1495 }
1496
1497 if (test_bit(S_SCAN_HW, &il->status)) {
e7392364 1498 D_SCAN("Multiple concurrent scan requests in parallel.\n");
0cdc2136
SG		 1499 return -EBUSY;
1500 }
1501
1502 if (test_bit(S_SCAN_ABORTING, &il->status)) {
1503 D_SCAN("Scan request while abort pending.\n");
1504 return -EBUSY;
1505 }
1506
1507 D_SCAN("Starting scan...\n");
1508
1509 set_bit(S_SCANNING, &il->status);
1510 il->scan_start = jiffies;
1511
c39ae9fd 1512 ret = il->ops->utils->request_scan(il, vif);
0cdc2136
SG		 1513 if (ret) {
1514 clear_bit(S_SCANNING, &il->status);
1515 return ret;
1516 }
1517
1518 queue_delayed_work(il->workqueue, &il->scan_check,
1519 IL_SCAN_CHECK_WATCHDOG);
1520
1521 return 0;
1522}
1523
e7392364
SG		 1524int
1525il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1526 struct cfg80211_scan_request *req)
0cdc2136
SG		 1527{
1528 struct il_priv *il = hw->priv;
1529 int ret;
1530
1531 D_MAC80211("enter\n");
1532
1533 if (req->n_channels == 0)
1534 return -EINVAL;
1535
1536 mutex_lock(&il->mutex);
1537
1538 if (test_bit(S_SCANNING, &il->status)) {
1539 D_SCAN("Scan already in progress.\n");
1540 ret = -EAGAIN;
1541 goto out_unlock;
1542 }
1543
1544 /* mac80211 will only ask for one band at a time */
1545 il->scan_request = req;
1546 il->scan_vif = vif;
1547 il->scan_band = req->channels[0]->band;
1548
1549 ret = il_scan_initiate(il, vif);
1550
1551 D_MAC80211("leave\n");
1552
1553out_unlock:
1554 mutex_unlock(&il->mutex);
1555
1556 return ret;
1557}
1558EXPORT_SYMBOL(il_mac_hw_scan);
1559
e7392364
SG		 1560static void
1561il_bg_scan_check(struct work_struct *data)
0cdc2136
SG		 1562{
1563 struct il_priv *il =
1564 container_of(data, struct il_priv, scan_check.work);
1565
1566 D_SCAN("Scan check work\n");
1567
1568 /* Since we are here firmware does not finish scan and
1569 * most likely is in bad shape, so we don't bother to
1570 * send abort command, just force scan complete to mac80211 */
1571 mutex_lock(&il->mutex);
1572 il_force_scan_end(il);
1573 mutex_unlock(&il->mutex);
1574}
1575
1576/**
1577 * il_fill_probe_req - fill in all required fields and IE for probe request
1578 */
1579
1580u16
1581il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1722f8e1 1582 const u8 *ta, const u8 *ies, int ie_len, int left)
0cdc2136
SG		 1583{
1584 int len = 0;
1585 u8 *pos = NULL;
1586
1587 /* Make sure there is enough space for the probe request,
1588 * two mandatory IEs and the data */
1589 left -= 24;
1590 if (left < 0)
1591 return 0;
1592
1593 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
1594 memcpy(frame->da, il_bcast_addr, ETH_ALEN);
1595 memcpy(frame->sa, ta, ETH_ALEN);
1596 memcpy(frame->bssid, il_bcast_addr, ETH_ALEN);
1597 frame->seq_ctrl = 0;
1598
1599 len += 24;
1600
1601 /* ...next IE... */
1602 pos = &frame->u.probe_req.variable[0];
1603
1604 /* fill in our indirect SSID IE */
1605 left -= 2;
1606 if (left < 0)
1607 return 0;
1608 *pos++ = WLAN_EID_SSID;
1609 *pos++ = 0;
1610
1611 len += 2;
1612
1613 if (WARN_ON(left < ie_len))
1614 return len;
1615
1616 if (ies && ie_len) {
1617 memcpy(pos, ies, ie_len);
1618 len += ie_len;
1619 }
1620
e7392364 1621 return (u16) len;
0cdc2136
SG		 1622}
1623EXPORT_SYMBOL(il_fill_probe_req);
1624
e7392364
SG		 1625static void
1626il_bg_abort_scan(struct work_struct *work)
0cdc2136
SG		 1627{
1628 struct il_priv *il = container_of(work, struct il_priv, abort_scan);
1629
1630 D_SCAN("Abort scan work\n");
1631
1632 /* We keep scan_check work queued in case when firmware will not
1633 * report back scan completed notification */
1634 mutex_lock(&il->mutex);
1635 il_scan_cancel_timeout(il, 200);
1636 mutex_unlock(&il->mutex);
1637}
1638
e7392364
SG		 1639static void
1640il_bg_scan_completed(struct work_struct *work)
0cdc2136 1641{
e7392364 1642 struct il_priv *il = container_of(work, struct il_priv, scan_completed);
0cdc2136
SG		 1643 bool aborted;
1644
1645 D_SCAN("Completed scan.\n");
1646
1647 cancel_delayed_work(&il->scan_check);
1648
1649 mutex_lock(&il->mutex);
1650
1651 aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status);
1652 if (aborted)
1653 D_SCAN("Aborted scan completed.\n");
1654
1655 if (!test_and_clear_bit(S_SCANNING, &il->status)) {
1656 D_SCAN("Scan already completed.\n");
1657 goto out_settings;
1658 }
1659
1660 il_complete_scan(il, aborted);
1661
1662out_settings:
1663 /* Can we still talk to firmware ? */
1664 if (!il_is_ready_rf(il))
1665 goto out;
1666
1667 /*
1668 * We do not commit power settings while scan is pending,
1669 * do it now if the settings changed.
1670 */
1671 il_power_set_mode(il, &il->power_data.sleep_cmd_next, false);
1672 il_set_tx_power(il, il->tx_power_next, false);
1673
c39ae9fd 1674 il->ops->utils->post_scan(il);
0cdc2136
SG		 1675
1676out:
1677 mutex_unlock(&il->mutex);
1678}
1679
e7392364
SG		 1680void
1681il_setup_scan_deferred_work(struct il_priv *il)
0cdc2136
SG		 1682{
1683 INIT_WORK(&il->scan_completed, il_bg_scan_completed);
1684 INIT_WORK(&il->abort_scan, il_bg_abort_scan);
1685 INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check);
1686}
1687EXPORT_SYMBOL(il_setup_scan_deferred_work);
1688
e7392364
SG		 1689void
1690il_cancel_scan_deferred_work(struct il_priv *il)
0cdc2136
SG		 1691{
1692 cancel_work_sync(&il->abort_scan);
1693 cancel_work_sync(&il->scan_completed);
1694
1695 if (cancel_delayed_work_sync(&il->scan_check)) {
1696 mutex_lock(&il->mutex);
1697 il_force_scan_end(il);
1698 mutex_unlock(&il->mutex);
1699 }
1700}
1701EXPORT_SYMBOL(il_cancel_scan_deferred_work);
1702
1703/* il->sta_lock must be held */
e7392364
SG		 1704static void
1705il_sta_ucode_activate(struct il_priv *il, u8 sta_id)
0cdc2136
SG		 1706{
1707
1708 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE))
e7392364
SG		 1709 IL_ERR("ACTIVATE a non DRIVER active station id %u addr %pM\n",
1710 sta_id, il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1711
1712 if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) {
e7392364
SG		 1713 D_ASSOC("STA id %u addr %pM already present"
1714 " in uCode (according to driver)\n", sta_id,
1715 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1716 } else {
1717 il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE;
e7392364
SG		 1718 D_ASSOC("Added STA id %u addr %pM to uCode\n", sta_id,
1719 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1720 }
1721}
1722
e7392364
SG		 1723static int
1724il_process_add_sta_resp(struct il_priv *il, struct il_addsta_cmd *addsta,
1725 struct il_rx_pkt *pkt, bool sync)
0cdc2136
SG		 1726{
1727 u8 sta_id = addsta->sta.sta_id;
1728 unsigned long flags;
1729 int ret = -EIO;
1730
1731 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
e7392364 1732 IL_ERR("Bad return from C_ADD_STA (0x%08X)\n", pkt->hdr.flags);
0cdc2136
SG		 1733 return ret;
1734 }
1735
e7392364 1736 D_INFO("Processing response for adding station %u\n", sta_id);
0cdc2136
SG		 1737
1738 spin_lock_irqsave(&il->sta_lock, flags);
1739
1740 switch (pkt->u.add_sta.status) {
1741 case ADD_STA_SUCCESS_MSK:
1742 D_INFO("C_ADD_STA PASSED\n");
1743 il_sta_ucode_activate(il, sta_id);
1744 ret = 0;
1745 break;
1746 case ADD_STA_NO_ROOM_IN_TBL:
e7392364 1747 IL_ERR("Adding station %d failed, no room in table.\n", sta_id);
0cdc2136
SG		 1748 break;
1749 case ADD_STA_NO_BLOCK_ACK_RESOURCE:
e7392364
SG		 1750 IL_ERR("Adding station %d failed, no block ack resource.\n",
1751 sta_id);
0cdc2136
SG		 1752 break;
1753 case ADD_STA_MODIFY_NON_EXIST_STA:
1754 IL_ERR("Attempting to modify non-existing station %d\n",
e7392364 1755 sta_id);
0cdc2136
SG		 1756 break;
1757 default:
e7392364 1758 D_ASSOC("Received C_ADD_STA:(0x%08X)\n", pkt->u.add_sta.status);
0cdc2136
SG		 1759 break;
1760 }
1761
1762 D_INFO("%s station id %u addr %pM\n",
e7392364
SG		 1763 il->stations[sta_id].sta.mode ==
1764 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", sta_id,
1765 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1766
1767 /*
1768 * XXX: The MAC address in the command buffer is often changed from
1769 * the original sent to the device. That is, the MAC address
1770 * written to the command buffer often is not the same MAC address
1771 * read from the command buffer when the command returns. This
1772 * issue has not yet been resolved and this debugging is left to
1773 * observe the problem.
1774 */
1775 D_INFO("%s station according to cmd buffer %pM\n",
e7392364
SG		 1776 il->stations[sta_id].sta.mode ==
1777 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", addsta->sta.addr);
0cdc2136
SG		 1778 spin_unlock_irqrestore(&il->sta_lock, flags);
1779
1780 return ret;
1781}
1782
e7392364
SG		 1783static void
1784il_add_sta_callback(struct il_priv *il, struct il_device_cmd *cmd,
1785 struct il_rx_pkt *pkt)
0cdc2136 1786{
e7392364 1787 struct il_addsta_cmd *addsta = (struct il_addsta_cmd *)cmd->cmd.payload;
0cdc2136
SG		 1788
1789 il_process_add_sta_resp(il, addsta, pkt, false);
1790
1791}
1792
e7392364
SG		 1793int
1794il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags)
0cdc2136
SG		 1795{
1796 struct il_rx_pkt *pkt = NULL;
1797 int ret = 0;
1798 u8 data[sizeof(*sta)];
1799 struct il_host_cmd cmd = {
1800 .id = C_ADD_STA,
1801 .flags = flags,
1802 .data = data,
1803 };
1804 u8 sta_id __maybe_unused = sta->sta.sta_id;
1805
e7392364
SG		 1806 D_INFO("Adding sta %u (%pM) %ssynchronously\n", sta_id, sta->sta.addr,
1807 flags & CMD_ASYNC ? "a" : "");
0cdc2136
SG		 1808
1809 if (flags & CMD_ASYNC)
1810 cmd.callback = il_add_sta_callback;
1811 else {
1812 cmd.flags |= CMD_WANT_SKB;
1813 might_sleep();
1814 }
1815
c39ae9fd 1816 cmd.len = il->ops->utils->build_addsta_hcmd(sta, data);
0cdc2136
SG		 1817 ret = il_send_cmd(il, &cmd);
1818
1819 if (ret || (flags & CMD_ASYNC))
1820 return ret;
1821
1822 if (ret == 0) {
1823 pkt = (struct il_rx_pkt *)cmd.reply_page;
1824 ret = il_process_add_sta_resp(il, sta, pkt, true);
1825 }
1826 il_free_pages(il, cmd.reply_page);
1827
1828 return ret;
1829}
1830EXPORT_SYMBOL(il_send_add_sta);
1831
e7392364 1832static void
83007196 1833il_set_ht_add_station(struct il_priv *il, u8 idx, struct ieee80211_sta *sta)
0cdc2136
SG		 1834{
1835 struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->ht_cap;
1836 __le32 sta_flags;
1837 u8 mimo_ps_mode;
1838
1839 if (!sta || !sta_ht_inf->ht_supported)
1840 goto done;
1841
1842 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_SM_PS) >> 2;
1843 D_ASSOC("spatial multiplexing power save mode: %s\n",
1722f8e1
SG		 1844 (mimo_ps_mode == WLAN_HT_CAP_SM_PS_STATIC) ? "static" :
1845 (mimo_ps_mode == WLAN_HT_CAP_SM_PS_DYNAMIC) ? "dynamic" :
1846 "disabled");
0cdc2136
SG		 1847
1848 sta_flags = il->stations[idx].sta.station_flags;
1849
1850 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
1851
1852 switch (mimo_ps_mode) {
1853 case WLAN_HT_CAP_SM_PS_STATIC:
1854 sta_flags |= STA_FLG_MIMO_DIS_MSK;
1855 break;
1856 case WLAN_HT_CAP_SM_PS_DYNAMIC:
1857 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
1858 break;
1859 case WLAN_HT_CAP_SM_PS_DISABLED:
1860 break;
1861 default:
1862 IL_WARN("Invalid MIMO PS mode %d\n", mimo_ps_mode);
1863 break;
1864 }
1865
e7392364
SG		 1866 sta_flags |=
1867 cpu_to_le32((u32) sta_ht_inf->
1868 ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
0cdc2136 1869
e7392364
SG		 1870 sta_flags |=
1871 cpu_to_le32((u32) sta_ht_inf->
1872 ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
0cdc2136 1873
83007196 1874 if (il_is_ht40_tx_allowed(il, &sta->ht_cap))
0cdc2136
SG		 1875 sta_flags |= STA_FLG_HT40_EN_MSK;
1876 else
1877 sta_flags &= ~STA_FLG_HT40_EN_MSK;
1878
1879 il->stations[idx].sta.station_flags = sta_flags;
e7392364 1880done:
0cdc2136
SG		 1881 return;
1882}
1883
1884/**
1885 * il_prep_station - Prepare station information for addition
1886 *
1887 * should be called with sta_lock held
1888 */
e7392364 1889u8
83007196
SG		 1890il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
1891 struct ieee80211_sta *sta)
0cdc2136
SG		 1892{
1893 struct il_station_entry *station;
1894 int i;
1895 u8 sta_id = IL_INVALID_STATION;
1896 u16 rate;
1897
1898 if (is_ap)
8f9e5645 1899 sta_id = IL_AP_ID;
0cdc2136 1900 else if (is_broadcast_ether_addr(addr))
b16db50a 1901 sta_id = il->hw_params.bcast_id;
0cdc2136
SG		 1902 else
1903 for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) {
e7392364
SG		 1904 if (!compare_ether_addr
1905 (il->stations[i].sta.sta.addr, addr)) {
0cdc2136
SG		 1906 sta_id = i;
1907 break;
1908 }
1909
1910 if (!il->stations[i].used &&
1911 sta_id == IL_INVALID_STATION)
1912 sta_id = i;
1913 }
1914
1915 /*
1916 * These two conditions have the same outcome, but keep them
1917 * separate
1918 */
1919 if (unlikely(sta_id == IL_INVALID_STATION))
1920 return sta_id;
1921
1922 /*
1923 * uCode is not able to deal with multiple requests to add a
1924 * station. Keep track if one is in progress so that we do not send
1925 * another.
1926 */
1927 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
e7392364 1928 D_INFO("STA %d already in process of being added.\n", sta_id);
0cdc2136
SG		 1929 return sta_id;
1930 }
1931
1932 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
1933 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) &&
1934 !compare_ether_addr(il->stations[sta_id].sta.sta.addr, addr)) {
e7392364
SG		 1935 D_ASSOC("STA %d (%pM) already added, not adding again.\n",
1936 sta_id, addr);
0cdc2136
SG		 1937 return sta_id;
1938 }
1939
1940 station = &il->stations[sta_id];
1941 station->used = IL_STA_DRIVER_ACTIVE;
e7392364 1942 D_ASSOC("Add STA to driver ID %d: %pM\n", sta_id, addr);
0cdc2136
SG		 1943 il->num_stations++;
1944
1945 /* Set up the C_ADD_STA command to send to device */
1946 memset(&station->sta, 0, sizeof(struct il_addsta_cmd));
1947 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
1948 station->sta.mode = 0;
1949 station->sta.sta.sta_id = sta_id;
fd6415bc 1950 station->sta.station_flags = 0;
0cdc2136 1951
0cdc2136
SG		 1952 /*
1953 * OK to call unconditionally, since local stations (IBSS BSSID
1954 * STA and broadcast STA) pass in a NULL sta, and mac80211
1955 * doesn't allow HT IBSS.
1956 */
83007196 1957 il_set_ht_add_station(il, sta_id, sta);
0cdc2136
SG		 1958
1959 /* 3945 only */
e7392364 1960 rate = (il->band == IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP : RATE_1M_PLCP;
0cdc2136
SG		 1961 /* Turn on both antennas for the station... */
1962 station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK);
1963
1964 return sta_id;
1965
1966}
1967EXPORT_SYMBOL_GPL(il_prep_station);
1968
1969#define STA_WAIT_TIMEOUT (HZ/2)
1970
1971/**
1972 * il_add_station_common -
1973 */
1974int
83007196
SG		 1975il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
1976 struct ieee80211_sta *sta, u8 *sta_id_r)
0cdc2136
SG		 1977{
1978 unsigned long flags_spin;
1979 int ret = 0;
1980 u8 sta_id;
1981 struct il_addsta_cmd sta_cmd;
1982
1983 *sta_id_r = 0;
1984 spin_lock_irqsave(&il->sta_lock, flags_spin);
83007196 1985 sta_id = il_prep_station(il, addr, is_ap, sta);
0cdc2136 1986 if (sta_id == IL_INVALID_STATION) {
e7392364 1987 IL_ERR("Unable to prepare station %pM for addition\n", addr);
0cdc2136
SG		 1988 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
1989 return -EINVAL;
1990 }
1991
1992 /*
1993 * uCode is not able to deal with multiple requests to add a
1994 * station. Keep track if one is in progress so that we do not send
1995 * another.
1996 */
1997 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
e7392364 1998 D_INFO("STA %d already in process of being added.\n", sta_id);
0cdc2136
SG		 1999 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2000 return -EEXIST;
2001 }
2002
2003 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
2004 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
e7392364 2005 D_ASSOC("STA %d (%pM) already added, not adding again.\n",
0cdc2136
SG		 2006 sta_id, addr);
2007 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2008 return -EEXIST;
2009 }
2010
2011 il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS;
2012 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 2013 sizeof(struct il_addsta_cmd));
0cdc2136
SG		 2014 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2015
2016 /* Add station to device's station table */
2017 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2018 if (ret) {
2019 spin_lock_irqsave(&il->sta_lock, flags_spin);
2020 IL_ERR("Adding station %pM failed.\n",
e7392364 2021 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 2022 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
2023 il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
2024 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2025 }
2026 *sta_id_r = sta_id;
2027 return ret;
2028}
2029EXPORT_SYMBOL(il_add_station_common);
2030
2031/**
2032 * il_sta_ucode_deactivate - deactivate ucode status for a station
2033 *
2034 * il->sta_lock must be held
2035 */
e7392364
SG		 2036static void
2037il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id)
0cdc2136
SG		 2038{
2039 /* Ucode must be active and driver must be non active */
e7392364
SG		 2040 if ((il->stations[sta_id].
2041 used & (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) !=
2042 IL_STA_UCODE_ACTIVE)
0cdc2136
SG		 2043 IL_ERR("removed non active STA %u\n", sta_id);
2044
2045 il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE;
2046
2047 memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry));
2048 D_ASSOC("Removed STA %u\n", sta_id);
2049}
2050
e7392364
SG		 2051static int
2052il_send_remove_station(struct il_priv *il, const u8 * addr, int sta_id,
2053 bool temporary)
0cdc2136
SG		 2054{
2055 struct il_rx_pkt *pkt;
2056 int ret;
2057
2058 unsigned long flags_spin;
2059 struct il_rem_sta_cmd rm_sta_cmd;
2060
2061 struct il_host_cmd cmd = {
2062 .id = C_REM_STA,
2063 .len = sizeof(struct il_rem_sta_cmd),
2064 .flags = CMD_SYNC,
2065 .data = &rm_sta_cmd,
2066 };
2067
2068 memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd));
2069 rm_sta_cmd.num_sta = 1;
2070 memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN);
2071
2072 cmd.flags |= CMD_WANT_SKB;
2073
2074 ret = il_send_cmd(il, &cmd);
2075
2076 if (ret)
2077 return ret;
2078
2079 pkt = (struct il_rx_pkt *)cmd.reply_page;
2080 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
e7392364 2081 IL_ERR("Bad return from C_REM_STA (0x%08X)\n", pkt->hdr.flags);
0cdc2136
SG		 2082 ret = -EIO;
2083 }
2084
2085 if (!ret) {
2086 switch (pkt->u.rem_sta.status) {
2087 case REM_STA_SUCCESS_MSK:
2088 if (!temporary) {
2089 spin_lock_irqsave(&il->sta_lock, flags_spin);
2090 il_sta_ucode_deactivate(il, sta_id);
2091 spin_unlock_irqrestore(&il->sta_lock,
e7392364 2092 flags_spin);
0cdc2136
SG		 2093 }
2094 D_ASSOC("C_REM_STA PASSED\n");
2095 break;
2096 default:
2097 ret = -EIO;
2098 IL_ERR("C_REM_STA failed\n");
2099 break;
2100 }
2101 }
2102 il_free_pages(il, cmd.reply_page);
2103
2104 return ret;
2105}
2106
2107/**
2108 * il_remove_station - Remove driver's knowledge of station.
2109 */
e7392364
SG		 2110int
2111il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr)
0cdc2136
SG		 2112{
2113 unsigned long flags;
2114
2115 if (!il_is_ready(il)) {
e7392364
SG		 2116 D_INFO("Unable to remove station %pM, device not ready.\n",
2117 addr);
0cdc2136
SG		 2118 /*
2119 * It is typical for stations to be removed when we are
2120 * going down. Return success since device will be down
2121 * soon anyway
2122 */
2123 return 0;
2124 }
2125
e7392364 2126 D_ASSOC("Removing STA from driver:%d %pM\n", sta_id, addr);
0cdc2136
SG		 2127
2128 if (WARN_ON(sta_id == IL_INVALID_STATION))
2129 return -EINVAL;
2130
2131 spin_lock_irqsave(&il->sta_lock, flags);
2132
2133 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) {
e7392364 2134 D_INFO("Removing %pM but non DRIVER active\n", addr);
0cdc2136
SG		 2135 goto out_err;
2136 }
2137
2138 if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
e7392364 2139 D_INFO("Removing %pM but non UCODE active\n", addr);
0cdc2136
SG		 2140 goto out_err;
2141 }
2142
2143 if (il->stations[sta_id].used & IL_STA_LOCAL) {
2144 kfree(il->stations[sta_id].lq);
2145 il->stations[sta_id].lq = NULL;
2146 }
2147
2148 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
2149
2150 il->num_stations--;
2151
2152 BUG_ON(il->num_stations < 0);
2153
2154 spin_unlock_irqrestore(&il->sta_lock, flags);
2155
2156 return il_send_remove_station(il, addr, sta_id, false);
2157out_err:
2158 spin_unlock_irqrestore(&il->sta_lock, flags);
2159 return -EINVAL;
2160}
2161EXPORT_SYMBOL_GPL(il_remove_station);
2162
2163/**
2164 * il_clear_ucode_stations - clear ucode station table bits
2165 *
2166 * This function clears all the bits in the driver indicating
2167 * which stations are active in the ucode. Call when something
2168 * other than explicit station management would cause this in
2169 * the ucode, e.g. unassociated RXON.
2170 */
e7392364 2171void
83007196 2172il_clear_ucode_stations(struct il_priv *il)
0cdc2136
SG		 2173{
2174 int i;
2175 unsigned long flags_spin;
2176 bool cleared = false;
2177
2178 D_INFO("Clearing ucode stations in driver\n");
2179
2180 spin_lock_irqsave(&il->sta_lock, flags_spin);
2181 for (i = 0; i < il->hw_params.max_stations; i++) {
0cdc2136 2182 if (il->stations[i].used & IL_STA_UCODE_ACTIVE) {
e7392364 2183 D_INFO("Clearing ucode active for station %d\n", i);
0cdc2136
SG		 2184 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2185 cleared = true;
2186 }
2187 }
2188 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2189
2190 if (!cleared)
e7392364 2191 D_INFO("No active stations found to be cleared\n");
0cdc2136
SG		 2192}
2193EXPORT_SYMBOL(il_clear_ucode_stations);
2194
2195/**
2196 * il_restore_stations() - Restore driver known stations to device
2197 *
2198 * All stations considered active by driver, but not present in ucode, is
2199 * restored.
2200 *
2201 * Function sleeps.
2202 */
2203void
83007196 2204il_restore_stations(struct il_priv *il)
0cdc2136
SG		 2205{
2206 struct il_addsta_cmd sta_cmd;
2207 struct il_link_quality_cmd lq;
2208 unsigned long flags_spin;
2209 int i;
2210 bool found = false;
2211 int ret;
2212 bool send_lq;
2213
2214 if (!il_is_ready(il)) {
e7392364 2215 D_INFO("Not ready yet, not restoring any stations.\n");
0cdc2136
SG		 2216 return;
2217 }
2218
2219 D_ASSOC("Restoring all known stations ... start.\n");
2220 spin_lock_irqsave(&il->sta_lock, flags_spin);
2221 for (i = 0; i < il->hw_params.max_stations; i++) {
0cdc2136
SG		 2222 if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) &&
2223 !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) {
2224 D_ASSOC("Restoring sta %pM\n",
e7392364 2225 il->stations[i].sta.sta.addr);
0cdc2136
SG		 2226 il->stations[i].sta.mode = 0;
2227 il->stations[i].used |= IL_STA_UCODE_INPROGRESS;
2228 found = true;
2229 }
2230 }
2231
2232 for (i = 0; i < il->hw_params.max_stations; i++) {
2233 if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) {
2234 memcpy(&sta_cmd, &il->stations[i].sta,
2235 sizeof(struct il_addsta_cmd));
2236 send_lq = false;
2237 if (il->stations[i].lq) {
2238 memcpy(&lq, il->stations[i].lq,
2239 sizeof(struct il_link_quality_cmd));
2240 send_lq = true;
2241 }
2242 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2243 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2244 if (ret) {
2245 spin_lock_irqsave(&il->sta_lock, flags_spin);
2246 IL_ERR("Adding station %pM failed.\n",
e7392364
SG		 2247 il->stations[i].sta.sta.addr);
2248 il->stations[i].used &= ~IL_STA_DRIVER_ACTIVE;
0cdc2136 2249 il->stations[i].used &=
e7392364 2250 ~IL_STA_UCODE_INPROGRESS;
0cdc2136 2251 spin_unlock_irqrestore(&il->sta_lock,
e7392364 2252 flags_spin);
0cdc2136
SG		 2253 }
2254 /*
2255 * Rate scaling has already been initialized, send
2256 * current LQ command
2257 */
2258 if (send_lq)
83007196 2259 il_send_lq_cmd(il, &lq, CMD_SYNC, true);
0cdc2136
SG		 2260 spin_lock_irqsave(&il->sta_lock, flags_spin);
2261 il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS;
2262 }
2263 }
2264
2265 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2266 if (!found)
2267 D_INFO("Restoring all known stations"
e7392364 2268 " .... no stations to be restored.\n");
0cdc2136 2269 else
e7392364 2270 D_INFO("Restoring all known stations" " .... complete.\n");
0cdc2136
SG		 2271}
2272EXPORT_SYMBOL(il_restore_stations);
2273
e7392364
SG		 2274int
2275il_get_free_ucode_key_idx(struct il_priv *il)
0cdc2136
SG		 2276{
2277 int i;
2278
2279 for (i = 0; i < il->sta_key_max_num; i++)
2280 if (!test_and_set_bit(i, &il->ucode_key_table))
2281 return i;
2282
2283 return WEP_INVALID_OFFSET;
2284}
2285EXPORT_SYMBOL(il_get_free_ucode_key_idx);
2286
e7392364
SG		 2287void
2288il_dealloc_bcast_stations(struct il_priv *il)
0cdc2136
SG		 2289{
2290 unsigned long flags;
2291 int i;
2292
2293 spin_lock_irqsave(&il->sta_lock, flags);
2294 for (i = 0; i < il->hw_params.max_stations; i++) {
2295 if (!(il->stations[i].used & IL_STA_BCAST))
2296 continue;
2297
2298 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2299 il->num_stations--;
2300 BUG_ON(il->num_stations < 0);
2301 kfree(il->stations[i].lq);
2302 il->stations[i].lq = NULL;
2303 }
2304 spin_unlock_irqrestore(&il->sta_lock, flags);
2305}
2306EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations);
2307
2308#ifdef CONFIG_IWLEGACY_DEBUG
e7392364
SG		 2309static void
2310il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG		 2311{
2312 int i;
2313 D_RATE("lq station id 0x%x\n", lq->sta_id);
e7392364
SG		 2314 D_RATE("lq ant 0x%X 0x%X\n", lq->general_params.single_stream_ant_msk,
2315 lq->general_params.dual_stream_ant_msk);
0cdc2136
SG		 2316
2317 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
e7392364 2318 D_RATE("lq idx %d 0x%X\n", i, lq->rs_table[i].rate_n_flags);
0cdc2136
SG		 2319}
2320#else
e7392364
SG		 2321static inline void
2322il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG		 2323{
2324}
2325#endif
2326
2327/**
2328 * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity
2329 *
2330 * It sometimes happens when a HT rate has been in use and we
2331 * loose connectivity with AP then mac80211 will first tell us that the
2332 * current channel is not HT anymore before removing the station. In such a
2333 * scenario the RXON flags will be updated to indicate we are not
2334 * communicating HT anymore, but the LQ command may still contain HT rates.
2335 * Test for this to prevent driver from sending LQ command between the time
2336 * RXON flags are updated and when LQ command is updated.
2337 */
e7392364 2338static bool
83007196 2339il_is_lq_table_valid(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG		 2340{
2341 int i;
2342
1c03c462 2343 if (il->ht.enabled)
0cdc2136
SG		 2344 return true;
2345
c8b03958 2346 D_INFO("Channel %u is not an HT channel\n", il->active.channel);
0cdc2136 2347 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
e7392364
SG		 2348 if (le32_to_cpu(lq->rs_table[i].rate_n_flags) & RATE_MCS_HT_MSK) {
2349 D_INFO("idx %d of LQ expects HT channel\n", i);
0cdc2136
SG		 2350 return false;
2351 }
2352 }
2353 return true;
2354}
2355
2356/**
2357 * il_send_lq_cmd() - Send link quality command
2358 * @init: This command is sent as part of station initialization right
2359 * after station has been added.
2360 *
2361 * The link quality command is sent as the last step of station creation.
2362 * This is the special case in which init is set and we call a callback in
2363 * this case to clear the state indicating that station creation is in
2364 * progress.
2365 */
e7392364 2366int
83007196
SG		 2367il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2368 u8 flags, bool init)
0cdc2136
SG		 2369{
2370 int ret = 0;
2371 unsigned long flags_spin;
2372
2373 struct il_host_cmd cmd = {
2374 .id = C_TX_LINK_QUALITY_CMD,
2375 .len = sizeof(struct il_link_quality_cmd),
2376 .flags = flags,
2377 .data = lq,
2378 };
2379
2380 if (WARN_ON(lq->sta_id == IL_INVALID_STATION))
2381 return -EINVAL;
2382
0cdc2136
SG		 2383 spin_lock_irqsave(&il->sta_lock, flags_spin);
2384 if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) {
2385 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2386 return -EINVAL;
2387 }
2388 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2389
2390 il_dump_lq_cmd(il, lq);
2391 BUG_ON(init && (cmd.flags & CMD_ASYNC));
2392
83007196 2393 if (il_is_lq_table_valid(il, lq))
0cdc2136
SG		 2394 ret = il_send_cmd(il, &cmd);
2395 else
2396 ret = -EINVAL;
2397
2398 if (cmd.flags & CMD_ASYNC)
2399 return ret;
2400
2401 if (init) {
2402 D_INFO("init LQ command complete,"
e7392364
SG		 2403 " clearing sta addition status for sta %d\n",
2404 lq->sta_id);
0cdc2136
SG		 2405 spin_lock_irqsave(&il->sta_lock, flags_spin);
2406 il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
2407 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2408 }
2409 return ret;
2410}
2411EXPORT_SYMBOL(il_send_lq_cmd);
2412
e7392364
SG		 2413int
2414il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2415 struct ieee80211_sta *sta)
0cdc2136
SG		 2416{
2417 struct il_priv *il = hw->priv;
2418 struct il_station_priv_common *sta_common = (void *)sta->drv_priv;
2419 int ret;
2420
e7392364 2421 D_INFO("received request to remove station %pM\n", sta->addr);
0cdc2136 2422 mutex_lock(&il->mutex);
e7392364 2423 D_INFO("proceeding to remove station %pM\n", sta->addr);
0cdc2136
SG		 2424 ret = il_remove_station(il, sta_common->sta_id, sta->addr);
2425 if (ret)
e7392364 2426 IL_ERR("Error removing station %pM\n", sta->addr);
0cdc2136
SG		 2427 mutex_unlock(&il->mutex);
2428 return ret;
2429}
2430EXPORT_SYMBOL(il_mac_sta_remove);
2431
2432/************************** RX-FUNCTIONS ****************************/
2433/*
2434 * Rx theory of operation
2435 *
2436 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
2437 * each of which point to Receive Buffers to be filled by the NIC. These get
2438 * used not only for Rx frames, but for any command response or notification
2439 * from the NIC. The driver and NIC manage the Rx buffers by means
2440 * of idxes into the circular buffer.
2441 *
2442 * Rx Queue Indexes
2443 * The host/firmware share two idx registers for managing the Rx buffers.
2444 *
2445 * The READ idx maps to the first position that the firmware may be writing
2446 * to -- the driver can read up to (but not including) this position and get
2447 * good data.
2448 * The READ idx is managed by the firmware once the card is enabled.
2449 *
2450 * The WRITE idx maps to the last position the driver has read from -- the
2451 * position preceding WRITE is the last slot the firmware can place a packet.
2452 *
2453 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
2454 * WRITE = READ.
2455 *
2456 * During initialization, the host sets up the READ queue position to the first
2457 * IDX position, and WRITE to the last (READ - 1 wrapped)
2458 *
2459 * When the firmware places a packet in a buffer, it will advance the READ idx
2460 * and fire the RX interrupt. The driver can then query the READ idx and
2461 * process as many packets as possible, moving the WRITE idx forward as it
2462 * resets the Rx queue buffers with new memory.
2463 *
2464 * The management in the driver is as follows:
2465 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
2466 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
2467 * to replenish the iwl->rxq->rx_free.
2468 * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the
2469 * iwl->rxq is replenished and the READ IDX is updated (updating the
2470 * 'processed' and 'read' driver idxes as well)
2471 * + A received packet is processed and handed to the kernel network stack,
2472 * detached from the iwl->rxq. The driver 'processed' idx is updated.
2473 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
2474 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
2475 * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
2476 * were enough free buffers and RX_STALLED is set it is cleared.
2477 *
2478 *
2479 * Driver sequence:
2480 *
2481 * il_rx_queue_alloc() Allocates rx_free
2482 * il_rx_replenish() Replenishes rx_free list from rx_used, and calls
2483 * il_rx_queue_restock
2484 * il_rx_queue_restock() Moves available buffers from rx_free into Rx
2485 * queue, updates firmware pointers, and updates
2486 * the WRITE idx. If insufficient rx_free buffers
2487 * are available, schedules il_rx_replenish
2488 *
2489 * -- enable interrupts --
2490 * ISR - il_rx() Detach il_rx_bufs from pool up to the
2491 * READ IDX, detaching the SKB from the pool.
2492 * Moves the packet buffer from queue to rx_used.
2493 * Calls il_rx_queue_restock to refill any empty
2494 * slots.
2495 * ...
2496 *
2497 */
2498
2499/**
2500 * il_rx_queue_space - Return number of free slots available in queue.
2501 */
e7392364
SG		 2502int
2503il_rx_queue_space(const struct il_rx_queue *q)
0cdc2136
SG		 2504{
2505 int s = q->read - q->write;
2506 if (s <= 0)
2507 s += RX_QUEUE_SIZE;
2508 /* keep some buffer to not confuse full and empty queue */
2509 s -= 2;
2510 if (s < 0)
2511 s = 0;
2512 return s;
2513}
2514EXPORT_SYMBOL(il_rx_queue_space);
2515
2516/**
2517 * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue
2518 */
2519void
e7392364 2520il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q)
0cdc2136
SG		 2521{
2522 unsigned long flags;
2523 u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg;
2524 u32 reg;
2525
2526 spin_lock_irqsave(&q->lock, flags);
2527
2528 if (q->need_update == 0)
2529 goto exit_unlock;
2530
2531 /* If power-saving is in use, make sure device is awake */
2532 if (test_bit(S_POWER_PMI, &il->status)) {
2533 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2534
2535 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
e7392364
SG		 2536 D_INFO("Rx queue requesting wakeup," " GP1 = 0x%x\n",
2537 reg);
0cdc2136 2538 il_set_bit(il, CSR_GP_CNTRL,
e7392364 2539 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
0cdc2136
SG		 2540 goto exit_unlock;
2541 }
2542
2543 q->write_actual = (q->write & ~0x7);
e7392364 2544 il_wr(il, rx_wrt_ptr_reg, q->write_actual);
0cdc2136 2545
e7392364 2546 /* Else device is assumed to be awake */
0cdc2136
SG		 2547 } else {
2548 /* Device expects a multiple of 8 */
2549 q->write_actual = (q->write & ~0x7);
e7392364 2550 il_wr(il, rx_wrt_ptr_reg, q->write_actual);
0cdc2136
SG		 2551 }
2552
2553 q->need_update = 0;
2554
e7392364 2555exit_unlock:
0cdc2136
SG		 2556 spin_unlock_irqrestore(&q->lock, flags);
2557}
2558EXPORT_SYMBOL(il_rx_queue_update_write_ptr);
2559
e7392364
SG		 2560int
2561il_rx_queue_alloc(struct il_priv *il)
0cdc2136
SG		 2562{
2563 struct il_rx_queue *rxq = &il->rxq;
2564 struct device *dev = &il->pci_dev->dev;
2565 int i;
2566
2567 spin_lock_init(&rxq->lock);
2568 INIT_LIST_HEAD(&rxq->rx_free);
2569 INIT_LIST_HEAD(&rxq->rx_used);
2570
2571 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
e7392364
SG		 2572 rxq->bd =
2573 dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
2574 GFP_KERNEL);
0cdc2136
SG		 2575 if (!rxq->bd)
2576 goto err_bd;
2577
e7392364
SG		 2578 rxq->rb_stts =
2579 dma_alloc_coherent(dev, sizeof(struct il_rb_status),
2580 &rxq->rb_stts_dma, GFP_KERNEL);
0cdc2136
SG		 2581 if (!rxq->rb_stts)
2582 goto err_rb;
2583
2584 /* Fill the rx_used queue with _all_ of the Rx buffers */
2585 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
2586 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
2587
2588 /* Set us so that we have processed and used all buffers, but have
2589 * not restocked the Rx queue with fresh buffers */
2590 rxq->read = rxq->write = 0;
2591 rxq->write_actual = 0;
2592 rxq->free_count = 0;
2593 rxq->need_update = 0;
2594 return 0;
2595
2596err_rb:
2597 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
2598 rxq->bd_dma);
2599err_bd:
2600 return -ENOMEM;
2601}
e7392364 2602EXPORT_SYMBOL(il_rx_queue_alloc);
0cdc2136 2603
e7392364
SG		 2604void
2605il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 2606{
2607 struct il_rx_pkt *pkt = rxb_addr(rxb);
2608 struct il_spectrum_notification *report = &(pkt->u.spectrum_notif);
2609
2610 if (!report->state) {
e7392364 2611 D_11H("Spectrum Measure Notification: Start\n");
0cdc2136
SG		 2612 return;
2613 }
2614
2615 memcpy(&il->measure_report, report, sizeof(*report));
2616 il->measurement_status |= MEASUREMENT_READY;
2617}
2618EXPORT_SYMBOL(il_hdl_spectrum_measurement);
2619
2620/*
2621 * returns non-zero if packet should be dropped
2622 */
e7392364
SG		 2623int
2624il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
2625 u32 decrypt_res, struct ieee80211_rx_status *stats)
0cdc2136
SG		 2626{
2627 u16 fc = le16_to_cpu(hdr->frame_control);
2628
2629 /*
2630 * All contexts have the same setting here due to it being
2631 * a module parameter, so OK to check any context.
2632 */
c8b03958 2633 if (il->active.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
0cdc2136
SG		 2634 return 0;
2635
2636 if (!(fc & IEEE80211_FCTL_PROTECTED))
2637 return 0;
2638
2639 D_RX("decrypt_res:0x%x\n", decrypt_res);
2640 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2641 case RX_RES_STATUS_SEC_TYPE_TKIP:
2642 /* The uCode has got a bad phase 1 Key, pushes the packet.
2643 * Decryption will be done in SW. */
2644 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2645 RX_RES_STATUS_BAD_KEY_TTAK)
2646 break;
2647
2648 case RX_RES_STATUS_SEC_TYPE_WEP:
2649 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2650 RX_RES_STATUS_BAD_ICV_MIC) {
2651 /* bad ICV, the packet is destroyed since the
2652 * decryption is inplace, drop it */
2653 D_RX("Packet destroyed\n");
2654 return -1;
2655 }
2656 case RX_RES_STATUS_SEC_TYPE_CCMP:
2657 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2658 RX_RES_STATUS_DECRYPT_OK) {
2659 D_RX("hw decrypt successfully!!!\n");
2660 stats->flag |= RX_FLAG_DECRYPTED;
2661 }
2662 break;
2663
2664 default:
2665 break;
2666 }
2667 return 0;
2668}
2669EXPORT_SYMBOL(il_set_decrypted_flag);
2670
2671/**
2672 * il_txq_update_write_ptr - Send new write idx to hardware
2673 */
2674void
2675il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq)
2676{
2677 u32 reg = 0;
2678 int txq_id = txq->q.id;
2679
2680 if (txq->need_update == 0)
2681 return;
2682
2683 /* if we're trying to save power */
2684 if (test_bit(S_POWER_PMI, &il->status)) {
2685 /* wake up nic if it's powered down ...
2686 * uCode will wake up, and interrupt us again, so next
2687 * time we'll skip this part. */
2688 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2689
2690 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
e7392364
SG		 2691 D_INFO("Tx queue %d requesting wakeup," " GP1 = 0x%x\n",
2692 txq_id, reg);
0cdc2136 2693 il_set_bit(il, CSR_GP_CNTRL,
e7392364 2694 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
0cdc2136
SG		 2695 return;
2696 }
2697
e7392364 2698 il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
0cdc2136
SG		 2699
2700 /*
2701 * else not in power-save mode,
2702 * uCode will never sleep when we're
2703 * trying to tx (during RFKILL, we're not trying to tx).
2704 */
2705 } else
e7392364 2706 _il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
0cdc2136
SG		 2707 txq->need_update = 0;
2708}
2709EXPORT_SYMBOL(il_txq_update_write_ptr);
2710
2711/**
2712 * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
2713 */
e7392364
SG		 2714void
2715il_tx_queue_unmap(struct il_priv *il, int txq_id)
0cdc2136
SG		 2716{
2717 struct il_tx_queue *txq = &il->txq[txq_id];
2718 struct il_queue *q = &txq->q;
2719
2720 if (q->n_bd == 0)
2721 return;
2722
2723 while (q->write_ptr != q->read_ptr) {
c39ae9fd 2724 il->ops->lib->txq_free_tfd(il, txq);
0cdc2136
SG		 2725 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2726 }
2727}
2728EXPORT_SYMBOL(il_tx_queue_unmap);
2729
2730/**
2731 * il_tx_queue_free - Deallocate DMA queue.
2732 * @txq: Transmit queue to deallocate.
2733 *
2734 * Empty queue by removing and destroying all BD's.
2735 * Free all buffers.
2736 * 0-fill, but do not free "txq" descriptor structure.
2737 */
e7392364
SG		 2738void
2739il_tx_queue_free(struct il_priv *il, int txq_id)
0cdc2136
SG		 2740{
2741 struct il_tx_queue *txq = &il->txq[txq_id];
2742 struct device *dev = &il->pci_dev->dev;
2743 int i;
2744
2745 il_tx_queue_unmap(il, txq_id);
2746
2747 /* De-alloc array of command/tx buffers */
2748 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
2749 kfree(txq->cmd[i]);
2750
2751 /* De-alloc circular buffer of TFDs */
2752 if (txq->q.n_bd)
e7392364
SG		 2753 dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
2754 txq->tfds, txq->q.dma_addr);
0cdc2136
SG		 2755
2756 /* De-alloc array of per-TFD driver data */
00ea99e1
SG		 2757 kfree(txq->skbs);
2758 txq->skbs = NULL;
0cdc2136
SG		 2759
2760 /* deallocate arrays */
2761 kfree(txq->cmd);
2762 kfree(txq->meta);
2763 txq->cmd = NULL;
2764 txq->meta = NULL;
2765
2766 /* 0-fill queue descriptor structure */
2767 memset(txq, 0, sizeof(*txq));
2768}
2769EXPORT_SYMBOL(il_tx_queue_free);
2770
2771/**
2772 * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
2773 */
e7392364
SG		 2774void
2775il_cmd_queue_unmap(struct il_priv *il)
0cdc2136
SG		 2776{
2777 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2778 struct il_queue *q = &txq->q;
2779 int i;
2780
2781 if (q->n_bd == 0)
2782 return;
2783
2784 while (q->read_ptr != q->write_ptr) {
2785 i = il_get_cmd_idx(q, q->read_ptr, 0);
2786
2787 if (txq->meta[i].flags & CMD_MAPPED) {
2788 pci_unmap_single(il->pci_dev,
2789 dma_unmap_addr(&txq->meta[i], mapping),
2790 dma_unmap_len(&txq->meta[i], len),
2791 PCI_DMA_BIDIRECTIONAL);
2792 txq->meta[i].flags = 0;
2793 }
2794
2795 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2796 }
2797
2798 i = q->n_win;
2799 if (txq->meta[i].flags & CMD_MAPPED) {
2800 pci_unmap_single(il->pci_dev,
2801 dma_unmap_addr(&txq->meta[i], mapping),
2802 dma_unmap_len(&txq->meta[i], len),
2803 PCI_DMA_BIDIRECTIONAL);
2804 txq->meta[i].flags = 0;
2805 }
2806}
2807EXPORT_SYMBOL(il_cmd_queue_unmap);
2808
2809/**
2810 * il_cmd_queue_free - Deallocate DMA queue.
2811 * @txq: Transmit queue to deallocate.
2812 *
2813 * Empty queue by removing and destroying all BD's.
2814 * Free all buffers.
2815 * 0-fill, but do not free "txq" descriptor structure.
2816 */
e7392364
SG		 2817void
2818il_cmd_queue_free(struct il_priv *il)
0cdc2136
SG		 2819{
2820 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2821 struct device *dev = &il->pci_dev->dev;
2822 int i;
2823
2824 il_cmd_queue_unmap(il);
2825
2826 /* De-alloc array of command/tx buffers */
2827 for (i = 0; i <= TFD_CMD_SLOTS; i++)
2828 kfree(txq->cmd[i]);
2829
2830 /* De-alloc circular buffer of TFDs */
2831 if (txq->q.n_bd)
2832 dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
2833 txq->tfds, txq->q.dma_addr);
2834
2835 /* deallocate arrays */
2836 kfree(txq->cmd);
2837 kfree(txq->meta);
2838 txq->cmd = NULL;
2839 txq->meta = NULL;
2840
2841 /* 0-fill queue descriptor structure */
2842 memset(txq, 0, sizeof(*txq));
2843}
2844EXPORT_SYMBOL(il_cmd_queue_free);
2845
2846/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
2847 * DMA services
2848 *
2849 * Theory of operation
2850 *
2851 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
2852 * of buffer descriptors, each of which points to one or more data buffers for
2853 * the device to read from or fill. Driver and device exchange status of each
2854 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
2855 * entries in each circular buffer, to protect against confusing empty and full
2856 * queue states.
2857 *
2858 * The device reads or writes the data in the queues via the device's several
2859 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
2860 *
2861 * For Tx queue, there are low mark and high mark limits. If, after queuing
2862 * the packet for Tx, free space become < low mark, Tx queue stopped. When
2863 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
2864 * Tx queue resumed.
2865 *
2866 * See more detailed info in 4965.h.
2867 ***************************************************/
2868
e7392364
SG		 2869int
2870il_queue_space(const struct il_queue *q)
0cdc2136
SG		 2871{
2872 int s = q->read_ptr - q->write_ptr;
2873
2874 if (q->read_ptr > q->write_ptr)
2875 s -= q->n_bd;
2876
2877 if (s <= 0)
2878 s += q->n_win;
2879 /* keep some reserve to not confuse empty and full situations */
2880 s -= 2;
2881 if (s < 0)
2882 s = 0;
2883 return s;
2884}
2885EXPORT_SYMBOL(il_queue_space);
2886
2887
2888/**
2889 * il_queue_init - Initialize queue's high/low-water and read/write idxes
2890 */
e7392364
SG		 2891static int
2892il_queue_init(struct il_priv *il, struct il_queue *q, int count, int slots_num,
2893 u32 id)
0cdc2136
SG		 2894{
2895 q->n_bd = count;
2896 q->n_win = slots_num;
2897 q->id = id;
2898
2899 /* count must be power-of-two size, otherwise il_queue_inc_wrap
2900 * and il_queue_dec_wrap are broken. */
2901 BUG_ON(!is_power_of_2(count));
2902
2903 /* slots_num must be power-of-two size, otherwise
2904 * il_get_cmd_idx is broken. */
2905 BUG_ON(!is_power_of_2(slots_num));
2906
2907 q->low_mark = q->n_win / 4;
2908 if (q->low_mark < 4)
2909 q->low_mark = 4;
2910
2911 q->high_mark = q->n_win / 8;
2912 if (q->high_mark < 2)
2913 q->high_mark = 2;
2914
2915 q->write_ptr = q->read_ptr = 0;
2916
2917 return 0;
2918}
2919
2920/**
2921 * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
2922 */
e7392364
SG		 2923static int
2924il_tx_queue_alloc(struct il_priv *il, struct il_tx_queue *txq, u32 id)
0cdc2136
SG		 2925{
2926 struct device *dev = &il->pci_dev->dev;
2927 size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
2928
2929 /* Driver ilate data, only for Tx (not command) queues,
2930 * not shared with device. */
2931 if (id != il->cmd_queue) {
00ea99e1
SG		 2932 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(struct skb *),
2933 GFP_KERNEL);
2934 if (!txq->skbs) {
2935 IL_ERR("Fail to alloc skbs\n");
0cdc2136
SG		 2936 goto error;
2937 }
00ea99e1
SG		 2938 } else
2939 txq->skbs = NULL;
0cdc2136
SG		 2940
2941 /* Circular buffer of transmit frame descriptors (TFDs),
2942 * shared with device */
e7392364
SG		 2943 txq->tfds =
2944 dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, GFP_KERNEL);
0cdc2136 2945 if (!txq->tfds) {
00ea99e1 2946 IL_ERR("Fail to alloc TFDs\n");
0cdc2136
SG		 2947 goto error;
2948 }
2949 txq->q.id = id;
2950
2951 return 0;
2952
e7392364 2953error:
00ea99e1
SG		 2954 kfree(txq->skbs);
2955 txq->skbs = NULL;
0cdc2136
SG		 2956
2957 return -ENOMEM;
2958}
2959
2960/**
2961 * il_tx_queue_init - Allocate and initialize one tx/cmd queue
2962 */
e7392364
SG		 2963int
2964il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
2965 u32 txq_id)
0cdc2136
SG		 2966{
2967 int i, len;
2968 int ret;
2969 int actual_slots = slots_num;
2970
2971 /*
2972 * Alloc buffer array for commands (Tx or other types of commands).
2973 * For the command queue (#4/#9), allocate command space + one big
2974 * command for scan, since scan command is very huge; the system will
2975 * not have two scans at the same time, so only one is needed.
2976 * For normal Tx queues (all other queues), no super-size command
2977 * space is needed.
2978 */
2979 if (txq_id == il->cmd_queue)
2980 actual_slots++;
2981
e7392364
SG		 2982 txq->meta =
2983 kzalloc(sizeof(struct il_cmd_meta) * actual_slots, GFP_KERNEL);
2984 txq->cmd =
2985 kzalloc(sizeof(struct il_device_cmd *) * actual_slots, GFP_KERNEL);
0cdc2136
SG		 2986
2987 if (!txq->meta || !txq->cmd)
2988 goto out_free_arrays;
2989
2990 len = sizeof(struct il_device_cmd);
2991 for (i = 0; i < actual_slots; i++) {
2992 /* only happens for cmd queue */
2993 if (i == slots_num)
2994 len = IL_MAX_CMD_SIZE;
2995
2996 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
2997 if (!txq->cmd[i])
2998 goto err;
2999 }
3000
3001 /* Alloc driver data array and TFD circular buffer */
3002 ret = il_tx_queue_alloc(il, txq, txq_id);
3003 if (ret)
3004 goto err;
3005
3006 txq->need_update = 0;
3007
3008 /*
3009 * For the default queues 0-3, set up the swq_id
3010 * already -- all others need to get one later
3011 * (if they need one at all).
3012 */
3013 if (txq_id < 4)
3014 il_set_swq_id(txq, txq_id, txq_id);
3015
3016 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
3017 * il_queue_inc_wrap and il_queue_dec_wrap are broken. */
3018 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
3019
3020 /* Initialize queue's high/low-water marks, and head/tail idxes */
e7392364 3021 il_queue_init(il, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
0cdc2136
SG		 3022
3023 /* Tell device where to find queue */
c39ae9fd 3024 il->ops->lib->txq_init(il, txq);
0cdc2136
SG		 3025
3026 return 0;
3027err:
3028 for (i = 0; i < actual_slots; i++)
3029 kfree(txq->cmd[i]);
3030out_free_arrays:
3031 kfree(txq->meta);
3032 kfree(txq->cmd);
3033
3034 return -ENOMEM;
3035}
3036EXPORT_SYMBOL(il_tx_queue_init);
3037
e7392364
SG		 3038void
3039il_tx_queue_reset(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
3040 u32 txq_id)
0cdc2136
SG		 3041{
3042 int actual_slots = slots_num;
3043
3044 if (txq_id == il->cmd_queue)
3045 actual_slots++;
3046
3047 memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots);
3048
3049 txq->need_update = 0;
3050
3051 /* Initialize queue's high/low-water marks, and head/tail idxes */
e7392364 3052 il_queue_init(il, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
0cdc2136
SG		 3053
3054 /* Tell device where to find queue */
c39ae9fd 3055 il->ops->lib->txq_init(il, txq);
0cdc2136
SG		 3056}
3057EXPORT_SYMBOL(il_tx_queue_reset);
3058
3059/*************** HOST COMMAND QUEUE FUNCTIONS *****/
3060
3061/**
3062 * il_enqueue_hcmd - enqueue a uCode command
3063 * @il: device ilate data point
3064 * @cmd: a point to the ucode command structure
3065 *
3066 * The function returns < 0 values to indicate the operation is
3067 * failed. On success, it turns the idx (> 0) of command in the
3068 * command queue.
3069 */
e7392364
SG		 3070int
3071il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG		 3072{
3073 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
3074 struct il_queue *q = &txq->q;
3075 struct il_device_cmd *out_cmd;
3076 struct il_cmd_meta *out_meta;
3077 dma_addr_t phys_addr;
3078 unsigned long flags;
3079 int len;
3080 u32 idx;
3081 u16 fix_size;
3082
c39ae9fd 3083 cmd->len = il->ops->utils->get_hcmd_size(cmd->id, cmd->len);
e7392364 3084 fix_size = (u16) (cmd->len + sizeof(out_cmd->hdr));
0cdc2136
SG		 3085
3086 /* If any of the command structures end up being larger than
3087 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
3088 * we will need to increase the size of the TFD entries
3089 * Also, check to see if command buffer should not exceed the size
3090 * of device_cmd and max_cmd_size. */
3091 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
3092 !(cmd->flags & CMD_SIZE_HUGE));
3093 BUG_ON(fix_size > IL_MAX_CMD_SIZE);
3094
3095 if (il_is_rfkill(il) || il_is_ctkill(il)) {
3096 IL_WARN("Not sending command - %s KILL\n",
e7392364 3097 il_is_rfkill(il) ? "RF" : "CT");
0cdc2136
SG		 3098 return -EIO;
3099 }
3100
3101 spin_lock_irqsave(&il->hcmd_lock, flags);
3102
3103 if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
3104 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3105
3106 IL_ERR("Restarting adapter due to command queue full\n");
3107 queue_work(il->workqueue, &il->restart);
3108 return -ENOSPC;
3109 }
3110
3111 idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
3112 out_cmd = txq->cmd[idx];
3113 out_meta = &txq->meta[idx];
3114
3115 if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
3116 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3117 return -ENOSPC;
3118 }
3119
3120 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
3121 out_meta->flags = cmd->flags | CMD_MAPPED;
3122 if (cmd->flags & CMD_WANT_SKB)
3123 out_meta->source = cmd;
3124 if (cmd->flags & CMD_ASYNC)
3125 out_meta->callback = cmd->callback;
3126
3127 out_cmd->hdr.cmd = cmd->id;
3128 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
3129
3130 /* At this point, the out_cmd now has all of the incoming cmd
3131 * information */
3132
3133 out_cmd->hdr.flags = 0;
e7392364
SG		 3134 out_cmd->hdr.sequence =
3135 cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) | IDX_TO_SEQ(q->write_ptr));
0cdc2136
SG		 3136 if (cmd->flags & CMD_SIZE_HUGE)
3137 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
3138 len = sizeof(struct il_device_cmd);
3139 if (idx == TFD_CMD_SLOTS)
3140 len = IL_MAX_CMD_SIZE;
3141
3142#ifdef CONFIG_IWLEGACY_DEBUG
3143 switch (out_cmd->hdr.cmd) {
3144 case C_TX_LINK_QUALITY_CMD:
3145 case C_SENSITIVITY:
e7392364
SG		 3146 D_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
3147 "%d bytes at %d[%d]:%d\n",
3148 il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
3149 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
3150 q->write_ptr, idx, il->cmd_queue);
0cdc2136
SG		 3151 break;
3152 default:
3153 D_HC("Sending command %s (#%x), seq: 0x%04X, "
e7392364
SG		 3154 "%d bytes at %d[%d]:%d\n",
3155 il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
3156 le16_to_cpu(out_cmd->hdr.sequence), fix_size, q->write_ptr,
3157 idx, il->cmd_queue);
0cdc2136
SG		 3158 }
3159#endif
3160 txq->need_update = 1;
3161
c39ae9fd 3162 if (il->ops->lib->txq_update_byte_cnt_tbl)
0cdc2136 3163 /* Set up entry in queue's byte count circular buffer */
c39ae9fd 3164 il->ops->lib->txq_update_byte_cnt_tbl(il, txq, 0);
0cdc2136 3165
e7392364
SG		 3166 phys_addr =
3167 pci_map_single(il->pci_dev, &out_cmd->hdr, fix_size,
3168 PCI_DMA_BIDIRECTIONAL);
0cdc2136
SG		 3169 dma_unmap_addr_set(out_meta, mapping, phys_addr);
3170 dma_unmap_len_set(out_meta, len, fix_size);
3171
c39ae9fd
SG		 3172 il->ops->lib->txq_attach_buf_to_tfd(il, txq, phys_addr, fix_size, 1,
3173 U32_PAD(cmd->len));
0cdc2136
SG		 3174
3175 /* Increment and update queue's write idx */
3176 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
3177 il_txq_update_write_ptr(il, txq);
3178
3179 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3180 return idx;
3181}
3182
3183/**
3184 * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
3185 *
3186 * When FW advances 'R' idx, all entries between old and new 'R' idx
3187 * need to be reclaimed. As result, some free space forms. If there is
3188 * enough free space (> low mark), wake the stack that feeds us.
3189 */
e7392364
SG		 3190static void
3191il_hcmd_queue_reclaim(struct il_priv *il, int txq_id, int idx, int cmd_idx)
0cdc2136
SG		 3192{
3193 struct il_tx_queue *txq = &il->txq[txq_id];
3194 struct il_queue *q = &txq->q;
3195 int nfreed = 0;
3196
3197 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
3198 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
e7392364
SG		 3199 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
3200 q->write_ptr, q->read_ptr);
0cdc2136
SG		 3201 return;
3202 }
3203
3204 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
3205 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3206
3207 if (nfreed++ > 0) {
3208 IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx,
e7392364 3209 q->write_ptr, q->read_ptr);
0cdc2136
SG		 3210 queue_work(il->workqueue, &il->restart);
3211 }
3212
3213 }
3214}
3215
3216/**
3217 * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
3218 * @rxb: Rx buffer to reclaim
3219 *
3220 * If an Rx buffer has an async callback associated with it the callback
3221 * will be executed. The attached skb (if present) will only be freed
3222 * if the callback returns 1
3223 */
3224void
3225il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb)
3226{
3227 struct il_rx_pkt *pkt = rxb_addr(rxb);
3228 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3229 int txq_id = SEQ_TO_QUEUE(sequence);
3230 int idx = SEQ_TO_IDX(sequence);
3231 int cmd_idx;
3232 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
3233 struct il_device_cmd *cmd;
3234 struct il_cmd_meta *meta;
3235 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
3236 unsigned long flags;
3237
3238 /* If a Tx command is being handled and it isn't in the actual
3239 * command queue then there a command routing bug has been introduced
3240 * in the queue management code. */
e7392364
SG		 3241 if (WARN
3242 (txq_id != il->cmd_queue,
3243 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
3244 txq_id, il->cmd_queue, sequence, il->txq[il->cmd_queue].q.read_ptr,
3245 il->txq[il->cmd_queue].q.write_ptr)) {
0cdc2136
SG		 3246 il_print_hex_error(il, pkt, 32);
3247 return;
3248 }
3249
3250 cmd_idx = il_get_cmd_idx(&txq->q, idx, huge);
3251 cmd = txq->cmd[cmd_idx];
3252 meta = &txq->meta[cmd_idx];
3253
3254 txq->time_stamp = jiffies;
3255
e7392364
SG		 3256 pci_unmap_single(il->pci_dev, dma_unmap_addr(meta, mapping),
3257 dma_unmap_len(meta, len), PCI_DMA_BIDIRECTIONAL);
0cdc2136
SG		 3258
3259 /* Input error checking is done when commands are added to queue. */
3260 if (meta->flags & CMD_WANT_SKB) {
3261 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
3262 rxb->page = NULL;
3263 } else if (meta->callback)
3264 meta->callback(il, cmd, pkt);
3265
3266 spin_lock_irqsave(&il->hcmd_lock, flags);
3267
3268 il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx);
3269
3270 if (!(meta->flags & CMD_ASYNC)) {
3271 clear_bit(S_HCMD_ACTIVE, &il->status);
3272 D_INFO("Clearing HCMD_ACTIVE for command %s\n",
e7392364 3273 il_get_cmd_string(cmd->hdr.cmd));
0cdc2136
SG		 3274 wake_up(&il->wait_command_queue);
3275 }
3276
3277 /* Mark as unmapped */
3278 meta->flags = 0;
3279
3280 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3281}
3282EXPORT_SYMBOL(il_tx_cmd_complete);
be663ab6
WYG		 3283
3284MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965");
3285MODULE_VERSION(IWLWIFI_VERSION);
3286MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
3287MODULE_LICENSE("GPL");
3288
3289/*
3290 * set bt_coex_active to true, uCode will do kill/defer
3291 * every time the priority line is asserted (BT is sending signals on the
3292 * priority line in the PCIx).
3293 * set bt_coex_active to false, uCode will ignore the BT activity and
3294 * perform the normal operation
3295 *
3296 * User might experience transmit issue on some platform due to WiFi/BT
3297 * co-exist problem. The possible behaviors are:
3298 * Able to scan and finding all the available AP
3299 * Not able to associate with any AP
3300 * On those platforms, WiFi communication can be restored by set
3301 * "bt_coex_active" module parameter to "false"
3302 *
3303 * default: bt_coex_active = true (BT_COEX_ENABLE)
3304 */
ef33417d 3305static bool bt_coex_active = true;
be663ab6
WYG		 3306module_param(bt_coex_active, bool, S_IRUGO);
3307MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
3308
d2ddf621
SG		 3309u32 il_debug_level;
3310EXPORT_SYMBOL(il_debug_level);
be663ab6 3311
d2ddf621 3312const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
e7392364 3313EXPORT_SYMBOL(il_bcast_addr);
be663ab6 3314
e7392364
SG		 3315#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
3316#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
3317static void
3318il_init_ht_hw_capab(const struct il_priv *il,
3319 struct ieee80211_sta_ht_cap *ht_info,
3320 enum ieee80211_band band)
be663ab6
WYG		 3321{
3322 u16 max_bit_rate = 0;
46bc8d4b
SG		 3323 u8 rx_chains_num = il->hw_params.rx_chains_num;
3324 u8 tx_chains_num = il->hw_params.tx_chains_num;
be663ab6
WYG		 3325
3326 ht_info->cap = 0;
3327 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
3328
3329 ht_info->ht_supported = true;
3330
3331 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
3332 max_bit_rate = MAX_BIT_RATE_20_MHZ;
46bc8d4b 3333 if (il->hw_params.ht40_channel & BIT(band)) {
be663ab6
WYG		 3334 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
3335 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
3336 ht_info->mcs.rx_mask[4] = 0x01;
3337 max_bit_rate = MAX_BIT_RATE_40_MHZ;
3338 }
3339
46bc8d4b 3340 if (il->cfg->mod_params->amsdu_size_8K)
be663ab6
WYG		 3341 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
3342
3343 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3344 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3345
3346 ht_info->mcs.rx_mask[0] = 0xFF;
3347 if (rx_chains_num >= 2)
3348 ht_info->mcs.rx_mask[1] = 0xFF;
3349 if (rx_chains_num >= 3)
3350 ht_info->mcs.rx_mask[2] = 0xFF;
3351
3352 /* Highest supported Rx data rate */
3353 max_bit_rate *= rx_chains_num;
3354 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
3355 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
3356
3357 /* Tx MCS capabilities */
3358 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
3359 if (tx_chains_num != rx_chains_num) {
3360 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
e7392364
SG		 3361 ht_info->mcs.tx_params |=
3362 ((tx_chains_num -
3363 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
be663ab6
WYG		 3364 }
3365}
3366
3367/**
e2ebc833 3368 * il_init_geos - Initialize mac80211's geo/channel info based from eeprom
be663ab6 3369 */
e7392364
SG		 3370int
3371il_init_geos(struct il_priv *il)
be663ab6 3372{
e2ebc833 3373 struct il_channel_info *ch;
be663ab6
WYG		 3374 struct ieee80211_supported_band *sband;
3375 struct ieee80211_channel *channels;
3376 struct ieee80211_channel *geo_ch;
3377 struct ieee80211_rate *rates;
3378 int i = 0;
332704a5 3379 s8 max_tx_power = 0;
be663ab6 3380
46bc8d4b
SG		 3381 if (il->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
3382 il->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
58de00a4 3383 D_INFO("Geography modes already initialized.\n");
a6766ccd 3384 set_bit(S_GEO_CONFIGURED, &il->status);
be663ab6
WYG		 3385 return 0;
3386 }
3387
e7392364
SG		 3388 channels =
3389 kzalloc(sizeof(struct ieee80211_channel) * il->channel_count,
3390 GFP_KERNEL);
be663ab6
WYG		 3391 if (!channels)
3392 return -ENOMEM;
3393
e7392364
SG		 3394 rates =
3395 kzalloc((sizeof(struct ieee80211_rate) * RATE_COUNT_LEGACY),
3396 GFP_KERNEL);
be663ab6
WYG		 3397 if (!rates) {
3398 kfree(channels);
3399 return -ENOMEM;
3400 }
3401
3402 /* 5.2GHz channels start after the 2.4GHz channels */
46bc8d4b 3403 sband = &il->bands[IEEE80211_BAND_5GHZ];
d2ddf621 3404 sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)];
be663ab6 3405 /* just OFDM */
e2ebc833 3406 sband->bitrates = &rates[IL_FIRST_OFDM_RATE];
2eb05816 3407 sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE;
be663ab6 3408
46bc8d4b 3409 if (il->cfg->sku & IL_SKU_N)
e7392364 3410 il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_5GHZ);
be663ab6 3411
46bc8d4b 3412 sband = &il->bands[IEEE80211_BAND_2GHZ];
be663ab6
WYG		 3413 sband->channels = channels;
3414 /* OFDM & CCK */
3415 sband->bitrates = rates;
2eb05816 3416 sband->n_bitrates = RATE_COUNT_LEGACY;
be663ab6 3417
46bc8d4b 3418 if (il->cfg->sku & IL_SKU_N)
e7392364 3419 il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_2GHZ);
be663ab6 3420
46bc8d4b
SG		 3421 il->ieee_channels = channels;
3422 il->ieee_rates = rates;
be663ab6 3423
e7392364 3424 for (i = 0; i < il->channel_count; i++) {
46bc8d4b 3425 ch = &il->channel_info[i];
be663ab6 3426
e2ebc833 3427 if (!il_is_channel_valid(ch))
be663ab6
WYG		 3428 continue;
3429
46bc8d4b 3430 sband = &il->bands[ch->band];
be663ab6
WYG		 3431
3432 geo_ch = &sband->channels[sband->n_channels++];
3433
3434 geo_ch->center_freq =
e7392364 3435 ieee80211_channel_to_frequency(ch->channel, ch->band);
be663ab6
WYG		 3436 geo_ch->max_power = ch->max_power_avg;
3437 geo_ch->max_antenna_gain = 0xff;
3438 geo_ch->hw_value = ch->channel;
3439
e2ebc833 3440 if (il_is_channel_valid(ch)) {
be663ab6
WYG		 3441 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
3442 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
3443
3444 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
3445 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
3446
3447 if (ch->flags & EEPROM_CHANNEL_RADAR)
3448 geo_ch->flags |= IEEE80211_CHAN_RADAR;
3449
3450 geo_ch->flags |= ch->ht40_extension_channel;
3451
332704a5
SG		 3452 if (ch->max_power_avg > max_tx_power)
3453 max_tx_power = ch->max_power_avg;
be663ab6
WYG		 3454 } else {
3455 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
3456 }
3457
e7392364
SG		 3458 D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", ch->channel,
3459 geo_ch->center_freq,
3460 il_is_channel_a_band(ch) ? "5.2" : "2.4",
3461 geo_ch->
3462 flags & IEEE80211_CHAN_DISABLED ? "restricted" : "valid",
3463 geo_ch->flags);
be663ab6
WYG		 3464 }
3465
46bc8d4b
SG		 3466 il->tx_power_device_lmt = max_tx_power;
3467 il->tx_power_user_lmt = max_tx_power;
3468 il->tx_power_next = max_tx_power;
332704a5 3469
232913b5
SG		 3470 if (il->bands[IEEE80211_BAND_5GHZ].n_channels == 0 &&
3471 (il->cfg->sku & IL_SKU_A)) {
9406f797 3472 IL_INFO("Incorrectly detected BG card as ABG. "
be663ab6 3473 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
e7392364 3474 il->pci_dev->device, il->pci_dev->subsystem_device);
46bc8d4b 3475 il->cfg->sku &= ~IL_SKU_A;
be663ab6
WYG		 3476 }
3477
9406f797 3478 IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n",
e7392364
SG		 3479 il->bands[IEEE80211_BAND_2GHZ].n_channels,
3480 il->bands[IEEE80211_BAND_5GHZ].n_channels);
be663ab6 3481
a6766ccd 3482 set_bit(S_GEO_CONFIGURED, &il->status);
be663ab6
WYG		 3483
3484 return 0;
3485}
e2ebc833 3486EXPORT_SYMBOL(il_init_geos);
be663ab6
WYG		 3487
3488/*
e2ebc833 3489 * il_free_geos - undo allocations in il_init_geos
be663ab6 3490 */
e7392364
SG		 3491void
3492il_free_geos(struct il_priv *il)
be663ab6 3493{
46bc8d4b
SG		 3494 kfree(il->ieee_channels);
3495 kfree(il->ieee_rates);
a6766ccd 3496 clear_bit(S_GEO_CONFIGURED, &il->status);
be663ab6 3497}
e2ebc833 3498EXPORT_SYMBOL(il_free_geos);
be663ab6 3499
e7392364
SG		 3500static bool
3501il_is_channel_extension(struct il_priv *il, enum ieee80211_band band,
3502 u16 channel, u8 extension_chan_offset)
be663ab6 3503{
e2ebc833 3504 const struct il_channel_info *ch_info;
be663ab6 3505
46bc8d4b 3506 ch_info = il_get_channel_info(il, band, channel);
e2ebc833 3507 if (!il_is_channel_valid(ch_info))
be663ab6
WYG		 3508 return false;
3509
3510 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
e7392364
SG		 3511 return !(ch_info->
3512 ht40_extension_channel & IEEE80211_CHAN_NO_HT40PLUS);
be663ab6 3513 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
e7392364
SG		 3514 return !(ch_info->
3515 ht40_extension_channel & IEEE80211_CHAN_NO_HT40MINUS);
be663ab6
WYG		 3516
3517 return false;
3518}
3519
e7392364 3520bool
83007196 3521il_is_ht40_tx_allowed(struct il_priv *il, struct ieee80211_sta_ht_cap *ht_cap)
be663ab6 3522{
1c03c462 3523 if (!il->ht.enabled || !il->ht.is_40mhz)
be663ab6
WYG		 3524 return false;
3525
3526 /*
3527 * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
3528 * the bit will not set if it is pure 40MHz case
3529 */
3530 if (ht_cap && !ht_cap->ht_supported)
3531 return false;
3532
d3175167 3533#ifdef CONFIG_IWLEGACY_DEBUGFS
46bc8d4b 3534 if (il->disable_ht40)
be663ab6
WYG		 3535 return false;
3536#endif
3537
46bc8d4b 3538 return il_is_channel_extension(il, il->band,
c8b03958 3539 le16_to_cpu(il->staging.channel),
1c03c462 3540 il->ht.extension_chan_offset);
be663ab6 3541}
e2ebc833 3542EXPORT_SYMBOL(il_is_ht40_tx_allowed);
be663ab6 3543
e7392364
SG		 3544static u16
3545il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
be663ab6
WYG		 3546{
3547 u16 new_val;
3548 u16 beacon_factor;
3549
3550 /*
3551 * If mac80211 hasn't given us a beacon interval, program
3552 * the default into the device.
3553 */
3554 if (!beacon_val)
3555 return DEFAULT_BEACON_INTERVAL;
3556
3557 /*
3558 * If the beacon interval we obtained from the peer
3559 * is too large, we'll have to wake up more often
3560 * (and in IBSS case, we'll beacon too much)
3561 *
3562 * For example, if max_beacon_val is 4096, and the
3563 * requested beacon interval is 7000, we'll have to
3564 * use 3500 to be able to wake up on the beacons.
3565 *
3566 * This could badly influence beacon detection stats.
3567 */
3568
3569 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
3570 new_val = beacon_val / beacon_factor;
3571
3572 if (!new_val)
3573 new_val = max_beacon_val;
3574
3575 return new_val;
3576}
3577
3578int
83007196 3579il_send_rxon_timing(struct il_priv *il)
be663ab6
WYG		 3580{
3581 u64 tsf;
3582 s32 interval_tm, rem;
3583 struct ieee80211_conf *conf = NULL;
3584 u16 beacon_int;
83007196 3585 struct ieee80211_vif *vif = il->vif;
be663ab6 3586
6278ddab 3587 conf = &il->hw->conf;
be663ab6 3588
46bc8d4b 3589 lockdep_assert_held(&il->mutex);
be663ab6 3590
c8b03958 3591 memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd));
be663ab6 3592
c8b03958
SG		 3593 il->timing.timestamp = cpu_to_le64(il->timestamp);
3594 il->timing.listen_interval = cpu_to_le16(conf->listen_interval);
be663ab6
WYG		 3595
3596 beacon_int = vif ? vif->bss_conf.beacon_int : 0;
3597
3598 /*
6ce1dc45 3599 * TODO: For IBSS we need to get atim_win from mac80211,
e7392364 3600 * for now just always use 0
be663ab6 3601 */
c8b03958 3602 il->timing.atim_win = 0;
be663ab6 3603
e7392364
SG		 3604 beacon_int =
3605 il_adjust_beacon_interval(beacon_int,
3606 il->hw_params.max_beacon_itrvl *
3607 TIME_UNIT);
c8b03958 3608 il->timing.beacon_interval = cpu_to_le16(beacon_int);
be663ab6 3609
e7392364 3610 tsf = il->timestamp; /* tsf is modifed by do_div: copy it */
be663ab6
WYG		 3611 interval_tm = beacon_int * TIME_UNIT;
3612 rem = do_div(tsf, interval_tm);
c8b03958 3613 il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
be663ab6 3614
c8b03958 3615 il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1;
be663ab6 3616
e7392364 3617 D_ASSOC("beacon interval %d beacon timer %d beacon tim %d\n",
c8b03958
SG		 3618 le16_to_cpu(il->timing.beacon_interval),
3619 le32_to_cpu(il->timing.beacon_init_val),
3620 le16_to_cpu(il->timing.atim_win));
be663ab6 3621
63d0f0c5 3622 return il_send_cmd_pdu(il, C_RXON_TIMING, sizeof(il->timing),
c8b03958 3623 &il->timing);
be663ab6 3624}
e2ebc833 3625EXPORT_SYMBOL(il_send_rxon_timing);
be663ab6
WYG		 3626
3627void
83007196 3628il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt)
be663ab6 3629{
c8b03958 3630 struct il_rxon_cmd *rxon = &il->staging;
be663ab6
WYG		 3631
3632 if (hw_decrypt)
3633 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
3634 else
3635 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
3636
3637}
e2ebc833 3638EXPORT_SYMBOL(il_set_rxon_hwcrypto);
be663ab6
WYG		 3639
3640/* validate RXON structure is valid */
3641int
83007196 3642il_check_rxon_cmd(struct il_priv *il)
be663ab6 3643{
c8b03958 3644 struct il_rxon_cmd *rxon = &il->staging;
be663ab6
WYG		 3645 bool error = false;
3646
3647 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
3648 if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
9406f797 3649 IL_WARN("check 2.4G: wrong narrow\n");
be663ab6
WYG		 3650 error = true;
3651 }
3652 if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
9406f797 3653 IL_WARN("check 2.4G: wrong radar\n");
be663ab6
WYG		 3654 error = true;
3655 }
3656 } else {
3657 if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
9406f797 3658 IL_WARN("check 5.2G: not short slot!\n");
be663ab6
WYG		 3659 error = true;
3660 }
3661 if (rxon->flags & RXON_FLG_CCK_MSK) {
9406f797 3662 IL_WARN("check 5.2G: CCK!\n");
be663ab6
WYG		 3663 error = true;
3664 }
3665 }
3666 if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
9406f797 3667 IL_WARN("mac/bssid mcast!\n");
be663ab6
WYG		 3668 error = true;
3669 }
3670
3671 /* make sure basic rates 6Mbps and 1Mbps are supported */
2eb05816
SG		 3672 if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 &&
3673 (rxon->cck_basic_rates & RATE_1M_MASK) == 0) {
9406f797 3674 IL_WARN("neither 1 nor 6 are basic\n");
be663ab6
WYG		 3675 error = true;
3676 }
3677
3678 if (le16_to_cpu(rxon->assoc_id) > 2007) {
9406f797 3679 IL_WARN("aid > 2007\n");
be663ab6
WYG		 3680 error = true;
3681 }
3682
e7392364
SG		 3683 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) ==
3684 (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
9406f797 3685 IL_WARN("CCK and short slot\n");
be663ab6
WYG		 3686 error = true;
3687 }
3688
e7392364
SG		 3689 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) ==
3690 (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
9406f797 3691 IL_WARN("CCK and auto detect");
be663ab6
WYG		 3692 error = true;
3693 }
3694
e7392364
SG		 3695 if ((rxon->
3696 flags & (RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK)) ==
3697 RXON_FLG_TGG_PROTECT_MSK) {
9406f797 3698 IL_WARN("TGg but no auto-detect\n");
be663ab6
WYG		 3699 error = true;
3700 }
3701
3702 if (error)
e7392364 3703 IL_WARN("Tuning to channel %d\n", le16_to_cpu(rxon->channel));
be663ab6
WYG		 3704
3705 if (error) {
9406f797 3706 IL_ERR("Invalid RXON\n");
be663ab6
WYG		 3707 return -EINVAL;
3708 }
3709 return 0;
3710}
e2ebc833 3711EXPORT_SYMBOL(il_check_rxon_cmd);
be663ab6
WYG		 3712
3713/**
e2ebc833 3714 * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
46bc8d4b 3715 * @il: staging_rxon is compared to active_rxon
be663ab6
WYG		 3716 *
3717 * If the RXON structure is changing enough to require a new tune,
3718 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
3719 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
3720 */
e7392364 3721int
83007196 3722il_full_rxon_required(struct il_priv *il)
be663ab6 3723{
c8b03958
SG		 3724 const struct il_rxon_cmd *staging = &il->staging;
3725 const struct il_rxon_cmd *active = &il->active;
be663ab6
WYG		 3726
3727#define CHK(cond) \
3728 if ((cond)) { \
58de00a4 3729 D_INFO("need full RXON - " #cond "\n"); \
be663ab6
WYG		 3730 return 1; \
3731 }
3732
3733#define CHK_NEQ(c1, c2) \
3734 if ((c1) != (c2)) { \
58de00a4 3735 D_INFO("need full RXON - " \
be663ab6
WYG		 3736 #c1 " != " #c2 " - %d != %d\n", \
3737 (c1), (c2)); \
3738 return 1; \
3739 }
3740
3741 /* These items are only settable from the full RXON command */
c8b03958 3742 CHK(!il_is_associated(il));
be663ab6
WYG		 3743 CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr));
3744 CHK(compare_ether_addr(staging->node_addr, active->node_addr));
e7392364
SG		 3745 CHK(compare_ether_addr
3746 (staging->wlap_bssid_addr, active->wlap_bssid_addr));
be663ab6
WYG		 3747 CHK_NEQ(staging->dev_type, active->dev_type);
3748 CHK_NEQ(staging->channel, active->channel);
3749 CHK_NEQ(staging->air_propagation, active->air_propagation);
3750 CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
3751 active->ofdm_ht_single_stream_basic_rates);
3752 CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
3753 active->ofdm_ht_dual_stream_basic_rates);
3754 CHK_NEQ(staging->assoc_id, active->assoc_id);
3755
3756 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
3757 * be updated with the RXON_ASSOC command -- however only some
3758 * flag transitions are allowed using RXON_ASSOC */
3759
3760 /* Check if we are not switching bands */
3761 CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
3762 active->flags & RXON_FLG_BAND_24G_MSK);
3763
3764 /* Check if we are switching association toggle */
3765 CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
3766 active->filter_flags & RXON_FILTER_ASSOC_MSK);
3767
3768#undef CHK
3769#undef CHK_NEQ
3770
3771 return 0;
3772}
e2ebc833 3773EXPORT_SYMBOL(il_full_rxon_required);
be663ab6 3774
e7392364 3775u8
83007196 3776il_get_lowest_plcp(struct il_priv *il)
be663ab6
WYG		 3777{
3778 /*
3779 * Assign the lowest rate -- should really get this from
3780 * the beacon skb from mac80211.
3781 */
c8b03958 3782 if (il->staging.flags & RXON_FLG_BAND_24G_MSK)
2eb05816 3783 return RATE_1M_PLCP;
be663ab6 3784 else
2eb05816 3785 return RATE_6M_PLCP;
be663ab6 3786}
e2ebc833 3787EXPORT_SYMBOL(il_get_lowest_plcp);
be663ab6 3788
e7392364 3789static void
83007196 3790_il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
be663ab6 3791{
c8b03958 3792 struct il_rxon_cmd *rxon = &il->staging;
be663ab6 3793
1c03c462 3794 if (!il->ht.enabled) {
e7392364
SG		 3795 rxon->flags &=
3796 ~(RXON_FLG_CHANNEL_MODE_MSK |
3797 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | RXON_FLG_HT40_PROT_MSK
3798 | RXON_FLG_HT_PROT_MSK);
be663ab6
WYG		 3799 return;
3800 }
3801
e7392364 3802 rxon->flags |=
1c03c462 3803 cpu_to_le32(il->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS);
be663ab6
WYG		 3804
3805 /* Set up channel bandwidth:
3806 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
3807 /* clear the HT channel mode before set the mode */
e7392364
SG		 3808 rxon->flags &=
3809 ~(RXON_FLG_CHANNEL_MODE_MSK | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
83007196 3810 if (il_is_ht40_tx_allowed(il, NULL)) {
be663ab6 3811 /* pure ht40 */
1c03c462 3812 if (il->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
be663ab6
WYG		 3813 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
3814 /* Note: control channel is opposite of extension channel */
1c03c462 3815 switch (il->ht.extension_chan_offset) {
be663ab6
WYG		 3816 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3817 rxon->flags &=
e7392364 3818 ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG		 3819 break;
3820 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
e7392364 3821 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG		 3822 break;
3823 }
3824 } else {
3825 /* Note: control channel is opposite of extension channel */
1c03c462 3826 switch (il->ht.extension_chan_offset) {
be663ab6
WYG		 3827 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3828 rxon->flags &=
e7392364 3829 ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
be663ab6
WYG		 3830 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3831 break;
3832 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
e7392364 3833 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG		 3834 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3835 break;
3836 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
3837 default:
3838 /* channel location only valid if in Mixed mode */
e7392364 3839 IL_ERR("invalid extension channel offset\n");
be663ab6
WYG		 3840 break;
3841 }
3842 }
3843 } else {
3844 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
3845 }
3846
c39ae9fd
SG		 3847 if (il->ops->hcmd->set_rxon_chain)
3848 il->ops->hcmd->set_rxon_chain(il);
be663ab6 3849
58de00a4 3850 D_ASSOC("rxon flags 0x%X operation mode :0x%X "
e7392364 3851 "extension channel offset 0x%x\n", le32_to_cpu(rxon->flags),
1c03c462 3852 il->ht.protection, il->ht.extension_chan_offset);
be663ab6
WYG		 3853}
3854
e7392364
SG		 3855void
3856il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
be663ab6 3857{
83007196 3858 _il_set_rxon_ht(il, ht_conf);
be663ab6 3859}
e2ebc833 3860EXPORT_SYMBOL(il_set_rxon_ht);
be663ab6
WYG		 3861
3862/* Return valid, unused, channel for a passive scan to reset the RF */
e7392364
SG		 3863u8
3864il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band)
be663ab6 3865{
e2ebc833 3866 const struct il_channel_info *ch_info;
be663ab6
WYG		 3867 int i;
3868 u8 channel = 0;
3869 u8 min, max;
be663ab6
WYG		 3870
3871 if (band == IEEE80211_BAND_5GHZ) {
3872 min = 14;
46bc8d4b 3873 max = il->channel_count;
be663ab6
WYG		 3874 } else {
3875 min = 0;
3876 max = 14;
3877 }
3878
3879 for (i = min; i < max; i++) {
17d6e557 3880 channel = il->channel_info[i].channel;
c8b03958 3881 if (channel == le16_to_cpu(il->staging.channel))
be663ab6
WYG		 3882 continue;
3883
46bc8d4b 3884 ch_info = il_get_channel_info(il, band, channel);
e2ebc833 3885 if (il_is_channel_valid(ch_info))
be663ab6
WYG		 3886 break;
3887 }
3888
3889 return channel;
3890}
e2ebc833 3891EXPORT_SYMBOL(il_get_single_channel_number);
be663ab6
WYG		 3892
3893/**
e2ebc833 3894 * il_set_rxon_channel - Set the band and channel values in staging RXON
be663ab6
WYG		 3895 * @ch: requested channel as a pointer to struct ieee80211_channel
3896
3897 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
3898 * in the staging RXON flag structure based on the ch->band
3899 */
3900int
83007196 3901il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch)
be663ab6
WYG		 3902{
3903 enum ieee80211_band band = ch->band;
3904 u16 channel = ch->hw_value;
3905
c8b03958 3906 if (le16_to_cpu(il->staging.channel) == channel && il->band == band)
be663ab6
WYG		 3907 return 0;
3908
c8b03958 3909 il->staging.channel = cpu_to_le16(channel);
be663ab6 3910 if (band == IEEE80211_BAND_5GHZ)
c8b03958 3911 il->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
be663ab6 3912 else
c8b03958 3913 il->staging.flags |= RXON_FLG_BAND_24G_MSK;
be663ab6 3914
46bc8d4b 3915 il->band = band;
be663ab6 3916
58de00a4 3917 D_INFO("Staging channel set to %d [%d]\n", channel, band);
be663ab6
WYG		 3918
3919 return 0;
3920}
e2ebc833 3921EXPORT_SYMBOL(il_set_rxon_channel);
be663ab6 3922
e7392364 3923void
83007196
SG		 3924il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band,
3925 struct ieee80211_vif *vif)
be663ab6
WYG		 3926{
3927 if (band == IEEE80211_BAND_5GHZ) {
c8b03958 3928 il->staging.flags &=
e7392364
SG		 3929 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
3930 RXON_FLG_CCK_MSK);
c8b03958 3931 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3932 } else {
e2ebc833 3933 /* Copied from il_post_associate() */
be663ab6 3934 if (vif && vif->bss_conf.use_short_slot)
c8b03958 3935 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3936 else
c8b03958 3937 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3938
c8b03958
SG		 3939 il->staging.flags |= RXON_FLG_BAND_24G_MSK;
3940 il->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
3941 il->staging.flags &= ~RXON_FLG_CCK_MSK;
be663ab6
WYG		 3942 }
3943}
e2ebc833 3944EXPORT_SYMBOL(il_set_flags_for_band);
be663ab6
WYG		 3945
3946/*
3947 * initialize rxon structure with default values from eeprom
3948 */
e7392364 3949void
83007196 3950il_connection_init_rx_config(struct il_priv *il)
be663ab6 3951{
e2ebc833 3952 const struct il_channel_info *ch_info;
be663ab6 3953
c8b03958 3954 memset(&il->staging, 0, sizeof(il->staging));
be663ab6 3955
83007196 3956 if (!il->vif) {
0f8b90f5 3957 il->staging.dev_type = RXON_DEV_TYPE_ESS;
83007196
SG		 3958 } else if (il->vif->type == NL80211_IFTYPE_STATION) {
3959 il->staging.dev_type = RXON_DEV_TYPE_ESS;
3960 il->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
3961 } else if (il->vif->type == NL80211_IFTYPE_ADHOC) {
3962 il->staging.dev_type = RXON_DEV_TYPE_IBSS;
3963 il->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
3964 il->staging.filter_flags =
3965 RXON_FILTER_BCON_AWARE_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
3966 } else {
3967 IL_ERR("Unsupported interface type %d\n", il->vif->type);
3968 return;
3969 }
be663ab6
WYG		 3970
3971#if 0
3972 /* TODO: Figure out when short_preamble would be set and cache from
3973 * that */
46bc8d4b 3974 if (!hw_to_local(il->hw)->short_preamble)
c8b03958 3975 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6 3976 else
c8b03958 3977 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6
WYG		 3978#endif
3979
e7392364 3980 ch_info =
c8b03958 3981 il_get_channel_info(il, il->band, le16_to_cpu(il->active.channel));
be663ab6
WYG		 3982
3983 if (!ch_info)
46bc8d4b 3984 ch_info = &il->channel_info[0];
be663ab6 3985
c8b03958 3986 il->staging.channel = cpu_to_le16(ch_info->channel);
46bc8d4b 3987 il->band = ch_info->band;
be663ab6 3988
83007196 3989 il_set_flags_for_band(il, il->band, il->vif);
be663ab6 3990
c8b03958 3991 il->staging.ofdm_basic_rates =
e2ebc833 3992 (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
c8b03958 3993 il->staging.cck_basic_rates =
e2ebc833 3994 (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
be663ab6
WYG		 3995
3996 /* clear both MIX and PURE40 mode flag */
c8b03958 3997 il->staging.flags &=
e7392364 3998 ~(RXON_FLG_CHANNEL_MODE_MIXED | RXON_FLG_CHANNEL_MODE_PURE_40);
83007196
SG		 3999 if (il->vif)
4000 memcpy(il->staging.node_addr, il->vif->addr, ETH_ALEN);
be663ab6 4001
c8b03958
SG		 4002 il->staging.ofdm_ht_single_stream_basic_rates = 0xff;
4003 il->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
be663ab6 4004}
e2ebc833 4005EXPORT_SYMBOL(il_connection_init_rx_config);
be663ab6 4006
e7392364
SG		 4007void
4008il_set_rate(struct il_priv *il)
be663ab6
WYG		 4009{
4010 const struct ieee80211_supported_band *hw = NULL;
4011 struct ieee80211_rate *rate;
be663ab6
WYG		 4012 int i;
4013
46bc8d4b 4014 hw = il_get_hw_mode(il, il->band);
be663ab6 4015 if (!hw) {
9406f797 4016 IL_ERR("Failed to set rate: unable to get hw mode\n");
be663ab6
WYG		 4017 return;
4018 }
4019
46bc8d4b 4020 il->active_rate = 0;
be663ab6
WYG		 4021
4022 for (i = 0; i < hw->n_bitrates; i++) {
4023 rate = &(hw->bitrates[i]);
2eb05816 4024 if (rate->hw_value < RATE_COUNT_LEGACY)
46bc8d4b 4025 il->active_rate |= (1 << rate->hw_value);
be663ab6
WYG		 4026 }
4027
58de00a4 4028 D_RATE("Set active_rate = %0x\n", il->active_rate);
be663ab6 4029
c8b03958 4030 il->staging.cck_basic_rates =
e7392364 4031 (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
be663ab6 4032
c8b03958 4033 il->staging.ofdm_basic_rates =
e7392364 4034 (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
be663ab6 4035}
e2ebc833 4036EXPORT_SYMBOL(il_set_rate);
be663ab6 4037
e7392364
SG		 4038void
4039il_chswitch_done(struct il_priv *il, bool is_success)
be663ab6 4040{
a6766ccd 4041 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4042 return;
4043
a6766ccd 4044 if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
83007196 4045 ieee80211_chswitch_done(il->vif, is_success);
be663ab6 4046}
e2ebc833 4047EXPORT_SYMBOL(il_chswitch_done);
be663ab6 4048
e7392364
SG		 4049void
4050il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4051{
dcae1c64 4052 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4053 struct il_csa_notification *csa = &(pkt->u.csa_notif);
c8b03958 4054 struct il_rxon_cmd *rxon = (void *)&il->active;
be663ab6 4055
a6766ccd 4056 if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
51e65257
SG		 4057 return;
4058
46bc8d4b 4059 if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) {
51e65257 4060 rxon->channel = csa->channel;
c8b03958 4061 il->staging.channel = csa->channel;
e7392364 4062 D_11H("CSA notif: channel %d\n", le16_to_cpu(csa->channel));
46bc8d4b 4063 il_chswitch_done(il, true);
51e65257 4064 } else {
9406f797 4065 IL_ERR("CSA notif (fail) : channel %d\n",
e7392364 4066 le16_to_cpu(csa->channel));
46bc8d4b 4067 il_chswitch_done(il, false);
be663ab6
WYG		 4068 }
4069}
d2dfb33e 4070EXPORT_SYMBOL(il_hdl_csa);
be663ab6 4071
d3175167 4072#ifdef CONFIG_IWLEGACY_DEBUG
e7392364 4073void
83007196 4074il_print_rx_config_cmd(struct il_priv *il)
be663ab6 4075{
c8b03958 4076 struct il_rxon_cmd *rxon = &il->staging;
be663ab6 4077
58de00a4 4078 D_RADIO("RX CONFIG:\n");
46bc8d4b 4079 il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e7392364 4080 D_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
58de00a4 4081 D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
e7392364 4082 D_RADIO("u32 filter_flags: 0x%08x\n", le32_to_cpu(rxon->filter_flags));
58de00a4 4083 D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
e7392364
SG		 4084 D_RADIO("u8 ofdm_basic_rates: 0x%02x\n", rxon->ofdm_basic_rates);
4085 D_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
58de00a4
SG		 4086 D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
4087 D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
e7392364 4088 D_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
be663ab6 4089}
e2ebc833 4090EXPORT_SYMBOL(il_print_rx_config_cmd);
be663ab6
WYG		 4091#endif
4092/**
e2ebc833 4093 * il_irq_handle_error - called for HW or SW error interrupt from card
be663ab6 4094 */
e7392364
SG		 4095void
4096il_irq_handle_error(struct il_priv *il)
be663ab6 4097{
e2ebc833 4098 /* Set the FW error flag -- cleared on il_down */
a6766ccd 4099 set_bit(S_FW_ERROR, &il->status);
be663ab6
WYG		 4100
4101 /* Cancel currently queued command. */
a6766ccd 4102 clear_bit(S_HCMD_ACTIVE, &il->status);
be663ab6 4103
e7392364 4104 IL_ERR("Loaded firmware version: %s\n", il->hw->wiphy->fw_version);
be663ab6 4105
c39ae9fd
SG		 4106 il->ops->lib->dump_nic_error_log(il);
4107 if (il->ops->lib->dump_fh)
4108 il->ops->lib->dump_fh(il, NULL, false);
d3175167 4109#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4110 if (il_get_debug_level(il) & IL_DL_FW_ERRORS)
83007196 4111 il_print_rx_config_cmd(il);
be663ab6
WYG		 4112#endif
4113
46bc8d4b 4114 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4115
4116 /* Keep the restart process from trying to send host
4117 * commands by clearing the INIT status bit */
a6766ccd 4118 clear_bit(S_READY, &il->status);
be663ab6 4119
a6766ccd 4120 if (!test_bit(S_EXIT_PENDING, &il->status)) {
58de00a4 4121 IL_DBG(IL_DL_FW_ERRORS,
e7392364 4122 "Restarting adapter due to uCode error.\n");
be663ab6 4123
46bc8d4b
SG		 4124 if (il->cfg->mod_params->restart_fw)
4125 queue_work(il->workqueue, &il->restart);
be663ab6
WYG		 4126 }
4127}
e2ebc833 4128EXPORT_SYMBOL(il_irq_handle_error);
be663ab6 4129
e7392364
SG		 4130static int
4131il_apm_stop_master(struct il_priv *il)
be663ab6
WYG		 4132{
4133 int ret = 0;
4134
4135 /* stop device's busmaster DMA activity */
46bc8d4b 4136 il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
be663ab6 4137
e7392364
SG		 4138 ret =
4139 _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
4140 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
be663ab6 4141 if (ret)
9406f797 4142 IL_WARN("Master Disable Timed Out, 100 usec\n");
be663ab6 4143
58de00a4 4144 D_INFO("stop master\n");
be663ab6
WYG		 4145
4146 return ret;
4147}
4148
e7392364
SG		 4149void
4150il_apm_stop(struct il_priv *il)
be663ab6 4151{
58de00a4 4152 D_INFO("Stop card, put in low power state\n");
be663ab6
WYG		 4153
4154 /* Stop device's DMA activity */
46bc8d4b 4155 il_apm_stop_master(il);
be663ab6
WYG		 4156
4157 /* Reset the entire device */
46bc8d4b 4158 il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
be663ab6
WYG		 4159
4160 udelay(10);
4161
4162 /*
4163 * Clear "initialization complete" bit to move adapter from
4164 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
4165 */
e7392364 4166 il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
be663ab6 4167}
e7392364 4168EXPORT_SYMBOL(il_apm_stop);
be663ab6
WYG		 4169
4170/*
4171 * Start up NIC's basic functionality after it has been reset
e2ebc833 4172 * (e.g. after platform boot, or shutdown via il_apm_stop())
be663ab6
WYG		 4173 * NOTE: This does not load uCode nor start the embedded processor
4174 */
e7392364
SG		 4175int
4176il_apm_init(struct il_priv *il)
be663ab6
WYG		 4177{
4178 int ret = 0;
4179 u16 lctl;
4180
58de00a4 4181 D_INFO("Init card's basic functions\n");
be663ab6
WYG		 4182
4183 /*
4184 * Use "set_bit" below rather than "write", to preserve any hardware
4185 * bits already set by default after reset.
4186 */
4187
4188 /* Disable L0S exit timer (platform NMI Work/Around) */
46bc8d4b 4189 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
e7392364 4190 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
be663ab6
WYG		 4191
4192 /*
4193 * Disable L0s without affecting L1;
4194 * don't wait for ICH L0s (ICH bug W/A)
4195 */
46bc8d4b 4196 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
e7392364 4197 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
be663ab6
WYG		 4198
4199 /* Set FH wait threshold to maximum (HW error during stress W/A) */
e7392364 4200 il_set_bit(il, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
be663ab6
WYG		 4201
4202 /*
4203 * Enable HAP INTA (interrupt from management bus) to
4204 * wake device's PCI Express link L1a -> L0s
25985edc 4205 * NOTE: This is no-op for 3945 (non-existent bit)
be663ab6 4206 */
46bc8d4b 4207 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 4208 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
be663ab6
WYG		 4209
4210 /*
4211 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
4212 * Check if BIOS (or OS) enabled L1-ASPM on this device.
4213 * If so (likely), disable L0S, so device moves directly L0->L1;
4214 * costs negligible amount of power savings.
4215 * If not (unlikely), enable L0S, so there is at least some
4216 * power savings, even without L1.
4217 */
89ef1ed2 4218 if (il->cfg->set_l0s) {
46bc8d4b 4219 lctl = il_pcie_link_ctl(il);
be663ab6 4220 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
e7392364 4221 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
be663ab6 4222 /* L1-ASPM enabled; disable(!) L0S */
46bc8d4b 4223 il_set_bit(il, CSR_GIO_REG,
e7392364 4224 CSR_GIO_REG_VAL_L0S_ENABLED);
58de00a4 4225 D_POWER("L1 Enabled; Disabling L0S\n");
be663ab6
WYG		 4226 } else {
4227 /* L1-ASPM disabled; enable(!) L0S */
46bc8d4b 4228 il_clear_bit(il, CSR_GIO_REG,
e7392364 4229 CSR_GIO_REG_VAL_L0S_ENABLED);
58de00a4 4230 D_POWER("L1 Disabled; Enabling L0S\n");
be663ab6
WYG		 4231 }
4232 }
4233
4234 /* Configure analog phase-lock-loop before activating to D0A */
89ef1ed2 4235 if (il->cfg->pll_cfg_val)
46bc8d4b 4236 il_set_bit(il, CSR_ANA_PLL_CFG,
89ef1ed2 4237 il->cfg->pll_cfg_val);
be663ab6
WYG		 4238
4239 /*
4240 * Set "initialization complete" bit to move adapter from
4241 * D0U* --> D0A* (powered-up active) state.
4242 */
46bc8d4b 4243 il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
be663ab6
WYG		 4244
4245 /*
4246 * Wait for clock stabilization; once stabilized, access to
db54eb57 4247 * device-internal resources is supported, e.g. il_wr_prph()
be663ab6
WYG		 4248 * and accesses to uCode SRAM.
4249 */
e7392364
SG		 4250 ret =
4251 _il_poll_bit(il, CSR_GP_CNTRL,
4252 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
4253 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
be663ab6 4254 if (ret < 0) {
58de00a4 4255 D_INFO("Failed to init the card\n");
be663ab6
WYG		 4256 goto out;
4257 }
4258
4259 /*
4260 * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
4261 * BSM (Boostrap State Machine) is only in 3945 and 4965.
4262 *
4263 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
4264 * do not disable clocks. This preserves any hardware bits already
4265 * set by default in "CLK_CTRL_REG" after reset.
4266 */
89ef1ed2 4267 if (il->cfg->use_bsm)
db54eb57 4268 il_wr_prph(il, APMG_CLK_EN_REG,
e7392364 4269 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
be663ab6 4270 else
e7392364 4271 il_wr_prph(il, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
be663ab6
WYG		 4272 udelay(20);
4273
4274 /* Disable L1-Active */
46bc8d4b 4275 il_set_bits_prph(il, APMG_PCIDEV_STT_REG,
e7392364 4276 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
be663ab6
WYG		 4277
4278out:
4279 return ret;
4280}
e7392364 4281EXPORT_SYMBOL(il_apm_init);
be663ab6 4282
e7392364
SG		 4283int
4284il_set_tx_power(struct il_priv *il, s8 tx_power, bool force)
be663ab6
WYG		 4285{
4286 int ret;
4287 s8 prev_tx_power;
43f12d47 4288 bool defer;
be663ab6 4289
46bc8d4b 4290 lockdep_assert_held(&il->mutex);
be663ab6 4291
46bc8d4b 4292 if (il->tx_power_user_lmt == tx_power && !force)
be663ab6
WYG		 4293 return 0;
4294
c39ae9fd 4295 if (!il->ops->lib->send_tx_power)
be663ab6
WYG		 4296 return -EOPNOTSUPP;
4297
332704a5
SG		 4298 /* 0 dBm mean 1 milliwatt */
4299 if (tx_power < 0) {
e7392364 4300 IL_WARN("Requested user TXPOWER %d below 1 mW.\n", tx_power);
be663ab6
WYG		 4301 return -EINVAL;
4302 }
4303
46bc8d4b 4304 if (tx_power > il->tx_power_device_lmt) {
e7392364
SG		 4305 IL_WARN("Requested user TXPOWER %d above upper limit %d.\n",
4306 tx_power, il->tx_power_device_lmt);
be663ab6
WYG		 4307 return -EINVAL;
4308 }
4309
46bc8d4b 4310 if (!il_is_ready_rf(il))
be663ab6
WYG		 4311 return -EIO;
4312
43f12d47
SG		 4313 /* scan complete and commit_rxon use tx_power_next value,
4314 * it always need to be updated for newest request */
46bc8d4b 4315 il->tx_power_next = tx_power;
43f12d47
SG		 4316
4317 /* do not set tx power when scanning or channel changing */
a6766ccd 4318 defer = test_bit(S_SCANNING, &il->status) ||
c8b03958 4319 memcmp(&il->active, &il->staging, sizeof(il->staging));
43f12d47 4320 if (defer && !force) {
58de00a4 4321 D_INFO("Deferring tx power set\n");
be663ab6
WYG		 4322 return 0;
4323 }
4324
46bc8d4b
SG		 4325 prev_tx_power = il->tx_power_user_lmt;
4326 il->tx_power_user_lmt = tx_power;
be663ab6 4327
c39ae9fd 4328 ret = il->ops->lib->send_tx_power(il);
be663ab6
WYG		 4329
4330 /* if fail to set tx_power, restore the orig. tx power */
4331 if (ret) {
46bc8d4b
SG		 4332 il->tx_power_user_lmt = prev_tx_power;
4333 il->tx_power_next = prev_tx_power;
be663ab6
WYG		 4334 }
4335 return ret;
4336}
e2ebc833 4337EXPORT_SYMBOL(il_set_tx_power);
be663ab6 4338
e7392364
SG		 4339void
4340il_send_bt_config(struct il_priv *il)
be663ab6 4341{
e2ebc833 4342 struct il_bt_cmd bt_cmd = {
be663ab6
WYG		 4343 .lead_time = BT_LEAD_TIME_DEF,
4344 .max_kill = BT_MAX_KILL_DEF,
4345 .kill_ack_mask = 0,
4346 .kill_cts_mask = 0,
4347 };
4348
4349 if (!bt_coex_active)
4350 bt_cmd.flags = BT_COEX_DISABLE;
4351 else
4352 bt_cmd.flags = BT_COEX_ENABLE;
4353
58de00a4 4354 D_INFO("BT coex %s\n",
e7392364 4355 (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
be663ab6 4356
e7392364 4357 if (il_send_cmd_pdu(il, C_BT_CONFIG, sizeof(struct il_bt_cmd), &bt_cmd))
9406f797 4358 IL_ERR("failed to send BT Coex Config\n");
be663ab6 4359}
e2ebc833 4360EXPORT_SYMBOL(il_send_bt_config);
be663ab6 4361
e7392364
SG		 4362int
4363il_send_stats_request(struct il_priv *il, u8 flags, bool clear)
be663ab6 4364{
ebf0d90d 4365 struct il_stats_cmd stats_cmd = {
e7392364 4366 .configuration_flags = clear ? IL_STATS_CONF_CLEAR_STATS : 0,
be663ab6
WYG		 4367 };
4368
4369 if (flags & CMD_ASYNC)
e7392364
SG		 4370 return il_send_cmd_pdu_async(il, C_STATS, sizeof(struct il_stats_cmd),
4371 &stats_cmd, NULL);
be663ab6 4372 else
e7392364
SG		 4373 return il_send_cmd_pdu(il, C_STATS, sizeof(struct il_stats_cmd),
4374 &stats_cmd);
be663ab6 4375}
ebf0d90d 4376EXPORT_SYMBOL(il_send_stats_request);
be663ab6 4377
e7392364
SG		 4378void
4379il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4380{
d3175167 4381#ifdef CONFIG_IWLEGACY_DEBUG
dcae1c64 4382 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4383 struct il_sleep_notification *sleep = &(pkt->u.sleep_notif);
58de00a4 4384 D_RX("sleep mode: %d, src: %d\n",
1722f8e1 4385 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
be663ab6
WYG		 4386#endif
4387}
d2dfb33e 4388EXPORT_SYMBOL(il_hdl_pm_sleep);
be663ab6 4389
e7392364
SG		 4390void
4391il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4392{
dcae1c64 4393 struct il_rx_pkt *pkt = rxb_addr(rxb);
e94a4099 4394 u32 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
e7392364
SG		 4395 D_RADIO("Dumping %d bytes of unhandled notification for %s:\n", len,
4396 il_get_cmd_string(pkt->hdr.cmd));
46bc8d4b 4397 il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len);
be663ab6 4398}
d2dfb33e 4399EXPORT_SYMBOL(il_hdl_pm_debug_stats);
be663ab6 4400
e7392364
SG		 4401void
4402il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4403{
dcae1c64 4404 struct il_rx_pkt *pkt = rxb_addr(rxb);
be663ab6 4405
9406f797 4406 IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) "
e7392364
SG		 4407 "seq 0x%04X ser 0x%08X\n",
4408 le32_to_cpu(pkt->u.err_resp.error_type),
4409 il_get_cmd_string(pkt->u.err_resp.cmd_id),
4410 pkt->u.err_resp.cmd_id,
4411 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
4412 le32_to_cpu(pkt->u.err_resp.error_info));
be663ab6 4413}
6e9848b4 4414EXPORT_SYMBOL(il_hdl_error);
be663ab6 4415
e7392364
SG		 4416void
4417il_clear_isr_stats(struct il_priv *il)
be663ab6 4418{
46bc8d4b 4419 memset(&il->isr_stats, 0, sizeof(il->isr_stats));
be663ab6
WYG		 4420}
4421
e7392364
SG		 4422int
4423il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
4424 const struct ieee80211_tx_queue_params *params)
be663ab6 4425{
46bc8d4b 4426 struct il_priv *il = hw->priv;
be663ab6
WYG		 4427 unsigned long flags;
4428 int q;
4429
58de00a4 4430 D_MAC80211("enter\n");
be663ab6 4431
46bc8d4b 4432 if (!il_is_ready_rf(il)) {
58de00a4 4433 D_MAC80211("leave - RF not ready\n");
be663ab6
WYG		 4434 return -EIO;
4435 }
4436
4437 if (queue >= AC_NUM) {
58de00a4 4438 D_MAC80211("leave - queue >= AC_NUM %d\n", queue);
be663ab6
WYG		 4439 return 0;
4440 }
4441
4442 q = AC_NUM - 1 - queue;
4443
46bc8d4b 4444 spin_lock_irqsave(&il->lock, flags);
be663ab6 4445
8d44f2bd 4446 il->qos_data.def_qos_parm.ac[q].cw_min =
e7392364 4447 cpu_to_le16(params->cw_min);
8d44f2bd 4448 il->qos_data.def_qos_parm.ac[q].cw_max =
e7392364 4449 cpu_to_le16(params->cw_max);
8d44f2bd
SG		 4450 il->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
4451 il->qos_data.def_qos_parm.ac[q].edca_txop =
e7392364 4452 cpu_to_le16((params->txop * 32));
be663ab6 4453
8d44f2bd 4454 il->qos_data.def_qos_parm.ac[q].reserved1 = 0;
be663ab6 4455
46bc8d4b 4456 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 4457
58de00a4 4458 D_MAC80211("leave\n");
be663ab6
WYG		 4459 return 0;
4460}
e2ebc833 4461EXPORT_SYMBOL(il_mac_conf_tx);
be663ab6 4462
e7392364
SG		 4463int
4464il_mac_tx_last_beacon(struct ieee80211_hw *hw)
be663ab6 4465{
46bc8d4b 4466 struct il_priv *il = hw->priv;
be663ab6 4467
46bc8d4b 4468 return il->ibss_manager == IL_IBSS_MANAGER;
be663ab6 4469}
e2ebc833 4470EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon);
be663ab6
WYG		 4471
4472static int
83007196 4473il_set_mode(struct il_priv *il)
be663ab6 4474{
83007196 4475 il_connection_init_rx_config(il);
be663ab6 4476
c39ae9fd
SG		 4477 if (il->ops->hcmd->set_rxon_chain)
4478 il->ops->hcmd->set_rxon_chain(il);
be663ab6 4479
83007196 4480 return il_commit_rxon(il);
be663ab6
WYG		 4481}
4482
be663ab6 4483int
e2ebc833 4484il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 4485{
46bc8d4b 4486 struct il_priv *il = hw->priv;
be663ab6
WYG		 4487 int err;
4488
e7392364 4489 D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
be663ab6 4490
46bc8d4b 4491 mutex_lock(&il->mutex);
be663ab6 4492
46bc8d4b 4493 if (!il_is_ready_rf(il)) {
9406f797 4494 IL_WARN("Try to add interface when device not ready\n");
be663ab6
WYG		 4495 err = -EINVAL;
4496 goto out;
4497 }
4498
83007196 4499 if (il->vif) {
be663ab6
WYG		 4500 err = -EOPNOTSUPP;
4501 goto out;
4502 }
4503
83007196 4504 il->vif = vif;
20c47eba 4505 il->iw_mode = vif->type;
be663ab6 4506
83007196 4507 err = il_set_mode(il);
17d6e557 4508 if (err) {
83007196 4509 il->vif = NULL;
17d6e557
SG		 4510 il->iw_mode = NL80211_IFTYPE_STATION;
4511 }
be663ab6 4512
e7392364 4513out:
46bc8d4b 4514 mutex_unlock(&il->mutex);
be663ab6 4515
58de00a4 4516 D_MAC80211("leave\n");
be663ab6
WYG		 4517 return err;
4518}
e2ebc833 4519EXPORT_SYMBOL(il_mac_add_interface);
be663ab6 4520
e7392364
SG		 4521static void
4522il_teardown_interface(struct il_priv *il, struct ieee80211_vif *vif,
4523 bool mode_change)
be663ab6 4524{
46bc8d4b 4525 lockdep_assert_held(&il->mutex);
be663ab6 4526
46bc8d4b
SG		 4527 if (il->scan_vif == vif) {
4528 il_scan_cancel_timeout(il, 200);
4529 il_force_scan_end(il);
be663ab6
WYG		 4530 }
4531
dee9a09e 4532 if (!mode_change)
83007196 4533 il_set_mode(il);
dee9a09e 4534
be663ab6
WYG		 4535}
4536
e7392364
SG		 4537void
4538il_mac_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 4539{
46bc8d4b 4540 struct il_priv *il = hw->priv;
be663ab6 4541
58de00a4 4542 D_MAC80211("enter\n");
be663ab6 4543
46bc8d4b 4544 mutex_lock(&il->mutex);
be663ab6 4545
83007196
SG		 4546 WARN_ON(il->vif != vif);
4547 il->vif = NULL;
be663ab6 4548
46bc8d4b 4549 il_teardown_interface(il, vif, false);
be663ab6 4550
46bc8d4b
SG		 4551 memset(il->bssid, 0, ETH_ALEN);
4552 mutex_unlock(&il->mutex);
be663ab6 4553
58de00a4 4554 D_MAC80211("leave\n");
be663ab6
WYG		 4555
4556}
e2ebc833 4557EXPORT_SYMBOL(il_mac_remove_interface);
be663ab6 4558
e7392364
SG		 4559int
4560il_alloc_txq_mem(struct il_priv *il)
be663ab6 4561{
46bc8d4b 4562 if (!il->txq)
e7392364
SG		 4563 il->txq =
4564 kzalloc(sizeof(struct il_tx_queue) *
89ef1ed2 4565 il->cfg->num_of_queues, GFP_KERNEL);
46bc8d4b 4566 if (!il->txq) {
9406f797 4567 IL_ERR("Not enough memory for txq\n");
be663ab6
WYG		 4568 return -ENOMEM;
4569 }
4570 return 0;
4571}
e2ebc833 4572EXPORT_SYMBOL(il_alloc_txq_mem);
be663ab6 4573
e7392364
SG		 4574void
4575il_txq_mem(struct il_priv *il)
be663ab6 4576{
46bc8d4b
SG		 4577 kfree(il->txq);
4578 il->txq = NULL;
be663ab6 4579}
e2ebc833 4580EXPORT_SYMBOL(il_txq_mem);
be663ab6 4581
d3175167 4582#ifdef CONFIG_IWLEGACY_DEBUGFS
be663ab6 4583
e2ebc833 4584#define IL_TRAFFIC_DUMP_SIZE (IL_TRAFFIC_ENTRY_SIZE * IL_TRAFFIC_ENTRIES)
be663ab6 4585
e7392364
SG		 4586void
4587il_reset_traffic_log(struct il_priv *il)
be663ab6 4588{
46bc8d4b
SG		 4589 il->tx_traffic_idx = 0;
4590 il->rx_traffic_idx = 0;
4591 if (il->tx_traffic)
4592 memset(il->tx_traffic, 0, IL_TRAFFIC_DUMP_SIZE);
4593 if (il->rx_traffic)
4594 memset(il->rx_traffic, 0, IL_TRAFFIC_DUMP_SIZE);
be663ab6
WYG		 4595}
4596
e7392364
SG		 4597int
4598il_alloc_traffic_mem(struct il_priv *il)
be663ab6 4599{
e2ebc833 4600 u32 traffic_size = IL_TRAFFIC_DUMP_SIZE;
be663ab6 4601
d2ddf621 4602 if (il_debug_level & IL_DL_TX) {
46bc8d4b 4603 if (!il->tx_traffic) {
e7392364 4604 il->tx_traffic = kzalloc(traffic_size, GFP_KERNEL);
46bc8d4b 4605 if (!il->tx_traffic)
be663ab6
WYG		 4606 return -ENOMEM;
4607 }
4608 }
d2ddf621 4609 if (il_debug_level & IL_DL_RX) {
46bc8d4b 4610 if (!il->rx_traffic) {
e7392364 4611 il->rx_traffic = kzalloc(traffic_size, GFP_KERNEL);
46bc8d4b 4612 if (!il->rx_traffic)
be663ab6
WYG		 4613 return -ENOMEM;
4614 }
4615 }
46bc8d4b 4616 il_reset_traffic_log(il);
be663ab6
WYG		 4617 return 0;
4618}
e2ebc833 4619EXPORT_SYMBOL(il_alloc_traffic_mem);
be663ab6 4620
e7392364
SG		 4621void
4622il_free_traffic_mem(struct il_priv *il)
be663ab6 4623{
46bc8d4b
SG		 4624 kfree(il->tx_traffic);
4625 il->tx_traffic = NULL;
be663ab6 4626
46bc8d4b
SG		 4627 kfree(il->rx_traffic);
4628 il->rx_traffic = NULL;
be663ab6 4629}
e2ebc833 4630EXPORT_SYMBOL(il_free_traffic_mem);
be663ab6 4631
e7392364
SG		 4632void
4633il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
4634 struct ieee80211_hdr *header)
be663ab6
WYG		 4635{
4636 __le16 fc;
4637 u16 len;
4638
d2ddf621 4639 if (likely(!(il_debug_level & IL_DL_TX)))
be663ab6
WYG		 4640 return;
4641
46bc8d4b 4642 if (!il->tx_traffic)
be663ab6
WYG		 4643 return;
4644
4645 fc = header->frame_control;
4646 if (ieee80211_is_data(fc)) {
e7392364
SG		 4647 len =
4648 (length >
4649 IL_TRAFFIC_ENTRY_SIZE) ? IL_TRAFFIC_ENTRY_SIZE : length;
46bc8d4b 4650 memcpy((il->tx_traffic +
e7392364
SG		 4651 (il->tx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)), header,
4652 len);
46bc8d4b 4653 il->tx_traffic_idx =
e7392364 4654 (il->tx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES;
be663ab6
WYG		 4655 }
4656}
e2ebc833 4657EXPORT_SYMBOL(il_dbg_log_tx_data_frame);
be663ab6 4658
e7392364
SG		 4659void
4660il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
4661 struct ieee80211_hdr *header)
be663ab6
WYG		 4662{
4663 __le16 fc;
4664 u16 len;
4665
d2ddf621 4666 if (likely(!(il_debug_level & IL_DL_RX)))
be663ab6
WYG		 4667 return;
4668
46bc8d4b 4669 if (!il->rx_traffic)
be663ab6
WYG		 4670 return;
4671
4672 fc = header->frame_control;
4673 if (ieee80211_is_data(fc)) {
e7392364
SG		 4674 len =
4675 (length >
4676 IL_TRAFFIC_ENTRY_SIZE) ? IL_TRAFFIC_ENTRY_SIZE : length;
46bc8d4b 4677 memcpy((il->rx_traffic +
e7392364
SG		 4678 (il->rx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)), header,
4679 len);
46bc8d4b 4680 il->rx_traffic_idx =
e7392364 4681 (il->rx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES;
be663ab6
WYG		 4682 }
4683}
e2ebc833 4684EXPORT_SYMBOL(il_dbg_log_rx_data_frame);
be663ab6 4685
e7392364
SG		 4686const char *
4687il_get_mgmt_string(int cmd)
be663ab6
WYG		 4688{
4689 switch (cmd) {
e2ebc833
SG		 4690 IL_CMD(MANAGEMENT_ASSOC_REQ);
4691 IL_CMD(MANAGEMENT_ASSOC_RESP);
4692 IL_CMD(MANAGEMENT_REASSOC_REQ);
4693 IL_CMD(MANAGEMENT_REASSOC_RESP);
4694 IL_CMD(MANAGEMENT_PROBE_REQ);
4695 IL_CMD(MANAGEMENT_PROBE_RESP);
4696 IL_CMD(MANAGEMENT_BEACON);
4697 IL_CMD(MANAGEMENT_ATIM);
4698 IL_CMD(MANAGEMENT_DISASSOC);
4699 IL_CMD(MANAGEMENT_AUTH);
4700 IL_CMD(MANAGEMENT_DEAUTH);
4701 IL_CMD(MANAGEMENT_ACTION);
be663ab6
WYG		 4702 default:
4703 return "UNKNOWN";
4704
4705 }
4706}
4707
e7392364
SG		 4708const char *
4709il_get_ctrl_string(int cmd)
be663ab6
WYG		 4710{
4711 switch (cmd) {
e2ebc833
SG		 4712 IL_CMD(CONTROL_BACK_REQ);
4713 IL_CMD(CONTROL_BACK);
4714 IL_CMD(CONTROL_PSPOLL);
4715 IL_CMD(CONTROL_RTS);
4716 IL_CMD(CONTROL_CTS);
4717 IL_CMD(CONTROL_ACK);
4718 IL_CMD(CONTROL_CFEND);
4719 IL_CMD(CONTROL_CFENDACK);
be663ab6
WYG		 4720 default:
4721 return "UNKNOWN";
4722
4723 }
4724}
4725
e7392364
SG		 4726void
4727il_clear_traffic_stats(struct il_priv *il)
be663ab6 4728{
46bc8d4b
SG		 4729 memset(&il->tx_stats, 0, sizeof(struct traffic_stats));
4730 memset(&il->rx_stats, 0, sizeof(struct traffic_stats));
be663ab6
WYG		 4731}
4732
4733/*
d3175167 4734 * if CONFIG_IWLEGACY_DEBUGFS defined,
e2ebc833 4735 * il_update_stats function will
be663ab6 4736 * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass
ebf0d90d 4737 * Use debugFs to display the rx/rx_stats
d3175167 4738 * if CONFIG_IWLEGACY_DEBUGFS not being defined, then no MGMT and CTRL
be663ab6 4739 * information will be recorded, but DATA pkt still will be recorded
e2ebc833 4740 * for the reason of il_led.c need to control the led blinking based on
be663ab6
WYG		 4741 * number of tx and rx data.
4742 *
4743 */
4744void
46bc8d4b 4745il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
be663ab6 4746{
e7392364 4747 struct traffic_stats *stats;
be663ab6
WYG		 4748
4749 if (is_tx)
46bc8d4b 4750 stats = &il->tx_stats;
be663ab6 4751 else
46bc8d4b 4752 stats = &il->rx_stats;
be663ab6
WYG		 4753
4754 if (ieee80211_is_mgmt(fc)) {
4755 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
4756 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
4757 stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
4758 break;
4759 case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
4760 stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
4761 break;
4762 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
4763 stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
4764 break;
4765 case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
4766 stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
4767 break;
4768 case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
4769 stats->mgmt[MANAGEMENT_PROBE_REQ]++;
4770 break;
4771 case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
4772 stats->mgmt[MANAGEMENT_PROBE_RESP]++;
4773 break;
4774 case cpu_to_le16(IEEE80211_STYPE_BEACON):
4775 stats->mgmt[MANAGEMENT_BEACON]++;
4776 break;
4777 case cpu_to_le16(IEEE80211_STYPE_ATIM):
4778 stats->mgmt[MANAGEMENT_ATIM]++;
4779 break;
4780 case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
4781 stats->mgmt[MANAGEMENT_DISASSOC]++;
4782 break;
4783 case cpu_to_le16(IEEE80211_STYPE_AUTH):
4784 stats->mgmt[MANAGEMENT_AUTH]++;
4785 break;
4786 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
4787 stats->mgmt[MANAGEMENT_DEAUTH]++;
4788 break;
4789 case cpu_to_le16(IEEE80211_STYPE_ACTION):
4790 stats->mgmt[MANAGEMENT_ACTION]++;
4791 break;
4792 }
4793 } else if (ieee80211_is_ctl(fc)) {
4794 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
4795 case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
4796 stats->ctrl[CONTROL_BACK_REQ]++;
4797 break;
4798 case cpu_to_le16(IEEE80211_STYPE_BACK):
4799 stats->ctrl[CONTROL_BACK]++;
4800 break;
4801 case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
4802 stats->ctrl[CONTROL_PSPOLL]++;
4803 break;
4804 case cpu_to_le16(IEEE80211_STYPE_RTS):
4805 stats->ctrl[CONTROL_RTS]++;
4806 break;
4807 case cpu_to_le16(IEEE80211_STYPE_CTS):
4808 stats->ctrl[CONTROL_CTS]++;
4809 break;
4810 case cpu_to_le16(IEEE80211_STYPE_ACK):
4811 stats->ctrl[CONTROL_ACK]++;
4812 break;
4813 case cpu_to_le16(IEEE80211_STYPE_CFEND):
4814 stats->ctrl[CONTROL_CFEND]++;
4815 break;
4816 case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
4817 stats->ctrl[CONTROL_CFENDACK]++;
4818 break;
4819 }
4820 } else {
4821 /* data */
4822 stats->data_cnt++;
4823 stats->data_bytes += len;
4824 }
4825}
e2ebc833 4826EXPORT_SYMBOL(il_update_stats);
be663ab6
WYG		 4827#endif
4828
e7392364
SG		 4829int
4830il_force_reset(struct il_priv *il, bool external)
be663ab6 4831{
e2ebc833 4832 struct il_force_reset *force_reset;
be663ab6 4833
a6766ccd 4834 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4835 return -EINVAL;
4836
46bc8d4b 4837 force_reset = &il->force_reset;
be663ab6
WYG		 4838 force_reset->reset_request_count++;
4839 if (!external) {
4840 if (force_reset->last_force_reset_jiffies &&
4841 time_after(force_reset->last_force_reset_jiffies +
e7392364 4842 force_reset->reset_duration, jiffies)) {
58de00a4 4843 D_INFO("force reset rejected\n");
be663ab6
WYG		 4844 force_reset->reset_reject_count++;
4845 return -EAGAIN;
4846 }
4847 }
4848 force_reset->reset_success_count++;
4849 force_reset->last_force_reset_jiffies = jiffies;
dd6d2a8a
SG		 4850
4851 /*
4852 * if the request is from external(ex: debugfs),
4853 * then always perform the request in regardless the module
4854 * parameter setting
4855 * if the request is from internal (uCode error or driver
4856 * detect failure), then fw_restart module parameter
4857 * need to be check before performing firmware reload
4858 */
4859
46bc8d4b 4860 if (!external && !il->cfg->mod_params->restart_fw) {
58de00a4 4861 D_INFO("Cancel firmware reload based on "
e7392364 4862 "module parameter setting\n");
dd6d2a8a 4863 return 0;
be663ab6 4864 }
dd6d2a8a 4865
9406f797 4866 IL_ERR("On demand firmware reload\n");
dd6d2a8a 4867
e2ebc833 4868 /* Set the FW error flag -- cleared on il_down */
a6766ccd 4869 set_bit(S_FW_ERROR, &il->status);
46bc8d4b 4870 wake_up(&il->wait_command_queue);
dd6d2a8a
SG		 4871 /*
4872 * Keep the restart process from trying to send host
4873 * commands by clearing the INIT status bit
4874 */
a6766ccd 4875 clear_bit(S_READY, &il->status);
46bc8d4b 4876 queue_work(il->workqueue, &il->restart);
dd6d2a8a 4877
be663ab6
WYG		 4878 return 0;
4879}
4880
4881int
e7392364 4882il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
be663ab6
WYG		 4883 enum nl80211_iftype newtype, bool newp2p)
4884{
46bc8d4b 4885 struct il_priv *il = hw->priv;
be663ab6
WYG		 4886 int err;
4887
8c9c48d5
SG		 4888 if (newp2p)
4889 return -EOPNOTSUPP;
be663ab6 4890
46bc8d4b 4891 mutex_lock(&il->mutex);
be663ab6 4892
83007196 4893 if (!il->vif || !il_is_ready_rf(il)) {
ffd8c746
JB		 4894 /*
4895 * Huh? But wait ... this can maybe happen when
4896 * we're in the middle of a firmware restart!
4897 */
4898 err = -EBUSY;
4899 goto out;
4900 }
4901
be663ab6 4902 /* success */
46bc8d4b 4903 il_teardown_interface(il, vif, true);
be663ab6 4904 vif->type = newtype;
8c9c48d5 4905 vif->p2p = false;
83007196 4906 err = il_set_mode(il);
be663ab6
WYG		 4907 WARN_ON(err);
4908 /*
4909 * We've switched internally, but submitting to the
4910 * device may have failed for some reason. Mask this
4911 * error, because otherwise mac80211 will not switch
4912 * (and set the interface type back) and we'll be
4913 * out of sync with it.
4914 */
4915 err = 0;
4916
e7392364 4917out:
46bc8d4b 4918 mutex_unlock(&il->mutex);
be663ab6
WYG		 4919 return err;
4920}
e2ebc833 4921EXPORT_SYMBOL(il_mac_change_interface);
be663ab6
WYG		 4922
4923/*
4924 * On every watchdog tick we check (latest) time stamp. If it does not
4925 * change during timeout period and queue is not empty we reset firmware.
4926 */
e7392364
SG		 4927static int
4928il_check_stuck_queue(struct il_priv *il, int cnt)
be663ab6 4929{
46bc8d4b 4930 struct il_tx_queue *txq = &il->txq[cnt];
e2ebc833 4931 struct il_queue *q = &txq->q;
be663ab6
WYG		 4932 unsigned long timeout;
4933 int ret;
4934
4935 if (q->read_ptr == q->write_ptr) {
4936 txq->time_stamp = jiffies;
4937 return 0;
4938 }
4939
e7392364
SG		 4940 timeout =
4941 txq->time_stamp +
89ef1ed2 4942 msecs_to_jiffies(il->cfg->wd_timeout);
be663ab6
WYG		 4943
4944 if (time_after(jiffies, timeout)) {
e7392364 4945 IL_ERR("Queue %d stuck for %u ms.\n", q->id,
89ef1ed2 4946 il->cfg->wd_timeout);
46bc8d4b 4947 ret = il_force_reset(il, false);
be663ab6
WYG		 4948 return (ret == -EAGAIN) ? 0 : 1;
4949 }
4950
4951 return 0;
4952}
4953
4954/*
4955 * Making watchdog tick be a quarter of timeout assure we will
4956 * discover the queue hung between timeout and 1.25*timeout
4957 */
e2ebc833 4958#define IL_WD_TICK(timeout) ((timeout) / 4)
be663ab6
WYG		 4959
4960/*
4961 * Watchdog timer callback, we check each tx queue for stuck, if if hung
4962 * we reset the firmware. If everything is fine just rearm the timer.
4963 */
e7392364
SG		 4964void
4965il_bg_watchdog(unsigned long data)
be663ab6 4966{
46bc8d4b 4967 struct il_priv *il = (struct il_priv *)data;
be663ab6
WYG		 4968 int cnt;
4969 unsigned long timeout;
4970
a6766ccd 4971 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4972 return;
4973
89ef1ed2 4974 timeout = il->cfg->wd_timeout;
be663ab6
WYG		 4975 if (timeout == 0)
4976 return;
4977
4978 /* monitor and check for stuck cmd queue */
46bc8d4b 4979 if (il_check_stuck_queue(il, il->cmd_queue))
be663ab6
WYG		 4980 return;
4981
4982 /* monitor and check for other stuck queues */
46bc8d4b
SG		 4983 if (il_is_any_associated(il)) {
4984 for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) {
be663ab6 4985 /* skip as we already checked the command queue */
46bc8d4b 4986 if (cnt == il->cmd_queue)
be663ab6 4987 continue;
46bc8d4b 4988 if (il_check_stuck_queue(il, cnt))
be663ab6
WYG		 4989 return;
4990 }
4991 }
4992
e7392364
SG		 4993 mod_timer(&il->watchdog,
4994 jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
be663ab6 4995}
e2ebc833 4996EXPORT_SYMBOL(il_bg_watchdog);
be663ab6 4997
e7392364
SG		 4998void
4999il_setup_watchdog(struct il_priv *il)
be663ab6 5000{
89ef1ed2 5001 unsigned int timeout = il->cfg->wd_timeout;
be663ab6
WYG		 5002
5003 if (timeout)
46bc8d4b 5004 mod_timer(&il->watchdog,
e2ebc833 5005 jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
be663ab6 5006 else
46bc8d4b 5007 del_timer(&il->watchdog);
be663ab6 5008}
e2ebc833 5009EXPORT_SYMBOL(il_setup_watchdog);
be663ab6
WYG		 5010
5011/*
5012 * extended beacon time format
5013 * time in usec will be changed into a 32-bit value in extended:internal format
5014 * the extended part is the beacon counts
5015 * the internal part is the time in usec within one beacon interval
5016 */
5017u32
e7392364 5018il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval)
be663ab6
WYG		 5019{
5020 u32 quot;
5021 u32 rem;
5022 u32 interval = beacon_interval * TIME_UNIT;
5023
5024 if (!interval || !usec)
5025 return 0;
5026
e7392364
SG		 5027 quot =
5028 (usec /
5029 interval) & (il_beacon_time_mask_high(il,
5030 il->hw_params.
5031 beacon_time_tsf_bits) >> il->
5032 hw_params.beacon_time_tsf_bits);
5033 rem =
5034 (usec % interval) & il_beacon_time_mask_low(il,
5035 il->hw_params.
5036 beacon_time_tsf_bits);
be663ab6 5037
46bc8d4b 5038 return (quot << il->hw_params.beacon_time_tsf_bits) + rem;
be663ab6 5039}
e2ebc833 5040EXPORT_SYMBOL(il_usecs_to_beacons);
be663ab6
WYG		 5041
5042/* base is usually what we get from ucode with each received frame,
5043 * the same as HW timer counter counting down
5044 */
e7392364 5045__le32
1722f8e1 5046il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
e7392364 5047 u32 beacon_interval)
be663ab6 5048{
46bc8d4b 5049 u32 base_low = base & il_beacon_time_mask_low(il,
e7392364
SG		 5050 il->hw_params.
5051 beacon_time_tsf_bits);
46bc8d4b 5052 u32 addon_low = addon & il_beacon_time_mask_low(il,
e7392364
SG		 5053 il->hw_params.
5054 beacon_time_tsf_bits);
be663ab6 5055 u32 interval = beacon_interval * TIME_UNIT;
46bc8d4b 5056 u32 res = (base & il_beacon_time_mask_high(il,
e7392364
SG		 5057 il->hw_params.
5058 beacon_time_tsf_bits)) +
5059 (addon & il_beacon_time_mask_high(il,
5060 il->hw_params.
5061 beacon_time_tsf_bits));
be663ab6
WYG		 5062
5063 if (base_low > addon_low)
5064 res += base_low - addon_low;
5065 else if (base_low < addon_low) {
5066 res += interval + base_low - addon_low;
46bc8d4b 5067 res += (1 << il->hw_params.beacon_time_tsf_bits);
be663ab6 5068 } else
46bc8d4b 5069 res += (1 << il->hw_params.beacon_time_tsf_bits);
be663ab6
WYG		 5070
5071 return cpu_to_le32(res);
5072}
e2ebc833 5073EXPORT_SYMBOL(il_add_beacon_time);
be663ab6
WYG		 5074
5075#ifdef CONFIG_PM
5076
e7392364
SG		 5077int
5078il_pci_suspend(struct device *device)
be663ab6
WYG		 5079{
5080 struct pci_dev *pdev = to_pci_dev(device);
46bc8d4b 5081 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 5082
5083 /*
5084 * This function is called when system goes into suspend state
e2ebc833
SG		 5085 * mac80211 will call il_mac_stop() from the mac80211 suspend function
5086 * first but since il_mac_stop() has no knowledge of who the caller is,
be663ab6
WYG		 5087 * it will not call apm_ops.stop() to stop the DMA operation.
5088 * Calling apm_ops.stop here to make sure we stop the DMA.
5089 */
46bc8d4b 5090 il_apm_stop(il);
be663ab6
WYG		 5091
5092 return 0;
5093}
e2ebc833 5094EXPORT_SYMBOL(il_pci_suspend);
be663ab6 5095
e7392364
SG		 5096int
5097il_pci_resume(struct device *device)
be663ab6
WYG		 5098{
5099 struct pci_dev *pdev = to_pci_dev(device);
46bc8d4b 5100 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 5101 bool hw_rfkill = false;
5102
5103 /*
5104 * We disable the RETRY_TIMEOUT register (0x41) to keep
5105 * PCI Tx retries from interfering with C3 CPU state.
5106 */
5107 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
5108
46bc8d4b 5109 il_enable_interrupts(il);
be663ab6 5110
e7392364 5111 if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
be663ab6
WYG		 5112 hw_rfkill = true;
5113
5114 if (hw_rfkill)
a6766ccd 5115 set_bit(S_RF_KILL_HW, &il->status);
be663ab6 5116 else
a6766ccd 5117 clear_bit(S_RF_KILL_HW, &il->status);
be663ab6 5118
46bc8d4b 5119 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill);
be663ab6
WYG		 5120
5121 return 0;
5122}
e2ebc833 5123EXPORT_SYMBOL(il_pci_resume);
be663ab6 5124
e2ebc833
SG		 5125const struct dev_pm_ops il_pm_ops = {
5126 .suspend = il_pci_suspend,
5127 .resume = il_pci_resume,
5128 .freeze = il_pci_suspend,
5129 .thaw = il_pci_resume,
5130 .poweroff = il_pci_suspend,
5131 .restore = il_pci_resume,
be663ab6 5132};
e2ebc833 5133EXPORT_SYMBOL(il_pm_ops);
be663ab6
WYG		 5134
5135#endif /* CONFIG_PM */
5136
5137static void
83007196 5138il_update_qos(struct il_priv *il)
be663ab6 5139{
a6766ccd 5140 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5141 return;
5142
8d44f2bd 5143 il->qos_data.def_qos_parm.qos_flags = 0;
be663ab6 5144
8d44f2bd
SG		 5145 if (il->qos_data.qos_active)
5146 il->qos_data.def_qos_parm.qos_flags |=
e7392364 5147 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
be663ab6 5148
1c03c462 5149 if (il->ht.enabled)
8d44f2bd 5150 il->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
be663ab6 5151
58de00a4 5152 D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
8d44f2bd 5153 il->qos_data.qos_active, il->qos_data.def_qos_parm.qos_flags);
be663ab6 5154
b96ed60c 5155 il_send_cmd_pdu_async(il, C_QOS_PARAM, sizeof(struct il_qosparam_cmd),
8d44f2bd 5156 &il->qos_data.def_qos_parm, NULL);
be663ab6
WYG		 5157}
5158
5159/**
e2ebc833 5160 * il_mac_config - mac80211 config callback
be663ab6 5161 */
e7392364
SG		 5162int
5163il_mac_config(struct ieee80211_hw *hw, u32 changed)
be663ab6 5164{
46bc8d4b 5165 struct il_priv *il = hw->priv;
e2ebc833 5166 const struct il_channel_info *ch_info;
be663ab6
WYG		 5167 struct ieee80211_conf *conf = &hw->conf;
5168 struct ieee80211_channel *channel = conf->channel;
46bc8d4b 5169 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6
WYG		 5170 unsigned long flags = 0;
5171 int ret = 0;
5172 u16 ch;
5173 int scan_active = 0;
7c2cde2e 5174 bool ht_changed = false;
be663ab6 5175
c39ae9fd 5176 if (WARN_ON(!il->ops->legacy))
be663ab6
WYG		 5177 return -EOPNOTSUPP;
5178
46bc8d4b 5179 mutex_lock(&il->mutex);
be663ab6 5180
e7392364
SG		 5181 D_MAC80211("enter to channel %d changed 0x%X\n", channel->hw_value,
5182 changed);
be663ab6 5183
a6766ccd 5184 if (unlikely(test_bit(S_SCANNING, &il->status))) {
be663ab6 5185 scan_active = 1;
58de00a4 5186 D_MAC80211("scan active\n");
be663ab6
WYG		 5187 }
5188
e7392364
SG		 5189 if (changed &
5190 (IEEE80211_CONF_CHANGE_SMPS | IEEE80211_CONF_CHANGE_CHANNEL)) {
be663ab6 5191 /* mac80211 uses static for non-HT which is what we want */
46bc8d4b 5192 il->current_ht_config.smps = conf->smps_mode;
be663ab6
WYG		 5193
5194 /*
5195 * Recalculate chain counts.
5196 *
5197 * If monitor mode is enabled then mac80211 will
5198 * set up the SM PS mode to OFF if an HT channel is
5199 * configured.
5200 */
c39ae9fd
SG		 5201 if (il->ops->hcmd->set_rxon_chain)
5202 il->ops->hcmd->set_rxon_chain(il);
be663ab6
WYG		 5203 }
5204
5205 /* during scanning mac80211 will delay channel setting until
5206 * scan finish with changed = 0
5207 */
5208 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
17d6e557 5209
be663ab6
WYG		 5210 if (scan_active)
5211 goto set_ch_out;
5212
5213 ch = channel->hw_value;
46bc8d4b 5214 ch_info = il_get_channel_info(il, channel->band, ch);
e2ebc833 5215 if (!il_is_channel_valid(ch_info)) {
58de00a4 5216 D_MAC80211("leave - invalid channel\n");
be663ab6
WYG		 5217 ret = -EINVAL;
5218 goto set_ch_out;
5219 }
5220
46bc8d4b 5221 if (il->iw_mode == NL80211_IFTYPE_ADHOC &&
e2ebc833 5222 !il_is_channel_ibss(ch_info)) {
58de00a4 5223 D_MAC80211("leave - not IBSS channel\n");
eb85de3f
SG		 5224 ret = -EINVAL;
5225 goto set_ch_out;
5226 }
5227
46bc8d4b 5228 spin_lock_irqsave(&il->lock, flags);
be663ab6 5229
17d6e557 5230 /* Configure HT40 channels */
1c03c462
SG		 5231 if (il->ht.enabled != conf_is_ht(conf)) {
5232 il->ht.enabled = conf_is_ht(conf);
17d6e557
SG		 5233 ht_changed = true;
5234 }
1c03c462 5235 if (il->ht.enabled) {
17d6e557 5236 if (conf_is_ht40_minus(conf)) {
1c03c462 5237 il->ht.extension_chan_offset =
e7392364 5238 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
1c03c462 5239 il->ht.is_40mhz = true;
17d6e557 5240 } else if (conf_is_ht40_plus(conf)) {
1c03c462 5241 il->ht.extension_chan_offset =
e7392364 5242 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
1c03c462 5243 il->ht.is_40mhz = true;
17d6e557 5244 } else {
1c03c462 5245 il->ht.extension_chan_offset =
e7392364 5246 IEEE80211_HT_PARAM_CHA_SEC_NONE;
1c03c462 5247 il->ht.is_40mhz = false;
17d6e557
SG		 5248 }
5249 } else
1c03c462 5250 il->ht.is_40mhz = false;
be663ab6 5251
17d6e557
SG		 5252 /*
5253 * Default to no protection. Protection mode will
5254 * later be set from BSS config in il_ht_conf
5255 */
1c03c462 5256 il->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
be663ab6 5257
17d6e557
SG		 5258 /* if we are switching from ht to 2.4 clear flags
5259 * from any ht related info since 2.4 does not
5260 * support ht */
c8b03958
SG		 5261 if ((le16_to_cpu(il->staging.channel) != ch))
5262 il->staging.flags = 0;
be663ab6 5263
83007196 5264 il_set_rxon_channel(il, channel);
17d6e557 5265 il_set_rxon_ht(il, ht_conf);
be663ab6 5266
83007196 5267 il_set_flags_for_band(il, channel->band, il->vif);
be663ab6 5268
46bc8d4b 5269 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5270
c39ae9fd
SG		 5271 if (il->ops->legacy->update_bcast_stations)
5272 ret = il->ops->legacy->update_bcast_stations(il);
be663ab6 5273
e7392364 5274set_ch_out:
be663ab6
WYG		 5275 /* The list of supported rates and rate mask can be different
5276 * for each band; since the band may have changed, reset
5277 * the rate mask to what mac80211 lists */
46bc8d4b 5278 il_set_rate(il);
be663ab6
WYG		 5279 }
5280
e7392364 5281 if (changed & (IEEE80211_CONF_CHANGE_PS | IEEE80211_CONF_CHANGE_IDLE)) {
46bc8d4b 5282 ret = il_power_update_mode(il, false);
be663ab6 5283 if (ret)
58de00a4 5284 D_MAC80211("Error setting sleep level\n");
be663ab6
WYG		 5285 }
5286
5287 if (changed & IEEE80211_CONF_CHANGE_POWER) {
e7392364
SG		 5288 D_MAC80211("TX Power old=%d new=%d\n", il->tx_power_user_lmt,
5289 conf->power_level);
be663ab6 5290
46bc8d4b 5291 il_set_tx_power(il, conf->power_level, false);
be663ab6
WYG		 5292 }
5293
46bc8d4b 5294 if (!il_is_ready(il)) {
58de00a4 5295 D_MAC80211("leave - not ready\n");
be663ab6
WYG		 5296 goto out;
5297 }
5298
5299 if (scan_active)
5300 goto out;
5301
c8b03958 5302 if (memcmp(&il->active, &il->staging, sizeof(il->staging)))
83007196 5303 il_commit_rxon(il);
17d6e557
SG		 5304 else
5305 D_INFO("Not re-sending same RXON configuration.\n");
5306 if (ht_changed)
83007196 5307 il_update_qos(il);
be663ab6
WYG		 5308
5309out:
58de00a4 5310 D_MAC80211("leave\n");
46bc8d4b 5311 mutex_unlock(&il->mutex);
be663ab6
WYG		 5312 return ret;
5313}
e2ebc833 5314EXPORT_SYMBOL(il_mac_config);
be663ab6 5315
e7392364
SG		 5316void
5317il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 5318{
46bc8d4b 5319 struct il_priv *il = hw->priv;
be663ab6 5320 unsigned long flags;
be663ab6 5321
c39ae9fd 5322 if (WARN_ON(!il->ops->legacy))
be663ab6
WYG		 5323 return;
5324
46bc8d4b 5325 mutex_lock(&il->mutex);
58de00a4 5326 D_MAC80211("enter\n");
be663ab6 5327
46bc8d4b
SG		 5328 spin_lock_irqsave(&il->lock, flags);
5329 memset(&il->current_ht_config, 0, sizeof(struct il_ht_config));
5330 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5331
46bc8d4b 5332 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 5333
5334 /* new association get rid of ibss beacon skb */
46bc8d4b
SG		 5335 if (il->beacon_skb)
5336 dev_kfree_skb(il->beacon_skb);
be663ab6 5337
46bc8d4b 5338 il->beacon_skb = NULL;
be663ab6 5339
46bc8d4b 5340 il->timestamp = 0;
be663ab6 5341
46bc8d4b 5342 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5343
46bc8d4b
SG		 5344 il_scan_cancel_timeout(il, 100);
5345 if (!il_is_ready_rf(il)) {
58de00a4 5346 D_MAC80211("leave - not ready\n");
46bc8d4b 5347 mutex_unlock(&il->mutex);
be663ab6
WYG		 5348 return;
5349 }
5350
5351 /* we are restarting association process
5352 * clear RXON_FILTER_ASSOC_MSK bit
5353 */
c8b03958 5354 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
83007196 5355 il_commit_rxon(il);
be663ab6 5356
46bc8d4b 5357 il_set_rate(il);
be663ab6 5358
46bc8d4b 5359 mutex_unlock(&il->mutex);
be663ab6 5360
58de00a4 5361 D_MAC80211("leave\n");
be663ab6 5362}
e2ebc833 5363EXPORT_SYMBOL(il_mac_reset_tsf);
be663ab6 5364
e7392364
SG		 5365static void
5366il_ht_conf(struct il_priv *il, struct ieee80211_vif *vif)
be663ab6 5367{
46bc8d4b 5368 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6
WYG		 5369 struct ieee80211_sta *sta;
5370 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
be663ab6 5371
58de00a4 5372 D_ASSOC("enter:\n");
be663ab6 5373
1c03c462 5374 if (!il->ht.enabled)
be663ab6
WYG		 5375 return;
5376
1c03c462 5377 il->ht.protection =
e7392364 5378 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
1c03c462 5379 il->ht.non_gf_sta_present =
e7392364
SG		 5380 !!(bss_conf->
5381 ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
be663ab6
WYG		 5382
5383 ht_conf->single_chain_sufficient = false;
5384
5385 switch (vif->type) {
5386 case NL80211_IFTYPE_STATION:
5387 rcu_read_lock();
5388 sta = ieee80211_find_sta(vif, bss_conf->bssid);
5389 if (sta) {
5390 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
5391 int maxstreams;
5392
e7392364
SG		 5393 maxstreams =
5394 (ht_cap->mcs.
5395 tx_params & IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
5396 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
be663ab6
WYG		 5397 maxstreams += 1;
5398
232913b5
SG		 5399 if (ht_cap->mcs.rx_mask[1] == 0 &&
5400 ht_cap->mcs.rx_mask[2] == 0)
be663ab6
WYG		 5401 ht_conf->single_chain_sufficient = true;
5402 if (maxstreams <= 1)
5403 ht_conf->single_chain_sufficient = true;
5404 } else {
5405 /*
5406 * If at all, this can only happen through a race
5407 * when the AP disconnects us while we're still
5408 * setting up the connection, in that case mac80211
5409 * will soon tell us about that.
5410 */
5411 ht_conf->single_chain_sufficient = true;
5412 }
5413 rcu_read_unlock();
5414 break;
5415 case NL80211_IFTYPE_ADHOC:
5416 ht_conf->single_chain_sufficient = true;
5417 break;
5418 default:
5419 break;
5420 }
5421
58de00a4 5422 D_ASSOC("leave\n");
be663ab6
WYG		 5423}
5424
e7392364
SG		 5425static inline void
5426il_set_no_assoc(struct il_priv *il, struct ieee80211_vif *vif)
be663ab6 5427{
be663ab6
WYG		 5428 /*
5429 * inform the ucode that there is no longer an
5430 * association and that no more packets should be
5431 * sent
5432 */
c8b03958
SG		 5433 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5434 il->staging.assoc_id = 0;
83007196 5435 il_commit_rxon(il);
be663ab6
WYG		 5436}
5437
e7392364
SG		 5438static void
5439il_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 5440{
46bc8d4b 5441 struct il_priv *il = hw->priv;
be663ab6
WYG		 5442 unsigned long flags;
5443 __le64 timestamp;
5444 struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
5445
5446 if (!skb)
5447 return;
5448
58de00a4 5449 D_MAC80211("enter\n");
be663ab6 5450
46bc8d4b 5451 lockdep_assert_held(&il->mutex);
be663ab6 5452
83007196
SG		 5453 if (!il->beacon_enabled) {
5454 IL_ERR("update beacon with no beaconing enabled\n");
be663ab6
WYG		 5455 dev_kfree_skb(skb);
5456 return;
5457 }
5458
46bc8d4b 5459 spin_lock_irqsave(&il->lock, flags);
be663ab6 5460
46bc8d4b
SG		 5461 if (il->beacon_skb)
5462 dev_kfree_skb(il->beacon_skb);
be663ab6 5463
46bc8d4b 5464 il->beacon_skb = skb;
be663ab6
WYG		 5465
5466 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
46bc8d4b 5467 il->timestamp = le64_to_cpu(timestamp);
be663ab6 5468
58de00a4 5469 D_MAC80211("leave\n");
46bc8d4b 5470 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5471
46bc8d4b 5472 if (!il_is_ready_rf(il)) {
58de00a4 5473 D_MAC80211("leave - RF not ready\n");
be663ab6
WYG		 5474 return;
5475 }
5476
c39ae9fd 5477 il->ops->legacy->post_associate(il);
be663ab6
WYG		 5478}
5479
e7392364
SG		 5480void
5481il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5482 struct ieee80211_bss_conf *bss_conf, u32 changes)
be663ab6 5483{
46bc8d4b 5484 struct il_priv *il = hw->priv;
be663ab6
WYG		 5485 int ret;
5486
c39ae9fd 5487 if (WARN_ON(!il->ops->legacy))
be663ab6
WYG		 5488 return;
5489
58de00a4 5490 D_MAC80211("changes = 0x%X\n", changes);
be663ab6 5491
46bc8d4b 5492 mutex_lock(&il->mutex);
be663ab6 5493
46bc8d4b
SG		 5494 if (!il_is_alive(il)) {
5495 mutex_unlock(&il->mutex);
28a6e577
SG		 5496 return;
5497 }
5498
be663ab6
WYG		 5499 if (changes & BSS_CHANGED_QOS) {
5500 unsigned long flags;
5501
46bc8d4b 5502 spin_lock_irqsave(&il->lock, flags);
8d44f2bd 5503 il->qos_data.qos_active = bss_conf->qos;
83007196 5504 il_update_qos(il);
46bc8d4b 5505 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5506 }
5507
5508 if (changes & BSS_CHANGED_BEACON_ENABLED) {
83007196 5509 /* FIXME: can we remove beacon_enabled ? */
be663ab6 5510 if (vif->bss_conf.enable_beacon)
83007196 5511 il->beacon_enabled = true;
be663ab6 5512 else
83007196 5513 il->beacon_enabled = false;
be663ab6
WYG		 5514 }
5515
5516 if (changes & BSS_CHANGED_BSSID) {
58de00a4 5517 D_MAC80211("BSSID %pM\n", bss_conf->bssid);
be663ab6
WYG		 5518
5519 /*
5520 * If there is currently a HW scan going on in the
5521 * background then we need to cancel it else the RXON
5522 * below/in post_associate will fail.
5523 */
46bc8d4b 5524 if (il_scan_cancel_timeout(il, 100)) {
e7392364
SG		 5525 IL_WARN("Aborted scan still in progress after 100ms\n");
5526 D_MAC80211("leaving - scan abort failed.\n");
46bc8d4b 5527 mutex_unlock(&il->mutex);
be663ab6
WYG		 5528 return;
5529 }
5530
5531 /* mac80211 only sets assoc when in STATION mode */
5532 if (vif->type == NL80211_IFTYPE_ADHOC || bss_conf->assoc) {
c8b03958 5533 memcpy(il->staging.bssid_addr, bss_conf->bssid,
e7392364 5534 ETH_ALEN);
be663ab6
WYG		 5535
5536 /* currently needed in a few places */
46bc8d4b 5537 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
be663ab6 5538 } else {
c8b03958 5539 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
be663ab6
WYG		 5540 }
5541
5542 }
5543
5544 /*
5545 * This needs to be after setting the BSSID in case
5546 * mac80211 decides to do both changes at once because
5547 * it will invoke post_associate.
5548 */
232913b5 5549 if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON))
e2ebc833 5550 il_beacon_update(hw, vif);
be663ab6
WYG		 5551
5552 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
e7392364 5553 D_MAC80211("ERP_PREAMBLE %d\n", bss_conf->use_short_preamble);
be663ab6 5554 if (bss_conf->use_short_preamble)
c8b03958 5555 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6 5556 else
c8b03958 5557 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6
WYG		 5558 }
5559
5560 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
e7392364 5561 D_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
232913b5 5562 if (bss_conf->use_cts_prot && il->band != IEEE80211_BAND_5GHZ)
c8b03958 5563 il->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
be663ab6 5564 else
c8b03958 5565 il->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
be663ab6 5566 if (bss_conf->use_cts_prot)
c8b03958 5567 il->staging.flags |= RXON_FLG_SELF_CTS_EN;
be663ab6 5568 else
c8b03958 5569 il->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
be663ab6
WYG		 5570 }
5571
5572 if (changes & BSS_CHANGED_BASIC_RATES) {
5573 /* XXX use this information
5574 *
e2ebc833 5575 * To do that, remove code from il_set_rate() and put something
be663ab6
WYG		 5576 * like this here:
5577 *
e7392364 5578 if (A-band)
c8b03958 5579 il->staging.ofdm_basic_rates =
e7392364
SG		 5580 bss_conf->basic_rates;
5581 else
c8b03958 5582 il->staging.ofdm_basic_rates =
e7392364 5583 bss_conf->basic_rates >> 4;
c8b03958 5584 il->staging.cck_basic_rates =
e7392364 5585 bss_conf->basic_rates & 0xF;
be663ab6
WYG		 5586 */
5587 }
5588
5589 if (changes & BSS_CHANGED_HT) {
46bc8d4b 5590 il_ht_conf(il, vif);
be663ab6 5591
c39ae9fd
SG		 5592 if (il->ops->hcmd->set_rxon_chain)
5593 il->ops->hcmd->set_rxon_chain(il);
be663ab6
WYG		 5594 }
5595
5596 if (changes & BSS_CHANGED_ASSOC) {
58de00a4 5597 D_MAC80211("ASSOC %d\n", bss_conf->assoc);
be663ab6 5598 if (bss_conf->assoc) {
46bc8d4b 5599 il->timestamp = bss_conf->timestamp;
be663ab6 5600
46bc8d4b 5601 if (!il_is_rfkill(il))
c39ae9fd 5602 il->ops->legacy->post_associate(il);
be663ab6 5603 } else
46bc8d4b 5604 il_set_no_assoc(il, vif);
be663ab6
WYG		 5605 }
5606
c8b03958 5607 if (changes && il_is_associated(il) && bss_conf->aid) {
e7392364 5608 D_MAC80211("Changes (%#x) while associated\n", changes);
83007196 5609 ret = il_send_rxon_assoc(il);
be663ab6
WYG		 5610 if (!ret) {
5611 /* Sync active_rxon with latest change. */
c8b03958 5612 memcpy((void *)&il->active, &il->staging,
e7392364 5613 sizeof(struct il_rxon_cmd));
be663ab6
WYG		 5614 }
5615 }
5616
5617 if (changes & BSS_CHANGED_BEACON_ENABLED) {
5618 if (vif->bss_conf.enable_beacon) {
c8b03958 5619 memcpy(il->staging.bssid_addr, bss_conf->bssid,
e7392364 5620 ETH_ALEN);
46bc8d4b 5621 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
c39ae9fd 5622 il->ops->legacy->config_ap(il);
be663ab6 5623 } else
46bc8d4b 5624 il_set_no_assoc(il, vif);
be663ab6
WYG		 5625 }
5626
5627 if (changes & BSS_CHANGED_IBSS) {
e7392364 5628 ret =
c39ae9fd
SG		 5629 il->ops->legacy->manage_ibss_station(il, vif,
5630 bss_conf->ibss_joined);
be663ab6 5631 if (ret)
9406f797 5632 IL_ERR("failed to %s IBSS station %pM\n",
e7392364
SG		 5633 bss_conf->ibss_joined ? "add" : "remove",
5634 bss_conf->bssid);
be663ab6
WYG		 5635 }
5636
46bc8d4b 5637 mutex_unlock(&il->mutex);
be663ab6 5638
58de00a4 5639 D_MAC80211("leave\n");
be663ab6 5640}
e2ebc833 5641EXPORT_SYMBOL(il_mac_bss_info_changed);
be663ab6 5642
e7392364
SG		 5643irqreturn_t
5644il_isr(int irq, void *data)
be663ab6 5645{
46bc8d4b 5646 struct il_priv *il = data;
be663ab6
WYG		 5647 u32 inta, inta_mask;
5648 u32 inta_fh;
5649 unsigned long flags;
46bc8d4b 5650 if (!il)
be663ab6
WYG		 5651 return IRQ_NONE;
5652
46bc8d4b 5653 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 5654
5655 /* Disable (but don't clear!) interrupts here to avoid
5656 * back-to-back ISRs and sporadic interrupts from our NIC.
5657 * If we have something to service, the tasklet will re-enable ints.
5658 * If we *don't* have something, we'll re-enable before leaving here. */
e7392364 5659 inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */
841b2cca 5660 _il_wr(il, CSR_INT_MASK, 0x00000000);
be663ab6
WYG		 5661
5662 /* Discover which interrupts are active/pending */
841b2cca
SG		 5663 inta = _il_rd(il, CSR_INT);
5664 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
be663ab6
WYG		 5665
5666 /* Ignore interrupt if there's nothing in NIC to service.
5667 * This may be due to IRQ shared with another device,
5668 * or due to sporadic interrupts thrown from our NIC. */
5669 if (!inta && !inta_fh) {
e7392364 5670 D_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
be663ab6
WYG		 5671 goto none;
5672 }
5673
232913b5 5674 if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) {
be663ab6
WYG		 5675 /* Hardware disappeared. It might have already raised
5676 * an interrupt */
9406f797 5677 IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta);
be663ab6
WYG		 5678 goto unplugged;
5679 }
5680
e7392364
SG		 5681 D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, inta_mask,
5682 inta_fh);
be663ab6
WYG		 5683
5684 inta &= ~CSR_INT_BIT_SCD;
5685
e2ebc833 5686 /* il_irq_tasklet() will service interrupts and re-enable them */
be663ab6 5687 if (likely(inta || inta_fh))
46bc8d4b 5688 tasklet_schedule(&il->irq_tasklet);
be663ab6
WYG		 5689
5690unplugged:
46bc8d4b 5691 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5692 return IRQ_HANDLED;
5693
5694none:
5695 /* re-enable interrupts here since we don't have anything to service. */
93fd74e3 5696 /* only Re-enable if disabled by irq */
a6766ccd 5697 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b
SG		 5698 il_enable_interrupts(il);
5699 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5700 return IRQ_NONE;
5701}
e2ebc833 5702EXPORT_SYMBOL(il_isr);
be663ab6
WYG		 5703
5704/*
e2ebc833 5705 * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
be663ab6
WYG		 5706 * function.
5707 */
e7392364
SG		 5708void
5709il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1722f8e1 5710 __le16 fc, __le32 *tx_flags)
be663ab6
WYG		 5711{
5712 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
5713 *tx_flags |= TX_CMD_FLG_RTS_MSK;
5714 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
5715 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5716
5717 if (!ieee80211_is_mgmt(fc))
5718 return;
5719
5720 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
5721 case cpu_to_le16(IEEE80211_STYPE_AUTH):
5722 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
5723 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
5724 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
5725 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5726 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5727 break;
5728 }
e7392364
SG		 5729 } else if (info->control.rates[0].
5730 flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
be663ab6
WYG		 5731 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5732 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5733 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5734 }
5735}
e2ebc833 5736EXPORT_SYMBOL(il_tx_cmd_protection);
Linux kernel - Deliverables
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