iwlegacy: get rid of wep_key_cmd
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / common.c
CommitLineData
be663ab6
WYG
1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/etherdevice.h>
32#include <linux/sched.h>
33#include <linux/slab.h>
0cdc2136
SG
34#include <linux/types.h>
35#include <linux/lockdep.h>
36#include <linux/init.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/skbuff.h>
be663ab6
WYG
41#include <net/mac80211.h>
42
98613be0 43#include "common.h"
be663ab6 44
17d4eca6
SG
45int
46_il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout)
47{
48 const int interval = 10; /* microseconds */
49 int t = 0;
50
51 do {
52 if ((_il_rd(il, addr) & mask) == (bits & mask))
53 return t;
54 udelay(interval);
55 t += interval;
56 } while (t < timeout);
57
58 return -ETIMEDOUT;
59}
60EXPORT_SYMBOL(_il_poll_bit);
61
62void
63il_set_bit(struct il_priv *p, u32 r, u32 m)
64{
65 unsigned long reg_flags;
66
67 spin_lock_irqsave(&p->reg_lock, reg_flags);
68 _il_set_bit(p, r, m);
69 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
70}
71EXPORT_SYMBOL(il_set_bit);
72
73void
74il_clear_bit(struct il_priv *p, u32 r, u32 m)
75{
76 unsigned long reg_flags;
77
78 spin_lock_irqsave(&p->reg_lock, reg_flags);
79 _il_clear_bit(p, r, m);
80 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
81}
82EXPORT_SYMBOL(il_clear_bit);
83
84int
85_il_grab_nic_access(struct il_priv *il)
86{
87 int ret;
88 u32 val;
89
90 /* this bit wakes up the NIC */
91 _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
92
93 /*
94 * These bits say the device is running, and should keep running for
95 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
96 * but they do not indicate that embedded SRAM is restored yet;
97 * 3945 and 4965 have volatile SRAM, and must save/restore contents
98 * to/from host DRAM when sleeping/waking for power-saving.
99 * Each direction takes approximately 1/4 millisecond; with this
100 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
101 * series of register accesses are expected (e.g. reading Event Log),
102 * to keep device from sleeping.
103 *
104 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
105 * SRAM is okay/restored. We don't check that here because this call
106 * is just for hardware register access; but GP1 MAC_SLEEP check is a
107 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
108 *
109 */
110 ret =
111 _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
112 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
113 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
114 if (ret < 0) {
115 val = _il_rd(il, CSR_GP_CNTRL);
116 IL_ERR("MAC is in deep sleep!. CSR_GP_CNTRL = 0x%08X\n", val);
117 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
118 return -EIO;
119 }
120
121 return 0;
122}
123EXPORT_SYMBOL_GPL(_il_grab_nic_access);
124
125int
126il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout)
127{
128 const int interval = 10; /* microseconds */
129 int t = 0;
130
131 do {
132 if ((il_rd(il, addr) & mask) == mask)
133 return t;
134 udelay(interval);
135 t += interval;
136 } while (t < timeout);
137
138 return -ETIMEDOUT;
139}
140EXPORT_SYMBOL(il_poll_bit);
141
142u32
143il_rd_prph(struct il_priv *il, u32 reg)
144{
145 unsigned long reg_flags;
146 u32 val;
147
148 spin_lock_irqsave(&il->reg_lock, reg_flags);
149 _il_grab_nic_access(il);
150 val = _il_rd_prph(il, reg);
151 _il_release_nic_access(il);
152 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
153 return val;
154}
155EXPORT_SYMBOL(il_rd_prph);
156
157void
158il_wr_prph(struct il_priv *il, u32 addr, u32 val)
159{
160 unsigned long reg_flags;
161
162 spin_lock_irqsave(&il->reg_lock, reg_flags);
163 if (!_il_grab_nic_access(il)) {
164 _il_wr_prph(il, addr, val);
165 _il_release_nic_access(il);
166 }
167 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
168}
169EXPORT_SYMBOL(il_wr_prph);
170
171u32
172il_read_targ_mem(struct il_priv *il, u32 addr)
173{
174 unsigned long reg_flags;
175 u32 value;
176
177 spin_lock_irqsave(&il->reg_lock, reg_flags);
178 _il_grab_nic_access(il);
179
180 _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
181 rmb();
182 value = _il_rd(il, HBUS_TARG_MEM_RDAT);
183
184 _il_release_nic_access(il);
185 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
186 return value;
187}
188EXPORT_SYMBOL(il_read_targ_mem);
189
190void
191il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
192{
193 unsigned long reg_flags;
194
195 spin_lock_irqsave(&il->reg_lock, reg_flags);
196 if (!_il_grab_nic_access(il)) {
197 _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
198 wmb();
199 _il_wr(il, HBUS_TARG_MEM_WDAT, val);
200 _il_release_nic_access(il);
201 }
202 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
203}
204EXPORT_SYMBOL(il_write_targ_mem);
205
e7392364
SG
206const char *
207il_get_cmd_string(u8 cmd)
0cdc2136
SG
208{
209 switch (cmd) {
210 IL_CMD(N_ALIVE);
211 IL_CMD(N_ERROR);
212 IL_CMD(C_RXON);
213 IL_CMD(C_RXON_ASSOC);
214 IL_CMD(C_QOS_PARAM);
215 IL_CMD(C_RXON_TIMING);
216 IL_CMD(C_ADD_STA);
217 IL_CMD(C_REM_STA);
218 IL_CMD(C_WEPKEY);
219 IL_CMD(N_3945_RX);
220 IL_CMD(C_TX);
221 IL_CMD(C_RATE_SCALE);
222 IL_CMD(C_LEDS);
223 IL_CMD(C_TX_LINK_QUALITY_CMD);
224 IL_CMD(C_CHANNEL_SWITCH);
225 IL_CMD(N_CHANNEL_SWITCH);
226 IL_CMD(C_SPECTRUM_MEASUREMENT);
227 IL_CMD(N_SPECTRUM_MEASUREMENT);
228 IL_CMD(C_POWER_TBL);
229 IL_CMD(N_PM_SLEEP);
230 IL_CMD(N_PM_DEBUG_STATS);
231 IL_CMD(C_SCAN);
232 IL_CMD(C_SCAN_ABORT);
233 IL_CMD(N_SCAN_START);
234 IL_CMD(N_SCAN_RESULTS);
235 IL_CMD(N_SCAN_COMPLETE);
236 IL_CMD(N_BEACON);
237 IL_CMD(C_TX_BEACON);
238 IL_CMD(C_TX_PWR_TBL);
239 IL_CMD(C_BT_CONFIG);
240 IL_CMD(C_STATS);
241 IL_CMD(N_STATS);
242 IL_CMD(N_CARD_STATE);
243 IL_CMD(N_MISSED_BEACONS);
244 IL_CMD(C_CT_KILL_CONFIG);
245 IL_CMD(C_SENSITIVITY);
246 IL_CMD(C_PHY_CALIBRATION);
247 IL_CMD(N_RX_PHY);
248 IL_CMD(N_RX_MPDU);
249 IL_CMD(N_RX);
250 IL_CMD(N_COMPRESSED_BA);
251 default:
252 return "UNKNOWN";
253
254 }
255}
256EXPORT_SYMBOL(il_get_cmd_string);
257
258#define HOST_COMPLETE_TIMEOUT (HZ / 2)
259
e7392364
SG
260static void
261il_generic_cmd_callback(struct il_priv *il, struct il_device_cmd *cmd,
262 struct il_rx_pkt *pkt)
0cdc2136
SG
263{
264 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
265 IL_ERR("Bad return from %s (0x%08X)\n",
e7392364 266 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
0cdc2136
SG
267 return;
268 }
0cdc2136
SG
269#ifdef CONFIG_IWLEGACY_DEBUG
270 switch (cmd->hdr.cmd) {
271 case C_TX_LINK_QUALITY_CMD:
272 case C_SENSITIVITY:
273 D_HC_DUMP("back from %s (0x%08X)\n",
e7392364 274 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
0cdc2136
SG
275 break;
276 default:
e7392364
SG
277 D_HC("back from %s (0x%08X)\n", il_get_cmd_string(cmd->hdr.cmd),
278 pkt->hdr.flags);
0cdc2136
SG
279 }
280#endif
281}
282
283static int
284il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd)
285{
286 int ret;
287
288 BUG_ON(!(cmd->flags & CMD_ASYNC));
289
290 /* An asynchronous command can not expect an SKB to be set. */
291 BUG_ON(cmd->flags & CMD_WANT_SKB);
292
293 /* Assign a generic callback if one is not provided */
294 if (!cmd->callback)
295 cmd->callback = il_generic_cmd_callback;
296
297 if (test_bit(S_EXIT_PENDING, &il->status))
298 return -EBUSY;
299
300 ret = il_enqueue_hcmd(il, cmd);
301 if (ret < 0) {
302 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
e7392364 303 il_get_cmd_string(cmd->id), ret);
0cdc2136
SG
304 return ret;
305 }
306 return 0;
307}
308
e7392364
SG
309int
310il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG
311{
312 int cmd_idx;
313 int ret;
314
315 lockdep_assert_held(&il->mutex);
316
317 BUG_ON(cmd->flags & CMD_ASYNC);
318
e7392364 319 /* A synchronous command can not have a callback set. */
0cdc2136
SG
320 BUG_ON(cmd->callback);
321
322 D_INFO("Attempting to send sync command %s\n",
e7392364 323 il_get_cmd_string(cmd->id));
0cdc2136
SG
324
325 set_bit(S_HCMD_ACTIVE, &il->status);
326 D_INFO("Setting HCMD_ACTIVE for command %s\n",
e7392364 327 il_get_cmd_string(cmd->id));
0cdc2136
SG
328
329 cmd_idx = il_enqueue_hcmd(il, cmd);
330 if (cmd_idx < 0) {
331 ret = cmd_idx;
332 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
e7392364 333 il_get_cmd_string(cmd->id), ret);
0cdc2136
SG
334 goto out;
335 }
336
337 ret = wait_event_timeout(il->wait_command_queue,
e7392364
SG
338 !test_bit(S_HCMD_ACTIVE, &il->status),
339 HOST_COMPLETE_TIMEOUT);
0cdc2136
SG
340 if (!ret) {
341 if (test_bit(S_HCMD_ACTIVE, &il->status)) {
e7392364
SG
342 IL_ERR("Error sending %s: time out after %dms.\n",
343 il_get_cmd_string(cmd->id),
344 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
0cdc2136
SG
345
346 clear_bit(S_HCMD_ACTIVE, &il->status);
e7392364
SG
347 D_INFO("Clearing HCMD_ACTIVE for command %s\n",
348 il_get_cmd_string(cmd->id));
0cdc2136
SG
349 ret = -ETIMEDOUT;
350 goto cancel;
351 }
352 }
353
354 if (test_bit(S_RF_KILL_HW, &il->status)) {
355 IL_ERR("Command %s aborted: RF KILL Switch\n",
e7392364 356 il_get_cmd_string(cmd->id));
0cdc2136
SG
357 ret = -ECANCELED;
358 goto fail;
359 }
360 if (test_bit(S_FW_ERROR, &il->status)) {
361 IL_ERR("Command %s failed: FW Error\n",
e7392364 362 il_get_cmd_string(cmd->id));
0cdc2136
SG
363 ret = -EIO;
364 goto fail;
365 }
366 if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
367 IL_ERR("Error: Response NULL in '%s'\n",
e7392364 368 il_get_cmd_string(cmd->id));
0cdc2136
SG
369 ret = -EIO;
370 goto cancel;
371 }
372
373 ret = 0;
374 goto out;
375
376cancel:
377 if (cmd->flags & CMD_WANT_SKB) {
378 /*
379 * Cancel the CMD_WANT_SKB flag for the cmd in the
380 * TX cmd queue. Otherwise in case the cmd comes
381 * in later, it will possibly set an invalid
382 * address (cmd->meta.source).
383 */
e7392364 384 il->txq[il->cmd_queue].meta[cmd_idx].flags &= ~CMD_WANT_SKB;
0cdc2136
SG
385 }
386fail:
387 if (cmd->reply_page) {
388 il_free_pages(il, cmd->reply_page);
389 cmd->reply_page = 0;
390 }
391out:
392 return ret;
393}
394EXPORT_SYMBOL(il_send_cmd_sync);
395
e7392364
SG
396int
397il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG
398{
399 if (cmd->flags & CMD_ASYNC)
400 return il_send_cmd_async(il, cmd);
401
402 return il_send_cmd_sync(il, cmd);
403}
404EXPORT_SYMBOL(il_send_cmd);
405
406int
407il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data)
408{
409 struct il_host_cmd cmd = {
410 .id = id,
411 .len = len,
412 .data = data,
413 };
414
415 return il_send_cmd_sync(il, &cmd);
416}
417EXPORT_SYMBOL(il_send_cmd_pdu);
418
e7392364
SG
419int
420il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1722f8e1
SG
421 void (*callback) (struct il_priv *il,
422 struct il_device_cmd *cmd,
423 struct il_rx_pkt *pkt))
0cdc2136
SG
424{
425 struct il_host_cmd cmd = {
426 .id = id,
427 .len = len,
428 .data = data,
429 };
430
431 cmd.flags |= CMD_ASYNC;
432 cmd.callback = callback;
433
434 return il_send_cmd_async(il, &cmd);
435}
436EXPORT_SYMBOL(il_send_cmd_pdu_async);
437
438/* default: IL_LED_BLINK(0) using blinking idx table */
439static int led_mode;
440module_param(led_mode, int, S_IRUGO);
e7392364
SG
441MODULE_PARM_DESC(led_mode,
442 "0=system default, " "1=On(RF On)/Off(RF Off), 2=blinking");
0cdc2136
SG
443
444/* Throughput OFF time(ms) ON time (ms)
445 * >300 25 25
446 * >200 to 300 40 40
447 * >100 to 200 55 55
448 * >70 to 100 65 65
449 * >50 to 70 75 75
450 * >20 to 50 85 85
451 * >10 to 20 95 95
452 * >5 to 10 110 110
453 * >1 to 5 130 130
454 * >0 to 1 167 167
455 * <=0 SOLID ON
456 */
457static const struct ieee80211_tpt_blink il_blink[] = {
1722f8e1
SG
458 {.throughput = 0, .blink_time = 334},
459 {.throughput = 1 * 1024 - 1, .blink_time = 260},
460 {.throughput = 5 * 1024 - 1, .blink_time = 220},
461 {.throughput = 10 * 1024 - 1, .blink_time = 190},
462 {.throughput = 20 * 1024 - 1, .blink_time = 170},
463 {.throughput = 50 * 1024 - 1, .blink_time = 150},
464 {.throughput = 70 * 1024 - 1, .blink_time = 130},
465 {.throughput = 100 * 1024 - 1, .blink_time = 110},
466 {.throughput = 200 * 1024 - 1, .blink_time = 80},
467 {.throughput = 300 * 1024 - 1, .blink_time = 50},
0cdc2136
SG
468};
469
470/*
471 * Adjust led blink rate to compensate on a MAC Clock difference on every HW
472 * Led blink rate analysis showed an average deviation of 0% on 3945,
473 * 5% on 4965 HW.
474 * Need to compensate on the led on/off time per HW according to the deviation
475 * to achieve the desired led frequency
476 * The calculation is: (100-averageDeviation)/100 * blinkTime
477 * For code efficiency the calculation will be:
478 * compensation = (100 - averageDeviation) * 64 / 100
479 * NewBlinkTime = (compensation * BlinkTime) / 64
480 */
e7392364
SG
481static inline u8
482il_blink_compensation(struct il_priv *il, u8 time, u16 compensation)
0cdc2136
SG
483{
484 if (!compensation) {
485 IL_ERR("undefined blink compensation: "
e7392364 486 "use pre-defined blinking time\n");
0cdc2136
SG
487 return time;
488 }
489
e7392364 490 return (u8) ((time * compensation) >> 6);
0cdc2136
SG
491}
492
493/* Set led pattern command */
e7392364
SG
494static int
495il_led_cmd(struct il_priv *il, unsigned long on, unsigned long off)
0cdc2136
SG
496{
497 struct il_led_cmd led_cmd = {
498 .id = IL_LED_LINK,
499 .interval = IL_DEF_LED_INTRVL
500 };
501 int ret;
502
503 if (!test_bit(S_READY, &il->status))
504 return -EBUSY;
505
506 if (il->blink_on == on && il->blink_off == off)
507 return 0;
508
509 if (off == 0) {
510 /* led is SOLID_ON */
511 on = IL_LED_SOLID;
512 }
513
514 D_LED("Led blink time compensation=%u\n",
e7392364
SG
515 il->cfg->base_params->led_compensation);
516 led_cmd.on =
517 il_blink_compensation(il, on,
518 il->cfg->base_params->led_compensation);
519 led_cmd.off =
520 il_blink_compensation(il, off,
521 il->cfg->base_params->led_compensation);
0cdc2136
SG
522
523 ret = il->cfg->ops->led->cmd(il, &led_cmd);
524 if (!ret) {
525 il->blink_on = on;
526 il->blink_off = off;
527 }
528 return ret;
529}
530
e7392364
SG
531static void
532il_led_brightness_set(struct led_classdev *led_cdev,
533 enum led_brightness brightness)
0cdc2136
SG
534{
535 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
536 unsigned long on = 0;
537
538 if (brightness > 0)
539 on = IL_LED_SOLID;
540
541 il_led_cmd(il, on, 0);
542}
543
e7392364
SG
544static int
545il_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on,
546 unsigned long *delay_off)
0cdc2136
SG
547{
548 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
549
550 return il_led_cmd(il, *delay_on, *delay_off);
551}
552
e7392364
SG
553void
554il_leds_init(struct il_priv *il)
0cdc2136
SG
555{
556 int mode = led_mode;
557 int ret;
558
559 if (mode == IL_LED_DEFAULT)
560 mode = il->cfg->led_mode;
561
e7392364
SG
562 il->led.name =
563 kasprintf(GFP_KERNEL, "%s-led", wiphy_name(il->hw->wiphy));
0cdc2136
SG
564 il->led.brightness_set = il_led_brightness_set;
565 il->led.blink_set = il_led_blink_set;
566 il->led.max_brightness = 1;
567
568 switch (mode) {
569 case IL_LED_DEFAULT:
570 WARN_ON(1);
571 break;
572 case IL_LED_BLINK:
573 il->led.default_trigger =
e7392364
SG
574 ieee80211_create_tpt_led_trigger(il->hw,
575 IEEE80211_TPT_LEDTRIG_FL_CONNECTED,
576 il_blink,
577 ARRAY_SIZE(il_blink));
0cdc2136
SG
578 break;
579 case IL_LED_RF_STATE:
e7392364 580 il->led.default_trigger = ieee80211_get_radio_led_name(il->hw);
0cdc2136
SG
581 break;
582 }
583
584 ret = led_classdev_register(&il->pci_dev->dev, &il->led);
585 if (ret) {
586 kfree(il->led.name);
587 return;
588 }
589
590 il->led_registered = true;
591}
592EXPORT_SYMBOL(il_leds_init);
593
e7392364
SG
594void
595il_leds_exit(struct il_priv *il)
0cdc2136
SG
596{
597 if (!il->led_registered)
598 return;
599
600 led_classdev_unregister(&il->led);
601 kfree(il->led.name);
602}
603EXPORT_SYMBOL(il_leds_exit);
604
605/************************** EEPROM BANDS ****************************
606 *
607 * The il_eeprom_band definitions below provide the mapping from the
608 * EEPROM contents to the specific channel number supported for each
609 * band.
610 *
611 * For example, il_priv->eeprom.band_3_channels[4] from the band_3
612 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
613 * The specific geography and calibration information for that channel
614 * is contained in the eeprom map itself.
615 *
616 * During init, we copy the eeprom information and channel map
617 * information into il->channel_info_24/52 and il->channel_map_24/52
618 *
619 * channel_map_24/52 provides the idx in the channel_info array for a
620 * given channel. We have to have two separate maps as there is channel
621 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
622 * band_2
623 *
624 * A value of 0xff stored in the channel_map indicates that the channel
625 * is not supported by the hardware at all.
626 *
627 * A value of 0xfe in the channel_map indicates that the channel is not
628 * valid for Tx with the current hardware. This means that
629 * while the system can tune and receive on a given channel, it may not
630 * be able to associate or transmit any frames on that
631 * channel. There is no corresponding channel information for that
632 * entry.
633 *
634 *********************************************************************/
635
636/* 2.4 GHz */
637const u8 il_eeprom_band_1[14] = {
638 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
639};
640
641/* 5.2 GHz bands */
642static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */
643 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
644};
645
646static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */
647 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
648};
649
650static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */
651 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
652};
653
654static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */
655 145, 149, 153, 157, 161, 165
656};
657
e7392364 658static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */
0cdc2136
SG
659 1, 2, 3, 4, 5, 6, 7
660};
661
e7392364 662static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */
0cdc2136
SG
663 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
664};
665
666/******************************************************************************
667 *
668 * EEPROM related functions
669 *
670******************************************************************************/
671
e7392364
SG
672static int
673il_eeprom_verify_signature(struct il_priv *il)
0cdc2136
SG
674{
675 u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
676 int ret = 0;
677
678 D_EEPROM("EEPROM signature=0x%08x\n", gp);
679 switch (gp) {
680 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
681 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
682 break;
683 default:
e7392364 684 IL_ERR("bad EEPROM signature," "EEPROM_GP=0x%08x\n", gp);
0cdc2136
SG
685 ret = -ENOENT;
686 break;
687 }
688 return ret;
689}
690
e7392364
SG
691const u8 *
692il_eeprom_query_addr(const struct il_priv *il, size_t offset)
0cdc2136
SG
693{
694 BUG_ON(offset >= il->cfg->base_params->eeprom_size);
695 return &il->eeprom[offset];
696}
697EXPORT_SYMBOL(il_eeprom_query_addr);
698
e7392364 699u16
1722f8e1 700il_eeprom_query16(const struct il_priv *il, size_t offset)
0cdc2136
SG
701{
702 if (!il->eeprom)
703 return 0;
e7392364 704 return (u16) il->eeprom[offset] | ((u16) il->eeprom[offset + 1] << 8);
0cdc2136
SG
705}
706EXPORT_SYMBOL(il_eeprom_query16);
707
708/**
709 * il_eeprom_init - read EEPROM contents
710 *
711 * Load the EEPROM contents from adapter into il->eeprom
712 *
713 * NOTE: This routine uses the non-debug IO access functions.
714 */
e7392364
SG
715int
716il_eeprom_init(struct il_priv *il)
0cdc2136
SG
717{
718 __le16 *e;
719 u32 gp = _il_rd(il, CSR_EEPROM_GP);
720 int sz;
721 int ret;
722 u16 addr;
723
724 /* allocate eeprom */
725 sz = il->cfg->base_params->eeprom_size;
726 D_EEPROM("NVM size = %d\n", sz);
727 il->eeprom = kzalloc(sz, GFP_KERNEL);
728 if (!il->eeprom) {
729 ret = -ENOMEM;
730 goto alloc_err;
731 }
e7392364 732 e = (__le16 *) il->eeprom;
0cdc2136
SG
733
734 il->cfg->ops->lib->apm_ops.init(il);
735
736 ret = il_eeprom_verify_signature(il);
737 if (ret < 0) {
738 IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
739 ret = -ENOENT;
740 goto err;
741 }
742
743 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
744 ret = il->cfg->ops->lib->eeprom_ops.acquire_semaphore(il);
745 if (ret < 0) {
746 IL_ERR("Failed to acquire EEPROM semaphore.\n");
747 ret = -ENOENT;
748 goto err;
749 }
750
751 /* eeprom is an array of 16bit values */
752 for (addr = 0; addr < sz; addr += sizeof(u16)) {
753 u32 r;
754
755 _il_wr(il, CSR_EEPROM_REG,
e7392364 756 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
0cdc2136 757
e7392364
SG
758 ret =
759 _il_poll_bit(il, CSR_EEPROM_REG,
760 CSR_EEPROM_REG_READ_VALID_MSK,
761 CSR_EEPROM_REG_READ_VALID_MSK,
762 IL_EEPROM_ACCESS_TIMEOUT);
0cdc2136 763 if (ret < 0) {
e7392364 764 IL_ERR("Time out reading EEPROM[%d]\n", addr);
0cdc2136
SG
765 goto done;
766 }
767 r = _il_rd(il, CSR_EEPROM_REG);
768 e[addr / 2] = cpu_to_le16(r >> 16);
769 }
770
e7392364
SG
771 D_EEPROM("NVM Type: %s, version: 0x%x\n", "EEPROM",
772 il_eeprom_query16(il, EEPROM_VERSION));
0cdc2136
SG
773
774 ret = 0;
775done:
776 il->cfg->ops->lib->eeprom_ops.release_semaphore(il);
777
778err:
779 if (ret)
780 il_eeprom_free(il);
781 /* Reset chip to save power until we load uCode during "up". */
782 il_apm_stop(il);
783alloc_err:
784 return ret;
785}
786EXPORT_SYMBOL(il_eeprom_init);
787
e7392364
SG
788void
789il_eeprom_free(struct il_priv *il)
0cdc2136
SG
790{
791 kfree(il->eeprom);
792 il->eeprom = NULL;
793}
794EXPORT_SYMBOL(il_eeprom_free);
795
e7392364
SG
796static void
797il_init_band_reference(const struct il_priv *il, int eep_band,
798 int *eeprom_ch_count,
799 const struct il_eeprom_channel **eeprom_ch_info,
1722f8e1 800 const u8 **eeprom_ch_idx)
0cdc2136 801{
e7392364
SG
802 u32 offset =
803 il->cfg->ops->lib->eeprom_ops.regulatory_bands[eep_band - 1];
0cdc2136
SG
804 switch (eep_band) {
805 case 1: /* 2.4GHz band */
806 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1);
e7392364
SG
807 *eeprom_ch_info =
808 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
809 offset);
0cdc2136
SG
810 *eeprom_ch_idx = il_eeprom_band_1;
811 break;
812 case 2: /* 4.9GHz band */
813 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2);
e7392364
SG
814 *eeprom_ch_info =
815 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
816 offset);
0cdc2136
SG
817 *eeprom_ch_idx = il_eeprom_band_2;
818 break;
819 case 3: /* 5.2GHz band */
820 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3);
e7392364
SG
821 *eeprom_ch_info =
822 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
823 offset);
0cdc2136
SG
824 *eeprom_ch_idx = il_eeprom_band_3;
825 break;
826 case 4: /* 5.5GHz band */
827 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4);
e7392364
SG
828 *eeprom_ch_info =
829 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
830 offset);
0cdc2136
SG
831 *eeprom_ch_idx = il_eeprom_band_4;
832 break;
833 case 5: /* 5.7GHz band */
834 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5);
e7392364
SG
835 *eeprom_ch_info =
836 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
837 offset);
0cdc2136
SG
838 *eeprom_ch_idx = il_eeprom_band_5;
839 break;
840 case 6: /* 2.4GHz ht40 channels */
841 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6);
e7392364
SG
842 *eeprom_ch_info =
843 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
844 offset);
0cdc2136
SG
845 *eeprom_ch_idx = il_eeprom_band_6;
846 break;
847 case 7: /* 5 GHz ht40 channels */
848 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7);
e7392364
SG
849 *eeprom_ch_info =
850 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
851 offset);
0cdc2136
SG
852 *eeprom_ch_idx = il_eeprom_band_7;
853 break;
854 default:
855 BUG();
856 }
857}
858
859#define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
860 ? # x " " : "")
861/**
862 * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il.
863 *
864 * Does not set up a command, or touch hardware.
865 */
e7392364
SG
866static int
867il_mod_ht40_chan_info(struct il_priv *il, enum ieee80211_band band, u16 channel,
868 const struct il_eeprom_channel *eeprom_ch,
869 u8 clear_ht40_extension_channel)
0cdc2136
SG
870{
871 struct il_channel_info *ch_info;
872
e7392364
SG
873 ch_info =
874 (struct il_channel_info *)il_get_channel_info(il, band, channel);
0cdc2136
SG
875
876 if (!il_is_channel_valid(ch_info))
877 return -1;
878
879 D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
e7392364
SG
880 " Ad-Hoc %ssupported\n", ch_info->channel,
881 il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
882 CHECK_AND_PRINT(IBSS), CHECK_AND_PRINT(ACTIVE),
883 CHECK_AND_PRINT(RADAR), CHECK_AND_PRINT(WIDE),
884 CHECK_AND_PRINT(DFS), eeprom_ch->flags,
885 eeprom_ch->max_power_avg,
886 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) &&
887 !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" : "not ");
0cdc2136
SG
888
889 ch_info->ht40_eeprom = *eeprom_ch;
890 ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
891 ch_info->ht40_flags = eeprom_ch->flags;
892 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
893 ch_info->ht40_extension_channel &=
e7392364 894 ~clear_ht40_extension_channel;
0cdc2136
SG
895
896 return 0;
897}
898
899#define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
900 ? # x " " : "")
901
902/**
903 * il_init_channel_map - Set up driver's info for all possible channels
904 */
e7392364
SG
905int
906il_init_channel_map(struct il_priv *il)
0cdc2136
SG
907{
908 int eeprom_ch_count = 0;
909 const u8 *eeprom_ch_idx = NULL;
910 const struct il_eeprom_channel *eeprom_ch_info = NULL;
911 int band, ch;
912 struct il_channel_info *ch_info;
913
914 if (il->channel_count) {
915 D_EEPROM("Channel map already initialized.\n");
916 return 0;
917 }
918
919 D_EEPROM("Initializing regulatory info from EEPROM\n");
920
921 il->channel_count =
e7392364
SG
922 ARRAY_SIZE(il_eeprom_band_1) + ARRAY_SIZE(il_eeprom_band_2) +
923 ARRAY_SIZE(il_eeprom_band_3) + ARRAY_SIZE(il_eeprom_band_4) +
0cdc2136
SG
924 ARRAY_SIZE(il_eeprom_band_5);
925
e7392364 926 D_EEPROM("Parsing data for %d channels.\n", il->channel_count);
0cdc2136 927
e7392364
SG
928 il->channel_info =
929 kzalloc(sizeof(struct il_channel_info) * il->channel_count,
930 GFP_KERNEL);
0cdc2136
SG
931 if (!il->channel_info) {
932 IL_ERR("Could not allocate channel_info\n");
933 il->channel_count = 0;
934 return -ENOMEM;
935 }
936
937 ch_info = il->channel_info;
938
939 /* Loop through the 5 EEPROM bands adding them in order to the
940 * channel map we maintain (that contains additional information than
941 * what just in the EEPROM) */
942 for (band = 1; band <= 5; band++) {
943
944 il_init_band_reference(il, band, &eeprom_ch_count,
e7392364 945 &eeprom_ch_info, &eeprom_ch_idx);
0cdc2136
SG
946
947 /* Loop through each band adding each of the channels */
948 for (ch = 0; ch < eeprom_ch_count; ch++) {
949 ch_info->channel = eeprom_ch_idx[ch];
e7392364
SG
950 ch_info->band =
951 (band ==
952 1) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
0cdc2136
SG
953
954 /* permanently store EEPROM's channel regulatory flags
955 * and max power in channel info database. */
956 ch_info->eeprom = eeprom_ch_info[ch];
957
958 /* Copy the run-time flags so they are there even on
959 * invalid channels */
960 ch_info->flags = eeprom_ch_info[ch].flags;
961 /* First write that ht40 is not enabled, and then enable
962 * one by one */
963 ch_info->ht40_extension_channel =
e7392364 964 IEEE80211_CHAN_NO_HT40;
0cdc2136
SG
965
966 if (!(il_is_channel_valid(ch_info))) {
e7392364
SG
967 D_EEPROM("Ch. %d Flags %x [%sGHz] - "
968 "No traffic\n", ch_info->channel,
969 ch_info->flags,
970 il_is_channel_a_band(ch_info) ? "5.2" :
971 "2.4");
0cdc2136
SG
972 ch_info++;
973 continue;
974 }
975
976 /* Initialize regulatory-based run-time data */
977 ch_info->max_power_avg = ch_info->curr_txpow =
978 eeprom_ch_info[ch].max_power_avg;
979 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
980 ch_info->min_power = 0;
981
e7392364
SG
982 D_EEPROM("Ch. %d [%sGHz] " "%s%s%s%s%s%s(0x%02x %ddBm):"
983 " Ad-Hoc %ssupported\n", ch_info->channel,
984 il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
985 CHECK_AND_PRINT_I(VALID),
986 CHECK_AND_PRINT_I(IBSS),
987 CHECK_AND_PRINT_I(ACTIVE),
988 CHECK_AND_PRINT_I(RADAR),
989 CHECK_AND_PRINT_I(WIDE),
990 CHECK_AND_PRINT_I(DFS),
991 eeprom_ch_info[ch].flags,
992 eeprom_ch_info[ch].max_power_avg,
993 ((eeprom_ch_info[ch].
994 flags & EEPROM_CHANNEL_IBSS) &&
995 !(eeprom_ch_info[ch].
996 flags & EEPROM_CHANNEL_RADAR)) ? "" :
997 "not ");
0cdc2136
SG
998
999 ch_info++;
1000 }
1001 }
1002
1003 /* Check if we do have HT40 channels */
1004 if (il->cfg->ops->lib->eeprom_ops.regulatory_bands[5] ==
1005 EEPROM_REGULATORY_BAND_NO_HT40 &&
1006 il->cfg->ops->lib->eeprom_ops.regulatory_bands[6] ==
1007 EEPROM_REGULATORY_BAND_NO_HT40)
1008 return 0;
1009
1010 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
1011 for (band = 6; band <= 7; band++) {
1012 enum ieee80211_band ieeeband;
1013
1014 il_init_band_reference(il, band, &eeprom_ch_count,
e7392364 1015 &eeprom_ch_info, &eeprom_ch_idx);
0cdc2136
SG
1016
1017 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
1018 ieeeband =
e7392364 1019 (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
0cdc2136
SG
1020
1021 /* Loop through each band adding each of the channels */
1022 for (ch = 0; ch < eeprom_ch_count; ch++) {
1023 /* Set up driver's info for lower half */
e7392364
SG
1024 il_mod_ht40_chan_info(il, ieeeband, eeprom_ch_idx[ch],
1025 &eeprom_ch_info[ch],
1026 IEEE80211_CHAN_NO_HT40PLUS);
0cdc2136
SG
1027
1028 /* Set up driver's info for upper half */
1029 il_mod_ht40_chan_info(il, ieeeband,
e7392364
SG
1030 eeprom_ch_idx[ch] + 4,
1031 &eeprom_ch_info[ch],
1032 IEEE80211_CHAN_NO_HT40MINUS);
0cdc2136
SG
1033 }
1034 }
1035
1036 return 0;
1037}
1038EXPORT_SYMBOL(il_init_channel_map);
1039
1040/*
1041 * il_free_channel_map - undo allocations in il_init_channel_map
1042 */
e7392364
SG
1043void
1044il_free_channel_map(struct il_priv *il)
0cdc2136
SG
1045{
1046 kfree(il->channel_info);
1047 il->channel_count = 0;
1048}
1049EXPORT_SYMBOL(il_free_channel_map);
1050
1051/**
1052 * il_get_channel_info - Find driver's ilate channel info
1053 *
1054 * Based on band and channel number.
1055 */
e7392364
SG
1056const struct il_channel_info *
1057il_get_channel_info(const struct il_priv *il, enum ieee80211_band band,
1058 u16 channel)
0cdc2136
SG
1059{
1060 int i;
1061
1062 switch (band) {
1063 case IEEE80211_BAND_5GHZ:
1064 for (i = 14; i < il->channel_count; i++) {
1065 if (il->channel_info[i].channel == channel)
1066 return &il->channel_info[i];
1067 }
1068 break;
1069 case IEEE80211_BAND_2GHZ:
1070 if (channel >= 1 && channel <= 14)
1071 return &il->channel_info[channel - 1];
1072 break;
1073 default:
1074 BUG();
1075 }
1076
1077 return NULL;
1078}
1079EXPORT_SYMBOL(il_get_channel_info);
1080
1081/*
1082 * Setting power level allows the card to go to sleep when not busy.
1083 *
1084 * We calculate a sleep command based on the required latency, which
1085 * we get from mac80211. In order to handle thermal throttling, we can
1086 * also use pre-defined power levels.
1087 */
1088
1089/*
1090 * This defines the old power levels. They are still used by default
1091 * (level 1) and for thermal throttle (levels 3 through 5)
1092 */
1093
1094struct il_power_vec_entry {
1095 struct il_powertable_cmd cmd;
e7392364 1096 u8 no_dtim; /* number of skip dtim */
0cdc2136
SG
1097};
1098
e7392364
SG
1099static void
1100il_power_sleep_cam_cmd(struct il_priv *il, struct il_powertable_cmd *cmd)
0cdc2136
SG
1101{
1102 memset(cmd, 0, sizeof(*cmd));
1103
1104 if (il->power_data.pci_pm)
1105 cmd->flags |= IL_POWER_PCI_PM_MSK;
1106
1107 D_POWER("Sleep command for CAM\n");
1108}
1109
1110static int
1111il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd)
1112{
1113 D_POWER("Sending power/sleep command\n");
1114 D_POWER("Flags value = 0x%08X\n", cmd->flags);
e7392364
SG
1115 D_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1116 D_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1117 D_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1118 le32_to_cpu(cmd->sleep_interval[0]),
1119 le32_to_cpu(cmd->sleep_interval[1]),
1120 le32_to_cpu(cmd->sleep_interval[2]),
1121 le32_to_cpu(cmd->sleep_interval[3]),
1122 le32_to_cpu(cmd->sleep_interval[4]));
0cdc2136
SG
1123
1124 return il_send_cmd_pdu(il, C_POWER_TBL,
e7392364 1125 sizeof(struct il_powertable_cmd), cmd);
0cdc2136
SG
1126}
1127
1128int
e7392364 1129il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd, bool force)
0cdc2136
SG
1130{
1131 int ret;
1132 bool update_chains;
1133
1134 lockdep_assert_held(&il->mutex);
1135
1136 /* Don't update the RX chain when chain noise calibration is running */
1137 update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE ||
e7392364 1138 il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE;
0cdc2136
SG
1139
1140 if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
1141 return 0;
1142
1143 if (!il_is_ready_rf(il))
1144 return -EIO;
1145
1146 /* scan complete use sleep_power_next, need to be updated */
1147 memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
1148 if (test_bit(S_SCANNING, &il->status) && !force) {
1149 D_INFO("Defer power set mode while scanning\n");
1150 return 0;
1151 }
1152
1153 if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)
1154 set_bit(S_POWER_PMI, &il->status);
1155
1156 ret = il_set_power(il, cmd);
1157 if (!ret) {
1158 if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK))
1159 clear_bit(S_POWER_PMI, &il->status);
1160
1161 if (il->cfg->ops->lib->update_chain_flags && update_chains)
1162 il->cfg->ops->lib->update_chain_flags(il);
1163 else if (il->cfg->ops->lib->update_chain_flags)
e7392364
SG
1164 D_POWER("Cannot update the power, chain noise "
1165 "calibration running: %d\n",
1166 il->chain_noise_data.state);
0cdc2136
SG
1167
1168 memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd));
1169 } else
1170 IL_ERR("set power fail, ret = %d", ret);
1171
1172 return ret;
1173}
1174
e7392364
SG
1175int
1176il_power_update_mode(struct il_priv *il, bool force)
0cdc2136
SG
1177{
1178 struct il_powertable_cmd cmd;
1179
1180 il_power_sleep_cam_cmd(il, &cmd);
1181 return il_power_set_mode(il, &cmd, force);
1182}
1183EXPORT_SYMBOL(il_power_update_mode);
1184
1185/* initialize to default */
e7392364
SG
1186void
1187il_power_initialize(struct il_priv *il)
0cdc2136
SG
1188{
1189 u16 lctl = il_pcie_link_ctl(il);
1190
1191 il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
1192
1193 il->power_data.debug_sleep_level_override = -1;
1194
e7392364 1195 memset(&il->power_data.sleep_cmd, 0, sizeof(il->power_data.sleep_cmd));
0cdc2136
SG
1196}
1197EXPORT_SYMBOL(il_power_initialize);
1198
1199/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
1200 * sending probe req. This should be set long enough to hear probe responses
1201 * from more than one AP. */
e7392364 1202#define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
0cdc2136
SG
1203#define IL_ACTIVE_DWELL_TIME_52 (20)
1204
1205#define IL_ACTIVE_DWELL_FACTOR_24GHZ (3)
1206#define IL_ACTIVE_DWELL_FACTOR_52GHZ (2)
1207
1208/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
1209 * Must be set longer than active dwell time.
1210 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
e7392364 1211#define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
0cdc2136
SG
1212#define IL_PASSIVE_DWELL_TIME_52 (10)
1213#define IL_PASSIVE_DWELL_BASE (100)
1214#define IL_CHANNEL_TUNE_TIME 5
1215
e7392364
SG
1216static int
1217il_send_scan_abort(struct il_priv *il)
0cdc2136
SG
1218{
1219 int ret;
1220 struct il_rx_pkt *pkt;
1221 struct il_host_cmd cmd = {
1222 .id = C_SCAN_ABORT,
1223 .flags = CMD_WANT_SKB,
1224 };
1225
1226 /* Exit instantly with error when device is not ready
1227 * to receive scan abort command or it does not perform
1228 * hardware scan currently */
1229 if (!test_bit(S_READY, &il->status) ||
1230 !test_bit(S_GEO_CONFIGURED, &il->status) ||
1231 !test_bit(S_SCAN_HW, &il->status) ||
1232 test_bit(S_FW_ERROR, &il->status) ||
1233 test_bit(S_EXIT_PENDING, &il->status))
1234 return -EIO;
1235
1236 ret = il_send_cmd_sync(il, &cmd);
1237 if (ret)
1238 return ret;
1239
1240 pkt = (struct il_rx_pkt *)cmd.reply_page;
1241 if (pkt->u.status != CAN_ABORT_STATUS) {
1242 /* The scan abort will return 1 for success or
1243 * 2 for "failure". A failure condition can be
1244 * due to simply not being in an active scan which
1245 * can occur if we send the scan abort before we
1246 * the microcode has notified us that a scan is
1247 * completed. */
1248 D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status);
1249 ret = -EIO;
1250 }
1251
1252 il_free_pages(il, cmd.reply_page);
1253 return ret;
1254}
1255
e7392364
SG
1256static void
1257il_complete_scan(struct il_priv *il, bool aborted)
0cdc2136
SG
1258{
1259 /* check if scan was requested from mac80211 */
1260 if (il->scan_request) {
1261 D_SCAN("Complete scan in mac80211\n");
1262 ieee80211_scan_completed(il->hw, aborted);
1263 }
1264
1265 il->scan_vif = NULL;
1266 il->scan_request = NULL;
1267}
1268
e7392364
SG
1269void
1270il_force_scan_end(struct il_priv *il)
0cdc2136
SG
1271{
1272 lockdep_assert_held(&il->mutex);
1273
1274 if (!test_bit(S_SCANNING, &il->status)) {
1275 D_SCAN("Forcing scan end while not scanning\n");
1276 return;
1277 }
1278
1279 D_SCAN("Forcing scan end\n");
1280 clear_bit(S_SCANNING, &il->status);
1281 clear_bit(S_SCAN_HW, &il->status);
1282 clear_bit(S_SCAN_ABORTING, &il->status);
1283 il_complete_scan(il, true);
1284}
1285
e7392364
SG
1286static void
1287il_do_scan_abort(struct il_priv *il)
0cdc2136
SG
1288{
1289 int ret;
1290
1291 lockdep_assert_held(&il->mutex);
1292
1293 if (!test_bit(S_SCANNING, &il->status)) {
1294 D_SCAN("Not performing scan to abort\n");
1295 return;
1296 }
1297
1298 if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) {
1299 D_SCAN("Scan abort in progress\n");
1300 return;
1301 }
1302
1303 ret = il_send_scan_abort(il);
1304 if (ret) {
1305 D_SCAN("Send scan abort failed %d\n", ret);
1306 il_force_scan_end(il);
1307 } else
1308 D_SCAN("Successfully send scan abort\n");
1309}
1310
1311/**
1312 * il_scan_cancel - Cancel any currently executing HW scan
1313 */
e7392364
SG
1314int
1315il_scan_cancel(struct il_priv *il)
0cdc2136
SG
1316{
1317 D_SCAN("Queuing abort scan\n");
1318 queue_work(il->workqueue, &il->abort_scan);
1319 return 0;
1320}
1321EXPORT_SYMBOL(il_scan_cancel);
1322
1323/**
1324 * il_scan_cancel_timeout - Cancel any currently executing HW scan
1325 * @ms: amount of time to wait (in milliseconds) for scan to abort
1326 *
1327 */
e7392364
SG
1328int
1329il_scan_cancel_timeout(struct il_priv *il, unsigned long ms)
0cdc2136
SG
1330{
1331 unsigned long timeout = jiffies + msecs_to_jiffies(ms);
1332
1333 lockdep_assert_held(&il->mutex);
1334
1335 D_SCAN("Scan cancel timeout\n");
1336
1337 il_do_scan_abort(il);
1338
1339 while (time_before_eq(jiffies, timeout)) {
1340 if (!test_bit(S_SCAN_HW, &il->status))
1341 break;
1342 msleep(20);
1343 }
1344
1345 return test_bit(S_SCAN_HW, &il->status);
1346}
1347EXPORT_SYMBOL(il_scan_cancel_timeout);
1348
1349/* Service response to C_SCAN (0x80) */
e7392364
SG
1350static void
1351il_hdl_scan(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG
1352{
1353#ifdef CONFIG_IWLEGACY_DEBUG
1354 struct il_rx_pkt *pkt = rxb_addr(rxb);
1355 struct il_scanreq_notification *notif =
1356 (struct il_scanreq_notification *)pkt->u.raw;
1357
1358 D_SCAN("Scan request status = 0x%x\n", notif->status);
1359#endif
1360}
1361
1362/* Service N_SCAN_START (0x82) */
e7392364
SG
1363static void
1364il_hdl_scan_start(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG
1365{
1366 struct il_rx_pkt *pkt = rxb_addr(rxb);
1367 struct il_scanstart_notification *notif =
1368 (struct il_scanstart_notification *)pkt->u.raw;
1369 il->scan_start_tsf = le32_to_cpu(notif->tsf_low);
e7392364
SG
1370 D_SCAN("Scan start: " "%d [802.11%s] "
1371 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", notif->channel,
1372 notif->band ? "bg" : "a", le32_to_cpu(notif->tsf_high),
1373 le32_to_cpu(notif->tsf_low), notif->status, notif->beacon_timer);
0cdc2136
SG
1374}
1375
1376/* Service N_SCAN_RESULTS (0x83) */
e7392364
SG
1377static void
1378il_hdl_scan_results(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG
1379{
1380#ifdef CONFIG_IWLEGACY_DEBUG
1381 struct il_rx_pkt *pkt = rxb_addr(rxb);
1382 struct il_scanresults_notification *notif =
1383 (struct il_scanresults_notification *)pkt->u.raw;
1384
e7392364
SG
1385 D_SCAN("Scan ch.res: " "%d [802.11%s] " "(TSF: 0x%08X:%08X) - %d "
1386 "elapsed=%lu usec\n", notif->channel, notif->band ? "bg" : "a",
1387 le32_to_cpu(notif->tsf_high), le32_to_cpu(notif->tsf_low),
1388 le32_to_cpu(notif->stats[0]),
1389 le32_to_cpu(notif->tsf_low) - il->scan_start_tsf);
0cdc2136
SG
1390#endif
1391}
1392
1393/* Service N_SCAN_COMPLETE (0x84) */
e7392364
SG
1394static void
1395il_hdl_scan_complete(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG
1396{
1397
1398#ifdef CONFIG_IWLEGACY_DEBUG
1399 struct il_rx_pkt *pkt = rxb_addr(rxb);
1400 struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
1401#endif
1402
e7392364
SG
1403 D_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
1404 scan_notif->scanned_channels, scan_notif->tsf_low,
1405 scan_notif->tsf_high, scan_notif->status);
0cdc2136
SG
1406
1407 /* The HW is no longer scanning */
1408 clear_bit(S_SCAN_HW, &il->status);
1409
1410 D_SCAN("Scan on %sGHz took %dms\n",
e7392364
SG
1411 (il->scan_band == IEEE80211_BAND_2GHZ) ? "2.4" : "5.2",
1412 jiffies_to_msecs(jiffies - il->scan_start));
0cdc2136
SG
1413
1414 queue_work(il->workqueue, &il->scan_completed);
1415}
1416
e7392364
SG
1417void
1418il_setup_rx_scan_handlers(struct il_priv *il)
0cdc2136
SG
1419{
1420 /* scan handlers */
1421 il->handlers[C_SCAN] = il_hdl_scan;
e7392364
SG
1422 il->handlers[N_SCAN_START] = il_hdl_scan_start;
1423 il->handlers[N_SCAN_RESULTS] = il_hdl_scan_results;
1424 il->handlers[N_SCAN_COMPLETE] = il_hdl_scan_complete;
0cdc2136
SG
1425}
1426EXPORT_SYMBOL(il_setup_rx_scan_handlers);
1427
e7392364
SG
1428inline u16
1429il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1430 u8 n_probes)
0cdc2136
SG
1431{
1432 if (band == IEEE80211_BAND_5GHZ)
1433 return IL_ACTIVE_DWELL_TIME_52 +
e7392364 1434 IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
0cdc2136
SG
1435 else
1436 return IL_ACTIVE_DWELL_TIME_24 +
e7392364 1437 IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
0cdc2136
SG
1438}
1439EXPORT_SYMBOL(il_get_active_dwell_time);
1440
e7392364 1441u16
1722f8e1
SG
1442il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1443 struct ieee80211_vif *vif)
0cdc2136
SG
1444{
1445 struct il_rxon_context *ctx = &il->ctx;
1446 u16 value;
1447
e7392364
SG
1448 u16 passive =
1449 (band ==
1450 IEEE80211_BAND_2GHZ) ? IL_PASSIVE_DWELL_BASE +
1451 IL_PASSIVE_DWELL_TIME_24 : IL_PASSIVE_DWELL_BASE +
1452 IL_PASSIVE_DWELL_TIME_52;
0cdc2136
SG
1453
1454 if (il_is_any_associated(il)) {
1455 /*
1456 * If we're associated, we clamp the maximum passive
1457 * dwell time to be 98% of the smallest beacon interval
1458 * (minus 2 * channel tune time)
1459 */
1460 value = ctx->vif ? ctx->vif->bss_conf.beacon_int : 0;
1461 if (value > IL_PASSIVE_DWELL_BASE || !value)
1462 value = IL_PASSIVE_DWELL_BASE;
1463 value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2;
1464 passive = min(value, passive);
1465 }
1466
1467 return passive;
1468}
1469EXPORT_SYMBOL(il_get_passive_dwell_time);
1470
e7392364
SG
1471void
1472il_init_scan_params(struct il_priv *il)
0cdc2136
SG
1473{
1474 u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1;
1475 if (!il->scan_tx_ant[IEEE80211_BAND_5GHZ])
1476 il->scan_tx_ant[IEEE80211_BAND_5GHZ] = ant_idx;
1477 if (!il->scan_tx_ant[IEEE80211_BAND_2GHZ])
1478 il->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx;
1479}
1480EXPORT_SYMBOL(il_init_scan_params);
1481
e7392364
SG
1482static int
1483il_scan_initiate(struct il_priv *il, struct ieee80211_vif *vif)
0cdc2136
SG
1484{
1485 int ret;
1486
1487 lockdep_assert_held(&il->mutex);
1488
1489 if (WARN_ON(!il->cfg->ops->utils->request_scan))
1490 return -EOPNOTSUPP;
1491
1492 cancel_delayed_work(&il->scan_check);
1493
1494 if (!il_is_ready_rf(il)) {
1495 IL_WARN("Request scan called when driver not ready.\n");
1496 return -EIO;
1497 }
1498
1499 if (test_bit(S_SCAN_HW, &il->status)) {
e7392364 1500 D_SCAN("Multiple concurrent scan requests in parallel.\n");
0cdc2136
SG
1501 return -EBUSY;
1502 }
1503
1504 if (test_bit(S_SCAN_ABORTING, &il->status)) {
1505 D_SCAN("Scan request while abort pending.\n");
1506 return -EBUSY;
1507 }
1508
1509 D_SCAN("Starting scan...\n");
1510
1511 set_bit(S_SCANNING, &il->status);
1512 il->scan_start = jiffies;
1513
1514 ret = il->cfg->ops->utils->request_scan(il, vif);
1515 if (ret) {
1516 clear_bit(S_SCANNING, &il->status);
1517 return ret;
1518 }
1519
1520 queue_delayed_work(il->workqueue, &il->scan_check,
1521 IL_SCAN_CHECK_WATCHDOG);
1522
1523 return 0;
1524}
1525
e7392364
SG
1526int
1527il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1528 struct cfg80211_scan_request *req)
0cdc2136
SG
1529{
1530 struct il_priv *il = hw->priv;
1531 int ret;
1532
1533 D_MAC80211("enter\n");
1534
1535 if (req->n_channels == 0)
1536 return -EINVAL;
1537
1538 mutex_lock(&il->mutex);
1539
1540 if (test_bit(S_SCANNING, &il->status)) {
1541 D_SCAN("Scan already in progress.\n");
1542 ret = -EAGAIN;
1543 goto out_unlock;
1544 }
1545
1546 /* mac80211 will only ask for one band at a time */
1547 il->scan_request = req;
1548 il->scan_vif = vif;
1549 il->scan_band = req->channels[0]->band;
1550
1551 ret = il_scan_initiate(il, vif);
1552
1553 D_MAC80211("leave\n");
1554
1555out_unlock:
1556 mutex_unlock(&il->mutex);
1557
1558 return ret;
1559}
1560EXPORT_SYMBOL(il_mac_hw_scan);
1561
e7392364
SG
1562static void
1563il_bg_scan_check(struct work_struct *data)
0cdc2136
SG
1564{
1565 struct il_priv *il =
1566 container_of(data, struct il_priv, scan_check.work);
1567
1568 D_SCAN("Scan check work\n");
1569
1570 /* Since we are here firmware does not finish scan and
1571 * most likely is in bad shape, so we don't bother to
1572 * send abort command, just force scan complete to mac80211 */
1573 mutex_lock(&il->mutex);
1574 il_force_scan_end(il);
1575 mutex_unlock(&il->mutex);
1576}
1577
1578/**
1579 * il_fill_probe_req - fill in all required fields and IE for probe request
1580 */
1581
1582u16
1583il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1722f8e1 1584 const u8 *ta, const u8 *ies, int ie_len, int left)
0cdc2136
SG
1585{
1586 int len = 0;
1587 u8 *pos = NULL;
1588
1589 /* Make sure there is enough space for the probe request,
1590 * two mandatory IEs and the data */
1591 left -= 24;
1592 if (left < 0)
1593 return 0;
1594
1595 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
1596 memcpy(frame->da, il_bcast_addr, ETH_ALEN);
1597 memcpy(frame->sa, ta, ETH_ALEN);
1598 memcpy(frame->bssid, il_bcast_addr, ETH_ALEN);
1599 frame->seq_ctrl = 0;
1600
1601 len += 24;
1602
1603 /* ...next IE... */
1604 pos = &frame->u.probe_req.variable[0];
1605
1606 /* fill in our indirect SSID IE */
1607 left -= 2;
1608 if (left < 0)
1609 return 0;
1610 *pos++ = WLAN_EID_SSID;
1611 *pos++ = 0;
1612
1613 len += 2;
1614
1615 if (WARN_ON(left < ie_len))
1616 return len;
1617
1618 if (ies && ie_len) {
1619 memcpy(pos, ies, ie_len);
1620 len += ie_len;
1621 }
1622
e7392364 1623 return (u16) len;
0cdc2136
SG
1624}
1625EXPORT_SYMBOL(il_fill_probe_req);
1626
e7392364
SG
1627static void
1628il_bg_abort_scan(struct work_struct *work)
0cdc2136
SG
1629{
1630 struct il_priv *il = container_of(work, struct il_priv, abort_scan);
1631
1632 D_SCAN("Abort scan work\n");
1633
1634 /* We keep scan_check work queued in case when firmware will not
1635 * report back scan completed notification */
1636 mutex_lock(&il->mutex);
1637 il_scan_cancel_timeout(il, 200);
1638 mutex_unlock(&il->mutex);
1639}
1640
e7392364
SG
1641static void
1642il_bg_scan_completed(struct work_struct *work)
0cdc2136 1643{
e7392364 1644 struct il_priv *il = container_of(work, struct il_priv, scan_completed);
0cdc2136
SG
1645 bool aborted;
1646
1647 D_SCAN("Completed scan.\n");
1648
1649 cancel_delayed_work(&il->scan_check);
1650
1651 mutex_lock(&il->mutex);
1652
1653 aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status);
1654 if (aborted)
1655 D_SCAN("Aborted scan completed.\n");
1656
1657 if (!test_and_clear_bit(S_SCANNING, &il->status)) {
1658 D_SCAN("Scan already completed.\n");
1659 goto out_settings;
1660 }
1661
1662 il_complete_scan(il, aborted);
1663
1664out_settings:
1665 /* Can we still talk to firmware ? */
1666 if (!il_is_ready_rf(il))
1667 goto out;
1668
1669 /*
1670 * We do not commit power settings while scan is pending,
1671 * do it now if the settings changed.
1672 */
1673 il_power_set_mode(il, &il->power_data.sleep_cmd_next, false);
1674 il_set_tx_power(il, il->tx_power_next, false);
1675
1676 il->cfg->ops->utils->post_scan(il);
1677
1678out:
1679 mutex_unlock(&il->mutex);
1680}
1681
e7392364
SG
1682void
1683il_setup_scan_deferred_work(struct il_priv *il)
0cdc2136
SG
1684{
1685 INIT_WORK(&il->scan_completed, il_bg_scan_completed);
1686 INIT_WORK(&il->abort_scan, il_bg_abort_scan);
1687 INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check);
1688}
1689EXPORT_SYMBOL(il_setup_scan_deferred_work);
1690
e7392364
SG
1691void
1692il_cancel_scan_deferred_work(struct il_priv *il)
0cdc2136
SG
1693{
1694 cancel_work_sync(&il->abort_scan);
1695 cancel_work_sync(&il->scan_completed);
1696
1697 if (cancel_delayed_work_sync(&il->scan_check)) {
1698 mutex_lock(&il->mutex);
1699 il_force_scan_end(il);
1700 mutex_unlock(&il->mutex);
1701 }
1702}
1703EXPORT_SYMBOL(il_cancel_scan_deferred_work);
1704
1705/* il->sta_lock must be held */
e7392364
SG
1706static void
1707il_sta_ucode_activate(struct il_priv *il, u8 sta_id)
0cdc2136
SG
1708{
1709
1710 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE))
e7392364
SG
1711 IL_ERR("ACTIVATE a non DRIVER active station id %u addr %pM\n",
1712 sta_id, il->stations[sta_id].sta.sta.addr);
0cdc2136
SG
1713
1714 if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) {
e7392364
SG
1715 D_ASSOC("STA id %u addr %pM already present"
1716 " in uCode (according to driver)\n", sta_id,
1717 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG
1718 } else {
1719 il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE;
e7392364
SG
1720 D_ASSOC("Added STA id %u addr %pM to uCode\n", sta_id,
1721 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG
1722 }
1723}
1724
e7392364
SG
1725static int
1726il_process_add_sta_resp(struct il_priv *il, struct il_addsta_cmd *addsta,
1727 struct il_rx_pkt *pkt, bool sync)
0cdc2136
SG
1728{
1729 u8 sta_id = addsta->sta.sta_id;
1730 unsigned long flags;
1731 int ret = -EIO;
1732
1733 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
e7392364 1734 IL_ERR("Bad return from C_ADD_STA (0x%08X)\n", pkt->hdr.flags);
0cdc2136
SG
1735 return ret;
1736 }
1737
e7392364 1738 D_INFO("Processing response for adding station %u\n", sta_id);
0cdc2136
SG
1739
1740 spin_lock_irqsave(&il->sta_lock, flags);
1741
1742 switch (pkt->u.add_sta.status) {
1743 case ADD_STA_SUCCESS_MSK:
1744 D_INFO("C_ADD_STA PASSED\n");
1745 il_sta_ucode_activate(il, sta_id);
1746 ret = 0;
1747 break;
1748 case ADD_STA_NO_ROOM_IN_TBL:
e7392364 1749 IL_ERR("Adding station %d failed, no room in table.\n", sta_id);
0cdc2136
SG
1750 break;
1751 case ADD_STA_NO_BLOCK_ACK_RESOURCE:
e7392364
SG
1752 IL_ERR("Adding station %d failed, no block ack resource.\n",
1753 sta_id);
0cdc2136
SG
1754 break;
1755 case ADD_STA_MODIFY_NON_EXIST_STA:
1756 IL_ERR("Attempting to modify non-existing station %d\n",
e7392364 1757 sta_id);
0cdc2136
SG
1758 break;
1759 default:
e7392364 1760 D_ASSOC("Received C_ADD_STA:(0x%08X)\n", pkt->u.add_sta.status);
0cdc2136
SG
1761 break;
1762 }
1763
1764 D_INFO("%s station id %u addr %pM\n",
e7392364
SG
1765 il->stations[sta_id].sta.mode ==
1766 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", sta_id,
1767 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG
1768
1769 /*
1770 * XXX: The MAC address in the command buffer is often changed from
1771 * the original sent to the device. That is, the MAC address
1772 * written to the command buffer often is not the same MAC address
1773 * read from the command buffer when the command returns. This
1774 * issue has not yet been resolved and this debugging is left to
1775 * observe the problem.
1776 */
1777 D_INFO("%s station according to cmd buffer %pM\n",
e7392364
SG
1778 il->stations[sta_id].sta.mode ==
1779 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", addsta->sta.addr);
0cdc2136
SG
1780 spin_unlock_irqrestore(&il->sta_lock, flags);
1781
1782 return ret;
1783}
1784
e7392364
SG
1785static void
1786il_add_sta_callback(struct il_priv *il, struct il_device_cmd *cmd,
1787 struct il_rx_pkt *pkt)
0cdc2136 1788{
e7392364 1789 struct il_addsta_cmd *addsta = (struct il_addsta_cmd *)cmd->cmd.payload;
0cdc2136
SG
1790
1791 il_process_add_sta_resp(il, addsta, pkt, false);
1792
1793}
1794
e7392364
SG
1795int
1796il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags)
0cdc2136
SG
1797{
1798 struct il_rx_pkt *pkt = NULL;
1799 int ret = 0;
1800 u8 data[sizeof(*sta)];
1801 struct il_host_cmd cmd = {
1802 .id = C_ADD_STA,
1803 .flags = flags,
1804 .data = data,
1805 };
1806 u8 sta_id __maybe_unused = sta->sta.sta_id;
1807
e7392364
SG
1808 D_INFO("Adding sta %u (%pM) %ssynchronously\n", sta_id, sta->sta.addr,
1809 flags & CMD_ASYNC ? "a" : "");
0cdc2136
SG
1810
1811 if (flags & CMD_ASYNC)
1812 cmd.callback = il_add_sta_callback;
1813 else {
1814 cmd.flags |= CMD_WANT_SKB;
1815 might_sleep();
1816 }
1817
1818 cmd.len = il->cfg->ops->utils->build_addsta_hcmd(sta, data);
1819 ret = il_send_cmd(il, &cmd);
1820
1821 if (ret || (flags & CMD_ASYNC))
1822 return ret;
1823
1824 if (ret == 0) {
1825 pkt = (struct il_rx_pkt *)cmd.reply_page;
1826 ret = il_process_add_sta_resp(il, sta, pkt, true);
1827 }
1828 il_free_pages(il, cmd.reply_page);
1829
1830 return ret;
1831}
1832EXPORT_SYMBOL(il_send_add_sta);
1833
e7392364
SG
1834static void
1835il_set_ht_add_station(struct il_priv *il, u8 idx, struct ieee80211_sta *sta,
1836 struct il_rxon_context *ctx)
0cdc2136
SG
1837{
1838 struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->ht_cap;
1839 __le32 sta_flags;
1840 u8 mimo_ps_mode;
1841
1842 if (!sta || !sta_ht_inf->ht_supported)
1843 goto done;
1844
1845 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_SM_PS) >> 2;
1846 D_ASSOC("spatial multiplexing power save mode: %s\n",
1722f8e1
SG
1847 (mimo_ps_mode == WLAN_HT_CAP_SM_PS_STATIC) ? "static" :
1848 (mimo_ps_mode == WLAN_HT_CAP_SM_PS_DYNAMIC) ? "dynamic" :
1849 "disabled");
0cdc2136
SG
1850
1851 sta_flags = il->stations[idx].sta.station_flags;
1852
1853 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
1854
1855 switch (mimo_ps_mode) {
1856 case WLAN_HT_CAP_SM_PS_STATIC:
1857 sta_flags |= STA_FLG_MIMO_DIS_MSK;
1858 break;
1859 case WLAN_HT_CAP_SM_PS_DYNAMIC:
1860 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
1861 break;
1862 case WLAN_HT_CAP_SM_PS_DISABLED:
1863 break;
1864 default:
1865 IL_WARN("Invalid MIMO PS mode %d\n", mimo_ps_mode);
1866 break;
1867 }
1868
e7392364
SG
1869 sta_flags |=
1870 cpu_to_le32((u32) sta_ht_inf->
1871 ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
0cdc2136 1872
e7392364
SG
1873 sta_flags |=
1874 cpu_to_le32((u32) sta_ht_inf->
1875 ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
0cdc2136
SG
1876
1877 if (il_is_ht40_tx_allowed(il, ctx, &sta->ht_cap))
1878 sta_flags |= STA_FLG_HT40_EN_MSK;
1879 else
1880 sta_flags &= ~STA_FLG_HT40_EN_MSK;
1881
1882 il->stations[idx].sta.station_flags = sta_flags;
e7392364 1883done:
0cdc2136
SG
1884 return;
1885}
1886
1887/**
1888 * il_prep_station - Prepare station information for addition
1889 *
1890 * should be called with sta_lock held
1891 */
e7392364 1892u8
1722f8e1
SG
1893il_prep_station(struct il_priv *il, struct il_rxon_context *ctx,
1894 const u8 *addr, bool is_ap, struct ieee80211_sta *sta)
0cdc2136
SG
1895{
1896 struct il_station_entry *station;
1897 int i;
1898 u8 sta_id = IL_INVALID_STATION;
1899 u16 rate;
1900
1901 if (is_ap)
1902 sta_id = ctx->ap_sta_id;
1903 else if (is_broadcast_ether_addr(addr))
1904 sta_id = ctx->bcast_sta_id;
1905 else
1906 for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) {
e7392364
SG
1907 if (!compare_ether_addr
1908 (il->stations[i].sta.sta.addr, addr)) {
0cdc2136
SG
1909 sta_id = i;
1910 break;
1911 }
1912
1913 if (!il->stations[i].used &&
1914 sta_id == IL_INVALID_STATION)
1915 sta_id = i;
1916 }
1917
1918 /*
1919 * These two conditions have the same outcome, but keep them
1920 * separate
1921 */
1922 if (unlikely(sta_id == IL_INVALID_STATION))
1923 return sta_id;
1924
1925 /*
1926 * uCode is not able to deal with multiple requests to add a
1927 * station. Keep track if one is in progress so that we do not send
1928 * another.
1929 */
1930 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
e7392364 1931 D_INFO("STA %d already in process of being added.\n", sta_id);
0cdc2136
SG
1932 return sta_id;
1933 }
1934
1935 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
1936 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) &&
1937 !compare_ether_addr(il->stations[sta_id].sta.sta.addr, addr)) {
e7392364
SG
1938 D_ASSOC("STA %d (%pM) already added, not adding again.\n",
1939 sta_id, addr);
0cdc2136
SG
1940 return sta_id;
1941 }
1942
1943 station = &il->stations[sta_id];
1944 station->used = IL_STA_DRIVER_ACTIVE;
e7392364 1945 D_ASSOC("Add STA to driver ID %d: %pM\n", sta_id, addr);
0cdc2136
SG
1946 il->num_stations++;
1947
1948 /* Set up the C_ADD_STA command to send to device */
1949 memset(&station->sta, 0, sizeof(struct il_addsta_cmd));
1950 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
1951 station->sta.mode = 0;
1952 station->sta.sta.sta_id = sta_id;
1953 station->sta.station_flags = ctx->station_flags;
1954 station->ctxid = ctx->ctxid;
1955
1956 if (sta) {
1957 struct il_station_priv_common *sta_priv;
1958
1959 sta_priv = (void *)sta->drv_priv;
1960 sta_priv->ctx = ctx;
1961 }
1962
1963 /*
1964 * OK to call unconditionally, since local stations (IBSS BSSID
1965 * STA and broadcast STA) pass in a NULL sta, and mac80211
1966 * doesn't allow HT IBSS.
1967 */
1968 il_set_ht_add_station(il, sta_id, sta, ctx);
1969
1970 /* 3945 only */
e7392364 1971 rate = (il->band == IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP : RATE_1M_PLCP;
0cdc2136
SG
1972 /* Turn on both antennas for the station... */
1973 station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK);
1974
1975 return sta_id;
1976
1977}
1978EXPORT_SYMBOL_GPL(il_prep_station);
1979
1980#define STA_WAIT_TIMEOUT (HZ/2)
1981
1982/**
1983 * il_add_station_common -
1984 */
1985int
e7392364 1986il_add_station_common(struct il_priv *il, struct il_rxon_context *ctx,
1722f8e1
SG
1987 const u8 *addr, bool is_ap, struct ieee80211_sta *sta,
1988 u8 *sta_id_r)
0cdc2136
SG
1989{
1990 unsigned long flags_spin;
1991 int ret = 0;
1992 u8 sta_id;
1993 struct il_addsta_cmd sta_cmd;
1994
1995 *sta_id_r = 0;
1996 spin_lock_irqsave(&il->sta_lock, flags_spin);
1997 sta_id = il_prep_station(il, ctx, addr, is_ap, sta);
1998 if (sta_id == IL_INVALID_STATION) {
e7392364 1999 IL_ERR("Unable to prepare station %pM for addition\n", addr);
0cdc2136
SG
2000 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2001 return -EINVAL;
2002 }
2003
2004 /*
2005 * uCode is not able to deal with multiple requests to add a
2006 * station. Keep track if one is in progress so that we do not send
2007 * another.
2008 */
2009 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
e7392364 2010 D_INFO("STA %d already in process of being added.\n", sta_id);
0cdc2136
SG
2011 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2012 return -EEXIST;
2013 }
2014
2015 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
2016 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
e7392364 2017 D_ASSOC("STA %d (%pM) already added, not adding again.\n",
0cdc2136
SG
2018 sta_id, addr);
2019 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2020 return -EEXIST;
2021 }
2022
2023 il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS;
2024 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 2025 sizeof(struct il_addsta_cmd));
0cdc2136
SG
2026 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2027
2028 /* Add station to device's station table */
2029 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2030 if (ret) {
2031 spin_lock_irqsave(&il->sta_lock, flags_spin);
2032 IL_ERR("Adding station %pM failed.\n",
e7392364 2033 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG
2034 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
2035 il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
2036 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2037 }
2038 *sta_id_r = sta_id;
2039 return ret;
2040}
2041EXPORT_SYMBOL(il_add_station_common);
2042
2043/**
2044 * il_sta_ucode_deactivate - deactivate ucode status for a station
2045 *
2046 * il->sta_lock must be held
2047 */
e7392364
SG
2048static void
2049il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id)
0cdc2136
SG
2050{
2051 /* Ucode must be active and driver must be non active */
e7392364
SG
2052 if ((il->stations[sta_id].
2053 used & (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) !=
2054 IL_STA_UCODE_ACTIVE)
0cdc2136
SG
2055 IL_ERR("removed non active STA %u\n", sta_id);
2056
2057 il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE;
2058
2059 memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry));
2060 D_ASSOC("Removed STA %u\n", sta_id);
2061}
2062
e7392364
SG
2063static int
2064il_send_remove_station(struct il_priv *il, const u8 * addr, int sta_id,
2065 bool temporary)
0cdc2136
SG
2066{
2067 struct il_rx_pkt *pkt;
2068 int ret;
2069
2070 unsigned long flags_spin;
2071 struct il_rem_sta_cmd rm_sta_cmd;
2072
2073 struct il_host_cmd cmd = {
2074 .id = C_REM_STA,
2075 .len = sizeof(struct il_rem_sta_cmd),
2076 .flags = CMD_SYNC,
2077 .data = &rm_sta_cmd,
2078 };
2079
2080 memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd));
2081 rm_sta_cmd.num_sta = 1;
2082 memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN);
2083
2084 cmd.flags |= CMD_WANT_SKB;
2085
2086 ret = il_send_cmd(il, &cmd);
2087
2088 if (ret)
2089 return ret;
2090
2091 pkt = (struct il_rx_pkt *)cmd.reply_page;
2092 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
e7392364 2093 IL_ERR("Bad return from C_REM_STA (0x%08X)\n", pkt->hdr.flags);
0cdc2136
SG
2094 ret = -EIO;
2095 }
2096
2097 if (!ret) {
2098 switch (pkt->u.rem_sta.status) {
2099 case REM_STA_SUCCESS_MSK:
2100 if (!temporary) {
2101 spin_lock_irqsave(&il->sta_lock, flags_spin);
2102 il_sta_ucode_deactivate(il, sta_id);
2103 spin_unlock_irqrestore(&il->sta_lock,
e7392364 2104 flags_spin);
0cdc2136
SG
2105 }
2106 D_ASSOC("C_REM_STA PASSED\n");
2107 break;
2108 default:
2109 ret = -EIO;
2110 IL_ERR("C_REM_STA failed\n");
2111 break;
2112 }
2113 }
2114 il_free_pages(il, cmd.reply_page);
2115
2116 return ret;
2117}
2118
2119/**
2120 * il_remove_station - Remove driver's knowledge of station.
2121 */
e7392364
SG
2122int
2123il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr)
0cdc2136
SG
2124{
2125 unsigned long flags;
2126
2127 if (!il_is_ready(il)) {
e7392364
SG
2128 D_INFO("Unable to remove station %pM, device not ready.\n",
2129 addr);
0cdc2136
SG
2130 /*
2131 * It is typical for stations to be removed when we are
2132 * going down. Return success since device will be down
2133 * soon anyway
2134 */
2135 return 0;
2136 }
2137
e7392364 2138 D_ASSOC("Removing STA from driver:%d %pM\n", sta_id, addr);
0cdc2136
SG
2139
2140 if (WARN_ON(sta_id == IL_INVALID_STATION))
2141 return -EINVAL;
2142
2143 spin_lock_irqsave(&il->sta_lock, flags);
2144
2145 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) {
e7392364 2146 D_INFO("Removing %pM but non DRIVER active\n", addr);
0cdc2136
SG
2147 goto out_err;
2148 }
2149
2150 if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
e7392364 2151 D_INFO("Removing %pM but non UCODE active\n", addr);
0cdc2136
SG
2152 goto out_err;
2153 }
2154
2155 if (il->stations[sta_id].used & IL_STA_LOCAL) {
2156 kfree(il->stations[sta_id].lq);
2157 il->stations[sta_id].lq = NULL;
2158 }
2159
2160 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
2161
2162 il->num_stations--;
2163
2164 BUG_ON(il->num_stations < 0);
2165
2166 spin_unlock_irqrestore(&il->sta_lock, flags);
2167
2168 return il_send_remove_station(il, addr, sta_id, false);
2169out_err:
2170 spin_unlock_irqrestore(&il->sta_lock, flags);
2171 return -EINVAL;
2172}
2173EXPORT_SYMBOL_GPL(il_remove_station);
2174
2175/**
2176 * il_clear_ucode_stations - clear ucode station table bits
2177 *
2178 * This function clears all the bits in the driver indicating
2179 * which stations are active in the ucode. Call when something
2180 * other than explicit station management would cause this in
2181 * the ucode, e.g. unassociated RXON.
2182 */
e7392364
SG
2183void
2184il_clear_ucode_stations(struct il_priv *il, struct il_rxon_context *ctx)
0cdc2136
SG
2185{
2186 int i;
2187 unsigned long flags_spin;
2188 bool cleared = false;
2189
2190 D_INFO("Clearing ucode stations in driver\n");
2191
2192 spin_lock_irqsave(&il->sta_lock, flags_spin);
2193 for (i = 0; i < il->hw_params.max_stations; i++) {
2194 if (ctx && ctx->ctxid != il->stations[i].ctxid)
2195 continue;
2196
2197 if (il->stations[i].used & IL_STA_UCODE_ACTIVE) {
e7392364 2198 D_INFO("Clearing ucode active for station %d\n", i);
0cdc2136
SG
2199 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2200 cleared = true;
2201 }
2202 }
2203 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2204
2205 if (!cleared)
e7392364 2206 D_INFO("No active stations found to be cleared\n");
0cdc2136
SG
2207}
2208EXPORT_SYMBOL(il_clear_ucode_stations);
2209
2210/**
2211 * il_restore_stations() - Restore driver known stations to device
2212 *
2213 * All stations considered active by driver, but not present in ucode, is
2214 * restored.
2215 *
2216 * Function sleeps.
2217 */
2218void
2219il_restore_stations(struct il_priv *il, struct il_rxon_context *ctx)
2220{
2221 struct il_addsta_cmd sta_cmd;
2222 struct il_link_quality_cmd lq;
2223 unsigned long flags_spin;
2224 int i;
2225 bool found = false;
2226 int ret;
2227 bool send_lq;
2228
2229 if (!il_is_ready(il)) {
e7392364 2230 D_INFO("Not ready yet, not restoring any stations.\n");
0cdc2136
SG
2231 return;
2232 }
2233
2234 D_ASSOC("Restoring all known stations ... start.\n");
2235 spin_lock_irqsave(&il->sta_lock, flags_spin);
2236 for (i = 0; i < il->hw_params.max_stations; i++) {
2237 if (ctx->ctxid != il->stations[i].ctxid)
2238 continue;
2239 if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) &&
2240 !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) {
2241 D_ASSOC("Restoring sta %pM\n",
e7392364 2242 il->stations[i].sta.sta.addr);
0cdc2136
SG
2243 il->stations[i].sta.mode = 0;
2244 il->stations[i].used |= IL_STA_UCODE_INPROGRESS;
2245 found = true;
2246 }
2247 }
2248
2249 for (i = 0; i < il->hw_params.max_stations; i++) {
2250 if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) {
2251 memcpy(&sta_cmd, &il->stations[i].sta,
2252 sizeof(struct il_addsta_cmd));
2253 send_lq = false;
2254 if (il->stations[i].lq) {
2255 memcpy(&lq, il->stations[i].lq,
2256 sizeof(struct il_link_quality_cmd));
2257 send_lq = true;
2258 }
2259 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2260 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2261 if (ret) {
2262 spin_lock_irqsave(&il->sta_lock, flags_spin);
2263 IL_ERR("Adding station %pM failed.\n",
e7392364
SG
2264 il->stations[i].sta.sta.addr);
2265 il->stations[i].used &= ~IL_STA_DRIVER_ACTIVE;
0cdc2136 2266 il->stations[i].used &=
e7392364 2267 ~IL_STA_UCODE_INPROGRESS;
0cdc2136 2268 spin_unlock_irqrestore(&il->sta_lock,
e7392364 2269 flags_spin);
0cdc2136
SG
2270 }
2271 /*
2272 * Rate scaling has already been initialized, send
2273 * current LQ command
2274 */
2275 if (send_lq)
e7392364 2276 il_send_lq_cmd(il, ctx, &lq, CMD_SYNC, true);
0cdc2136
SG
2277 spin_lock_irqsave(&il->sta_lock, flags_spin);
2278 il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS;
2279 }
2280 }
2281
2282 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2283 if (!found)
2284 D_INFO("Restoring all known stations"
e7392364 2285 " .... no stations to be restored.\n");
0cdc2136 2286 else
e7392364 2287 D_INFO("Restoring all known stations" " .... complete.\n");
0cdc2136
SG
2288}
2289EXPORT_SYMBOL(il_restore_stations);
2290
e7392364
SG
2291int
2292il_get_free_ucode_key_idx(struct il_priv *il)
0cdc2136
SG
2293{
2294 int i;
2295
2296 for (i = 0; i < il->sta_key_max_num; i++)
2297 if (!test_and_set_bit(i, &il->ucode_key_table))
2298 return i;
2299
2300 return WEP_INVALID_OFFSET;
2301}
2302EXPORT_SYMBOL(il_get_free_ucode_key_idx);
2303
e7392364
SG
2304void
2305il_dealloc_bcast_stations(struct il_priv *il)
0cdc2136
SG
2306{
2307 unsigned long flags;
2308 int i;
2309
2310 spin_lock_irqsave(&il->sta_lock, flags);
2311 for (i = 0; i < il->hw_params.max_stations; i++) {
2312 if (!(il->stations[i].used & IL_STA_BCAST))
2313 continue;
2314
2315 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2316 il->num_stations--;
2317 BUG_ON(il->num_stations < 0);
2318 kfree(il->stations[i].lq);
2319 il->stations[i].lq = NULL;
2320 }
2321 spin_unlock_irqrestore(&il->sta_lock, flags);
2322}
2323EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations);
2324
2325#ifdef CONFIG_IWLEGACY_DEBUG
e7392364
SG
2326static void
2327il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG
2328{
2329 int i;
2330 D_RATE("lq station id 0x%x\n", lq->sta_id);
e7392364
SG
2331 D_RATE("lq ant 0x%X 0x%X\n", lq->general_params.single_stream_ant_msk,
2332 lq->general_params.dual_stream_ant_msk);
0cdc2136
SG
2333
2334 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
e7392364 2335 D_RATE("lq idx %d 0x%X\n", i, lq->rs_table[i].rate_n_flags);
0cdc2136
SG
2336}
2337#else
e7392364
SG
2338static inline void
2339il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG
2340{
2341}
2342#endif
2343
2344/**
2345 * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity
2346 *
2347 * It sometimes happens when a HT rate has been in use and we
2348 * loose connectivity with AP then mac80211 will first tell us that the
2349 * current channel is not HT anymore before removing the station. In such a
2350 * scenario the RXON flags will be updated to indicate we are not
2351 * communicating HT anymore, but the LQ command may still contain HT rates.
2352 * Test for this to prevent driver from sending LQ command between the time
2353 * RXON flags are updated and when LQ command is updated.
2354 */
e7392364
SG
2355static bool
2356il_is_lq_table_valid(struct il_priv *il, struct il_rxon_context *ctx,
2357 struct il_link_quality_cmd *lq)
0cdc2136
SG
2358{
2359 int i;
2360
2361 if (ctx->ht.enabled)
2362 return true;
2363
c8b03958 2364 D_INFO("Channel %u is not an HT channel\n", il->active.channel);
0cdc2136 2365 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
e7392364
SG
2366 if (le32_to_cpu(lq->rs_table[i].rate_n_flags) & RATE_MCS_HT_MSK) {
2367 D_INFO("idx %d of LQ expects HT channel\n", i);
0cdc2136
SG
2368 return false;
2369 }
2370 }
2371 return true;
2372}
2373
2374/**
2375 * il_send_lq_cmd() - Send link quality command
2376 * @init: This command is sent as part of station initialization right
2377 * after station has been added.
2378 *
2379 * The link quality command is sent as the last step of station creation.
2380 * This is the special case in which init is set and we call a callback in
2381 * this case to clear the state indicating that station creation is in
2382 * progress.
2383 */
e7392364
SG
2384int
2385il_send_lq_cmd(struct il_priv *il, struct il_rxon_context *ctx,
2386 struct il_link_quality_cmd *lq, u8 flags, bool init)
0cdc2136
SG
2387{
2388 int ret = 0;
2389 unsigned long flags_spin;
2390
2391 struct il_host_cmd cmd = {
2392 .id = C_TX_LINK_QUALITY_CMD,
2393 .len = sizeof(struct il_link_quality_cmd),
2394 .flags = flags,
2395 .data = lq,
2396 };
2397
2398 if (WARN_ON(lq->sta_id == IL_INVALID_STATION))
2399 return -EINVAL;
2400
0cdc2136
SG
2401 spin_lock_irqsave(&il->sta_lock, flags_spin);
2402 if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) {
2403 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2404 return -EINVAL;
2405 }
2406 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2407
2408 il_dump_lq_cmd(il, lq);
2409 BUG_ON(init && (cmd.flags & CMD_ASYNC));
2410
2411 if (il_is_lq_table_valid(il, ctx, lq))
2412 ret = il_send_cmd(il, &cmd);
2413 else
2414 ret = -EINVAL;
2415
2416 if (cmd.flags & CMD_ASYNC)
2417 return ret;
2418
2419 if (init) {
2420 D_INFO("init LQ command complete,"
e7392364
SG
2421 " clearing sta addition status for sta %d\n",
2422 lq->sta_id);
0cdc2136
SG
2423 spin_lock_irqsave(&il->sta_lock, flags_spin);
2424 il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
2425 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2426 }
2427 return ret;
2428}
2429EXPORT_SYMBOL(il_send_lq_cmd);
2430
e7392364
SG
2431int
2432il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2433 struct ieee80211_sta *sta)
0cdc2136
SG
2434{
2435 struct il_priv *il = hw->priv;
2436 struct il_station_priv_common *sta_common = (void *)sta->drv_priv;
2437 int ret;
2438
e7392364 2439 D_INFO("received request to remove station %pM\n", sta->addr);
0cdc2136 2440 mutex_lock(&il->mutex);
e7392364 2441 D_INFO("proceeding to remove station %pM\n", sta->addr);
0cdc2136
SG
2442 ret = il_remove_station(il, sta_common->sta_id, sta->addr);
2443 if (ret)
e7392364 2444 IL_ERR("Error removing station %pM\n", sta->addr);
0cdc2136
SG
2445 mutex_unlock(&il->mutex);
2446 return ret;
2447}
2448EXPORT_SYMBOL(il_mac_sta_remove);
2449
2450/************************** RX-FUNCTIONS ****************************/
2451/*
2452 * Rx theory of operation
2453 *
2454 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
2455 * each of which point to Receive Buffers to be filled by the NIC. These get
2456 * used not only for Rx frames, but for any command response or notification
2457 * from the NIC. The driver and NIC manage the Rx buffers by means
2458 * of idxes into the circular buffer.
2459 *
2460 * Rx Queue Indexes
2461 * The host/firmware share two idx registers for managing the Rx buffers.
2462 *
2463 * The READ idx maps to the first position that the firmware may be writing
2464 * to -- the driver can read up to (but not including) this position and get
2465 * good data.
2466 * The READ idx is managed by the firmware once the card is enabled.
2467 *
2468 * The WRITE idx maps to the last position the driver has read from -- the
2469 * position preceding WRITE is the last slot the firmware can place a packet.
2470 *
2471 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
2472 * WRITE = READ.
2473 *
2474 * During initialization, the host sets up the READ queue position to the first
2475 * IDX position, and WRITE to the last (READ - 1 wrapped)
2476 *
2477 * When the firmware places a packet in a buffer, it will advance the READ idx
2478 * and fire the RX interrupt. The driver can then query the READ idx and
2479 * process as many packets as possible, moving the WRITE idx forward as it
2480 * resets the Rx queue buffers with new memory.
2481 *
2482 * The management in the driver is as follows:
2483 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
2484 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
2485 * to replenish the iwl->rxq->rx_free.
2486 * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the
2487 * iwl->rxq is replenished and the READ IDX is updated (updating the
2488 * 'processed' and 'read' driver idxes as well)
2489 * + A received packet is processed and handed to the kernel network stack,
2490 * detached from the iwl->rxq. The driver 'processed' idx is updated.
2491 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
2492 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
2493 * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
2494 * were enough free buffers and RX_STALLED is set it is cleared.
2495 *
2496 *
2497 * Driver sequence:
2498 *
2499 * il_rx_queue_alloc() Allocates rx_free
2500 * il_rx_replenish() Replenishes rx_free list from rx_used, and calls
2501 * il_rx_queue_restock
2502 * il_rx_queue_restock() Moves available buffers from rx_free into Rx
2503 * queue, updates firmware pointers, and updates
2504 * the WRITE idx. If insufficient rx_free buffers
2505 * are available, schedules il_rx_replenish
2506 *
2507 * -- enable interrupts --
2508 * ISR - il_rx() Detach il_rx_bufs from pool up to the
2509 * READ IDX, detaching the SKB from the pool.
2510 * Moves the packet buffer from queue to rx_used.
2511 * Calls il_rx_queue_restock to refill any empty
2512 * slots.
2513 * ...
2514 *
2515 */
2516
2517/**
2518 * il_rx_queue_space - Return number of free slots available in queue.
2519 */
e7392364
SG
2520int
2521il_rx_queue_space(const struct il_rx_queue *q)
0cdc2136
SG
2522{
2523 int s = q->read - q->write;
2524 if (s <= 0)
2525 s += RX_QUEUE_SIZE;
2526 /* keep some buffer to not confuse full and empty queue */
2527 s -= 2;
2528 if (s < 0)
2529 s = 0;
2530 return s;
2531}
2532EXPORT_SYMBOL(il_rx_queue_space);
2533
2534/**
2535 * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue
2536 */
2537void
e7392364 2538il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q)
0cdc2136
SG
2539{
2540 unsigned long flags;
2541 u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg;
2542 u32 reg;
2543
2544 spin_lock_irqsave(&q->lock, flags);
2545
2546 if (q->need_update == 0)
2547 goto exit_unlock;
2548
2549 /* If power-saving is in use, make sure device is awake */
2550 if (test_bit(S_POWER_PMI, &il->status)) {
2551 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2552
2553 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
e7392364
SG
2554 D_INFO("Rx queue requesting wakeup," " GP1 = 0x%x\n",
2555 reg);
0cdc2136 2556 il_set_bit(il, CSR_GP_CNTRL,
e7392364 2557 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
0cdc2136
SG
2558 goto exit_unlock;
2559 }
2560
2561 q->write_actual = (q->write & ~0x7);
e7392364 2562 il_wr(il, rx_wrt_ptr_reg, q->write_actual);
0cdc2136 2563
e7392364 2564 /* Else device is assumed to be awake */
0cdc2136
SG
2565 } else {
2566 /* Device expects a multiple of 8 */
2567 q->write_actual = (q->write & ~0x7);
e7392364 2568 il_wr(il, rx_wrt_ptr_reg, q->write_actual);
0cdc2136
SG
2569 }
2570
2571 q->need_update = 0;
2572
e7392364 2573exit_unlock:
0cdc2136
SG
2574 spin_unlock_irqrestore(&q->lock, flags);
2575}
2576EXPORT_SYMBOL(il_rx_queue_update_write_ptr);
2577
e7392364
SG
2578int
2579il_rx_queue_alloc(struct il_priv *il)
0cdc2136
SG
2580{
2581 struct il_rx_queue *rxq = &il->rxq;
2582 struct device *dev = &il->pci_dev->dev;
2583 int i;
2584
2585 spin_lock_init(&rxq->lock);
2586 INIT_LIST_HEAD(&rxq->rx_free);
2587 INIT_LIST_HEAD(&rxq->rx_used);
2588
2589 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
e7392364
SG
2590 rxq->bd =
2591 dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
2592 GFP_KERNEL);
0cdc2136
SG
2593 if (!rxq->bd)
2594 goto err_bd;
2595
e7392364
SG
2596 rxq->rb_stts =
2597 dma_alloc_coherent(dev, sizeof(struct il_rb_status),
2598 &rxq->rb_stts_dma, GFP_KERNEL);
0cdc2136
SG
2599 if (!rxq->rb_stts)
2600 goto err_rb;
2601
2602 /* Fill the rx_used queue with _all_ of the Rx buffers */
2603 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
2604 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
2605
2606 /* Set us so that we have processed and used all buffers, but have
2607 * not restocked the Rx queue with fresh buffers */
2608 rxq->read = rxq->write = 0;
2609 rxq->write_actual = 0;
2610 rxq->free_count = 0;
2611 rxq->need_update = 0;
2612 return 0;
2613
2614err_rb:
2615 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
2616 rxq->bd_dma);
2617err_bd:
2618 return -ENOMEM;
2619}
e7392364 2620EXPORT_SYMBOL(il_rx_queue_alloc);
0cdc2136 2621
e7392364
SG
2622void
2623il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG
2624{
2625 struct il_rx_pkt *pkt = rxb_addr(rxb);
2626 struct il_spectrum_notification *report = &(pkt->u.spectrum_notif);
2627
2628 if (!report->state) {
e7392364 2629 D_11H("Spectrum Measure Notification: Start\n");
0cdc2136
SG
2630 return;
2631 }
2632
2633 memcpy(&il->measure_report, report, sizeof(*report));
2634 il->measurement_status |= MEASUREMENT_READY;
2635}
2636EXPORT_SYMBOL(il_hdl_spectrum_measurement);
2637
2638/*
2639 * returns non-zero if packet should be dropped
2640 */
e7392364
SG
2641int
2642il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
2643 u32 decrypt_res, struct ieee80211_rx_status *stats)
0cdc2136
SG
2644{
2645 u16 fc = le16_to_cpu(hdr->frame_control);
2646
2647 /*
2648 * All contexts have the same setting here due to it being
2649 * a module parameter, so OK to check any context.
2650 */
c8b03958 2651 if (il->active.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
0cdc2136
SG
2652 return 0;
2653
2654 if (!(fc & IEEE80211_FCTL_PROTECTED))
2655 return 0;
2656
2657 D_RX("decrypt_res:0x%x\n", decrypt_res);
2658 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2659 case RX_RES_STATUS_SEC_TYPE_TKIP:
2660 /* The uCode has got a bad phase 1 Key, pushes the packet.
2661 * Decryption will be done in SW. */
2662 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2663 RX_RES_STATUS_BAD_KEY_TTAK)
2664 break;
2665
2666 case RX_RES_STATUS_SEC_TYPE_WEP:
2667 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2668 RX_RES_STATUS_BAD_ICV_MIC) {
2669 /* bad ICV, the packet is destroyed since the
2670 * decryption is inplace, drop it */
2671 D_RX("Packet destroyed\n");
2672 return -1;
2673 }
2674 case RX_RES_STATUS_SEC_TYPE_CCMP:
2675 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2676 RX_RES_STATUS_DECRYPT_OK) {
2677 D_RX("hw decrypt successfully!!!\n");
2678 stats->flag |= RX_FLAG_DECRYPTED;
2679 }
2680 break;
2681
2682 default:
2683 break;
2684 }
2685 return 0;
2686}
2687EXPORT_SYMBOL(il_set_decrypted_flag);
2688
2689/**
2690 * il_txq_update_write_ptr - Send new write idx to hardware
2691 */
2692void
2693il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq)
2694{
2695 u32 reg = 0;
2696 int txq_id = txq->q.id;
2697
2698 if (txq->need_update == 0)
2699 return;
2700
2701 /* if we're trying to save power */
2702 if (test_bit(S_POWER_PMI, &il->status)) {
2703 /* wake up nic if it's powered down ...
2704 * uCode will wake up, and interrupt us again, so next
2705 * time we'll skip this part. */
2706 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2707
2708 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
e7392364
SG
2709 D_INFO("Tx queue %d requesting wakeup," " GP1 = 0x%x\n",
2710 txq_id, reg);
0cdc2136 2711 il_set_bit(il, CSR_GP_CNTRL,
e7392364 2712 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
0cdc2136
SG
2713 return;
2714 }
2715
e7392364 2716 il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
0cdc2136
SG
2717
2718 /*
2719 * else not in power-save mode,
2720 * uCode will never sleep when we're
2721 * trying to tx (during RFKILL, we're not trying to tx).
2722 */
2723 } else
e7392364 2724 _il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
0cdc2136
SG
2725 txq->need_update = 0;
2726}
2727EXPORT_SYMBOL(il_txq_update_write_ptr);
2728
2729/**
2730 * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
2731 */
e7392364
SG
2732void
2733il_tx_queue_unmap(struct il_priv *il, int txq_id)
0cdc2136
SG
2734{
2735 struct il_tx_queue *txq = &il->txq[txq_id];
2736 struct il_queue *q = &txq->q;
2737
2738 if (q->n_bd == 0)
2739 return;
2740
2741 while (q->write_ptr != q->read_ptr) {
2742 il->cfg->ops->lib->txq_free_tfd(il, txq);
2743 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2744 }
2745}
2746EXPORT_SYMBOL(il_tx_queue_unmap);
2747
2748/**
2749 * il_tx_queue_free - Deallocate DMA queue.
2750 * @txq: Transmit queue to deallocate.
2751 *
2752 * Empty queue by removing and destroying all BD's.
2753 * Free all buffers.
2754 * 0-fill, but do not free "txq" descriptor structure.
2755 */
e7392364
SG
2756void
2757il_tx_queue_free(struct il_priv *il, int txq_id)
0cdc2136
SG
2758{
2759 struct il_tx_queue *txq = &il->txq[txq_id];
2760 struct device *dev = &il->pci_dev->dev;
2761 int i;
2762
2763 il_tx_queue_unmap(il, txq_id);
2764
2765 /* De-alloc array of command/tx buffers */
2766 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
2767 kfree(txq->cmd[i]);
2768
2769 /* De-alloc circular buffer of TFDs */
2770 if (txq->q.n_bd)
e7392364
SG
2771 dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
2772 txq->tfds, txq->q.dma_addr);
0cdc2136
SG
2773
2774 /* De-alloc array of per-TFD driver data */
2775 kfree(txq->txb);
2776 txq->txb = NULL;
2777
2778 /* deallocate arrays */
2779 kfree(txq->cmd);
2780 kfree(txq->meta);
2781 txq->cmd = NULL;
2782 txq->meta = NULL;
2783
2784 /* 0-fill queue descriptor structure */
2785 memset(txq, 0, sizeof(*txq));
2786}
2787EXPORT_SYMBOL(il_tx_queue_free);
2788
2789/**
2790 * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
2791 */
e7392364
SG
2792void
2793il_cmd_queue_unmap(struct il_priv *il)
0cdc2136
SG
2794{
2795 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2796 struct il_queue *q = &txq->q;
2797 int i;
2798
2799 if (q->n_bd == 0)
2800 return;
2801
2802 while (q->read_ptr != q->write_ptr) {
2803 i = il_get_cmd_idx(q, q->read_ptr, 0);
2804
2805 if (txq->meta[i].flags & CMD_MAPPED) {
2806 pci_unmap_single(il->pci_dev,
2807 dma_unmap_addr(&txq->meta[i], mapping),
2808 dma_unmap_len(&txq->meta[i], len),
2809 PCI_DMA_BIDIRECTIONAL);
2810 txq->meta[i].flags = 0;
2811 }
2812
2813 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2814 }
2815
2816 i = q->n_win;
2817 if (txq->meta[i].flags & CMD_MAPPED) {
2818 pci_unmap_single(il->pci_dev,
2819 dma_unmap_addr(&txq->meta[i], mapping),
2820 dma_unmap_len(&txq->meta[i], len),
2821 PCI_DMA_BIDIRECTIONAL);
2822 txq->meta[i].flags = 0;
2823 }
2824}
2825EXPORT_SYMBOL(il_cmd_queue_unmap);
2826
2827/**
2828 * il_cmd_queue_free - Deallocate DMA queue.
2829 * @txq: Transmit queue to deallocate.
2830 *
2831 * Empty queue by removing and destroying all BD's.
2832 * Free all buffers.
2833 * 0-fill, but do not free "txq" descriptor structure.
2834 */
e7392364
SG
2835void
2836il_cmd_queue_free(struct il_priv *il)
0cdc2136
SG
2837{
2838 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2839 struct device *dev = &il->pci_dev->dev;
2840 int i;
2841
2842 il_cmd_queue_unmap(il);
2843
2844 /* De-alloc array of command/tx buffers */
2845 for (i = 0; i <= TFD_CMD_SLOTS; i++)
2846 kfree(txq->cmd[i]);
2847
2848 /* De-alloc circular buffer of TFDs */
2849 if (txq->q.n_bd)
2850 dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
2851 txq->tfds, txq->q.dma_addr);
2852
2853 /* deallocate arrays */
2854 kfree(txq->cmd);
2855 kfree(txq->meta);
2856 txq->cmd = NULL;
2857 txq->meta = NULL;
2858
2859 /* 0-fill queue descriptor structure */
2860 memset(txq, 0, sizeof(*txq));
2861}
2862EXPORT_SYMBOL(il_cmd_queue_free);
2863
2864/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
2865 * DMA services
2866 *
2867 * Theory of operation
2868 *
2869 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
2870 * of buffer descriptors, each of which points to one or more data buffers for
2871 * the device to read from or fill. Driver and device exchange status of each
2872 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
2873 * entries in each circular buffer, to protect against confusing empty and full
2874 * queue states.
2875 *
2876 * The device reads or writes the data in the queues via the device's several
2877 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
2878 *
2879 * For Tx queue, there are low mark and high mark limits. If, after queuing
2880 * the packet for Tx, free space become < low mark, Tx queue stopped. When
2881 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
2882 * Tx queue resumed.
2883 *
2884 * See more detailed info in 4965.h.
2885 ***************************************************/
2886
e7392364
SG
2887int
2888il_queue_space(const struct il_queue *q)
0cdc2136
SG
2889{
2890 int s = q->read_ptr - q->write_ptr;
2891
2892 if (q->read_ptr > q->write_ptr)
2893 s -= q->n_bd;
2894
2895 if (s <= 0)
2896 s += q->n_win;
2897 /* keep some reserve to not confuse empty and full situations */
2898 s -= 2;
2899 if (s < 0)
2900 s = 0;
2901 return s;
2902}
2903EXPORT_SYMBOL(il_queue_space);
2904
2905
2906/**
2907 * il_queue_init - Initialize queue's high/low-water and read/write idxes
2908 */
e7392364
SG
2909static int
2910il_queue_init(struct il_priv *il, struct il_queue *q, int count, int slots_num,
2911 u32 id)
0cdc2136
SG
2912{
2913 q->n_bd = count;
2914 q->n_win = slots_num;
2915 q->id = id;
2916
2917 /* count must be power-of-two size, otherwise il_queue_inc_wrap
2918 * and il_queue_dec_wrap are broken. */
2919 BUG_ON(!is_power_of_2(count));
2920
2921 /* slots_num must be power-of-two size, otherwise
2922 * il_get_cmd_idx is broken. */
2923 BUG_ON(!is_power_of_2(slots_num));
2924
2925 q->low_mark = q->n_win / 4;
2926 if (q->low_mark < 4)
2927 q->low_mark = 4;
2928
2929 q->high_mark = q->n_win / 8;
2930 if (q->high_mark < 2)
2931 q->high_mark = 2;
2932
2933 q->write_ptr = q->read_ptr = 0;
2934
2935 return 0;
2936}
2937
2938/**
2939 * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
2940 */
e7392364
SG
2941static int
2942il_tx_queue_alloc(struct il_priv *il, struct il_tx_queue *txq, u32 id)
0cdc2136
SG
2943{
2944 struct device *dev = &il->pci_dev->dev;
2945 size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
2946
2947 /* Driver ilate data, only for Tx (not command) queues,
2948 * not shared with device. */
2949 if (id != il->cmd_queue) {
2b50b8f5
TM
2950 txq->txb = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(txq->txb[0]),
2951 GFP_KERNEL);
0cdc2136
SG
2952 if (!txq->txb) {
2953 IL_ERR("kmalloc for auxiliary BD "
e7392364 2954 "structures failed\n");
0cdc2136
SG
2955 goto error;
2956 }
2957 } else {
2958 txq->txb = NULL;
2959 }
2960
2961 /* Circular buffer of transmit frame descriptors (TFDs),
2962 * shared with device */
e7392364
SG
2963 txq->tfds =
2964 dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, GFP_KERNEL);
0cdc2136
SG
2965 if (!txq->tfds) {
2966 IL_ERR("pci_alloc_consistent(%zd) failed\n", tfd_sz);
2967 goto error;
2968 }
2969 txq->q.id = id;
2970
2971 return 0;
2972
e7392364 2973error:
0cdc2136
SG
2974 kfree(txq->txb);
2975 txq->txb = NULL;
2976
2977 return -ENOMEM;
2978}
2979
2980/**
2981 * il_tx_queue_init - Allocate and initialize one tx/cmd queue
2982 */
e7392364
SG
2983int
2984il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
2985 u32 txq_id)
0cdc2136
SG
2986{
2987 int i, len;
2988 int ret;
2989 int actual_slots = slots_num;
2990
2991 /*
2992 * Alloc buffer array for commands (Tx or other types of commands).
2993 * For the command queue (#4/#9), allocate command space + one big
2994 * command for scan, since scan command is very huge; the system will
2995 * not have two scans at the same time, so only one is needed.
2996 * For normal Tx queues (all other queues), no super-size command
2997 * space is needed.
2998 */
2999 if (txq_id == il->cmd_queue)
3000 actual_slots++;
3001
e7392364
SG
3002 txq->meta =
3003 kzalloc(sizeof(struct il_cmd_meta) * actual_slots, GFP_KERNEL);
3004 txq->cmd =
3005 kzalloc(sizeof(struct il_device_cmd *) * actual_slots, GFP_KERNEL);
0cdc2136
SG
3006
3007 if (!txq->meta || !txq->cmd)
3008 goto out_free_arrays;
3009
3010 len = sizeof(struct il_device_cmd);
3011 for (i = 0; i < actual_slots; i++) {
3012 /* only happens for cmd queue */
3013 if (i == slots_num)
3014 len = IL_MAX_CMD_SIZE;
3015
3016 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
3017 if (!txq->cmd[i])
3018 goto err;
3019 }
3020
3021 /* Alloc driver data array and TFD circular buffer */
3022 ret = il_tx_queue_alloc(il, txq, txq_id);
3023 if (ret)
3024 goto err;
3025
3026 txq->need_update = 0;
3027
3028 /*
3029 * For the default queues 0-3, set up the swq_id
3030 * already -- all others need to get one later
3031 * (if they need one at all).
3032 */
3033 if (txq_id < 4)
3034 il_set_swq_id(txq, txq_id, txq_id);
3035
3036 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
3037 * il_queue_inc_wrap and il_queue_dec_wrap are broken. */
3038 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
3039
3040 /* Initialize queue's high/low-water marks, and head/tail idxes */
e7392364 3041 il_queue_init(il, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
0cdc2136
SG
3042
3043 /* Tell device where to find queue */
3044 il->cfg->ops->lib->txq_init(il, txq);
3045
3046 return 0;
3047err:
3048 for (i = 0; i < actual_slots; i++)
3049 kfree(txq->cmd[i]);
3050out_free_arrays:
3051 kfree(txq->meta);
3052 kfree(txq->cmd);
3053
3054 return -ENOMEM;
3055}
3056EXPORT_SYMBOL(il_tx_queue_init);
3057
e7392364
SG
3058void
3059il_tx_queue_reset(struct il_priv *il, struct il_tx_queue *txq, int slots_num,
3060 u32 txq_id)
0cdc2136
SG
3061{
3062 int actual_slots = slots_num;
3063
3064 if (txq_id == il->cmd_queue)
3065 actual_slots++;
3066
3067 memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots);
3068
3069 txq->need_update = 0;
3070
3071 /* Initialize queue's high/low-water marks, and head/tail idxes */
e7392364 3072 il_queue_init(il, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
0cdc2136
SG
3073
3074 /* Tell device where to find queue */
3075 il->cfg->ops->lib->txq_init(il, txq);
3076}
3077EXPORT_SYMBOL(il_tx_queue_reset);
3078
3079/*************** HOST COMMAND QUEUE FUNCTIONS *****/
3080
3081/**
3082 * il_enqueue_hcmd - enqueue a uCode command
3083 * @il: device ilate data point
3084 * @cmd: a point to the ucode command structure
3085 *
3086 * The function returns < 0 values to indicate the operation is
3087 * failed. On success, it turns the idx (> 0) of command in the
3088 * command queue.
3089 */
e7392364
SG
3090int
3091il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG
3092{
3093 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
3094 struct il_queue *q = &txq->q;
3095 struct il_device_cmd *out_cmd;
3096 struct il_cmd_meta *out_meta;
3097 dma_addr_t phys_addr;
3098 unsigned long flags;
3099 int len;
3100 u32 idx;
3101 u16 fix_size;
3102
3103 cmd->len = il->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
e7392364 3104 fix_size = (u16) (cmd->len + sizeof(out_cmd->hdr));
0cdc2136
SG
3105
3106 /* If any of the command structures end up being larger than
3107 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
3108 * we will need to increase the size of the TFD entries
3109 * Also, check to see if command buffer should not exceed the size
3110 * of device_cmd and max_cmd_size. */
3111 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
3112 !(cmd->flags & CMD_SIZE_HUGE));
3113 BUG_ON(fix_size > IL_MAX_CMD_SIZE);
3114
3115 if (il_is_rfkill(il) || il_is_ctkill(il)) {
3116 IL_WARN("Not sending command - %s KILL\n",
e7392364 3117 il_is_rfkill(il) ? "RF" : "CT");
0cdc2136
SG
3118 return -EIO;
3119 }
3120
3121 spin_lock_irqsave(&il->hcmd_lock, flags);
3122
3123 if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
3124 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3125
3126 IL_ERR("Restarting adapter due to command queue full\n");
3127 queue_work(il->workqueue, &il->restart);
3128 return -ENOSPC;
3129 }
3130
3131 idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
3132 out_cmd = txq->cmd[idx];
3133 out_meta = &txq->meta[idx];
3134
3135 if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
3136 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3137 return -ENOSPC;
3138 }
3139
3140 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
3141 out_meta->flags = cmd->flags | CMD_MAPPED;
3142 if (cmd->flags & CMD_WANT_SKB)
3143 out_meta->source = cmd;
3144 if (cmd->flags & CMD_ASYNC)
3145 out_meta->callback = cmd->callback;
3146
3147 out_cmd->hdr.cmd = cmd->id;
3148 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
3149
3150 /* At this point, the out_cmd now has all of the incoming cmd
3151 * information */
3152
3153 out_cmd->hdr.flags = 0;
e7392364
SG
3154 out_cmd->hdr.sequence =
3155 cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) | IDX_TO_SEQ(q->write_ptr));
0cdc2136
SG
3156 if (cmd->flags & CMD_SIZE_HUGE)
3157 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
3158 len = sizeof(struct il_device_cmd);
3159 if (idx == TFD_CMD_SLOTS)
3160 len = IL_MAX_CMD_SIZE;
3161
3162#ifdef CONFIG_IWLEGACY_DEBUG
3163 switch (out_cmd->hdr.cmd) {
3164 case C_TX_LINK_QUALITY_CMD:
3165 case C_SENSITIVITY:
e7392364
SG
3166 D_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
3167 "%d bytes at %d[%d]:%d\n",
3168 il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
3169 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
3170 q->write_ptr, idx, il->cmd_queue);
0cdc2136
SG
3171 break;
3172 default:
3173 D_HC("Sending command %s (#%x), seq: 0x%04X, "
e7392364
SG
3174 "%d bytes at %d[%d]:%d\n",
3175 il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
3176 le16_to_cpu(out_cmd->hdr.sequence), fix_size, q->write_ptr,
3177 idx, il->cmd_queue);
0cdc2136
SG
3178 }
3179#endif
3180 txq->need_update = 1;
3181
3182 if (il->cfg->ops->lib->txq_update_byte_cnt_tbl)
3183 /* Set up entry in queue's byte count circular buffer */
3184 il->cfg->ops->lib->txq_update_byte_cnt_tbl(il, txq, 0);
3185
e7392364
SG
3186 phys_addr =
3187 pci_map_single(il->pci_dev, &out_cmd->hdr, fix_size,
3188 PCI_DMA_BIDIRECTIONAL);
0cdc2136
SG
3189 dma_unmap_addr_set(out_meta, mapping, phys_addr);
3190 dma_unmap_len_set(out_meta, len, fix_size);
3191
e7392364
SG
3192 il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq, phys_addr, fix_size,
3193 1, U32_PAD(cmd->len));
0cdc2136
SG
3194
3195 /* Increment and update queue's write idx */
3196 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
3197 il_txq_update_write_ptr(il, txq);
3198
3199 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3200 return idx;
3201}
3202
3203/**
3204 * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
3205 *
3206 * When FW advances 'R' idx, all entries between old and new 'R' idx
3207 * need to be reclaimed. As result, some free space forms. If there is
3208 * enough free space (> low mark), wake the stack that feeds us.
3209 */
e7392364
SG
3210static void
3211il_hcmd_queue_reclaim(struct il_priv *il, int txq_id, int idx, int cmd_idx)
0cdc2136
SG
3212{
3213 struct il_tx_queue *txq = &il->txq[txq_id];
3214 struct il_queue *q = &txq->q;
3215 int nfreed = 0;
3216
3217 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
3218 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
e7392364
SG
3219 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
3220 q->write_ptr, q->read_ptr);
0cdc2136
SG
3221 return;
3222 }
3223
3224 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
3225 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3226
3227 if (nfreed++ > 0) {
3228 IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx,
e7392364 3229 q->write_ptr, q->read_ptr);
0cdc2136
SG
3230 queue_work(il->workqueue, &il->restart);
3231 }
3232
3233 }
3234}
3235
3236/**
3237 * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
3238 * @rxb: Rx buffer to reclaim
3239 *
3240 * If an Rx buffer has an async callback associated with it the callback
3241 * will be executed. The attached skb (if present) will only be freed
3242 * if the callback returns 1
3243 */
3244void
3245il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb)
3246{
3247 struct il_rx_pkt *pkt = rxb_addr(rxb);
3248 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3249 int txq_id = SEQ_TO_QUEUE(sequence);
3250 int idx = SEQ_TO_IDX(sequence);
3251 int cmd_idx;
3252 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
3253 struct il_device_cmd *cmd;
3254 struct il_cmd_meta *meta;
3255 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
3256 unsigned long flags;
3257
3258 /* If a Tx command is being handled and it isn't in the actual
3259 * command queue then there a command routing bug has been introduced
3260 * in the queue management code. */
e7392364
SG
3261 if (WARN
3262 (txq_id != il->cmd_queue,
3263 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
3264 txq_id, il->cmd_queue, sequence, il->txq[il->cmd_queue].q.read_ptr,
3265 il->txq[il->cmd_queue].q.write_ptr)) {
0cdc2136
SG
3266 il_print_hex_error(il, pkt, 32);
3267 return;
3268 }
3269
3270 cmd_idx = il_get_cmd_idx(&txq->q, idx, huge);
3271 cmd = txq->cmd[cmd_idx];
3272 meta = &txq->meta[cmd_idx];
3273
3274 txq->time_stamp = jiffies;
3275
e7392364
SG
3276 pci_unmap_single(il->pci_dev, dma_unmap_addr(meta, mapping),
3277 dma_unmap_len(meta, len), PCI_DMA_BIDIRECTIONAL);
0cdc2136
SG
3278
3279 /* Input error checking is done when commands are added to queue. */
3280 if (meta->flags & CMD_WANT_SKB) {
3281 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
3282 rxb->page = NULL;
3283 } else if (meta->callback)
3284 meta->callback(il, cmd, pkt);
3285
3286 spin_lock_irqsave(&il->hcmd_lock, flags);
3287
3288 il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx);
3289
3290 if (!(meta->flags & CMD_ASYNC)) {
3291 clear_bit(S_HCMD_ACTIVE, &il->status);
3292 D_INFO("Clearing HCMD_ACTIVE for command %s\n",
e7392364 3293 il_get_cmd_string(cmd->hdr.cmd));
0cdc2136
SG
3294 wake_up(&il->wait_command_queue);
3295 }
3296
3297 /* Mark as unmapped */
3298 meta->flags = 0;
3299
3300 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3301}
3302EXPORT_SYMBOL(il_tx_cmd_complete);
be663ab6
WYG
3303
3304MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965");
3305MODULE_VERSION(IWLWIFI_VERSION);
3306MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
3307MODULE_LICENSE("GPL");
3308
3309/*
3310 * set bt_coex_active to true, uCode will do kill/defer
3311 * every time the priority line is asserted (BT is sending signals on the
3312 * priority line in the PCIx).
3313 * set bt_coex_active to false, uCode will ignore the BT activity and
3314 * perform the normal operation
3315 *
3316 * User might experience transmit issue on some platform due to WiFi/BT
3317 * co-exist problem. The possible behaviors are:
3318 * Able to scan and finding all the available AP
3319 * Not able to associate with any AP
3320 * On those platforms, WiFi communication can be restored by set
3321 * "bt_coex_active" module parameter to "false"
3322 *
3323 * default: bt_coex_active = true (BT_COEX_ENABLE)
3324 */
ef33417d 3325static bool bt_coex_active = true;
be663ab6
WYG
3326module_param(bt_coex_active, bool, S_IRUGO);
3327MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
3328
d2ddf621
SG
3329u32 il_debug_level;
3330EXPORT_SYMBOL(il_debug_level);
be663ab6 3331
d2ddf621 3332const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
e7392364 3333EXPORT_SYMBOL(il_bcast_addr);
be663ab6 3334
46bc8d4b 3335/* This function both allocates and initializes hw and il. */
e7392364
SG
3336struct ieee80211_hw *
3337il_alloc_all(struct il_cfg *cfg)
be663ab6 3338{
46bc8d4b 3339 struct il_priv *il;
be663ab6 3340 /* mac80211 allocates memory for this device instance, including
46bc8d4b 3341 * space for this driver's ilate structure */
be663ab6
WYG
3342 struct ieee80211_hw *hw;
3343
e2ebc833 3344 hw = ieee80211_alloc_hw(sizeof(struct il_priv),
be663ab6
WYG
3345 cfg->ops->ieee80211_ops);
3346 if (hw == NULL) {
e7392364 3347 pr_err("%s: Can not allocate network device\n", cfg->name);
be663ab6
WYG
3348 goto out;
3349 }
3350
46bc8d4b
SG
3351 il = hw->priv;
3352 il->hw = hw;
be663ab6
WYG
3353
3354out:
3355 return hw;
3356}
e2ebc833 3357EXPORT_SYMBOL(il_alloc_all);
be663ab6 3358
e7392364
SG
3359#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
3360#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
3361static void
3362il_init_ht_hw_capab(const struct il_priv *il,
3363 struct ieee80211_sta_ht_cap *ht_info,
3364 enum ieee80211_band band)
be663ab6
WYG
3365{
3366 u16 max_bit_rate = 0;
46bc8d4b
SG
3367 u8 rx_chains_num = il->hw_params.rx_chains_num;
3368 u8 tx_chains_num = il->hw_params.tx_chains_num;
be663ab6
WYG
3369
3370 ht_info->cap = 0;
3371 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
3372
3373 ht_info->ht_supported = true;
3374
3375 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
3376 max_bit_rate = MAX_BIT_RATE_20_MHZ;
46bc8d4b 3377 if (il->hw_params.ht40_channel & BIT(band)) {
be663ab6
WYG
3378 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
3379 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
3380 ht_info->mcs.rx_mask[4] = 0x01;
3381 max_bit_rate = MAX_BIT_RATE_40_MHZ;
3382 }
3383
46bc8d4b 3384 if (il->cfg->mod_params->amsdu_size_8K)
be663ab6
WYG
3385 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
3386
3387 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3388 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3389
3390 ht_info->mcs.rx_mask[0] = 0xFF;
3391 if (rx_chains_num >= 2)
3392 ht_info->mcs.rx_mask[1] = 0xFF;
3393 if (rx_chains_num >= 3)
3394 ht_info->mcs.rx_mask[2] = 0xFF;
3395
3396 /* Highest supported Rx data rate */
3397 max_bit_rate *= rx_chains_num;
3398 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
3399 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
3400
3401 /* Tx MCS capabilities */
3402 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
3403 if (tx_chains_num != rx_chains_num) {
3404 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
e7392364
SG
3405 ht_info->mcs.tx_params |=
3406 ((tx_chains_num -
3407 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
be663ab6
WYG
3408 }
3409}
3410
3411/**
e2ebc833 3412 * il_init_geos - Initialize mac80211's geo/channel info based from eeprom
be663ab6 3413 */
e7392364
SG
3414int
3415il_init_geos(struct il_priv *il)
be663ab6 3416{
e2ebc833 3417 struct il_channel_info *ch;
be663ab6
WYG
3418 struct ieee80211_supported_band *sband;
3419 struct ieee80211_channel *channels;
3420 struct ieee80211_channel *geo_ch;
3421 struct ieee80211_rate *rates;
3422 int i = 0;
332704a5 3423 s8 max_tx_power = 0;
be663ab6 3424
46bc8d4b
SG
3425 if (il->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
3426 il->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
58de00a4 3427 D_INFO("Geography modes already initialized.\n");
a6766ccd 3428 set_bit(S_GEO_CONFIGURED, &il->status);
be663ab6
WYG
3429 return 0;
3430 }
3431
e7392364
SG
3432 channels =
3433 kzalloc(sizeof(struct ieee80211_channel) * il->channel_count,
3434 GFP_KERNEL);
be663ab6
WYG
3435 if (!channels)
3436 return -ENOMEM;
3437
e7392364
SG
3438 rates =
3439 kzalloc((sizeof(struct ieee80211_rate) * RATE_COUNT_LEGACY),
3440 GFP_KERNEL);
be663ab6
WYG
3441 if (!rates) {
3442 kfree(channels);
3443 return -ENOMEM;
3444 }
3445
3446 /* 5.2GHz channels start after the 2.4GHz channels */
46bc8d4b 3447 sband = &il->bands[IEEE80211_BAND_5GHZ];
d2ddf621 3448 sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)];
be663ab6 3449 /* just OFDM */
e2ebc833 3450 sband->bitrates = &rates[IL_FIRST_OFDM_RATE];
2eb05816 3451 sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE;
be663ab6 3452
46bc8d4b 3453 if (il->cfg->sku & IL_SKU_N)
e7392364 3454 il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_5GHZ);
be663ab6 3455
46bc8d4b 3456 sband = &il->bands[IEEE80211_BAND_2GHZ];
be663ab6
WYG
3457 sband->channels = channels;
3458 /* OFDM & CCK */
3459 sband->bitrates = rates;
2eb05816 3460 sband->n_bitrates = RATE_COUNT_LEGACY;
be663ab6 3461
46bc8d4b 3462 if (il->cfg->sku & IL_SKU_N)
e7392364 3463 il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_2GHZ);
be663ab6 3464
46bc8d4b
SG
3465 il->ieee_channels = channels;
3466 il->ieee_rates = rates;
be663ab6 3467
e7392364 3468 for (i = 0; i < il->channel_count; i++) {
46bc8d4b 3469 ch = &il->channel_info[i];
be663ab6 3470
e2ebc833 3471 if (!il_is_channel_valid(ch))
be663ab6
WYG
3472 continue;
3473
46bc8d4b 3474 sband = &il->bands[ch->band];
be663ab6
WYG
3475
3476 geo_ch = &sband->channels[sband->n_channels++];
3477
3478 geo_ch->center_freq =
e7392364 3479 ieee80211_channel_to_frequency(ch->channel, ch->band);
be663ab6
WYG
3480 geo_ch->max_power = ch->max_power_avg;
3481 geo_ch->max_antenna_gain = 0xff;
3482 geo_ch->hw_value = ch->channel;
3483
e2ebc833 3484 if (il_is_channel_valid(ch)) {
be663ab6
WYG
3485 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
3486 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
3487
3488 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
3489 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
3490
3491 if (ch->flags & EEPROM_CHANNEL_RADAR)
3492 geo_ch->flags |= IEEE80211_CHAN_RADAR;
3493
3494 geo_ch->flags |= ch->ht40_extension_channel;
3495
332704a5
SG
3496 if (ch->max_power_avg > max_tx_power)
3497 max_tx_power = ch->max_power_avg;
be663ab6
WYG
3498 } else {
3499 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
3500 }
3501
e7392364
SG
3502 D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", ch->channel,
3503 geo_ch->center_freq,
3504 il_is_channel_a_band(ch) ? "5.2" : "2.4",
3505 geo_ch->
3506 flags & IEEE80211_CHAN_DISABLED ? "restricted" : "valid",
3507 geo_ch->flags);
be663ab6
WYG
3508 }
3509
46bc8d4b
SG
3510 il->tx_power_device_lmt = max_tx_power;
3511 il->tx_power_user_lmt = max_tx_power;
3512 il->tx_power_next = max_tx_power;
332704a5 3513
232913b5
SG
3514 if (il->bands[IEEE80211_BAND_5GHZ].n_channels == 0 &&
3515 (il->cfg->sku & IL_SKU_A)) {
9406f797 3516 IL_INFO("Incorrectly detected BG card as ABG. "
be663ab6 3517 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
e7392364 3518 il->pci_dev->device, il->pci_dev->subsystem_device);
46bc8d4b 3519 il->cfg->sku &= ~IL_SKU_A;
be663ab6
WYG
3520 }
3521
9406f797 3522 IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n",
e7392364
SG
3523 il->bands[IEEE80211_BAND_2GHZ].n_channels,
3524 il->bands[IEEE80211_BAND_5GHZ].n_channels);
be663ab6 3525
a6766ccd 3526 set_bit(S_GEO_CONFIGURED, &il->status);
be663ab6
WYG
3527
3528 return 0;
3529}
e2ebc833 3530EXPORT_SYMBOL(il_init_geos);
be663ab6
WYG
3531
3532/*
e2ebc833 3533 * il_free_geos - undo allocations in il_init_geos
be663ab6 3534 */
e7392364
SG
3535void
3536il_free_geos(struct il_priv *il)
be663ab6 3537{
46bc8d4b
SG
3538 kfree(il->ieee_channels);
3539 kfree(il->ieee_rates);
a6766ccd 3540 clear_bit(S_GEO_CONFIGURED, &il->status);
be663ab6 3541}
e2ebc833 3542EXPORT_SYMBOL(il_free_geos);
be663ab6 3543
e7392364
SG
3544static bool
3545il_is_channel_extension(struct il_priv *il, enum ieee80211_band band,
3546 u16 channel, u8 extension_chan_offset)
be663ab6 3547{
e2ebc833 3548 const struct il_channel_info *ch_info;
be663ab6 3549
46bc8d4b 3550 ch_info = il_get_channel_info(il, band, channel);
e2ebc833 3551 if (!il_is_channel_valid(ch_info))
be663ab6
WYG
3552 return false;
3553
3554 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
e7392364
SG
3555 return !(ch_info->
3556 ht40_extension_channel & IEEE80211_CHAN_NO_HT40PLUS);
be663ab6 3557 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
e7392364
SG
3558 return !(ch_info->
3559 ht40_extension_channel & IEEE80211_CHAN_NO_HT40MINUS);
be663ab6
WYG
3560
3561 return false;
3562}
3563
e7392364 3564bool
1722f8e1
SG
3565il_is_ht40_tx_allowed(struct il_priv *il, struct il_rxon_context *ctx,
3566 struct ieee80211_sta_ht_cap *ht_cap)
be663ab6
WYG
3567{
3568 if (!ctx->ht.enabled || !ctx->ht.is_40mhz)
3569 return false;
3570
3571 /*
3572 * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
3573 * the bit will not set if it is pure 40MHz case
3574 */
3575 if (ht_cap && !ht_cap->ht_supported)
3576 return false;
3577
d3175167 3578#ifdef CONFIG_IWLEGACY_DEBUGFS
46bc8d4b 3579 if (il->disable_ht40)
be663ab6
WYG
3580 return false;
3581#endif
3582
46bc8d4b 3583 return il_is_channel_extension(il, il->band,
c8b03958 3584 le16_to_cpu(il->staging.channel),
e7392364 3585 ctx->ht.extension_chan_offset);
be663ab6 3586}
e2ebc833 3587EXPORT_SYMBOL(il_is_ht40_tx_allowed);
be663ab6 3588
e7392364
SG
3589static u16
3590il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
be663ab6
WYG
3591{
3592 u16 new_val;
3593 u16 beacon_factor;
3594
3595 /*
3596 * If mac80211 hasn't given us a beacon interval, program
3597 * the default into the device.
3598 */
3599 if (!beacon_val)
3600 return DEFAULT_BEACON_INTERVAL;
3601
3602 /*
3603 * If the beacon interval we obtained from the peer
3604 * is too large, we'll have to wake up more often
3605 * (and in IBSS case, we'll beacon too much)
3606 *
3607 * For example, if max_beacon_val is 4096, and the
3608 * requested beacon interval is 7000, we'll have to
3609 * use 3500 to be able to wake up on the beacons.
3610 *
3611 * This could badly influence beacon detection stats.
3612 */
3613
3614 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
3615 new_val = beacon_val / beacon_factor;
3616
3617 if (!new_val)
3618 new_val = max_beacon_val;
3619
3620 return new_val;
3621}
3622
3623int
46bc8d4b 3624il_send_rxon_timing(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6
WYG
3625{
3626 u64 tsf;
3627 s32 interval_tm, rem;
3628 struct ieee80211_conf *conf = NULL;
3629 u16 beacon_int;
3630 struct ieee80211_vif *vif = ctx->vif;
3631
6278ddab 3632 conf = &il->hw->conf;
be663ab6 3633
46bc8d4b 3634 lockdep_assert_held(&il->mutex);
be663ab6 3635
c8b03958 3636 memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd));
be663ab6 3637
c8b03958
SG
3638 il->timing.timestamp = cpu_to_le64(il->timestamp);
3639 il->timing.listen_interval = cpu_to_le16(conf->listen_interval);
be663ab6
WYG
3640
3641 beacon_int = vif ? vif->bss_conf.beacon_int : 0;
3642
3643 /*
6ce1dc45 3644 * TODO: For IBSS we need to get atim_win from mac80211,
e7392364 3645 * for now just always use 0
be663ab6 3646 */
c8b03958 3647 il->timing.atim_win = 0;
be663ab6 3648
e7392364
SG
3649 beacon_int =
3650 il_adjust_beacon_interval(beacon_int,
3651 il->hw_params.max_beacon_itrvl *
3652 TIME_UNIT);
c8b03958 3653 il->timing.beacon_interval = cpu_to_le16(beacon_int);
be663ab6 3654
e7392364 3655 tsf = il->timestamp; /* tsf is modifed by do_div: copy it */
be663ab6
WYG
3656 interval_tm = beacon_int * TIME_UNIT;
3657 rem = do_div(tsf, interval_tm);
c8b03958 3658 il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
be663ab6 3659
c8b03958 3660 il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1;
be663ab6 3661
e7392364 3662 D_ASSOC("beacon interval %d beacon timer %d beacon tim %d\n",
c8b03958
SG
3663 le16_to_cpu(il->timing.beacon_interval),
3664 le32_to_cpu(il->timing.beacon_init_val),
3665 le16_to_cpu(il->timing.atim_win));
be663ab6 3666
63d0f0c5 3667 return il_send_cmd_pdu(il, C_RXON_TIMING, sizeof(il->timing),
c8b03958 3668 &il->timing);
be663ab6 3669}
e2ebc833 3670EXPORT_SYMBOL(il_send_rxon_timing);
be663ab6
WYG
3671
3672void
e7392364
SG
3673il_set_rxon_hwcrypto(struct il_priv *il, struct il_rxon_context *ctx,
3674 int hw_decrypt)
be663ab6 3675{
c8b03958 3676 struct il_rxon_cmd *rxon = &il->staging;
be663ab6
WYG
3677
3678 if (hw_decrypt)
3679 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
3680 else
3681 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
3682
3683}
e2ebc833 3684EXPORT_SYMBOL(il_set_rxon_hwcrypto);
be663ab6
WYG
3685
3686/* validate RXON structure is valid */
3687int
46bc8d4b 3688il_check_rxon_cmd(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 3689{
c8b03958 3690 struct il_rxon_cmd *rxon = &il->staging;
be663ab6
WYG
3691 bool error = false;
3692
3693 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
3694 if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
9406f797 3695 IL_WARN("check 2.4G: wrong narrow\n");
be663ab6
WYG
3696 error = true;
3697 }
3698 if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
9406f797 3699 IL_WARN("check 2.4G: wrong radar\n");
be663ab6
WYG
3700 error = true;
3701 }
3702 } else {
3703 if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
9406f797 3704 IL_WARN("check 5.2G: not short slot!\n");
be663ab6
WYG
3705 error = true;
3706 }
3707 if (rxon->flags & RXON_FLG_CCK_MSK) {
9406f797 3708 IL_WARN("check 5.2G: CCK!\n");
be663ab6
WYG
3709 error = true;
3710 }
3711 }
3712 if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
9406f797 3713 IL_WARN("mac/bssid mcast!\n");
be663ab6
WYG
3714 error = true;
3715 }
3716
3717 /* make sure basic rates 6Mbps and 1Mbps are supported */
2eb05816
SG
3718 if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 &&
3719 (rxon->cck_basic_rates & RATE_1M_MASK) == 0) {
9406f797 3720 IL_WARN("neither 1 nor 6 are basic\n");
be663ab6
WYG
3721 error = true;
3722 }
3723
3724 if (le16_to_cpu(rxon->assoc_id) > 2007) {
9406f797 3725 IL_WARN("aid > 2007\n");
be663ab6
WYG
3726 error = true;
3727 }
3728
e7392364
SG
3729 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) ==
3730 (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
9406f797 3731 IL_WARN("CCK and short slot\n");
be663ab6
WYG
3732 error = true;
3733 }
3734
e7392364
SG
3735 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) ==
3736 (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
9406f797 3737 IL_WARN("CCK and auto detect");
be663ab6
WYG
3738 error = true;
3739 }
3740
e7392364
SG
3741 if ((rxon->
3742 flags & (RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK)) ==
3743 RXON_FLG_TGG_PROTECT_MSK) {
9406f797 3744 IL_WARN("TGg but no auto-detect\n");
be663ab6
WYG
3745 error = true;
3746 }
3747
3748 if (error)
e7392364 3749 IL_WARN("Tuning to channel %d\n", le16_to_cpu(rxon->channel));
be663ab6
WYG
3750
3751 if (error) {
9406f797 3752 IL_ERR("Invalid RXON\n");
be663ab6
WYG
3753 return -EINVAL;
3754 }
3755 return 0;
3756}
e2ebc833 3757EXPORT_SYMBOL(il_check_rxon_cmd);
be663ab6
WYG
3758
3759/**
e2ebc833 3760 * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
46bc8d4b 3761 * @il: staging_rxon is compared to active_rxon
be663ab6
WYG
3762 *
3763 * If the RXON structure is changing enough to require a new tune,
3764 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
3765 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
3766 */
e7392364
SG
3767int
3768il_full_rxon_required(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 3769{
c8b03958
SG
3770 const struct il_rxon_cmd *staging = &il->staging;
3771 const struct il_rxon_cmd *active = &il->active;
be663ab6
WYG
3772
3773#define CHK(cond) \
3774 if ((cond)) { \
58de00a4 3775 D_INFO("need full RXON - " #cond "\n"); \
be663ab6
WYG
3776 return 1; \
3777 }
3778
3779#define CHK_NEQ(c1, c2) \
3780 if ((c1) != (c2)) { \
58de00a4 3781 D_INFO("need full RXON - " \
be663ab6
WYG
3782 #c1 " != " #c2 " - %d != %d\n", \
3783 (c1), (c2)); \
3784 return 1; \
3785 }
3786
3787 /* These items are only settable from the full RXON command */
c8b03958 3788 CHK(!il_is_associated(il));
be663ab6
WYG
3789 CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr));
3790 CHK(compare_ether_addr(staging->node_addr, active->node_addr));
e7392364
SG
3791 CHK(compare_ether_addr
3792 (staging->wlap_bssid_addr, active->wlap_bssid_addr));
be663ab6
WYG
3793 CHK_NEQ(staging->dev_type, active->dev_type);
3794 CHK_NEQ(staging->channel, active->channel);
3795 CHK_NEQ(staging->air_propagation, active->air_propagation);
3796 CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
3797 active->ofdm_ht_single_stream_basic_rates);
3798 CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
3799 active->ofdm_ht_dual_stream_basic_rates);
3800 CHK_NEQ(staging->assoc_id, active->assoc_id);
3801
3802 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
3803 * be updated with the RXON_ASSOC command -- however only some
3804 * flag transitions are allowed using RXON_ASSOC */
3805
3806 /* Check if we are not switching bands */
3807 CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
3808 active->flags & RXON_FLG_BAND_24G_MSK);
3809
3810 /* Check if we are switching association toggle */
3811 CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
3812 active->filter_flags & RXON_FILTER_ASSOC_MSK);
3813
3814#undef CHK
3815#undef CHK_NEQ
3816
3817 return 0;
3818}
e2ebc833 3819EXPORT_SYMBOL(il_full_rxon_required);
be663ab6 3820
e7392364 3821u8
1722f8e1 3822il_get_lowest_plcp(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6
WYG
3823{
3824 /*
3825 * Assign the lowest rate -- should really get this from
3826 * the beacon skb from mac80211.
3827 */
c8b03958 3828 if (il->staging.flags & RXON_FLG_BAND_24G_MSK)
2eb05816 3829 return RATE_1M_PLCP;
be663ab6 3830 else
2eb05816 3831 return RATE_6M_PLCP;
be663ab6 3832}
e2ebc833 3833EXPORT_SYMBOL(il_get_lowest_plcp);
be663ab6 3834
e7392364
SG
3835static void
3836_il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf,
3837 struct il_rxon_context *ctx)
be663ab6 3838{
c8b03958 3839 struct il_rxon_cmd *rxon = &il->staging;
be663ab6
WYG
3840
3841 if (!ctx->ht.enabled) {
e7392364
SG
3842 rxon->flags &=
3843 ~(RXON_FLG_CHANNEL_MODE_MSK |
3844 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | RXON_FLG_HT40_PROT_MSK
3845 | RXON_FLG_HT_PROT_MSK);
be663ab6
WYG
3846 return;
3847 }
3848
e7392364
SG
3849 rxon->flags |=
3850 cpu_to_le32(ctx->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS);
be663ab6
WYG
3851
3852 /* Set up channel bandwidth:
3853 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
3854 /* clear the HT channel mode before set the mode */
e7392364
SG
3855 rxon->flags &=
3856 ~(RXON_FLG_CHANNEL_MODE_MSK | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
46bc8d4b 3857 if (il_is_ht40_tx_allowed(il, ctx, NULL)) {
be663ab6 3858 /* pure ht40 */
e7392364 3859 if (ctx->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
be663ab6
WYG
3860 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
3861 /* Note: control channel is opposite of extension channel */
3862 switch (ctx->ht.extension_chan_offset) {
3863 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3864 rxon->flags &=
e7392364 3865 ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG
3866 break;
3867 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
e7392364 3868 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG
3869 break;
3870 }
3871 } else {
3872 /* Note: control channel is opposite of extension channel */
3873 switch (ctx->ht.extension_chan_offset) {
3874 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3875 rxon->flags &=
e7392364 3876 ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
be663ab6
WYG
3877 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3878 break;
3879 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
e7392364 3880 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG
3881 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3882 break;
3883 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
3884 default:
3885 /* channel location only valid if in Mixed mode */
e7392364 3886 IL_ERR("invalid extension channel offset\n");
be663ab6
WYG
3887 break;
3888 }
3889 }
3890 } else {
3891 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
3892 }
3893
46bc8d4b
SG
3894 if (il->cfg->ops->hcmd->set_rxon_chain)
3895 il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
be663ab6 3896
58de00a4 3897 D_ASSOC("rxon flags 0x%X operation mode :0x%X "
e7392364
SG
3898 "extension channel offset 0x%x\n", le32_to_cpu(rxon->flags),
3899 ctx->ht.protection, ctx->ht.extension_chan_offset);
be663ab6
WYG
3900}
3901
e7392364
SG
3902void
3903il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
be663ab6 3904{
17d6e557 3905 _il_set_rxon_ht(il, ht_conf, &il->ctx);
be663ab6 3906}
e2ebc833 3907EXPORT_SYMBOL(il_set_rxon_ht);
be663ab6
WYG
3908
3909/* Return valid, unused, channel for a passive scan to reset the RF */
e7392364
SG
3910u8
3911il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band)
be663ab6 3912{
e2ebc833 3913 const struct il_channel_info *ch_info;
be663ab6
WYG
3914 int i;
3915 u8 channel = 0;
3916 u8 min, max;
be663ab6
WYG
3917
3918 if (band == IEEE80211_BAND_5GHZ) {
3919 min = 14;
46bc8d4b 3920 max = il->channel_count;
be663ab6
WYG
3921 } else {
3922 min = 0;
3923 max = 14;
3924 }
3925
3926 for (i = min; i < max; i++) {
17d6e557 3927 channel = il->channel_info[i].channel;
c8b03958 3928 if (channel == le16_to_cpu(il->staging.channel))
be663ab6
WYG
3929 continue;
3930
46bc8d4b 3931 ch_info = il_get_channel_info(il, band, channel);
e2ebc833 3932 if (il_is_channel_valid(ch_info))
be663ab6
WYG
3933 break;
3934 }
3935
3936 return channel;
3937}
e2ebc833 3938EXPORT_SYMBOL(il_get_single_channel_number);
be663ab6
WYG
3939
3940/**
e2ebc833 3941 * il_set_rxon_channel - Set the band and channel values in staging RXON
be663ab6
WYG
3942 * @ch: requested channel as a pointer to struct ieee80211_channel
3943
3944 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
3945 * in the staging RXON flag structure based on the ch->band
3946 */
3947int
46bc8d4b 3948il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch,
e7392364 3949 struct il_rxon_context *ctx)
be663ab6
WYG
3950{
3951 enum ieee80211_band band = ch->band;
3952 u16 channel = ch->hw_value;
3953
c8b03958 3954 if (le16_to_cpu(il->staging.channel) == channel && il->band == band)
be663ab6
WYG
3955 return 0;
3956
c8b03958 3957 il->staging.channel = cpu_to_le16(channel);
be663ab6 3958 if (band == IEEE80211_BAND_5GHZ)
c8b03958 3959 il->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
be663ab6 3960 else
c8b03958 3961 il->staging.flags |= RXON_FLG_BAND_24G_MSK;
be663ab6 3962
46bc8d4b 3963 il->band = band;
be663ab6 3964
58de00a4 3965 D_INFO("Staging channel set to %d [%d]\n", channel, band);
be663ab6
WYG
3966
3967 return 0;
3968}
e2ebc833 3969EXPORT_SYMBOL(il_set_rxon_channel);
be663ab6 3970
e7392364
SG
3971void
3972il_set_flags_for_band(struct il_priv *il, struct il_rxon_context *ctx,
3973 enum ieee80211_band band, struct ieee80211_vif *vif)
be663ab6
WYG
3974{
3975 if (band == IEEE80211_BAND_5GHZ) {
c8b03958 3976 il->staging.flags &=
e7392364
SG
3977 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
3978 RXON_FLG_CCK_MSK);
c8b03958 3979 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3980 } else {
e2ebc833 3981 /* Copied from il_post_associate() */
be663ab6 3982 if (vif && vif->bss_conf.use_short_slot)
c8b03958 3983 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3984 else
c8b03958 3985 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3986
c8b03958
SG
3987 il->staging.flags |= RXON_FLG_BAND_24G_MSK;
3988 il->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
3989 il->staging.flags &= ~RXON_FLG_CCK_MSK;
be663ab6
WYG
3990 }
3991}
e2ebc833 3992EXPORT_SYMBOL(il_set_flags_for_band);
be663ab6
WYG
3993
3994/*
3995 * initialize rxon structure with default values from eeprom
3996 */
e7392364
SG
3997void
3998il_connection_init_rx_config(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 3999{
e2ebc833 4000 const struct il_channel_info *ch_info;
be663ab6 4001
c8b03958 4002 memset(&il->staging, 0, sizeof(il->staging));
be663ab6
WYG
4003
4004 if (!ctx->vif) {
c8b03958 4005 il->staging.dev_type = ctx->unused_devtype;
be663ab6 4006 } else
e7392364 4007 switch (ctx->vif->type) {
be663ab6 4008
e7392364 4009 case NL80211_IFTYPE_STATION:
c8b03958
SG
4010 il->staging.dev_type = ctx->station_devtype;
4011 il->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
e7392364 4012 break;
be663ab6 4013
e7392364 4014 case NL80211_IFTYPE_ADHOC:
c8b03958
SG
4015 il->staging.dev_type = ctx->ibss_devtype;
4016 il->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
4017 il->staging.filter_flags =
e7392364
SG
4018 RXON_FILTER_BCON_AWARE_MSK |
4019 RXON_FILTER_ACCEPT_GRP_MSK;
4020 break;
be663ab6 4021
e7392364
SG
4022 default:
4023 IL_ERR("Unsupported interface type %d\n",
4024 ctx->vif->type);
4025 break;
4026 }
be663ab6
WYG
4027
4028#if 0
4029 /* TODO: Figure out when short_preamble would be set and cache from
4030 * that */
46bc8d4b 4031 if (!hw_to_local(il->hw)->short_preamble)
c8b03958 4032 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6 4033 else
c8b03958 4034 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6
WYG
4035#endif
4036
e7392364 4037 ch_info =
c8b03958 4038 il_get_channel_info(il, il->band, le16_to_cpu(il->active.channel));
be663ab6
WYG
4039
4040 if (!ch_info)
46bc8d4b 4041 ch_info = &il->channel_info[0];
be663ab6 4042
c8b03958 4043 il->staging.channel = cpu_to_le16(ch_info->channel);
46bc8d4b 4044 il->band = ch_info->band;
be663ab6 4045
46bc8d4b 4046 il_set_flags_for_band(il, ctx, il->band, ctx->vif);
be663ab6 4047
c8b03958 4048 il->staging.ofdm_basic_rates =
e2ebc833 4049 (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
c8b03958 4050 il->staging.cck_basic_rates =
e2ebc833 4051 (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
be663ab6
WYG
4052
4053 /* clear both MIX and PURE40 mode flag */
c8b03958 4054 il->staging.flags &=
e7392364 4055 ~(RXON_FLG_CHANNEL_MODE_MIXED | RXON_FLG_CHANNEL_MODE_PURE_40);
be663ab6 4056 if (ctx->vif)
c8b03958 4057 memcpy(il->staging.node_addr, ctx->vif->addr, ETH_ALEN);
be663ab6 4058
c8b03958
SG
4059 il->staging.ofdm_ht_single_stream_basic_rates = 0xff;
4060 il->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
be663ab6 4061}
e2ebc833 4062EXPORT_SYMBOL(il_connection_init_rx_config);
be663ab6 4063
e7392364
SG
4064void
4065il_set_rate(struct il_priv *il)
be663ab6
WYG
4066{
4067 const struct ieee80211_supported_band *hw = NULL;
4068 struct ieee80211_rate *rate;
be663ab6
WYG
4069 int i;
4070
46bc8d4b 4071 hw = il_get_hw_mode(il, il->band);
be663ab6 4072 if (!hw) {
9406f797 4073 IL_ERR("Failed to set rate: unable to get hw mode\n");
be663ab6
WYG
4074 return;
4075 }
4076
46bc8d4b 4077 il->active_rate = 0;
be663ab6
WYG
4078
4079 for (i = 0; i < hw->n_bitrates; i++) {
4080 rate = &(hw->bitrates[i]);
2eb05816 4081 if (rate->hw_value < RATE_COUNT_LEGACY)
46bc8d4b 4082 il->active_rate |= (1 << rate->hw_value);
be663ab6
WYG
4083 }
4084
58de00a4 4085 D_RATE("Set active_rate = %0x\n", il->active_rate);
be663ab6 4086
c8b03958 4087 il->staging.cck_basic_rates =
e7392364 4088 (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
be663ab6 4089
c8b03958 4090 il->staging.ofdm_basic_rates =
e7392364 4091 (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
be663ab6 4092}
e2ebc833 4093EXPORT_SYMBOL(il_set_rate);
be663ab6 4094
e7392364
SG
4095void
4096il_chswitch_done(struct il_priv *il, bool is_success)
be663ab6 4097{
7c2cde2e 4098 struct il_rxon_context *ctx = &il->ctx;
be663ab6 4099
a6766ccd 4100 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG
4101 return;
4102
a6766ccd 4103 if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
be663ab6 4104 ieee80211_chswitch_done(ctx->vif, is_success);
be663ab6 4105}
e2ebc833 4106EXPORT_SYMBOL(il_chswitch_done);
be663ab6 4107
e7392364
SG
4108void
4109il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4110{
dcae1c64 4111 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4112 struct il_csa_notification *csa = &(pkt->u.csa_notif);
c8b03958 4113 struct il_rxon_cmd *rxon = (void *)&il->active;
be663ab6 4114
a6766ccd 4115 if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
51e65257
SG
4116 return;
4117
46bc8d4b 4118 if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) {
51e65257 4119 rxon->channel = csa->channel;
c8b03958 4120 il->staging.channel = csa->channel;
e7392364 4121 D_11H("CSA notif: channel %d\n", le16_to_cpu(csa->channel));
46bc8d4b 4122 il_chswitch_done(il, true);
51e65257 4123 } else {
9406f797 4124 IL_ERR("CSA notif (fail) : channel %d\n",
e7392364 4125 le16_to_cpu(csa->channel));
46bc8d4b 4126 il_chswitch_done(il, false);
be663ab6
WYG
4127 }
4128}
d2dfb33e 4129EXPORT_SYMBOL(il_hdl_csa);
be663ab6 4130
d3175167 4131#ifdef CONFIG_IWLEGACY_DEBUG
e7392364
SG
4132void
4133il_print_rx_config_cmd(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 4134{
c8b03958 4135 struct il_rxon_cmd *rxon = &il->staging;
be663ab6 4136
58de00a4 4137 D_RADIO("RX CONFIG:\n");
46bc8d4b 4138 il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e7392364 4139 D_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
58de00a4 4140 D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
e7392364 4141 D_RADIO("u32 filter_flags: 0x%08x\n", le32_to_cpu(rxon->filter_flags));
58de00a4 4142 D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
e7392364
SG
4143 D_RADIO("u8 ofdm_basic_rates: 0x%02x\n", rxon->ofdm_basic_rates);
4144 D_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
58de00a4
SG
4145 D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
4146 D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
e7392364 4147 D_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
be663ab6 4148}
e2ebc833 4149EXPORT_SYMBOL(il_print_rx_config_cmd);
be663ab6
WYG
4150#endif
4151/**
e2ebc833 4152 * il_irq_handle_error - called for HW or SW error interrupt from card
be663ab6 4153 */
e7392364
SG
4154void
4155il_irq_handle_error(struct il_priv *il)
be663ab6 4156{
e2ebc833 4157 /* Set the FW error flag -- cleared on il_down */
a6766ccd 4158 set_bit(S_FW_ERROR, &il->status);
be663ab6
WYG
4159
4160 /* Cancel currently queued command. */
a6766ccd 4161 clear_bit(S_HCMD_ACTIVE, &il->status);
be663ab6 4162
e7392364 4163 IL_ERR("Loaded firmware version: %s\n", il->hw->wiphy->fw_version);
be663ab6 4164
46bc8d4b
SG
4165 il->cfg->ops->lib->dump_nic_error_log(il);
4166 if (il->cfg->ops->lib->dump_fh)
4167 il->cfg->ops->lib->dump_fh(il, NULL, false);
d3175167 4168#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4169 if (il_get_debug_level(il) & IL_DL_FW_ERRORS)
e7392364 4170 il_print_rx_config_cmd(il, &il->ctx);
be663ab6
WYG
4171#endif
4172
46bc8d4b 4173 wake_up(&il->wait_command_queue);
be663ab6
WYG
4174
4175 /* Keep the restart process from trying to send host
4176 * commands by clearing the INIT status bit */
a6766ccd 4177 clear_bit(S_READY, &il->status);
be663ab6 4178
a6766ccd 4179 if (!test_bit(S_EXIT_PENDING, &il->status)) {
58de00a4 4180 IL_DBG(IL_DL_FW_ERRORS,
e7392364 4181 "Restarting adapter due to uCode error.\n");
be663ab6 4182
46bc8d4b
SG
4183 if (il->cfg->mod_params->restart_fw)
4184 queue_work(il->workqueue, &il->restart);
be663ab6
WYG
4185 }
4186}
e2ebc833 4187EXPORT_SYMBOL(il_irq_handle_error);
be663ab6 4188
e7392364
SG
4189static int
4190il_apm_stop_master(struct il_priv *il)
be663ab6
WYG
4191{
4192 int ret = 0;
4193
4194 /* stop device's busmaster DMA activity */
46bc8d4b 4195 il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
be663ab6 4196
e7392364
SG
4197 ret =
4198 _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
4199 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
be663ab6 4200 if (ret)
9406f797 4201 IL_WARN("Master Disable Timed Out, 100 usec\n");
be663ab6 4202
58de00a4 4203 D_INFO("stop master\n");
be663ab6
WYG
4204
4205 return ret;
4206}
4207
e7392364
SG
4208void
4209il_apm_stop(struct il_priv *il)
be663ab6 4210{
58de00a4 4211 D_INFO("Stop card, put in low power state\n");
be663ab6
WYG
4212
4213 /* Stop device's DMA activity */
46bc8d4b 4214 il_apm_stop_master(il);
be663ab6
WYG
4215
4216 /* Reset the entire device */
46bc8d4b 4217 il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
be663ab6
WYG
4218
4219 udelay(10);
4220
4221 /*
4222 * Clear "initialization complete" bit to move adapter from
4223 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
4224 */
e7392364 4225 il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
be663ab6 4226}
e7392364 4227EXPORT_SYMBOL(il_apm_stop);
be663ab6
WYG
4228
4229/*
4230 * Start up NIC's basic functionality after it has been reset
e2ebc833 4231 * (e.g. after platform boot, or shutdown via il_apm_stop())
be663ab6
WYG
4232 * NOTE: This does not load uCode nor start the embedded processor
4233 */
e7392364
SG
4234int
4235il_apm_init(struct il_priv *il)
be663ab6
WYG
4236{
4237 int ret = 0;
4238 u16 lctl;
4239
58de00a4 4240 D_INFO("Init card's basic functions\n");
be663ab6
WYG
4241
4242 /*
4243 * Use "set_bit" below rather than "write", to preserve any hardware
4244 * bits already set by default after reset.
4245 */
4246
4247 /* Disable L0S exit timer (platform NMI Work/Around) */
46bc8d4b 4248 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
e7392364 4249 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
be663ab6
WYG
4250
4251 /*
4252 * Disable L0s without affecting L1;
4253 * don't wait for ICH L0s (ICH bug W/A)
4254 */
46bc8d4b 4255 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
e7392364 4256 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
be663ab6
WYG
4257
4258 /* Set FH wait threshold to maximum (HW error during stress W/A) */
e7392364 4259 il_set_bit(il, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
be663ab6
WYG
4260
4261 /*
4262 * Enable HAP INTA (interrupt from management bus) to
4263 * wake device's PCI Express link L1a -> L0s
25985edc 4264 * NOTE: This is no-op for 3945 (non-existent bit)
be663ab6 4265 */
46bc8d4b 4266 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 4267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
be663ab6
WYG
4268
4269 /*
4270 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
4271 * Check if BIOS (or OS) enabled L1-ASPM on this device.
4272 * If so (likely), disable L0S, so device moves directly L0->L1;
4273 * costs negligible amount of power savings.
4274 * If not (unlikely), enable L0S, so there is at least some
4275 * power savings, even without L1.
4276 */
46bc8d4b
SG
4277 if (il->cfg->base_params->set_l0s) {
4278 lctl = il_pcie_link_ctl(il);
be663ab6 4279 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
e7392364 4280 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
be663ab6 4281 /* L1-ASPM enabled; disable(!) L0S */
46bc8d4b 4282 il_set_bit(il, CSR_GIO_REG,
e7392364 4283 CSR_GIO_REG_VAL_L0S_ENABLED);
58de00a4 4284 D_POWER("L1 Enabled; Disabling L0S\n");
be663ab6
WYG
4285 } else {
4286 /* L1-ASPM disabled; enable(!) L0S */
46bc8d4b 4287 il_clear_bit(il, CSR_GIO_REG,
e7392364 4288 CSR_GIO_REG_VAL_L0S_ENABLED);
58de00a4 4289 D_POWER("L1 Disabled; Enabling L0S\n");
be663ab6
WYG
4290 }
4291 }
4292
4293 /* Configure analog phase-lock-loop before activating to D0A */
46bc8d4b
SG
4294 if (il->cfg->base_params->pll_cfg_val)
4295 il_set_bit(il, CSR_ANA_PLL_CFG,
e7392364 4296 il->cfg->base_params->pll_cfg_val);
be663ab6
WYG
4297
4298 /*
4299 * Set "initialization complete" bit to move adapter from
4300 * D0U* --> D0A* (powered-up active) state.
4301 */
46bc8d4b 4302 il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
be663ab6
WYG
4303
4304 /*
4305 * Wait for clock stabilization; once stabilized, access to
db54eb57 4306 * device-internal resources is supported, e.g. il_wr_prph()
be663ab6
WYG
4307 * and accesses to uCode SRAM.
4308 */
e7392364
SG
4309 ret =
4310 _il_poll_bit(il, CSR_GP_CNTRL,
4311 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
4312 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
be663ab6 4313 if (ret < 0) {
58de00a4 4314 D_INFO("Failed to init the card\n");
be663ab6
WYG
4315 goto out;
4316 }
4317
4318 /*
4319 * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
4320 * BSM (Boostrap State Machine) is only in 3945 and 4965.
4321 *
4322 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
4323 * do not disable clocks. This preserves any hardware bits already
4324 * set by default in "CLK_CTRL_REG" after reset.
4325 */
46bc8d4b 4326 if (il->cfg->base_params->use_bsm)
db54eb57 4327 il_wr_prph(il, APMG_CLK_EN_REG,
e7392364 4328 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
be663ab6 4329 else
e7392364 4330 il_wr_prph(il, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
be663ab6
WYG
4331 udelay(20);
4332
4333 /* Disable L1-Active */
46bc8d4b 4334 il_set_bits_prph(il, APMG_PCIDEV_STT_REG,
e7392364 4335 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
be663ab6
WYG
4336
4337out:
4338 return ret;
4339}
e7392364 4340EXPORT_SYMBOL(il_apm_init);
be663ab6 4341
e7392364
SG
4342int
4343il_set_tx_power(struct il_priv *il, s8 tx_power, bool force)
be663ab6
WYG
4344{
4345 int ret;
4346 s8 prev_tx_power;
43f12d47 4347 bool defer;
be663ab6 4348
46bc8d4b 4349 lockdep_assert_held(&il->mutex);
be663ab6 4350
46bc8d4b 4351 if (il->tx_power_user_lmt == tx_power && !force)
be663ab6
WYG
4352 return 0;
4353
46bc8d4b 4354 if (!il->cfg->ops->lib->send_tx_power)
be663ab6
WYG
4355 return -EOPNOTSUPP;
4356
332704a5
SG
4357 /* 0 dBm mean 1 milliwatt */
4358 if (tx_power < 0) {
e7392364 4359 IL_WARN("Requested user TXPOWER %d below 1 mW.\n", tx_power);
be663ab6
WYG
4360 return -EINVAL;
4361 }
4362
46bc8d4b 4363 if (tx_power > il->tx_power_device_lmt) {
e7392364
SG
4364 IL_WARN("Requested user TXPOWER %d above upper limit %d.\n",
4365 tx_power, il->tx_power_device_lmt);
be663ab6
WYG
4366 return -EINVAL;
4367 }
4368
46bc8d4b 4369 if (!il_is_ready_rf(il))
be663ab6
WYG
4370 return -EIO;
4371
43f12d47
SG
4372 /* scan complete and commit_rxon use tx_power_next value,
4373 * it always need to be updated for newest request */
46bc8d4b 4374 il->tx_power_next = tx_power;
43f12d47
SG
4375
4376 /* do not set tx power when scanning or channel changing */
a6766ccd 4377 defer = test_bit(S_SCANNING, &il->status) ||
c8b03958 4378 memcmp(&il->active, &il->staging, sizeof(il->staging));
43f12d47 4379 if (defer && !force) {
58de00a4 4380 D_INFO("Deferring tx power set\n");
be663ab6
WYG
4381 return 0;
4382 }
4383
46bc8d4b
SG
4384 prev_tx_power = il->tx_power_user_lmt;
4385 il->tx_power_user_lmt = tx_power;
be663ab6 4386
46bc8d4b 4387 ret = il->cfg->ops->lib->send_tx_power(il);
be663ab6
WYG
4388
4389 /* if fail to set tx_power, restore the orig. tx power */
4390 if (ret) {
46bc8d4b
SG
4391 il->tx_power_user_lmt = prev_tx_power;
4392 il->tx_power_next = prev_tx_power;
be663ab6
WYG
4393 }
4394 return ret;
4395}
e2ebc833 4396EXPORT_SYMBOL(il_set_tx_power);
be663ab6 4397
e7392364
SG
4398void
4399il_send_bt_config(struct il_priv *il)
be663ab6 4400{
e2ebc833 4401 struct il_bt_cmd bt_cmd = {
be663ab6
WYG
4402 .lead_time = BT_LEAD_TIME_DEF,
4403 .max_kill = BT_MAX_KILL_DEF,
4404 .kill_ack_mask = 0,
4405 .kill_cts_mask = 0,
4406 };
4407
4408 if (!bt_coex_active)
4409 bt_cmd.flags = BT_COEX_DISABLE;
4410 else
4411 bt_cmd.flags = BT_COEX_ENABLE;
4412
58de00a4 4413 D_INFO("BT coex %s\n",
e7392364 4414 (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
be663ab6 4415
e7392364 4416 if (il_send_cmd_pdu(il, C_BT_CONFIG, sizeof(struct il_bt_cmd), &bt_cmd))
9406f797 4417 IL_ERR("failed to send BT Coex Config\n");
be663ab6 4418}
e2ebc833 4419EXPORT_SYMBOL(il_send_bt_config);
be663ab6 4420
e7392364
SG
4421int
4422il_send_stats_request(struct il_priv *il, u8 flags, bool clear)
be663ab6 4423{
ebf0d90d 4424 struct il_stats_cmd stats_cmd = {
e7392364 4425 .configuration_flags = clear ? IL_STATS_CONF_CLEAR_STATS : 0,
be663ab6
WYG
4426 };
4427
4428 if (flags & CMD_ASYNC)
e7392364
SG
4429 return il_send_cmd_pdu_async(il, C_STATS, sizeof(struct il_stats_cmd),
4430 &stats_cmd, NULL);
be663ab6 4431 else
e7392364
SG
4432 return il_send_cmd_pdu(il, C_STATS, sizeof(struct il_stats_cmd),
4433 &stats_cmd);
be663ab6 4434}
ebf0d90d 4435EXPORT_SYMBOL(il_send_stats_request);
be663ab6 4436
e7392364
SG
4437void
4438il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4439{
d3175167 4440#ifdef CONFIG_IWLEGACY_DEBUG
dcae1c64 4441 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4442 struct il_sleep_notification *sleep = &(pkt->u.sleep_notif);
58de00a4 4443 D_RX("sleep mode: %d, src: %d\n",
1722f8e1 4444 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
be663ab6
WYG
4445#endif
4446}
d2dfb33e 4447EXPORT_SYMBOL(il_hdl_pm_sleep);
be663ab6 4448
e7392364
SG
4449void
4450il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4451{
dcae1c64 4452 struct il_rx_pkt *pkt = rxb_addr(rxb);
e94a4099 4453 u32 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
e7392364
SG
4454 D_RADIO("Dumping %d bytes of unhandled notification for %s:\n", len,
4455 il_get_cmd_string(pkt->hdr.cmd));
46bc8d4b 4456 il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len);
be663ab6 4457}
d2dfb33e 4458EXPORT_SYMBOL(il_hdl_pm_debug_stats);
be663ab6 4459
e7392364
SG
4460void
4461il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4462{
dcae1c64 4463 struct il_rx_pkt *pkt = rxb_addr(rxb);
be663ab6 4464
9406f797 4465 IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) "
e7392364
SG
4466 "seq 0x%04X ser 0x%08X\n",
4467 le32_to_cpu(pkt->u.err_resp.error_type),
4468 il_get_cmd_string(pkt->u.err_resp.cmd_id),
4469 pkt->u.err_resp.cmd_id,
4470 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
4471 le32_to_cpu(pkt->u.err_resp.error_info));
be663ab6 4472}
6e9848b4 4473EXPORT_SYMBOL(il_hdl_error);
be663ab6 4474
e7392364
SG
4475void
4476il_clear_isr_stats(struct il_priv *il)
be663ab6 4477{
46bc8d4b 4478 memset(&il->isr_stats, 0, sizeof(il->isr_stats));
be663ab6
WYG
4479}
4480
e7392364
SG
4481int
4482il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
4483 const struct ieee80211_tx_queue_params *params)
be663ab6 4484{
46bc8d4b 4485 struct il_priv *il = hw->priv;
be663ab6
WYG
4486 unsigned long flags;
4487 int q;
4488
58de00a4 4489 D_MAC80211("enter\n");
be663ab6 4490
46bc8d4b 4491 if (!il_is_ready_rf(il)) {
58de00a4 4492 D_MAC80211("leave - RF not ready\n");
be663ab6
WYG
4493 return -EIO;
4494 }
4495
4496 if (queue >= AC_NUM) {
58de00a4 4497 D_MAC80211("leave - queue >= AC_NUM %d\n", queue);
be663ab6
WYG
4498 return 0;
4499 }
4500
4501 q = AC_NUM - 1 - queue;
4502
46bc8d4b 4503 spin_lock_irqsave(&il->lock, flags);
be663ab6 4504
17d6e557 4505 il->ctx.qos_data.def_qos_parm.ac[q].cw_min =
e7392364 4506 cpu_to_le16(params->cw_min);
17d6e557 4507 il->ctx.qos_data.def_qos_parm.ac[q].cw_max =
e7392364 4508 cpu_to_le16(params->cw_max);
17d6e557
SG
4509 il->ctx.qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
4510 il->ctx.qos_data.def_qos_parm.ac[q].edca_txop =
e7392364 4511 cpu_to_le16((params->txop * 32));
be663ab6 4512
17d6e557 4513 il->ctx.qos_data.def_qos_parm.ac[q].reserved1 = 0;
be663ab6 4514
46bc8d4b 4515 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 4516
58de00a4 4517 D_MAC80211("leave\n");
be663ab6
WYG
4518 return 0;
4519}
e2ebc833 4520EXPORT_SYMBOL(il_mac_conf_tx);
be663ab6 4521
e7392364
SG
4522int
4523il_mac_tx_last_beacon(struct ieee80211_hw *hw)
be663ab6 4524{
46bc8d4b 4525 struct il_priv *il = hw->priv;
be663ab6 4526
46bc8d4b 4527 return il->ibss_manager == IL_IBSS_MANAGER;
be663ab6 4528}
e2ebc833 4529EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon);
be663ab6
WYG
4530
4531static int
46bc8d4b 4532il_set_mode(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 4533{
46bc8d4b 4534 il_connection_init_rx_config(il, ctx);
be663ab6 4535
46bc8d4b
SG
4536 if (il->cfg->ops->hcmd->set_rxon_chain)
4537 il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
be663ab6 4538
46bc8d4b 4539 return il_commit_rxon(il, ctx);
be663ab6
WYG
4540}
4541
e7392364
SG
4542static int
4543il_setup_interface(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6
WYG
4544{
4545 struct ieee80211_vif *vif = ctx->vif;
4546 int err;
4547
46bc8d4b 4548 lockdep_assert_held(&il->mutex);
be663ab6
WYG
4549
4550 /*
4551 * This variable will be correct only when there's just
4552 * a single context, but all code using it is for hardware
4553 * that supports only one context.
4554 */
46bc8d4b 4555 il->iw_mode = vif->type;
be663ab6
WYG
4556
4557 ctx->is_active = true;
4558
46bc8d4b 4559 err = il_set_mode(il, ctx);
be663ab6
WYG
4560 if (err) {
4561 if (!ctx->always_active)
4562 ctx->is_active = false;
4563 return err;
4564 }
4565
4566 return 0;
4567}
4568
4569int
e2ebc833 4570il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 4571{
46bc8d4b 4572 struct il_priv *il = hw->priv;
e2ebc833 4573 struct il_vif_priv *vif_priv = (void *)vif->drv_priv;
be663ab6 4574 int err;
17d6e557 4575 u32 modes;
be663ab6 4576
e7392364 4577 D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
be663ab6 4578
46bc8d4b 4579 mutex_lock(&il->mutex);
be663ab6 4580
46bc8d4b 4581 if (!il_is_ready_rf(il)) {
9406f797 4582 IL_WARN("Try to add interface when device not ready\n");
be663ab6
WYG
4583 err = -EINVAL;
4584 goto out;
4585 }
4586
17d6e557
SG
4587 /* check if busy context is exclusive */
4588 if (il->ctx.vif &&
4589 (il->ctx.exclusive_interface_modes & BIT(il->ctx.vif->type))) {
4590 err = -EINVAL;
4591 goto out;
be663ab6
WYG
4592 }
4593
17d6e557
SG
4594 modes = il->ctx.interface_modes | il->ctx.exclusive_interface_modes;
4595 if (!(modes & BIT(vif->type))) {
be663ab6
WYG
4596 err = -EOPNOTSUPP;
4597 goto out;
4598 }
4599
17d6e557
SG
4600 vif_priv->ctx = &il->ctx;
4601 il->ctx.vif = vif;
be663ab6 4602
17d6e557
SG
4603 err = il_setup_interface(il, &il->ctx);
4604 if (err) {
4605 il->ctx.vif = NULL;
4606 il->iw_mode = NL80211_IFTYPE_STATION;
4607 }
be663ab6 4608
e7392364 4609out:
46bc8d4b 4610 mutex_unlock(&il->mutex);
be663ab6 4611
58de00a4 4612 D_MAC80211("leave\n");
be663ab6
WYG
4613 return err;
4614}
e2ebc833 4615EXPORT_SYMBOL(il_mac_add_interface);
be663ab6 4616
e7392364
SG
4617static void
4618il_teardown_interface(struct il_priv *il, struct ieee80211_vif *vif,
4619 bool mode_change)
be663ab6 4620{
e2ebc833 4621 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6 4622
46bc8d4b 4623 lockdep_assert_held(&il->mutex);
be663ab6 4624
46bc8d4b
SG
4625 if (il->scan_vif == vif) {
4626 il_scan_cancel_timeout(il, 200);
4627 il_force_scan_end(il);
be663ab6
WYG
4628 }
4629
4630 if (!mode_change) {
46bc8d4b 4631 il_set_mode(il, ctx);
be663ab6
WYG
4632 if (!ctx->always_active)
4633 ctx->is_active = false;
4634 }
4635}
4636
e7392364
SG
4637void
4638il_mac_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 4639{
46bc8d4b 4640 struct il_priv *il = hw->priv;
e2ebc833 4641 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6 4642
58de00a4 4643 D_MAC80211("enter\n");
be663ab6 4644
46bc8d4b 4645 mutex_lock(&il->mutex);
be663ab6
WYG
4646
4647 WARN_ON(ctx->vif != vif);
4648 ctx->vif = NULL;
4649
46bc8d4b 4650 il_teardown_interface(il, vif, false);
be663ab6 4651
46bc8d4b
SG
4652 memset(il->bssid, 0, ETH_ALEN);
4653 mutex_unlock(&il->mutex);
be663ab6 4654
58de00a4 4655 D_MAC80211("leave\n");
be663ab6
WYG
4656
4657}
e2ebc833 4658EXPORT_SYMBOL(il_mac_remove_interface);
be663ab6 4659
e7392364
SG
4660int
4661il_alloc_txq_mem(struct il_priv *il)
be663ab6 4662{
46bc8d4b 4663 if (!il->txq)
e7392364
SG
4664 il->txq =
4665 kzalloc(sizeof(struct il_tx_queue) *
4666 il->cfg->base_params->num_of_queues, GFP_KERNEL);
46bc8d4b 4667 if (!il->txq) {
9406f797 4668 IL_ERR("Not enough memory for txq\n");
be663ab6
WYG
4669 return -ENOMEM;
4670 }
4671 return 0;
4672}
e2ebc833 4673EXPORT_SYMBOL(il_alloc_txq_mem);
be663ab6 4674
e7392364
SG
4675void
4676il_txq_mem(struct il_priv *il)
be663ab6 4677{
46bc8d4b
SG
4678 kfree(il->txq);
4679 il->txq = NULL;
be663ab6 4680}
e2ebc833 4681EXPORT_SYMBOL(il_txq_mem);
be663ab6 4682
d3175167 4683#ifdef CONFIG_IWLEGACY_DEBUGFS
be663ab6 4684
e2ebc833 4685#define IL_TRAFFIC_DUMP_SIZE (IL_TRAFFIC_ENTRY_SIZE * IL_TRAFFIC_ENTRIES)
be663ab6 4686
e7392364
SG
4687void
4688il_reset_traffic_log(struct il_priv *il)
be663ab6 4689{
46bc8d4b
SG
4690 il->tx_traffic_idx = 0;
4691 il->rx_traffic_idx = 0;
4692 if (il->tx_traffic)
4693 memset(il->tx_traffic, 0, IL_TRAFFIC_DUMP_SIZE);
4694 if (il->rx_traffic)
4695 memset(il->rx_traffic, 0, IL_TRAFFIC_DUMP_SIZE);
be663ab6
WYG
4696}
4697
e7392364
SG
4698int
4699il_alloc_traffic_mem(struct il_priv *il)
be663ab6 4700{
e2ebc833 4701 u32 traffic_size = IL_TRAFFIC_DUMP_SIZE;
be663ab6 4702
d2ddf621 4703 if (il_debug_level & IL_DL_TX) {
46bc8d4b 4704 if (!il->tx_traffic) {
e7392364 4705 il->tx_traffic = kzalloc(traffic_size, GFP_KERNEL);
46bc8d4b 4706 if (!il->tx_traffic)
be663ab6
WYG
4707 return -ENOMEM;
4708 }
4709 }
d2ddf621 4710 if (il_debug_level & IL_DL_RX) {
46bc8d4b 4711 if (!il->rx_traffic) {
e7392364 4712 il->rx_traffic = kzalloc(traffic_size, GFP_KERNEL);
46bc8d4b 4713 if (!il->rx_traffic)
be663ab6
WYG
4714 return -ENOMEM;
4715 }
4716 }
46bc8d4b 4717 il_reset_traffic_log(il);
be663ab6
WYG
4718 return 0;
4719}
e2ebc833 4720EXPORT_SYMBOL(il_alloc_traffic_mem);
be663ab6 4721
e7392364
SG
4722void
4723il_free_traffic_mem(struct il_priv *il)
be663ab6 4724{
46bc8d4b
SG
4725 kfree(il->tx_traffic);
4726 il->tx_traffic = NULL;
be663ab6 4727
46bc8d4b
SG
4728 kfree(il->rx_traffic);
4729 il->rx_traffic = NULL;
be663ab6 4730}
e2ebc833 4731EXPORT_SYMBOL(il_free_traffic_mem);
be663ab6 4732
e7392364
SG
4733void
4734il_dbg_log_tx_data_frame(struct il_priv *il, u16 length,
4735 struct ieee80211_hdr *header)
be663ab6
WYG
4736{
4737 __le16 fc;
4738 u16 len;
4739
d2ddf621 4740 if (likely(!(il_debug_level & IL_DL_TX)))
be663ab6
WYG
4741 return;
4742
46bc8d4b 4743 if (!il->tx_traffic)
be663ab6
WYG
4744 return;
4745
4746 fc = header->frame_control;
4747 if (ieee80211_is_data(fc)) {
e7392364
SG
4748 len =
4749 (length >
4750 IL_TRAFFIC_ENTRY_SIZE) ? IL_TRAFFIC_ENTRY_SIZE : length;
46bc8d4b 4751 memcpy((il->tx_traffic +
e7392364
SG
4752 (il->tx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)), header,
4753 len);
46bc8d4b 4754 il->tx_traffic_idx =
e7392364 4755 (il->tx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES;
be663ab6
WYG
4756 }
4757}
e2ebc833 4758EXPORT_SYMBOL(il_dbg_log_tx_data_frame);
be663ab6 4759
e7392364
SG
4760void
4761il_dbg_log_rx_data_frame(struct il_priv *il, u16 length,
4762 struct ieee80211_hdr *header)
be663ab6
WYG
4763{
4764 __le16 fc;
4765 u16 len;
4766
d2ddf621 4767 if (likely(!(il_debug_level & IL_DL_RX)))
be663ab6
WYG
4768 return;
4769
46bc8d4b 4770 if (!il->rx_traffic)
be663ab6
WYG
4771 return;
4772
4773 fc = header->frame_control;
4774 if (ieee80211_is_data(fc)) {
e7392364
SG
4775 len =
4776 (length >
4777 IL_TRAFFIC_ENTRY_SIZE) ? IL_TRAFFIC_ENTRY_SIZE : length;
46bc8d4b 4778 memcpy((il->rx_traffic +
e7392364
SG
4779 (il->rx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)), header,
4780 len);
46bc8d4b 4781 il->rx_traffic_idx =
e7392364 4782 (il->rx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES;
be663ab6
WYG
4783 }
4784}
e2ebc833 4785EXPORT_SYMBOL(il_dbg_log_rx_data_frame);
be663ab6 4786
e7392364
SG
4787const char *
4788il_get_mgmt_string(int cmd)
be663ab6
WYG
4789{
4790 switch (cmd) {
e2ebc833
SG
4791 IL_CMD(MANAGEMENT_ASSOC_REQ);
4792 IL_CMD(MANAGEMENT_ASSOC_RESP);
4793 IL_CMD(MANAGEMENT_REASSOC_REQ);
4794 IL_CMD(MANAGEMENT_REASSOC_RESP);
4795 IL_CMD(MANAGEMENT_PROBE_REQ);
4796 IL_CMD(MANAGEMENT_PROBE_RESP);
4797 IL_CMD(MANAGEMENT_BEACON);
4798 IL_CMD(MANAGEMENT_ATIM);
4799 IL_CMD(MANAGEMENT_DISASSOC);
4800 IL_CMD(MANAGEMENT_AUTH);
4801 IL_CMD(MANAGEMENT_DEAUTH);
4802 IL_CMD(MANAGEMENT_ACTION);
be663ab6
WYG
4803 default:
4804 return "UNKNOWN";
4805
4806 }
4807}
4808
e7392364
SG
4809const char *
4810il_get_ctrl_string(int cmd)
be663ab6
WYG
4811{
4812 switch (cmd) {
e2ebc833
SG
4813 IL_CMD(CONTROL_BACK_REQ);
4814 IL_CMD(CONTROL_BACK);
4815 IL_CMD(CONTROL_PSPOLL);
4816 IL_CMD(CONTROL_RTS);
4817 IL_CMD(CONTROL_CTS);
4818 IL_CMD(CONTROL_ACK);
4819 IL_CMD(CONTROL_CFEND);
4820 IL_CMD(CONTROL_CFENDACK);
be663ab6
WYG
4821 default:
4822 return "UNKNOWN";
4823
4824 }
4825}
4826
e7392364
SG
4827void
4828il_clear_traffic_stats(struct il_priv *il)
be663ab6 4829{
46bc8d4b
SG
4830 memset(&il->tx_stats, 0, sizeof(struct traffic_stats));
4831 memset(&il->rx_stats, 0, sizeof(struct traffic_stats));
be663ab6
WYG
4832}
4833
4834/*
d3175167 4835 * if CONFIG_IWLEGACY_DEBUGFS defined,
e2ebc833 4836 * il_update_stats function will
be663ab6 4837 * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass
ebf0d90d 4838 * Use debugFs to display the rx/rx_stats
d3175167 4839 * if CONFIG_IWLEGACY_DEBUGFS not being defined, then no MGMT and CTRL
be663ab6 4840 * information will be recorded, but DATA pkt still will be recorded
e2ebc833 4841 * for the reason of il_led.c need to control the led blinking based on
be663ab6
WYG
4842 * number of tx and rx data.
4843 *
4844 */
4845void
46bc8d4b 4846il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
be663ab6 4847{
e7392364 4848 struct traffic_stats *stats;
be663ab6
WYG
4849
4850 if (is_tx)
46bc8d4b 4851 stats = &il->tx_stats;
be663ab6 4852 else
46bc8d4b 4853 stats = &il->rx_stats;
be663ab6
WYG
4854
4855 if (ieee80211_is_mgmt(fc)) {
4856 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
4857 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
4858 stats->mgmt[MANAGEMENT_ASSOC_REQ]++;
4859 break;
4860 case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP):
4861 stats->mgmt[MANAGEMENT_ASSOC_RESP]++;
4862 break;
4863 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
4864 stats->mgmt[MANAGEMENT_REASSOC_REQ]++;
4865 break;
4866 case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP):
4867 stats->mgmt[MANAGEMENT_REASSOC_RESP]++;
4868 break;
4869 case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ):
4870 stats->mgmt[MANAGEMENT_PROBE_REQ]++;
4871 break;
4872 case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP):
4873 stats->mgmt[MANAGEMENT_PROBE_RESP]++;
4874 break;
4875 case cpu_to_le16(IEEE80211_STYPE_BEACON):
4876 stats->mgmt[MANAGEMENT_BEACON]++;
4877 break;
4878 case cpu_to_le16(IEEE80211_STYPE_ATIM):
4879 stats->mgmt[MANAGEMENT_ATIM]++;
4880 break;
4881 case cpu_to_le16(IEEE80211_STYPE_DISASSOC):
4882 stats->mgmt[MANAGEMENT_DISASSOC]++;
4883 break;
4884 case cpu_to_le16(IEEE80211_STYPE_AUTH):
4885 stats->mgmt[MANAGEMENT_AUTH]++;
4886 break;
4887 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
4888 stats->mgmt[MANAGEMENT_DEAUTH]++;
4889 break;
4890 case cpu_to_le16(IEEE80211_STYPE_ACTION):
4891 stats->mgmt[MANAGEMENT_ACTION]++;
4892 break;
4893 }
4894 } else if (ieee80211_is_ctl(fc)) {
4895 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
4896 case cpu_to_le16(IEEE80211_STYPE_BACK_REQ):
4897 stats->ctrl[CONTROL_BACK_REQ]++;
4898 break;
4899 case cpu_to_le16(IEEE80211_STYPE_BACK):
4900 stats->ctrl[CONTROL_BACK]++;
4901 break;
4902 case cpu_to_le16(IEEE80211_STYPE_PSPOLL):
4903 stats->ctrl[CONTROL_PSPOLL]++;
4904 break;
4905 case cpu_to_le16(IEEE80211_STYPE_RTS):
4906 stats->ctrl[CONTROL_RTS]++;
4907 break;
4908 case cpu_to_le16(IEEE80211_STYPE_CTS):
4909 stats->ctrl[CONTROL_CTS]++;
4910 break;
4911 case cpu_to_le16(IEEE80211_STYPE_ACK):
4912 stats->ctrl[CONTROL_ACK]++;
4913 break;
4914 case cpu_to_le16(IEEE80211_STYPE_CFEND):
4915 stats->ctrl[CONTROL_CFEND]++;
4916 break;
4917 case cpu_to_le16(IEEE80211_STYPE_CFENDACK):
4918 stats->ctrl[CONTROL_CFENDACK]++;
4919 break;
4920 }
4921 } else {
4922 /* data */
4923 stats->data_cnt++;
4924 stats->data_bytes += len;
4925 }
4926}
e2ebc833 4927EXPORT_SYMBOL(il_update_stats);
be663ab6
WYG
4928#endif
4929
e7392364
SG
4930int
4931il_force_reset(struct il_priv *il, bool external)
be663ab6 4932{
e2ebc833 4933 struct il_force_reset *force_reset;
be663ab6 4934
a6766ccd 4935 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG
4936 return -EINVAL;
4937
46bc8d4b 4938 force_reset = &il->force_reset;
be663ab6
WYG
4939 force_reset->reset_request_count++;
4940 if (!external) {
4941 if (force_reset->last_force_reset_jiffies &&
4942 time_after(force_reset->last_force_reset_jiffies +
e7392364 4943 force_reset->reset_duration, jiffies)) {
58de00a4 4944 D_INFO("force reset rejected\n");
be663ab6
WYG
4945 force_reset->reset_reject_count++;
4946 return -EAGAIN;
4947 }
4948 }
4949 force_reset->reset_success_count++;
4950 force_reset->last_force_reset_jiffies = jiffies;
dd6d2a8a
SG
4951
4952 /*
4953 * if the request is from external(ex: debugfs),
4954 * then always perform the request in regardless the module
4955 * parameter setting
4956 * if the request is from internal (uCode error or driver
4957 * detect failure), then fw_restart module parameter
4958 * need to be check before performing firmware reload
4959 */
4960
46bc8d4b 4961 if (!external && !il->cfg->mod_params->restart_fw) {
58de00a4 4962 D_INFO("Cancel firmware reload based on "
e7392364 4963 "module parameter setting\n");
dd6d2a8a 4964 return 0;
be663ab6 4965 }
dd6d2a8a 4966
9406f797 4967 IL_ERR("On demand firmware reload\n");
dd6d2a8a 4968
e2ebc833 4969 /* Set the FW error flag -- cleared on il_down */
a6766ccd 4970 set_bit(S_FW_ERROR, &il->status);
46bc8d4b 4971 wake_up(&il->wait_command_queue);
dd6d2a8a
SG
4972 /*
4973 * Keep the restart process from trying to send host
4974 * commands by clearing the INIT status bit
4975 */
a6766ccd 4976 clear_bit(S_READY, &il->status);
46bc8d4b 4977 queue_work(il->workqueue, &il->restart);
dd6d2a8a 4978
be663ab6
WYG
4979 return 0;
4980}
4981
4982int
e7392364 4983il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
be663ab6
WYG
4984 enum nl80211_iftype newtype, bool newp2p)
4985{
46bc8d4b 4986 struct il_priv *il = hw->priv;
e2ebc833 4987 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
17d6e557 4988 u32 modes;
be663ab6
WYG
4989 int err;
4990
4991 newtype = ieee80211_iftype_p2p(newtype, newp2p);
4992
46bc8d4b 4993 mutex_lock(&il->mutex);
be663ab6 4994
46bc8d4b 4995 if (!ctx->vif || !il_is_ready_rf(il)) {
ffd8c746
JB
4996 /*
4997 * Huh? But wait ... this can maybe happen when
4998 * we're in the middle of a firmware restart!
4999 */
5000 err = -EBUSY;
5001 goto out;
5002 }
5003
17d6e557
SG
5004 modes = ctx->interface_modes | ctx->exclusive_interface_modes;
5005 if (!(modes & BIT(newtype))) {
5006 err = -EOPNOTSUPP;
be663ab6
WYG
5007 goto out;
5008 }
5009
17d6e557
SG
5010 if ((il->ctx.exclusive_interface_modes & BIT(il->ctx.vif->type)) ||
5011 (il->ctx.exclusive_interface_modes & BIT(newtype))) {
5012 err = -EINVAL;
5013 goto out;
be663ab6
WYG
5014 }
5015
5016 /* success */
46bc8d4b 5017 il_teardown_interface(il, vif, true);
be663ab6 5018 vif->type = newtype;
ffd8c746 5019 vif->p2p = newp2p;
46bc8d4b 5020 err = il_setup_interface(il, ctx);
be663ab6
WYG
5021 WARN_ON(err);
5022 /*
5023 * We've switched internally, but submitting to the
5024 * device may have failed for some reason. Mask this
5025 * error, because otherwise mac80211 will not switch
5026 * (and set the interface type back) and we'll be
5027 * out of sync with it.
5028 */
5029 err = 0;
5030
e7392364 5031out:
46bc8d4b 5032 mutex_unlock(&il->mutex);
be663ab6
WYG
5033 return err;
5034}
e2ebc833 5035EXPORT_SYMBOL(il_mac_change_interface);
be663ab6
WYG
5036
5037/*
5038 * On every watchdog tick we check (latest) time stamp. If it does not
5039 * change during timeout period and queue is not empty we reset firmware.
5040 */
e7392364
SG
5041static int
5042il_check_stuck_queue(struct il_priv *il, int cnt)
be663ab6 5043{
46bc8d4b 5044 struct il_tx_queue *txq = &il->txq[cnt];
e2ebc833 5045 struct il_queue *q = &txq->q;
be663ab6
WYG
5046 unsigned long timeout;
5047 int ret;
5048
5049 if (q->read_ptr == q->write_ptr) {
5050 txq->time_stamp = jiffies;
5051 return 0;
5052 }
5053
e7392364
SG
5054 timeout =
5055 txq->time_stamp +
5056 msecs_to_jiffies(il->cfg->base_params->wd_timeout);
be663ab6
WYG
5057
5058 if (time_after(jiffies, timeout)) {
e7392364
SG
5059 IL_ERR("Queue %d stuck for %u ms.\n", q->id,
5060 il->cfg->base_params->wd_timeout);
46bc8d4b 5061 ret = il_force_reset(il, false);
be663ab6
WYG
5062 return (ret == -EAGAIN) ? 0 : 1;
5063 }
5064
5065 return 0;
5066}
5067
5068/*
5069 * Making watchdog tick be a quarter of timeout assure we will
5070 * discover the queue hung between timeout and 1.25*timeout
5071 */
e2ebc833 5072#define IL_WD_TICK(timeout) ((timeout) / 4)
be663ab6
WYG
5073
5074/*
5075 * Watchdog timer callback, we check each tx queue for stuck, if if hung
5076 * we reset the firmware. If everything is fine just rearm the timer.
5077 */
e7392364
SG
5078void
5079il_bg_watchdog(unsigned long data)
be663ab6 5080{
46bc8d4b 5081 struct il_priv *il = (struct il_priv *)data;
be663ab6
WYG
5082 int cnt;
5083 unsigned long timeout;
5084
a6766ccd 5085 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG
5086 return;
5087
46bc8d4b 5088 timeout = il->cfg->base_params->wd_timeout;
be663ab6
WYG
5089 if (timeout == 0)
5090 return;
5091
5092 /* monitor and check for stuck cmd queue */
46bc8d4b 5093 if (il_check_stuck_queue(il, il->cmd_queue))
be663ab6
WYG
5094 return;
5095
5096 /* monitor and check for other stuck queues */
46bc8d4b
SG
5097 if (il_is_any_associated(il)) {
5098 for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) {
be663ab6 5099 /* skip as we already checked the command queue */
46bc8d4b 5100 if (cnt == il->cmd_queue)
be663ab6 5101 continue;
46bc8d4b 5102 if (il_check_stuck_queue(il, cnt))
be663ab6
WYG
5103 return;
5104 }
5105 }
5106
e7392364
SG
5107 mod_timer(&il->watchdog,
5108 jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
be663ab6 5109}
e2ebc833 5110EXPORT_SYMBOL(il_bg_watchdog);
be663ab6 5111
e7392364
SG
5112void
5113il_setup_watchdog(struct il_priv *il)
be663ab6 5114{
46bc8d4b 5115 unsigned int timeout = il->cfg->base_params->wd_timeout;
be663ab6
WYG
5116
5117 if (timeout)
46bc8d4b 5118 mod_timer(&il->watchdog,
e2ebc833 5119 jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
be663ab6 5120 else
46bc8d4b 5121 del_timer(&il->watchdog);
be663ab6 5122}
e2ebc833 5123EXPORT_SYMBOL(il_setup_watchdog);
be663ab6
WYG
5124
5125/*
5126 * extended beacon time format
5127 * time in usec will be changed into a 32-bit value in extended:internal format
5128 * the extended part is the beacon counts
5129 * the internal part is the time in usec within one beacon interval
5130 */
5131u32
e7392364 5132il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval)
be663ab6
WYG
5133{
5134 u32 quot;
5135 u32 rem;
5136 u32 interval = beacon_interval * TIME_UNIT;
5137
5138 if (!interval || !usec)
5139 return 0;
5140
e7392364
SG
5141 quot =
5142 (usec /
5143 interval) & (il_beacon_time_mask_high(il,
5144 il->hw_params.
5145 beacon_time_tsf_bits) >> il->
5146 hw_params.beacon_time_tsf_bits);
5147 rem =
5148 (usec % interval) & il_beacon_time_mask_low(il,
5149 il->hw_params.
5150 beacon_time_tsf_bits);
be663ab6 5151
46bc8d4b 5152 return (quot << il->hw_params.beacon_time_tsf_bits) + rem;
be663ab6 5153}
e2ebc833 5154EXPORT_SYMBOL(il_usecs_to_beacons);
be663ab6
WYG
5155
5156/* base is usually what we get from ucode with each received frame,
5157 * the same as HW timer counter counting down
5158 */
e7392364 5159__le32
1722f8e1 5160il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
e7392364 5161 u32 beacon_interval)
be663ab6 5162{
46bc8d4b 5163 u32 base_low = base & il_beacon_time_mask_low(il,
e7392364
SG
5164 il->hw_params.
5165 beacon_time_tsf_bits);
46bc8d4b 5166 u32 addon_low = addon & il_beacon_time_mask_low(il,
e7392364
SG
5167 il->hw_params.
5168 beacon_time_tsf_bits);
be663ab6 5169 u32 interval = beacon_interval * TIME_UNIT;
46bc8d4b 5170 u32 res = (base & il_beacon_time_mask_high(il,
e7392364
SG
5171 il->hw_params.
5172 beacon_time_tsf_bits)) +
5173 (addon & il_beacon_time_mask_high(il,
5174 il->hw_params.
5175 beacon_time_tsf_bits));
be663ab6
WYG
5176
5177 if (base_low > addon_low)
5178 res += base_low - addon_low;
5179 else if (base_low < addon_low) {
5180 res += interval + base_low - addon_low;
46bc8d4b 5181 res += (1 << il->hw_params.beacon_time_tsf_bits);
be663ab6 5182 } else
46bc8d4b 5183 res += (1 << il->hw_params.beacon_time_tsf_bits);
be663ab6
WYG
5184
5185 return cpu_to_le32(res);
5186}
e2ebc833 5187EXPORT_SYMBOL(il_add_beacon_time);
be663ab6
WYG
5188
5189#ifdef CONFIG_PM
5190
e7392364
SG
5191int
5192il_pci_suspend(struct device *device)
be663ab6
WYG
5193{
5194 struct pci_dev *pdev = to_pci_dev(device);
46bc8d4b 5195 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG
5196
5197 /*
5198 * This function is called when system goes into suspend state
e2ebc833
SG
5199 * mac80211 will call il_mac_stop() from the mac80211 suspend function
5200 * first but since il_mac_stop() has no knowledge of who the caller is,
be663ab6
WYG
5201 * it will not call apm_ops.stop() to stop the DMA operation.
5202 * Calling apm_ops.stop here to make sure we stop the DMA.
5203 */
46bc8d4b 5204 il_apm_stop(il);
be663ab6
WYG
5205
5206 return 0;
5207}
e2ebc833 5208EXPORT_SYMBOL(il_pci_suspend);
be663ab6 5209
e7392364
SG
5210int
5211il_pci_resume(struct device *device)
be663ab6
WYG
5212{
5213 struct pci_dev *pdev = to_pci_dev(device);
46bc8d4b 5214 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG
5215 bool hw_rfkill = false;
5216
5217 /*
5218 * We disable the RETRY_TIMEOUT register (0x41) to keep
5219 * PCI Tx retries from interfering with C3 CPU state.
5220 */
5221 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
5222
46bc8d4b 5223 il_enable_interrupts(il);
be663ab6 5224
e7392364 5225 if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
be663ab6
WYG
5226 hw_rfkill = true;
5227
5228 if (hw_rfkill)
a6766ccd 5229 set_bit(S_RF_KILL_HW, &il->status);
be663ab6 5230 else
a6766ccd 5231 clear_bit(S_RF_KILL_HW, &il->status);
be663ab6 5232
46bc8d4b 5233 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill);
be663ab6
WYG
5234
5235 return 0;
5236}
e2ebc833 5237EXPORT_SYMBOL(il_pci_resume);
be663ab6 5238
e2ebc833
SG
5239const struct dev_pm_ops il_pm_ops = {
5240 .suspend = il_pci_suspend,
5241 .resume = il_pci_resume,
5242 .freeze = il_pci_suspend,
5243 .thaw = il_pci_resume,
5244 .poweroff = il_pci_suspend,
5245 .restore = il_pci_resume,
be663ab6 5246};
e2ebc833 5247EXPORT_SYMBOL(il_pm_ops);
be663ab6
WYG
5248
5249#endif /* CONFIG_PM */
5250
5251static void
46bc8d4b 5252il_update_qos(struct il_priv *il, struct il_rxon_context *ctx)
be663ab6 5253{
a6766ccd 5254 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG
5255 return;
5256
5257 if (!ctx->is_active)
5258 return;
5259
5260 ctx->qos_data.def_qos_parm.qos_flags = 0;
5261
5262 if (ctx->qos_data.qos_active)
5263 ctx->qos_data.def_qos_parm.qos_flags |=
e7392364 5264 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
be663ab6
WYG
5265
5266 if (ctx->ht.enabled)
5267 ctx->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
5268
58de00a4 5269 D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
e7392364 5270 ctx->qos_data.qos_active, ctx->qos_data.def_qos_parm.qos_flags);
be663ab6 5271
b96ed60c 5272 il_send_cmd_pdu_async(il, C_QOS_PARAM, sizeof(struct il_qosparam_cmd),
e7392364 5273 &ctx->qos_data.def_qos_parm, NULL);
be663ab6
WYG
5274}
5275
5276/**
e2ebc833 5277 * il_mac_config - mac80211 config callback
be663ab6 5278 */
e7392364
SG
5279int
5280il_mac_config(struct ieee80211_hw *hw, u32 changed)
be663ab6 5281{
46bc8d4b 5282 struct il_priv *il = hw->priv;
e2ebc833 5283 const struct il_channel_info *ch_info;
be663ab6
WYG
5284 struct ieee80211_conf *conf = &hw->conf;
5285 struct ieee80211_channel *channel = conf->channel;
46bc8d4b 5286 struct il_ht_config *ht_conf = &il->current_ht_config;
17d6e557 5287 struct il_rxon_context *ctx = &il->ctx;
be663ab6
WYG
5288 unsigned long flags = 0;
5289 int ret = 0;
5290 u16 ch;
5291 int scan_active = 0;
7c2cde2e 5292 bool ht_changed = false;
be663ab6 5293
46bc8d4b 5294 if (WARN_ON(!il->cfg->ops->legacy))
be663ab6
WYG
5295 return -EOPNOTSUPP;
5296
46bc8d4b 5297 mutex_lock(&il->mutex);
be663ab6 5298
e7392364
SG
5299 D_MAC80211("enter to channel %d changed 0x%X\n", channel->hw_value,
5300 changed);
be663ab6 5301
a6766ccd 5302 if (unlikely(test_bit(S_SCANNING, &il->status))) {
be663ab6 5303 scan_active = 1;
58de00a4 5304 D_MAC80211("scan active\n");
be663ab6
WYG
5305 }
5306
e7392364
SG
5307 if (changed &
5308 (IEEE80211_CONF_CHANGE_SMPS | IEEE80211_CONF_CHANGE_CHANNEL)) {
be663ab6 5309 /* mac80211 uses static for non-HT which is what we want */
46bc8d4b 5310 il->current_ht_config.smps = conf->smps_mode;
be663ab6
WYG
5311
5312 /*
5313 * Recalculate chain counts.
5314 *
5315 * If monitor mode is enabled then mac80211 will
5316 * set up the SM PS mode to OFF if an HT channel is
5317 * configured.
5318 */
46bc8d4b 5319 if (il->cfg->ops->hcmd->set_rxon_chain)
17d6e557 5320 il->cfg->ops->hcmd->set_rxon_chain(il, &il->ctx);
be663ab6
WYG
5321 }
5322
5323 /* during scanning mac80211 will delay channel setting until
5324 * scan finish with changed = 0
5325 */
5326 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
17d6e557 5327
be663ab6
WYG
5328 if (scan_active)
5329 goto set_ch_out;
5330
5331 ch = channel->hw_value;
46bc8d4b 5332 ch_info = il_get_channel_info(il, channel->band, ch);
e2ebc833 5333 if (!il_is_channel_valid(ch_info)) {
58de00a4 5334 D_MAC80211("leave - invalid channel\n");
be663ab6
WYG
5335 ret = -EINVAL;
5336 goto set_ch_out;
5337 }
5338
46bc8d4b 5339 if (il->iw_mode == NL80211_IFTYPE_ADHOC &&
e2ebc833 5340 !il_is_channel_ibss(ch_info)) {
58de00a4 5341 D_MAC80211("leave - not IBSS channel\n");
eb85de3f
SG
5342 ret = -EINVAL;
5343 goto set_ch_out;
5344 }
5345
46bc8d4b 5346 spin_lock_irqsave(&il->lock, flags);
be663ab6 5347
17d6e557
SG
5348 /* Configure HT40 channels */
5349 if (ctx->ht.enabled != conf_is_ht(conf)) {
5350 ctx->ht.enabled = conf_is_ht(conf);
5351 ht_changed = true;
5352 }
5353 if (ctx->ht.enabled) {
5354 if (conf_is_ht40_minus(conf)) {
5355 ctx->ht.extension_chan_offset =
e7392364 5356 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
17d6e557
SG
5357 ctx->ht.is_40mhz = true;
5358 } else if (conf_is_ht40_plus(conf)) {
5359 ctx->ht.extension_chan_offset =
e7392364 5360 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
17d6e557
SG
5361 ctx->ht.is_40mhz = true;
5362 } else {
5363 ctx->ht.extension_chan_offset =
e7392364 5364 IEEE80211_HT_PARAM_CHA_SEC_NONE;
be663ab6 5365 ctx->ht.is_40mhz = false;
17d6e557
SG
5366 }
5367 } else
5368 ctx->ht.is_40mhz = false;
be663ab6 5369
17d6e557
SG
5370 /*
5371 * Default to no protection. Protection mode will
5372 * later be set from BSS config in il_ht_conf
5373 */
e7392364 5374 ctx->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
be663ab6 5375
17d6e557
SG
5376 /* if we are switching from ht to 2.4 clear flags
5377 * from any ht related info since 2.4 does not
5378 * support ht */
c8b03958
SG
5379 if ((le16_to_cpu(il->staging.channel) != ch))
5380 il->staging.flags = 0;
be663ab6 5381
17d6e557
SG
5382 il_set_rxon_channel(il, channel, ctx);
5383 il_set_rxon_ht(il, ht_conf);
be663ab6 5384
e7392364 5385 il_set_flags_for_band(il, ctx, channel->band, ctx->vif);
be663ab6 5386
46bc8d4b 5387 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5388
46bc8d4b 5389 if (il->cfg->ops->legacy->update_bcast_stations)
e7392364 5390 ret = il->cfg->ops->legacy->update_bcast_stations(il);
be663ab6 5391
e7392364 5392set_ch_out:
be663ab6
WYG
5393 /* The list of supported rates and rate mask can be different
5394 * for each band; since the band may have changed, reset
5395 * the rate mask to what mac80211 lists */
46bc8d4b 5396 il_set_rate(il);
be663ab6
WYG
5397 }
5398
e7392364 5399 if (changed & (IEEE80211_CONF_CHANGE_PS | IEEE80211_CONF_CHANGE_IDLE)) {
46bc8d4b 5400 ret = il_power_update_mode(il, false);
be663ab6 5401 if (ret)
58de00a4 5402 D_MAC80211("Error setting sleep level\n");
be663ab6
WYG
5403 }
5404
5405 if (changed & IEEE80211_CONF_CHANGE_POWER) {
e7392364
SG
5406 D_MAC80211("TX Power old=%d new=%d\n", il->tx_power_user_lmt,
5407 conf->power_level);
be663ab6 5408
46bc8d4b 5409 il_set_tx_power(il, conf->power_level, false);
be663ab6
WYG
5410 }
5411
46bc8d4b 5412 if (!il_is_ready(il)) {
58de00a4 5413 D_MAC80211("leave - not ready\n");
be663ab6
WYG
5414 goto out;
5415 }
5416
5417 if (scan_active)
5418 goto out;
5419
c8b03958 5420 if (memcmp(&il->active, &il->staging, sizeof(il->staging)))
17d6e557
SG
5421 il_commit_rxon(il, ctx);
5422 else
5423 D_INFO("Not re-sending same RXON configuration.\n");
5424 if (ht_changed)
5425 il_update_qos(il, ctx);
be663ab6
WYG
5426
5427out:
58de00a4 5428 D_MAC80211("leave\n");
46bc8d4b 5429 mutex_unlock(&il->mutex);
be663ab6
WYG
5430 return ret;
5431}
e2ebc833 5432EXPORT_SYMBOL(il_mac_config);
be663ab6 5433
e7392364
SG
5434void
5435il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 5436{
46bc8d4b 5437 struct il_priv *il = hw->priv;
be663ab6 5438 unsigned long flags;
7c2cde2e 5439 struct il_rxon_context *ctx = &il->ctx;
be663ab6 5440
46bc8d4b 5441 if (WARN_ON(!il->cfg->ops->legacy))
be663ab6
WYG
5442 return;
5443
46bc8d4b 5444 mutex_lock(&il->mutex);
58de00a4 5445 D_MAC80211("enter\n");
be663ab6 5446
46bc8d4b
SG
5447 spin_lock_irqsave(&il->lock, flags);
5448 memset(&il->current_ht_config, 0, sizeof(struct il_ht_config));
5449 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5450
46bc8d4b 5451 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG
5452
5453 /* new association get rid of ibss beacon skb */
46bc8d4b
SG
5454 if (il->beacon_skb)
5455 dev_kfree_skb(il->beacon_skb);
be663ab6 5456
46bc8d4b 5457 il->beacon_skb = NULL;
be663ab6 5458
46bc8d4b 5459 il->timestamp = 0;
be663ab6 5460
46bc8d4b 5461 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5462
46bc8d4b
SG
5463 il_scan_cancel_timeout(il, 100);
5464 if (!il_is_ready_rf(il)) {
58de00a4 5465 D_MAC80211("leave - not ready\n");
46bc8d4b 5466 mutex_unlock(&il->mutex);
be663ab6
WYG
5467 return;
5468 }
5469
5470 /* we are restarting association process
5471 * clear RXON_FILTER_ASSOC_MSK bit
5472 */
c8b03958 5473 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
46bc8d4b 5474 il_commit_rxon(il, ctx);
be663ab6 5475
46bc8d4b 5476 il_set_rate(il);
be663ab6 5477
46bc8d4b 5478 mutex_unlock(&il->mutex);
be663ab6 5479
58de00a4 5480 D_MAC80211("leave\n");
be663ab6 5481}
e2ebc833 5482EXPORT_SYMBOL(il_mac_reset_tsf);
be663ab6 5483
e7392364
SG
5484static void
5485il_ht_conf(struct il_priv *il, struct ieee80211_vif *vif)
be663ab6 5486{
46bc8d4b 5487 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6
WYG
5488 struct ieee80211_sta *sta;
5489 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
e2ebc833 5490 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6 5491
58de00a4 5492 D_ASSOC("enter:\n");
be663ab6
WYG
5493
5494 if (!ctx->ht.enabled)
5495 return;
5496
5497 ctx->ht.protection =
e7392364 5498 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
be663ab6 5499 ctx->ht.non_gf_sta_present =
e7392364
SG
5500 !!(bss_conf->
5501 ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
be663ab6
WYG
5502
5503 ht_conf->single_chain_sufficient = false;
5504
5505 switch (vif->type) {
5506 case NL80211_IFTYPE_STATION:
5507 rcu_read_lock();
5508 sta = ieee80211_find_sta(vif, bss_conf->bssid);
5509 if (sta) {
5510 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
5511 int maxstreams;
5512
e7392364
SG
5513 maxstreams =
5514 (ht_cap->mcs.
5515 tx_params & IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
5516 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
be663ab6
WYG
5517 maxstreams += 1;
5518
232913b5
SG
5519 if (ht_cap->mcs.rx_mask[1] == 0 &&
5520 ht_cap->mcs.rx_mask[2] == 0)
be663ab6
WYG
5521 ht_conf->single_chain_sufficient = true;
5522 if (maxstreams <= 1)
5523 ht_conf->single_chain_sufficient = true;
5524 } else {
5525 /*
5526 * If at all, this can only happen through a race
5527 * when the AP disconnects us while we're still
5528 * setting up the connection, in that case mac80211
5529 * will soon tell us about that.
5530 */
5531 ht_conf->single_chain_sufficient = true;
5532 }
5533 rcu_read_unlock();
5534 break;
5535 case NL80211_IFTYPE_ADHOC:
5536 ht_conf->single_chain_sufficient = true;
5537 break;
5538 default:
5539 break;
5540 }
5541
58de00a4 5542 D_ASSOC("leave\n");
be663ab6
WYG
5543}
5544
e7392364
SG
5545static inline void
5546il_set_no_assoc(struct il_priv *il, struct ieee80211_vif *vif)
be663ab6 5547{
e2ebc833 5548 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6
WYG
5549
5550 /*
5551 * inform the ucode that there is no longer an
5552 * association and that no more packets should be
5553 * sent
5554 */
c8b03958
SG
5555 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5556 il->staging.assoc_id = 0;
46bc8d4b 5557 il_commit_rxon(il, ctx);
be663ab6
WYG
5558}
5559
e7392364
SG
5560static void
5561il_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 5562{
46bc8d4b 5563 struct il_priv *il = hw->priv;
be663ab6
WYG
5564 unsigned long flags;
5565 __le64 timestamp;
5566 struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
5567
5568 if (!skb)
5569 return;
5570
58de00a4 5571 D_MAC80211("enter\n");
be663ab6 5572
46bc8d4b 5573 lockdep_assert_held(&il->mutex);
be663ab6 5574
46bc8d4b 5575 if (!il->beacon_ctx) {
9406f797 5576 IL_ERR("update beacon but no beacon context!\n");
be663ab6
WYG
5577 dev_kfree_skb(skb);
5578 return;
5579 }
5580
46bc8d4b 5581 spin_lock_irqsave(&il->lock, flags);
be663ab6 5582
46bc8d4b
SG
5583 if (il->beacon_skb)
5584 dev_kfree_skb(il->beacon_skb);
be663ab6 5585
46bc8d4b 5586 il->beacon_skb = skb;
be663ab6
WYG
5587
5588 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
46bc8d4b 5589 il->timestamp = le64_to_cpu(timestamp);
be663ab6 5590
58de00a4 5591 D_MAC80211("leave\n");
46bc8d4b 5592 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5593
46bc8d4b 5594 if (!il_is_ready_rf(il)) {
58de00a4 5595 D_MAC80211("leave - RF not ready\n");
be663ab6
WYG
5596 return;
5597 }
5598
46bc8d4b 5599 il->cfg->ops->legacy->post_associate(il);
be663ab6
WYG
5600}
5601
e7392364
SG
5602void
5603il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5604 struct ieee80211_bss_conf *bss_conf, u32 changes)
be663ab6 5605{
46bc8d4b 5606 struct il_priv *il = hw->priv;
e2ebc833 5607 struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif);
be663ab6
WYG
5608 int ret;
5609
46bc8d4b 5610 if (WARN_ON(!il->cfg->ops->legacy))
be663ab6
WYG
5611 return;
5612
58de00a4 5613 D_MAC80211("changes = 0x%X\n", changes);
be663ab6 5614
46bc8d4b 5615 mutex_lock(&il->mutex);
be663ab6 5616
46bc8d4b
SG
5617 if (!il_is_alive(il)) {
5618 mutex_unlock(&il->mutex);
28a6e577
SG
5619 return;
5620 }
5621
be663ab6
WYG
5622 if (changes & BSS_CHANGED_QOS) {
5623 unsigned long flags;
5624
46bc8d4b 5625 spin_lock_irqsave(&il->lock, flags);
be663ab6 5626 ctx->qos_data.qos_active = bss_conf->qos;
46bc8d4b
SG
5627 il_update_qos(il, ctx);
5628 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG
5629 }
5630
5631 if (changes & BSS_CHANGED_BEACON_ENABLED) {
5632 /*
5633 * the add_interface code must make sure we only ever
5634 * have a single interface that could be beaconing at
5635 * any time.
5636 */
5637 if (vif->bss_conf.enable_beacon)
46bc8d4b 5638 il->beacon_ctx = ctx;
be663ab6 5639 else
46bc8d4b 5640 il->beacon_ctx = NULL;
be663ab6
WYG
5641 }
5642
5643 if (changes & BSS_CHANGED_BSSID) {
58de00a4 5644 D_MAC80211("BSSID %pM\n", bss_conf->bssid);
be663ab6
WYG
5645
5646 /*
5647 * If there is currently a HW scan going on in the
5648 * background then we need to cancel it else the RXON
5649 * below/in post_associate will fail.
5650 */
46bc8d4b 5651 if (il_scan_cancel_timeout(il, 100)) {
e7392364
SG
5652 IL_WARN("Aborted scan still in progress after 100ms\n");
5653 D_MAC80211("leaving - scan abort failed.\n");
46bc8d4b 5654 mutex_unlock(&il->mutex);
be663ab6
WYG
5655 return;
5656 }
5657
5658 /* mac80211 only sets assoc when in STATION mode */
5659 if (vif->type == NL80211_IFTYPE_ADHOC || bss_conf->assoc) {
c8b03958 5660 memcpy(il->staging.bssid_addr, bss_conf->bssid,
e7392364 5661 ETH_ALEN);
be663ab6
WYG
5662
5663 /* currently needed in a few places */
46bc8d4b 5664 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
be663ab6 5665 } else {
c8b03958 5666 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
be663ab6
WYG
5667 }
5668
5669 }
5670
5671 /*
5672 * This needs to be after setting the BSSID in case
5673 * mac80211 decides to do both changes at once because
5674 * it will invoke post_associate.
5675 */
232913b5 5676 if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON))
e2ebc833 5677 il_beacon_update(hw, vif);
be663ab6
WYG
5678
5679 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
e7392364 5680 D_MAC80211("ERP_PREAMBLE %d\n", bss_conf->use_short_preamble);
be663ab6 5681 if (bss_conf->use_short_preamble)
c8b03958 5682 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6 5683 else
c8b03958 5684 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6
WYG
5685 }
5686
5687 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
e7392364 5688 D_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
232913b5 5689 if (bss_conf->use_cts_prot && il->band != IEEE80211_BAND_5GHZ)
c8b03958 5690 il->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
be663ab6 5691 else
c8b03958 5692 il->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
be663ab6 5693 if (bss_conf->use_cts_prot)
c8b03958 5694 il->staging.flags |= RXON_FLG_SELF_CTS_EN;
be663ab6 5695 else
c8b03958 5696 il->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
be663ab6
WYG
5697 }
5698
5699 if (changes & BSS_CHANGED_BASIC_RATES) {
5700 /* XXX use this information
5701 *
e2ebc833 5702 * To do that, remove code from il_set_rate() and put something
be663ab6
WYG
5703 * like this here:
5704 *
e7392364 5705 if (A-band)
c8b03958 5706 il->staging.ofdm_basic_rates =
e7392364
SG
5707 bss_conf->basic_rates;
5708 else
c8b03958 5709 il->staging.ofdm_basic_rates =
e7392364 5710 bss_conf->basic_rates >> 4;
c8b03958 5711 il->staging.cck_basic_rates =
e7392364 5712 bss_conf->basic_rates & 0xF;
be663ab6
WYG
5713 */
5714 }
5715
5716 if (changes & BSS_CHANGED_HT) {
46bc8d4b 5717 il_ht_conf(il, vif);
be663ab6 5718
46bc8d4b
SG
5719 if (il->cfg->ops->hcmd->set_rxon_chain)
5720 il->cfg->ops->hcmd->set_rxon_chain(il, ctx);
be663ab6
WYG
5721 }
5722
5723 if (changes & BSS_CHANGED_ASSOC) {
58de00a4 5724 D_MAC80211("ASSOC %d\n", bss_conf->assoc);
be663ab6 5725 if (bss_conf->assoc) {
46bc8d4b 5726 il->timestamp = bss_conf->timestamp;
be663ab6 5727
46bc8d4b
SG
5728 if (!il_is_rfkill(il))
5729 il->cfg->ops->legacy->post_associate(il);
be663ab6 5730 } else
46bc8d4b 5731 il_set_no_assoc(il, vif);
be663ab6
WYG
5732 }
5733
c8b03958 5734 if (changes && il_is_associated(il) && bss_conf->aid) {
e7392364 5735 D_MAC80211("Changes (%#x) while associated\n", changes);
46bc8d4b 5736 ret = il_send_rxon_assoc(il, ctx);
be663ab6
WYG
5737 if (!ret) {
5738 /* Sync active_rxon with latest change. */
c8b03958 5739 memcpy((void *)&il->active, &il->staging,
e7392364 5740 sizeof(struct il_rxon_cmd));
be663ab6
WYG
5741 }
5742 }
5743
5744 if (changes & BSS_CHANGED_BEACON_ENABLED) {
5745 if (vif->bss_conf.enable_beacon) {
c8b03958 5746 memcpy(il->staging.bssid_addr, bss_conf->bssid,
e7392364 5747 ETH_ALEN);
46bc8d4b
SG
5748 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
5749 il->cfg->ops->legacy->config_ap(il);
be663ab6 5750 } else
46bc8d4b 5751 il_set_no_assoc(il, vif);
be663ab6
WYG
5752 }
5753
5754 if (changes & BSS_CHANGED_IBSS) {
e7392364
SG
5755 ret =
5756 il->cfg->ops->legacy->manage_ibss_station(il, vif,
5757 bss_conf->
5758 ibss_joined);
be663ab6 5759 if (ret)
9406f797 5760 IL_ERR("failed to %s IBSS station %pM\n",
e7392364
SG
5761 bss_conf->ibss_joined ? "add" : "remove",
5762 bss_conf->bssid);
be663ab6
WYG
5763 }
5764
46bc8d4b 5765 mutex_unlock(&il->mutex);
be663ab6 5766
58de00a4 5767 D_MAC80211("leave\n");
be663ab6 5768}
e2ebc833 5769EXPORT_SYMBOL(il_mac_bss_info_changed);
be663ab6 5770
e7392364
SG
5771irqreturn_t
5772il_isr(int irq, void *data)
be663ab6 5773{
46bc8d4b 5774 struct il_priv *il = data;
be663ab6
WYG
5775 u32 inta, inta_mask;
5776 u32 inta_fh;
5777 unsigned long flags;
46bc8d4b 5778 if (!il)
be663ab6
WYG
5779 return IRQ_NONE;
5780
46bc8d4b 5781 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG
5782
5783 /* Disable (but don't clear!) interrupts here to avoid
5784 * back-to-back ISRs and sporadic interrupts from our NIC.
5785 * If we have something to service, the tasklet will re-enable ints.
5786 * If we *don't* have something, we'll re-enable before leaving here. */
e7392364 5787 inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */
841b2cca 5788 _il_wr(il, CSR_INT_MASK, 0x00000000);
be663ab6
WYG
5789
5790 /* Discover which interrupts are active/pending */
841b2cca
SG
5791 inta = _il_rd(il, CSR_INT);
5792 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
be663ab6
WYG
5793
5794 /* Ignore interrupt if there's nothing in NIC to service.
5795 * This may be due to IRQ shared with another device,
5796 * or due to sporadic interrupts thrown from our NIC. */
5797 if (!inta && !inta_fh) {
e7392364 5798 D_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
be663ab6
WYG
5799 goto none;
5800 }
5801
232913b5 5802 if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) {
be663ab6
WYG
5803 /* Hardware disappeared. It might have already raised
5804 * an interrupt */
9406f797 5805 IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta);
be663ab6
WYG
5806 goto unplugged;
5807 }
5808
e7392364
SG
5809 D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, inta_mask,
5810 inta_fh);
be663ab6
WYG
5811
5812 inta &= ~CSR_INT_BIT_SCD;
5813
e2ebc833 5814 /* il_irq_tasklet() will service interrupts and re-enable them */
be663ab6 5815 if (likely(inta || inta_fh))
46bc8d4b 5816 tasklet_schedule(&il->irq_tasklet);
be663ab6
WYG
5817
5818unplugged:
46bc8d4b 5819 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG
5820 return IRQ_HANDLED;
5821
5822none:
5823 /* re-enable interrupts here since we don't have anything to service. */
93fd74e3 5824 /* only Re-enable if disabled by irq */
a6766ccd 5825 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b
SG
5826 il_enable_interrupts(il);
5827 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG
5828 return IRQ_NONE;
5829}
e2ebc833 5830EXPORT_SYMBOL(il_isr);
be663ab6
WYG
5831
5832/*
e2ebc833 5833 * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
be663ab6
WYG
5834 * function.
5835 */
e7392364
SG
5836void
5837il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1722f8e1 5838 __le16 fc, __le32 *tx_flags)
be663ab6
WYG
5839{
5840 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
5841 *tx_flags |= TX_CMD_FLG_RTS_MSK;
5842 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
5843 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5844
5845 if (!ieee80211_is_mgmt(fc))
5846 return;
5847
5848 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
5849 case cpu_to_le16(IEEE80211_STYPE_AUTH):
5850 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
5851 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
5852 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
5853 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5854 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5855 break;
5856 }
e7392364
SG
5857 } else if (info->control.rates[0].
5858 flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
be663ab6
WYG
5859 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5860 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5861 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5862 }
5863}
e2ebc833 5864EXPORT_SYMBOL(il_tx_cmd_protection);
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