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be663ab6 WYG |
1 | /****************************************************************************** |
2 | * | |
3 | * GPL LICENSE SUMMARY | |
4 | * | |
5 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of version 2 of the GNU General Public License as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
19 | * USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * Contact Information: | |
25 | * Intel Linux Wireless <ilw@linux.intel.com> | |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
27 | *****************************************************************************/ | |
28 | ||
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/sched.h> | |
33 | #include <linux/slab.h> | |
0cdc2136 SG |
34 | #include <linux/types.h> |
35 | #include <linux/lockdep.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/skbuff.h> | |
be663ab6 WYG |
41 | #include <net/mac80211.h> |
42 | ||
98613be0 | 43 | #include "common.h" |
be663ab6 | 44 | |
e7392364 SG |
45 | const char * |
46 | il_get_cmd_string(u8 cmd) | |
0cdc2136 SG |
47 | { |
48 | switch (cmd) { | |
49 | IL_CMD(N_ALIVE); | |
50 | IL_CMD(N_ERROR); | |
51 | IL_CMD(C_RXON); | |
52 | IL_CMD(C_RXON_ASSOC); | |
53 | IL_CMD(C_QOS_PARAM); | |
54 | IL_CMD(C_RXON_TIMING); | |
55 | IL_CMD(C_ADD_STA); | |
56 | IL_CMD(C_REM_STA); | |
57 | IL_CMD(C_WEPKEY); | |
58 | IL_CMD(N_3945_RX); | |
59 | IL_CMD(C_TX); | |
60 | IL_CMD(C_RATE_SCALE); | |
61 | IL_CMD(C_LEDS); | |
62 | IL_CMD(C_TX_LINK_QUALITY_CMD); | |
63 | IL_CMD(C_CHANNEL_SWITCH); | |
64 | IL_CMD(N_CHANNEL_SWITCH); | |
65 | IL_CMD(C_SPECTRUM_MEASUREMENT); | |
66 | IL_CMD(N_SPECTRUM_MEASUREMENT); | |
67 | IL_CMD(C_POWER_TBL); | |
68 | IL_CMD(N_PM_SLEEP); | |
69 | IL_CMD(N_PM_DEBUG_STATS); | |
70 | IL_CMD(C_SCAN); | |
71 | IL_CMD(C_SCAN_ABORT); | |
72 | IL_CMD(N_SCAN_START); | |
73 | IL_CMD(N_SCAN_RESULTS); | |
74 | IL_CMD(N_SCAN_COMPLETE); | |
75 | IL_CMD(N_BEACON); | |
76 | IL_CMD(C_TX_BEACON); | |
77 | IL_CMD(C_TX_PWR_TBL); | |
78 | IL_CMD(C_BT_CONFIG); | |
79 | IL_CMD(C_STATS); | |
80 | IL_CMD(N_STATS); | |
81 | IL_CMD(N_CARD_STATE); | |
82 | IL_CMD(N_MISSED_BEACONS); | |
83 | IL_CMD(C_CT_KILL_CONFIG); | |
84 | IL_CMD(C_SENSITIVITY); | |
85 | IL_CMD(C_PHY_CALIBRATION); | |
86 | IL_CMD(N_RX_PHY); | |
87 | IL_CMD(N_RX_MPDU); | |
88 | IL_CMD(N_RX); | |
89 | IL_CMD(N_COMPRESSED_BA); | |
90 | default: | |
91 | return "UNKNOWN"; | |
92 | ||
93 | } | |
94 | } | |
e7392364 | 95 | |
0cdc2136 SG |
96 | EXPORT_SYMBOL(il_get_cmd_string); |
97 | ||
98 | #define HOST_COMPLETE_TIMEOUT (HZ / 2) | |
99 | ||
e7392364 SG |
100 | static void |
101 | il_generic_cmd_callback(struct il_priv *il, struct il_device_cmd *cmd, | |
102 | struct il_rx_pkt *pkt) | |
0cdc2136 SG |
103 | { |
104 | if (pkt->hdr.flags & IL_CMD_FAILED_MSK) { | |
105 | IL_ERR("Bad return from %s (0x%08X)\n", | |
e7392364 | 106 | il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); |
0cdc2136 SG |
107 | return; |
108 | } | |
0cdc2136 SG |
109 | #ifdef CONFIG_IWLEGACY_DEBUG |
110 | switch (cmd->hdr.cmd) { | |
111 | case C_TX_LINK_QUALITY_CMD: | |
112 | case C_SENSITIVITY: | |
113 | D_HC_DUMP("back from %s (0x%08X)\n", | |
e7392364 | 114 | il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags); |
0cdc2136 SG |
115 | break; |
116 | default: | |
e7392364 SG |
117 | D_HC("back from %s (0x%08X)\n", il_get_cmd_string(cmd->hdr.cmd), |
118 | pkt->hdr.flags); | |
0cdc2136 SG |
119 | } |
120 | #endif | |
121 | } | |
122 | ||
123 | static int | |
124 | il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd) | |
125 | { | |
126 | int ret; | |
127 | ||
128 | BUG_ON(!(cmd->flags & CMD_ASYNC)); | |
129 | ||
130 | /* An asynchronous command can not expect an SKB to be set. */ | |
131 | BUG_ON(cmd->flags & CMD_WANT_SKB); | |
132 | ||
133 | /* Assign a generic callback if one is not provided */ | |
134 | if (!cmd->callback) | |
135 | cmd->callback = il_generic_cmd_callback; | |
136 | ||
137 | if (test_bit(S_EXIT_PENDING, &il->status)) | |
138 | return -EBUSY; | |
139 | ||
140 | ret = il_enqueue_hcmd(il, cmd); | |
141 | if (ret < 0) { | |
142 | IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n", | |
e7392364 | 143 | il_get_cmd_string(cmd->id), ret); |
0cdc2136 SG |
144 | return ret; |
145 | } | |
146 | return 0; | |
147 | } | |
148 | ||
e7392364 SG |
149 | int |
150 | il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd) | |
0cdc2136 SG |
151 | { |
152 | int cmd_idx; | |
153 | int ret; | |
154 | ||
155 | lockdep_assert_held(&il->mutex); | |
156 | ||
157 | BUG_ON(cmd->flags & CMD_ASYNC); | |
158 | ||
e7392364 | 159 | /* A synchronous command can not have a callback set. */ |
0cdc2136 SG |
160 | BUG_ON(cmd->callback); |
161 | ||
162 | D_INFO("Attempting to send sync command %s\n", | |
e7392364 | 163 | il_get_cmd_string(cmd->id)); |
0cdc2136 SG |
164 | |
165 | set_bit(S_HCMD_ACTIVE, &il->status); | |
166 | D_INFO("Setting HCMD_ACTIVE for command %s\n", | |
e7392364 | 167 | il_get_cmd_string(cmd->id)); |
0cdc2136 SG |
168 | |
169 | cmd_idx = il_enqueue_hcmd(il, cmd); | |
170 | if (cmd_idx < 0) { | |
171 | ret = cmd_idx; | |
172 | IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n", | |
e7392364 | 173 | il_get_cmd_string(cmd->id), ret); |
0cdc2136 SG |
174 | goto out; |
175 | } | |
176 | ||
177 | ret = wait_event_timeout(il->wait_command_queue, | |
e7392364 SG |
178 | !test_bit(S_HCMD_ACTIVE, &il->status), |
179 | HOST_COMPLETE_TIMEOUT); | |
0cdc2136 SG |
180 | if (!ret) { |
181 | if (test_bit(S_HCMD_ACTIVE, &il->status)) { | |
e7392364 SG |
182 | IL_ERR("Error sending %s: time out after %dms.\n", |
183 | il_get_cmd_string(cmd->id), | |
184 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); | |
0cdc2136 SG |
185 | |
186 | clear_bit(S_HCMD_ACTIVE, &il->status); | |
e7392364 SG |
187 | D_INFO("Clearing HCMD_ACTIVE for command %s\n", |
188 | il_get_cmd_string(cmd->id)); | |
0cdc2136 SG |
189 | ret = -ETIMEDOUT; |
190 | goto cancel; | |
191 | } | |
192 | } | |
193 | ||
194 | if (test_bit(S_RF_KILL_HW, &il->status)) { | |
195 | IL_ERR("Command %s aborted: RF KILL Switch\n", | |
e7392364 | 196 | il_get_cmd_string(cmd->id)); |
0cdc2136 SG |
197 | ret = -ECANCELED; |
198 | goto fail; | |
199 | } | |
200 | if (test_bit(S_FW_ERROR, &il->status)) { | |
201 | IL_ERR("Command %s failed: FW Error\n", | |
e7392364 | 202 | il_get_cmd_string(cmd->id)); |
0cdc2136 SG |
203 | ret = -EIO; |
204 | goto fail; | |
205 | } | |
206 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) { | |
207 | IL_ERR("Error: Response NULL in '%s'\n", | |
e7392364 | 208 | il_get_cmd_string(cmd->id)); |
0cdc2136 SG |
209 | ret = -EIO; |
210 | goto cancel; | |
211 | } | |
212 | ||
213 | ret = 0; | |
214 | goto out; | |
215 | ||
216 | cancel: | |
217 | if (cmd->flags & CMD_WANT_SKB) { | |
218 | /* | |
219 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
220 | * TX cmd queue. Otherwise in case the cmd comes | |
221 | * in later, it will possibly set an invalid | |
222 | * address (cmd->meta.source). | |
223 | */ | |
e7392364 | 224 | il->txq[il->cmd_queue].meta[cmd_idx].flags &= ~CMD_WANT_SKB; |
0cdc2136 SG |
225 | } |
226 | fail: | |
227 | if (cmd->reply_page) { | |
228 | il_free_pages(il, cmd->reply_page); | |
229 | cmd->reply_page = 0; | |
230 | } | |
231 | out: | |
232 | return ret; | |
233 | } | |
e7392364 | 234 | |
0cdc2136 SG |
235 | EXPORT_SYMBOL(il_send_cmd_sync); |
236 | ||
e7392364 SG |
237 | int |
238 | il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd) | |
0cdc2136 SG |
239 | { |
240 | if (cmd->flags & CMD_ASYNC) | |
241 | return il_send_cmd_async(il, cmd); | |
242 | ||
243 | return il_send_cmd_sync(il, cmd); | |
244 | } | |
e7392364 | 245 | |
0cdc2136 SG |
246 | EXPORT_SYMBOL(il_send_cmd); |
247 | ||
248 | int | |
249 | il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data) | |
250 | { | |
251 | struct il_host_cmd cmd = { | |
252 | .id = id, | |
253 | .len = len, | |
254 | .data = data, | |
255 | }; | |
256 | ||
257 | return il_send_cmd_sync(il, &cmd); | |
258 | } | |
e7392364 | 259 | |
0cdc2136 SG |
260 | EXPORT_SYMBOL(il_send_cmd_pdu); |
261 | ||
e7392364 SG |
262 | int |
263 | il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data, | |
264 | void (*callback) (struct il_priv * il, | |
265 | struct il_device_cmd * cmd, | |
266 | struct il_rx_pkt * pkt)) | |
0cdc2136 SG |
267 | { |
268 | struct il_host_cmd cmd = { | |
269 | .id = id, | |
270 | .len = len, | |
271 | .data = data, | |
272 | }; | |
273 | ||
274 | cmd.flags |= CMD_ASYNC; | |
275 | cmd.callback = callback; | |
276 | ||
277 | return il_send_cmd_async(il, &cmd); | |
278 | } | |
e7392364 | 279 | |
0cdc2136 SG |
280 | EXPORT_SYMBOL(il_send_cmd_pdu_async); |
281 | ||
282 | /* default: IL_LED_BLINK(0) using blinking idx table */ | |
283 | static int led_mode; | |
284 | module_param(led_mode, int, S_IRUGO); | |
e7392364 SG |
285 | MODULE_PARM_DESC(led_mode, |
286 | "0=system default, " "1=On(RF On)/Off(RF Off), 2=blinking"); | |
0cdc2136 SG |
287 | |
288 | /* Throughput OFF time(ms) ON time (ms) | |
289 | * >300 25 25 | |
290 | * >200 to 300 40 40 | |
291 | * >100 to 200 55 55 | |
292 | * >70 to 100 65 65 | |
293 | * >50 to 70 75 75 | |
294 | * >20 to 50 85 85 | |
295 | * >10 to 20 95 95 | |
296 | * >5 to 10 110 110 | |
297 | * >1 to 5 130 130 | |
298 | * >0 to 1 167 167 | |
299 | * <=0 SOLID ON | |
300 | */ | |
301 | static const struct ieee80211_tpt_blink il_blink[] = { | |
e7392364 SG |
302 | {.throughput = 0,.blink_time = 334}, |
303 | {.throughput = 1 * 1024 - 1,.blink_time = 260}, | |
304 | {.throughput = 5 * 1024 - 1,.blink_time = 220}, | |
305 | {.throughput = 10 * 1024 - 1,.blink_time = 190}, | |
306 | {.throughput = 20 * 1024 - 1,.blink_time = 170}, | |
307 | {.throughput = 50 * 1024 - 1,.blink_time = 150}, | |
308 | {.throughput = 70 * 1024 - 1,.blink_time = 130}, | |
309 | {.throughput = 100 * 1024 - 1,.blink_time = 110}, | |
310 | {.throughput = 200 * 1024 - 1,.blink_time = 80}, | |
311 | {.throughput = 300 * 1024 - 1,.blink_time = 50}, | |
0cdc2136 SG |
312 | }; |
313 | ||
314 | /* | |
315 | * Adjust led blink rate to compensate on a MAC Clock difference on every HW | |
316 | * Led blink rate analysis showed an average deviation of 0% on 3945, | |
317 | * 5% on 4965 HW. | |
318 | * Need to compensate on the led on/off time per HW according to the deviation | |
319 | * to achieve the desired led frequency | |
320 | * The calculation is: (100-averageDeviation)/100 * blinkTime | |
321 | * For code efficiency the calculation will be: | |
322 | * compensation = (100 - averageDeviation) * 64 / 100 | |
323 | * NewBlinkTime = (compensation * BlinkTime) / 64 | |
324 | */ | |
e7392364 SG |
325 | static inline u8 |
326 | il_blink_compensation(struct il_priv *il, u8 time, u16 compensation) | |
0cdc2136 SG |
327 | { |
328 | if (!compensation) { | |
329 | IL_ERR("undefined blink compensation: " | |
e7392364 | 330 | "use pre-defined blinking time\n"); |
0cdc2136 SG |
331 | return time; |
332 | } | |
333 | ||
e7392364 | 334 | return (u8) ((time * compensation) >> 6); |
0cdc2136 SG |
335 | } |
336 | ||
337 | /* Set led pattern command */ | |
e7392364 SG |
338 | static int |
339 | il_led_cmd(struct il_priv *il, unsigned long on, unsigned long off) | |
0cdc2136 SG |
340 | { |
341 | struct il_led_cmd led_cmd = { | |
342 | .id = IL_LED_LINK, | |
343 | .interval = IL_DEF_LED_INTRVL | |
344 | }; | |
345 | int ret; | |
346 | ||
347 | if (!test_bit(S_READY, &il->status)) | |
348 | return -EBUSY; | |
349 | ||
350 | if (il->blink_on == on && il->blink_off == off) | |
351 | return 0; | |
352 | ||
353 | if (off == 0) { | |
354 | /* led is SOLID_ON */ | |
355 | on = IL_LED_SOLID; | |
356 | } | |
357 | ||
358 | D_LED("Led blink time compensation=%u\n", | |
e7392364 SG |
359 | il->cfg->base_params->led_compensation); |
360 | led_cmd.on = | |
361 | il_blink_compensation(il, on, | |
362 | il->cfg->base_params->led_compensation); | |
363 | led_cmd.off = | |
364 | il_blink_compensation(il, off, | |
365 | il->cfg->base_params->led_compensation); | |
0cdc2136 SG |
366 | |
367 | ret = il->cfg->ops->led->cmd(il, &led_cmd); | |
368 | if (!ret) { | |
369 | il->blink_on = on; | |
370 | il->blink_off = off; | |
371 | } | |
372 | return ret; | |
373 | } | |
374 | ||
e7392364 SG |
375 | static void |
376 | il_led_brightness_set(struct led_classdev *led_cdev, | |
377 | enum led_brightness brightness) | |
0cdc2136 SG |
378 | { |
379 | struct il_priv *il = container_of(led_cdev, struct il_priv, led); | |
380 | unsigned long on = 0; | |
381 | ||
382 | if (brightness > 0) | |
383 | on = IL_LED_SOLID; | |
384 | ||
385 | il_led_cmd(il, on, 0); | |
386 | } | |
387 | ||
e7392364 SG |
388 | static int |
389 | il_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on, | |
390 | unsigned long *delay_off) | |
0cdc2136 SG |
391 | { |
392 | struct il_priv *il = container_of(led_cdev, struct il_priv, led); | |
393 | ||
394 | return il_led_cmd(il, *delay_on, *delay_off); | |
395 | } | |
396 | ||
e7392364 SG |
397 | void |
398 | il_leds_init(struct il_priv *il) | |
0cdc2136 SG |
399 | { |
400 | int mode = led_mode; | |
401 | int ret; | |
402 | ||
403 | if (mode == IL_LED_DEFAULT) | |
404 | mode = il->cfg->led_mode; | |
405 | ||
e7392364 SG |
406 | il->led.name = |
407 | kasprintf(GFP_KERNEL, "%s-led", wiphy_name(il->hw->wiphy)); | |
0cdc2136 SG |
408 | il->led.brightness_set = il_led_brightness_set; |
409 | il->led.blink_set = il_led_blink_set; | |
410 | il->led.max_brightness = 1; | |
411 | ||
412 | switch (mode) { | |
413 | case IL_LED_DEFAULT: | |
414 | WARN_ON(1); | |
415 | break; | |
416 | case IL_LED_BLINK: | |
417 | il->led.default_trigger = | |
e7392364 SG |
418 | ieee80211_create_tpt_led_trigger(il->hw, |
419 | IEEE80211_TPT_LEDTRIG_FL_CONNECTED, | |
420 | il_blink, | |
421 | ARRAY_SIZE(il_blink)); | |
0cdc2136 SG |
422 | break; |
423 | case IL_LED_RF_STATE: | |
e7392364 | 424 | il->led.default_trigger = ieee80211_get_radio_led_name(il->hw); |
0cdc2136 SG |
425 | break; |
426 | } | |
427 | ||
428 | ret = led_classdev_register(&il->pci_dev->dev, &il->led); | |
429 | if (ret) { | |
430 | kfree(il->led.name); | |
431 | return; | |
432 | } | |
433 | ||
434 | il->led_registered = true; | |
435 | } | |
e7392364 | 436 | |
0cdc2136 SG |
437 | EXPORT_SYMBOL(il_leds_init); |
438 | ||
e7392364 SG |
439 | void |
440 | il_leds_exit(struct il_priv *il) | |
0cdc2136 SG |
441 | { |
442 | if (!il->led_registered) | |
443 | return; | |
444 | ||
445 | led_classdev_unregister(&il->led); | |
446 | kfree(il->led.name); | |
447 | } | |
e7392364 | 448 | |
0cdc2136 SG |
449 | EXPORT_SYMBOL(il_leds_exit); |
450 | ||
451 | /************************** EEPROM BANDS **************************** | |
452 | * | |
453 | * The il_eeprom_band definitions below provide the mapping from the | |
454 | * EEPROM contents to the specific channel number supported for each | |
455 | * band. | |
456 | * | |
457 | * For example, il_priv->eeprom.band_3_channels[4] from the band_3 | |
458 | * definition below maps to physical channel 42 in the 5.2GHz spectrum. | |
459 | * The specific geography and calibration information for that channel | |
460 | * is contained in the eeprom map itself. | |
461 | * | |
462 | * During init, we copy the eeprom information and channel map | |
463 | * information into il->channel_info_24/52 and il->channel_map_24/52 | |
464 | * | |
465 | * channel_map_24/52 provides the idx in the channel_info array for a | |
466 | * given channel. We have to have two separate maps as there is channel | |
467 | * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and | |
468 | * band_2 | |
469 | * | |
470 | * A value of 0xff stored in the channel_map indicates that the channel | |
471 | * is not supported by the hardware at all. | |
472 | * | |
473 | * A value of 0xfe in the channel_map indicates that the channel is not | |
474 | * valid for Tx with the current hardware. This means that | |
475 | * while the system can tune and receive on a given channel, it may not | |
476 | * be able to associate or transmit any frames on that | |
477 | * channel. There is no corresponding channel information for that | |
478 | * entry. | |
479 | * | |
480 | *********************************************************************/ | |
481 | ||
482 | /* 2.4 GHz */ | |
483 | const u8 il_eeprom_band_1[14] = { | |
484 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 | |
485 | }; | |
486 | ||
487 | /* 5.2 GHz bands */ | |
488 | static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */ | |
489 | 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 | |
490 | }; | |
491 | ||
492 | static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */ | |
493 | 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 | |
494 | }; | |
495 | ||
496 | static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */ | |
497 | 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 | |
498 | }; | |
499 | ||
500 | static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */ | |
501 | 145, 149, 153, 157, 161, 165 | |
502 | }; | |
503 | ||
e7392364 | 504 | static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */ |
0cdc2136 SG |
505 | 1, 2, 3, 4, 5, 6, 7 |
506 | }; | |
507 | ||
e7392364 | 508 | static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */ |
0cdc2136 SG |
509 | 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 |
510 | }; | |
511 | ||
512 | /****************************************************************************** | |
513 | * | |
514 | * EEPROM related functions | |
515 | * | |
516 | ******************************************************************************/ | |
517 | ||
e7392364 SG |
518 | static int |
519 | il_eeprom_verify_signature(struct il_priv *il) | |
0cdc2136 SG |
520 | { |
521 | u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK; | |
522 | int ret = 0; | |
523 | ||
524 | D_EEPROM("EEPROM signature=0x%08x\n", gp); | |
525 | switch (gp) { | |
526 | case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K: | |
527 | case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K: | |
528 | break; | |
529 | default: | |
e7392364 | 530 | IL_ERR("bad EEPROM signature," "EEPROM_GP=0x%08x\n", gp); |
0cdc2136 SG |
531 | ret = -ENOENT; |
532 | break; | |
533 | } | |
534 | return ret; | |
535 | } | |
536 | ||
e7392364 SG |
537 | const u8 * |
538 | il_eeprom_query_addr(const struct il_priv *il, size_t offset) | |
0cdc2136 SG |
539 | { |
540 | BUG_ON(offset >= il->cfg->base_params->eeprom_size); | |
541 | return &il->eeprom[offset]; | |
542 | } | |
e7392364 | 543 | |
0cdc2136 SG |
544 | EXPORT_SYMBOL(il_eeprom_query_addr); |
545 | ||
e7392364 SG |
546 | u16 |
547 | il_eeprom_query16(const struct il_priv * il, size_t offset) | |
0cdc2136 SG |
548 | { |
549 | if (!il->eeprom) | |
550 | return 0; | |
e7392364 | 551 | return (u16) il->eeprom[offset] | ((u16) il->eeprom[offset + 1] << 8); |
0cdc2136 | 552 | } |
e7392364 | 553 | |
0cdc2136 SG |
554 | EXPORT_SYMBOL(il_eeprom_query16); |
555 | ||
556 | /** | |
557 | * il_eeprom_init - read EEPROM contents | |
558 | * | |
559 | * Load the EEPROM contents from adapter into il->eeprom | |
560 | * | |
561 | * NOTE: This routine uses the non-debug IO access functions. | |
562 | */ | |
e7392364 SG |
563 | int |
564 | il_eeprom_init(struct il_priv *il) | |
0cdc2136 SG |
565 | { |
566 | __le16 *e; | |
567 | u32 gp = _il_rd(il, CSR_EEPROM_GP); | |
568 | int sz; | |
569 | int ret; | |
570 | u16 addr; | |
571 | ||
572 | /* allocate eeprom */ | |
573 | sz = il->cfg->base_params->eeprom_size; | |
574 | D_EEPROM("NVM size = %d\n", sz); | |
575 | il->eeprom = kzalloc(sz, GFP_KERNEL); | |
576 | if (!il->eeprom) { | |
577 | ret = -ENOMEM; | |
578 | goto alloc_err; | |
579 | } | |
e7392364 | 580 | e = (__le16 *) il->eeprom; |
0cdc2136 SG |
581 | |
582 | il->cfg->ops->lib->apm_ops.init(il); | |
583 | ||
584 | ret = il_eeprom_verify_signature(il); | |
585 | if (ret < 0) { | |
586 | IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp); | |
587 | ret = -ENOENT; | |
588 | goto err; | |
589 | } | |
590 | ||
591 | /* Make sure driver (instead of uCode) is allowed to read EEPROM */ | |
592 | ret = il->cfg->ops->lib->eeprom_ops.acquire_semaphore(il); | |
593 | if (ret < 0) { | |
594 | IL_ERR("Failed to acquire EEPROM semaphore.\n"); | |
595 | ret = -ENOENT; | |
596 | goto err; | |
597 | } | |
598 | ||
599 | /* eeprom is an array of 16bit values */ | |
600 | for (addr = 0; addr < sz; addr += sizeof(u16)) { | |
601 | u32 r; | |
602 | ||
603 | _il_wr(il, CSR_EEPROM_REG, | |
e7392364 | 604 | CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); |
0cdc2136 | 605 | |
e7392364 SG |
606 | ret = |
607 | _il_poll_bit(il, CSR_EEPROM_REG, | |
608 | CSR_EEPROM_REG_READ_VALID_MSK, | |
609 | CSR_EEPROM_REG_READ_VALID_MSK, | |
610 | IL_EEPROM_ACCESS_TIMEOUT); | |
0cdc2136 | 611 | if (ret < 0) { |
e7392364 | 612 | IL_ERR("Time out reading EEPROM[%d]\n", addr); |
0cdc2136 SG |
613 | goto done; |
614 | } | |
615 | r = _il_rd(il, CSR_EEPROM_REG); | |
616 | e[addr / 2] = cpu_to_le16(r >> 16); | |
617 | } | |
618 | ||
e7392364 SG |
619 | D_EEPROM("NVM Type: %s, version: 0x%x\n", "EEPROM", |
620 | il_eeprom_query16(il, EEPROM_VERSION)); | |
0cdc2136 SG |
621 | |
622 | ret = 0; | |
623 | done: | |
624 | il->cfg->ops->lib->eeprom_ops.release_semaphore(il); | |
625 | ||
626 | err: | |
627 | if (ret) | |
628 | il_eeprom_free(il); | |
629 | /* Reset chip to save power until we load uCode during "up". */ | |
630 | il_apm_stop(il); | |
631 | alloc_err: | |
632 | return ret; | |
633 | } | |
e7392364 | 634 | |
0cdc2136 SG |
635 | EXPORT_SYMBOL(il_eeprom_init); |
636 | ||
e7392364 SG |
637 | void |
638 | il_eeprom_free(struct il_priv *il) | |
0cdc2136 SG |
639 | { |
640 | kfree(il->eeprom); | |
641 | il->eeprom = NULL; | |
642 | } | |
e7392364 | 643 | |
0cdc2136 SG |
644 | EXPORT_SYMBOL(il_eeprom_free); |
645 | ||
e7392364 SG |
646 | static void |
647 | il_init_band_reference(const struct il_priv *il, int eep_band, | |
648 | int *eeprom_ch_count, | |
649 | const struct il_eeprom_channel **eeprom_ch_info, | |
650 | const u8 ** eeprom_ch_idx) | |
0cdc2136 | 651 | { |
e7392364 SG |
652 | u32 offset = |
653 | il->cfg->ops->lib->eeprom_ops.regulatory_bands[eep_band - 1]; | |
0cdc2136 SG |
654 | switch (eep_band) { |
655 | case 1: /* 2.4GHz band */ | |
656 | *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1); | |
e7392364 SG |
657 | *eeprom_ch_info = |
658 | (struct il_eeprom_channel *)il_eeprom_query_addr(il, | |
659 | offset); | |
0cdc2136 SG |
660 | *eeprom_ch_idx = il_eeprom_band_1; |
661 | break; | |
662 | case 2: /* 4.9GHz band */ | |
663 | *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2); | |
e7392364 SG |
664 | *eeprom_ch_info = |
665 | (struct il_eeprom_channel *)il_eeprom_query_addr(il, | |
666 | offset); | |
0cdc2136 SG |
667 | *eeprom_ch_idx = il_eeprom_band_2; |
668 | break; | |
669 | case 3: /* 5.2GHz band */ | |
670 | *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3); | |
e7392364 SG |
671 | *eeprom_ch_info = |
672 | (struct il_eeprom_channel *)il_eeprom_query_addr(il, | |
673 | offset); | |
0cdc2136 SG |
674 | *eeprom_ch_idx = il_eeprom_band_3; |
675 | break; | |
676 | case 4: /* 5.5GHz band */ | |
677 | *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4); | |
e7392364 SG |
678 | *eeprom_ch_info = |
679 | (struct il_eeprom_channel *)il_eeprom_query_addr(il, | |
680 | offset); | |
0cdc2136 SG |
681 | *eeprom_ch_idx = il_eeprom_band_4; |
682 | break; | |
683 | case 5: /* 5.7GHz band */ | |
684 | *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5); | |
e7392364 SG |
685 | *eeprom_ch_info = |
686 | (struct il_eeprom_channel *)il_eeprom_query_addr(il, | |
687 | offset); | |
0cdc2136 SG |
688 | *eeprom_ch_idx = il_eeprom_band_5; |
689 | break; | |
690 | case 6: /* 2.4GHz ht40 channels */ | |
691 | *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6); | |
e7392364 SG |
692 | *eeprom_ch_info = |
693 | (struct il_eeprom_channel *)il_eeprom_query_addr(il, | |
694 | offset); | |
0cdc2136 SG |
695 | *eeprom_ch_idx = il_eeprom_band_6; |
696 | break; | |
697 | case 7: /* 5 GHz ht40 channels */ | |
698 | *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7); | |
e7392364 SG |
699 | *eeprom_ch_info = |
700 | (struct il_eeprom_channel *)il_eeprom_query_addr(il, | |
701 | offset); | |
0cdc2136 SG |
702 | *eeprom_ch_idx = il_eeprom_band_7; |
703 | break; | |
704 | default: | |
705 | BUG(); | |
706 | } | |
707 | } | |
708 | ||
709 | #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \ | |
710 | ? # x " " : "") | |
711 | /** | |
712 | * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il. | |
713 | * | |
714 | * Does not set up a command, or touch hardware. | |
715 | */ | |
e7392364 SG |
716 | static int |
717 | il_mod_ht40_chan_info(struct il_priv *il, enum ieee80211_band band, u16 channel, | |
718 | const struct il_eeprom_channel *eeprom_ch, | |
719 | u8 clear_ht40_extension_channel) | |
0cdc2136 SG |
720 | { |
721 | struct il_channel_info *ch_info; | |
722 | ||
e7392364 SG |
723 | ch_info = |
724 | (struct il_channel_info *)il_get_channel_info(il, band, channel); | |
0cdc2136 SG |
725 | |
726 | if (!il_is_channel_valid(ch_info)) | |
727 | return -1; | |
728 | ||
729 | D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):" | |
e7392364 SG |
730 | " Ad-Hoc %ssupported\n", ch_info->channel, |
731 | il_is_channel_a_band(ch_info) ? "5.2" : "2.4", | |
732 | CHECK_AND_PRINT(IBSS), CHECK_AND_PRINT(ACTIVE), | |
733 | CHECK_AND_PRINT(RADAR), CHECK_AND_PRINT(WIDE), | |
734 | CHECK_AND_PRINT(DFS), eeprom_ch->flags, | |
735 | eeprom_ch->max_power_avg, | |
736 | ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) && | |
737 | !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" : "not "); | |
0cdc2136 SG |
738 | |
739 | ch_info->ht40_eeprom = *eeprom_ch; | |
740 | ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg; | |
741 | ch_info->ht40_flags = eeprom_ch->flags; | |
742 | if (eeprom_ch->flags & EEPROM_CHANNEL_VALID) | |
743 | ch_info->ht40_extension_channel &= | |
e7392364 | 744 | ~clear_ht40_extension_channel; |
0cdc2136 SG |
745 | |
746 | return 0; | |
747 | } | |
748 | ||
749 | #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \ | |
750 | ? # x " " : "") | |
751 | ||
752 | /** | |
753 | * il_init_channel_map - Set up driver's info for all possible channels | |
754 | */ | |
e7392364 SG |
755 | int |
756 | il_init_channel_map(struct il_priv *il) | |
0cdc2136 SG |
757 | { |
758 | int eeprom_ch_count = 0; | |
759 | const u8 *eeprom_ch_idx = NULL; | |
760 | const struct il_eeprom_channel *eeprom_ch_info = NULL; | |
761 | int band, ch; | |
762 | struct il_channel_info *ch_info; | |
763 | ||
764 | if (il->channel_count) { | |
765 | D_EEPROM("Channel map already initialized.\n"); | |
766 | return 0; | |
767 | } | |
768 | ||
769 | D_EEPROM("Initializing regulatory info from EEPROM\n"); | |
770 | ||
771 | il->channel_count = | |
e7392364 SG |
772 | ARRAY_SIZE(il_eeprom_band_1) + ARRAY_SIZE(il_eeprom_band_2) + |
773 | ARRAY_SIZE(il_eeprom_band_3) + ARRAY_SIZE(il_eeprom_band_4) + | |
0cdc2136 SG |
774 | ARRAY_SIZE(il_eeprom_band_5); |
775 | ||
e7392364 | 776 | D_EEPROM("Parsing data for %d channels.\n", il->channel_count); |
0cdc2136 | 777 | |
e7392364 SG |
778 | il->channel_info = |
779 | kzalloc(sizeof(struct il_channel_info) * il->channel_count, | |
780 | GFP_KERNEL); | |
0cdc2136 SG |
781 | if (!il->channel_info) { |
782 | IL_ERR("Could not allocate channel_info\n"); | |
783 | il->channel_count = 0; | |
784 | return -ENOMEM; | |
785 | } | |
786 | ||
787 | ch_info = il->channel_info; | |
788 | ||
789 | /* Loop through the 5 EEPROM bands adding them in order to the | |
790 | * channel map we maintain (that contains additional information than | |
791 | * what just in the EEPROM) */ | |
792 | for (band = 1; band <= 5; band++) { | |
793 | ||
794 | il_init_band_reference(il, band, &eeprom_ch_count, | |
e7392364 | 795 | &eeprom_ch_info, &eeprom_ch_idx); |
0cdc2136 SG |
796 | |
797 | /* Loop through each band adding each of the channels */ | |
798 | for (ch = 0; ch < eeprom_ch_count; ch++) { | |
799 | ch_info->channel = eeprom_ch_idx[ch]; | |
e7392364 SG |
800 | ch_info->band = |
801 | (band == | |
802 | 1) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; | |
0cdc2136 SG |
803 | |
804 | /* permanently store EEPROM's channel regulatory flags | |
805 | * and max power in channel info database. */ | |
806 | ch_info->eeprom = eeprom_ch_info[ch]; | |
807 | ||
808 | /* Copy the run-time flags so they are there even on | |
809 | * invalid channels */ | |
810 | ch_info->flags = eeprom_ch_info[ch].flags; | |
811 | /* First write that ht40 is not enabled, and then enable | |
812 | * one by one */ | |
813 | ch_info->ht40_extension_channel = | |
e7392364 | 814 | IEEE80211_CHAN_NO_HT40; |
0cdc2136 SG |
815 | |
816 | if (!(il_is_channel_valid(ch_info))) { | |
e7392364 SG |
817 | D_EEPROM("Ch. %d Flags %x [%sGHz] - " |
818 | "No traffic\n", ch_info->channel, | |
819 | ch_info->flags, | |
820 | il_is_channel_a_band(ch_info) ? "5.2" : | |
821 | "2.4"); | |
0cdc2136 SG |
822 | ch_info++; |
823 | continue; | |
824 | } | |
825 | ||
826 | /* Initialize regulatory-based run-time data */ | |
827 | ch_info->max_power_avg = ch_info->curr_txpow = | |
828 | eeprom_ch_info[ch].max_power_avg; | |
829 | ch_info->scan_power = eeprom_ch_info[ch].max_power_avg; | |
830 | ch_info->min_power = 0; | |
831 | ||
e7392364 SG |
832 | D_EEPROM("Ch. %d [%sGHz] " "%s%s%s%s%s%s(0x%02x %ddBm):" |
833 | " Ad-Hoc %ssupported\n", ch_info->channel, | |
834 | il_is_channel_a_band(ch_info) ? "5.2" : "2.4", | |
835 | CHECK_AND_PRINT_I(VALID), | |
836 | CHECK_AND_PRINT_I(IBSS), | |
837 | CHECK_AND_PRINT_I(ACTIVE), | |
838 | CHECK_AND_PRINT_I(RADAR), | |
839 | CHECK_AND_PRINT_I(WIDE), | |
840 | CHECK_AND_PRINT_I(DFS), | |
841 | eeprom_ch_info[ch].flags, | |
842 | eeprom_ch_info[ch].max_power_avg, | |
843 | ((eeprom_ch_info[ch]. | |
844 | flags & EEPROM_CHANNEL_IBSS) && | |
845 | !(eeprom_ch_info[ch]. | |
846 | flags & EEPROM_CHANNEL_RADAR)) ? "" : | |
847 | "not "); | |
0cdc2136 SG |
848 | |
849 | ch_info++; | |
850 | } | |
851 | } | |
852 | ||
853 | /* Check if we do have HT40 channels */ | |
854 | if (il->cfg->ops->lib->eeprom_ops.regulatory_bands[5] == | |
855 | EEPROM_REGULATORY_BAND_NO_HT40 && | |
856 | il->cfg->ops->lib->eeprom_ops.regulatory_bands[6] == | |
857 | EEPROM_REGULATORY_BAND_NO_HT40) | |
858 | return 0; | |
859 | ||
860 | /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */ | |
861 | for (band = 6; band <= 7; band++) { | |
862 | enum ieee80211_band ieeeband; | |
863 | ||
864 | il_init_band_reference(il, band, &eeprom_ch_count, | |
e7392364 | 865 | &eeprom_ch_info, &eeprom_ch_idx); |
0cdc2136 SG |
866 | |
867 | /* EEPROM band 6 is 2.4, band 7 is 5 GHz */ | |
868 | ieeeband = | |
e7392364 | 869 | (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; |
0cdc2136 SG |
870 | |
871 | /* Loop through each band adding each of the channels */ | |
872 | for (ch = 0; ch < eeprom_ch_count; ch++) { | |
873 | /* Set up driver's info for lower half */ | |
e7392364 SG |
874 | il_mod_ht40_chan_info(il, ieeeband, eeprom_ch_idx[ch], |
875 | &eeprom_ch_info[ch], | |
876 | IEEE80211_CHAN_NO_HT40PLUS); | |
0cdc2136 SG |
877 | |
878 | /* Set up driver's info for upper half */ | |
879 | il_mod_ht40_chan_info(il, ieeeband, | |
e7392364 SG |
880 | eeprom_ch_idx[ch] + 4, |
881 | &eeprom_ch_info[ch], | |
882 | IEEE80211_CHAN_NO_HT40MINUS); | |
0cdc2136 SG |
883 | } |
884 | } | |
885 | ||
886 | return 0; | |
887 | } | |
e7392364 | 888 | |
0cdc2136 SG |
889 | EXPORT_SYMBOL(il_init_channel_map); |
890 | ||
891 | /* | |
892 | * il_free_channel_map - undo allocations in il_init_channel_map | |
893 | */ | |
e7392364 SG |
894 | void |
895 | il_free_channel_map(struct il_priv *il) | |
0cdc2136 SG |
896 | { |
897 | kfree(il->channel_info); | |
898 | il->channel_count = 0; | |
899 | } | |
e7392364 | 900 | |
0cdc2136 SG |
901 | EXPORT_SYMBOL(il_free_channel_map); |
902 | ||
903 | /** | |
904 | * il_get_channel_info - Find driver's ilate channel info | |
905 | * | |
906 | * Based on band and channel number. | |
907 | */ | |
e7392364 SG |
908 | const struct il_channel_info * |
909 | il_get_channel_info(const struct il_priv *il, enum ieee80211_band band, | |
910 | u16 channel) | |
0cdc2136 SG |
911 | { |
912 | int i; | |
913 | ||
914 | switch (band) { | |
915 | case IEEE80211_BAND_5GHZ: | |
916 | for (i = 14; i < il->channel_count; i++) { | |
917 | if (il->channel_info[i].channel == channel) | |
918 | return &il->channel_info[i]; | |
919 | } | |
920 | break; | |
921 | case IEEE80211_BAND_2GHZ: | |
922 | if (channel >= 1 && channel <= 14) | |
923 | return &il->channel_info[channel - 1]; | |
924 | break; | |
925 | default: | |
926 | BUG(); | |
927 | } | |
928 | ||
929 | return NULL; | |
930 | } | |
e7392364 | 931 | |
0cdc2136 SG |
932 | EXPORT_SYMBOL(il_get_channel_info); |
933 | ||
934 | /* | |
935 | * Setting power level allows the card to go to sleep when not busy. | |
936 | * | |
937 | * We calculate a sleep command based on the required latency, which | |
938 | * we get from mac80211. In order to handle thermal throttling, we can | |
939 | * also use pre-defined power levels. | |
940 | */ | |
941 | ||
942 | /* | |
943 | * This defines the old power levels. They are still used by default | |
944 | * (level 1) and for thermal throttle (levels 3 through 5) | |
945 | */ | |
946 | ||
947 | struct il_power_vec_entry { | |
948 | struct il_powertable_cmd cmd; | |
e7392364 | 949 | u8 no_dtim; /* number of skip dtim */ |
0cdc2136 SG |
950 | }; |
951 | ||
e7392364 SG |
952 | static void |
953 | il_power_sleep_cam_cmd(struct il_priv *il, struct il_powertable_cmd *cmd) | |
0cdc2136 SG |
954 | { |
955 | memset(cmd, 0, sizeof(*cmd)); | |
956 | ||
957 | if (il->power_data.pci_pm) | |
958 | cmd->flags |= IL_POWER_PCI_PM_MSK; | |
959 | ||
960 | D_POWER("Sleep command for CAM\n"); | |
961 | } | |
962 | ||
963 | static int | |
964 | il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd) | |
965 | { | |
966 | D_POWER("Sending power/sleep command\n"); | |
967 | D_POWER("Flags value = 0x%08X\n", cmd->flags); | |
e7392364 SG |
968 | D_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout)); |
969 | D_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout)); | |
970 | D_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n", | |
971 | le32_to_cpu(cmd->sleep_interval[0]), | |
972 | le32_to_cpu(cmd->sleep_interval[1]), | |
973 | le32_to_cpu(cmd->sleep_interval[2]), | |
974 | le32_to_cpu(cmd->sleep_interval[3]), | |
975 | le32_to_cpu(cmd->sleep_interval[4])); | |
0cdc2136 SG |
976 | |
977 | return il_send_cmd_pdu(il, C_POWER_TBL, | |
e7392364 | 978 | sizeof(struct il_powertable_cmd), cmd); |
0cdc2136 SG |
979 | } |
980 | ||
981 | int | |
e7392364 | 982 | il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd, bool force) |
0cdc2136 SG |
983 | { |
984 | int ret; | |
985 | bool update_chains; | |
986 | ||
987 | lockdep_assert_held(&il->mutex); | |
988 | ||
989 | /* Don't update the RX chain when chain noise calibration is running */ | |
990 | update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE || | |
e7392364 | 991 | il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE; |
0cdc2136 SG |
992 | |
993 | if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force) | |
994 | return 0; | |
995 | ||
996 | if (!il_is_ready_rf(il)) | |
997 | return -EIO; | |
998 | ||
999 | /* scan complete use sleep_power_next, need to be updated */ | |
1000 | memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd)); | |
1001 | if (test_bit(S_SCANNING, &il->status) && !force) { | |
1002 | D_INFO("Defer power set mode while scanning\n"); | |
1003 | return 0; | |
1004 | } | |
1005 | ||
1006 | if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK) | |
1007 | set_bit(S_POWER_PMI, &il->status); | |
1008 | ||
1009 | ret = il_set_power(il, cmd); | |
1010 | if (!ret) { | |
1011 | if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)) | |
1012 | clear_bit(S_POWER_PMI, &il->status); | |
1013 | ||
1014 | if (il->cfg->ops->lib->update_chain_flags && update_chains) | |
1015 | il->cfg->ops->lib->update_chain_flags(il); | |
1016 | else if (il->cfg->ops->lib->update_chain_flags) | |
e7392364 SG |
1017 | D_POWER("Cannot update the power, chain noise " |
1018 | "calibration running: %d\n", | |
1019 | il->chain_noise_data.state); | |
0cdc2136 SG |
1020 | |
1021 | memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)); | |
1022 | } else | |
1023 | IL_ERR("set power fail, ret = %d", ret); | |
1024 | ||
1025 | return ret; | |
1026 | } | |
1027 | ||
e7392364 SG |
1028 | int |
1029 | il_power_update_mode(struct il_priv *il, bool force) | |
0cdc2136 SG |
1030 | { |
1031 | struct il_powertable_cmd cmd; | |
1032 | ||
1033 | il_power_sleep_cam_cmd(il, &cmd); | |
1034 | return il_power_set_mode(il, &cmd, force); | |
1035 | } | |
e7392364 | 1036 | |
0cdc2136 SG |
1037 | EXPORT_SYMBOL(il_power_update_mode); |
1038 | ||
1039 | /* initialize to default */ | |
e7392364 SG |
1040 | void |
1041 | il_power_initialize(struct il_priv *il) | |
0cdc2136 SG |
1042 | { |
1043 | u16 lctl = il_pcie_link_ctl(il); | |
1044 | ||
1045 | il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN); | |
1046 | ||
1047 | il->power_data.debug_sleep_level_override = -1; | |
1048 | ||
e7392364 | 1049 | memset(&il->power_data.sleep_cmd, 0, sizeof(il->power_data.sleep_cmd)); |
0cdc2136 SG |
1050 | } |
1051 | EXPORT_SYMBOL(il_power_initialize); | |
1052 | ||
1053 | /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after | |
1054 | * sending probe req. This should be set long enough to hear probe responses | |
1055 | * from more than one AP. */ | |
e7392364 | 1056 | #define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */ |
0cdc2136 SG |
1057 | #define IL_ACTIVE_DWELL_TIME_52 (20) |
1058 | ||
1059 | #define IL_ACTIVE_DWELL_FACTOR_24GHZ (3) | |
1060 | #define IL_ACTIVE_DWELL_FACTOR_52GHZ (2) | |
1061 | ||
1062 | /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel. | |
1063 | * Must be set longer than active dwell time. | |
1064 | * For the most reliable scan, set > AP beacon interval (typically 100msec). */ | |
e7392364 | 1065 | #define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */ |
0cdc2136 SG |
1066 | #define IL_PASSIVE_DWELL_TIME_52 (10) |
1067 | #define IL_PASSIVE_DWELL_BASE (100) | |
1068 | #define IL_CHANNEL_TUNE_TIME 5 | |
1069 | ||
e7392364 SG |
1070 | static int |
1071 | il_send_scan_abort(struct il_priv *il) | |
0cdc2136 SG |
1072 | { |
1073 | int ret; | |
1074 | struct il_rx_pkt *pkt; | |
1075 | struct il_host_cmd cmd = { | |
1076 | .id = C_SCAN_ABORT, | |
1077 | .flags = CMD_WANT_SKB, | |
1078 | }; | |
1079 | ||
1080 | /* Exit instantly with error when device is not ready | |
1081 | * to receive scan abort command or it does not perform | |
1082 | * hardware scan currently */ | |
1083 | if (!test_bit(S_READY, &il->status) || | |
1084 | !test_bit(S_GEO_CONFIGURED, &il->status) || | |
1085 | !test_bit(S_SCAN_HW, &il->status) || | |
1086 | test_bit(S_FW_ERROR, &il->status) || | |
1087 | test_bit(S_EXIT_PENDING, &il->status)) | |
1088 | return -EIO; | |
1089 | ||
1090 | ret = il_send_cmd_sync(il, &cmd); | |
1091 | if (ret) | |
1092 | return ret; | |
1093 | ||
1094 | pkt = (struct il_rx_pkt *)cmd.reply_page; | |
1095 | if (pkt->u.status != CAN_ABORT_STATUS) { | |
1096 | /* The scan abort will return 1 for success or | |
1097 | * 2 for "failure". A failure condition can be | |
1098 | * due to simply not being in an active scan which | |
1099 | * can occur if we send the scan abort before we | |
1100 | * the microcode has notified us that a scan is | |
1101 | * completed. */ | |
1102 | D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status); | |
1103 | ret = -EIO; | |
1104 | } | |
1105 | ||
1106 | il_free_pages(il, cmd.reply_page); | |
1107 | return ret; | |
1108 | } | |
1109 | ||
e7392364 SG |
1110 | static void |
1111 | il_complete_scan(struct il_priv *il, bool aborted) | |
0cdc2136 SG |
1112 | { |
1113 | /* check if scan was requested from mac80211 */ | |
1114 | if (il->scan_request) { | |
1115 | D_SCAN("Complete scan in mac80211\n"); | |
1116 | ieee80211_scan_completed(il->hw, aborted); | |
1117 | } | |
1118 | ||
1119 | il->scan_vif = NULL; | |
1120 | il->scan_request = NULL; | |
1121 | } | |
1122 | ||
e7392364 SG |
1123 | void |
1124 | il_force_scan_end(struct il_priv *il) | |
0cdc2136 SG |
1125 | { |
1126 | lockdep_assert_held(&il->mutex); | |
1127 | ||
1128 | if (!test_bit(S_SCANNING, &il->status)) { | |
1129 | D_SCAN("Forcing scan end while not scanning\n"); | |
1130 | return; | |
1131 | } | |
1132 | ||
1133 | D_SCAN("Forcing scan end\n"); | |
1134 | clear_bit(S_SCANNING, &il->status); | |
1135 | clear_bit(S_SCAN_HW, &il->status); | |
1136 | clear_bit(S_SCAN_ABORTING, &il->status); | |
1137 | il_complete_scan(il, true); | |
1138 | } | |
1139 | ||
e7392364 SG |
1140 | static void |
1141 | il_do_scan_abort(struct il_priv *il) | |
0cdc2136 SG |
1142 | { |
1143 | int ret; | |
1144 | ||
1145 | lockdep_assert_held(&il->mutex); | |
1146 | ||
1147 | if (!test_bit(S_SCANNING, &il->status)) { | |
1148 | D_SCAN("Not performing scan to abort\n"); | |
1149 | return; | |
1150 | } | |
1151 | ||
1152 | if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) { | |
1153 | D_SCAN("Scan abort in progress\n"); | |
1154 | return; | |
1155 | } | |
1156 | ||
1157 | ret = il_send_scan_abort(il); | |
1158 | if (ret) { | |
1159 | D_SCAN("Send scan abort failed %d\n", ret); | |
1160 | il_force_scan_end(il); | |
1161 | } else | |
1162 | D_SCAN("Successfully send scan abort\n"); | |
1163 | } | |
1164 | ||
1165 | /** | |
1166 | * il_scan_cancel - Cancel any currently executing HW scan | |
1167 | */ | |
e7392364 SG |
1168 | int |
1169 | il_scan_cancel(struct il_priv *il) | |
0cdc2136 SG |
1170 | { |
1171 | D_SCAN("Queuing abort scan\n"); | |
1172 | queue_work(il->workqueue, &il->abort_scan); | |
1173 | return 0; | |
1174 | } | |
e7392364 | 1175 | |
0cdc2136 SG |
1176 | EXPORT_SYMBOL(il_scan_cancel); |
1177 | ||
1178 | /** | |
1179 | * il_scan_cancel_timeout - Cancel any currently executing HW scan | |
1180 | * @ms: amount of time to wait (in milliseconds) for scan to abort | |
1181 | * | |
1182 | */ | |
e7392364 SG |
1183 | int |
1184 | il_scan_cancel_timeout(struct il_priv *il, unsigned long ms) | |
0cdc2136 SG |
1185 | { |
1186 | unsigned long timeout = jiffies + msecs_to_jiffies(ms); | |
1187 | ||
1188 | lockdep_assert_held(&il->mutex); | |
1189 | ||
1190 | D_SCAN("Scan cancel timeout\n"); | |
1191 | ||
1192 | il_do_scan_abort(il); | |
1193 | ||
1194 | while (time_before_eq(jiffies, timeout)) { | |
1195 | if (!test_bit(S_SCAN_HW, &il->status)) | |
1196 | break; | |
1197 | msleep(20); | |
1198 | } | |
1199 | ||
1200 | return test_bit(S_SCAN_HW, &il->status); | |
1201 | } | |
e7392364 | 1202 | |
0cdc2136 SG |
1203 | EXPORT_SYMBOL(il_scan_cancel_timeout); |
1204 | ||
1205 | /* Service response to C_SCAN (0x80) */ | |
e7392364 SG |
1206 | static void |
1207 | il_hdl_scan(struct il_priv *il, struct il_rx_buf *rxb) | |
0cdc2136 SG |
1208 | { |
1209 | #ifdef CONFIG_IWLEGACY_DEBUG | |
1210 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
1211 | struct il_scanreq_notification *notif = | |
1212 | (struct il_scanreq_notification *)pkt->u.raw; | |
1213 | ||
1214 | D_SCAN("Scan request status = 0x%x\n", notif->status); | |
1215 | #endif | |
1216 | } | |
1217 | ||
1218 | /* Service N_SCAN_START (0x82) */ | |
e7392364 SG |
1219 | static void |
1220 | il_hdl_scan_start(struct il_priv *il, struct il_rx_buf *rxb) | |
0cdc2136 SG |
1221 | { |
1222 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
1223 | struct il_scanstart_notification *notif = | |
1224 | (struct il_scanstart_notification *)pkt->u.raw; | |
1225 | il->scan_start_tsf = le32_to_cpu(notif->tsf_low); | |
e7392364 SG |
1226 | D_SCAN("Scan start: " "%d [802.11%s] " |
1227 | "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", notif->channel, | |
1228 | notif->band ? "bg" : "a", le32_to_cpu(notif->tsf_high), | |
1229 | le32_to_cpu(notif->tsf_low), notif->status, notif->beacon_timer); | |
0cdc2136 SG |
1230 | } |
1231 | ||
1232 | /* Service N_SCAN_RESULTS (0x83) */ | |
e7392364 SG |
1233 | static void |
1234 | il_hdl_scan_results(struct il_priv *il, struct il_rx_buf *rxb) | |
0cdc2136 SG |
1235 | { |
1236 | #ifdef CONFIG_IWLEGACY_DEBUG | |
1237 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
1238 | struct il_scanresults_notification *notif = | |
1239 | (struct il_scanresults_notification *)pkt->u.raw; | |
1240 | ||
e7392364 SG |
1241 | D_SCAN("Scan ch.res: " "%d [802.11%s] " "(TSF: 0x%08X:%08X) - %d " |
1242 | "elapsed=%lu usec\n", notif->channel, notif->band ? "bg" : "a", | |
1243 | le32_to_cpu(notif->tsf_high), le32_to_cpu(notif->tsf_low), | |
1244 | le32_to_cpu(notif->stats[0]), | |
1245 | le32_to_cpu(notif->tsf_low) - il->scan_start_tsf); | |
0cdc2136 SG |
1246 | #endif |
1247 | } | |
1248 | ||
1249 | /* Service N_SCAN_COMPLETE (0x84) */ | |
e7392364 SG |
1250 | static void |
1251 | il_hdl_scan_complete(struct il_priv *il, struct il_rx_buf *rxb) | |
0cdc2136 SG |
1252 | { |
1253 | ||
1254 | #ifdef CONFIG_IWLEGACY_DEBUG | |
1255 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
1256 | struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw; | |
1257 | #endif | |
1258 | ||
e7392364 SG |
1259 | D_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n", |
1260 | scan_notif->scanned_channels, scan_notif->tsf_low, | |
1261 | scan_notif->tsf_high, scan_notif->status); | |
0cdc2136 SG |
1262 | |
1263 | /* The HW is no longer scanning */ | |
1264 | clear_bit(S_SCAN_HW, &il->status); | |
1265 | ||
1266 | D_SCAN("Scan on %sGHz took %dms\n", | |
e7392364 SG |
1267 | (il->scan_band == IEEE80211_BAND_2GHZ) ? "2.4" : "5.2", |
1268 | jiffies_to_msecs(jiffies - il->scan_start)); | |
0cdc2136 SG |
1269 | |
1270 | queue_work(il->workqueue, &il->scan_completed); | |
1271 | } | |
1272 | ||
e7392364 SG |
1273 | void |
1274 | il_setup_rx_scan_handlers(struct il_priv *il) | |
0cdc2136 SG |
1275 | { |
1276 | /* scan handlers */ | |
1277 | il->handlers[C_SCAN] = il_hdl_scan; | |
e7392364 SG |
1278 | il->handlers[N_SCAN_START] = il_hdl_scan_start; |
1279 | il->handlers[N_SCAN_RESULTS] = il_hdl_scan_results; | |
1280 | il->handlers[N_SCAN_COMPLETE] = il_hdl_scan_complete; | |
0cdc2136 | 1281 | } |
e7392364 | 1282 | |
0cdc2136 SG |
1283 | EXPORT_SYMBOL(il_setup_rx_scan_handlers); |
1284 | ||
e7392364 SG |
1285 | inline u16 |
1286 | il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band, | |
1287 | u8 n_probes) | |
0cdc2136 SG |
1288 | { |
1289 | if (band == IEEE80211_BAND_5GHZ) | |
1290 | return IL_ACTIVE_DWELL_TIME_52 + | |
e7392364 | 1291 | IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1); |
0cdc2136 SG |
1292 | else |
1293 | return IL_ACTIVE_DWELL_TIME_24 + | |
e7392364 | 1294 | IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1); |
0cdc2136 | 1295 | } |
e7392364 | 1296 | |
0cdc2136 SG |
1297 | EXPORT_SYMBOL(il_get_active_dwell_time); |
1298 | ||
e7392364 SG |
1299 | u16 |
1300 | il_get_passive_dwell_time(struct il_priv * il, enum ieee80211_band band, | |
1301 | struct ieee80211_vif * vif) | |
0cdc2136 SG |
1302 | { |
1303 | struct il_rxon_context *ctx = &il->ctx; | |
1304 | u16 value; | |
1305 | ||
e7392364 SG |
1306 | u16 passive = |
1307 | (band == | |
1308 | IEEE80211_BAND_2GHZ) ? IL_PASSIVE_DWELL_BASE + | |
1309 | IL_PASSIVE_DWELL_TIME_24 : IL_PASSIVE_DWELL_BASE + | |
1310 | IL_PASSIVE_DWELL_TIME_52; | |
0cdc2136 SG |
1311 | |
1312 | if (il_is_any_associated(il)) { | |
1313 | /* | |
1314 | * If we're associated, we clamp the maximum passive | |
1315 | * dwell time to be 98% of the smallest beacon interval | |
1316 | * (minus 2 * channel tune time) | |
1317 | */ | |
1318 | value = ctx->vif ? ctx->vif->bss_conf.beacon_int : 0; | |
1319 | if (value > IL_PASSIVE_DWELL_BASE || !value) | |
1320 | value = IL_PASSIVE_DWELL_BASE; | |
1321 | value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2; | |
1322 | passive = min(value, passive); | |
1323 | } | |
1324 | ||
1325 | return passive; | |
1326 | } | |
e7392364 | 1327 | |
0cdc2136 SG |
1328 | EXPORT_SYMBOL(il_get_passive_dwell_time); |
1329 | ||
e7392364 SG |
1330 | void |
1331 | il_init_scan_params(struct il_priv *il) | |
0cdc2136 SG |
1332 | { |
1333 | u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1; | |
1334 | if (!il->scan_tx_ant[IEEE80211_BAND_5GHZ]) | |
1335 | il->scan_tx_ant[IEEE80211_BAND_5GHZ] = ant_idx; | |
1336 | if (!il->scan_tx_ant[IEEE80211_BAND_2GHZ]) | |
1337 | il->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx; | |
1338 | } | |
e7392364 | 1339 | |
0cdc2136 SG |
1340 | EXPORT_SYMBOL(il_init_scan_params); |
1341 | ||
e7392364 SG |
1342 | static int |
1343 | il_scan_initiate(struct il_priv *il, struct ieee80211_vif *vif) | |
0cdc2136 SG |
1344 | { |
1345 | int ret; | |
1346 | ||
1347 | lockdep_assert_held(&il->mutex); | |
1348 | ||
1349 | if (WARN_ON(!il->cfg->ops->utils->request_scan)) | |
1350 | return -EOPNOTSUPP; | |
1351 | ||
1352 | cancel_delayed_work(&il->scan_check); | |
1353 | ||
1354 | if (!il_is_ready_rf(il)) { | |
1355 | IL_WARN("Request scan called when driver not ready.\n"); | |
1356 | return -EIO; | |
1357 | } | |
1358 | ||
1359 | if (test_bit(S_SCAN_HW, &il->status)) { | |
e7392364 | 1360 | D_SCAN("Multiple concurrent scan requests in parallel.\n"); |
0cdc2136 SG |
1361 | return -EBUSY; |
1362 | } | |
1363 | ||
1364 | if (test_bit(S_SCAN_ABORTING, &il->status)) { | |
1365 | D_SCAN("Scan request while abort pending.\n"); | |
1366 | return -EBUSY; | |
1367 | } | |
1368 | ||
1369 | D_SCAN("Starting scan...\n"); | |
1370 | ||
1371 | set_bit(S_SCANNING, &il->status); | |
1372 | il->scan_start = jiffies; | |
1373 | ||
1374 | ret = il->cfg->ops->utils->request_scan(il, vif); | |
1375 | if (ret) { | |
1376 | clear_bit(S_SCANNING, &il->status); | |
1377 | return ret; | |
1378 | } | |
1379 | ||
1380 | queue_delayed_work(il->workqueue, &il->scan_check, | |
1381 | IL_SCAN_CHECK_WATCHDOG); | |
1382 | ||
1383 | return 0; | |
1384 | } | |
1385 | ||
e7392364 SG |
1386 | int |
1387 | il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
1388 | struct cfg80211_scan_request *req) | |
0cdc2136 SG |
1389 | { |
1390 | struct il_priv *il = hw->priv; | |
1391 | int ret; | |
1392 | ||
1393 | D_MAC80211("enter\n"); | |
1394 | ||
1395 | if (req->n_channels == 0) | |
1396 | return -EINVAL; | |
1397 | ||
1398 | mutex_lock(&il->mutex); | |
1399 | ||
1400 | if (test_bit(S_SCANNING, &il->status)) { | |
1401 | D_SCAN("Scan already in progress.\n"); | |
1402 | ret = -EAGAIN; | |
1403 | goto out_unlock; | |
1404 | } | |
1405 | ||
1406 | /* mac80211 will only ask for one band at a time */ | |
1407 | il->scan_request = req; | |
1408 | il->scan_vif = vif; | |
1409 | il->scan_band = req->channels[0]->band; | |
1410 | ||
1411 | ret = il_scan_initiate(il, vif); | |
1412 | ||
1413 | D_MAC80211("leave\n"); | |
1414 | ||
1415 | out_unlock: | |
1416 | mutex_unlock(&il->mutex); | |
1417 | ||
1418 | return ret; | |
1419 | } | |
e7392364 | 1420 | |
0cdc2136 SG |
1421 | EXPORT_SYMBOL(il_mac_hw_scan); |
1422 | ||
e7392364 SG |
1423 | static void |
1424 | il_bg_scan_check(struct work_struct *data) | |
0cdc2136 SG |
1425 | { |
1426 | struct il_priv *il = | |
1427 | container_of(data, struct il_priv, scan_check.work); | |
1428 | ||
1429 | D_SCAN("Scan check work\n"); | |
1430 | ||
1431 | /* Since we are here firmware does not finish scan and | |
1432 | * most likely is in bad shape, so we don't bother to | |
1433 | * send abort command, just force scan complete to mac80211 */ | |
1434 | mutex_lock(&il->mutex); | |
1435 | il_force_scan_end(il); | |
1436 | mutex_unlock(&il->mutex); | |
1437 | } | |
1438 | ||
1439 | /** | |
1440 | * il_fill_probe_req - fill in all required fields and IE for probe request | |
1441 | */ | |
1442 | ||
1443 | u16 | |
1444 | il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame, | |
e7392364 | 1445 | const u8 * ta, const u8 * ies, int ie_len, int left) |
0cdc2136 SG |
1446 | { |
1447 | int len = 0; | |
1448 | u8 *pos = NULL; | |
1449 | ||
1450 | /* Make sure there is enough space for the probe request, | |
1451 | * two mandatory IEs and the data */ | |
1452 | left -= 24; | |
1453 | if (left < 0) | |
1454 | return 0; | |
1455 | ||
1456 | frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ); | |
1457 | memcpy(frame->da, il_bcast_addr, ETH_ALEN); | |
1458 | memcpy(frame->sa, ta, ETH_ALEN); | |
1459 | memcpy(frame->bssid, il_bcast_addr, ETH_ALEN); | |
1460 | frame->seq_ctrl = 0; | |
1461 | ||
1462 | len += 24; | |
1463 | ||
1464 | /* ...next IE... */ | |
1465 | pos = &frame->u.probe_req.variable[0]; | |
1466 | ||
1467 | /* fill in our indirect SSID IE */ | |
1468 | left -= 2; | |
1469 | if (left < 0) | |
1470 | return 0; | |
1471 | *pos++ = WLAN_EID_SSID; | |
1472 | *pos++ = 0; | |
1473 | ||
1474 | len += 2; | |
1475 | ||
1476 | if (WARN_ON(left < ie_len)) | |
1477 | return len; | |
1478 | ||
1479 | if (ies && ie_len) { | |
1480 | memcpy(pos, ies, ie_len); | |
1481 | len += ie_len; | |
1482 | } | |
1483 | ||
e7392364 | 1484 | return (u16) len; |
0cdc2136 | 1485 | } |
e7392364 | 1486 | |
0cdc2136 SG |
1487 | EXPORT_SYMBOL(il_fill_probe_req); |
1488 | ||
e7392364 SG |
1489 | static void |
1490 | il_bg_abort_scan(struct work_struct *work) | |
0cdc2136 SG |
1491 | { |
1492 | struct il_priv *il = container_of(work, struct il_priv, abort_scan); | |
1493 | ||
1494 | D_SCAN("Abort scan work\n"); | |
1495 | ||
1496 | /* We keep scan_check work queued in case when firmware will not | |
1497 | * report back scan completed notification */ | |
1498 | mutex_lock(&il->mutex); | |
1499 | il_scan_cancel_timeout(il, 200); | |
1500 | mutex_unlock(&il->mutex); | |
1501 | } | |
1502 | ||
e7392364 SG |
1503 | static void |
1504 | il_bg_scan_completed(struct work_struct *work) | |
0cdc2136 | 1505 | { |
e7392364 | 1506 | struct il_priv *il = container_of(work, struct il_priv, scan_completed); |
0cdc2136 SG |
1507 | bool aborted; |
1508 | ||
1509 | D_SCAN("Completed scan.\n"); | |
1510 | ||
1511 | cancel_delayed_work(&il->scan_check); | |
1512 | ||
1513 | mutex_lock(&il->mutex); | |
1514 | ||
1515 | aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status); | |
1516 | if (aborted) | |
1517 | D_SCAN("Aborted scan completed.\n"); | |
1518 | ||
1519 | if (!test_and_clear_bit(S_SCANNING, &il->status)) { | |
1520 | D_SCAN("Scan already completed.\n"); | |
1521 | goto out_settings; | |
1522 | } | |
1523 | ||
1524 | il_complete_scan(il, aborted); | |
1525 | ||
1526 | out_settings: | |
1527 | /* Can we still talk to firmware ? */ | |
1528 | if (!il_is_ready_rf(il)) | |
1529 | goto out; | |
1530 | ||
1531 | /* | |
1532 | * We do not commit power settings while scan is pending, | |
1533 | * do it now if the settings changed. | |
1534 | */ | |
1535 | il_power_set_mode(il, &il->power_data.sleep_cmd_next, false); | |
1536 | il_set_tx_power(il, il->tx_power_next, false); | |
1537 | ||
1538 | il->cfg->ops->utils->post_scan(il); | |
1539 | ||
1540 | out: | |
1541 | mutex_unlock(&il->mutex); | |
1542 | } | |
1543 | ||
e7392364 SG |
1544 | void |
1545 | il_setup_scan_deferred_work(struct il_priv *il) | |
0cdc2136 SG |
1546 | { |
1547 | INIT_WORK(&il->scan_completed, il_bg_scan_completed); | |
1548 | INIT_WORK(&il->abort_scan, il_bg_abort_scan); | |
1549 | INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check); | |
1550 | } | |
e7392364 | 1551 | |
0cdc2136 SG |
1552 | EXPORT_SYMBOL(il_setup_scan_deferred_work); |
1553 | ||
e7392364 SG |
1554 | void |
1555 | il_cancel_scan_deferred_work(struct il_priv *il) | |
0cdc2136 SG |
1556 | { |
1557 | cancel_work_sync(&il->abort_scan); | |
1558 | cancel_work_sync(&il->scan_completed); | |
1559 | ||
1560 | if (cancel_delayed_work_sync(&il->scan_check)) { | |
1561 | mutex_lock(&il->mutex); | |
1562 | il_force_scan_end(il); | |
1563 | mutex_unlock(&il->mutex); | |
1564 | } | |
1565 | } | |
e7392364 | 1566 | |
0cdc2136 SG |
1567 | EXPORT_SYMBOL(il_cancel_scan_deferred_work); |
1568 | ||
1569 | /* il->sta_lock must be held */ | |
e7392364 SG |
1570 | static void |
1571 | il_sta_ucode_activate(struct il_priv *il, u8 sta_id) | |
0cdc2136 SG |
1572 | { |
1573 | ||
1574 | if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) | |
e7392364 SG |
1575 | IL_ERR("ACTIVATE a non DRIVER active station id %u addr %pM\n", |
1576 | sta_id, il->stations[sta_id].sta.sta.addr); | |
0cdc2136 SG |
1577 | |
1578 | if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) { | |
e7392364 SG |
1579 | D_ASSOC("STA id %u addr %pM already present" |
1580 | " in uCode (according to driver)\n", sta_id, | |
1581 | il->stations[sta_id].sta.sta.addr); | |
0cdc2136 SG |
1582 | } else { |
1583 | il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE; | |
e7392364 SG |
1584 | D_ASSOC("Added STA id %u addr %pM to uCode\n", sta_id, |
1585 | il->stations[sta_id].sta.sta.addr); | |
0cdc2136 SG |
1586 | } |
1587 | } | |
1588 | ||
e7392364 SG |
1589 | static int |
1590 | il_process_add_sta_resp(struct il_priv *il, struct il_addsta_cmd *addsta, | |
1591 | struct il_rx_pkt *pkt, bool sync) | |
0cdc2136 SG |
1592 | { |
1593 | u8 sta_id = addsta->sta.sta_id; | |
1594 | unsigned long flags; | |
1595 | int ret = -EIO; | |
1596 | ||
1597 | if (pkt->hdr.flags & IL_CMD_FAILED_MSK) { | |
e7392364 | 1598 | IL_ERR("Bad return from C_ADD_STA (0x%08X)\n", pkt->hdr.flags); |
0cdc2136 SG |
1599 | return ret; |
1600 | } | |
1601 | ||
e7392364 | 1602 | D_INFO("Processing response for adding station %u\n", sta_id); |
0cdc2136 SG |
1603 | |
1604 | spin_lock_irqsave(&il->sta_lock, flags); | |
1605 | ||
1606 | switch (pkt->u.add_sta.status) { | |
1607 | case ADD_STA_SUCCESS_MSK: | |
1608 | D_INFO("C_ADD_STA PASSED\n"); | |
1609 | il_sta_ucode_activate(il, sta_id); | |
1610 | ret = 0; | |
1611 | break; | |
1612 | case ADD_STA_NO_ROOM_IN_TBL: | |
e7392364 | 1613 | IL_ERR("Adding station %d failed, no room in table.\n", sta_id); |
0cdc2136 SG |
1614 | break; |
1615 | case ADD_STA_NO_BLOCK_ACK_RESOURCE: | |
e7392364 SG |
1616 | IL_ERR("Adding station %d failed, no block ack resource.\n", |
1617 | sta_id); | |
0cdc2136 SG |
1618 | break; |
1619 | case ADD_STA_MODIFY_NON_EXIST_STA: | |
1620 | IL_ERR("Attempting to modify non-existing station %d\n", | |
e7392364 | 1621 | sta_id); |
0cdc2136 SG |
1622 | break; |
1623 | default: | |
e7392364 | 1624 | D_ASSOC("Received C_ADD_STA:(0x%08X)\n", pkt->u.add_sta.status); |
0cdc2136 SG |
1625 | break; |
1626 | } | |
1627 | ||
1628 | D_INFO("%s station id %u addr %pM\n", | |
e7392364 SG |
1629 | il->stations[sta_id].sta.mode == |
1630 | STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", sta_id, | |
1631 | il->stations[sta_id].sta.sta.addr); | |
0cdc2136 SG |
1632 | |
1633 | /* | |
1634 | * XXX: The MAC address in the command buffer is often changed from | |
1635 | * the original sent to the device. That is, the MAC address | |
1636 | * written to the command buffer often is not the same MAC address | |
1637 | * read from the command buffer when the command returns. This | |
1638 | * issue has not yet been resolved and this debugging is left to | |
1639 | * observe the problem. | |
1640 | */ | |
1641 | D_INFO("%s station according to cmd buffer %pM\n", | |
e7392364 SG |
1642 | il->stations[sta_id].sta.mode == |
1643 | STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", addsta->sta.addr); | |
0cdc2136 SG |
1644 | spin_unlock_irqrestore(&il->sta_lock, flags); |
1645 | ||
1646 | return ret; | |
1647 | } | |
1648 | ||
e7392364 SG |
1649 | static void |
1650 | il_add_sta_callback(struct il_priv *il, struct il_device_cmd *cmd, | |
1651 | struct il_rx_pkt *pkt) | |
0cdc2136 | 1652 | { |
e7392364 | 1653 | struct il_addsta_cmd *addsta = (struct il_addsta_cmd *)cmd->cmd.payload; |
0cdc2136 SG |
1654 | |
1655 | il_process_add_sta_resp(il, addsta, pkt, false); | |
1656 | ||
1657 | } | |
1658 | ||
e7392364 SG |
1659 | int |
1660 | il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags) | |
0cdc2136 SG |
1661 | { |
1662 | struct il_rx_pkt *pkt = NULL; | |
1663 | int ret = 0; | |
1664 | u8 data[sizeof(*sta)]; | |
1665 | struct il_host_cmd cmd = { | |
1666 | .id = C_ADD_STA, | |
1667 | .flags = flags, | |
1668 | .data = data, | |
1669 | }; | |
1670 | u8 sta_id __maybe_unused = sta->sta.sta_id; | |
1671 | ||
e7392364 SG |
1672 | D_INFO("Adding sta %u (%pM) %ssynchronously\n", sta_id, sta->sta.addr, |
1673 | flags & CMD_ASYNC ? "a" : ""); | |
0cdc2136 SG |
1674 | |
1675 | if (flags & CMD_ASYNC) | |
1676 | cmd.callback = il_add_sta_callback; | |
1677 | else { | |
1678 | cmd.flags |= CMD_WANT_SKB; | |
1679 | might_sleep(); | |
1680 | } | |
1681 | ||
1682 | cmd.len = il->cfg->ops->utils->build_addsta_hcmd(sta, data); | |
1683 | ret = il_send_cmd(il, &cmd); | |
1684 | ||
1685 | if (ret || (flags & CMD_ASYNC)) | |
1686 | return ret; | |
1687 | ||
1688 | if (ret == 0) { | |
1689 | pkt = (struct il_rx_pkt *)cmd.reply_page; | |
1690 | ret = il_process_add_sta_resp(il, sta, pkt, true); | |
1691 | } | |
1692 | il_free_pages(il, cmd.reply_page); | |
1693 | ||
1694 | return ret; | |
1695 | } | |
e7392364 | 1696 | |
0cdc2136 SG |
1697 | EXPORT_SYMBOL(il_send_add_sta); |
1698 | ||
e7392364 SG |
1699 | static void |
1700 | il_set_ht_add_station(struct il_priv *il, u8 idx, struct ieee80211_sta *sta, | |
1701 | struct il_rxon_context *ctx) | |
0cdc2136 SG |
1702 | { |
1703 | struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->ht_cap; | |
1704 | __le32 sta_flags; | |
1705 | u8 mimo_ps_mode; | |
1706 | ||
1707 | if (!sta || !sta_ht_inf->ht_supported) | |
1708 | goto done; | |
1709 | ||
1710 | mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_SM_PS) >> 2; | |
1711 | D_ASSOC("spatial multiplexing power save mode: %s\n", | |
e7392364 SG |
1712 | (mimo_ps_mode == |
1713 | WLAN_HT_CAP_SM_PS_STATIC) ? "static" : (mimo_ps_mode == | |
1714 | WLAN_HT_CAP_SM_PS_DYNAMIC) | |
1715 | ? "dynamic" : "disabled"); | |
0cdc2136 SG |
1716 | |
1717 | sta_flags = il->stations[idx].sta.station_flags; | |
1718 | ||
1719 | sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK); | |
1720 | ||
1721 | switch (mimo_ps_mode) { | |
1722 | case WLAN_HT_CAP_SM_PS_STATIC: | |
1723 | sta_flags |= STA_FLG_MIMO_DIS_MSK; | |
1724 | break; | |
1725 | case WLAN_HT_CAP_SM_PS_DYNAMIC: | |
1726 | sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK; | |
1727 | break; | |
1728 | case WLAN_HT_CAP_SM_PS_DISABLED: | |
1729 | break; | |
1730 | default: | |
1731 | IL_WARN("Invalid MIMO PS mode %d\n", mimo_ps_mode); | |
1732 | break; | |
1733 | } | |
1734 | ||
e7392364 SG |
1735 | sta_flags |= |
1736 | cpu_to_le32((u32) sta_ht_inf-> | |
1737 | ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS); | |
0cdc2136 | 1738 | |
e7392364 SG |
1739 | sta_flags |= |
1740 | cpu_to_le32((u32) sta_ht_inf-> | |
1741 | ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS); | |
0cdc2136 SG |
1742 | |
1743 | if (il_is_ht40_tx_allowed(il, ctx, &sta->ht_cap)) | |
1744 | sta_flags |= STA_FLG_HT40_EN_MSK; | |
1745 | else | |
1746 | sta_flags &= ~STA_FLG_HT40_EN_MSK; | |
1747 | ||
1748 | il->stations[idx].sta.station_flags = sta_flags; | |
e7392364 | 1749 | done: |
0cdc2136 SG |
1750 | return; |
1751 | } | |
1752 | ||
1753 | /** | |
1754 | * il_prep_station - Prepare station information for addition | |
1755 | * | |
1756 | * should be called with sta_lock held | |
1757 | */ | |
e7392364 SG |
1758 | u8 |
1759 | il_prep_station(struct il_priv * il, struct il_rxon_context * ctx, | |
1760 | const u8 * addr, bool is_ap, struct ieee80211_sta * sta) | |
0cdc2136 SG |
1761 | { |
1762 | struct il_station_entry *station; | |
1763 | int i; | |
1764 | u8 sta_id = IL_INVALID_STATION; | |
1765 | u16 rate; | |
1766 | ||
1767 | if (is_ap) | |
1768 | sta_id = ctx->ap_sta_id; | |
1769 | else if (is_broadcast_ether_addr(addr)) | |
1770 | sta_id = ctx->bcast_sta_id; | |
1771 | else | |
1772 | for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) { | |
e7392364 SG |
1773 | if (!compare_ether_addr |
1774 | (il->stations[i].sta.sta.addr, addr)) { | |
0cdc2136 SG |
1775 | sta_id = i; |
1776 | break; | |
1777 | } | |
1778 | ||
1779 | if (!il->stations[i].used && | |
1780 | sta_id == IL_INVALID_STATION) | |
1781 | sta_id = i; | |
1782 | } | |
1783 | ||
1784 | /* | |
1785 | * These two conditions have the same outcome, but keep them | |
1786 | * separate | |
1787 | */ | |
1788 | if (unlikely(sta_id == IL_INVALID_STATION)) | |
1789 | return sta_id; | |
1790 | ||
1791 | /* | |
1792 | * uCode is not able to deal with multiple requests to add a | |
1793 | * station. Keep track if one is in progress so that we do not send | |
1794 | * another. | |
1795 | */ | |
1796 | if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) { | |
e7392364 | 1797 | D_INFO("STA %d already in process of being added.\n", sta_id); |
0cdc2136 SG |
1798 | return sta_id; |
1799 | } | |
1800 | ||
1801 | if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) && | |
1802 | (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) && | |
1803 | !compare_ether_addr(il->stations[sta_id].sta.sta.addr, addr)) { | |
e7392364 SG |
1804 | D_ASSOC("STA %d (%pM) already added, not adding again.\n", |
1805 | sta_id, addr); | |
0cdc2136 SG |
1806 | return sta_id; |
1807 | } | |
1808 | ||
1809 | station = &il->stations[sta_id]; | |
1810 | station->used = IL_STA_DRIVER_ACTIVE; | |
e7392364 | 1811 | D_ASSOC("Add STA to driver ID %d: %pM\n", sta_id, addr); |
0cdc2136 SG |
1812 | il->num_stations++; |
1813 | ||
1814 | /* Set up the C_ADD_STA command to send to device */ | |
1815 | memset(&station->sta, 0, sizeof(struct il_addsta_cmd)); | |
1816 | memcpy(station->sta.sta.addr, addr, ETH_ALEN); | |
1817 | station->sta.mode = 0; | |
1818 | station->sta.sta.sta_id = sta_id; | |
1819 | station->sta.station_flags = ctx->station_flags; | |
1820 | station->ctxid = ctx->ctxid; | |
1821 | ||
1822 | if (sta) { | |
1823 | struct il_station_priv_common *sta_priv; | |
1824 | ||
1825 | sta_priv = (void *)sta->drv_priv; | |
1826 | sta_priv->ctx = ctx; | |
1827 | } | |
1828 | ||
1829 | /* | |
1830 | * OK to call unconditionally, since local stations (IBSS BSSID | |
1831 | * STA and broadcast STA) pass in a NULL sta, and mac80211 | |
1832 | * doesn't allow HT IBSS. | |
1833 | */ | |
1834 | il_set_ht_add_station(il, sta_id, sta, ctx); | |
1835 | ||
1836 | /* 3945 only */ | |
e7392364 | 1837 | rate = (il->band == IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP : RATE_1M_PLCP; |
0cdc2136 SG |
1838 | /* Turn on both antennas for the station... */ |
1839 | station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK); | |
1840 | ||
1841 | return sta_id; | |
1842 | ||
1843 | } | |
e7392364 | 1844 | |
0cdc2136 SG |
1845 | EXPORT_SYMBOL_GPL(il_prep_station); |
1846 | ||
1847 | #define STA_WAIT_TIMEOUT (HZ/2) | |
1848 | ||
1849 | /** | |
1850 | * il_add_station_common - | |
1851 | */ | |
1852 | int | |
e7392364 SG |
1853 | il_add_station_common(struct il_priv *il, struct il_rxon_context *ctx, |
1854 | const u8 * addr, bool is_ap, struct ieee80211_sta *sta, | |
1855 | u8 * sta_id_r) | |
0cdc2136 SG |
1856 | { |
1857 | unsigned long flags_spin; | |
1858 | int ret = 0; | |
1859 | u8 sta_id; | |
1860 | struct il_addsta_cmd sta_cmd; | |
1861 | ||
1862 | *sta_id_r = 0; | |
1863 | spin_lock_irqsave(&il->sta_lock, flags_spin); | |
1864 | sta_id = il_prep_station(il, ctx, addr, is_ap, sta); | |
1865 | if (sta_id == IL_INVALID_STATION) { | |
e7392364 | 1866 | IL_ERR("Unable to prepare station %pM for addition\n", addr); |
0cdc2136 SG |
1867 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); |
1868 | return -EINVAL; | |
1869 | } | |
1870 | ||
1871 | /* | |
1872 | * uCode is not able to deal with multiple requests to add a | |
1873 | * station. Keep track if one is in progress so that we do not send | |
1874 | * another. | |
1875 | */ | |
1876 | if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) { | |
e7392364 | 1877 | D_INFO("STA %d already in process of being added.\n", sta_id); |
0cdc2136 SG |
1878 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); |
1879 | return -EEXIST; | |
1880 | } | |
1881 | ||
1882 | if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) && | |
1883 | (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) { | |
e7392364 | 1884 | D_ASSOC("STA %d (%pM) already added, not adding again.\n", |
0cdc2136 SG |
1885 | sta_id, addr); |
1886 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
1887 | return -EEXIST; | |
1888 | } | |
1889 | ||
1890 | il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS; | |
1891 | memcpy(&sta_cmd, &il->stations[sta_id].sta, | |
e7392364 | 1892 | sizeof(struct il_addsta_cmd)); |
0cdc2136 SG |
1893 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); |
1894 | ||
1895 | /* Add station to device's station table */ | |
1896 | ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC); | |
1897 | if (ret) { | |
1898 | spin_lock_irqsave(&il->sta_lock, flags_spin); | |
1899 | IL_ERR("Adding station %pM failed.\n", | |
e7392364 | 1900 | il->stations[sta_id].sta.sta.addr); |
0cdc2136 SG |
1901 | il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE; |
1902 | il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS; | |
1903 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
1904 | } | |
1905 | *sta_id_r = sta_id; | |
1906 | return ret; | |
1907 | } | |
e7392364 | 1908 | |
0cdc2136 SG |
1909 | EXPORT_SYMBOL(il_add_station_common); |
1910 | ||
1911 | /** | |
1912 | * il_sta_ucode_deactivate - deactivate ucode status for a station | |
1913 | * | |
1914 | * il->sta_lock must be held | |
1915 | */ | |
e7392364 SG |
1916 | static void |
1917 | il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id) | |
0cdc2136 SG |
1918 | { |
1919 | /* Ucode must be active and driver must be non active */ | |
e7392364 SG |
1920 | if ((il->stations[sta_id]. |
1921 | used & (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) != | |
1922 | IL_STA_UCODE_ACTIVE) | |
0cdc2136 SG |
1923 | IL_ERR("removed non active STA %u\n", sta_id); |
1924 | ||
1925 | il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE; | |
1926 | ||
1927 | memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry)); | |
1928 | D_ASSOC("Removed STA %u\n", sta_id); | |
1929 | } | |
1930 | ||
e7392364 SG |
1931 | static int |
1932 | il_send_remove_station(struct il_priv *il, const u8 * addr, int sta_id, | |
1933 | bool temporary) | |
0cdc2136 SG |
1934 | { |
1935 | struct il_rx_pkt *pkt; | |
1936 | int ret; | |
1937 | ||
1938 | unsigned long flags_spin; | |
1939 | struct il_rem_sta_cmd rm_sta_cmd; | |
1940 | ||
1941 | struct il_host_cmd cmd = { | |
1942 | .id = C_REM_STA, | |
1943 | .len = sizeof(struct il_rem_sta_cmd), | |
1944 | .flags = CMD_SYNC, | |
1945 | .data = &rm_sta_cmd, | |
1946 | }; | |
1947 | ||
1948 | memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd)); | |
1949 | rm_sta_cmd.num_sta = 1; | |
1950 | memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN); | |
1951 | ||
1952 | cmd.flags |= CMD_WANT_SKB; | |
1953 | ||
1954 | ret = il_send_cmd(il, &cmd); | |
1955 | ||
1956 | if (ret) | |
1957 | return ret; | |
1958 | ||
1959 | pkt = (struct il_rx_pkt *)cmd.reply_page; | |
1960 | if (pkt->hdr.flags & IL_CMD_FAILED_MSK) { | |
e7392364 | 1961 | IL_ERR("Bad return from C_REM_STA (0x%08X)\n", pkt->hdr.flags); |
0cdc2136 SG |
1962 | ret = -EIO; |
1963 | } | |
1964 | ||
1965 | if (!ret) { | |
1966 | switch (pkt->u.rem_sta.status) { | |
1967 | case REM_STA_SUCCESS_MSK: | |
1968 | if (!temporary) { | |
1969 | spin_lock_irqsave(&il->sta_lock, flags_spin); | |
1970 | il_sta_ucode_deactivate(il, sta_id); | |
1971 | spin_unlock_irqrestore(&il->sta_lock, | |
e7392364 | 1972 | flags_spin); |
0cdc2136 SG |
1973 | } |
1974 | D_ASSOC("C_REM_STA PASSED\n"); | |
1975 | break; | |
1976 | default: | |
1977 | ret = -EIO; | |
1978 | IL_ERR("C_REM_STA failed\n"); | |
1979 | break; | |
1980 | } | |
1981 | } | |
1982 | il_free_pages(il, cmd.reply_page); | |
1983 | ||
1984 | return ret; | |
1985 | } | |
1986 | ||
1987 | /** | |
1988 | * il_remove_station - Remove driver's knowledge of station. | |
1989 | */ | |
e7392364 SG |
1990 | int |
1991 | il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr) | |
0cdc2136 SG |
1992 | { |
1993 | unsigned long flags; | |
1994 | ||
1995 | if (!il_is_ready(il)) { | |
e7392364 SG |
1996 | D_INFO("Unable to remove station %pM, device not ready.\n", |
1997 | addr); | |
0cdc2136 SG |
1998 | /* |
1999 | * It is typical for stations to be removed when we are | |
2000 | * going down. Return success since device will be down | |
2001 | * soon anyway | |
2002 | */ | |
2003 | return 0; | |
2004 | } | |
2005 | ||
e7392364 | 2006 | D_ASSOC("Removing STA from driver:%d %pM\n", sta_id, addr); |
0cdc2136 SG |
2007 | |
2008 | if (WARN_ON(sta_id == IL_INVALID_STATION)) | |
2009 | return -EINVAL; | |
2010 | ||
2011 | spin_lock_irqsave(&il->sta_lock, flags); | |
2012 | ||
2013 | if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) { | |
e7392364 | 2014 | D_INFO("Removing %pM but non DRIVER active\n", addr); |
0cdc2136 SG |
2015 | goto out_err; |
2016 | } | |
2017 | ||
2018 | if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) { | |
e7392364 | 2019 | D_INFO("Removing %pM but non UCODE active\n", addr); |
0cdc2136 SG |
2020 | goto out_err; |
2021 | } | |
2022 | ||
2023 | if (il->stations[sta_id].used & IL_STA_LOCAL) { | |
2024 | kfree(il->stations[sta_id].lq); | |
2025 | il->stations[sta_id].lq = NULL; | |
2026 | } | |
2027 | ||
2028 | il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE; | |
2029 | ||
2030 | il->num_stations--; | |
2031 | ||
2032 | BUG_ON(il->num_stations < 0); | |
2033 | ||
2034 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
2035 | ||
2036 | return il_send_remove_station(il, addr, sta_id, false); | |
2037 | out_err: | |
2038 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
2039 | return -EINVAL; | |
2040 | } | |
e7392364 | 2041 | |
0cdc2136 SG |
2042 | EXPORT_SYMBOL_GPL(il_remove_station); |
2043 | ||
2044 | /** | |
2045 | * il_clear_ucode_stations - clear ucode station table bits | |
2046 | * | |
2047 | * This function clears all the bits in the driver indicating | |
2048 | * which stations are active in the ucode. Call when something | |
2049 | * other than explicit station management would cause this in | |
2050 | * the ucode, e.g. unassociated RXON. | |
2051 | */ | |
e7392364 SG |
2052 | void |
2053 | il_clear_ucode_stations(struct il_priv *il, struct il_rxon_context *ctx) | |
0cdc2136 SG |
2054 | { |
2055 | int i; | |
2056 | unsigned long flags_spin; | |
2057 | bool cleared = false; | |
2058 | ||
2059 | D_INFO("Clearing ucode stations in driver\n"); | |
2060 | ||
2061 | spin_lock_irqsave(&il->sta_lock, flags_spin); | |
2062 | for (i = 0; i < il->hw_params.max_stations; i++) { | |
2063 | if (ctx && ctx->ctxid != il->stations[i].ctxid) | |
2064 | continue; | |
2065 | ||
2066 | if (il->stations[i].used & IL_STA_UCODE_ACTIVE) { | |
e7392364 | 2067 | D_INFO("Clearing ucode active for station %d\n", i); |
0cdc2136 SG |
2068 | il->stations[i].used &= ~IL_STA_UCODE_ACTIVE; |
2069 | cleared = true; | |
2070 | } | |
2071 | } | |
2072 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
2073 | ||
2074 | if (!cleared) | |
e7392364 | 2075 | D_INFO("No active stations found to be cleared\n"); |
0cdc2136 | 2076 | } |
e7392364 | 2077 | |
0cdc2136 SG |
2078 | EXPORT_SYMBOL(il_clear_ucode_stations); |
2079 | ||
2080 | /** | |
2081 | * il_restore_stations() - Restore driver known stations to device | |
2082 | * | |
2083 | * All stations considered active by driver, but not present in ucode, is | |
2084 | * restored. | |
2085 | * | |
2086 | * Function sleeps. | |
2087 | */ | |
2088 | void | |
2089 | il_restore_stations(struct il_priv *il, struct il_rxon_context *ctx) | |
2090 | { | |
2091 | struct il_addsta_cmd sta_cmd; | |
2092 | struct il_link_quality_cmd lq; | |
2093 | unsigned long flags_spin; | |
2094 | int i; | |
2095 | bool found = false; | |
2096 | int ret; | |
2097 | bool send_lq; | |
2098 | ||
2099 | if (!il_is_ready(il)) { | |
e7392364 | 2100 | D_INFO("Not ready yet, not restoring any stations.\n"); |
0cdc2136 SG |
2101 | return; |
2102 | } | |
2103 | ||
2104 | D_ASSOC("Restoring all known stations ... start.\n"); | |
2105 | spin_lock_irqsave(&il->sta_lock, flags_spin); | |
2106 | for (i = 0; i < il->hw_params.max_stations; i++) { | |
2107 | if (ctx->ctxid != il->stations[i].ctxid) | |
2108 | continue; | |
2109 | if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) && | |
2110 | !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) { | |
2111 | D_ASSOC("Restoring sta %pM\n", | |
e7392364 | 2112 | il->stations[i].sta.sta.addr); |
0cdc2136 SG |
2113 | il->stations[i].sta.mode = 0; |
2114 | il->stations[i].used |= IL_STA_UCODE_INPROGRESS; | |
2115 | found = true; | |
2116 | } | |
2117 | } | |
2118 | ||
2119 | for (i = 0; i < il->hw_params.max_stations; i++) { | |
2120 | if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) { | |
2121 | memcpy(&sta_cmd, &il->stations[i].sta, | |
2122 | sizeof(struct il_addsta_cmd)); | |
2123 | send_lq = false; | |
2124 | if (il->stations[i].lq) { | |
2125 | memcpy(&lq, il->stations[i].lq, | |
2126 | sizeof(struct il_link_quality_cmd)); | |
2127 | send_lq = true; | |
2128 | } | |
2129 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
2130 | ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC); | |
2131 | if (ret) { | |
2132 | spin_lock_irqsave(&il->sta_lock, flags_spin); | |
2133 | IL_ERR("Adding station %pM failed.\n", | |
e7392364 SG |
2134 | il->stations[i].sta.sta.addr); |
2135 | il->stations[i].used &= ~IL_STA_DRIVER_ACTIVE; | |
0cdc2136 | 2136 | il->stations[i].used &= |
e7392364 | 2137 | ~IL_STA_UCODE_INPROGRESS; |
0cdc2136 | 2138 | spin_unlock_irqrestore(&il->sta_lock, |
e7392364 | 2139 | flags_spin); |
0cdc2136 SG |
2140 | } |
2141 | /* | |
2142 | * Rate scaling has already been initialized, send | |
2143 | * current LQ command | |
2144 | */ | |
2145 | if (send_lq) | |
e7392364 | 2146 | il_send_lq_cmd(il, ctx, &lq, CMD_SYNC, true); |
0cdc2136 SG |
2147 | spin_lock_irqsave(&il->sta_lock, flags_spin); |
2148 | il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS; | |
2149 | } | |
2150 | } | |
2151 | ||
2152 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
2153 | if (!found) | |
2154 | D_INFO("Restoring all known stations" | |
e7392364 | 2155 | " .... no stations to be restored.\n"); |
0cdc2136 | 2156 | else |
e7392364 | 2157 | D_INFO("Restoring all known stations" " .... complete.\n"); |
0cdc2136 | 2158 | } |
e7392364 | 2159 | |
0cdc2136 SG |
2160 | EXPORT_SYMBOL(il_restore_stations); |
2161 | ||
e7392364 SG |
2162 | int |
2163 | il_get_free_ucode_key_idx(struct il_priv *il) | |
0cdc2136 SG |
2164 | { |
2165 | int i; | |
2166 | ||
2167 | for (i = 0; i < il->sta_key_max_num; i++) | |
2168 | if (!test_and_set_bit(i, &il->ucode_key_table)) | |
2169 | return i; | |
2170 | ||
2171 | return WEP_INVALID_OFFSET; | |
2172 | } | |
e7392364 | 2173 | |
0cdc2136 SG |
2174 | EXPORT_SYMBOL(il_get_free_ucode_key_idx); |
2175 | ||
e7392364 SG |
2176 | void |
2177 | il_dealloc_bcast_stations(struct il_priv *il) | |
0cdc2136 SG |
2178 | { |
2179 | unsigned long flags; | |
2180 | int i; | |
2181 | ||
2182 | spin_lock_irqsave(&il->sta_lock, flags); | |
2183 | for (i = 0; i < il->hw_params.max_stations; i++) { | |
2184 | if (!(il->stations[i].used & IL_STA_BCAST)) | |
2185 | continue; | |
2186 | ||
2187 | il->stations[i].used &= ~IL_STA_UCODE_ACTIVE; | |
2188 | il->num_stations--; | |
2189 | BUG_ON(il->num_stations < 0); | |
2190 | kfree(il->stations[i].lq); | |
2191 | il->stations[i].lq = NULL; | |
2192 | } | |
2193 | spin_unlock_irqrestore(&il->sta_lock, flags); | |
2194 | } | |
e7392364 | 2195 | |
0cdc2136 SG |
2196 | EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations); |
2197 | ||
2198 | #ifdef CONFIG_IWLEGACY_DEBUG | |
e7392364 SG |
2199 | static void |
2200 | il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq) | |
0cdc2136 SG |
2201 | { |
2202 | int i; | |
2203 | D_RATE("lq station id 0x%x\n", lq->sta_id); | |
e7392364 SG |
2204 | D_RATE("lq ant 0x%X 0x%X\n", lq->general_params.single_stream_ant_msk, |
2205 | lq->general_params.dual_stream_ant_msk); | |
0cdc2136 SG |
2206 | |
2207 | for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) | |
e7392364 | 2208 | D_RATE("lq idx %d 0x%X\n", i, lq->rs_table[i].rate_n_flags); |
0cdc2136 SG |
2209 | } |
2210 | #else | |
e7392364 SG |
2211 | static inline void |
2212 | il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq) | |
0cdc2136 SG |
2213 | { |
2214 | } | |
2215 | #endif | |
2216 | ||
2217 | /** | |
2218 | * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity | |
2219 | * | |
2220 | * It sometimes happens when a HT rate has been in use and we | |
2221 | * loose connectivity with AP then mac80211 will first tell us that the | |
2222 | * current channel is not HT anymore before removing the station. In such a | |
2223 | * scenario the RXON flags will be updated to indicate we are not | |
2224 | * communicating HT anymore, but the LQ command may still contain HT rates. | |
2225 | * Test for this to prevent driver from sending LQ command between the time | |
2226 | * RXON flags are updated and when LQ command is updated. | |
2227 | */ | |
e7392364 SG |
2228 | static bool |
2229 | il_is_lq_table_valid(struct il_priv *il, struct il_rxon_context *ctx, | |
2230 | struct il_link_quality_cmd *lq) | |
0cdc2136 SG |
2231 | { |
2232 | int i; | |
2233 | ||
2234 | if (ctx->ht.enabled) | |
2235 | return true; | |
2236 | ||
e7392364 | 2237 | D_INFO("Channel %u is not an HT channel\n", ctx->active.channel); |
0cdc2136 | 2238 | for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) { |
e7392364 SG |
2239 | if (le32_to_cpu(lq->rs_table[i].rate_n_flags) & RATE_MCS_HT_MSK) { |
2240 | D_INFO("idx %d of LQ expects HT channel\n", i); | |
0cdc2136 SG |
2241 | return false; |
2242 | } | |
2243 | } | |
2244 | return true; | |
2245 | } | |
2246 | ||
2247 | /** | |
2248 | * il_send_lq_cmd() - Send link quality command | |
2249 | * @init: This command is sent as part of station initialization right | |
2250 | * after station has been added. | |
2251 | * | |
2252 | * The link quality command is sent as the last step of station creation. | |
2253 | * This is the special case in which init is set and we call a callback in | |
2254 | * this case to clear the state indicating that station creation is in | |
2255 | * progress. | |
2256 | */ | |
e7392364 SG |
2257 | int |
2258 | il_send_lq_cmd(struct il_priv *il, struct il_rxon_context *ctx, | |
2259 | struct il_link_quality_cmd *lq, u8 flags, bool init) | |
0cdc2136 SG |
2260 | { |
2261 | int ret = 0; | |
2262 | unsigned long flags_spin; | |
2263 | ||
2264 | struct il_host_cmd cmd = { | |
2265 | .id = C_TX_LINK_QUALITY_CMD, | |
2266 | .len = sizeof(struct il_link_quality_cmd), | |
2267 | .flags = flags, | |
2268 | .data = lq, | |
2269 | }; | |
2270 | ||
2271 | if (WARN_ON(lq->sta_id == IL_INVALID_STATION)) | |
2272 | return -EINVAL; | |
2273 | ||
0cdc2136 SG |
2274 | spin_lock_irqsave(&il->sta_lock, flags_spin); |
2275 | if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) { | |
2276 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
2277 | return -EINVAL; | |
2278 | } | |
2279 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
2280 | ||
2281 | il_dump_lq_cmd(il, lq); | |
2282 | BUG_ON(init && (cmd.flags & CMD_ASYNC)); | |
2283 | ||
2284 | if (il_is_lq_table_valid(il, ctx, lq)) | |
2285 | ret = il_send_cmd(il, &cmd); | |
2286 | else | |
2287 | ret = -EINVAL; | |
2288 | ||
2289 | if (cmd.flags & CMD_ASYNC) | |
2290 | return ret; | |
2291 | ||
2292 | if (init) { | |
2293 | D_INFO("init LQ command complete," | |
e7392364 SG |
2294 | " clearing sta addition status for sta %d\n", |
2295 | lq->sta_id); | |
0cdc2136 SG |
2296 | spin_lock_irqsave(&il->sta_lock, flags_spin); |
2297 | il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS; | |
2298 | spin_unlock_irqrestore(&il->sta_lock, flags_spin); | |
2299 | } | |
2300 | return ret; | |
2301 | } | |
e7392364 | 2302 | |
0cdc2136 SG |
2303 | EXPORT_SYMBOL(il_send_lq_cmd); |
2304 | ||
e7392364 SG |
2305 | int |
2306 | il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
2307 | struct ieee80211_sta *sta) | |
0cdc2136 SG |
2308 | { |
2309 | struct il_priv *il = hw->priv; | |
2310 | struct il_station_priv_common *sta_common = (void *)sta->drv_priv; | |
2311 | int ret; | |
2312 | ||
e7392364 | 2313 | D_INFO("received request to remove station %pM\n", sta->addr); |
0cdc2136 | 2314 | mutex_lock(&il->mutex); |
e7392364 | 2315 | D_INFO("proceeding to remove station %pM\n", sta->addr); |
0cdc2136 SG |
2316 | ret = il_remove_station(il, sta_common->sta_id, sta->addr); |
2317 | if (ret) | |
e7392364 | 2318 | IL_ERR("Error removing station %pM\n", sta->addr); |
0cdc2136 SG |
2319 | mutex_unlock(&il->mutex); |
2320 | return ret; | |
2321 | } | |
e7392364 | 2322 | |
0cdc2136 SG |
2323 | EXPORT_SYMBOL(il_mac_sta_remove); |
2324 | ||
2325 | /************************** RX-FUNCTIONS ****************************/ | |
2326 | /* | |
2327 | * Rx theory of operation | |
2328 | * | |
2329 | * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs), | |
2330 | * each of which point to Receive Buffers to be filled by the NIC. These get | |
2331 | * used not only for Rx frames, but for any command response or notification | |
2332 | * from the NIC. The driver and NIC manage the Rx buffers by means | |
2333 | * of idxes into the circular buffer. | |
2334 | * | |
2335 | * Rx Queue Indexes | |
2336 | * The host/firmware share two idx registers for managing the Rx buffers. | |
2337 | * | |
2338 | * The READ idx maps to the first position that the firmware may be writing | |
2339 | * to -- the driver can read up to (but not including) this position and get | |
2340 | * good data. | |
2341 | * The READ idx is managed by the firmware once the card is enabled. | |
2342 | * | |
2343 | * The WRITE idx maps to the last position the driver has read from -- the | |
2344 | * position preceding WRITE is the last slot the firmware can place a packet. | |
2345 | * | |
2346 | * The queue is empty (no good data) if WRITE = READ - 1, and is full if | |
2347 | * WRITE = READ. | |
2348 | * | |
2349 | * During initialization, the host sets up the READ queue position to the first | |
2350 | * IDX position, and WRITE to the last (READ - 1 wrapped) | |
2351 | * | |
2352 | * When the firmware places a packet in a buffer, it will advance the READ idx | |
2353 | * and fire the RX interrupt. The driver can then query the READ idx and | |
2354 | * process as many packets as possible, moving the WRITE idx forward as it | |
2355 | * resets the Rx queue buffers with new memory. | |
2356 | * | |
2357 | * The management in the driver is as follows: | |
2358 | * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When | |
2359 | * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled | |
2360 | * to replenish the iwl->rxq->rx_free. | |
2361 | * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the | |
2362 | * iwl->rxq is replenished and the READ IDX is updated (updating the | |
2363 | * 'processed' and 'read' driver idxes as well) | |
2364 | * + A received packet is processed and handed to the kernel network stack, | |
2365 | * detached from the iwl->rxq. The driver 'processed' idx is updated. | |
2366 | * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free | |
2367 | * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ | |
2368 | * IDX is not incremented and iwl->status(RX_STALLED) is set. If there | |
2369 | * were enough free buffers and RX_STALLED is set it is cleared. | |
2370 | * | |
2371 | * | |
2372 | * Driver sequence: | |
2373 | * | |
2374 | * il_rx_queue_alloc() Allocates rx_free | |
2375 | * il_rx_replenish() Replenishes rx_free list from rx_used, and calls | |
2376 | * il_rx_queue_restock | |
2377 | * il_rx_queue_restock() Moves available buffers from rx_free into Rx | |
2378 | * queue, updates firmware pointers, and updates | |
2379 | * the WRITE idx. If insufficient rx_free buffers | |
2380 | * are available, schedules il_rx_replenish | |
2381 | * | |
2382 | * -- enable interrupts -- | |
2383 | * ISR - il_rx() Detach il_rx_bufs from pool up to the | |
2384 | * READ IDX, detaching the SKB from the pool. | |
2385 | * Moves the packet buffer from queue to rx_used. | |
2386 | * Calls il_rx_queue_restock to refill any empty | |
2387 | * slots. | |
2388 | * ... | |
2389 | * | |
2390 | */ | |
2391 | ||
2392 | /** | |
2393 | * il_rx_queue_space - Return number of free slots available in queue. | |
2394 | */ | |
e7392364 SG |
2395 | int |
2396 | il_rx_queue_space(const struct il_rx_queue *q) | |
0cdc2136 SG |
2397 | { |
2398 | int s = q->read - q->write; | |
2399 | if (s <= 0) | |
2400 | s += RX_QUEUE_SIZE; | |
2401 | /* keep some buffer to not confuse full and empty queue */ | |
2402 | s -= 2; | |
2403 | if (s < 0) | |
2404 | s = 0; | |
2405 | return s; | |
2406 | } | |
e7392364 | 2407 | |
0cdc2136 SG |
2408 | EXPORT_SYMBOL(il_rx_queue_space); |
2409 | ||
2410 | /** | |
2411 | * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue | |
2412 | */ | |
2413 | void | |
e7392364 | 2414 | il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q) |
0cdc2136 SG |
2415 | { |
2416 | unsigned long flags; | |
2417 | u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg; | |
2418 | u32 reg; | |
2419 | ||
2420 | spin_lock_irqsave(&q->lock, flags); | |
2421 | ||
2422 | if (q->need_update == 0) | |
2423 | goto exit_unlock; | |
2424 | ||
2425 | /* If power-saving is in use, make sure device is awake */ | |
2426 | if (test_bit(S_POWER_PMI, &il->status)) { | |
2427 | reg = _il_rd(il, CSR_UCODE_DRV_GP1); | |
2428 | ||
2429 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
e7392364 SG |
2430 | D_INFO("Rx queue requesting wakeup," " GP1 = 0x%x\n", |
2431 | reg); | |
0cdc2136 | 2432 | il_set_bit(il, CSR_GP_CNTRL, |
e7392364 | 2433 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
0cdc2136 SG |
2434 | goto exit_unlock; |
2435 | } | |
2436 | ||
2437 | q->write_actual = (q->write & ~0x7); | |
e7392364 | 2438 | il_wr(il, rx_wrt_ptr_reg, q->write_actual); |
0cdc2136 | 2439 | |
e7392364 | 2440 | /* Else device is assumed to be awake */ |
0cdc2136 SG |
2441 | } else { |
2442 | /* Device expects a multiple of 8 */ | |
2443 | q->write_actual = (q->write & ~0x7); | |
e7392364 | 2444 | il_wr(il, rx_wrt_ptr_reg, q->write_actual); |
0cdc2136 SG |
2445 | } |
2446 | ||
2447 | q->need_update = 0; | |
2448 | ||
e7392364 | 2449 | exit_unlock: |
0cdc2136 SG |
2450 | spin_unlock_irqrestore(&q->lock, flags); |
2451 | } | |
e7392364 | 2452 | |
0cdc2136 SG |
2453 | EXPORT_SYMBOL(il_rx_queue_update_write_ptr); |
2454 | ||
e7392364 SG |
2455 | int |
2456 | il_rx_queue_alloc(struct il_priv *il) | |
0cdc2136 SG |
2457 | { |
2458 | struct il_rx_queue *rxq = &il->rxq; | |
2459 | struct device *dev = &il->pci_dev->dev; | |
2460 | int i; | |
2461 | ||
2462 | spin_lock_init(&rxq->lock); | |
2463 | INIT_LIST_HEAD(&rxq->rx_free); | |
2464 | INIT_LIST_HEAD(&rxq->rx_used); | |
2465 | ||
2466 | /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */ | |
e7392364 SG |
2467 | rxq->bd = |
2468 | dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma, | |
2469 | GFP_KERNEL); | |
0cdc2136 SG |
2470 | if (!rxq->bd) |
2471 | goto err_bd; | |
2472 | ||
e7392364 SG |
2473 | rxq->rb_stts = |
2474 | dma_alloc_coherent(dev, sizeof(struct il_rb_status), | |
2475 | &rxq->rb_stts_dma, GFP_KERNEL); | |
0cdc2136 SG |
2476 | if (!rxq->rb_stts) |
2477 | goto err_rb; | |
2478 | ||
2479 | /* Fill the rx_used queue with _all_ of the Rx buffers */ | |
2480 | for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) | |
2481 | list_add_tail(&rxq->pool[i].list, &rxq->rx_used); | |
2482 | ||
2483 | /* Set us so that we have processed and used all buffers, but have | |
2484 | * not restocked the Rx queue with fresh buffers */ | |
2485 | rxq->read = rxq->write = 0; | |
2486 | rxq->write_actual = 0; | |
2487 | rxq->free_count = 0; | |
2488 | rxq->need_update = 0; | |
2489 | return 0; | |
2490 | ||
2491 | err_rb: | |
2492 | dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd, | |
2493 | rxq->bd_dma); | |
2494 | err_bd: | |
2495 | return -ENOMEM; | |
2496 | } | |
0cdc2136 | 2497 | |
e7392364 | 2498 | EXPORT_SYMBOL(il_rx_queue_alloc); |
0cdc2136 | 2499 | |
e7392364 SG |
2500 | void |
2501 | il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb) | |
0cdc2136 SG |
2502 | { |
2503 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
2504 | struct il_spectrum_notification *report = &(pkt->u.spectrum_notif); | |
2505 | ||
2506 | if (!report->state) { | |
e7392364 | 2507 | D_11H("Spectrum Measure Notification: Start\n"); |
0cdc2136 SG |
2508 | return; |
2509 | } | |
2510 | ||
2511 | memcpy(&il->measure_report, report, sizeof(*report)); | |
2512 | il->measurement_status |= MEASUREMENT_READY; | |
2513 | } | |
e7392364 | 2514 | |
0cdc2136 SG |
2515 | EXPORT_SYMBOL(il_hdl_spectrum_measurement); |
2516 | ||
2517 | /* | |
2518 | * returns non-zero if packet should be dropped | |
2519 | */ | |
e7392364 SG |
2520 | int |
2521 | il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr, | |
2522 | u32 decrypt_res, struct ieee80211_rx_status *stats) | |
0cdc2136 SG |
2523 | { |
2524 | u16 fc = le16_to_cpu(hdr->frame_control); | |
2525 | ||
2526 | /* | |
2527 | * All contexts have the same setting here due to it being | |
2528 | * a module parameter, so OK to check any context. | |
2529 | */ | |
e7392364 | 2530 | if (il->ctx.active.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK) |
0cdc2136 SG |
2531 | return 0; |
2532 | ||
2533 | if (!(fc & IEEE80211_FCTL_PROTECTED)) | |
2534 | return 0; | |
2535 | ||
2536 | D_RX("decrypt_res:0x%x\n", decrypt_res); | |
2537 | switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) { | |
2538 | case RX_RES_STATUS_SEC_TYPE_TKIP: | |
2539 | /* The uCode has got a bad phase 1 Key, pushes the packet. | |
2540 | * Decryption will be done in SW. */ | |
2541 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2542 | RX_RES_STATUS_BAD_KEY_TTAK) | |
2543 | break; | |
2544 | ||
2545 | case RX_RES_STATUS_SEC_TYPE_WEP: | |
2546 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2547 | RX_RES_STATUS_BAD_ICV_MIC) { | |
2548 | /* bad ICV, the packet is destroyed since the | |
2549 | * decryption is inplace, drop it */ | |
2550 | D_RX("Packet destroyed\n"); | |
2551 | return -1; | |
2552 | } | |
2553 | case RX_RES_STATUS_SEC_TYPE_CCMP: | |
2554 | if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) == | |
2555 | RX_RES_STATUS_DECRYPT_OK) { | |
2556 | D_RX("hw decrypt successfully!!!\n"); | |
2557 | stats->flag |= RX_FLAG_DECRYPTED; | |
2558 | } | |
2559 | break; | |
2560 | ||
2561 | default: | |
2562 | break; | |
2563 | } | |
2564 | return 0; | |
2565 | } | |
e7392364 | 2566 | |
0cdc2136 SG |
2567 | EXPORT_SYMBOL(il_set_decrypted_flag); |
2568 | ||
2569 | /** | |
2570 | * il_txq_update_write_ptr - Send new write idx to hardware | |
2571 | */ | |
2572 | void | |
2573 | il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq) | |
2574 | { | |
2575 | u32 reg = 0; | |
2576 | int txq_id = txq->q.id; | |
2577 | ||
2578 | if (txq->need_update == 0) | |
2579 | return; | |
2580 | ||
2581 | /* if we're trying to save power */ | |
2582 | if (test_bit(S_POWER_PMI, &il->status)) { | |
2583 | /* wake up nic if it's powered down ... | |
2584 | * uCode will wake up, and interrupt us again, so next | |
2585 | * time we'll skip this part. */ | |
2586 | reg = _il_rd(il, CSR_UCODE_DRV_GP1); | |
2587 | ||
2588 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { | |
e7392364 SG |
2589 | D_INFO("Tx queue %d requesting wakeup," " GP1 = 0x%x\n", |
2590 | txq_id, reg); | |
0cdc2136 | 2591 | il_set_bit(il, CSR_GP_CNTRL, |
e7392364 | 2592 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
0cdc2136 SG |
2593 | return; |
2594 | } | |
2595 | ||
e7392364 | 2596 | il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8)); |
0cdc2136 SG |
2597 | |
2598 | /* | |
2599 | * else not in power-save mode, | |
2600 | * uCode will never sleep when we're | |
2601 | * trying to tx (during RFKILL, we're not trying to tx). | |
2602 | */ | |
2603 | } else | |
e7392364 | 2604 | _il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8)); |
0cdc2136 SG |
2605 | txq->need_update = 0; |
2606 | } | |
e7392364 | 2607 | |
0cdc2136 SG |
2608 | EXPORT_SYMBOL(il_txq_update_write_ptr); |
2609 | ||
2610 | /** | |
2611 | * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's | |
2612 | */ | |
e7392364 SG |
2613 | void |
2614 | il_tx_queue_unmap(struct il_priv *il, int txq_id) | |
0cdc2136 SG |
2615 | { |
2616 | struct il_tx_queue *txq = &il->txq[txq_id]; | |
2617 | struct il_queue *q = &txq->q; | |
2618 | ||
2619 | if (q->n_bd == 0) | |
2620 | return; | |
2621 | ||
2622 | while (q->write_ptr != q->read_ptr) { | |
2623 | il->cfg->ops->lib->txq_free_tfd(il, txq); | |
2624 | q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd); | |
2625 | } | |
2626 | } | |
e7392364 | 2627 | |
0cdc2136 SG |
2628 | EXPORT_SYMBOL(il_tx_queue_unmap); |
2629 | ||
2630 | /** | |
2631 | * il_tx_queue_free - Deallocate DMA queue. | |
2632 | * @txq: Transmit queue to deallocate. | |
2633 | * | |
2634 | * Empty queue by removing and destroying all BD's. | |
2635 | * Free all buffers. | |
2636 | * 0-fill, but do not free "txq" descriptor structure. | |
2637 | */ | |
e7392364 SG |
2638 | void |
2639 | il_tx_queue_free(struct il_priv *il, int txq_id) | |
0cdc2136 SG |
2640 | { |
2641 | struct il_tx_queue *txq = &il->txq[txq_id]; | |
2642 | struct device *dev = &il->pci_dev->dev; | |
2643 | int i; | |
2644 | ||
2645 | il_tx_queue_unmap(il, txq_id); | |
2646 | ||
2647 | /* De-alloc array of command/tx buffers */ | |
2648 | for (i = 0; i < TFD_TX_CMD_SLOTS; i++) | |
2649 | kfree(txq->cmd[i]); | |
2650 | ||
2651 | /* De-alloc circular buffer of TFDs */ | |
2652 | if (txq->q.n_bd) | |
e7392364 SG |
2653 | dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd, |
2654 | txq->tfds, txq->q.dma_addr); | |
0cdc2136 SG |
2655 | |
2656 | /* De-alloc array of per-TFD driver data */ | |
2657 | kfree(txq->txb); | |
2658 | txq->txb = NULL; | |
2659 | ||
2660 | /* deallocate arrays */ | |
2661 | kfree(txq->cmd); | |
2662 | kfree(txq->meta); | |
2663 | txq->cmd = NULL; | |
2664 | txq->meta = NULL; | |
2665 | ||
2666 | /* 0-fill queue descriptor structure */ | |
2667 | memset(txq, 0, sizeof(*txq)); | |
2668 | } | |
e7392364 | 2669 | |
0cdc2136 SG |
2670 | EXPORT_SYMBOL(il_tx_queue_free); |
2671 | ||
2672 | /** | |
2673 | * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue | |
2674 | */ | |
e7392364 SG |
2675 | void |
2676 | il_cmd_queue_unmap(struct il_priv *il) | |
0cdc2136 SG |
2677 | { |
2678 | struct il_tx_queue *txq = &il->txq[il->cmd_queue]; | |
2679 | struct il_queue *q = &txq->q; | |
2680 | int i; | |
2681 | ||
2682 | if (q->n_bd == 0) | |
2683 | return; | |
2684 | ||
2685 | while (q->read_ptr != q->write_ptr) { | |
2686 | i = il_get_cmd_idx(q, q->read_ptr, 0); | |
2687 | ||
2688 | if (txq->meta[i].flags & CMD_MAPPED) { | |
2689 | pci_unmap_single(il->pci_dev, | |
2690 | dma_unmap_addr(&txq->meta[i], mapping), | |
2691 | dma_unmap_len(&txq->meta[i], len), | |
2692 | PCI_DMA_BIDIRECTIONAL); | |
2693 | txq->meta[i].flags = 0; | |
2694 | } | |
2695 | ||
2696 | q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd); | |
2697 | } | |
2698 | ||
2699 | i = q->n_win; | |
2700 | if (txq->meta[i].flags & CMD_MAPPED) { | |
2701 | pci_unmap_single(il->pci_dev, | |
2702 | dma_unmap_addr(&txq->meta[i], mapping), | |
2703 | dma_unmap_len(&txq->meta[i], len), | |
2704 | PCI_DMA_BIDIRECTIONAL); | |
2705 | txq->meta[i].flags = 0; | |
2706 | } | |
2707 | } | |
e7392364 | 2708 | |
0cdc2136 SG |
2709 | EXPORT_SYMBOL(il_cmd_queue_unmap); |
2710 | ||
2711 | /** | |
2712 | * il_cmd_queue_free - Deallocate DMA queue. | |
2713 | * @txq: Transmit queue to deallocate. | |
2714 | * | |
2715 | * Empty queue by removing and destroying all BD's. | |
2716 | * Free all buffers. | |
2717 | * 0-fill, but do not free "txq" descriptor structure. | |
2718 | */ | |
e7392364 SG |
2719 | void |
2720 | il_cmd_queue_free(struct il_priv *il) | |
0cdc2136 SG |
2721 | { |
2722 | struct il_tx_queue *txq = &il->txq[il->cmd_queue]; | |
2723 | struct device *dev = &il->pci_dev->dev; | |
2724 | int i; | |
2725 | ||
2726 | il_cmd_queue_unmap(il); | |
2727 | ||
2728 | /* De-alloc array of command/tx buffers */ | |
2729 | for (i = 0; i <= TFD_CMD_SLOTS; i++) | |
2730 | kfree(txq->cmd[i]); | |
2731 | ||
2732 | /* De-alloc circular buffer of TFDs */ | |
2733 | if (txq->q.n_bd) | |
2734 | dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd, | |
2735 | txq->tfds, txq->q.dma_addr); | |
2736 | ||
2737 | /* deallocate arrays */ | |
2738 | kfree(txq->cmd); | |
2739 | kfree(txq->meta); | |
2740 | txq->cmd = NULL; | |
2741 | txq->meta = NULL; | |
2742 | ||
2743 | /* 0-fill queue descriptor structure */ | |
2744 | memset(txq, 0, sizeof(*txq)); | |
2745 | } | |
e7392364 | 2746 | |
0cdc2136 SG |
2747 | EXPORT_SYMBOL(il_cmd_queue_free); |
2748 | ||
2749 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** | |
2750 | * DMA services | |
2751 | * | |
2752 | * Theory of operation | |
2753 | * | |
2754 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
2755 | * of buffer descriptors, each of which points to one or more data buffers for | |
2756 | * the device to read from or fill. Driver and device exchange status of each | |
2757 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
2758 | * entries in each circular buffer, to protect against confusing empty and full | |
2759 | * queue states. | |
2760 | * | |
2761 | * The device reads or writes the data in the queues via the device's several | |
2762 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
2763 | * | |
2764 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
2765 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
2766 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
2767 | * Tx queue resumed. | |
2768 | * | |
2769 | * See more detailed info in 4965.h. | |
2770 | ***************************************************/ | |
2771 | ||
e7392364 SG |
2772 | int |
2773 | il_queue_space(const struct il_queue *q) | |
0cdc2136 SG |
2774 | { |
2775 | int s = q->read_ptr - q->write_ptr; | |
2776 | ||
2777 | if (q->read_ptr > q->write_ptr) | |
2778 | s -= q->n_bd; | |
2779 | ||
2780 | if (s <= 0) | |
2781 | s += q->n_win; | |
2782 | /* keep some reserve to not confuse empty and full situations */ | |
2783 | s -= 2; | |
2784 | if (s < 0) | |
2785 | s = 0; | |
2786 | return s; | |
2787 | } | |
e7392364 | 2788 | |
0cdc2136 SG |
2789 | EXPORT_SYMBOL(il_queue_space); |
2790 | ||
2791 | ||
2792 | /** | |
2793 | * il_queue_init - Initialize queue's high/low-water and read/write idxes | |
2794 | */ | |
e7392364 SG |
2795 | static int |
2796 | il_queue_init(struct il_priv *il, struct il_queue *q, int count, int slots_num, | |
2797 | u32 id) | |
0cdc2136 SG |
2798 | { |
2799 | q->n_bd = count; | |
2800 | q->n_win = slots_num; | |
2801 | q->id = id; | |
2802 | ||
2803 | /* count must be power-of-two size, otherwise il_queue_inc_wrap | |
2804 | * and il_queue_dec_wrap are broken. */ | |
2805 | BUG_ON(!is_power_of_2(count)); | |
2806 | ||
2807 | /* slots_num must be power-of-two size, otherwise | |
2808 | * il_get_cmd_idx is broken. */ | |
2809 | BUG_ON(!is_power_of_2(slots_num)); | |
2810 | ||
2811 | q->low_mark = q->n_win / 4; | |
2812 | if (q->low_mark < 4) | |
2813 | q->low_mark = 4; | |
2814 | ||
2815 | q->high_mark = q->n_win / 8; | |
2816 | if (q->high_mark < 2) | |
2817 | q->high_mark = 2; | |
2818 | ||
2819 | q->write_ptr = q->read_ptr = 0; | |
2820 | ||
2821 | return 0; | |
2822 | } | |
2823 | ||
2824 | /** | |
2825 | * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue | |
2826 | */ | |
e7392364 SG |
2827 | static int |
2828 | il_tx_queue_alloc(struct il_priv *il, struct il_tx_queue *txq, u32 id) | |
0cdc2136 SG |
2829 | { |
2830 | struct device *dev = &il->pci_dev->dev; | |
2831 | size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX; | |
2832 | ||
2833 | /* Driver ilate data, only for Tx (not command) queues, | |
2834 | * not shared with device. */ | |
2835 | if (id != il->cmd_queue) { | |
e7392364 SG |
2836 | txq->txb = |
2837 | kzalloc(sizeof(txq->txb[0]) * TFD_QUEUE_SIZE_MAX, | |
2838 | GFP_KERNEL); | |
0cdc2136 SG |
2839 | if (!txq->txb) { |
2840 | IL_ERR("kmalloc for auxiliary BD " | |
e7392364 | 2841 | "structures failed\n"); |
0cdc2136 SG |
2842 | goto error; |
2843 | } | |
2844 | } else { | |
2845 | txq->txb = NULL; | |
2846 | } | |
2847 | ||
2848 | /* Circular buffer of transmit frame descriptors (TFDs), | |
2849 | * shared with device */ | |
e7392364 SG |
2850 | txq->tfds = |
2851 | dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, GFP_KERNEL); | |
0cdc2136 SG |
2852 | if (!txq->tfds) { |
2853 | IL_ERR("pci_alloc_consistent(%zd) failed\n", tfd_sz); | |
2854 | goto error; | |
2855 | } | |
2856 | txq->q.id = id; | |
2857 | ||
2858 | return 0; | |
2859 | ||
e7392364 | 2860 | error: |
0cdc2136 SG |
2861 | kfree(txq->txb); |
2862 | txq->txb = NULL; | |
2863 | ||
2864 | return -ENOMEM; | |
2865 | } | |
2866 | ||
2867 | /** | |
2868 | * il_tx_queue_init - Allocate and initialize one tx/cmd queue | |
2869 | */ | |
e7392364 SG |
2870 | int |
2871 | il_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq, int slots_num, | |
2872 | u32 txq_id) | |
0cdc2136 SG |
2873 | { |
2874 | int i, len; | |
2875 | int ret; | |
2876 | int actual_slots = slots_num; | |
2877 | ||
2878 | /* | |
2879 | * Alloc buffer array for commands (Tx or other types of commands). | |
2880 | * For the command queue (#4/#9), allocate command space + one big | |
2881 | * command for scan, since scan command is very huge; the system will | |
2882 | * not have two scans at the same time, so only one is needed. | |
2883 | * For normal Tx queues (all other queues), no super-size command | |
2884 | * space is needed. | |
2885 | */ | |
2886 | if (txq_id == il->cmd_queue) | |
2887 | actual_slots++; | |
2888 | ||
e7392364 SG |
2889 | txq->meta = |
2890 | kzalloc(sizeof(struct il_cmd_meta) * actual_slots, GFP_KERNEL); | |
2891 | txq->cmd = | |
2892 | kzalloc(sizeof(struct il_device_cmd *) * actual_slots, GFP_KERNEL); | |
0cdc2136 SG |
2893 | |
2894 | if (!txq->meta || !txq->cmd) | |
2895 | goto out_free_arrays; | |
2896 | ||
2897 | len = sizeof(struct il_device_cmd); | |
2898 | for (i = 0; i < actual_slots; i++) { | |
2899 | /* only happens for cmd queue */ | |
2900 | if (i == slots_num) | |
2901 | len = IL_MAX_CMD_SIZE; | |
2902 | ||
2903 | txq->cmd[i] = kmalloc(len, GFP_KERNEL); | |
2904 | if (!txq->cmd[i]) | |
2905 | goto err; | |
2906 | } | |
2907 | ||
2908 | /* Alloc driver data array and TFD circular buffer */ | |
2909 | ret = il_tx_queue_alloc(il, txq, txq_id); | |
2910 | if (ret) | |
2911 | goto err; | |
2912 | ||
2913 | txq->need_update = 0; | |
2914 | ||
2915 | /* | |
2916 | * For the default queues 0-3, set up the swq_id | |
2917 | * already -- all others need to get one later | |
2918 | * (if they need one at all). | |
2919 | */ | |
2920 | if (txq_id < 4) | |
2921 | il_set_swq_id(txq, txq_id, txq_id); | |
2922 | ||
2923 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
2924 | * il_queue_inc_wrap and il_queue_dec_wrap are broken. */ | |
2925 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
2926 | ||
2927 | /* Initialize queue's high/low-water marks, and head/tail idxes */ | |
e7392364 | 2928 | il_queue_init(il, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
0cdc2136 SG |
2929 | |
2930 | /* Tell device where to find queue */ | |
2931 | il->cfg->ops->lib->txq_init(il, txq); | |
2932 | ||
2933 | return 0; | |
2934 | err: | |
2935 | for (i = 0; i < actual_slots; i++) | |
2936 | kfree(txq->cmd[i]); | |
2937 | out_free_arrays: | |
2938 | kfree(txq->meta); | |
2939 | kfree(txq->cmd); | |
2940 | ||
2941 | return -ENOMEM; | |
2942 | } | |
e7392364 | 2943 | |
0cdc2136 SG |
2944 | EXPORT_SYMBOL(il_tx_queue_init); |
2945 | ||
e7392364 SG |
2946 | void |
2947 | il_tx_queue_reset(struct il_priv *il, struct il_tx_queue *txq, int slots_num, | |
2948 | u32 txq_id) | |
0cdc2136 SG |
2949 | { |
2950 | int actual_slots = slots_num; | |
2951 | ||
2952 | if (txq_id == il->cmd_queue) | |
2953 | actual_slots++; | |
2954 | ||
2955 | memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots); | |
2956 | ||
2957 | txq->need_update = 0; | |
2958 | ||
2959 | /* Initialize queue's high/low-water marks, and head/tail idxes */ | |
e7392364 | 2960 | il_queue_init(il, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id); |
0cdc2136 SG |
2961 | |
2962 | /* Tell device where to find queue */ | |
2963 | il->cfg->ops->lib->txq_init(il, txq); | |
2964 | } | |
e7392364 | 2965 | |
0cdc2136 SG |
2966 | EXPORT_SYMBOL(il_tx_queue_reset); |
2967 | ||
2968 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ | |
2969 | ||
2970 | /** | |
2971 | * il_enqueue_hcmd - enqueue a uCode command | |
2972 | * @il: device ilate data point | |
2973 | * @cmd: a point to the ucode command structure | |
2974 | * | |
2975 | * The function returns < 0 values to indicate the operation is | |
2976 | * failed. On success, it turns the idx (> 0) of command in the | |
2977 | * command queue. | |
2978 | */ | |
e7392364 SG |
2979 | int |
2980 | il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd) | |
0cdc2136 SG |
2981 | { |
2982 | struct il_tx_queue *txq = &il->txq[il->cmd_queue]; | |
2983 | struct il_queue *q = &txq->q; | |
2984 | struct il_device_cmd *out_cmd; | |
2985 | struct il_cmd_meta *out_meta; | |
2986 | dma_addr_t phys_addr; | |
2987 | unsigned long flags; | |
2988 | int len; | |
2989 | u32 idx; | |
2990 | u16 fix_size; | |
2991 | ||
2992 | cmd->len = il->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len); | |
e7392364 | 2993 | fix_size = (u16) (cmd->len + sizeof(out_cmd->hdr)); |
0cdc2136 SG |
2994 | |
2995 | /* If any of the command structures end up being larger than | |
2996 | * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then | |
2997 | * we will need to increase the size of the TFD entries | |
2998 | * Also, check to see if command buffer should not exceed the size | |
2999 | * of device_cmd and max_cmd_size. */ | |
3000 | BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) && | |
3001 | !(cmd->flags & CMD_SIZE_HUGE)); | |
3002 | BUG_ON(fix_size > IL_MAX_CMD_SIZE); | |
3003 | ||
3004 | if (il_is_rfkill(il) || il_is_ctkill(il)) { | |
3005 | IL_WARN("Not sending command - %s KILL\n", | |
e7392364 | 3006 | il_is_rfkill(il) ? "RF" : "CT"); |
0cdc2136 SG |
3007 | return -EIO; |
3008 | } | |
3009 | ||
3010 | spin_lock_irqsave(&il->hcmd_lock, flags); | |
3011 | ||
3012 | if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { | |
3013 | spin_unlock_irqrestore(&il->hcmd_lock, flags); | |
3014 | ||
3015 | IL_ERR("Restarting adapter due to command queue full\n"); | |
3016 | queue_work(il->workqueue, &il->restart); | |
3017 | return -ENOSPC; | |
3018 | } | |
3019 | ||
3020 | idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE); | |
3021 | out_cmd = txq->cmd[idx]; | |
3022 | out_meta = &txq->meta[idx]; | |
3023 | ||
3024 | if (WARN_ON(out_meta->flags & CMD_MAPPED)) { | |
3025 | spin_unlock_irqrestore(&il->hcmd_lock, flags); | |
3026 | return -ENOSPC; | |
3027 | } | |
3028 | ||
3029 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ | |
3030 | out_meta->flags = cmd->flags | CMD_MAPPED; | |
3031 | if (cmd->flags & CMD_WANT_SKB) | |
3032 | out_meta->source = cmd; | |
3033 | if (cmd->flags & CMD_ASYNC) | |
3034 | out_meta->callback = cmd->callback; | |
3035 | ||
3036 | out_cmd->hdr.cmd = cmd->id; | |
3037 | memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len); | |
3038 | ||
3039 | /* At this point, the out_cmd now has all of the incoming cmd | |
3040 | * information */ | |
3041 | ||
3042 | out_cmd->hdr.flags = 0; | |
e7392364 SG |
3043 | out_cmd->hdr.sequence = |
3044 | cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) | IDX_TO_SEQ(q->write_ptr)); | |
0cdc2136 SG |
3045 | if (cmd->flags & CMD_SIZE_HUGE) |
3046 | out_cmd->hdr.sequence |= SEQ_HUGE_FRAME; | |
3047 | len = sizeof(struct il_device_cmd); | |
3048 | if (idx == TFD_CMD_SLOTS) | |
3049 | len = IL_MAX_CMD_SIZE; | |
3050 | ||
3051 | #ifdef CONFIG_IWLEGACY_DEBUG | |
3052 | switch (out_cmd->hdr.cmd) { | |
3053 | case C_TX_LINK_QUALITY_CMD: | |
3054 | case C_SENSITIVITY: | |
e7392364 SG |
3055 | D_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, " |
3056 | "%d bytes at %d[%d]:%d\n", | |
3057 | il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd, | |
3058 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, | |
3059 | q->write_ptr, idx, il->cmd_queue); | |
0cdc2136 SG |
3060 | break; |
3061 | default: | |
3062 | D_HC("Sending command %s (#%x), seq: 0x%04X, " | |
e7392364 SG |
3063 | "%d bytes at %d[%d]:%d\n", |
3064 | il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd, | |
3065 | le16_to_cpu(out_cmd->hdr.sequence), fix_size, q->write_ptr, | |
3066 | idx, il->cmd_queue); | |
0cdc2136 SG |
3067 | } |
3068 | #endif | |
3069 | txq->need_update = 1; | |
3070 | ||
3071 | if (il->cfg->ops->lib->txq_update_byte_cnt_tbl) | |
3072 | /* Set up entry in queue's byte count circular buffer */ | |
3073 | il->cfg->ops->lib->txq_update_byte_cnt_tbl(il, txq, 0); | |
3074 | ||
e7392364 SG |
3075 | phys_addr = |
3076 | pci_map_single(il->pci_dev, &out_cmd->hdr, fix_size, | |
3077 | PCI_DMA_BIDIRECTIONAL); | |
0cdc2136 SG |
3078 | dma_unmap_addr_set(out_meta, mapping, phys_addr); |
3079 | dma_unmap_len_set(out_meta, len, fix_size); | |
3080 | ||
e7392364 SG |
3081 | il->cfg->ops->lib->txq_attach_buf_to_tfd(il, txq, phys_addr, fix_size, |
3082 | 1, U32_PAD(cmd->len)); | |
0cdc2136 SG |
3083 | |
3084 | /* Increment and update queue's write idx */ | |
3085 | q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd); | |
3086 | il_txq_update_write_ptr(il, txq); | |
3087 | ||
3088 | spin_unlock_irqrestore(&il->hcmd_lock, flags); | |
3089 | return idx; | |
3090 | } | |
3091 | ||
3092 | /** | |
3093 | * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd | |
3094 | * | |
3095 | * When FW advances 'R' idx, all entries between old and new 'R' idx | |
3096 | * need to be reclaimed. As result, some free space forms. If there is | |
3097 | * enough free space (> low mark), wake the stack that feeds us. | |
3098 | */ | |
e7392364 SG |
3099 | static void |
3100 | il_hcmd_queue_reclaim(struct il_priv *il, int txq_id, int idx, int cmd_idx) | |
0cdc2136 SG |
3101 | { |
3102 | struct il_tx_queue *txq = &il->txq[txq_id]; | |
3103 | struct il_queue *q = &txq->q; | |
3104 | int nfreed = 0; | |
3105 | ||
3106 | if (idx >= q->n_bd || il_queue_used(q, idx) == 0) { | |
3107 | IL_ERR("Read idx for DMA queue txq id (%d), idx %d, " | |
e7392364 SG |
3108 | "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd, |
3109 | q->write_ptr, q->read_ptr); | |
0cdc2136 SG |
3110 | return; |
3111 | } | |
3112 | ||
3113 | for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; | |
3114 | q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
3115 | ||
3116 | if (nfreed++ > 0) { | |
3117 | IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx, | |
e7392364 | 3118 | q->write_ptr, q->read_ptr); |
0cdc2136 SG |
3119 | queue_work(il->workqueue, &il->restart); |
3120 | } | |
3121 | ||
3122 | } | |
3123 | } | |
3124 | ||
3125 | /** | |
3126 | * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them | |
3127 | * @rxb: Rx buffer to reclaim | |
3128 | * | |
3129 | * If an Rx buffer has an async callback associated with it the callback | |
3130 | * will be executed. The attached skb (if present) will only be freed | |
3131 | * if the callback returns 1 | |
3132 | */ | |
3133 | void | |
3134 | il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb) | |
3135 | { | |
3136 | struct il_rx_pkt *pkt = rxb_addr(rxb); | |
3137 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | |
3138 | int txq_id = SEQ_TO_QUEUE(sequence); | |
3139 | int idx = SEQ_TO_IDX(sequence); | |
3140 | int cmd_idx; | |
3141 | bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME); | |
3142 | struct il_device_cmd *cmd; | |
3143 | struct il_cmd_meta *meta; | |
3144 | struct il_tx_queue *txq = &il->txq[il->cmd_queue]; | |
3145 | unsigned long flags; | |
3146 | ||
3147 | /* If a Tx command is being handled and it isn't in the actual | |
3148 | * command queue then there a command routing bug has been introduced | |
3149 | * in the queue management code. */ | |
e7392364 SG |
3150 | if (WARN |
3151 | (txq_id != il->cmd_queue, | |
3152 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", | |
3153 | txq_id, il->cmd_queue, sequence, il->txq[il->cmd_queue].q.read_ptr, | |
3154 | il->txq[il->cmd_queue].q.write_ptr)) { | |
0cdc2136 SG |
3155 | il_print_hex_error(il, pkt, 32); |
3156 | return; | |
3157 | } | |
3158 | ||
3159 | cmd_idx = il_get_cmd_idx(&txq->q, idx, huge); | |
3160 | cmd = txq->cmd[cmd_idx]; | |
3161 | meta = &txq->meta[cmd_idx]; | |
3162 | ||
3163 | txq->time_stamp = jiffies; | |
3164 | ||
e7392364 SG |
3165 | pci_unmap_single(il->pci_dev, dma_unmap_addr(meta, mapping), |
3166 | dma_unmap_len(meta, len), PCI_DMA_BIDIRECTIONAL); | |
0cdc2136 SG |
3167 | |
3168 | /* Input error checking is done when commands are added to queue. */ | |
3169 | if (meta->flags & CMD_WANT_SKB) { | |
3170 | meta->source->reply_page = (unsigned long)rxb_addr(rxb); | |
3171 | rxb->page = NULL; | |
3172 | } else if (meta->callback) | |
3173 | meta->callback(il, cmd, pkt); | |
3174 | ||
3175 | spin_lock_irqsave(&il->hcmd_lock, flags); | |
3176 | ||
3177 | il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx); | |
3178 | ||
3179 | if (!(meta->flags & CMD_ASYNC)) { | |
3180 | clear_bit(S_HCMD_ACTIVE, &il->status); | |
3181 | D_INFO("Clearing HCMD_ACTIVE for command %s\n", | |
e7392364 | 3182 | il_get_cmd_string(cmd->hdr.cmd)); |
0cdc2136 SG |
3183 | wake_up(&il->wait_command_queue); |
3184 | } | |
3185 | ||
3186 | /* Mark as unmapped */ | |
3187 | meta->flags = 0; | |
3188 | ||
3189 | spin_unlock_irqrestore(&il->hcmd_lock, flags); | |
3190 | } | |
3191 | EXPORT_SYMBOL(il_tx_cmd_complete); | |
be663ab6 WYG |
3192 | |
3193 | MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965"); | |
3194 | MODULE_VERSION(IWLWIFI_VERSION); | |
3195 | MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); | |
3196 | MODULE_LICENSE("GPL"); | |
3197 | ||
3198 | /* | |
3199 | * set bt_coex_active to true, uCode will do kill/defer | |
3200 | * every time the priority line is asserted (BT is sending signals on the | |
3201 | * priority line in the PCIx). | |
3202 | * set bt_coex_active to false, uCode will ignore the BT activity and | |
3203 | * perform the normal operation | |
3204 | * | |
3205 | * User might experience transmit issue on some platform due to WiFi/BT | |
3206 | * co-exist problem. The possible behaviors are: | |
3207 | * Able to scan and finding all the available AP | |
3208 | * Not able to associate with any AP | |
3209 | * On those platforms, WiFi communication can be restored by set | |
3210 | * "bt_coex_active" module parameter to "false" | |
3211 | * | |
3212 | * default: bt_coex_active = true (BT_COEX_ENABLE) | |
3213 | */ | |
ef33417d | 3214 | static bool bt_coex_active = true; |
be663ab6 WYG |
3215 | module_param(bt_coex_active, bool, S_IRUGO); |
3216 | MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist"); | |
3217 | ||
d2ddf621 SG |
3218 | u32 il_debug_level; |
3219 | EXPORT_SYMBOL(il_debug_level); | |
be663ab6 | 3220 | |
d2ddf621 | 3221 | const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; |
be663ab6 | 3222 | |
e7392364 | 3223 | EXPORT_SYMBOL(il_bcast_addr); |
be663ab6 | 3224 | |
46bc8d4b | 3225 | /* This function both allocates and initializes hw and il. */ |
e7392364 SG |
3226 | struct ieee80211_hw * |
3227 | il_alloc_all(struct il_cfg *cfg) | |
be663ab6 | 3228 | { |
46bc8d4b | 3229 | struct il_priv *il; |
be663ab6 | 3230 | /* mac80211 allocates memory for this device instance, including |
46bc8d4b | 3231 | * space for this driver's ilate structure */ |
be663ab6 WYG |
3232 | struct ieee80211_hw *hw; |
3233 | ||
e2ebc833 | 3234 | hw = ieee80211_alloc_hw(sizeof(struct il_priv), |
be663ab6 WYG |
3235 | cfg->ops->ieee80211_ops); |
3236 | if (hw == NULL) { | |
e7392364 | 3237 | pr_err("%s: Can not allocate network device\n", cfg->name); |
be663ab6 WYG |
3238 | goto out; |
3239 | } | |
3240 | ||
46bc8d4b SG |
3241 | il = hw->priv; |
3242 | il->hw = hw; | |
be663ab6 WYG |
3243 | |
3244 | out: | |
3245 | return hw; | |
3246 | } | |
e7392364 | 3247 | |
e2ebc833 | 3248 | EXPORT_SYMBOL(il_alloc_all); |
be663ab6 | 3249 | |
e7392364 SG |
3250 | #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */ |
3251 | #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */ | |
3252 | static void | |
3253 | il_init_ht_hw_capab(const struct il_priv *il, | |
3254 | struct ieee80211_sta_ht_cap *ht_info, | |
3255 | enum ieee80211_band band) | |
be663ab6 WYG |
3256 | { |
3257 | u16 max_bit_rate = 0; | |
46bc8d4b SG |
3258 | u8 rx_chains_num = il->hw_params.rx_chains_num; |
3259 | u8 tx_chains_num = il->hw_params.tx_chains_num; | |
be663ab6 WYG |
3260 | |
3261 | ht_info->cap = 0; | |
3262 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
3263 | ||
3264 | ht_info->ht_supported = true; | |
3265 | ||
3266 | ht_info->cap |= IEEE80211_HT_CAP_SGI_20; | |
3267 | max_bit_rate = MAX_BIT_RATE_20_MHZ; | |
46bc8d4b | 3268 | if (il->hw_params.ht40_channel & BIT(band)) { |
be663ab6 WYG |
3269 | ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; |
3270 | ht_info->cap |= IEEE80211_HT_CAP_SGI_40; | |
3271 | ht_info->mcs.rx_mask[4] = 0x01; | |
3272 | max_bit_rate = MAX_BIT_RATE_40_MHZ; | |
3273 | } | |
3274 | ||
46bc8d4b | 3275 | if (il->cfg->mod_params->amsdu_size_8K) |
be663ab6 WYG |
3276 | ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU; |
3277 | ||
3278 | ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF; | |
3279 | ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF; | |
3280 | ||
3281 | ht_info->mcs.rx_mask[0] = 0xFF; | |
3282 | if (rx_chains_num >= 2) | |
3283 | ht_info->mcs.rx_mask[1] = 0xFF; | |
3284 | if (rx_chains_num >= 3) | |
3285 | ht_info->mcs.rx_mask[2] = 0xFF; | |
3286 | ||
3287 | /* Highest supported Rx data rate */ | |
3288 | max_bit_rate *= rx_chains_num; | |
3289 | WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK); | |
3290 | ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate); | |
3291 | ||
3292 | /* Tx MCS capabilities */ | |
3293 | ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; | |
3294 | if (tx_chains_num != rx_chains_num) { | |
3295 | ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; | |
e7392364 SG |
3296 | ht_info->mcs.tx_params |= |
3297 | ((tx_chains_num - | |
3298 | 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); | |
be663ab6 WYG |
3299 | } |
3300 | } | |
3301 | ||
3302 | /** | |
e2ebc833 | 3303 | * il_init_geos - Initialize mac80211's geo/channel info based from eeprom |
be663ab6 | 3304 | */ |
e7392364 SG |
3305 | int |
3306 | il_init_geos(struct il_priv *il) | |
be663ab6 | 3307 | { |
e2ebc833 | 3308 | struct il_channel_info *ch; |
be663ab6 WYG |
3309 | struct ieee80211_supported_band *sband; |
3310 | struct ieee80211_channel *channels; | |
3311 | struct ieee80211_channel *geo_ch; | |
3312 | struct ieee80211_rate *rates; | |
3313 | int i = 0; | |
332704a5 | 3314 | s8 max_tx_power = 0; |
be663ab6 | 3315 | |
46bc8d4b SG |
3316 | if (il->bands[IEEE80211_BAND_2GHZ].n_bitrates || |
3317 | il->bands[IEEE80211_BAND_5GHZ].n_bitrates) { | |
58de00a4 | 3318 | D_INFO("Geography modes already initialized.\n"); |
a6766ccd | 3319 | set_bit(S_GEO_CONFIGURED, &il->status); |
be663ab6 WYG |
3320 | return 0; |
3321 | } | |
3322 | ||
e7392364 SG |
3323 | channels = |
3324 | kzalloc(sizeof(struct ieee80211_channel) * il->channel_count, | |
3325 | GFP_KERNEL); | |
be663ab6 WYG |
3326 | if (!channels) |
3327 | return -ENOMEM; | |
3328 | ||
e7392364 SG |
3329 | rates = |
3330 | kzalloc((sizeof(struct ieee80211_rate) * RATE_COUNT_LEGACY), | |
3331 | GFP_KERNEL); | |
be663ab6 WYG |
3332 | if (!rates) { |
3333 | kfree(channels); | |
3334 | return -ENOMEM; | |
3335 | } | |
3336 | ||
3337 | /* 5.2GHz channels start after the 2.4GHz channels */ | |
46bc8d4b | 3338 | sband = &il->bands[IEEE80211_BAND_5GHZ]; |
d2ddf621 | 3339 | sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)]; |
be663ab6 | 3340 | /* just OFDM */ |
e2ebc833 | 3341 | sband->bitrates = &rates[IL_FIRST_OFDM_RATE]; |
2eb05816 | 3342 | sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE; |
be663ab6 | 3343 | |
46bc8d4b | 3344 | if (il->cfg->sku & IL_SKU_N) |
e7392364 | 3345 | il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_5GHZ); |
be663ab6 | 3346 | |
46bc8d4b | 3347 | sband = &il->bands[IEEE80211_BAND_2GHZ]; |
be663ab6 WYG |
3348 | sband->channels = channels; |
3349 | /* OFDM & CCK */ | |
3350 | sband->bitrates = rates; | |
2eb05816 | 3351 | sband->n_bitrates = RATE_COUNT_LEGACY; |
be663ab6 | 3352 | |
46bc8d4b | 3353 | if (il->cfg->sku & IL_SKU_N) |
e7392364 | 3354 | il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_2GHZ); |
be663ab6 | 3355 | |
46bc8d4b SG |
3356 | il->ieee_channels = channels; |
3357 | il->ieee_rates = rates; | |
be663ab6 | 3358 | |
e7392364 | 3359 | for (i = 0; i < il->channel_count; i++) { |
46bc8d4b | 3360 | ch = &il->channel_info[i]; |
be663ab6 | 3361 | |
e2ebc833 | 3362 | if (!il_is_channel_valid(ch)) |
be663ab6 WYG |
3363 | continue; |
3364 | ||
46bc8d4b | 3365 | sband = &il->bands[ch->band]; |
be663ab6 WYG |
3366 | |
3367 | geo_ch = &sband->channels[sband->n_channels++]; | |
3368 | ||
3369 | geo_ch->center_freq = | |
e7392364 | 3370 | ieee80211_channel_to_frequency(ch->channel, ch->band); |
be663ab6 WYG |
3371 | geo_ch->max_power = ch->max_power_avg; |
3372 | geo_ch->max_antenna_gain = 0xff; | |
3373 | geo_ch->hw_value = ch->channel; | |
3374 | ||
e2ebc833 | 3375 | if (il_is_channel_valid(ch)) { |
be663ab6 WYG |
3376 | if (!(ch->flags & EEPROM_CHANNEL_IBSS)) |
3377 | geo_ch->flags |= IEEE80211_CHAN_NO_IBSS; | |
3378 | ||
3379 | if (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) | |
3380 | geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
3381 | ||
3382 | if (ch->flags & EEPROM_CHANNEL_RADAR) | |
3383 | geo_ch->flags |= IEEE80211_CHAN_RADAR; | |
3384 | ||
3385 | geo_ch->flags |= ch->ht40_extension_channel; | |
3386 | ||
332704a5 SG |
3387 | if (ch->max_power_avg > max_tx_power) |
3388 | max_tx_power = ch->max_power_avg; | |
be663ab6 WYG |
3389 | } else { |
3390 | geo_ch->flags |= IEEE80211_CHAN_DISABLED; | |
3391 | } | |
3392 | ||
e7392364 SG |
3393 | D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", ch->channel, |
3394 | geo_ch->center_freq, | |
3395 | il_is_channel_a_band(ch) ? "5.2" : "2.4", | |
3396 | geo_ch-> | |
3397 | flags & IEEE80211_CHAN_DISABLED ? "restricted" : "valid", | |
3398 | geo_ch->flags); | |
be663ab6 WYG |
3399 | } |
3400 | ||
46bc8d4b SG |
3401 | il->tx_power_device_lmt = max_tx_power; |
3402 | il->tx_power_user_lmt = max_tx_power; | |
3403 | il->tx_power_next = max_tx_power; | |
332704a5 | 3404 | |
232913b5 SG |
3405 | if (il->bands[IEEE80211_BAND_5GHZ].n_channels == 0 && |
3406 | (il->cfg->sku & IL_SKU_A)) { | |
9406f797 | 3407 | IL_INFO("Incorrectly detected BG card as ABG. " |
be663ab6 | 3408 | "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n", |
e7392364 | 3409 | il->pci_dev->device, il->pci_dev->subsystem_device); |
46bc8d4b | 3410 | il->cfg->sku &= ~IL_SKU_A; |
be663ab6 WYG |
3411 | } |
3412 | ||
9406f797 | 3413 | IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n", |
e7392364 SG |
3414 | il->bands[IEEE80211_BAND_2GHZ].n_channels, |
3415 | il->bands[IEEE80211_BAND_5GHZ].n_channels); | |
be663ab6 | 3416 | |
a6766ccd | 3417 | set_bit(S_GEO_CONFIGURED, &il->status); |
be663ab6 WYG |
3418 | |
3419 | return 0; | |
3420 | } | |
e7392364 | 3421 | |
e2ebc833 | 3422 | EXPORT_SYMBOL(il_init_geos); |
be663ab6 WYG |
3423 | |
3424 | /* | |
e2ebc833 | 3425 | * il_free_geos - undo allocations in il_init_geos |
be663ab6 | 3426 | */ |
e7392364 SG |
3427 | void |
3428 | il_free_geos(struct il_priv *il) | |
be663ab6 | 3429 | { |
46bc8d4b SG |
3430 | kfree(il->ieee_channels); |
3431 | kfree(il->ieee_rates); | |
a6766ccd | 3432 | clear_bit(S_GEO_CONFIGURED, &il->status); |
be663ab6 | 3433 | } |
e7392364 | 3434 | |
e2ebc833 | 3435 | EXPORT_SYMBOL(il_free_geos); |
be663ab6 | 3436 | |
e7392364 SG |
3437 | static bool |
3438 | il_is_channel_extension(struct il_priv *il, enum ieee80211_band band, | |
3439 | u16 channel, u8 extension_chan_offset) | |
be663ab6 | 3440 | { |
e2ebc833 | 3441 | const struct il_channel_info *ch_info; |
be663ab6 | 3442 | |
46bc8d4b | 3443 | ch_info = il_get_channel_info(il, band, channel); |
e2ebc833 | 3444 | if (!il_is_channel_valid(ch_info)) |
be663ab6 WYG |
3445 | return false; |
3446 | ||
3447 | if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) | |
e7392364 SG |
3448 | return !(ch_info-> |
3449 | ht40_extension_channel & IEEE80211_CHAN_NO_HT40PLUS); | |
be663ab6 | 3450 | else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) |
e7392364 SG |
3451 | return !(ch_info-> |
3452 | ht40_extension_channel & IEEE80211_CHAN_NO_HT40MINUS); | |
be663ab6 WYG |
3453 | |
3454 | return false; | |
3455 | } | |
3456 | ||
e7392364 SG |
3457 | bool |
3458 | il_is_ht40_tx_allowed(struct il_priv * il, struct il_rxon_context * ctx, | |
3459 | struct ieee80211_sta_ht_cap * ht_cap) | |
be663ab6 WYG |
3460 | { |
3461 | if (!ctx->ht.enabled || !ctx->ht.is_40mhz) | |
3462 | return false; | |
3463 | ||
3464 | /* | |
3465 | * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40 | |
3466 | * the bit will not set if it is pure 40MHz case | |
3467 | */ | |
3468 | if (ht_cap && !ht_cap->ht_supported) | |
3469 | return false; | |
3470 | ||
d3175167 | 3471 | #ifdef CONFIG_IWLEGACY_DEBUGFS |
46bc8d4b | 3472 | if (il->disable_ht40) |
be663ab6 WYG |
3473 | return false; |
3474 | #endif | |
3475 | ||
46bc8d4b | 3476 | return il_is_channel_extension(il, il->band, |
e7392364 SG |
3477 | le16_to_cpu(ctx->staging.channel), |
3478 | ctx->ht.extension_chan_offset); | |
be663ab6 | 3479 | } |
e7392364 | 3480 | |
e2ebc833 | 3481 | EXPORT_SYMBOL(il_is_ht40_tx_allowed); |
be663ab6 | 3482 | |
e7392364 SG |
3483 | static u16 |
3484 | il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val) | |
be663ab6 WYG |
3485 | { |
3486 | u16 new_val; | |
3487 | u16 beacon_factor; | |
3488 | ||
3489 | /* | |
3490 | * If mac80211 hasn't given us a beacon interval, program | |
3491 | * the default into the device. | |
3492 | */ | |
3493 | if (!beacon_val) | |
3494 | return DEFAULT_BEACON_INTERVAL; | |
3495 | ||
3496 | /* | |
3497 | * If the beacon interval we obtained from the peer | |
3498 | * is too large, we'll have to wake up more often | |
3499 | * (and in IBSS case, we'll beacon too much) | |
3500 | * | |
3501 | * For example, if max_beacon_val is 4096, and the | |
3502 | * requested beacon interval is 7000, we'll have to | |
3503 | * use 3500 to be able to wake up on the beacons. | |
3504 | * | |
3505 | * This could badly influence beacon detection stats. | |
3506 | */ | |
3507 | ||
3508 | beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val; | |
3509 | new_val = beacon_val / beacon_factor; | |
3510 | ||
3511 | if (!new_val) | |
3512 | new_val = max_beacon_val; | |
3513 | ||
3514 | return new_val; | |
3515 | } | |
3516 | ||
3517 | int | |
46bc8d4b | 3518 | il_send_rxon_timing(struct il_priv *il, struct il_rxon_context *ctx) |
be663ab6 WYG |
3519 | { |
3520 | u64 tsf; | |
3521 | s32 interval_tm, rem; | |
3522 | struct ieee80211_conf *conf = NULL; | |
3523 | u16 beacon_int; | |
3524 | struct ieee80211_vif *vif = ctx->vif; | |
3525 | ||
6278ddab | 3526 | conf = &il->hw->conf; |
be663ab6 | 3527 | |
46bc8d4b | 3528 | lockdep_assert_held(&il->mutex); |
be663ab6 | 3529 | |
e2ebc833 | 3530 | memset(&ctx->timing, 0, sizeof(struct il_rxon_time_cmd)); |
be663ab6 | 3531 | |
46bc8d4b | 3532 | ctx->timing.timestamp = cpu_to_le64(il->timestamp); |
be663ab6 WYG |
3533 | ctx->timing.listen_interval = cpu_to_le16(conf->listen_interval); |
3534 | ||
3535 | beacon_int = vif ? vif->bss_conf.beacon_int : 0; | |
3536 | ||
3537 | /* | |
6ce1dc45 | 3538 | * TODO: For IBSS we need to get atim_win from mac80211, |
e7392364 | 3539 | * for now just always use 0 |
be663ab6 | 3540 | */ |
6ce1dc45 | 3541 | ctx->timing.atim_win = 0; |
be663ab6 | 3542 | |
e7392364 SG |
3543 | beacon_int = |
3544 | il_adjust_beacon_interval(beacon_int, | |
3545 | il->hw_params.max_beacon_itrvl * | |
3546 | TIME_UNIT); | |
be663ab6 WYG |
3547 | ctx->timing.beacon_interval = cpu_to_le16(beacon_int); |
3548 | ||
e7392364 | 3549 | tsf = il->timestamp; /* tsf is modifed by do_div: copy it */ |
be663ab6 WYG |
3550 | interval_tm = beacon_int * TIME_UNIT; |
3551 | rem = do_div(tsf, interval_tm); | |
3552 | ctx->timing.beacon_init_val = cpu_to_le32(interval_tm - rem); | |
3553 | ||
e7392364 | 3554 | ctx->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1; |
be663ab6 | 3555 | |
e7392364 SG |
3556 | D_ASSOC("beacon interval %d beacon timer %d beacon tim %d\n", |
3557 | le16_to_cpu(ctx->timing.beacon_interval), | |
3558 | le32_to_cpu(ctx->timing.beacon_init_val), | |
3559 | le16_to_cpu(ctx->timing.atim_win)); | |
be663ab6 | 3560 | |
e7392364 SG |
3561 | return il_send_cmd_pdu(il, ctx->rxon_timing_cmd, sizeof(ctx->timing), |
3562 | &ctx->timing); | |
be663ab6 | 3563 | } |
e7392364 | 3564 | |
e2ebc833 | 3565 | EXPORT_SYMBOL(il_send_rxon_timing); |
be663ab6 WYG |
3566 | |
3567 | void | |
e7392364 SG |
3568 | il_set_rxon_hwcrypto(struct il_priv *il, struct il_rxon_context *ctx, |
3569 | int hw_decrypt) | |
be663ab6 | 3570 | { |
e2ebc833 | 3571 | struct il_rxon_cmd *rxon = &ctx->staging; |
be663ab6 WYG |
3572 | |
3573 | if (hw_decrypt) | |
3574 | rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK; | |
3575 | else | |
3576 | rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK; | |
3577 | ||
3578 | } | |
e7392364 | 3579 | |
e2ebc833 | 3580 | EXPORT_SYMBOL(il_set_rxon_hwcrypto); |
be663ab6 WYG |
3581 | |
3582 | /* validate RXON structure is valid */ | |
3583 | int | |
46bc8d4b | 3584 | il_check_rxon_cmd(struct il_priv *il, struct il_rxon_context *ctx) |
be663ab6 | 3585 | { |
e2ebc833 | 3586 | struct il_rxon_cmd *rxon = &ctx->staging; |
be663ab6 WYG |
3587 | bool error = false; |
3588 | ||
3589 | if (rxon->flags & RXON_FLG_BAND_24G_MSK) { | |
3590 | if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) { | |
9406f797 | 3591 | IL_WARN("check 2.4G: wrong narrow\n"); |
be663ab6 WYG |
3592 | error = true; |
3593 | } | |
3594 | if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) { | |
9406f797 | 3595 | IL_WARN("check 2.4G: wrong radar\n"); |
be663ab6 WYG |
3596 | error = true; |
3597 | } | |
3598 | } else { | |
3599 | if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) { | |
9406f797 | 3600 | IL_WARN("check 5.2G: not short slot!\n"); |
be663ab6 WYG |
3601 | error = true; |
3602 | } | |
3603 | if (rxon->flags & RXON_FLG_CCK_MSK) { | |
9406f797 | 3604 | IL_WARN("check 5.2G: CCK!\n"); |
be663ab6 WYG |
3605 | error = true; |
3606 | } | |
3607 | } | |
3608 | if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) { | |
9406f797 | 3609 | IL_WARN("mac/bssid mcast!\n"); |
be663ab6 WYG |
3610 | error = true; |
3611 | } | |
3612 | ||
3613 | /* make sure basic rates 6Mbps and 1Mbps are supported */ | |
2eb05816 SG |
3614 | if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 && |
3615 | (rxon->cck_basic_rates & RATE_1M_MASK) == 0) { | |
9406f797 | 3616 | IL_WARN("neither 1 nor 6 are basic\n"); |
be663ab6 WYG |
3617 | error = true; |
3618 | } | |
3619 | ||
3620 | if (le16_to_cpu(rxon->assoc_id) > 2007) { | |
9406f797 | 3621 | IL_WARN("aid > 2007\n"); |
be663ab6 WYG |
3622 | error = true; |
3623 | } | |
3624 | ||
e7392364 SG |
3625 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) == |
3626 | (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) { | |
9406f797 | 3627 | IL_WARN("CCK and short slot\n"); |
be663ab6 WYG |
3628 | error = true; |
3629 | } | |
3630 | ||
e7392364 SG |
3631 | if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) == |
3632 | (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) { | |
9406f797 | 3633 | IL_WARN("CCK and auto detect"); |
be663ab6 WYG |
3634 | error = true; |
3635 | } | |
3636 | ||
e7392364 SG |
3637 | if ((rxon-> |
3638 | flags & (RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK)) == | |
3639 | RXON_FLG_TGG_PROTECT_MSK) { | |
9406f797 | 3640 | IL_WARN("TGg but no auto-detect\n"); |
be663ab6 WYG |
3641 | error = true; |
3642 | } | |
3643 | ||
3644 | if (error) | |
e7392364 | 3645 | IL_WARN("Tuning to channel %d\n", le16_to_cpu(rxon->channel)); |
be663ab6 WYG |
3646 | |
3647 | if (error) { | |
9406f797 | 3648 | IL_ERR("Invalid RXON\n"); |
be663ab6 WYG |
3649 | return -EINVAL; |
3650 | } | |
3651 | return 0; | |
3652 | } | |
e7392364 | 3653 | |
e2ebc833 | 3654 | EXPORT_SYMBOL(il_check_rxon_cmd); |
be663ab6 WYG |
3655 | |
3656 | /** | |
e2ebc833 | 3657 | * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed |
46bc8d4b | 3658 | * @il: staging_rxon is compared to active_rxon |
be663ab6 WYG |
3659 | * |
3660 | * If the RXON structure is changing enough to require a new tune, | |
3661 | * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that | |
3662 | * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required. | |
3663 | */ | |
e7392364 SG |
3664 | int |
3665 | il_full_rxon_required(struct il_priv *il, struct il_rxon_context *ctx) | |
be663ab6 | 3666 | { |
e2ebc833 SG |
3667 | const struct il_rxon_cmd *staging = &ctx->staging; |
3668 | const struct il_rxon_cmd *active = &ctx->active; | |
be663ab6 WYG |
3669 | |
3670 | #define CHK(cond) \ | |
3671 | if ((cond)) { \ | |
58de00a4 | 3672 | D_INFO("need full RXON - " #cond "\n"); \ |
be663ab6 WYG |
3673 | return 1; \ |
3674 | } | |
3675 | ||
3676 | #define CHK_NEQ(c1, c2) \ | |
3677 | if ((c1) != (c2)) { \ | |
58de00a4 | 3678 | D_INFO("need full RXON - " \ |
be663ab6 WYG |
3679 | #c1 " != " #c2 " - %d != %d\n", \ |
3680 | (c1), (c2)); \ | |
3681 | return 1; \ | |
3682 | } | |
3683 | ||
3684 | /* These items are only settable from the full RXON command */ | |
e2ebc833 | 3685 | CHK(!il_is_associated_ctx(ctx)); |
be663ab6 WYG |
3686 | CHK(compare_ether_addr(staging->bssid_addr, active->bssid_addr)); |
3687 | CHK(compare_ether_addr(staging->node_addr, active->node_addr)); | |
e7392364 SG |
3688 | CHK(compare_ether_addr |
3689 | (staging->wlap_bssid_addr, active->wlap_bssid_addr)); | |
be663ab6 WYG |
3690 | CHK_NEQ(staging->dev_type, active->dev_type); |
3691 | CHK_NEQ(staging->channel, active->channel); | |
3692 | CHK_NEQ(staging->air_propagation, active->air_propagation); | |
3693 | CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates, | |
3694 | active->ofdm_ht_single_stream_basic_rates); | |
3695 | CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates, | |
3696 | active->ofdm_ht_dual_stream_basic_rates); | |
3697 | CHK_NEQ(staging->assoc_id, active->assoc_id); | |
3698 | ||
3699 | /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can | |
3700 | * be updated with the RXON_ASSOC command -- however only some | |
3701 | * flag transitions are allowed using RXON_ASSOC */ | |
3702 | ||
3703 | /* Check if we are not switching bands */ | |
3704 | CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK, | |
3705 | active->flags & RXON_FLG_BAND_24G_MSK); | |
3706 | ||
3707 | /* Check if we are switching association toggle */ | |
3708 | CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK, | |
3709 | active->filter_flags & RXON_FILTER_ASSOC_MSK); | |
3710 | ||
3711 | #undef CHK | |
3712 | #undef CHK_NEQ | |
3713 | ||
3714 | return 0; | |
3715 | } | |
e7392364 | 3716 | |
e2ebc833 | 3717 | EXPORT_SYMBOL(il_full_rxon_required); |
be663ab6 | 3718 | |
e7392364 SG |
3719 | u8 |
3720 | il_get_lowest_plcp(struct il_priv * il, struct il_rxon_context * ctx) | |
be663ab6 WYG |
3721 | { |
3722 | /* | |
3723 | * Assign the lowest rate -- should really get this from | |
3724 | * the beacon skb from mac80211. | |
3725 | */ | |
3726 | if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) | |
2eb05816 | 3727 | return RATE_1M_PLCP; |
be663ab6 | 3728 | else |
2eb05816 | 3729 | return RATE_6M_PLCP; |
be663ab6 | 3730 | } |
e7392364 | 3731 | |
e2ebc833 | 3732 | EXPORT_SYMBOL(il_get_lowest_plcp); |
be663ab6 | 3733 | |
e7392364 SG |
3734 | static void |
3735 | _il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf, | |
3736 | struct il_rxon_context *ctx) | |
be663ab6 | 3737 | { |
e2ebc833 | 3738 | struct il_rxon_cmd *rxon = &ctx->staging; |
be663ab6 WYG |
3739 | |
3740 | if (!ctx->ht.enabled) { | |
e7392364 SG |
3741 | rxon->flags &= |
3742 | ~(RXON_FLG_CHANNEL_MODE_MSK | | |
3743 | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | RXON_FLG_HT40_PROT_MSK | |
3744 | | RXON_FLG_HT_PROT_MSK); | |
be663ab6 WYG |
3745 | return; |
3746 | } | |
3747 | ||
e7392364 SG |
3748 | rxon->flags |= |
3749 | cpu_to_le32(ctx->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS); | |
be663ab6 WYG |
3750 | |
3751 | /* Set up channel bandwidth: | |
3752 | * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */ | |
3753 | /* clear the HT channel mode before set the mode */ | |
e7392364 SG |
3754 | rxon->flags &= |
3755 | ~(RXON_FLG_CHANNEL_MODE_MSK | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
46bc8d4b | 3756 | if (il_is_ht40_tx_allowed(il, ctx, NULL)) { |
be663ab6 | 3757 | /* pure ht40 */ |
e7392364 | 3758 | if (ctx->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) { |
be663ab6 WYG |
3759 | rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40; |
3760 | /* Note: control channel is opposite of extension channel */ | |
3761 | switch (ctx->ht.extension_chan_offset) { | |
3762 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: | |
3763 | rxon->flags &= | |
e7392364 | 3764 | ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; |
be663ab6 WYG |
3765 | break; |
3766 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
e7392364 | 3767 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; |
be663ab6 WYG |
3768 | break; |
3769 | } | |
3770 | } else { | |
3771 | /* Note: control channel is opposite of extension channel */ | |
3772 | switch (ctx->ht.extension_chan_offset) { | |
3773 | case IEEE80211_HT_PARAM_CHA_SEC_ABOVE: | |
3774 | rxon->flags &= | |
e7392364 | 3775 | ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); |
be663ab6 WYG |
3776 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; |
3777 | break; | |
3778 | case IEEE80211_HT_PARAM_CHA_SEC_BELOW: | |
e7392364 | 3779 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; |
be663ab6 WYG |
3780 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED; |
3781 | break; | |
3782 | case IEEE80211_HT_PARAM_CHA_SEC_NONE: | |
3783 | default: | |
3784 | /* channel location only valid if in Mixed mode */ | |
e7392364 | 3785 | IL_ERR("invalid extension channel offset\n"); |
be663ab6 WYG |
3786 | break; |
3787 | } | |
3788 | } | |
3789 | } else { | |
3790 | rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY; | |
3791 | } | |
3792 | ||
46bc8d4b SG |
3793 | if (il->cfg->ops->hcmd->set_rxon_chain) |
3794 | il->cfg->ops->hcmd->set_rxon_chain(il, ctx); | |
be663ab6 | 3795 | |
58de00a4 | 3796 | D_ASSOC("rxon flags 0x%X operation mode :0x%X " |
e7392364 SG |
3797 | "extension channel offset 0x%x\n", le32_to_cpu(rxon->flags), |
3798 | ctx->ht.protection, ctx->ht.extension_chan_offset); | |
be663ab6 WYG |
3799 | } |
3800 | ||
e7392364 SG |
3801 | void |
3802 | il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf) | |
be663ab6 | 3803 | { |
17d6e557 | 3804 | _il_set_rxon_ht(il, ht_conf, &il->ctx); |
be663ab6 | 3805 | } |
e7392364 | 3806 | |
e2ebc833 | 3807 | EXPORT_SYMBOL(il_set_rxon_ht); |
be663ab6 WYG |
3808 | |
3809 | /* Return valid, unused, channel for a passive scan to reset the RF */ | |
e7392364 SG |
3810 | u8 |
3811 | il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band) | |
be663ab6 | 3812 | { |
e2ebc833 | 3813 | const struct il_channel_info *ch_info; |
be663ab6 WYG |
3814 | int i; |
3815 | u8 channel = 0; | |
3816 | u8 min, max; | |
be663ab6 WYG |
3817 | |
3818 | if (band == IEEE80211_BAND_5GHZ) { | |
3819 | min = 14; | |
46bc8d4b | 3820 | max = il->channel_count; |
be663ab6 WYG |
3821 | } else { |
3822 | min = 0; | |
3823 | max = 14; | |
3824 | } | |
3825 | ||
3826 | for (i = min; i < max; i++) { | |
17d6e557 SG |
3827 | channel = il->channel_info[i].channel; |
3828 | if (channel == le16_to_cpu(il->ctx.staging.channel)) | |
be663ab6 WYG |
3829 | continue; |
3830 | ||
46bc8d4b | 3831 | ch_info = il_get_channel_info(il, band, channel); |
e2ebc833 | 3832 | if (il_is_channel_valid(ch_info)) |
be663ab6 WYG |
3833 | break; |
3834 | } | |
3835 | ||
3836 | return channel; | |
3837 | } | |
e7392364 | 3838 | |
e2ebc833 | 3839 | EXPORT_SYMBOL(il_get_single_channel_number); |
be663ab6 WYG |
3840 | |
3841 | /** | |
e2ebc833 | 3842 | * il_set_rxon_channel - Set the band and channel values in staging RXON |
be663ab6 WYG |
3843 | * @ch: requested channel as a pointer to struct ieee80211_channel |
3844 | ||
3845 | * NOTE: Does not commit to the hardware; it sets appropriate bit fields | |
3846 | * in the staging RXON flag structure based on the ch->band | |
3847 | */ | |
3848 | int | |
46bc8d4b | 3849 | il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch, |
e7392364 | 3850 | struct il_rxon_context *ctx) |
be663ab6 WYG |
3851 | { |
3852 | enum ieee80211_band band = ch->band; | |
3853 | u16 channel = ch->hw_value; | |
3854 | ||
232913b5 | 3855 | if (le16_to_cpu(ctx->staging.channel) == channel && il->band == band) |
be663ab6 WYG |
3856 | return 0; |
3857 | ||
3858 | ctx->staging.channel = cpu_to_le16(channel); | |
3859 | if (band == IEEE80211_BAND_5GHZ) | |
3860 | ctx->staging.flags &= ~RXON_FLG_BAND_24G_MSK; | |
3861 | else | |
3862 | ctx->staging.flags |= RXON_FLG_BAND_24G_MSK; | |
3863 | ||
46bc8d4b | 3864 | il->band = band; |
be663ab6 | 3865 | |
58de00a4 | 3866 | D_INFO("Staging channel set to %d [%d]\n", channel, band); |
be663ab6 WYG |
3867 | |
3868 | return 0; | |
3869 | } | |
e7392364 | 3870 | |
e2ebc833 | 3871 | EXPORT_SYMBOL(il_set_rxon_channel); |
be663ab6 | 3872 | |
e7392364 SG |
3873 | void |
3874 | il_set_flags_for_band(struct il_priv *il, struct il_rxon_context *ctx, | |
3875 | enum ieee80211_band band, struct ieee80211_vif *vif) | |
be663ab6 WYG |
3876 | { |
3877 | if (band == IEEE80211_BAND_5GHZ) { | |
3878 | ctx->staging.flags &= | |
e7392364 SG |
3879 | ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK | |
3880 | RXON_FLG_CCK_MSK); | |
be663ab6 WYG |
3881 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; |
3882 | } else { | |
e2ebc833 | 3883 | /* Copied from il_post_associate() */ |
be663ab6 WYG |
3884 | if (vif && vif->bss_conf.use_short_slot) |
3885 | ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK; | |
3886 | else | |
3887 | ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK; | |
3888 | ||
3889 | ctx->staging.flags |= RXON_FLG_BAND_24G_MSK; | |
3890 | ctx->staging.flags |= RXON_FLG_AUTO_DETECT_MSK; | |
3891 | ctx->staging.flags &= ~RXON_FLG_CCK_MSK; | |
3892 | } | |
3893 | } | |
e7392364 | 3894 | |
e2ebc833 | 3895 | EXPORT_SYMBOL(il_set_flags_for_band); |
be663ab6 WYG |
3896 | |
3897 | /* | |
3898 | * initialize rxon structure with default values from eeprom | |
3899 | */ | |
e7392364 SG |
3900 | void |
3901 | il_connection_init_rx_config(struct il_priv *il, struct il_rxon_context *ctx) | |
be663ab6 | 3902 | { |
e2ebc833 | 3903 | const struct il_channel_info *ch_info; |
be663ab6 WYG |
3904 | |
3905 | memset(&ctx->staging, 0, sizeof(ctx->staging)); | |
3906 | ||
3907 | if (!ctx->vif) { | |
3908 | ctx->staging.dev_type = ctx->unused_devtype; | |
3909 | } else | |
e7392364 | 3910 | switch (ctx->vif->type) { |
be663ab6 | 3911 | |
e7392364 SG |
3912 | case NL80211_IFTYPE_STATION: |
3913 | ctx->staging.dev_type = ctx->station_devtype; | |
3914 | ctx->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK; | |
3915 | break; | |
be663ab6 | 3916 | |
e7392364 SG |
3917 | case NL80211_IFTYPE_ADHOC: |
3918 | ctx->staging.dev_type = ctx->ibss_devtype; | |
3919 | ctx->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK; | |
3920 | ctx->staging.filter_flags = | |
3921 | RXON_FILTER_BCON_AWARE_MSK | | |
3922 | RXON_FILTER_ACCEPT_GRP_MSK; | |
3923 | break; | |
be663ab6 | 3924 | |
e7392364 SG |
3925 | default: |
3926 | IL_ERR("Unsupported interface type %d\n", | |
3927 | ctx->vif->type); | |
3928 | break; | |
3929 | } | |
be663ab6 WYG |
3930 | |
3931 | #if 0 | |
3932 | /* TODO: Figure out when short_preamble would be set and cache from | |
3933 | * that */ | |
46bc8d4b | 3934 | if (!hw_to_local(il->hw)->short_preamble) |
be663ab6 WYG |
3935 | ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; |
3936 | else | |
3937 | ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
3938 | #endif | |
3939 | ||
e7392364 SG |
3940 | ch_info = |
3941 | il_get_channel_info(il, il->band, le16_to_cpu(ctx->active.channel)); | |
be663ab6 WYG |
3942 | |
3943 | if (!ch_info) | |
46bc8d4b | 3944 | ch_info = &il->channel_info[0]; |
be663ab6 WYG |
3945 | |
3946 | ctx->staging.channel = cpu_to_le16(ch_info->channel); | |
46bc8d4b | 3947 | il->band = ch_info->band; |
be663ab6 | 3948 | |
46bc8d4b | 3949 | il_set_flags_for_band(il, ctx, il->band, ctx->vif); |
be663ab6 WYG |
3950 | |
3951 | ctx->staging.ofdm_basic_rates = | |
e2ebc833 | 3952 | (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF; |
be663ab6 | 3953 | ctx->staging.cck_basic_rates = |
e2ebc833 | 3954 | (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF; |
be663ab6 WYG |
3955 | |
3956 | /* clear both MIX and PURE40 mode flag */ | |
e7392364 SG |
3957 | ctx->staging.flags &= |
3958 | ~(RXON_FLG_CHANNEL_MODE_MIXED | RXON_FLG_CHANNEL_MODE_PURE_40); | |
be663ab6 WYG |
3959 | if (ctx->vif) |
3960 | memcpy(ctx->staging.node_addr, ctx->vif->addr, ETH_ALEN); | |
3961 | ||
3962 | ctx->staging.ofdm_ht_single_stream_basic_rates = 0xff; | |
3963 | ctx->staging.ofdm_ht_dual_stream_basic_rates = 0xff; | |
3964 | } | |
e7392364 | 3965 | |
e2ebc833 | 3966 | EXPORT_SYMBOL(il_connection_init_rx_config); |
be663ab6 | 3967 | |
e7392364 SG |
3968 | void |
3969 | il_set_rate(struct il_priv *il) | |
be663ab6 WYG |
3970 | { |
3971 | const struct ieee80211_supported_band *hw = NULL; | |
3972 | struct ieee80211_rate *rate; | |
be663ab6 WYG |
3973 | int i; |
3974 | ||
46bc8d4b | 3975 | hw = il_get_hw_mode(il, il->band); |
be663ab6 | 3976 | if (!hw) { |
9406f797 | 3977 | IL_ERR("Failed to set rate: unable to get hw mode\n"); |
be663ab6 WYG |
3978 | return; |
3979 | } | |
3980 | ||
46bc8d4b | 3981 | il->active_rate = 0; |
be663ab6 WYG |
3982 | |
3983 | for (i = 0; i < hw->n_bitrates; i++) { | |
3984 | rate = &(hw->bitrates[i]); | |
2eb05816 | 3985 | if (rate->hw_value < RATE_COUNT_LEGACY) |
46bc8d4b | 3986 | il->active_rate |= (1 << rate->hw_value); |
be663ab6 WYG |
3987 | } |
3988 | ||
58de00a4 | 3989 | D_RATE("Set active_rate = %0x\n", il->active_rate); |
be663ab6 | 3990 | |
17d6e557 | 3991 | il->ctx.staging.cck_basic_rates = |
e7392364 | 3992 | (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF; |
be663ab6 | 3993 | |
17d6e557 | 3994 | il->ctx.staging.ofdm_basic_rates = |
e7392364 | 3995 | (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF; |
be663ab6 | 3996 | } |
e7392364 | 3997 | |
e2ebc833 | 3998 | EXPORT_SYMBOL(il_set_rate); |
be663ab6 | 3999 | |
e7392364 SG |
4000 | void |
4001 | il_chswitch_done(struct il_priv *il, bool is_success) | |
be663ab6 | 4002 | { |
7c2cde2e | 4003 | struct il_rxon_context *ctx = &il->ctx; |
be663ab6 | 4004 | |
a6766ccd | 4005 | if (test_bit(S_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
4006 | return; |
4007 | ||
a6766ccd | 4008 | if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status)) |
be663ab6 | 4009 | ieee80211_chswitch_done(ctx->vif, is_success); |
be663ab6 | 4010 | } |
e7392364 | 4011 | |
e2ebc833 | 4012 | EXPORT_SYMBOL(il_chswitch_done); |
be663ab6 | 4013 | |
e7392364 SG |
4014 | void |
4015 | il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb) | |
be663ab6 | 4016 | { |
dcae1c64 | 4017 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
e2ebc833 | 4018 | struct il_csa_notification *csa = &(pkt->u.csa_notif); |
be663ab6 | 4019 | |
7c2cde2e | 4020 | struct il_rxon_context *ctx = &il->ctx; |
e2ebc833 | 4021 | struct il_rxon_cmd *rxon = (void *)&ctx->active; |
be663ab6 | 4022 | |
a6766ccd | 4023 | if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status)) |
51e65257 SG |
4024 | return; |
4025 | ||
46bc8d4b | 4026 | if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) { |
51e65257 SG |
4027 | rxon->channel = csa->channel; |
4028 | ctx->staging.channel = csa->channel; | |
e7392364 | 4029 | D_11H("CSA notif: channel %d\n", le16_to_cpu(csa->channel)); |
46bc8d4b | 4030 | il_chswitch_done(il, true); |
51e65257 | 4031 | } else { |
9406f797 | 4032 | IL_ERR("CSA notif (fail) : channel %d\n", |
e7392364 | 4033 | le16_to_cpu(csa->channel)); |
46bc8d4b | 4034 | il_chswitch_done(il, false); |
be663ab6 WYG |
4035 | } |
4036 | } | |
e7392364 | 4037 | |
d2dfb33e | 4038 | EXPORT_SYMBOL(il_hdl_csa); |
be663ab6 | 4039 | |
d3175167 | 4040 | #ifdef CONFIG_IWLEGACY_DEBUG |
e7392364 SG |
4041 | void |
4042 | il_print_rx_config_cmd(struct il_priv *il, struct il_rxon_context *ctx) | |
be663ab6 | 4043 | { |
e2ebc833 | 4044 | struct il_rxon_cmd *rxon = &ctx->staging; |
be663ab6 | 4045 | |
58de00a4 | 4046 | D_RADIO("RX CONFIG:\n"); |
46bc8d4b | 4047 | il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon)); |
e7392364 | 4048 | D_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel)); |
58de00a4 | 4049 | D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags)); |
e7392364 | 4050 | D_RADIO("u32 filter_flags: 0x%08x\n", le32_to_cpu(rxon->filter_flags)); |
58de00a4 | 4051 | D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type); |
e7392364 SG |
4052 | D_RADIO("u8 ofdm_basic_rates: 0x%02x\n", rxon->ofdm_basic_rates); |
4053 | D_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates); | |
58de00a4 SG |
4054 | D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr); |
4055 | D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr); | |
e7392364 | 4056 | D_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id)); |
be663ab6 | 4057 | } |
e7392364 | 4058 | |
e2ebc833 | 4059 | EXPORT_SYMBOL(il_print_rx_config_cmd); |
be663ab6 WYG |
4060 | #endif |
4061 | /** | |
e2ebc833 | 4062 | * il_irq_handle_error - called for HW or SW error interrupt from card |
be663ab6 | 4063 | */ |
e7392364 SG |
4064 | void |
4065 | il_irq_handle_error(struct il_priv *il) | |
be663ab6 | 4066 | { |
e2ebc833 | 4067 | /* Set the FW error flag -- cleared on il_down */ |
a6766ccd | 4068 | set_bit(S_FW_ERROR, &il->status); |
be663ab6 WYG |
4069 | |
4070 | /* Cancel currently queued command. */ | |
a6766ccd | 4071 | clear_bit(S_HCMD_ACTIVE, &il->status); |
be663ab6 | 4072 | |
e7392364 | 4073 | IL_ERR("Loaded firmware version: %s\n", il->hw->wiphy->fw_version); |
be663ab6 | 4074 | |
46bc8d4b SG |
4075 | il->cfg->ops->lib->dump_nic_error_log(il); |
4076 | if (il->cfg->ops->lib->dump_fh) | |
4077 | il->cfg->ops->lib->dump_fh(il, NULL, false); | |
d3175167 | 4078 | #ifdef CONFIG_IWLEGACY_DEBUG |
46bc8d4b | 4079 | if (il_get_debug_level(il) & IL_DL_FW_ERRORS) |
e7392364 | 4080 | il_print_rx_config_cmd(il, &il->ctx); |
be663ab6 WYG |
4081 | #endif |
4082 | ||
46bc8d4b | 4083 | wake_up(&il->wait_command_queue); |
be663ab6 WYG |
4084 | |
4085 | /* Keep the restart process from trying to send host | |
4086 | * commands by clearing the INIT status bit */ | |
a6766ccd | 4087 | clear_bit(S_READY, &il->status); |
be663ab6 | 4088 | |
a6766ccd | 4089 | if (!test_bit(S_EXIT_PENDING, &il->status)) { |
58de00a4 | 4090 | IL_DBG(IL_DL_FW_ERRORS, |
e7392364 | 4091 | "Restarting adapter due to uCode error.\n"); |
be663ab6 | 4092 | |
46bc8d4b SG |
4093 | if (il->cfg->mod_params->restart_fw) |
4094 | queue_work(il->workqueue, &il->restart); | |
be663ab6 WYG |
4095 | } |
4096 | } | |
e7392364 | 4097 | |
e2ebc833 | 4098 | EXPORT_SYMBOL(il_irq_handle_error); |
be663ab6 | 4099 | |
e7392364 SG |
4100 | static int |
4101 | il_apm_stop_master(struct il_priv *il) | |
be663ab6 WYG |
4102 | { |
4103 | int ret = 0; | |
4104 | ||
4105 | /* stop device's busmaster DMA activity */ | |
46bc8d4b | 4106 | il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); |
be663ab6 | 4107 | |
e7392364 SG |
4108 | ret = |
4109 | _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED, | |
4110 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
be663ab6 | 4111 | if (ret) |
9406f797 | 4112 | IL_WARN("Master Disable Timed Out, 100 usec\n"); |
be663ab6 | 4113 | |
58de00a4 | 4114 | D_INFO("stop master\n"); |
be663ab6 WYG |
4115 | |
4116 | return ret; | |
4117 | } | |
4118 | ||
e7392364 SG |
4119 | void |
4120 | il_apm_stop(struct il_priv *il) | |
be663ab6 | 4121 | { |
58de00a4 | 4122 | D_INFO("Stop card, put in low power state\n"); |
be663ab6 WYG |
4123 | |
4124 | /* Stop device's DMA activity */ | |
46bc8d4b | 4125 | il_apm_stop_master(il); |
be663ab6 WYG |
4126 | |
4127 | /* Reset the entire device */ | |
46bc8d4b | 4128 | il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
be663ab6 WYG |
4129 | |
4130 | udelay(10); | |
4131 | ||
4132 | /* | |
4133 | * Clear "initialization complete" bit to move adapter from | |
4134 | * D0A* (powered-up Active) --> D0U* (Uninitialized) state. | |
4135 | */ | |
e7392364 | 4136 | il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
be663ab6 | 4137 | } |
be663ab6 | 4138 | |
e7392364 | 4139 | EXPORT_SYMBOL(il_apm_stop); |
be663ab6 WYG |
4140 | |
4141 | /* | |
4142 | * Start up NIC's basic functionality after it has been reset | |
e2ebc833 | 4143 | * (e.g. after platform boot, or shutdown via il_apm_stop()) |
be663ab6 WYG |
4144 | * NOTE: This does not load uCode nor start the embedded processor |
4145 | */ | |
e7392364 SG |
4146 | int |
4147 | il_apm_init(struct il_priv *il) | |
be663ab6 WYG |
4148 | { |
4149 | int ret = 0; | |
4150 | u16 lctl; | |
4151 | ||
58de00a4 | 4152 | D_INFO("Init card's basic functions\n"); |
be663ab6 WYG |
4153 | |
4154 | /* | |
4155 | * Use "set_bit" below rather than "write", to preserve any hardware | |
4156 | * bits already set by default after reset. | |
4157 | */ | |
4158 | ||
4159 | /* Disable L0S exit timer (platform NMI Work/Around) */ | |
46bc8d4b | 4160 | il_set_bit(il, CSR_GIO_CHICKEN_BITS, |
e7392364 | 4161 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
be663ab6 WYG |
4162 | |
4163 | /* | |
4164 | * Disable L0s without affecting L1; | |
4165 | * don't wait for ICH L0s (ICH bug W/A) | |
4166 | */ | |
46bc8d4b | 4167 | il_set_bit(il, CSR_GIO_CHICKEN_BITS, |
e7392364 | 4168 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); |
be663ab6 WYG |
4169 | |
4170 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ | |
e7392364 | 4171 | il_set_bit(il, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); |
be663ab6 WYG |
4172 | |
4173 | /* | |
4174 | * Enable HAP INTA (interrupt from management bus) to | |
4175 | * wake device's PCI Express link L1a -> L0s | |
25985edc | 4176 | * NOTE: This is no-op for 3945 (non-existent bit) |
be663ab6 | 4177 | */ |
46bc8d4b | 4178 | il_set_bit(il, CSR_HW_IF_CONFIG_REG, |
e7392364 | 4179 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); |
be663ab6 WYG |
4180 | |
4181 | /* | |
4182 | * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition. | |
4183 | * Check if BIOS (or OS) enabled L1-ASPM on this device. | |
4184 | * If so (likely), disable L0S, so device moves directly L0->L1; | |
4185 | * costs negligible amount of power savings. | |
4186 | * If not (unlikely), enable L0S, so there is at least some | |
4187 | * power savings, even without L1. | |
4188 | */ | |
46bc8d4b SG |
4189 | if (il->cfg->base_params->set_l0s) { |
4190 | lctl = il_pcie_link_ctl(il); | |
be663ab6 | 4191 | if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == |
e7392364 | 4192 | PCI_CFG_LINK_CTRL_VAL_L1_EN) { |
be663ab6 | 4193 | /* L1-ASPM enabled; disable(!) L0S */ |
46bc8d4b | 4194 | il_set_bit(il, CSR_GIO_REG, |
e7392364 | 4195 | CSR_GIO_REG_VAL_L0S_ENABLED); |
58de00a4 | 4196 | D_POWER("L1 Enabled; Disabling L0S\n"); |
be663ab6 WYG |
4197 | } else { |
4198 | /* L1-ASPM disabled; enable(!) L0S */ | |
46bc8d4b | 4199 | il_clear_bit(il, CSR_GIO_REG, |
e7392364 | 4200 | CSR_GIO_REG_VAL_L0S_ENABLED); |
58de00a4 | 4201 | D_POWER("L1 Disabled; Enabling L0S\n"); |
be663ab6 WYG |
4202 | } |
4203 | } | |
4204 | ||
4205 | /* Configure analog phase-lock-loop before activating to D0A */ | |
46bc8d4b SG |
4206 | if (il->cfg->base_params->pll_cfg_val) |
4207 | il_set_bit(il, CSR_ANA_PLL_CFG, | |
e7392364 | 4208 | il->cfg->base_params->pll_cfg_val); |
be663ab6 WYG |
4209 | |
4210 | /* | |
4211 | * Set "initialization complete" bit to move adapter from | |
4212 | * D0U* --> D0A* (powered-up active) state. | |
4213 | */ | |
46bc8d4b | 4214 | il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
be663ab6 WYG |
4215 | |
4216 | /* | |
4217 | * Wait for clock stabilization; once stabilized, access to | |
db54eb57 | 4218 | * device-internal resources is supported, e.g. il_wr_prph() |
be663ab6 WYG |
4219 | * and accesses to uCode SRAM. |
4220 | */ | |
e7392364 SG |
4221 | ret = |
4222 | _il_poll_bit(il, CSR_GP_CNTRL, | |
4223 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
4224 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
be663ab6 | 4225 | if (ret < 0) { |
58de00a4 | 4226 | D_INFO("Failed to init the card\n"); |
be663ab6 WYG |
4227 | goto out; |
4228 | } | |
4229 | ||
4230 | /* | |
4231 | * Enable DMA and BSM (if used) clocks, wait for them to stabilize. | |
4232 | * BSM (Boostrap State Machine) is only in 3945 and 4965. | |
4233 | * | |
4234 | * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits | |
4235 | * do not disable clocks. This preserves any hardware bits already | |
4236 | * set by default in "CLK_CTRL_REG" after reset. | |
4237 | */ | |
46bc8d4b | 4238 | if (il->cfg->base_params->use_bsm) |
db54eb57 | 4239 | il_wr_prph(il, APMG_CLK_EN_REG, |
e7392364 | 4240 | APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT); |
be663ab6 | 4241 | else |
e7392364 | 4242 | il_wr_prph(il, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); |
be663ab6 WYG |
4243 | udelay(20); |
4244 | ||
4245 | /* Disable L1-Active */ | |
46bc8d4b | 4246 | il_set_bits_prph(il, APMG_PCIDEV_STT_REG, |
e7392364 | 4247 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
be663ab6 WYG |
4248 | |
4249 | out: | |
4250 | return ret; | |
4251 | } | |
be663ab6 | 4252 | |
e7392364 | 4253 | EXPORT_SYMBOL(il_apm_init); |
be663ab6 | 4254 | |
e7392364 SG |
4255 | int |
4256 | il_set_tx_power(struct il_priv *il, s8 tx_power, bool force) | |
be663ab6 WYG |
4257 | { |
4258 | int ret; | |
4259 | s8 prev_tx_power; | |
43f12d47 | 4260 | bool defer; |
7c2cde2e | 4261 | struct il_rxon_context *ctx = &il->ctx; |
be663ab6 | 4262 | |
46bc8d4b | 4263 | lockdep_assert_held(&il->mutex); |
be663ab6 | 4264 | |
46bc8d4b | 4265 | if (il->tx_power_user_lmt == tx_power && !force) |
be663ab6 WYG |
4266 | return 0; |
4267 | ||
46bc8d4b | 4268 | if (!il->cfg->ops->lib->send_tx_power) |
be663ab6 WYG |
4269 | return -EOPNOTSUPP; |
4270 | ||
332704a5 SG |
4271 | /* 0 dBm mean 1 milliwatt */ |
4272 | if (tx_power < 0) { | |
e7392364 | 4273 | IL_WARN("Requested user TXPOWER %d below 1 mW.\n", tx_power); |
be663ab6 WYG |
4274 | return -EINVAL; |
4275 | } | |
4276 | ||
46bc8d4b | 4277 | if (tx_power > il->tx_power_device_lmt) { |
e7392364 SG |
4278 | IL_WARN("Requested user TXPOWER %d above upper limit %d.\n", |
4279 | tx_power, il->tx_power_device_lmt); | |
be663ab6 WYG |
4280 | return -EINVAL; |
4281 | } | |
4282 | ||
46bc8d4b | 4283 | if (!il_is_ready_rf(il)) |
be663ab6 WYG |
4284 | return -EIO; |
4285 | ||
43f12d47 SG |
4286 | /* scan complete and commit_rxon use tx_power_next value, |
4287 | * it always need to be updated for newest request */ | |
46bc8d4b | 4288 | il->tx_power_next = tx_power; |
43f12d47 SG |
4289 | |
4290 | /* do not set tx power when scanning or channel changing */ | |
a6766ccd | 4291 | defer = test_bit(S_SCANNING, &il->status) || |
e7392364 | 4292 | memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging)); |
43f12d47 | 4293 | if (defer && !force) { |
58de00a4 | 4294 | D_INFO("Deferring tx power set\n"); |
be663ab6 WYG |
4295 | return 0; |
4296 | } | |
4297 | ||
46bc8d4b SG |
4298 | prev_tx_power = il->tx_power_user_lmt; |
4299 | il->tx_power_user_lmt = tx_power; | |
be663ab6 | 4300 | |
46bc8d4b | 4301 | ret = il->cfg->ops->lib->send_tx_power(il); |
be663ab6 WYG |
4302 | |
4303 | /* if fail to set tx_power, restore the orig. tx power */ | |
4304 | if (ret) { | |
46bc8d4b SG |
4305 | il->tx_power_user_lmt = prev_tx_power; |
4306 | il->tx_power_next = prev_tx_power; | |
be663ab6 WYG |
4307 | } |
4308 | return ret; | |
4309 | } | |
e7392364 | 4310 | |
e2ebc833 | 4311 | EXPORT_SYMBOL(il_set_tx_power); |
be663ab6 | 4312 | |
e7392364 SG |
4313 | void |
4314 | il_send_bt_config(struct il_priv *il) | |
be663ab6 | 4315 | { |
e2ebc833 | 4316 | struct il_bt_cmd bt_cmd = { |
be663ab6 WYG |
4317 | .lead_time = BT_LEAD_TIME_DEF, |
4318 | .max_kill = BT_MAX_KILL_DEF, | |
4319 | .kill_ack_mask = 0, | |
4320 | .kill_cts_mask = 0, | |
4321 | }; | |
4322 | ||
4323 | if (!bt_coex_active) | |
4324 | bt_cmd.flags = BT_COEX_DISABLE; | |
4325 | else | |
4326 | bt_cmd.flags = BT_COEX_ENABLE; | |
4327 | ||
58de00a4 | 4328 | D_INFO("BT coex %s\n", |
e7392364 | 4329 | (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active"); |
be663ab6 | 4330 | |
e7392364 | 4331 | if (il_send_cmd_pdu(il, C_BT_CONFIG, sizeof(struct il_bt_cmd), &bt_cmd)) |
9406f797 | 4332 | IL_ERR("failed to send BT Coex Config\n"); |
be663ab6 | 4333 | } |
e2ebc833 | 4334 | EXPORT_SYMBOL(il_send_bt_config); |
be663ab6 | 4335 | |
e7392364 SG |
4336 | int |
4337 | il_send_stats_request(struct il_priv *il, u8 flags, bool clear) | |
be663ab6 | 4338 | { |
ebf0d90d | 4339 | struct il_stats_cmd stats_cmd = { |
e7392364 | 4340 | .configuration_flags = clear ? IL_STATS_CONF_CLEAR_STATS : 0, |
be663ab6 WYG |
4341 | }; |
4342 | ||
4343 | if (flags & CMD_ASYNC) | |
e7392364 SG |
4344 | return il_send_cmd_pdu_async(il, C_STATS, sizeof(struct il_stats_cmd), |
4345 | &stats_cmd, NULL); | |
be663ab6 | 4346 | else |
e7392364 SG |
4347 | return il_send_cmd_pdu(il, C_STATS, sizeof(struct il_stats_cmd), |
4348 | &stats_cmd); | |
be663ab6 | 4349 | } |
ebf0d90d | 4350 | EXPORT_SYMBOL(il_send_stats_request); |
be663ab6 | 4351 | |
e7392364 SG |
4352 | void |
4353 | il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb) | |
be663ab6 | 4354 | { |
d3175167 | 4355 | #ifdef CONFIG_IWLEGACY_DEBUG |
dcae1c64 | 4356 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
e2ebc833 | 4357 | struct il_sleep_notification *sleep = &(pkt->u.sleep_notif); |
58de00a4 | 4358 | D_RX("sleep mode: %d, src: %d\n", |
be663ab6 WYG |
4359 | sleep->pm_sleep_mode, sleep->pm_wakeup_src); |
4360 | #endif | |
4361 | } | |
d2dfb33e | 4362 | EXPORT_SYMBOL(il_hdl_pm_sleep); |
be663ab6 | 4363 | |
e7392364 SG |
4364 | void |
4365 | il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb) | |
be663ab6 | 4366 | { |
dcae1c64 | 4367 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
e94a4099 | 4368 | u32 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK; |
e7392364 SG |
4369 | D_RADIO("Dumping %d bytes of unhandled notification for %s:\n", len, |
4370 | il_get_cmd_string(pkt->hdr.cmd)); | |
46bc8d4b | 4371 | il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len); |
be663ab6 | 4372 | } |
d2dfb33e | 4373 | EXPORT_SYMBOL(il_hdl_pm_debug_stats); |
be663ab6 | 4374 | |
e7392364 SG |
4375 | void |
4376 | il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb) | |
be663ab6 | 4377 | { |
dcae1c64 | 4378 | struct il_rx_pkt *pkt = rxb_addr(rxb); |
be663ab6 | 4379 | |
9406f797 | 4380 | IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) " |
e7392364 SG |
4381 | "seq 0x%04X ser 0x%08X\n", |
4382 | le32_to_cpu(pkt->u.err_resp.error_type), | |
4383 | il_get_cmd_string(pkt->u.err_resp.cmd_id), | |
4384 | pkt->u.err_resp.cmd_id, | |
4385 | le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num), | |
4386 | le32_to_cpu(pkt->u.err_resp.error_info)); | |
be663ab6 | 4387 | } |
6e9848b4 | 4388 | EXPORT_SYMBOL(il_hdl_error); |
be663ab6 | 4389 | |
e7392364 SG |
4390 | void |
4391 | il_clear_isr_stats(struct il_priv *il) | |
be663ab6 | 4392 | { |
46bc8d4b | 4393 | memset(&il->isr_stats, 0, sizeof(il->isr_stats)); |
be663ab6 WYG |
4394 | } |
4395 | ||
e7392364 SG |
4396 | int |
4397 | il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue, | |
4398 | const struct ieee80211_tx_queue_params *params) | |
be663ab6 | 4399 | { |
46bc8d4b | 4400 | struct il_priv *il = hw->priv; |
be663ab6 WYG |
4401 | unsigned long flags; |
4402 | int q; | |
4403 | ||
58de00a4 | 4404 | D_MAC80211("enter\n"); |
be663ab6 | 4405 | |
46bc8d4b | 4406 | if (!il_is_ready_rf(il)) { |
58de00a4 | 4407 | D_MAC80211("leave - RF not ready\n"); |
be663ab6 WYG |
4408 | return -EIO; |
4409 | } | |
4410 | ||
4411 | if (queue >= AC_NUM) { | |
58de00a4 | 4412 | D_MAC80211("leave - queue >= AC_NUM %d\n", queue); |
be663ab6 WYG |
4413 | return 0; |
4414 | } | |
4415 | ||
4416 | q = AC_NUM - 1 - queue; | |
4417 | ||
46bc8d4b | 4418 | spin_lock_irqsave(&il->lock, flags); |
be663ab6 | 4419 | |
17d6e557 | 4420 | il->ctx.qos_data.def_qos_parm.ac[q].cw_min = |
e7392364 | 4421 | cpu_to_le16(params->cw_min); |
17d6e557 | 4422 | il->ctx.qos_data.def_qos_parm.ac[q].cw_max = |
e7392364 | 4423 | cpu_to_le16(params->cw_max); |
17d6e557 SG |
4424 | il->ctx.qos_data.def_qos_parm.ac[q].aifsn = params->aifs; |
4425 | il->ctx.qos_data.def_qos_parm.ac[q].edca_txop = | |
e7392364 | 4426 | cpu_to_le16((params->txop * 32)); |
be663ab6 | 4427 | |
17d6e557 | 4428 | il->ctx.qos_data.def_qos_parm.ac[q].reserved1 = 0; |
be663ab6 | 4429 | |
46bc8d4b | 4430 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 | 4431 | |
58de00a4 | 4432 | D_MAC80211("leave\n"); |
be663ab6 WYG |
4433 | return 0; |
4434 | } | |
e7392364 | 4435 | |
e2ebc833 | 4436 | EXPORT_SYMBOL(il_mac_conf_tx); |
be663ab6 | 4437 | |
e7392364 SG |
4438 | int |
4439 | il_mac_tx_last_beacon(struct ieee80211_hw *hw) | |
be663ab6 | 4440 | { |
46bc8d4b | 4441 | struct il_priv *il = hw->priv; |
be663ab6 | 4442 | |
46bc8d4b | 4443 | return il->ibss_manager == IL_IBSS_MANAGER; |
be663ab6 | 4444 | } |
e7392364 | 4445 | |
e2ebc833 | 4446 | EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon); |
be663ab6 WYG |
4447 | |
4448 | static int | |
46bc8d4b | 4449 | il_set_mode(struct il_priv *il, struct il_rxon_context *ctx) |
be663ab6 | 4450 | { |
46bc8d4b | 4451 | il_connection_init_rx_config(il, ctx); |
be663ab6 | 4452 | |
46bc8d4b SG |
4453 | if (il->cfg->ops->hcmd->set_rxon_chain) |
4454 | il->cfg->ops->hcmd->set_rxon_chain(il, ctx); | |
be663ab6 | 4455 | |
46bc8d4b | 4456 | return il_commit_rxon(il, ctx); |
be663ab6 WYG |
4457 | } |
4458 | ||
e7392364 SG |
4459 | static int |
4460 | il_setup_interface(struct il_priv *il, struct il_rxon_context *ctx) | |
be663ab6 WYG |
4461 | { |
4462 | struct ieee80211_vif *vif = ctx->vif; | |
4463 | int err; | |
4464 | ||
46bc8d4b | 4465 | lockdep_assert_held(&il->mutex); |
be663ab6 WYG |
4466 | |
4467 | /* | |
4468 | * This variable will be correct only when there's just | |
4469 | * a single context, but all code using it is for hardware | |
4470 | * that supports only one context. | |
4471 | */ | |
46bc8d4b | 4472 | il->iw_mode = vif->type; |
be663ab6 WYG |
4473 | |
4474 | ctx->is_active = true; | |
4475 | ||
46bc8d4b | 4476 | err = il_set_mode(il, ctx); |
be663ab6 WYG |
4477 | if (err) { |
4478 | if (!ctx->always_active) | |
4479 | ctx->is_active = false; | |
4480 | return err; | |
4481 | } | |
4482 | ||
4483 | return 0; | |
4484 | } | |
4485 | ||
4486 | int | |
e2ebc833 | 4487 | il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
be663ab6 | 4488 | { |
46bc8d4b | 4489 | struct il_priv *il = hw->priv; |
e2ebc833 | 4490 | struct il_vif_priv *vif_priv = (void *)vif->drv_priv; |
be663ab6 | 4491 | int err; |
17d6e557 | 4492 | u32 modes; |
be663ab6 | 4493 | |
e7392364 | 4494 | D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr); |
be663ab6 | 4495 | |
46bc8d4b | 4496 | mutex_lock(&il->mutex); |
be663ab6 | 4497 | |
46bc8d4b | 4498 | if (!il_is_ready_rf(il)) { |
9406f797 | 4499 | IL_WARN("Try to add interface when device not ready\n"); |
be663ab6 WYG |
4500 | err = -EINVAL; |
4501 | goto out; | |
4502 | } | |
4503 | ||
17d6e557 SG |
4504 | /* check if busy context is exclusive */ |
4505 | if (il->ctx.vif && | |
4506 | (il->ctx.exclusive_interface_modes & BIT(il->ctx.vif->type))) { | |
4507 | err = -EINVAL; | |
4508 | goto out; | |
be663ab6 WYG |
4509 | } |
4510 | ||
17d6e557 SG |
4511 | modes = il->ctx.interface_modes | il->ctx.exclusive_interface_modes; |
4512 | if (!(modes & BIT(vif->type))) { | |
be663ab6 WYG |
4513 | err = -EOPNOTSUPP; |
4514 | goto out; | |
4515 | } | |
4516 | ||
17d6e557 SG |
4517 | vif_priv->ctx = &il->ctx; |
4518 | il->ctx.vif = vif; | |
be663ab6 | 4519 | |
17d6e557 SG |
4520 | err = il_setup_interface(il, &il->ctx); |
4521 | if (err) { | |
4522 | il->ctx.vif = NULL; | |
4523 | il->iw_mode = NL80211_IFTYPE_STATION; | |
4524 | } | |
be663ab6 | 4525 | |
e7392364 | 4526 | out: |
46bc8d4b | 4527 | mutex_unlock(&il->mutex); |
be663ab6 | 4528 | |
58de00a4 | 4529 | D_MAC80211("leave\n"); |
be663ab6 WYG |
4530 | return err; |
4531 | } | |
e7392364 | 4532 | |
e2ebc833 | 4533 | EXPORT_SYMBOL(il_mac_add_interface); |
be663ab6 | 4534 | |
e7392364 SG |
4535 | static void |
4536 | il_teardown_interface(struct il_priv *il, struct ieee80211_vif *vif, | |
4537 | bool mode_change) | |
be663ab6 | 4538 | { |
e2ebc833 | 4539 | struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif); |
be663ab6 | 4540 | |
46bc8d4b | 4541 | lockdep_assert_held(&il->mutex); |
be663ab6 | 4542 | |
46bc8d4b SG |
4543 | if (il->scan_vif == vif) { |
4544 | il_scan_cancel_timeout(il, 200); | |
4545 | il_force_scan_end(il); | |
be663ab6 WYG |
4546 | } |
4547 | ||
4548 | if (!mode_change) { | |
46bc8d4b | 4549 | il_set_mode(il, ctx); |
be663ab6 WYG |
4550 | if (!ctx->always_active) |
4551 | ctx->is_active = false; | |
4552 | } | |
4553 | } | |
4554 | ||
e7392364 SG |
4555 | void |
4556 | il_mac_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif) | |
be663ab6 | 4557 | { |
46bc8d4b | 4558 | struct il_priv *il = hw->priv; |
e2ebc833 | 4559 | struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif); |
be663ab6 | 4560 | |
58de00a4 | 4561 | D_MAC80211("enter\n"); |
be663ab6 | 4562 | |
46bc8d4b | 4563 | mutex_lock(&il->mutex); |
be663ab6 WYG |
4564 | |
4565 | WARN_ON(ctx->vif != vif); | |
4566 | ctx->vif = NULL; | |
4567 | ||
46bc8d4b | 4568 | il_teardown_interface(il, vif, false); |
be663ab6 | 4569 | |
46bc8d4b SG |
4570 | memset(il->bssid, 0, ETH_ALEN); |
4571 | mutex_unlock(&il->mutex); | |
be663ab6 | 4572 | |
58de00a4 | 4573 | D_MAC80211("leave\n"); |
be663ab6 WYG |
4574 | |
4575 | } | |
e7392364 | 4576 | |
e2ebc833 | 4577 | EXPORT_SYMBOL(il_mac_remove_interface); |
be663ab6 | 4578 | |
e7392364 SG |
4579 | int |
4580 | il_alloc_txq_mem(struct il_priv *il) | |
be663ab6 | 4581 | { |
46bc8d4b | 4582 | if (!il->txq) |
e7392364 SG |
4583 | il->txq = |
4584 | kzalloc(sizeof(struct il_tx_queue) * | |
4585 | il->cfg->base_params->num_of_queues, GFP_KERNEL); | |
46bc8d4b | 4586 | if (!il->txq) { |
9406f797 | 4587 | IL_ERR("Not enough memory for txq\n"); |
be663ab6 WYG |
4588 | return -ENOMEM; |
4589 | } | |
4590 | return 0; | |
4591 | } | |
e7392364 | 4592 | |
e2ebc833 | 4593 | EXPORT_SYMBOL(il_alloc_txq_mem); |
be663ab6 | 4594 | |
e7392364 SG |
4595 | void |
4596 | il_txq_mem(struct il_priv *il) | |
be663ab6 | 4597 | { |
46bc8d4b SG |
4598 | kfree(il->txq); |
4599 | il->txq = NULL; | |
be663ab6 | 4600 | } |
e7392364 | 4601 | |
e2ebc833 | 4602 | EXPORT_SYMBOL(il_txq_mem); |
be663ab6 | 4603 | |
d3175167 | 4604 | #ifdef CONFIG_IWLEGACY_DEBUGFS |
be663ab6 | 4605 | |
e2ebc833 | 4606 | #define IL_TRAFFIC_DUMP_SIZE (IL_TRAFFIC_ENTRY_SIZE * IL_TRAFFIC_ENTRIES) |
be663ab6 | 4607 | |
e7392364 SG |
4608 | void |
4609 | il_reset_traffic_log(struct il_priv *il) | |
be663ab6 | 4610 | { |
46bc8d4b SG |
4611 | il->tx_traffic_idx = 0; |
4612 | il->rx_traffic_idx = 0; | |
4613 | if (il->tx_traffic) | |
4614 | memset(il->tx_traffic, 0, IL_TRAFFIC_DUMP_SIZE); | |
4615 | if (il->rx_traffic) | |
4616 | memset(il->rx_traffic, 0, IL_TRAFFIC_DUMP_SIZE); | |
be663ab6 WYG |
4617 | } |
4618 | ||
e7392364 SG |
4619 | int |
4620 | il_alloc_traffic_mem(struct il_priv *il) | |
be663ab6 | 4621 | { |
e2ebc833 | 4622 | u32 traffic_size = IL_TRAFFIC_DUMP_SIZE; |
be663ab6 | 4623 | |
d2ddf621 | 4624 | if (il_debug_level & IL_DL_TX) { |
46bc8d4b | 4625 | if (!il->tx_traffic) { |
e7392364 | 4626 | il->tx_traffic = kzalloc(traffic_size, GFP_KERNEL); |
46bc8d4b | 4627 | if (!il->tx_traffic) |
be663ab6 WYG |
4628 | return -ENOMEM; |
4629 | } | |
4630 | } | |
d2ddf621 | 4631 | if (il_debug_level & IL_DL_RX) { |
46bc8d4b | 4632 | if (!il->rx_traffic) { |
e7392364 | 4633 | il->rx_traffic = kzalloc(traffic_size, GFP_KERNEL); |
46bc8d4b | 4634 | if (!il->rx_traffic) |
be663ab6 WYG |
4635 | return -ENOMEM; |
4636 | } | |
4637 | } | |
46bc8d4b | 4638 | il_reset_traffic_log(il); |
be663ab6 WYG |
4639 | return 0; |
4640 | } | |
e7392364 | 4641 | |
e2ebc833 | 4642 | EXPORT_SYMBOL(il_alloc_traffic_mem); |
be663ab6 | 4643 | |
e7392364 SG |
4644 | void |
4645 | il_free_traffic_mem(struct il_priv *il) | |
be663ab6 | 4646 | { |
46bc8d4b SG |
4647 | kfree(il->tx_traffic); |
4648 | il->tx_traffic = NULL; | |
be663ab6 | 4649 | |
46bc8d4b SG |
4650 | kfree(il->rx_traffic); |
4651 | il->rx_traffic = NULL; | |
be663ab6 | 4652 | } |
e7392364 | 4653 | |
e2ebc833 | 4654 | EXPORT_SYMBOL(il_free_traffic_mem); |
be663ab6 | 4655 | |
e7392364 SG |
4656 | void |
4657 | il_dbg_log_tx_data_frame(struct il_priv *il, u16 length, | |
4658 | struct ieee80211_hdr *header) | |
be663ab6 WYG |
4659 | { |
4660 | __le16 fc; | |
4661 | u16 len; | |
4662 | ||
d2ddf621 | 4663 | if (likely(!(il_debug_level & IL_DL_TX))) |
be663ab6 WYG |
4664 | return; |
4665 | ||
46bc8d4b | 4666 | if (!il->tx_traffic) |
be663ab6 WYG |
4667 | return; |
4668 | ||
4669 | fc = header->frame_control; | |
4670 | if (ieee80211_is_data(fc)) { | |
e7392364 SG |
4671 | len = |
4672 | (length > | |
4673 | IL_TRAFFIC_ENTRY_SIZE) ? IL_TRAFFIC_ENTRY_SIZE : length; | |
46bc8d4b | 4674 | memcpy((il->tx_traffic + |
e7392364 SG |
4675 | (il->tx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)), header, |
4676 | len); | |
46bc8d4b | 4677 | il->tx_traffic_idx = |
e7392364 | 4678 | (il->tx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES; |
be663ab6 WYG |
4679 | } |
4680 | } | |
e7392364 | 4681 | |
e2ebc833 | 4682 | EXPORT_SYMBOL(il_dbg_log_tx_data_frame); |
be663ab6 | 4683 | |
e7392364 SG |
4684 | void |
4685 | il_dbg_log_rx_data_frame(struct il_priv *il, u16 length, | |
4686 | struct ieee80211_hdr *header) | |
be663ab6 WYG |
4687 | { |
4688 | __le16 fc; | |
4689 | u16 len; | |
4690 | ||
d2ddf621 | 4691 | if (likely(!(il_debug_level & IL_DL_RX))) |
be663ab6 WYG |
4692 | return; |
4693 | ||
46bc8d4b | 4694 | if (!il->rx_traffic) |
be663ab6 WYG |
4695 | return; |
4696 | ||
4697 | fc = header->frame_control; | |
4698 | if (ieee80211_is_data(fc)) { | |
e7392364 SG |
4699 | len = |
4700 | (length > | |
4701 | IL_TRAFFIC_ENTRY_SIZE) ? IL_TRAFFIC_ENTRY_SIZE : length; | |
46bc8d4b | 4702 | memcpy((il->rx_traffic + |
e7392364 SG |
4703 | (il->rx_traffic_idx * IL_TRAFFIC_ENTRY_SIZE)), header, |
4704 | len); | |
46bc8d4b | 4705 | il->rx_traffic_idx = |
e7392364 | 4706 | (il->rx_traffic_idx + 1) % IL_TRAFFIC_ENTRIES; |
be663ab6 WYG |
4707 | } |
4708 | } | |
e7392364 | 4709 | |
e2ebc833 | 4710 | EXPORT_SYMBOL(il_dbg_log_rx_data_frame); |
be663ab6 | 4711 | |
e7392364 SG |
4712 | const char * |
4713 | il_get_mgmt_string(int cmd) | |
be663ab6 WYG |
4714 | { |
4715 | switch (cmd) { | |
e2ebc833 SG |
4716 | IL_CMD(MANAGEMENT_ASSOC_REQ); |
4717 | IL_CMD(MANAGEMENT_ASSOC_RESP); | |
4718 | IL_CMD(MANAGEMENT_REASSOC_REQ); | |
4719 | IL_CMD(MANAGEMENT_REASSOC_RESP); | |
4720 | IL_CMD(MANAGEMENT_PROBE_REQ); | |
4721 | IL_CMD(MANAGEMENT_PROBE_RESP); | |
4722 | IL_CMD(MANAGEMENT_BEACON); | |
4723 | IL_CMD(MANAGEMENT_ATIM); | |
4724 | IL_CMD(MANAGEMENT_DISASSOC); | |
4725 | IL_CMD(MANAGEMENT_AUTH); | |
4726 | IL_CMD(MANAGEMENT_DEAUTH); | |
4727 | IL_CMD(MANAGEMENT_ACTION); | |
be663ab6 WYG |
4728 | default: |
4729 | return "UNKNOWN"; | |
4730 | ||
4731 | } | |
4732 | } | |
4733 | ||
e7392364 SG |
4734 | const char * |
4735 | il_get_ctrl_string(int cmd) | |
be663ab6 WYG |
4736 | { |
4737 | switch (cmd) { | |
e2ebc833 SG |
4738 | IL_CMD(CONTROL_BACK_REQ); |
4739 | IL_CMD(CONTROL_BACK); | |
4740 | IL_CMD(CONTROL_PSPOLL); | |
4741 | IL_CMD(CONTROL_RTS); | |
4742 | IL_CMD(CONTROL_CTS); | |
4743 | IL_CMD(CONTROL_ACK); | |
4744 | IL_CMD(CONTROL_CFEND); | |
4745 | IL_CMD(CONTROL_CFENDACK); | |
be663ab6 WYG |
4746 | default: |
4747 | return "UNKNOWN"; | |
4748 | ||
4749 | } | |
4750 | } | |
4751 | ||
e7392364 SG |
4752 | void |
4753 | il_clear_traffic_stats(struct il_priv *il) | |
be663ab6 | 4754 | { |
46bc8d4b SG |
4755 | memset(&il->tx_stats, 0, sizeof(struct traffic_stats)); |
4756 | memset(&il->rx_stats, 0, sizeof(struct traffic_stats)); | |
be663ab6 WYG |
4757 | } |
4758 | ||
4759 | /* | |
d3175167 | 4760 | * if CONFIG_IWLEGACY_DEBUGFS defined, |
e2ebc833 | 4761 | * il_update_stats function will |
be663ab6 | 4762 | * record all the MGMT, CTRL and DATA pkt for both TX and Rx pass |
ebf0d90d | 4763 | * Use debugFs to display the rx/rx_stats |
d3175167 | 4764 | * if CONFIG_IWLEGACY_DEBUGFS not being defined, then no MGMT and CTRL |
be663ab6 | 4765 | * information will be recorded, but DATA pkt still will be recorded |
e2ebc833 | 4766 | * for the reason of il_led.c need to control the led blinking based on |
be663ab6 WYG |
4767 | * number of tx and rx data. |
4768 | * | |
4769 | */ | |
4770 | void | |
46bc8d4b | 4771 | il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len) |
be663ab6 | 4772 | { |
e7392364 | 4773 | struct traffic_stats *stats; |
be663ab6 WYG |
4774 | |
4775 | if (is_tx) | |
46bc8d4b | 4776 | stats = &il->tx_stats; |
be663ab6 | 4777 | else |
46bc8d4b | 4778 | stats = &il->rx_stats; |
be663ab6 WYG |
4779 | |
4780 | if (ieee80211_is_mgmt(fc)) { | |
4781 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
4782 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
4783 | stats->mgmt[MANAGEMENT_ASSOC_REQ]++; | |
4784 | break; | |
4785 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_RESP): | |
4786 | stats->mgmt[MANAGEMENT_ASSOC_RESP]++; | |
4787 | break; | |
4788 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
4789 | stats->mgmt[MANAGEMENT_REASSOC_REQ]++; | |
4790 | break; | |
4791 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_RESP): | |
4792 | stats->mgmt[MANAGEMENT_REASSOC_RESP]++; | |
4793 | break; | |
4794 | case cpu_to_le16(IEEE80211_STYPE_PROBE_REQ): | |
4795 | stats->mgmt[MANAGEMENT_PROBE_REQ]++; | |
4796 | break; | |
4797 | case cpu_to_le16(IEEE80211_STYPE_PROBE_RESP): | |
4798 | stats->mgmt[MANAGEMENT_PROBE_RESP]++; | |
4799 | break; | |
4800 | case cpu_to_le16(IEEE80211_STYPE_BEACON): | |
4801 | stats->mgmt[MANAGEMENT_BEACON]++; | |
4802 | break; | |
4803 | case cpu_to_le16(IEEE80211_STYPE_ATIM): | |
4804 | stats->mgmt[MANAGEMENT_ATIM]++; | |
4805 | break; | |
4806 | case cpu_to_le16(IEEE80211_STYPE_DISASSOC): | |
4807 | stats->mgmt[MANAGEMENT_DISASSOC]++; | |
4808 | break; | |
4809 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
4810 | stats->mgmt[MANAGEMENT_AUTH]++; | |
4811 | break; | |
4812 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
4813 | stats->mgmt[MANAGEMENT_DEAUTH]++; | |
4814 | break; | |
4815 | case cpu_to_le16(IEEE80211_STYPE_ACTION): | |
4816 | stats->mgmt[MANAGEMENT_ACTION]++; | |
4817 | break; | |
4818 | } | |
4819 | } else if (ieee80211_is_ctl(fc)) { | |
4820 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
4821 | case cpu_to_le16(IEEE80211_STYPE_BACK_REQ): | |
4822 | stats->ctrl[CONTROL_BACK_REQ]++; | |
4823 | break; | |
4824 | case cpu_to_le16(IEEE80211_STYPE_BACK): | |
4825 | stats->ctrl[CONTROL_BACK]++; | |
4826 | break; | |
4827 | case cpu_to_le16(IEEE80211_STYPE_PSPOLL): | |
4828 | stats->ctrl[CONTROL_PSPOLL]++; | |
4829 | break; | |
4830 | case cpu_to_le16(IEEE80211_STYPE_RTS): | |
4831 | stats->ctrl[CONTROL_RTS]++; | |
4832 | break; | |
4833 | case cpu_to_le16(IEEE80211_STYPE_CTS): | |
4834 | stats->ctrl[CONTROL_CTS]++; | |
4835 | break; | |
4836 | case cpu_to_le16(IEEE80211_STYPE_ACK): | |
4837 | stats->ctrl[CONTROL_ACK]++; | |
4838 | break; | |
4839 | case cpu_to_le16(IEEE80211_STYPE_CFEND): | |
4840 | stats->ctrl[CONTROL_CFEND]++; | |
4841 | break; | |
4842 | case cpu_to_le16(IEEE80211_STYPE_CFENDACK): | |
4843 | stats->ctrl[CONTROL_CFENDACK]++; | |
4844 | break; | |
4845 | } | |
4846 | } else { | |
4847 | /* data */ | |
4848 | stats->data_cnt++; | |
4849 | stats->data_bytes += len; | |
4850 | } | |
4851 | } | |
e7392364 | 4852 | |
e2ebc833 | 4853 | EXPORT_SYMBOL(il_update_stats); |
be663ab6 WYG |
4854 | #endif |
4855 | ||
e7392364 SG |
4856 | int |
4857 | il_force_reset(struct il_priv *il, bool external) | |
be663ab6 | 4858 | { |
e2ebc833 | 4859 | struct il_force_reset *force_reset; |
be663ab6 | 4860 | |
a6766ccd | 4861 | if (test_bit(S_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
4862 | return -EINVAL; |
4863 | ||
46bc8d4b | 4864 | force_reset = &il->force_reset; |
be663ab6 WYG |
4865 | force_reset->reset_request_count++; |
4866 | if (!external) { | |
4867 | if (force_reset->last_force_reset_jiffies && | |
4868 | time_after(force_reset->last_force_reset_jiffies + | |
e7392364 | 4869 | force_reset->reset_duration, jiffies)) { |
58de00a4 | 4870 | D_INFO("force reset rejected\n"); |
be663ab6 WYG |
4871 | force_reset->reset_reject_count++; |
4872 | return -EAGAIN; | |
4873 | } | |
4874 | } | |
4875 | force_reset->reset_success_count++; | |
4876 | force_reset->last_force_reset_jiffies = jiffies; | |
dd6d2a8a SG |
4877 | |
4878 | /* | |
4879 | * if the request is from external(ex: debugfs), | |
4880 | * then always perform the request in regardless the module | |
4881 | * parameter setting | |
4882 | * if the request is from internal (uCode error or driver | |
4883 | * detect failure), then fw_restart module parameter | |
4884 | * need to be check before performing firmware reload | |
4885 | */ | |
4886 | ||
46bc8d4b | 4887 | if (!external && !il->cfg->mod_params->restart_fw) { |
58de00a4 | 4888 | D_INFO("Cancel firmware reload based on " |
e7392364 | 4889 | "module parameter setting\n"); |
dd6d2a8a | 4890 | return 0; |
be663ab6 | 4891 | } |
dd6d2a8a | 4892 | |
9406f797 | 4893 | IL_ERR("On demand firmware reload\n"); |
dd6d2a8a | 4894 | |
e2ebc833 | 4895 | /* Set the FW error flag -- cleared on il_down */ |
a6766ccd | 4896 | set_bit(S_FW_ERROR, &il->status); |
46bc8d4b | 4897 | wake_up(&il->wait_command_queue); |
dd6d2a8a SG |
4898 | /* |
4899 | * Keep the restart process from trying to send host | |
4900 | * commands by clearing the INIT status bit | |
4901 | */ | |
a6766ccd | 4902 | clear_bit(S_READY, &il->status); |
46bc8d4b | 4903 | queue_work(il->workqueue, &il->restart); |
dd6d2a8a | 4904 | |
be663ab6 WYG |
4905 | return 0; |
4906 | } | |
4907 | ||
4908 | int | |
e7392364 | 4909 | il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
be663ab6 WYG |
4910 | enum nl80211_iftype newtype, bool newp2p) |
4911 | { | |
46bc8d4b | 4912 | struct il_priv *il = hw->priv; |
e2ebc833 | 4913 | struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif); |
17d6e557 | 4914 | u32 modes; |
be663ab6 WYG |
4915 | int err; |
4916 | ||
4917 | newtype = ieee80211_iftype_p2p(newtype, newp2p); | |
4918 | ||
46bc8d4b | 4919 | mutex_lock(&il->mutex); |
be663ab6 | 4920 | |
46bc8d4b | 4921 | if (!ctx->vif || !il_is_ready_rf(il)) { |
ffd8c746 JB |
4922 | /* |
4923 | * Huh? But wait ... this can maybe happen when | |
4924 | * we're in the middle of a firmware restart! | |
4925 | */ | |
4926 | err = -EBUSY; | |
4927 | goto out; | |
4928 | } | |
4929 | ||
17d6e557 SG |
4930 | modes = ctx->interface_modes | ctx->exclusive_interface_modes; |
4931 | if (!(modes & BIT(newtype))) { | |
4932 | err = -EOPNOTSUPP; | |
be663ab6 WYG |
4933 | goto out; |
4934 | } | |
4935 | ||
17d6e557 SG |
4936 | if ((il->ctx.exclusive_interface_modes & BIT(il->ctx.vif->type)) || |
4937 | (il->ctx.exclusive_interface_modes & BIT(newtype))) { | |
4938 | err = -EINVAL; | |
4939 | goto out; | |
be663ab6 WYG |
4940 | } |
4941 | ||
4942 | /* success */ | |
46bc8d4b | 4943 | il_teardown_interface(il, vif, true); |
be663ab6 | 4944 | vif->type = newtype; |
ffd8c746 | 4945 | vif->p2p = newp2p; |
46bc8d4b | 4946 | err = il_setup_interface(il, ctx); |
be663ab6 WYG |
4947 | WARN_ON(err); |
4948 | /* | |
4949 | * We've switched internally, but submitting to the | |
4950 | * device may have failed for some reason. Mask this | |
4951 | * error, because otherwise mac80211 will not switch | |
4952 | * (and set the interface type back) and we'll be | |
4953 | * out of sync with it. | |
4954 | */ | |
4955 | err = 0; | |
4956 | ||
e7392364 | 4957 | out: |
46bc8d4b | 4958 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
4959 | return err; |
4960 | } | |
e7392364 | 4961 | |
e2ebc833 | 4962 | EXPORT_SYMBOL(il_mac_change_interface); |
be663ab6 WYG |
4963 | |
4964 | /* | |
4965 | * On every watchdog tick we check (latest) time stamp. If it does not | |
4966 | * change during timeout period and queue is not empty we reset firmware. | |
4967 | */ | |
e7392364 SG |
4968 | static int |
4969 | il_check_stuck_queue(struct il_priv *il, int cnt) | |
be663ab6 | 4970 | { |
46bc8d4b | 4971 | struct il_tx_queue *txq = &il->txq[cnt]; |
e2ebc833 | 4972 | struct il_queue *q = &txq->q; |
be663ab6 WYG |
4973 | unsigned long timeout; |
4974 | int ret; | |
4975 | ||
4976 | if (q->read_ptr == q->write_ptr) { | |
4977 | txq->time_stamp = jiffies; | |
4978 | return 0; | |
4979 | } | |
4980 | ||
e7392364 SG |
4981 | timeout = |
4982 | txq->time_stamp + | |
4983 | msecs_to_jiffies(il->cfg->base_params->wd_timeout); | |
be663ab6 WYG |
4984 | |
4985 | if (time_after(jiffies, timeout)) { | |
e7392364 SG |
4986 | IL_ERR("Queue %d stuck for %u ms.\n", q->id, |
4987 | il->cfg->base_params->wd_timeout); | |
46bc8d4b | 4988 | ret = il_force_reset(il, false); |
be663ab6 WYG |
4989 | return (ret == -EAGAIN) ? 0 : 1; |
4990 | } | |
4991 | ||
4992 | return 0; | |
4993 | } | |
4994 | ||
4995 | /* | |
4996 | * Making watchdog tick be a quarter of timeout assure we will | |
4997 | * discover the queue hung between timeout and 1.25*timeout | |
4998 | */ | |
e2ebc833 | 4999 | #define IL_WD_TICK(timeout) ((timeout) / 4) |
be663ab6 WYG |
5000 | |
5001 | /* | |
5002 | * Watchdog timer callback, we check each tx queue for stuck, if if hung | |
5003 | * we reset the firmware. If everything is fine just rearm the timer. | |
5004 | */ | |
e7392364 SG |
5005 | void |
5006 | il_bg_watchdog(unsigned long data) | |
be663ab6 | 5007 | { |
46bc8d4b | 5008 | struct il_priv *il = (struct il_priv *)data; |
be663ab6 WYG |
5009 | int cnt; |
5010 | unsigned long timeout; | |
5011 | ||
a6766ccd | 5012 | if (test_bit(S_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
5013 | return; |
5014 | ||
46bc8d4b | 5015 | timeout = il->cfg->base_params->wd_timeout; |
be663ab6 WYG |
5016 | if (timeout == 0) |
5017 | return; | |
5018 | ||
5019 | /* monitor and check for stuck cmd queue */ | |
46bc8d4b | 5020 | if (il_check_stuck_queue(il, il->cmd_queue)) |
be663ab6 WYG |
5021 | return; |
5022 | ||
5023 | /* monitor and check for other stuck queues */ | |
46bc8d4b SG |
5024 | if (il_is_any_associated(il)) { |
5025 | for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) { | |
be663ab6 | 5026 | /* skip as we already checked the command queue */ |
46bc8d4b | 5027 | if (cnt == il->cmd_queue) |
be663ab6 | 5028 | continue; |
46bc8d4b | 5029 | if (il_check_stuck_queue(il, cnt)) |
be663ab6 WYG |
5030 | return; |
5031 | } | |
5032 | } | |
5033 | ||
e7392364 SG |
5034 | mod_timer(&il->watchdog, |
5035 | jiffies + msecs_to_jiffies(IL_WD_TICK(timeout))); | |
be663ab6 | 5036 | } |
e7392364 | 5037 | |
e2ebc833 | 5038 | EXPORT_SYMBOL(il_bg_watchdog); |
be663ab6 | 5039 | |
e7392364 SG |
5040 | void |
5041 | il_setup_watchdog(struct il_priv *il) | |
be663ab6 | 5042 | { |
46bc8d4b | 5043 | unsigned int timeout = il->cfg->base_params->wd_timeout; |
be663ab6 WYG |
5044 | |
5045 | if (timeout) | |
46bc8d4b | 5046 | mod_timer(&il->watchdog, |
e2ebc833 | 5047 | jiffies + msecs_to_jiffies(IL_WD_TICK(timeout))); |
be663ab6 | 5048 | else |
46bc8d4b | 5049 | del_timer(&il->watchdog); |
be663ab6 | 5050 | } |
e7392364 | 5051 | |
e2ebc833 | 5052 | EXPORT_SYMBOL(il_setup_watchdog); |
be663ab6 WYG |
5053 | |
5054 | /* | |
5055 | * extended beacon time format | |
5056 | * time in usec will be changed into a 32-bit value in extended:internal format | |
5057 | * the extended part is the beacon counts | |
5058 | * the internal part is the time in usec within one beacon interval | |
5059 | */ | |
5060 | u32 | |
e7392364 | 5061 | il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval) |
be663ab6 WYG |
5062 | { |
5063 | u32 quot; | |
5064 | u32 rem; | |
5065 | u32 interval = beacon_interval * TIME_UNIT; | |
5066 | ||
5067 | if (!interval || !usec) | |
5068 | return 0; | |
5069 | ||
e7392364 SG |
5070 | quot = |
5071 | (usec / | |
5072 | interval) & (il_beacon_time_mask_high(il, | |
5073 | il->hw_params. | |
5074 | beacon_time_tsf_bits) >> il-> | |
5075 | hw_params.beacon_time_tsf_bits); | |
5076 | rem = | |
5077 | (usec % interval) & il_beacon_time_mask_low(il, | |
5078 | il->hw_params. | |
5079 | beacon_time_tsf_bits); | |
be663ab6 | 5080 | |
46bc8d4b | 5081 | return (quot << il->hw_params.beacon_time_tsf_bits) + rem; |
be663ab6 | 5082 | } |
e7392364 | 5083 | |
e2ebc833 | 5084 | EXPORT_SYMBOL(il_usecs_to_beacons); |
be663ab6 WYG |
5085 | |
5086 | /* base is usually what we get from ucode with each received frame, | |
5087 | * the same as HW timer counter counting down | |
5088 | */ | |
e7392364 SG |
5089 | __le32 |
5090 | il_add_beacon_time(struct il_priv * il, u32 base, u32 addon, | |
5091 | u32 beacon_interval) | |
be663ab6 | 5092 | { |
46bc8d4b | 5093 | u32 base_low = base & il_beacon_time_mask_low(il, |
e7392364 SG |
5094 | il->hw_params. |
5095 | beacon_time_tsf_bits); | |
46bc8d4b | 5096 | u32 addon_low = addon & il_beacon_time_mask_low(il, |
e7392364 SG |
5097 | il->hw_params. |
5098 | beacon_time_tsf_bits); | |
be663ab6 | 5099 | u32 interval = beacon_interval * TIME_UNIT; |
46bc8d4b | 5100 | u32 res = (base & il_beacon_time_mask_high(il, |
e7392364 SG |
5101 | il->hw_params. |
5102 | beacon_time_tsf_bits)) + | |
5103 | (addon & il_beacon_time_mask_high(il, | |
5104 | il->hw_params. | |
5105 | beacon_time_tsf_bits)); | |
be663ab6 WYG |
5106 | |
5107 | if (base_low > addon_low) | |
5108 | res += base_low - addon_low; | |
5109 | else if (base_low < addon_low) { | |
5110 | res += interval + base_low - addon_low; | |
46bc8d4b | 5111 | res += (1 << il->hw_params.beacon_time_tsf_bits); |
be663ab6 | 5112 | } else |
46bc8d4b | 5113 | res += (1 << il->hw_params.beacon_time_tsf_bits); |
be663ab6 WYG |
5114 | |
5115 | return cpu_to_le32(res); | |
5116 | } | |
e7392364 | 5117 | |
e2ebc833 | 5118 | EXPORT_SYMBOL(il_add_beacon_time); |
be663ab6 WYG |
5119 | |
5120 | #ifdef CONFIG_PM | |
5121 | ||
e7392364 SG |
5122 | int |
5123 | il_pci_suspend(struct device *device) | |
be663ab6 WYG |
5124 | { |
5125 | struct pci_dev *pdev = to_pci_dev(device); | |
46bc8d4b | 5126 | struct il_priv *il = pci_get_drvdata(pdev); |
be663ab6 WYG |
5127 | |
5128 | /* | |
5129 | * This function is called when system goes into suspend state | |
e2ebc833 SG |
5130 | * mac80211 will call il_mac_stop() from the mac80211 suspend function |
5131 | * first but since il_mac_stop() has no knowledge of who the caller is, | |
be663ab6 WYG |
5132 | * it will not call apm_ops.stop() to stop the DMA operation. |
5133 | * Calling apm_ops.stop here to make sure we stop the DMA. | |
5134 | */ | |
46bc8d4b | 5135 | il_apm_stop(il); |
be663ab6 WYG |
5136 | |
5137 | return 0; | |
5138 | } | |
e7392364 | 5139 | |
e2ebc833 | 5140 | EXPORT_SYMBOL(il_pci_suspend); |
be663ab6 | 5141 | |
e7392364 SG |
5142 | int |
5143 | il_pci_resume(struct device *device) | |
be663ab6 WYG |
5144 | { |
5145 | struct pci_dev *pdev = to_pci_dev(device); | |
46bc8d4b | 5146 | struct il_priv *il = pci_get_drvdata(pdev); |
be663ab6 WYG |
5147 | bool hw_rfkill = false; |
5148 | ||
5149 | /* | |
5150 | * We disable the RETRY_TIMEOUT register (0x41) to keep | |
5151 | * PCI Tx retries from interfering with C3 CPU state. | |
5152 | */ | |
5153 | pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); | |
5154 | ||
46bc8d4b | 5155 | il_enable_interrupts(il); |
be663ab6 | 5156 | |
e7392364 | 5157 | if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) |
be663ab6 WYG |
5158 | hw_rfkill = true; |
5159 | ||
5160 | if (hw_rfkill) | |
a6766ccd | 5161 | set_bit(S_RF_KILL_HW, &il->status); |
be663ab6 | 5162 | else |
a6766ccd | 5163 | clear_bit(S_RF_KILL_HW, &il->status); |
be663ab6 | 5164 | |
46bc8d4b | 5165 | wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill); |
be663ab6 WYG |
5166 | |
5167 | return 0; | |
5168 | } | |
e7392364 | 5169 | |
e2ebc833 | 5170 | EXPORT_SYMBOL(il_pci_resume); |
be663ab6 | 5171 | |
e2ebc833 SG |
5172 | const struct dev_pm_ops il_pm_ops = { |
5173 | .suspend = il_pci_suspend, | |
5174 | .resume = il_pci_resume, | |
5175 | .freeze = il_pci_suspend, | |
5176 | .thaw = il_pci_resume, | |
5177 | .poweroff = il_pci_suspend, | |
5178 | .restore = il_pci_resume, | |
be663ab6 | 5179 | }; |
e7392364 | 5180 | |
e2ebc833 | 5181 | EXPORT_SYMBOL(il_pm_ops); |
be663ab6 WYG |
5182 | |
5183 | #endif /* CONFIG_PM */ | |
5184 | ||
5185 | static void | |
46bc8d4b | 5186 | il_update_qos(struct il_priv *il, struct il_rxon_context *ctx) |
be663ab6 | 5187 | { |
a6766ccd | 5188 | if (test_bit(S_EXIT_PENDING, &il->status)) |
be663ab6 WYG |
5189 | return; |
5190 | ||
5191 | if (!ctx->is_active) | |
5192 | return; | |
5193 | ||
5194 | ctx->qos_data.def_qos_parm.qos_flags = 0; | |
5195 | ||
5196 | if (ctx->qos_data.qos_active) | |
5197 | ctx->qos_data.def_qos_parm.qos_flags |= | |
e7392364 | 5198 | QOS_PARAM_FLG_UPDATE_EDCA_MSK; |
be663ab6 WYG |
5199 | |
5200 | if (ctx->ht.enabled) | |
5201 | ctx->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK; | |
5202 | ||
58de00a4 | 5203 | D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n", |
e7392364 | 5204 | ctx->qos_data.qos_active, ctx->qos_data.def_qos_parm.qos_flags); |
be663ab6 | 5205 | |
e7392364 SG |
5206 | il_send_cmd_pdu_async(il, ctx->qos_cmd, sizeof(struct il_qosparam_cmd), |
5207 | &ctx->qos_data.def_qos_parm, NULL); | |
be663ab6 WYG |
5208 | } |
5209 | ||
5210 | /** | |
e2ebc833 | 5211 | * il_mac_config - mac80211 config callback |
be663ab6 | 5212 | */ |
e7392364 SG |
5213 | int |
5214 | il_mac_config(struct ieee80211_hw *hw, u32 changed) | |
be663ab6 | 5215 | { |
46bc8d4b | 5216 | struct il_priv *il = hw->priv; |
e2ebc833 | 5217 | const struct il_channel_info *ch_info; |
be663ab6 WYG |
5218 | struct ieee80211_conf *conf = &hw->conf; |
5219 | struct ieee80211_channel *channel = conf->channel; | |
46bc8d4b | 5220 | struct il_ht_config *ht_conf = &il->current_ht_config; |
17d6e557 | 5221 | struct il_rxon_context *ctx = &il->ctx; |
be663ab6 WYG |
5222 | unsigned long flags = 0; |
5223 | int ret = 0; | |
5224 | u16 ch; | |
5225 | int scan_active = 0; | |
7c2cde2e | 5226 | bool ht_changed = false; |
be663ab6 | 5227 | |
46bc8d4b | 5228 | if (WARN_ON(!il->cfg->ops->legacy)) |
be663ab6 WYG |
5229 | return -EOPNOTSUPP; |
5230 | ||
46bc8d4b | 5231 | mutex_lock(&il->mutex); |
be663ab6 | 5232 | |
e7392364 SG |
5233 | D_MAC80211("enter to channel %d changed 0x%X\n", channel->hw_value, |
5234 | changed); | |
be663ab6 | 5235 | |
a6766ccd | 5236 | if (unlikely(test_bit(S_SCANNING, &il->status))) { |
be663ab6 | 5237 | scan_active = 1; |
58de00a4 | 5238 | D_MAC80211("scan active\n"); |
be663ab6 WYG |
5239 | } |
5240 | ||
e7392364 SG |
5241 | if (changed & |
5242 | (IEEE80211_CONF_CHANGE_SMPS | IEEE80211_CONF_CHANGE_CHANNEL)) { | |
be663ab6 | 5243 | /* mac80211 uses static for non-HT which is what we want */ |
46bc8d4b | 5244 | il->current_ht_config.smps = conf->smps_mode; |
be663ab6 WYG |
5245 | |
5246 | /* | |
5247 | * Recalculate chain counts. | |
5248 | * | |
5249 | * If monitor mode is enabled then mac80211 will | |
5250 | * set up the SM PS mode to OFF if an HT channel is | |
5251 | * configured. | |
5252 | */ | |
46bc8d4b | 5253 | if (il->cfg->ops->hcmd->set_rxon_chain) |
17d6e557 | 5254 | il->cfg->ops->hcmd->set_rxon_chain(il, &il->ctx); |
be663ab6 WYG |
5255 | } |
5256 | ||
5257 | /* during scanning mac80211 will delay channel setting until | |
5258 | * scan finish with changed = 0 | |
5259 | */ | |
5260 | if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) { | |
17d6e557 | 5261 | |
be663ab6 WYG |
5262 | if (scan_active) |
5263 | goto set_ch_out; | |
5264 | ||
5265 | ch = channel->hw_value; | |
46bc8d4b | 5266 | ch_info = il_get_channel_info(il, channel->band, ch); |
e2ebc833 | 5267 | if (!il_is_channel_valid(ch_info)) { |
58de00a4 | 5268 | D_MAC80211("leave - invalid channel\n"); |
be663ab6 WYG |
5269 | ret = -EINVAL; |
5270 | goto set_ch_out; | |
5271 | } | |
5272 | ||
46bc8d4b | 5273 | if (il->iw_mode == NL80211_IFTYPE_ADHOC && |
e2ebc833 | 5274 | !il_is_channel_ibss(ch_info)) { |
58de00a4 | 5275 | D_MAC80211("leave - not IBSS channel\n"); |
eb85de3f SG |
5276 | ret = -EINVAL; |
5277 | goto set_ch_out; | |
5278 | } | |
5279 | ||
46bc8d4b | 5280 | spin_lock_irqsave(&il->lock, flags); |
be663ab6 | 5281 | |
17d6e557 SG |
5282 | /* Configure HT40 channels */ |
5283 | if (ctx->ht.enabled != conf_is_ht(conf)) { | |
5284 | ctx->ht.enabled = conf_is_ht(conf); | |
5285 | ht_changed = true; | |
5286 | } | |
5287 | if (ctx->ht.enabled) { | |
5288 | if (conf_is_ht40_minus(conf)) { | |
5289 | ctx->ht.extension_chan_offset = | |
e7392364 | 5290 | IEEE80211_HT_PARAM_CHA_SEC_BELOW; |
17d6e557 SG |
5291 | ctx->ht.is_40mhz = true; |
5292 | } else if (conf_is_ht40_plus(conf)) { | |
5293 | ctx->ht.extension_chan_offset = | |
e7392364 | 5294 | IEEE80211_HT_PARAM_CHA_SEC_ABOVE; |
17d6e557 SG |
5295 | ctx->ht.is_40mhz = true; |
5296 | } else { | |
5297 | ctx->ht.extension_chan_offset = | |
e7392364 | 5298 | IEEE80211_HT_PARAM_CHA_SEC_NONE; |
be663ab6 | 5299 | ctx->ht.is_40mhz = false; |
17d6e557 SG |
5300 | } |
5301 | } else | |
5302 | ctx->ht.is_40mhz = false; | |
be663ab6 | 5303 | |
17d6e557 SG |
5304 | /* |
5305 | * Default to no protection. Protection mode will | |
5306 | * later be set from BSS config in il_ht_conf | |
5307 | */ | |
e7392364 | 5308 | ctx->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE; |
be663ab6 | 5309 | |
17d6e557 SG |
5310 | /* if we are switching from ht to 2.4 clear flags |
5311 | * from any ht related info since 2.4 does not | |
5312 | * support ht */ | |
5313 | if ((le16_to_cpu(ctx->staging.channel) != ch)) | |
5314 | ctx->staging.flags = 0; | |
be663ab6 | 5315 | |
17d6e557 SG |
5316 | il_set_rxon_channel(il, channel, ctx); |
5317 | il_set_rxon_ht(il, ht_conf); | |
be663ab6 | 5318 | |
e7392364 | 5319 | il_set_flags_for_band(il, ctx, channel->band, ctx->vif); |
be663ab6 | 5320 | |
46bc8d4b | 5321 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 | 5322 | |
46bc8d4b | 5323 | if (il->cfg->ops->legacy->update_bcast_stations) |
e7392364 | 5324 | ret = il->cfg->ops->legacy->update_bcast_stations(il); |
be663ab6 | 5325 | |
e7392364 | 5326 | set_ch_out: |
be663ab6 WYG |
5327 | /* The list of supported rates and rate mask can be different |
5328 | * for each band; since the band may have changed, reset | |
5329 | * the rate mask to what mac80211 lists */ | |
46bc8d4b | 5330 | il_set_rate(il); |
be663ab6 WYG |
5331 | } |
5332 | ||
e7392364 | 5333 | if (changed & (IEEE80211_CONF_CHANGE_PS | IEEE80211_CONF_CHANGE_IDLE)) { |
46bc8d4b | 5334 | ret = il_power_update_mode(il, false); |
be663ab6 | 5335 | if (ret) |
58de00a4 | 5336 | D_MAC80211("Error setting sleep level\n"); |
be663ab6 WYG |
5337 | } |
5338 | ||
5339 | if (changed & IEEE80211_CONF_CHANGE_POWER) { | |
e7392364 SG |
5340 | D_MAC80211("TX Power old=%d new=%d\n", il->tx_power_user_lmt, |
5341 | conf->power_level); | |
be663ab6 | 5342 | |
46bc8d4b | 5343 | il_set_tx_power(il, conf->power_level, false); |
be663ab6 WYG |
5344 | } |
5345 | ||
46bc8d4b | 5346 | if (!il_is_ready(il)) { |
58de00a4 | 5347 | D_MAC80211("leave - not ready\n"); |
be663ab6 WYG |
5348 | goto out; |
5349 | } | |
5350 | ||
5351 | if (scan_active) | |
5352 | goto out; | |
5353 | ||
17d6e557 SG |
5354 | if (memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging))) |
5355 | il_commit_rxon(il, ctx); | |
5356 | else | |
5357 | D_INFO("Not re-sending same RXON configuration.\n"); | |
5358 | if (ht_changed) | |
5359 | il_update_qos(il, ctx); | |
be663ab6 WYG |
5360 | |
5361 | out: | |
58de00a4 | 5362 | D_MAC80211("leave\n"); |
46bc8d4b | 5363 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
5364 | return ret; |
5365 | } | |
e2ebc833 | 5366 | EXPORT_SYMBOL(il_mac_config); |
be663ab6 | 5367 | |
e7392364 SG |
5368 | void |
5369 | il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif) | |
be663ab6 | 5370 | { |
46bc8d4b | 5371 | struct il_priv *il = hw->priv; |
be663ab6 | 5372 | unsigned long flags; |
7c2cde2e | 5373 | struct il_rxon_context *ctx = &il->ctx; |
be663ab6 | 5374 | |
46bc8d4b | 5375 | if (WARN_ON(!il->cfg->ops->legacy)) |
be663ab6 WYG |
5376 | return; |
5377 | ||
46bc8d4b | 5378 | mutex_lock(&il->mutex); |
58de00a4 | 5379 | D_MAC80211("enter\n"); |
be663ab6 | 5380 | |
46bc8d4b SG |
5381 | spin_lock_irqsave(&il->lock, flags); |
5382 | memset(&il->current_ht_config, 0, sizeof(struct il_ht_config)); | |
5383 | spin_unlock_irqrestore(&il->lock, flags); | |
be663ab6 | 5384 | |
46bc8d4b | 5385 | spin_lock_irqsave(&il->lock, flags); |
be663ab6 WYG |
5386 | |
5387 | /* new association get rid of ibss beacon skb */ | |
46bc8d4b SG |
5388 | if (il->beacon_skb) |
5389 | dev_kfree_skb(il->beacon_skb); | |
be663ab6 | 5390 | |
46bc8d4b | 5391 | il->beacon_skb = NULL; |
be663ab6 | 5392 | |
46bc8d4b | 5393 | il->timestamp = 0; |
be663ab6 | 5394 | |
46bc8d4b | 5395 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 | 5396 | |
46bc8d4b SG |
5397 | il_scan_cancel_timeout(il, 100); |
5398 | if (!il_is_ready_rf(il)) { | |
58de00a4 | 5399 | D_MAC80211("leave - not ready\n"); |
46bc8d4b | 5400 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
5401 | return; |
5402 | } | |
5403 | ||
5404 | /* we are restarting association process | |
5405 | * clear RXON_FILTER_ASSOC_MSK bit | |
5406 | */ | |
5407 | ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
46bc8d4b | 5408 | il_commit_rxon(il, ctx); |
be663ab6 | 5409 | |
46bc8d4b | 5410 | il_set_rate(il); |
be663ab6 | 5411 | |
46bc8d4b | 5412 | mutex_unlock(&il->mutex); |
be663ab6 | 5413 | |
58de00a4 | 5414 | D_MAC80211("leave\n"); |
be663ab6 | 5415 | } |
e7392364 | 5416 | |
e2ebc833 | 5417 | EXPORT_SYMBOL(il_mac_reset_tsf); |
be663ab6 | 5418 | |
e7392364 SG |
5419 | static void |
5420 | il_ht_conf(struct il_priv *il, struct ieee80211_vif *vif) | |
be663ab6 | 5421 | { |
46bc8d4b | 5422 | struct il_ht_config *ht_conf = &il->current_ht_config; |
be663ab6 WYG |
5423 | struct ieee80211_sta *sta; |
5424 | struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; | |
e2ebc833 | 5425 | struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif); |
be663ab6 | 5426 | |
58de00a4 | 5427 | D_ASSOC("enter:\n"); |
be663ab6 WYG |
5428 | |
5429 | if (!ctx->ht.enabled) | |
5430 | return; | |
5431 | ||
5432 | ctx->ht.protection = | |
e7392364 | 5433 | bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION; |
be663ab6 | 5434 | ctx->ht.non_gf_sta_present = |
e7392364 SG |
5435 | !!(bss_conf-> |
5436 | ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); | |
be663ab6 WYG |
5437 | |
5438 | ht_conf->single_chain_sufficient = false; | |
5439 | ||
5440 | switch (vif->type) { | |
5441 | case NL80211_IFTYPE_STATION: | |
5442 | rcu_read_lock(); | |
5443 | sta = ieee80211_find_sta(vif, bss_conf->bssid); | |
5444 | if (sta) { | |
5445 | struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap; | |
5446 | int maxstreams; | |
5447 | ||
e7392364 SG |
5448 | maxstreams = |
5449 | (ht_cap->mcs. | |
5450 | tx_params & IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK) | |
5451 | >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; | |
be663ab6 WYG |
5452 | maxstreams += 1; |
5453 | ||
232913b5 SG |
5454 | if (ht_cap->mcs.rx_mask[1] == 0 && |
5455 | ht_cap->mcs.rx_mask[2] == 0) | |
be663ab6 WYG |
5456 | ht_conf->single_chain_sufficient = true; |
5457 | if (maxstreams <= 1) | |
5458 | ht_conf->single_chain_sufficient = true; | |
5459 | } else { | |
5460 | /* | |
5461 | * If at all, this can only happen through a race | |
5462 | * when the AP disconnects us while we're still | |
5463 | * setting up the connection, in that case mac80211 | |
5464 | * will soon tell us about that. | |
5465 | */ | |
5466 | ht_conf->single_chain_sufficient = true; | |
5467 | } | |
5468 | rcu_read_unlock(); | |
5469 | break; | |
5470 | case NL80211_IFTYPE_ADHOC: | |
5471 | ht_conf->single_chain_sufficient = true; | |
5472 | break; | |
5473 | default: | |
5474 | break; | |
5475 | } | |
5476 | ||
58de00a4 | 5477 | D_ASSOC("leave\n"); |
be663ab6 WYG |
5478 | } |
5479 | ||
e7392364 SG |
5480 | static inline void |
5481 | il_set_no_assoc(struct il_priv *il, struct ieee80211_vif *vif) | |
be663ab6 | 5482 | { |
e2ebc833 | 5483 | struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif); |
be663ab6 WYG |
5484 | |
5485 | /* | |
5486 | * inform the ucode that there is no longer an | |
5487 | * association and that no more packets should be | |
5488 | * sent | |
5489 | */ | |
5490 | ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; | |
5491 | ctx->staging.assoc_id = 0; | |
46bc8d4b | 5492 | il_commit_rxon(il, ctx); |
be663ab6 WYG |
5493 | } |
5494 | ||
e7392364 SG |
5495 | static void |
5496 | il_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) | |
be663ab6 | 5497 | { |
46bc8d4b | 5498 | struct il_priv *il = hw->priv; |
be663ab6 WYG |
5499 | unsigned long flags; |
5500 | __le64 timestamp; | |
5501 | struct sk_buff *skb = ieee80211_beacon_get(hw, vif); | |
5502 | ||
5503 | if (!skb) | |
5504 | return; | |
5505 | ||
58de00a4 | 5506 | D_MAC80211("enter\n"); |
be663ab6 | 5507 | |
46bc8d4b | 5508 | lockdep_assert_held(&il->mutex); |
be663ab6 | 5509 | |
46bc8d4b | 5510 | if (!il->beacon_ctx) { |
9406f797 | 5511 | IL_ERR("update beacon but no beacon context!\n"); |
be663ab6 WYG |
5512 | dev_kfree_skb(skb); |
5513 | return; | |
5514 | } | |
5515 | ||
46bc8d4b | 5516 | spin_lock_irqsave(&il->lock, flags); |
be663ab6 | 5517 | |
46bc8d4b SG |
5518 | if (il->beacon_skb) |
5519 | dev_kfree_skb(il->beacon_skb); | |
be663ab6 | 5520 | |
46bc8d4b | 5521 | il->beacon_skb = skb; |
be663ab6 WYG |
5522 | |
5523 | timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp; | |
46bc8d4b | 5524 | il->timestamp = le64_to_cpu(timestamp); |
be663ab6 | 5525 | |
58de00a4 | 5526 | D_MAC80211("leave\n"); |
46bc8d4b | 5527 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 | 5528 | |
46bc8d4b | 5529 | if (!il_is_ready_rf(il)) { |
58de00a4 | 5530 | D_MAC80211("leave - RF not ready\n"); |
be663ab6 WYG |
5531 | return; |
5532 | } | |
5533 | ||
46bc8d4b | 5534 | il->cfg->ops->legacy->post_associate(il); |
be663ab6 WYG |
5535 | } |
5536 | ||
e7392364 SG |
5537 | void |
5538 | il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
5539 | struct ieee80211_bss_conf *bss_conf, u32 changes) | |
be663ab6 | 5540 | { |
46bc8d4b | 5541 | struct il_priv *il = hw->priv; |
e2ebc833 | 5542 | struct il_rxon_context *ctx = il_rxon_ctx_from_vif(vif); |
be663ab6 WYG |
5543 | int ret; |
5544 | ||
46bc8d4b | 5545 | if (WARN_ON(!il->cfg->ops->legacy)) |
be663ab6 WYG |
5546 | return; |
5547 | ||
58de00a4 | 5548 | D_MAC80211("changes = 0x%X\n", changes); |
be663ab6 | 5549 | |
46bc8d4b | 5550 | mutex_lock(&il->mutex); |
be663ab6 | 5551 | |
46bc8d4b SG |
5552 | if (!il_is_alive(il)) { |
5553 | mutex_unlock(&il->mutex); | |
28a6e577 SG |
5554 | return; |
5555 | } | |
5556 | ||
be663ab6 WYG |
5557 | if (changes & BSS_CHANGED_QOS) { |
5558 | unsigned long flags; | |
5559 | ||
46bc8d4b | 5560 | spin_lock_irqsave(&il->lock, flags); |
be663ab6 | 5561 | ctx->qos_data.qos_active = bss_conf->qos; |
46bc8d4b SG |
5562 | il_update_qos(il, ctx); |
5563 | spin_unlock_irqrestore(&il->lock, flags); | |
be663ab6 WYG |
5564 | } |
5565 | ||
5566 | if (changes & BSS_CHANGED_BEACON_ENABLED) { | |
5567 | /* | |
5568 | * the add_interface code must make sure we only ever | |
5569 | * have a single interface that could be beaconing at | |
5570 | * any time. | |
5571 | */ | |
5572 | if (vif->bss_conf.enable_beacon) | |
46bc8d4b | 5573 | il->beacon_ctx = ctx; |
be663ab6 | 5574 | else |
46bc8d4b | 5575 | il->beacon_ctx = NULL; |
be663ab6 WYG |
5576 | } |
5577 | ||
5578 | if (changes & BSS_CHANGED_BSSID) { | |
58de00a4 | 5579 | D_MAC80211("BSSID %pM\n", bss_conf->bssid); |
be663ab6 WYG |
5580 | |
5581 | /* | |
5582 | * If there is currently a HW scan going on in the | |
5583 | * background then we need to cancel it else the RXON | |
5584 | * below/in post_associate will fail. | |
5585 | */ | |
46bc8d4b | 5586 | if (il_scan_cancel_timeout(il, 100)) { |
e7392364 SG |
5587 | IL_WARN("Aborted scan still in progress after 100ms\n"); |
5588 | D_MAC80211("leaving - scan abort failed.\n"); | |
46bc8d4b | 5589 | mutex_unlock(&il->mutex); |
be663ab6 WYG |
5590 | return; |
5591 | } | |
5592 | ||
5593 | /* mac80211 only sets assoc when in STATION mode */ | |
5594 | if (vif->type == NL80211_IFTYPE_ADHOC || bss_conf->assoc) { | |
e7392364 SG |
5595 | memcpy(ctx->staging.bssid_addr, bss_conf->bssid, |
5596 | ETH_ALEN); | |
be663ab6 WYG |
5597 | |
5598 | /* currently needed in a few places */ | |
46bc8d4b | 5599 | memcpy(il->bssid, bss_conf->bssid, ETH_ALEN); |
be663ab6 | 5600 | } else { |
e7392364 | 5601 | ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK; |
be663ab6 WYG |
5602 | } |
5603 | ||
5604 | } | |
5605 | ||
5606 | /* | |
5607 | * This needs to be after setting the BSSID in case | |
5608 | * mac80211 decides to do both changes at once because | |
5609 | * it will invoke post_associate. | |
5610 | */ | |
232913b5 | 5611 | if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON)) |
e2ebc833 | 5612 | il_beacon_update(hw, vif); |
be663ab6 WYG |
5613 | |
5614 | if (changes & BSS_CHANGED_ERP_PREAMBLE) { | |
e7392364 | 5615 | D_MAC80211("ERP_PREAMBLE %d\n", bss_conf->use_short_preamble); |
be663ab6 WYG |
5616 | if (bss_conf->use_short_preamble) |
5617 | ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK; | |
5618 | else | |
5619 | ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK; | |
5620 | } | |
5621 | ||
5622 | if (changes & BSS_CHANGED_ERP_CTS_PROT) { | |
e7392364 | 5623 | D_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot); |
232913b5 | 5624 | if (bss_conf->use_cts_prot && il->band != IEEE80211_BAND_5GHZ) |
be663ab6 WYG |
5625 | ctx->staging.flags |= RXON_FLG_TGG_PROTECT_MSK; |
5626 | else | |
5627 | ctx->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK; | |
5628 | if (bss_conf->use_cts_prot) | |
5629 | ctx->staging.flags |= RXON_FLG_SELF_CTS_EN; | |
5630 | else | |
5631 | ctx->staging.flags &= ~RXON_FLG_SELF_CTS_EN; | |
5632 | } | |
5633 | ||
5634 | if (changes & BSS_CHANGED_BASIC_RATES) { | |
5635 | /* XXX use this information | |
5636 | * | |
e2ebc833 | 5637 | * To do that, remove code from il_set_rate() and put something |
be663ab6 WYG |
5638 | * like this here: |
5639 | * | |
e7392364 SG |
5640 | if (A-band) |
5641 | ctx->staging.ofdm_basic_rates = | |
5642 | bss_conf->basic_rates; | |
5643 | else | |
5644 | ctx->staging.ofdm_basic_rates = | |
5645 | bss_conf->basic_rates >> 4; | |
5646 | ctx->staging.cck_basic_rates = | |
5647 | bss_conf->basic_rates & 0xF; | |
be663ab6 WYG |
5648 | */ |
5649 | } | |
5650 | ||
5651 | if (changes & BSS_CHANGED_HT) { | |
46bc8d4b | 5652 | il_ht_conf(il, vif); |
be663ab6 | 5653 | |
46bc8d4b SG |
5654 | if (il->cfg->ops->hcmd->set_rxon_chain) |
5655 | il->cfg->ops->hcmd->set_rxon_chain(il, ctx); | |
be663ab6 WYG |
5656 | } |
5657 | ||
5658 | if (changes & BSS_CHANGED_ASSOC) { | |
58de00a4 | 5659 | D_MAC80211("ASSOC %d\n", bss_conf->assoc); |
be663ab6 | 5660 | if (bss_conf->assoc) { |
46bc8d4b | 5661 | il->timestamp = bss_conf->timestamp; |
be663ab6 | 5662 | |
46bc8d4b SG |
5663 | if (!il_is_rfkill(il)) |
5664 | il->cfg->ops->legacy->post_associate(il); | |
be663ab6 | 5665 | } else |
46bc8d4b | 5666 | il_set_no_assoc(il, vif); |
be663ab6 WYG |
5667 | } |
5668 | ||
e2ebc833 | 5669 | if (changes && il_is_associated_ctx(ctx) && bss_conf->aid) { |
e7392364 | 5670 | D_MAC80211("Changes (%#x) while associated\n", changes); |
46bc8d4b | 5671 | ret = il_send_rxon_assoc(il, ctx); |
be663ab6 WYG |
5672 | if (!ret) { |
5673 | /* Sync active_rxon with latest change. */ | |
e7392364 SG |
5674 | memcpy((void *)&ctx->active, &ctx->staging, |
5675 | sizeof(struct il_rxon_cmd)); | |
be663ab6 WYG |
5676 | } |
5677 | } | |
5678 | ||
5679 | if (changes & BSS_CHANGED_BEACON_ENABLED) { | |
5680 | if (vif->bss_conf.enable_beacon) { | |
e7392364 SG |
5681 | memcpy(ctx->staging.bssid_addr, bss_conf->bssid, |
5682 | ETH_ALEN); | |
46bc8d4b SG |
5683 | memcpy(il->bssid, bss_conf->bssid, ETH_ALEN); |
5684 | il->cfg->ops->legacy->config_ap(il); | |
be663ab6 | 5685 | } else |
46bc8d4b | 5686 | il_set_no_assoc(il, vif); |
be663ab6 WYG |
5687 | } |
5688 | ||
5689 | if (changes & BSS_CHANGED_IBSS) { | |
e7392364 SG |
5690 | ret = |
5691 | il->cfg->ops->legacy->manage_ibss_station(il, vif, | |
5692 | bss_conf-> | |
5693 | ibss_joined); | |
be663ab6 | 5694 | if (ret) |
9406f797 | 5695 | IL_ERR("failed to %s IBSS station %pM\n", |
e7392364 SG |
5696 | bss_conf->ibss_joined ? "add" : "remove", |
5697 | bss_conf->bssid); | |
be663ab6 WYG |
5698 | } |
5699 | ||
46bc8d4b | 5700 | mutex_unlock(&il->mutex); |
be663ab6 | 5701 | |
58de00a4 | 5702 | D_MAC80211("leave\n"); |
be663ab6 | 5703 | } |
e7392364 | 5704 | |
e2ebc833 | 5705 | EXPORT_SYMBOL(il_mac_bss_info_changed); |
be663ab6 | 5706 | |
e7392364 SG |
5707 | irqreturn_t |
5708 | il_isr(int irq, void *data) | |
be663ab6 | 5709 | { |
46bc8d4b | 5710 | struct il_priv *il = data; |
be663ab6 WYG |
5711 | u32 inta, inta_mask; |
5712 | u32 inta_fh; | |
5713 | unsigned long flags; | |
46bc8d4b | 5714 | if (!il) |
be663ab6 WYG |
5715 | return IRQ_NONE; |
5716 | ||
46bc8d4b | 5717 | spin_lock_irqsave(&il->lock, flags); |
be663ab6 WYG |
5718 | |
5719 | /* Disable (but don't clear!) interrupts here to avoid | |
5720 | * back-to-back ISRs and sporadic interrupts from our NIC. | |
5721 | * If we have something to service, the tasklet will re-enable ints. | |
5722 | * If we *don't* have something, we'll re-enable before leaving here. */ | |
e7392364 | 5723 | inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */ |
841b2cca | 5724 | _il_wr(il, CSR_INT_MASK, 0x00000000); |
be663ab6 WYG |
5725 | |
5726 | /* Discover which interrupts are active/pending */ | |
841b2cca SG |
5727 | inta = _il_rd(il, CSR_INT); |
5728 | inta_fh = _il_rd(il, CSR_FH_INT_STATUS); | |
be663ab6 WYG |
5729 | |
5730 | /* Ignore interrupt if there's nothing in NIC to service. | |
5731 | * This may be due to IRQ shared with another device, | |
5732 | * or due to sporadic interrupts thrown from our NIC. */ | |
5733 | if (!inta && !inta_fh) { | |
e7392364 | 5734 | D_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n"); |
be663ab6 WYG |
5735 | goto none; |
5736 | } | |
5737 | ||
232913b5 | 5738 | if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) { |
be663ab6 WYG |
5739 | /* Hardware disappeared. It might have already raised |
5740 | * an interrupt */ | |
9406f797 | 5741 | IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta); |
be663ab6 WYG |
5742 | goto unplugged; |
5743 | } | |
5744 | ||
e7392364 SG |
5745 | D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, inta_mask, |
5746 | inta_fh); | |
be663ab6 WYG |
5747 | |
5748 | inta &= ~CSR_INT_BIT_SCD; | |
5749 | ||
e2ebc833 | 5750 | /* il_irq_tasklet() will service interrupts and re-enable them */ |
be663ab6 | 5751 | if (likely(inta || inta_fh)) |
46bc8d4b | 5752 | tasklet_schedule(&il->irq_tasklet); |
be663ab6 WYG |
5753 | |
5754 | unplugged: | |
46bc8d4b | 5755 | spin_unlock_irqrestore(&il->lock, flags); |
be663ab6 WYG |
5756 | return IRQ_HANDLED; |
5757 | ||
5758 | none: | |
5759 | /* re-enable interrupts here since we don't have anything to service. */ | |
93fd74e3 | 5760 | /* only Re-enable if disabled by irq */ |
a6766ccd | 5761 | if (test_bit(S_INT_ENABLED, &il->status)) |
46bc8d4b SG |
5762 | il_enable_interrupts(il); |
5763 | spin_unlock_irqrestore(&il->lock, flags); | |
be663ab6 WYG |
5764 | return IRQ_NONE; |
5765 | } | |
e7392364 | 5766 | |
e2ebc833 | 5767 | EXPORT_SYMBOL(il_isr); |
be663ab6 WYG |
5768 | |
5769 | /* | |
e2ebc833 | 5770 | * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this |
be663ab6 WYG |
5771 | * function. |
5772 | */ | |
e7392364 SG |
5773 | void |
5774 | il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info, | |
5775 | __le16 fc, __le32 * tx_flags) | |
be663ab6 WYG |
5776 | { |
5777 | if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) { | |
5778 | *tx_flags |= TX_CMD_FLG_RTS_MSK; | |
5779 | *tx_flags &= ~TX_CMD_FLG_CTS_MSK; | |
5780 | *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
5781 | ||
5782 | if (!ieee80211_is_mgmt(fc)) | |
5783 | return; | |
5784 | ||
5785 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
5786 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
5787 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
5788 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
5789 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
5790 | *tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
5791 | *tx_flags |= TX_CMD_FLG_CTS_MSK; | |
5792 | break; | |
5793 | } | |
e7392364 SG |
5794 | } else if (info->control.rates[0]. |
5795 | flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { | |
be663ab6 WYG |
5796 | *tx_flags &= ~TX_CMD_FLG_RTS_MSK; |
5797 | *tx_flags |= TX_CMD_FLG_CTS_MSK; | |
5798 | *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK; | |
5799 | } | |
5800 | } | |
e7392364 | 5801 | |
e2ebc833 | 5802 | EXPORT_SYMBOL(il_tx_cmd_protection); |