projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rt2x00usb: fix indexes ordering on RX queue kick
[deliverable/linux.git] / drivers / net / wireless / iwlegacy / common.c
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/etherdevice.h>
32#include <linux/sched.h>
33#include <linux/slab.h>
0cdc2136
SG		 34#include <linux/types.h>
35#include <linux/lockdep.h>
36#include <linux/init.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/delay.h>
40#include <linux/skbuff.h>
be663ab6
WYG		 41#include <net/mac80211.h>
42
98613be0 43#include "common.h"
be663ab6 44
17d4eca6
SG		 45int
46_il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout)
47{
48 const int interval = 10; /* microseconds */
49 int t = 0;
50
51 do {
52 if ((_il_rd(il, addr) & mask) == (bits & mask))
53 return t;
54 udelay(interval);
55 t += interval;
56 } while (t < timeout);
57
58 return -ETIMEDOUT;
59}
60EXPORT_SYMBOL(_il_poll_bit);
61
62void
63il_set_bit(struct il_priv *p, u32 r, u32 m)
64{
65 unsigned long reg_flags;
66
67 spin_lock_irqsave(&p->reg_lock, reg_flags);
68 _il_set_bit(p, r, m);
69 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
70}
71EXPORT_SYMBOL(il_set_bit);
72
73void
74il_clear_bit(struct il_priv *p, u32 r, u32 m)
75{
76 unsigned long reg_flags;
77
78 spin_lock_irqsave(&p->reg_lock, reg_flags);
79 _il_clear_bit(p, r, m);
80 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
81}
82EXPORT_SYMBOL(il_clear_bit);
83
1e0f32a4 84bool
17d4eca6
SG		 85_il_grab_nic_access(struct il_priv *il)
86{
87 int ret;
88 u32 val;
89
90 /* this bit wakes up the NIC */
91 _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
92
93 /*
94 * These bits say the device is running, and should keep running for
95 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
96 * but they do not indicate that embedded SRAM is restored yet;
97 * 3945 and 4965 have volatile SRAM, and must save/restore contents
98 * to/from host DRAM when sleeping/waking for power-saving.
99 * Each direction takes approximately 1/4 millisecond; with this
100 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
101 * series of register accesses are expected (e.g. reading Event Log),
102 * to keep device from sleeping.
103 *
104 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
105 * SRAM is okay/restored. We don't check that here because this call
106 * is just for hardware register access; but GP1 MAC_SLEEP check is a
107 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
108 *
109 */
110 ret =
111 _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
112 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
113 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
b6603036 114 if (unlikely(ret < 0)) {
17d4eca6 115 val = _il_rd(il, CSR_GP_CNTRL);
b6603036
SG		 116 WARN_ONCE(1, "Timeout waiting for ucode processor access "
117 "(CSR_GP_CNTRL 0x%08x)\n", val);
17d4eca6 118 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1e0f32a4 119 return false;
17d4eca6
SG		 120 }
121
1e0f32a4 122 return true;
17d4eca6
SG		 123}
124EXPORT_SYMBOL_GPL(_il_grab_nic_access);
125
126int
127il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout)
128{
129 const int interval = 10; /* microseconds */
130 int t = 0;
131
132 do {
133 if ((il_rd(il, addr) & mask) == mask)
134 return t;
135 udelay(interval);
136 t += interval;
137 } while (t < timeout);
138
139 return -ETIMEDOUT;
140}
141EXPORT_SYMBOL(il_poll_bit);
142
143u32
144il_rd_prph(struct il_priv *il, u32 reg)
145{
146 unsigned long reg_flags;
147 u32 val;
148
149 spin_lock_irqsave(&il->reg_lock, reg_flags);
150 _il_grab_nic_access(il);
151 val = _il_rd_prph(il, reg);
152 _il_release_nic_access(il);
153 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
154 return val;
155}
156EXPORT_SYMBOL(il_rd_prph);
157
158void
159il_wr_prph(struct il_priv *il, u32 addr, u32 val)
160{
161 unsigned long reg_flags;
162
163 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4 164 if (likely(_il_grab_nic_access(il))) {
17d4eca6
SG		 165 _il_wr_prph(il, addr, val);
166 _il_release_nic_access(il);
167 }
168 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
169}
170EXPORT_SYMBOL(il_wr_prph);
171
172u32
173il_read_targ_mem(struct il_priv *il, u32 addr)
174{
175 unsigned long reg_flags;
176 u32 value;
177
178 spin_lock_irqsave(&il->reg_lock, reg_flags);
179 _il_grab_nic_access(il);
180
181 _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
17d4eca6
SG		 182 value = _il_rd(il, HBUS_TARG_MEM_RDAT);
183
184 _il_release_nic_access(il);
185 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
186 return value;
187}
188EXPORT_SYMBOL(il_read_targ_mem);
189
190void
191il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
192{
193 unsigned long reg_flags;
194
195 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4 196 if (likely(_il_grab_nic_access(il))) {
17d4eca6 197 _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
17d4eca6
SG		 198 _il_wr(il, HBUS_TARG_MEM_WDAT, val);
199 _il_release_nic_access(il);
200 }
201 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
202}
203EXPORT_SYMBOL(il_write_targ_mem);
204
e7392364
SG		 205const char *
206il_get_cmd_string(u8 cmd)
0cdc2136
SG		 207{
208 switch (cmd) {
209 IL_CMD(N_ALIVE);
210 IL_CMD(N_ERROR);
211 IL_CMD(C_RXON);
212 IL_CMD(C_RXON_ASSOC);
213 IL_CMD(C_QOS_PARAM);
214 IL_CMD(C_RXON_TIMING);
215 IL_CMD(C_ADD_STA);
216 IL_CMD(C_REM_STA);
217 IL_CMD(C_WEPKEY);
218 IL_CMD(N_3945_RX);
219 IL_CMD(C_TX);
220 IL_CMD(C_RATE_SCALE);
221 IL_CMD(C_LEDS);
222 IL_CMD(C_TX_LINK_QUALITY_CMD);
223 IL_CMD(C_CHANNEL_SWITCH);
224 IL_CMD(N_CHANNEL_SWITCH);
225 IL_CMD(C_SPECTRUM_MEASUREMENT);
226 IL_CMD(N_SPECTRUM_MEASUREMENT);
227 IL_CMD(C_POWER_TBL);
228 IL_CMD(N_PM_SLEEP);
229 IL_CMD(N_PM_DEBUG_STATS);
230 IL_CMD(C_SCAN);
231 IL_CMD(C_SCAN_ABORT);
232 IL_CMD(N_SCAN_START);
233 IL_CMD(N_SCAN_RESULTS);
234 IL_CMD(N_SCAN_COMPLETE);
235 IL_CMD(N_BEACON);
236 IL_CMD(C_TX_BEACON);
237 IL_CMD(C_TX_PWR_TBL);
238 IL_CMD(C_BT_CONFIG);
239 IL_CMD(C_STATS);
240 IL_CMD(N_STATS);
241 IL_CMD(N_CARD_STATE);
242 IL_CMD(N_MISSED_BEACONS);
243 IL_CMD(C_CT_KILL_CONFIG);
244 IL_CMD(C_SENSITIVITY);
245 IL_CMD(C_PHY_CALIBRATION);
246 IL_CMD(N_RX_PHY);
247 IL_CMD(N_RX_MPDU);
248 IL_CMD(N_RX);
249 IL_CMD(N_COMPRESSED_BA);
250 default:
251 return "UNKNOWN";
252
253 }
254}
255EXPORT_SYMBOL(il_get_cmd_string);
256
257#define HOST_COMPLETE_TIMEOUT (HZ / 2)
258
e7392364
SG		 259static void
260il_generic_cmd_callback(struct il_priv *il, struct il_device_cmd *cmd,
261 struct il_rx_pkt *pkt)
0cdc2136
SG		 262{
263 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
264 IL_ERR("Bad return from %s (0x%08X)\n",
e7392364 265 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
0cdc2136
SG		 266 return;
267 }
0cdc2136
SG		 268#ifdef CONFIG_IWLEGACY_DEBUG
269 switch (cmd->hdr.cmd) {
270 case C_TX_LINK_QUALITY_CMD:
271 case C_SENSITIVITY:
272 D_HC_DUMP("back from %s (0x%08X)\n",
e7392364 273 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
0cdc2136
SG		 274 break;
275 default:
e7392364
SG		 276 D_HC("back from %s (0x%08X)\n", il_get_cmd_string(cmd->hdr.cmd),
277 pkt->hdr.flags);
0cdc2136
SG		 278 }
279#endif
280}
281
282static int
283il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd)
284{
285 int ret;
286
287 BUG_ON(!(cmd->flags & CMD_ASYNC));
288
289 /* An asynchronous command can not expect an SKB to be set. */
290 BUG_ON(cmd->flags & CMD_WANT_SKB);
291
292 /* Assign a generic callback if one is not provided */
293 if (!cmd->callback)
294 cmd->callback = il_generic_cmd_callback;
295
296 if (test_bit(S_EXIT_PENDING, &il->status))
297 return -EBUSY;
298
299 ret = il_enqueue_hcmd(il, cmd);
300 if (ret < 0) {
301 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
e7392364 302 il_get_cmd_string(cmd->id), ret);
0cdc2136
SG		 303 return ret;
304 }
305 return 0;
306}
307
e7392364
SG		 308int
309il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG		 310{
311 int cmd_idx;
312 int ret;
313
314 lockdep_assert_held(&il->mutex);
315
316 BUG_ON(cmd->flags & CMD_ASYNC);
317
e7392364 318 /* A synchronous command can not have a callback set. */
0cdc2136
SG		 319 BUG_ON(cmd->callback);
320
321 D_INFO("Attempting to send sync command %s\n",
e7392364 322 il_get_cmd_string(cmd->id));
0cdc2136
SG		 323
324 set_bit(S_HCMD_ACTIVE, &il->status);
325 D_INFO("Setting HCMD_ACTIVE for command %s\n",
e7392364 326 il_get_cmd_string(cmd->id));
0cdc2136
SG		 327
328 cmd_idx = il_enqueue_hcmd(il, cmd);
329 if (cmd_idx < 0) {
330 ret = cmd_idx;
331 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
e7392364 332 il_get_cmd_string(cmd->id), ret);
0cdc2136
SG		 333 goto out;
334 }
335
336 ret = wait_event_timeout(il->wait_command_queue,
e7392364
SG		 337 !test_bit(S_HCMD_ACTIVE, &il->status),
338 HOST_COMPLETE_TIMEOUT);
0cdc2136
SG		 339 if (!ret) {
340 if (test_bit(S_HCMD_ACTIVE, &il->status)) {
e7392364
SG		 341 IL_ERR("Error sending %s: time out after %dms.\n",
342 il_get_cmd_string(cmd->id),
343 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
0cdc2136
SG		 344
345 clear_bit(S_HCMD_ACTIVE, &il->status);
e7392364
SG		 346 D_INFO("Clearing HCMD_ACTIVE for command %s\n",
347 il_get_cmd_string(cmd->id));
0cdc2136
SG		 348 ret = -ETIMEDOUT;
349 goto cancel;
350 }
351 }
352
bc269a8e 353 if (test_bit(S_RFKILL, &il->status)) {
0cdc2136 354 IL_ERR("Command %s aborted: RF KILL Switch\n",
e7392364 355 il_get_cmd_string(cmd->id));
0cdc2136
SG		 356 ret = -ECANCELED;
357 goto fail;
358 }
359 if (test_bit(S_FW_ERROR, &il->status)) {
360 IL_ERR("Command %s failed: FW Error\n",
e7392364 361 il_get_cmd_string(cmd->id));
0cdc2136
SG		 362 ret = -EIO;
363 goto fail;
364 }
365 if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
366 IL_ERR("Error: Response NULL in '%s'\n",
e7392364 367 il_get_cmd_string(cmd->id));
0cdc2136
SG		 368 ret = -EIO;
369 goto cancel;
370 }
371
372 ret = 0;
373 goto out;
374
375cancel:
376 if (cmd->flags & CMD_WANT_SKB) {
377 /*
378 * Cancel the CMD_WANT_SKB flag for the cmd in the
379 * TX cmd queue. Otherwise in case the cmd comes
380 * in later, it will possibly set an invalid
381 * address (cmd->meta.source).
382 */
e7392364 383 il->txq[il->cmd_queue].meta[cmd_idx].flags &= ~CMD_WANT_SKB;
0cdc2136
SG		 384 }
385fail:
386 if (cmd->reply_page) {
387 il_free_pages(il, cmd->reply_page);
388 cmd->reply_page = 0;
389 }
390out:
391 return ret;
392}
393EXPORT_SYMBOL(il_send_cmd_sync);
394
e7392364
SG		 395int
396il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG		 397{
398 if (cmd->flags & CMD_ASYNC)
399 return il_send_cmd_async(il, cmd);
400
401 return il_send_cmd_sync(il, cmd);
402}
403EXPORT_SYMBOL(il_send_cmd);
404
405int
406il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data)
407{
408 struct il_host_cmd cmd = {
409 .id = id,
410 .len = len,
411 .data = data,
412 };
413
414 return il_send_cmd_sync(il, &cmd);
415}
416EXPORT_SYMBOL(il_send_cmd_pdu);
417
e7392364
SG		 418int
419il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1722f8e1
SG		 420 void (*callback) (struct il_priv *il,
421 struct il_device_cmd *cmd,
422 struct il_rx_pkt *pkt))
0cdc2136
SG		 423{
424 struct il_host_cmd cmd = {
425 .id = id,
426 .len = len,
427 .data = data,
428 };
429
430 cmd.flags |= CMD_ASYNC;
431 cmd.callback = callback;
432
433 return il_send_cmd_async(il, &cmd);
434}
435EXPORT_SYMBOL(il_send_cmd_pdu_async);
436
437/* default: IL_LED_BLINK(0) using blinking idx table */
438static int led_mode;
439module_param(led_mode, int, S_IRUGO);
e7392364
SG		 440MODULE_PARM_DESC(led_mode,
441 "0=system default, " "1=On(RF On)/Off(RF Off), 2=blinking");
0cdc2136
SG		 442
443/* Throughput OFF time(ms) ON time (ms)
444 * >300 25 25
445 * >200 to 300 40 40
446 * >100 to 200 55 55
447 * >70 to 100 65 65
448 * >50 to 70 75 75
449 * >20 to 50 85 85
450 * >10 to 20 95 95
451 * >5 to 10 110 110
452 * >1 to 5 130 130
453 * >0 to 1 167 167
454 * <=0 SOLID ON
455 */
456static const struct ieee80211_tpt_blink il_blink[] = {
1722f8e1
SG		 457 {.throughput = 0, .blink_time = 334},
458 {.throughput = 1 * 1024 - 1, .blink_time = 260},
459 {.throughput = 5 * 1024 - 1, .blink_time = 220},
460 {.throughput = 10 * 1024 - 1, .blink_time = 190},
461 {.throughput = 20 * 1024 - 1, .blink_time = 170},
462 {.throughput = 50 * 1024 - 1, .blink_time = 150},
463 {.throughput = 70 * 1024 - 1, .blink_time = 130},
464 {.throughput = 100 * 1024 - 1, .blink_time = 110},
465 {.throughput = 200 * 1024 - 1, .blink_time = 80},
466 {.throughput = 300 * 1024 - 1, .blink_time = 50},
0cdc2136
SG		 467};
468
469/*
470 * Adjust led blink rate to compensate on a MAC Clock difference on every HW
471 * Led blink rate analysis showed an average deviation of 0% on 3945,
472 * 5% on 4965 HW.
473 * Need to compensate on the led on/off time per HW according to the deviation
474 * to achieve the desired led frequency
475 * The calculation is: (100-averageDeviation)/100 * blinkTime
476 * For code efficiency the calculation will be:
477 * compensation = (100 - averageDeviation) * 64 / 100
478 * NewBlinkTime = (compensation * BlinkTime) / 64
479 */
e7392364
SG		 480static inline u8
481il_blink_compensation(struct il_priv *il, u8 time, u16 compensation)
0cdc2136
SG		 482{
483 if (!compensation) {
484 IL_ERR("undefined blink compensation: "
e7392364 485 "use pre-defined blinking time\n");
0cdc2136
SG		 486 return time;
487 }
488
e7392364 489 return (u8) ((time * compensation) >> 6);
0cdc2136
SG		 490}
491
492/* Set led pattern command */
e7392364
SG		 493static int
494il_led_cmd(struct il_priv *il, unsigned long on, unsigned long off)
0cdc2136
SG		 495{
496 struct il_led_cmd led_cmd = {
497 .id = IL_LED_LINK,
498 .interval = IL_DEF_LED_INTRVL
499 };
500 int ret;
501
502 if (!test_bit(S_READY, &il->status))
503 return -EBUSY;
504
505 if (il->blink_on == on && il->blink_off == off)
506 return 0;
507
508 if (off == 0) {
509 /* led is SOLID_ON */
510 on = IL_LED_SOLID;
511 }
512
513 D_LED("Led blink time compensation=%u\n",
89ef1ed2 514 il->cfg->led_compensation);
e7392364
SG		 515 led_cmd.on =
516 il_blink_compensation(il, on,
89ef1ed2 517 il->cfg->led_compensation);
e7392364
SG		 518 led_cmd.off =
519 il_blink_compensation(il, off,
89ef1ed2 520 il->cfg->led_compensation);
0cdc2136 521
c9363551 522 ret = il->ops->send_led_cmd(il, &led_cmd);
0cdc2136
SG		 523 if (!ret) {
524 il->blink_on = on;
525 il->blink_off = off;
526 }
527 return ret;
528}
529
e7392364
SG		 530static void
531il_led_brightness_set(struct led_classdev *led_cdev,
532 enum led_brightness brightness)
0cdc2136
SG		 533{
534 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
535 unsigned long on = 0;
536
537 if (brightness > 0)
538 on = IL_LED_SOLID;
539
540 il_led_cmd(il, on, 0);
541}
542
e7392364
SG		 543static int
544il_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on,
545 unsigned long *delay_off)
0cdc2136
SG		 546{
547 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
548
549 return il_led_cmd(il, *delay_on, *delay_off);
550}
551
e7392364
SG		 552void
553il_leds_init(struct il_priv *il)
0cdc2136
SG		 554{
555 int mode = led_mode;
556 int ret;
557
558 if (mode == IL_LED_DEFAULT)
559 mode = il->cfg->led_mode;
560
e7392364
SG		 561 il->led.name =
562 kasprintf(GFP_KERNEL, "%s-led", wiphy_name(il->hw->wiphy));
0cdc2136
SG		 563 il->led.brightness_set = il_led_brightness_set;
564 il->led.blink_set = il_led_blink_set;
565 il->led.max_brightness = 1;
566
567 switch (mode) {
568 case IL_LED_DEFAULT:
569 WARN_ON(1);
570 break;
571 case IL_LED_BLINK:
572 il->led.default_trigger =
e7392364
SG		 573 ieee80211_create_tpt_led_trigger(il->hw,
574 IEEE80211_TPT_LEDTRIG_FL_CONNECTED,
575 il_blink,
576 ARRAY_SIZE(il_blink));
0cdc2136
SG		 577 break;
578 case IL_LED_RF_STATE:
e7392364 579 il->led.default_trigger = ieee80211_get_radio_led_name(il->hw);
0cdc2136
SG		 580 break;
581 }
582
583 ret = led_classdev_register(&il->pci_dev->dev, &il->led);
584 if (ret) {
585 kfree(il->led.name);
586 return;
587 }
588
589 il->led_registered = true;
590}
591EXPORT_SYMBOL(il_leds_init);
592
e7392364
SG		 593void
594il_leds_exit(struct il_priv *il)
0cdc2136
SG		 595{
596 if (!il->led_registered)
597 return;
598
599 led_classdev_unregister(&il->led);
600 kfree(il->led.name);
601}
602EXPORT_SYMBOL(il_leds_exit);
603
604/************************** EEPROM BANDS ****************************
605 *
606 * The il_eeprom_band definitions below provide the mapping from the
607 * EEPROM contents to the specific channel number supported for each
608 * band.
609 *
610 * For example, il_priv->eeprom.band_3_channels[4] from the band_3
611 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
612 * The specific geography and calibration information for that channel
613 * is contained in the eeprom map itself.
614 *
615 * During init, we copy the eeprom information and channel map
616 * information into il->channel_info_24/52 and il->channel_map_24/52
617 *
618 * channel_map_24/52 provides the idx in the channel_info array for a
619 * given channel. We have to have two separate maps as there is channel
620 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
621 * band_2
622 *
623 * A value of 0xff stored in the channel_map indicates that the channel
624 * is not supported by the hardware at all.
625 *
626 * A value of 0xfe in the channel_map indicates that the channel is not
627 * valid for Tx with the current hardware. This means that
628 * while the system can tune and receive on a given channel, it may not
629 * be able to associate or transmit any frames on that
630 * channel. There is no corresponding channel information for that
631 * entry.
632 *
633 *********************************************************************/
634
635/* 2.4 GHz */
636const u8 il_eeprom_band_1[14] = {
637 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
638};
639
640/* 5.2 GHz bands */
641static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */
642 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
643};
644
645static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */
646 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
647};
648
649static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */
650 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
651};
652
653static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */
654 145, 149, 153, 157, 161, 165
655};
656
e7392364 657static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */
0cdc2136
SG		 658 1, 2, 3, 4, 5, 6, 7
659};
660
e7392364 661static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */
0cdc2136
SG		 662 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
663};
664
665/******************************************************************************
666 *
667 * EEPROM related functions
668 *
669******************************************************************************/
670
e7392364
SG		 671static int
672il_eeprom_verify_signature(struct il_priv *il)
0cdc2136
SG		 673{
674 u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
675 int ret = 0;
676
677 D_EEPROM("EEPROM signature=0x%08x\n", gp);
678 switch (gp) {
679 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
680 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
681 break;
682 default:
e7392364 683 IL_ERR("bad EEPROM signature," "EEPROM_GP=0x%08x\n", gp);
0cdc2136
SG		 684 ret = -ENOENT;
685 break;
686 }
687 return ret;
688}
689
e7392364
SG		 690const u8 *
691il_eeprom_query_addr(const struct il_priv *il, size_t offset)
0cdc2136 692{
89ef1ed2 693 BUG_ON(offset >= il->cfg->eeprom_size);
0cdc2136
SG		 694 return &il->eeprom[offset];
695}
696EXPORT_SYMBOL(il_eeprom_query_addr);
697
e7392364 698u16
1722f8e1 699il_eeprom_query16(const struct il_priv *il, size_t offset)
0cdc2136
SG		 700{
701 if (!il->eeprom)
702 return 0;
e7392364 703 return (u16) il->eeprom[offset] | ((u16) il->eeprom[offset + 1] << 8);
0cdc2136
SG		 704}
705EXPORT_SYMBOL(il_eeprom_query16);
706
707/**
708 * il_eeprom_init - read EEPROM contents
709 *
710 * Load the EEPROM contents from adapter into il->eeprom
711 *
712 * NOTE: This routine uses the non-debug IO access functions.
713 */
e7392364
SG		 714int
715il_eeprom_init(struct il_priv *il)
0cdc2136
SG		 716{
717 __le16 *e;
718 u32 gp = _il_rd(il, CSR_EEPROM_GP);
719 int sz;
720 int ret;
721 u16 addr;
722
723 /* allocate eeprom */
89ef1ed2 724 sz = il->cfg->eeprom_size;
0cdc2136
SG		 725 D_EEPROM("NVM size = %d\n", sz);
726 il->eeprom = kzalloc(sz, GFP_KERNEL);
727 if (!il->eeprom) {
728 ret = -ENOMEM;
729 goto alloc_err;
730 }
e7392364 731 e = (__le16 *) il->eeprom;
0cdc2136 732
1600b875 733 il->ops->apm_init(il);
0cdc2136
SG		 734
735 ret = il_eeprom_verify_signature(il);
736 if (ret < 0) {
737 IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
738 ret = -ENOENT;
739 goto err;
740 }
741
742 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
1600b875 743 ret = il->ops->eeprom_acquire_semaphore(il);
0cdc2136
SG		 744 if (ret < 0) {
745 IL_ERR("Failed to acquire EEPROM semaphore.\n");
746 ret = -ENOENT;
747 goto err;
748 }
749
750 /* eeprom is an array of 16bit values */
751 for (addr = 0; addr < sz; addr += sizeof(u16)) {
752 u32 r;
753
754 _il_wr(il, CSR_EEPROM_REG,
e7392364 755 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
0cdc2136 756
e7392364
SG		 757 ret =
758 _il_poll_bit(il, CSR_EEPROM_REG,
759 CSR_EEPROM_REG_READ_VALID_MSK,
760 CSR_EEPROM_REG_READ_VALID_MSK,
761 IL_EEPROM_ACCESS_TIMEOUT);
0cdc2136 762 if (ret < 0) {
e7392364 763 IL_ERR("Time out reading EEPROM[%d]\n", addr);
0cdc2136
SG		 764 goto done;
765 }
766 r = _il_rd(il, CSR_EEPROM_REG);
767 e[addr / 2] = cpu_to_le16(r >> 16);
768 }
769
e7392364
SG		 770 D_EEPROM("NVM Type: %s, version: 0x%x\n", "EEPROM",
771 il_eeprom_query16(il, EEPROM_VERSION));
0cdc2136
SG		 772
773 ret = 0;
774done:
1600b875 775 il->ops->eeprom_release_semaphore(il);
0cdc2136
SG		 776
777err:
778 if (ret)
779 il_eeprom_free(il);
780 /* Reset chip to save power until we load uCode during "up". */
781 il_apm_stop(il);
782alloc_err:
783 return ret;
784}
785EXPORT_SYMBOL(il_eeprom_init);
786
e7392364
SG		 787void
788il_eeprom_free(struct il_priv *il)
0cdc2136
SG		 789{
790 kfree(il->eeprom);
791 il->eeprom = NULL;
792}
793EXPORT_SYMBOL(il_eeprom_free);
794
e7392364
SG		 795static void
796il_init_band_reference(const struct il_priv *il, int eep_band,
797 int *eeprom_ch_count,
798 const struct il_eeprom_channel **eeprom_ch_info,
1722f8e1 799 const u8 **eeprom_ch_idx)
0cdc2136 800{
93a984a4
SG		 801 u32 offset = il->cfg->regulatory_bands[eep_band - 1];
802
0cdc2136
SG		 803 switch (eep_band) {
804 case 1: /* 2.4GHz band */
805 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1);
e7392364
SG		 806 *eeprom_ch_info =
807 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
808 offset);
0cdc2136
SG		 809 *eeprom_ch_idx = il_eeprom_band_1;
810 break;
811 case 2: /* 4.9GHz band */
812 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2);
e7392364
SG		 813 *eeprom_ch_info =
814 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
815 offset);
0cdc2136
SG		 816 *eeprom_ch_idx = il_eeprom_band_2;
817 break;
818 case 3: /* 5.2GHz band */
819 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3);
e7392364
SG		 820 *eeprom_ch_info =
821 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
822 offset);
0cdc2136
SG		 823 *eeprom_ch_idx = il_eeprom_band_3;
824 break;
825 case 4: /* 5.5GHz band */
826 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4);
e7392364
SG		 827 *eeprom_ch_info =
828 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
829 offset);
0cdc2136
SG		 830 *eeprom_ch_idx = il_eeprom_band_4;
831 break;
832 case 5: /* 5.7GHz band */
833 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5);
e7392364
SG		 834 *eeprom_ch_info =
835 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
836 offset);
0cdc2136
SG		 837 *eeprom_ch_idx = il_eeprom_band_5;
838 break;
839 case 6: /* 2.4GHz ht40 channels */
840 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6);
e7392364
SG		 841 *eeprom_ch_info =
842 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
843 offset);
0cdc2136
SG		 844 *eeprom_ch_idx = il_eeprom_band_6;
845 break;
846 case 7: /* 5 GHz ht40 channels */
847 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7);
e7392364
SG		 848 *eeprom_ch_info =
849 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
850 offset);
0cdc2136
SG		 851 *eeprom_ch_idx = il_eeprom_band_7;
852 break;
853 default:
854 BUG();
855 }
856}
857
858#define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
859 ? # x " " : "")
860/**
861 * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il.
862 *
863 * Does not set up a command, or touch hardware.
864 */
e7392364
SG		 865static int
866il_mod_ht40_chan_info(struct il_priv *il, enum ieee80211_band band, u16 channel,
867 const struct il_eeprom_channel *eeprom_ch,
868 u8 clear_ht40_extension_channel)
0cdc2136
SG		 869{
870 struct il_channel_info *ch_info;
871
e7392364
SG		 872 ch_info =
873 (struct il_channel_info *)il_get_channel_info(il, band, channel);
0cdc2136
SG		 874
875 if (!il_is_channel_valid(ch_info))
876 return -1;
877
878 D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
e7392364
SG		 879 " Ad-Hoc %ssupported\n", ch_info->channel,
880 il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
881 CHECK_AND_PRINT(IBSS), CHECK_AND_PRINT(ACTIVE),
882 CHECK_AND_PRINT(RADAR), CHECK_AND_PRINT(WIDE),
883 CHECK_AND_PRINT(DFS), eeprom_ch->flags,
884 eeprom_ch->max_power_avg,
885 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) &&
886 !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" : "not ");
0cdc2136
SG		 887
888 ch_info->ht40_eeprom = *eeprom_ch;
889 ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
890 ch_info->ht40_flags = eeprom_ch->flags;
891 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
892 ch_info->ht40_extension_channel &=
e7392364 893 ~clear_ht40_extension_channel;
0cdc2136
SG		 894
895 return 0;
896}
897
898#define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
899 ? # x " " : "")
900
901/**
902 * il_init_channel_map - Set up driver's info for all possible channels
903 */
e7392364
SG		 904int
905il_init_channel_map(struct il_priv *il)
0cdc2136
SG		 906{
907 int eeprom_ch_count = 0;
908 const u8 *eeprom_ch_idx = NULL;
909 const struct il_eeprom_channel *eeprom_ch_info = NULL;
910 int band, ch;
911 struct il_channel_info *ch_info;
912
913 if (il->channel_count) {
914 D_EEPROM("Channel map already initialized.\n");
915 return 0;
916 }
917
918 D_EEPROM("Initializing regulatory info from EEPROM\n");
919
920 il->channel_count =
e7392364
SG		 921 ARRAY_SIZE(il_eeprom_band_1) + ARRAY_SIZE(il_eeprom_band_2) +
922 ARRAY_SIZE(il_eeprom_band_3) + ARRAY_SIZE(il_eeprom_band_4) +
0cdc2136
SG		 923 ARRAY_SIZE(il_eeprom_band_5);
924
e7392364 925 D_EEPROM("Parsing data for %d channels.\n", il->channel_count);
0cdc2136 926
e7392364
SG		 927 il->channel_info =
928 kzalloc(sizeof(struct il_channel_info) * il->channel_count,
929 GFP_KERNEL);
0cdc2136
SG		 930 if (!il->channel_info) {
931 IL_ERR("Could not allocate channel_info\n");
932 il->channel_count = 0;
933 return -ENOMEM;
934 }
935
936 ch_info = il->channel_info;
937
938 /* Loop through the 5 EEPROM bands adding them in order to the
939 * channel map we maintain (that contains additional information than
940 * what just in the EEPROM) */
941 for (band = 1; band <= 5; band++) {
942
943 il_init_band_reference(il, band, &eeprom_ch_count,
e7392364 944 &eeprom_ch_info, &eeprom_ch_idx);
0cdc2136
SG		 945
946 /* Loop through each band adding each of the channels */
947 for (ch = 0; ch < eeprom_ch_count; ch++) {
948 ch_info->channel = eeprom_ch_idx[ch];
e7392364
SG		 949 ch_info->band =
950 (band ==
951 1) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
0cdc2136
SG		 952
953 /* permanently store EEPROM's channel regulatory flags
954 * and max power in channel info database. */
955 ch_info->eeprom = eeprom_ch_info[ch];
956
957 /* Copy the run-time flags so they are there even on
958 * invalid channels */
959 ch_info->flags = eeprom_ch_info[ch].flags;
960 /* First write that ht40 is not enabled, and then enable
961 * one by one */
962 ch_info->ht40_extension_channel =
e7392364 963 IEEE80211_CHAN_NO_HT40;
0cdc2136
SG		 964
965 if (!(il_is_channel_valid(ch_info))) {
e7392364
SG		 966 D_EEPROM("Ch. %d Flags %x [%sGHz] - "
967 "No traffic\n", ch_info->channel,
968 ch_info->flags,
969 il_is_channel_a_band(ch_info) ? "5.2" :
970 "2.4");
0cdc2136
SG		 971 ch_info++;
972 continue;
973 }
974
975 /* Initialize regulatory-based run-time data */
976 ch_info->max_power_avg = ch_info->curr_txpow =
977 eeprom_ch_info[ch].max_power_avg;
978 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
979 ch_info->min_power = 0;
980
e7392364
SG		 981 D_EEPROM("Ch. %d [%sGHz] " "%s%s%s%s%s%s(0x%02x %ddBm):"
982 " Ad-Hoc %ssupported\n", ch_info->channel,
983 il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
984 CHECK_AND_PRINT_I(VALID),
985 CHECK_AND_PRINT_I(IBSS),
986 CHECK_AND_PRINT_I(ACTIVE),
987 CHECK_AND_PRINT_I(RADAR),
988 CHECK_AND_PRINT_I(WIDE),
989 CHECK_AND_PRINT_I(DFS),
990 eeprom_ch_info[ch].flags,
991 eeprom_ch_info[ch].max_power_avg,
992 ((eeprom_ch_info[ch].
993 flags & EEPROM_CHANNEL_IBSS) &&
994 !(eeprom_ch_info[ch].
995 flags & EEPROM_CHANNEL_RADAR)) ? "" :
996 "not ");
0cdc2136
SG		 997
998 ch_info++;
999 }
1000 }
1001
1002 /* Check if we do have HT40 channels */
93a984a4
SG		 1003 if (il->cfg->regulatory_bands[5] == EEPROM_REGULATORY_BAND_NO_HT40 &&
1004 il->cfg->regulatory_bands[6] == EEPROM_REGULATORY_BAND_NO_HT40)
0cdc2136
SG		 1005 return 0;
1006
1007 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
1008 for (band = 6; band <= 7; band++) {
1009 enum ieee80211_band ieeeband;
1010
1011 il_init_band_reference(il, band, &eeprom_ch_count,
e7392364 1012 &eeprom_ch_info, &eeprom_ch_idx);
0cdc2136
SG		 1013
1014 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
1015 ieeeband =
e7392364 1016 (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
0cdc2136
SG		 1017
1018 /* Loop through each band adding each of the channels */
1019 for (ch = 0; ch < eeprom_ch_count; ch++) {
1020 /* Set up driver's info for lower half */
e7392364
SG		 1021 il_mod_ht40_chan_info(il, ieeeband, eeprom_ch_idx[ch],
1022 &eeprom_ch_info[ch],
1023 IEEE80211_CHAN_NO_HT40PLUS);
0cdc2136
SG		 1024
1025 /* Set up driver's info for upper half */
1026 il_mod_ht40_chan_info(il, ieeeband,
e7392364
SG		 1027 eeprom_ch_idx[ch] + 4,
1028 &eeprom_ch_info[ch],
1029 IEEE80211_CHAN_NO_HT40MINUS);
0cdc2136
SG		 1030 }
1031 }
1032
1033 return 0;
1034}
1035EXPORT_SYMBOL(il_init_channel_map);
1036
1037/*
1038 * il_free_channel_map - undo allocations in il_init_channel_map
1039 */
e7392364
SG		 1040void
1041il_free_channel_map(struct il_priv *il)
0cdc2136
SG		 1042{
1043 kfree(il->channel_info);
1044 il->channel_count = 0;
1045}
1046EXPORT_SYMBOL(il_free_channel_map);
1047
1048/**
1049 * il_get_channel_info - Find driver's ilate channel info
1050 *
1051 * Based on band and channel number.
1052 */
e7392364
SG		 1053const struct il_channel_info *
1054il_get_channel_info(const struct il_priv *il, enum ieee80211_band band,
1055 u16 channel)
0cdc2136
SG		 1056{
1057 int i;
1058
1059 switch (band) {
1060 case IEEE80211_BAND_5GHZ:
1061 for (i = 14; i < il->channel_count; i++) {
1062 if (il->channel_info[i].channel == channel)
1063 return &il->channel_info[i];
1064 }
1065 break;
1066 case IEEE80211_BAND_2GHZ:
1067 if (channel >= 1 && channel <= 14)
1068 return &il->channel_info[channel - 1];
1069 break;
1070 default:
1071 BUG();
1072 }
1073
1074 return NULL;
1075}
1076EXPORT_SYMBOL(il_get_channel_info);
1077
1078/*
1079 * Setting power level allows the card to go to sleep when not busy.
1080 *
1081 * We calculate a sleep command based on the required latency, which
1082 * we get from mac80211. In order to handle thermal throttling, we can
1083 * also use pre-defined power levels.
1084 */
1085
1086/*
1087 * This defines the old power levels. They are still used by default
1088 * (level 1) and for thermal throttle (levels 3 through 5)
1089 */
1090
1091struct il_power_vec_entry {
1092 struct il_powertable_cmd cmd;
e7392364 1093 u8 no_dtim; /* number of skip dtim */
0cdc2136
SG		 1094};
1095
e7392364
SG		 1096static void
1097il_power_sleep_cam_cmd(struct il_priv *il, struct il_powertable_cmd *cmd)
0cdc2136
SG		 1098{
1099 memset(cmd, 0, sizeof(*cmd));
1100
1101 if (il->power_data.pci_pm)
1102 cmd->flags |= IL_POWER_PCI_PM_MSK;
1103
1104 D_POWER("Sleep command for CAM\n");
1105}
1106
1107static int
1108il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd)
1109{
1110 D_POWER("Sending power/sleep command\n");
1111 D_POWER("Flags value = 0x%08X\n", cmd->flags);
e7392364
SG		 1112 D_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1113 D_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1114 D_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1115 le32_to_cpu(cmd->sleep_interval[0]),
1116 le32_to_cpu(cmd->sleep_interval[1]),
1117 le32_to_cpu(cmd->sleep_interval[2]),
1118 le32_to_cpu(cmd->sleep_interval[3]),
1119 le32_to_cpu(cmd->sleep_interval[4]));
0cdc2136
SG		 1120
1121 return il_send_cmd_pdu(il, C_POWER_TBL,
e7392364 1122 sizeof(struct il_powertable_cmd), cmd);
0cdc2136
SG		 1123}
1124
1125int
e7392364 1126il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd, bool force)
0cdc2136
SG		 1127{
1128 int ret;
1129 bool update_chains;
1130
1131 lockdep_assert_held(&il->mutex);
1132
1133 /* Don't update the RX chain when chain noise calibration is running */
1134 update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE ||
e7392364 1135 il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE;
0cdc2136
SG		 1136
1137 if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
1138 return 0;
1139
1140 if (!il_is_ready_rf(il))
1141 return -EIO;
1142
1143 /* scan complete use sleep_power_next, need to be updated */
1144 memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
1145 if (test_bit(S_SCANNING, &il->status) && !force) {
1146 D_INFO("Defer power set mode while scanning\n");
1147 return 0;
1148 }
1149
1150 if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)
1151 set_bit(S_POWER_PMI, &il->status);
1152
1153 ret = il_set_power(il, cmd);
1154 if (!ret) {
1155 if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK))
1156 clear_bit(S_POWER_PMI, &il->status);
1157
1600b875
SG		 1158 if (il->ops->update_chain_flags && update_chains)
1159 il->ops->update_chain_flags(il);
1160 else if (il->ops->update_chain_flags)
e7392364
SG		 1161 D_POWER("Cannot update the power, chain noise "
1162 "calibration running: %d\n",
1163 il->chain_noise_data.state);
0cdc2136
SG		 1164
1165 memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd));
1166 } else
1167 IL_ERR("set power fail, ret = %d", ret);
1168
1169 return ret;
1170}
1171
e7392364
SG		 1172int
1173il_power_update_mode(struct il_priv *il, bool force)
0cdc2136
SG		 1174{
1175 struct il_powertable_cmd cmd;
1176
1177 il_power_sleep_cam_cmd(il, &cmd);
1178 return il_power_set_mode(il, &cmd, force);
1179}
1180EXPORT_SYMBOL(il_power_update_mode);
1181
1182/* initialize to default */
e7392364
SG		 1183void
1184il_power_initialize(struct il_priv *il)
0cdc2136
SG		 1185{
1186 u16 lctl = il_pcie_link_ctl(il);
1187
1188 il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);
1189
1190 il->power_data.debug_sleep_level_override = -1;
1191
e7392364 1192 memset(&il->power_data.sleep_cmd, 0, sizeof(il->power_data.sleep_cmd));
0cdc2136
SG		 1193}
1194EXPORT_SYMBOL(il_power_initialize);
1195
1196/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
1197 * sending probe req. This should be set long enough to hear probe responses
1198 * from more than one AP. */
e7392364 1199#define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
0cdc2136
SG		 1200#define IL_ACTIVE_DWELL_TIME_52 (20)
1201
1202#define IL_ACTIVE_DWELL_FACTOR_24GHZ (3)
1203#define IL_ACTIVE_DWELL_FACTOR_52GHZ (2)
1204
1205/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
1206 * Must be set longer than active dwell time.
1207 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
e7392364 1208#define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
0cdc2136
SG		 1209#define IL_PASSIVE_DWELL_TIME_52 (10)
1210#define IL_PASSIVE_DWELL_BASE (100)
1211#define IL_CHANNEL_TUNE_TIME 5
1212
e7392364
SG		 1213static int
1214il_send_scan_abort(struct il_priv *il)
0cdc2136
SG		 1215{
1216 int ret;
1217 struct il_rx_pkt *pkt;
1218 struct il_host_cmd cmd = {
1219 .id = C_SCAN_ABORT,
1220 .flags = CMD_WANT_SKB,
1221 };
1222
1223 /* Exit instantly with error when device is not ready
1224 * to receive scan abort command or it does not perform
1225 * hardware scan currently */
1226 if (!test_bit(S_READY, &il->status) ||
1227 !test_bit(S_GEO_CONFIGURED, &il->status) ||
1228 !test_bit(S_SCAN_HW, &il->status) ||
1229 test_bit(S_FW_ERROR, &il->status) ||
1230 test_bit(S_EXIT_PENDING, &il->status))
1231 return -EIO;
1232
1233 ret = il_send_cmd_sync(il, &cmd);
1234 if (ret)
1235 return ret;
1236
1237 pkt = (struct il_rx_pkt *)cmd.reply_page;
1238 if (pkt->u.status != CAN_ABORT_STATUS) {
1239 /* The scan abort will return 1 for success or
1240 * 2 for "failure". A failure condition can be
1241 * due to simply not being in an active scan which
1242 * can occur if we send the scan abort before we
1243 * the microcode has notified us that a scan is
1244 * completed. */
1245 D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status);
1246 ret = -EIO;
1247 }
1248
1249 il_free_pages(il, cmd.reply_page);
1250 return ret;
1251}
1252
e7392364
SG		 1253static void
1254il_complete_scan(struct il_priv *il, bool aborted)
0cdc2136
SG		 1255{
1256 /* check if scan was requested from mac80211 */
1257 if (il->scan_request) {
1258 D_SCAN("Complete scan in mac80211\n");
1259 ieee80211_scan_completed(il->hw, aborted);
1260 }
1261
1262 il->scan_vif = NULL;
1263 il->scan_request = NULL;
1264}
1265
e7392364
SG		 1266void
1267il_force_scan_end(struct il_priv *il)
0cdc2136
SG		 1268{
1269 lockdep_assert_held(&il->mutex);
1270
1271 if (!test_bit(S_SCANNING, &il->status)) {
1272 D_SCAN("Forcing scan end while not scanning\n");
1273 return;
1274 }
1275
1276 D_SCAN("Forcing scan end\n");
1277 clear_bit(S_SCANNING, &il->status);
1278 clear_bit(S_SCAN_HW, &il->status);
1279 clear_bit(S_SCAN_ABORTING, &il->status);
1280 il_complete_scan(il, true);
1281}
1282
e7392364
SG		 1283static void
1284il_do_scan_abort(struct il_priv *il)
0cdc2136
SG		 1285{
1286 int ret;
1287
1288 lockdep_assert_held(&il->mutex);
1289
1290 if (!test_bit(S_SCANNING, &il->status)) {
1291 D_SCAN("Not performing scan to abort\n");
1292 return;
1293 }
1294
1295 if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) {
1296 D_SCAN("Scan abort in progress\n");
1297 return;
1298 }
1299
1300 ret = il_send_scan_abort(il);
1301 if (ret) {
1302 D_SCAN("Send scan abort failed %d\n", ret);
1303 il_force_scan_end(il);
1304 } else
1305 D_SCAN("Successfully send scan abort\n");
1306}
1307
1308/**
1309 * il_scan_cancel - Cancel any currently executing HW scan
1310 */
e7392364
SG		 1311int
1312il_scan_cancel(struct il_priv *il)
0cdc2136
SG		 1313{
1314 D_SCAN("Queuing abort scan\n");
1315 queue_work(il->workqueue, &il->abort_scan);
1316 return 0;
1317}
1318EXPORT_SYMBOL(il_scan_cancel);
1319
1320/**
1321 * il_scan_cancel_timeout - Cancel any currently executing HW scan
1322 * @ms: amount of time to wait (in milliseconds) for scan to abort
1323 *
1324 */
e7392364
SG		 1325int
1326il_scan_cancel_timeout(struct il_priv *il, unsigned long ms)
0cdc2136
SG		 1327{
1328 unsigned long timeout = jiffies + msecs_to_jiffies(ms);
1329
1330 lockdep_assert_held(&il->mutex);
1331
1332 D_SCAN("Scan cancel timeout\n");
1333
1334 il_do_scan_abort(il);
1335
1336 while (time_before_eq(jiffies, timeout)) {
1337 if (!test_bit(S_SCAN_HW, &il->status))
1338 break;
1339 msleep(20);
1340 }
1341
1342 return test_bit(S_SCAN_HW, &il->status);
1343}
1344EXPORT_SYMBOL(il_scan_cancel_timeout);
1345
1346/* Service response to C_SCAN (0x80) */
e7392364
SG		 1347static void
1348il_hdl_scan(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1349{
1350#ifdef CONFIG_IWLEGACY_DEBUG
1351 struct il_rx_pkt *pkt = rxb_addr(rxb);
1352 struct il_scanreq_notification *notif =
1353 (struct il_scanreq_notification *)pkt->u.raw;
1354
1355 D_SCAN("Scan request status = 0x%x\n", notif->status);
1356#endif
1357}
1358
1359/* Service N_SCAN_START (0x82) */
e7392364
SG		 1360static void
1361il_hdl_scan_start(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1362{
1363 struct il_rx_pkt *pkt = rxb_addr(rxb);
1364 struct il_scanstart_notification *notif =
1365 (struct il_scanstart_notification *)pkt->u.raw;
1366 il->scan_start_tsf = le32_to_cpu(notif->tsf_low);
e7392364
SG		 1367 D_SCAN("Scan start: " "%d [802.11%s] "
1368 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", notif->channel,
1369 notif->band ? "bg" : "a", le32_to_cpu(notif->tsf_high),
1370 le32_to_cpu(notif->tsf_low), notif->status, notif->beacon_timer);
0cdc2136
SG		 1371}
1372
1373/* Service N_SCAN_RESULTS (0x83) */
e7392364
SG		 1374static void
1375il_hdl_scan_results(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1376{
1377#ifdef CONFIG_IWLEGACY_DEBUG
1378 struct il_rx_pkt *pkt = rxb_addr(rxb);
1379 struct il_scanresults_notification *notif =
1380 (struct il_scanresults_notification *)pkt->u.raw;
1381
e7392364
SG		 1382 D_SCAN("Scan ch.res: " "%d [802.11%s] " "(TSF: 0x%08X:%08X) - %d "
1383 "elapsed=%lu usec\n", notif->channel, notif->band ? "bg" : "a",
1384 le32_to_cpu(notif->tsf_high), le32_to_cpu(notif->tsf_low),
1385 le32_to_cpu(notif->stats[0]),
1386 le32_to_cpu(notif->tsf_low) - il->scan_start_tsf);
0cdc2136
SG		 1387#endif
1388}
1389
1390/* Service N_SCAN_COMPLETE (0x84) */
e7392364
SG		 1391static void
1392il_hdl_scan_complete(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1393{
1394
1395#ifdef CONFIG_IWLEGACY_DEBUG
1396 struct il_rx_pkt *pkt = rxb_addr(rxb);
1397 struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
1398#endif
1399
e7392364
SG		 1400 D_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
1401 scan_notif->scanned_channels, scan_notif->tsf_low,
1402 scan_notif->tsf_high, scan_notif->status);
0cdc2136
SG		 1403
1404 /* The HW is no longer scanning */
1405 clear_bit(S_SCAN_HW, &il->status);
1406
1407 D_SCAN("Scan on %sGHz took %dms\n",
e7392364
SG		 1408 (il->scan_band == IEEE80211_BAND_2GHZ) ? "2.4" : "5.2",
1409 jiffies_to_msecs(jiffies - il->scan_start));
0cdc2136
SG		 1410
1411 queue_work(il->workqueue, &il->scan_completed);
1412}
1413
e7392364
SG		 1414void
1415il_setup_rx_scan_handlers(struct il_priv *il)
0cdc2136
SG		 1416{
1417 /* scan handlers */
1418 il->handlers[C_SCAN] = il_hdl_scan;
e7392364
SG		 1419 il->handlers[N_SCAN_START] = il_hdl_scan_start;
1420 il->handlers[N_SCAN_RESULTS] = il_hdl_scan_results;
1421 il->handlers[N_SCAN_COMPLETE] = il_hdl_scan_complete;
0cdc2136
SG		 1422}
1423EXPORT_SYMBOL(il_setup_rx_scan_handlers);
1424
e7392364
SG		 1425inline u16
1426il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1427 u8 n_probes)
0cdc2136
SG		 1428{
1429 if (band == IEEE80211_BAND_5GHZ)
1430 return IL_ACTIVE_DWELL_TIME_52 +
e7392364 1431 IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
0cdc2136
SG		 1432 else
1433 return IL_ACTIVE_DWELL_TIME_24 +
e7392364 1434 IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
0cdc2136
SG		 1435}
1436EXPORT_SYMBOL(il_get_active_dwell_time);
1437
e7392364 1438u16
1722f8e1
SG		 1439il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1440 struct ieee80211_vif *vif)
0cdc2136 1441{
0cdc2136
SG		 1442 u16 value;
1443
e7392364
SG		 1444 u16 passive =
1445 (band ==
1446 IEEE80211_BAND_2GHZ) ? IL_PASSIVE_DWELL_BASE +
1447 IL_PASSIVE_DWELL_TIME_24 : IL_PASSIVE_DWELL_BASE +
1448 IL_PASSIVE_DWELL_TIME_52;
0cdc2136
SG		 1449
1450 if (il_is_any_associated(il)) {
1451 /*
1452 * If we're associated, we clamp the maximum passive
1453 * dwell time to be 98% of the smallest beacon interval
1454 * (minus 2 * channel tune time)
1455 */
83007196 1456 value = il->vif ? il->vif->bss_conf.beacon_int : 0;
0cdc2136
SG		 1457 if (value > IL_PASSIVE_DWELL_BASE || !value)
1458 value = IL_PASSIVE_DWELL_BASE;
1459 value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2;
1460 passive = min(value, passive);
1461 }
1462
1463 return passive;
1464}
1465EXPORT_SYMBOL(il_get_passive_dwell_time);
1466
e7392364
SG		 1467void
1468il_init_scan_params(struct il_priv *il)
0cdc2136
SG		 1469{
1470 u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1;
1471 if (!il->scan_tx_ant[IEEE80211_BAND_5GHZ])
1472 il->scan_tx_ant[IEEE80211_BAND_5GHZ] = ant_idx;
1473 if (!il->scan_tx_ant[IEEE80211_BAND_2GHZ])
1474 il->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx;
1475}
1476EXPORT_SYMBOL(il_init_scan_params);
1477
e7392364
SG		 1478static int
1479il_scan_initiate(struct il_priv *il, struct ieee80211_vif *vif)
0cdc2136
SG		 1480{
1481 int ret;
1482
1483 lockdep_assert_held(&il->mutex);
1484
0cdc2136
SG		 1485 cancel_delayed_work(&il->scan_check);
1486
1487 if (!il_is_ready_rf(il)) {
1488 IL_WARN("Request scan called when driver not ready.\n");
1489 return -EIO;
1490 }
1491
1492 if (test_bit(S_SCAN_HW, &il->status)) {
e7392364 1493 D_SCAN("Multiple concurrent scan requests in parallel.\n");
0cdc2136
SG		 1494 return -EBUSY;
1495 }
1496
1497 if (test_bit(S_SCAN_ABORTING, &il->status)) {
1498 D_SCAN("Scan request while abort pending.\n");
1499 return -EBUSY;
1500 }
1501
1502 D_SCAN("Starting scan...\n");
1503
1504 set_bit(S_SCANNING, &il->status);
1505 il->scan_start = jiffies;
1506
c9363551 1507 ret = il->ops->request_scan(il, vif);
0cdc2136
SG		 1508 if (ret) {
1509 clear_bit(S_SCANNING, &il->status);
1510 return ret;
1511 }
1512
1513 queue_delayed_work(il->workqueue, &il->scan_check,
1514 IL_SCAN_CHECK_WATCHDOG);
1515
1516 return 0;
1517}
1518
e7392364
SG		 1519int
1520il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1521 struct cfg80211_scan_request *req)
0cdc2136
SG		 1522{
1523 struct il_priv *il = hw->priv;
1524 int ret;
1525
9ce7b73c
SG		 1526 if (req->n_channels == 0) {
1527 IL_ERR("Can not scan on no channels.\n");
0cdc2136 1528 return -EINVAL;
9ce7b73c 1529 }
0cdc2136
SG		 1530
1531 mutex_lock(&il->mutex);
9ce7b73c 1532 D_MAC80211("enter\n");
0cdc2136
SG		 1533
1534 if (test_bit(S_SCANNING, &il->status)) {
1535 D_SCAN("Scan already in progress.\n");
1536 ret = -EAGAIN;
1537 goto out_unlock;
1538 }
1539
1540 /* mac80211 will only ask for one band at a time */
1541 il->scan_request = req;
1542 il->scan_vif = vif;
1543 il->scan_band = req->channels[0]->band;
1544
1545 ret = il_scan_initiate(il, vif);
1546
0cdc2136 1547out_unlock:
9ce7b73c 1548 D_MAC80211("leave ret %d\n", ret);
0cdc2136
SG		 1549 mutex_unlock(&il->mutex);
1550
1551 return ret;
1552}
1553EXPORT_SYMBOL(il_mac_hw_scan);
1554
e7392364
SG		 1555static void
1556il_bg_scan_check(struct work_struct *data)
0cdc2136
SG		 1557{
1558 struct il_priv *il =
1559 container_of(data, struct il_priv, scan_check.work);
1560
1561 D_SCAN("Scan check work\n");
1562
1563 /* Since we are here firmware does not finish scan and
1564 * most likely is in bad shape, so we don't bother to
1565 * send abort command, just force scan complete to mac80211 */
1566 mutex_lock(&il->mutex);
1567 il_force_scan_end(il);
1568 mutex_unlock(&il->mutex);
1569}
1570
1571/**
1572 * il_fill_probe_req - fill in all required fields and IE for probe request
1573 */
1574
1575u16
1576il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1722f8e1 1577 const u8 *ta, const u8 *ies, int ie_len, int left)
0cdc2136
SG		 1578{
1579 int len = 0;
1580 u8 *pos = NULL;
1581
1582 /* Make sure there is enough space for the probe request,
1583 * two mandatory IEs and the data */
1584 left -= 24;
1585 if (left < 0)
1586 return 0;
1587
1588 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
1589 memcpy(frame->da, il_bcast_addr, ETH_ALEN);
1590 memcpy(frame->sa, ta, ETH_ALEN);
1591 memcpy(frame->bssid, il_bcast_addr, ETH_ALEN);
1592 frame->seq_ctrl = 0;
1593
1594 len += 24;
1595
1596 /* ...next IE... */
1597 pos = &frame->u.probe_req.variable[0];
1598
1599 /* fill in our indirect SSID IE */
1600 left -= 2;
1601 if (left < 0)
1602 return 0;
1603 *pos++ = WLAN_EID_SSID;
1604 *pos++ = 0;
1605
1606 len += 2;
1607
1608 if (WARN_ON(left < ie_len))
1609 return len;
1610
1611 if (ies && ie_len) {
1612 memcpy(pos, ies, ie_len);
1613 len += ie_len;
1614 }
1615
e7392364 1616 return (u16) len;
0cdc2136
SG		 1617}
1618EXPORT_SYMBOL(il_fill_probe_req);
1619
e7392364
SG		 1620static void
1621il_bg_abort_scan(struct work_struct *work)
0cdc2136
SG		 1622{
1623 struct il_priv *il = container_of(work, struct il_priv, abort_scan);
1624
1625 D_SCAN("Abort scan work\n");
1626
1627 /* We keep scan_check work queued in case when firmware will not
1628 * report back scan completed notification */
1629 mutex_lock(&il->mutex);
1630 il_scan_cancel_timeout(il, 200);
1631 mutex_unlock(&il->mutex);
1632}
1633
e7392364
SG		 1634static void
1635il_bg_scan_completed(struct work_struct *work)
0cdc2136 1636{
e7392364 1637 struct il_priv *il = container_of(work, struct il_priv, scan_completed);
0cdc2136
SG		 1638 bool aborted;
1639
1640 D_SCAN("Completed scan.\n");
1641
1642 cancel_delayed_work(&il->scan_check);
1643
1644 mutex_lock(&il->mutex);
1645
1646 aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status);
1647 if (aborted)
1648 D_SCAN("Aborted scan completed.\n");
1649
1650 if (!test_and_clear_bit(S_SCANNING, &il->status)) {
1651 D_SCAN("Scan already completed.\n");
1652 goto out_settings;
1653 }
1654
1655 il_complete_scan(il, aborted);
1656
1657out_settings:
1658 /* Can we still talk to firmware ? */
1659 if (!il_is_ready_rf(il))
1660 goto out;
1661
1662 /*
1663 * We do not commit power settings while scan is pending,
1664 * do it now if the settings changed.
1665 */
1666 il_power_set_mode(il, &il->power_data.sleep_cmd_next, false);
1667 il_set_tx_power(il, il->tx_power_next, false);
1668
c9363551 1669 il->ops->post_scan(il);
0cdc2136
SG		 1670
1671out:
1672 mutex_unlock(&il->mutex);
1673}
1674
e7392364
SG		 1675void
1676il_setup_scan_deferred_work(struct il_priv *il)
0cdc2136
SG		 1677{
1678 INIT_WORK(&il->scan_completed, il_bg_scan_completed);
1679 INIT_WORK(&il->abort_scan, il_bg_abort_scan);
1680 INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check);
1681}
1682EXPORT_SYMBOL(il_setup_scan_deferred_work);
1683
e7392364
SG		 1684void
1685il_cancel_scan_deferred_work(struct il_priv *il)
0cdc2136
SG		 1686{
1687 cancel_work_sync(&il->abort_scan);
1688 cancel_work_sync(&il->scan_completed);
1689
1690 if (cancel_delayed_work_sync(&il->scan_check)) {
1691 mutex_lock(&il->mutex);
1692 il_force_scan_end(il);
1693 mutex_unlock(&il->mutex);
1694 }
1695}
1696EXPORT_SYMBOL(il_cancel_scan_deferred_work);
1697
1698/* il->sta_lock must be held */
e7392364
SG		 1699static void
1700il_sta_ucode_activate(struct il_priv *il, u8 sta_id)
0cdc2136
SG		 1701{
1702
1703 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE))
e7392364
SG		 1704 IL_ERR("ACTIVATE a non DRIVER active station id %u addr %pM\n",
1705 sta_id, il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1706
1707 if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) {
e7392364
SG		 1708 D_ASSOC("STA id %u addr %pM already present"
1709 " in uCode (according to driver)\n", sta_id,
1710 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1711 } else {
1712 il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE;
e7392364
SG		 1713 D_ASSOC("Added STA id %u addr %pM to uCode\n", sta_id,
1714 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1715 }
1716}
1717
e7392364
SG		 1718static int
1719il_process_add_sta_resp(struct il_priv *il, struct il_addsta_cmd *addsta,
1720 struct il_rx_pkt *pkt, bool sync)
0cdc2136
SG		 1721{
1722 u8 sta_id = addsta->sta.sta_id;
1723 unsigned long flags;
1724 int ret = -EIO;
1725
1726 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
e7392364 1727 IL_ERR("Bad return from C_ADD_STA (0x%08X)\n", pkt->hdr.flags);
0cdc2136
SG		 1728 return ret;
1729 }
1730
e7392364 1731 D_INFO("Processing response for adding station %u\n", sta_id);
0cdc2136
SG		 1732
1733 spin_lock_irqsave(&il->sta_lock, flags);
1734
1735 switch (pkt->u.add_sta.status) {
1736 case ADD_STA_SUCCESS_MSK:
1737 D_INFO("C_ADD_STA PASSED\n");
1738 il_sta_ucode_activate(il, sta_id);
1739 ret = 0;
1740 break;
1741 case ADD_STA_NO_ROOM_IN_TBL:
e7392364 1742 IL_ERR("Adding station %d failed, no room in table.\n", sta_id);
0cdc2136
SG		 1743 break;
1744 case ADD_STA_NO_BLOCK_ACK_RESOURCE:
e7392364
SG		 1745 IL_ERR("Adding station %d failed, no block ack resource.\n",
1746 sta_id);
0cdc2136
SG		 1747 break;
1748 case ADD_STA_MODIFY_NON_EXIST_STA:
1749 IL_ERR("Attempting to modify non-existing station %d\n",
e7392364 1750 sta_id);
0cdc2136
SG		 1751 break;
1752 default:
e7392364 1753 D_ASSOC("Received C_ADD_STA:(0x%08X)\n", pkt->u.add_sta.status);
0cdc2136
SG		 1754 break;
1755 }
1756
1757 D_INFO("%s station id %u addr %pM\n",
e7392364
SG		 1758 il->stations[sta_id].sta.mode ==
1759 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", sta_id,
1760 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1761
1762 /*
1763 * XXX: The MAC address in the command buffer is often changed from
1764 * the original sent to the device. That is, the MAC address
1765 * written to the command buffer often is not the same MAC address
1766 * read from the command buffer when the command returns. This
1767 * issue has not yet been resolved and this debugging is left to
1768 * observe the problem.
1769 */
1770 D_INFO("%s station according to cmd buffer %pM\n",
e7392364
SG		 1771 il->stations[sta_id].sta.mode ==
1772 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", addsta->sta.addr);
0cdc2136
SG		 1773 spin_unlock_irqrestore(&il->sta_lock, flags);
1774
1775 return ret;
1776}
1777
e7392364
SG		 1778static void
1779il_add_sta_callback(struct il_priv *il, struct il_device_cmd *cmd,
1780 struct il_rx_pkt *pkt)
0cdc2136 1781{
e7392364 1782 struct il_addsta_cmd *addsta = (struct il_addsta_cmd *)cmd->cmd.payload;
0cdc2136
SG		 1783
1784 il_process_add_sta_resp(il, addsta, pkt, false);
1785
1786}
1787
e7392364
SG		 1788int
1789il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags)
0cdc2136
SG		 1790{
1791 struct il_rx_pkt *pkt = NULL;
1792 int ret = 0;
1793 u8 data[sizeof(*sta)];
1794 struct il_host_cmd cmd = {
1795 .id = C_ADD_STA,
1796 .flags = flags,
1797 .data = data,
1798 };
1799 u8 sta_id __maybe_unused = sta->sta.sta_id;
1800
e7392364
SG		 1801 D_INFO("Adding sta %u (%pM) %ssynchronously\n", sta_id, sta->sta.addr,
1802 flags & CMD_ASYNC ? "a" : "");
0cdc2136
SG		 1803
1804 if (flags & CMD_ASYNC)
1805 cmd.callback = il_add_sta_callback;
1806 else {
1807 cmd.flags |= CMD_WANT_SKB;
1808 might_sleep();
1809 }
1810
c9363551 1811 cmd.len = il->ops->build_addsta_hcmd(sta, data);
0cdc2136
SG		 1812 ret = il_send_cmd(il, &cmd);
1813
1814 if (ret || (flags & CMD_ASYNC))
1815 return ret;
1816
1817 if (ret == 0) {
1818 pkt = (struct il_rx_pkt *)cmd.reply_page;
1819 ret = il_process_add_sta_resp(il, sta, pkt, true);
1820 }
1821 il_free_pages(il, cmd.reply_page);
1822
1823 return ret;
1824}
1825EXPORT_SYMBOL(il_send_add_sta);
1826
e7392364 1827static void
83007196 1828il_set_ht_add_station(struct il_priv *il, u8 idx, struct ieee80211_sta *sta)
0cdc2136
SG		 1829{
1830 struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->ht_cap;
1831 __le32 sta_flags;
1832 u8 mimo_ps_mode;
1833
1834 if (!sta || !sta_ht_inf->ht_supported)
1835 goto done;
1836
1837 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_SM_PS) >> 2;
1838 D_ASSOC("spatial multiplexing power save mode: %s\n",
1722f8e1
SG		 1839 (mimo_ps_mode == WLAN_HT_CAP_SM_PS_STATIC) ? "static" :
1840 (mimo_ps_mode == WLAN_HT_CAP_SM_PS_DYNAMIC) ? "dynamic" :
1841 "disabled");
0cdc2136
SG		 1842
1843 sta_flags = il->stations[idx].sta.station_flags;
1844
1845 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
1846
1847 switch (mimo_ps_mode) {
1848 case WLAN_HT_CAP_SM_PS_STATIC:
1849 sta_flags |= STA_FLG_MIMO_DIS_MSK;
1850 break;
1851 case WLAN_HT_CAP_SM_PS_DYNAMIC:
1852 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
1853 break;
1854 case WLAN_HT_CAP_SM_PS_DISABLED:
1855 break;
1856 default:
1857 IL_WARN("Invalid MIMO PS mode %d\n", mimo_ps_mode);
1858 break;
1859 }
1860
e7392364
SG		 1861 sta_flags |=
1862 cpu_to_le32((u32) sta_ht_inf->
1863 ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
0cdc2136 1864
e7392364
SG		 1865 sta_flags |=
1866 cpu_to_le32((u32) sta_ht_inf->
1867 ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
0cdc2136 1868
83007196 1869 if (il_is_ht40_tx_allowed(il, &sta->ht_cap))
0cdc2136
SG		 1870 sta_flags |= STA_FLG_HT40_EN_MSK;
1871 else
1872 sta_flags &= ~STA_FLG_HT40_EN_MSK;
1873
1874 il->stations[idx].sta.station_flags = sta_flags;
e7392364 1875done:
0cdc2136
SG		 1876 return;
1877}
1878
1879/**
1880 * il_prep_station - Prepare station information for addition
1881 *
1882 * should be called with sta_lock held
1883 */
e7392364 1884u8
83007196
SG		 1885il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
1886 struct ieee80211_sta *sta)
0cdc2136
SG		 1887{
1888 struct il_station_entry *station;
1889 int i;
1890 u8 sta_id = IL_INVALID_STATION;
1891 u16 rate;
1892
1893 if (is_ap)
8f9e5645 1894 sta_id = IL_AP_ID;
0cdc2136 1895 else if (is_broadcast_ether_addr(addr))
b16db50a 1896 sta_id = il->hw_params.bcast_id;
0cdc2136
SG		 1897 else
1898 for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) {
2e42e474
JP		 1899 if (ether_addr_equal(il->stations[i].sta.sta.addr,
1900 addr)) {
0cdc2136
SG		 1901 sta_id = i;
1902 break;
1903 }
1904
1905 if (!il->stations[i].used &&
1906 sta_id == IL_INVALID_STATION)
1907 sta_id = i;
1908 }
1909
1910 /*
1911 * These two conditions have the same outcome, but keep them
1912 * separate
1913 */
1914 if (unlikely(sta_id == IL_INVALID_STATION))
1915 return sta_id;
1916
1917 /*
1918 * uCode is not able to deal with multiple requests to add a
1919 * station. Keep track if one is in progress so that we do not send
1920 * another.
1921 */
1922 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
e7392364 1923 D_INFO("STA %d already in process of being added.\n", sta_id);
0cdc2136
SG		 1924 return sta_id;
1925 }
1926
1927 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
1928 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) &&
2e42e474 1929 ether_addr_equal(il->stations[sta_id].sta.sta.addr, addr)) {
e7392364
SG		 1930 D_ASSOC("STA %d (%pM) already added, not adding again.\n",
1931 sta_id, addr);
0cdc2136
SG		 1932 return sta_id;
1933 }
1934
1935 station = &il->stations[sta_id];
1936 station->used = IL_STA_DRIVER_ACTIVE;
e7392364 1937 D_ASSOC("Add STA to driver ID %d: %pM\n", sta_id, addr);
0cdc2136
SG		 1938 il->num_stations++;
1939
1940 /* Set up the C_ADD_STA command to send to device */
1941 memset(&station->sta, 0, sizeof(struct il_addsta_cmd));
1942 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
1943 station->sta.mode = 0;
1944 station->sta.sta.sta_id = sta_id;
fd6415bc 1945 station->sta.station_flags = 0;
0cdc2136 1946
0cdc2136
SG		 1947 /*
1948 * OK to call unconditionally, since local stations (IBSS BSSID
1949 * STA and broadcast STA) pass in a NULL sta, and mac80211
1950 * doesn't allow HT IBSS.
1951 */
83007196 1952 il_set_ht_add_station(il, sta_id, sta);
0cdc2136
SG		 1953
1954 /* 3945 only */
e7392364 1955 rate = (il->band == IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP : RATE_1M_PLCP;
0cdc2136
SG		 1956 /* Turn on both antennas for the station... */
1957 station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK);
1958
1959 return sta_id;
1960
1961}
1962EXPORT_SYMBOL_GPL(il_prep_station);
1963
1964#define STA_WAIT_TIMEOUT (HZ/2)
1965
1966/**
1967 * il_add_station_common -
1968 */
1969int
83007196
SG		 1970il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
1971 struct ieee80211_sta *sta, u8 *sta_id_r)
0cdc2136
SG		 1972{
1973 unsigned long flags_spin;
1974 int ret = 0;
1975 u8 sta_id;
1976 struct il_addsta_cmd sta_cmd;
1977
1978 *sta_id_r = 0;
1979 spin_lock_irqsave(&il->sta_lock, flags_spin);
83007196 1980 sta_id = il_prep_station(il, addr, is_ap, sta);
0cdc2136 1981 if (sta_id == IL_INVALID_STATION) {
e7392364 1982 IL_ERR("Unable to prepare station %pM for addition\n", addr);
0cdc2136
SG		 1983 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
1984 return -EINVAL;
1985 }
1986
1987 /*
1988 * uCode is not able to deal with multiple requests to add a
1989 * station. Keep track if one is in progress so that we do not send
1990 * another.
1991 */
1992 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
e7392364 1993 D_INFO("STA %d already in process of being added.\n", sta_id);
0cdc2136
SG		 1994 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
1995 return -EEXIST;
1996 }
1997
1998 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
1999 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
e7392364 2000 D_ASSOC("STA %d (%pM) already added, not adding again.\n",
0cdc2136
SG		 2001 sta_id, addr);
2002 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2003 return -EEXIST;
2004 }
2005
2006 il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS;
2007 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 2008 sizeof(struct il_addsta_cmd));
0cdc2136
SG		 2009 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2010
2011 /* Add station to device's station table */
2012 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2013 if (ret) {
2014 spin_lock_irqsave(&il->sta_lock, flags_spin);
2015 IL_ERR("Adding station %pM failed.\n",
e7392364 2016 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 2017 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
2018 il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
2019 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2020 }
2021 *sta_id_r = sta_id;
2022 return ret;
2023}
2024EXPORT_SYMBOL(il_add_station_common);
2025
2026/**
2027 * il_sta_ucode_deactivate - deactivate ucode status for a station
2028 *
2029 * il->sta_lock must be held
2030 */
e7392364
SG		 2031static void
2032il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id)
0cdc2136
SG		 2033{
2034 /* Ucode must be active and driver must be non active */
e7392364
SG		 2035 if ((il->stations[sta_id].
2036 used & (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) !=
2037 IL_STA_UCODE_ACTIVE)
0cdc2136
SG		 2038 IL_ERR("removed non active STA %u\n", sta_id);
2039
2040 il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE;
2041
2042 memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry));
2043 D_ASSOC("Removed STA %u\n", sta_id);
2044}
2045
e7392364
SG		 2046static int
2047il_send_remove_station(struct il_priv *il, const u8 * addr, int sta_id,
2048 bool temporary)
0cdc2136
SG		 2049{
2050 struct il_rx_pkt *pkt;
2051 int ret;
2052
2053 unsigned long flags_spin;
2054 struct il_rem_sta_cmd rm_sta_cmd;
2055
2056 struct il_host_cmd cmd = {
2057 .id = C_REM_STA,
2058 .len = sizeof(struct il_rem_sta_cmd),
2059 .flags = CMD_SYNC,
2060 .data = &rm_sta_cmd,
2061 };
2062
2063 memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd));
2064 rm_sta_cmd.num_sta = 1;
2065 memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN);
2066
2067 cmd.flags |= CMD_WANT_SKB;
2068
2069 ret = il_send_cmd(il, &cmd);
2070
2071 if (ret)
2072 return ret;
2073
2074 pkt = (struct il_rx_pkt *)cmd.reply_page;
2075 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
e7392364 2076 IL_ERR("Bad return from C_REM_STA (0x%08X)\n", pkt->hdr.flags);
0cdc2136
SG		 2077 ret = -EIO;
2078 }
2079
2080 if (!ret) {
2081 switch (pkt->u.rem_sta.status) {
2082 case REM_STA_SUCCESS_MSK:
2083 if (!temporary) {
2084 spin_lock_irqsave(&il->sta_lock, flags_spin);
2085 il_sta_ucode_deactivate(il, sta_id);
2086 spin_unlock_irqrestore(&il->sta_lock,
e7392364 2087 flags_spin);
0cdc2136
SG		 2088 }
2089 D_ASSOC("C_REM_STA PASSED\n");
2090 break;
2091 default:
2092 ret = -EIO;
2093 IL_ERR("C_REM_STA failed\n");
2094 break;
2095 }
2096 }
2097 il_free_pages(il, cmd.reply_page);
2098
2099 return ret;
2100}
2101
2102/**
2103 * il_remove_station - Remove driver's knowledge of station.
2104 */
e7392364
SG		 2105int
2106il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr)
0cdc2136
SG		 2107{
2108 unsigned long flags;
2109
2110 if (!il_is_ready(il)) {
e7392364
SG		 2111 D_INFO("Unable to remove station %pM, device not ready.\n",
2112 addr);
0cdc2136
SG		 2113 /*
2114 * It is typical for stations to be removed when we are
2115 * going down. Return success since device will be down
2116 * soon anyway
2117 */
2118 return 0;
2119 }
2120
e7392364 2121 D_ASSOC("Removing STA from driver:%d %pM\n", sta_id, addr);
0cdc2136
SG		 2122
2123 if (WARN_ON(sta_id == IL_INVALID_STATION))
2124 return -EINVAL;
2125
2126 spin_lock_irqsave(&il->sta_lock, flags);
2127
2128 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) {
e7392364 2129 D_INFO("Removing %pM but non DRIVER active\n", addr);
0cdc2136
SG		 2130 goto out_err;
2131 }
2132
2133 if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
e7392364 2134 D_INFO("Removing %pM but non UCODE active\n", addr);
0cdc2136
SG		 2135 goto out_err;
2136 }
2137
2138 if (il->stations[sta_id].used & IL_STA_LOCAL) {
2139 kfree(il->stations[sta_id].lq);
2140 il->stations[sta_id].lq = NULL;
2141 }
2142
2143 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
2144
2145 il->num_stations--;
2146
2147 BUG_ON(il->num_stations < 0);
2148
2149 spin_unlock_irqrestore(&il->sta_lock, flags);
2150
2151 return il_send_remove_station(il, addr, sta_id, false);
2152out_err:
2153 spin_unlock_irqrestore(&il->sta_lock, flags);
2154 return -EINVAL;
2155}
2156EXPORT_SYMBOL_GPL(il_remove_station);
2157
2158/**
2159 * il_clear_ucode_stations - clear ucode station table bits
2160 *
2161 * This function clears all the bits in the driver indicating
2162 * which stations are active in the ucode. Call when something
2163 * other than explicit station management would cause this in
2164 * the ucode, e.g. unassociated RXON.
2165 */
e7392364 2166void
83007196 2167il_clear_ucode_stations(struct il_priv *il)
0cdc2136
SG		 2168{
2169 int i;
2170 unsigned long flags_spin;
2171 bool cleared = false;
2172
2173 D_INFO("Clearing ucode stations in driver\n");
2174
2175 spin_lock_irqsave(&il->sta_lock, flags_spin);
2176 for (i = 0; i < il->hw_params.max_stations; i++) {
0cdc2136 2177 if (il->stations[i].used & IL_STA_UCODE_ACTIVE) {
e7392364 2178 D_INFO("Clearing ucode active for station %d\n", i);
0cdc2136
SG		 2179 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2180 cleared = true;
2181 }
2182 }
2183 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2184
2185 if (!cleared)
e7392364 2186 D_INFO("No active stations found to be cleared\n");
0cdc2136
SG		 2187}
2188EXPORT_SYMBOL(il_clear_ucode_stations);
2189
2190/**
2191 * il_restore_stations() - Restore driver known stations to device
2192 *
2193 * All stations considered active by driver, but not present in ucode, is
2194 * restored.
2195 *
2196 * Function sleeps.
2197 */
2198void
83007196 2199il_restore_stations(struct il_priv *il)
0cdc2136
SG		 2200{
2201 struct il_addsta_cmd sta_cmd;
2202 struct il_link_quality_cmd lq;
2203 unsigned long flags_spin;
2204 int i;
2205 bool found = false;
2206 int ret;
2207 bool send_lq;
2208
2209 if (!il_is_ready(il)) {
e7392364 2210 D_INFO("Not ready yet, not restoring any stations.\n");
0cdc2136
SG		 2211 return;
2212 }
2213
2214 D_ASSOC("Restoring all known stations ... start.\n");
2215 spin_lock_irqsave(&il->sta_lock, flags_spin);
2216 for (i = 0; i < il->hw_params.max_stations; i++) {
0cdc2136
SG		 2217 if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) &&
2218 !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) {
2219 D_ASSOC("Restoring sta %pM\n",
e7392364 2220 il->stations[i].sta.sta.addr);
0cdc2136
SG		 2221 il->stations[i].sta.mode = 0;
2222 il->stations[i].used |= IL_STA_UCODE_INPROGRESS;
2223 found = true;
2224 }
2225 }
2226
2227 for (i = 0; i < il->hw_params.max_stations; i++) {
2228 if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) {
2229 memcpy(&sta_cmd, &il->stations[i].sta,
2230 sizeof(struct il_addsta_cmd));
2231 send_lq = false;
2232 if (il->stations[i].lq) {
2233 memcpy(&lq, il->stations[i].lq,
2234 sizeof(struct il_link_quality_cmd));
2235 send_lq = true;
2236 }
2237 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2238 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2239 if (ret) {
2240 spin_lock_irqsave(&il->sta_lock, flags_spin);
2241 IL_ERR("Adding station %pM failed.\n",
e7392364
SG		 2242 il->stations[i].sta.sta.addr);
2243 il->stations[i].used &= ~IL_STA_DRIVER_ACTIVE;
0cdc2136 2244 il->stations[i].used &=
e7392364 2245 ~IL_STA_UCODE_INPROGRESS;
0cdc2136 2246 spin_unlock_irqrestore(&il->sta_lock,
e7392364 2247 flags_spin);
0cdc2136
SG		 2248 }
2249 /*
2250 * Rate scaling has already been initialized, send
2251 * current LQ command
2252 */
2253 if (send_lq)
83007196 2254 il_send_lq_cmd(il, &lq, CMD_SYNC, true);
0cdc2136
SG		 2255 spin_lock_irqsave(&il->sta_lock, flags_spin);
2256 il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS;
2257 }
2258 }
2259
2260 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2261 if (!found)
2262 D_INFO("Restoring all known stations"
e7392364 2263 " .... no stations to be restored.\n");
0cdc2136 2264 else
e7392364 2265 D_INFO("Restoring all known stations" " .... complete.\n");
0cdc2136
SG		 2266}
2267EXPORT_SYMBOL(il_restore_stations);
2268
e7392364
SG		 2269int
2270il_get_free_ucode_key_idx(struct il_priv *il)
0cdc2136
SG		 2271{
2272 int i;
2273
2274 for (i = 0; i < il->sta_key_max_num; i++)
2275 if (!test_and_set_bit(i, &il->ucode_key_table))
2276 return i;
2277
2278 return WEP_INVALID_OFFSET;
2279}
2280EXPORT_SYMBOL(il_get_free_ucode_key_idx);
2281
e7392364
SG		 2282void
2283il_dealloc_bcast_stations(struct il_priv *il)
0cdc2136
SG		 2284{
2285 unsigned long flags;
2286 int i;
2287
2288 spin_lock_irqsave(&il->sta_lock, flags);
2289 for (i = 0; i < il->hw_params.max_stations; i++) {
2290 if (!(il->stations[i].used & IL_STA_BCAST))
2291 continue;
2292
2293 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2294 il->num_stations--;
2295 BUG_ON(il->num_stations < 0);
2296 kfree(il->stations[i].lq);
2297 il->stations[i].lq = NULL;
2298 }
2299 spin_unlock_irqrestore(&il->sta_lock, flags);
2300}
2301EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations);
2302
2303#ifdef CONFIG_IWLEGACY_DEBUG
e7392364
SG		 2304static void
2305il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG		 2306{
2307 int i;
2308 D_RATE("lq station id 0x%x\n", lq->sta_id);
e7392364
SG		 2309 D_RATE("lq ant 0x%X 0x%X\n", lq->general_params.single_stream_ant_msk,
2310 lq->general_params.dual_stream_ant_msk);
0cdc2136
SG		 2311
2312 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
e7392364 2313 D_RATE("lq idx %d 0x%X\n", i, lq->rs_table[i].rate_n_flags);
0cdc2136
SG		 2314}
2315#else
e7392364
SG		 2316static inline void
2317il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG		 2318{
2319}
2320#endif
2321
2322/**
2323 * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity
2324 *
2325 * It sometimes happens when a HT rate has been in use and we
2326 * loose connectivity with AP then mac80211 will first tell us that the
2327 * current channel is not HT anymore before removing the station. In such a
2328 * scenario the RXON flags will be updated to indicate we are not
2329 * communicating HT anymore, but the LQ command may still contain HT rates.
2330 * Test for this to prevent driver from sending LQ command between the time
2331 * RXON flags are updated and when LQ command is updated.
2332 */
e7392364 2333static bool
83007196 2334il_is_lq_table_valid(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG		 2335{
2336 int i;
2337
1c03c462 2338 if (il->ht.enabled)
0cdc2136
SG		 2339 return true;
2340
c8b03958 2341 D_INFO("Channel %u is not an HT channel\n", il->active.channel);
0cdc2136 2342 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
e7392364
SG		 2343 if (le32_to_cpu(lq->rs_table[i].rate_n_flags) & RATE_MCS_HT_MSK) {
2344 D_INFO("idx %d of LQ expects HT channel\n", i);
0cdc2136
SG		 2345 return false;
2346 }
2347 }
2348 return true;
2349}
2350
2351/**
2352 * il_send_lq_cmd() - Send link quality command
2353 * @init: This command is sent as part of station initialization right
2354 * after station has been added.
2355 *
2356 * The link quality command is sent as the last step of station creation.
2357 * This is the special case in which init is set and we call a callback in
2358 * this case to clear the state indicating that station creation is in
2359 * progress.
2360 */
e7392364 2361int
83007196
SG		 2362il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2363 u8 flags, bool init)
0cdc2136
SG		 2364{
2365 int ret = 0;
2366 unsigned long flags_spin;
2367
2368 struct il_host_cmd cmd = {
2369 .id = C_TX_LINK_QUALITY_CMD,
2370 .len = sizeof(struct il_link_quality_cmd),
2371 .flags = flags,
2372 .data = lq,
2373 };
2374
2375 if (WARN_ON(lq->sta_id == IL_INVALID_STATION))
2376 return -EINVAL;
2377
0cdc2136
SG		 2378 spin_lock_irqsave(&il->sta_lock, flags_spin);
2379 if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) {
2380 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2381 return -EINVAL;
2382 }
2383 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2384
2385 il_dump_lq_cmd(il, lq);
2386 BUG_ON(init && (cmd.flags & CMD_ASYNC));
2387
83007196 2388 if (il_is_lq_table_valid(il, lq))
0cdc2136
SG		 2389 ret = il_send_cmd(il, &cmd);
2390 else
2391 ret = -EINVAL;
2392
2393 if (cmd.flags & CMD_ASYNC)
2394 return ret;
2395
2396 if (init) {
2397 D_INFO("init LQ command complete,"
e7392364
SG		 2398 " clearing sta addition status for sta %d\n",
2399 lq->sta_id);
0cdc2136
SG		 2400 spin_lock_irqsave(&il->sta_lock, flags_spin);
2401 il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
2402 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2403 }
2404 return ret;
2405}
2406EXPORT_SYMBOL(il_send_lq_cmd);
2407
e7392364
SG		 2408int
2409il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2410 struct ieee80211_sta *sta)
0cdc2136
SG		 2411{
2412 struct il_priv *il = hw->priv;
2413 struct il_station_priv_common *sta_common = (void *)sta->drv_priv;
2414 int ret;
2415
0cdc2136 2416 mutex_lock(&il->mutex);
9ce7b73c
SG		 2417 D_MAC80211("enter station %pM\n", sta->addr);
2418
0cdc2136
SG		 2419 ret = il_remove_station(il, sta_common->sta_id, sta->addr);
2420 if (ret)
e7392364 2421 IL_ERR("Error removing station %pM\n", sta->addr);
9ce7b73c
SG		 2422
2423 D_MAC80211("leave ret %d\n", ret);
0cdc2136 2424 mutex_unlock(&il->mutex);
9ce7b73c 2425
0cdc2136
SG		 2426 return ret;
2427}
2428EXPORT_SYMBOL(il_mac_sta_remove);
2429
2430/************************** RX-FUNCTIONS ****************************/
2431/*
2432 * Rx theory of operation
2433 *
2434 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
2435 * each of which point to Receive Buffers to be filled by the NIC. These get
2436 * used not only for Rx frames, but for any command response or notification
2437 * from the NIC. The driver and NIC manage the Rx buffers by means
2438 * of idxes into the circular buffer.
2439 *
2440 * Rx Queue Indexes
2441 * The host/firmware share two idx registers for managing the Rx buffers.
2442 *
2443 * The READ idx maps to the first position that the firmware may be writing
2444 * to -- the driver can read up to (but not including) this position and get
2445 * good data.
2446 * The READ idx is managed by the firmware once the card is enabled.
2447 *
2448 * The WRITE idx maps to the last position the driver has read from -- the
2449 * position preceding WRITE is the last slot the firmware can place a packet.
2450 *
2451 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
2452 * WRITE = READ.
2453 *
2454 * During initialization, the host sets up the READ queue position to the first
2455 * IDX position, and WRITE to the last (READ - 1 wrapped)
2456 *
2457 * When the firmware places a packet in a buffer, it will advance the READ idx
2458 * and fire the RX interrupt. The driver can then query the READ idx and
2459 * process as many packets as possible, moving the WRITE idx forward as it
2460 * resets the Rx queue buffers with new memory.
2461 *
2462 * The management in the driver is as follows:
2463 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
2464 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
2465 * to replenish the iwl->rxq->rx_free.
2466 * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the
2467 * iwl->rxq is replenished and the READ IDX is updated (updating the
2468 * 'processed' and 'read' driver idxes as well)
2469 * + A received packet is processed and handed to the kernel network stack,
2470 * detached from the iwl->rxq. The driver 'processed' idx is updated.
2471 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
2472 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
2473 * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
2474 * were enough free buffers and RX_STALLED is set it is cleared.
2475 *
2476 *
2477 * Driver sequence:
2478 *
2479 * il_rx_queue_alloc() Allocates rx_free
2480 * il_rx_replenish() Replenishes rx_free list from rx_used, and calls
2481 * il_rx_queue_restock
2482 * il_rx_queue_restock() Moves available buffers from rx_free into Rx
2483 * queue, updates firmware pointers, and updates
2484 * the WRITE idx. If insufficient rx_free buffers
2485 * are available, schedules il_rx_replenish
2486 *
2487 * -- enable interrupts --
2488 * ISR - il_rx() Detach il_rx_bufs from pool up to the
2489 * READ IDX, detaching the SKB from the pool.
2490 * Moves the packet buffer from queue to rx_used.
2491 * Calls il_rx_queue_restock to refill any empty
2492 * slots.
2493 * ...
2494 *
2495 */
2496
2497/**
2498 * il_rx_queue_space - Return number of free slots available in queue.
2499 */
e7392364
SG		 2500int
2501il_rx_queue_space(const struct il_rx_queue *q)
0cdc2136
SG		 2502{
2503 int s = q->read - q->write;
2504 if (s <= 0)
2505 s += RX_QUEUE_SIZE;
2506 /* keep some buffer to not confuse full and empty queue */
2507 s -= 2;
2508 if (s < 0)
2509 s = 0;
2510 return s;
2511}
2512EXPORT_SYMBOL(il_rx_queue_space);
2513
2514/**
2515 * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue
2516 */
2517void
e7392364 2518il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q)
0cdc2136
SG		 2519{
2520 unsigned long flags;
2521 u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg;
2522 u32 reg;
2523
2524 spin_lock_irqsave(&q->lock, flags);
2525
2526 if (q->need_update == 0)
2527 goto exit_unlock;
2528
2529 /* If power-saving is in use, make sure device is awake */
2530 if (test_bit(S_POWER_PMI, &il->status)) {
2531 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2532
2533 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
e7392364
SG		 2534 D_INFO("Rx queue requesting wakeup," " GP1 = 0x%x\n",
2535 reg);
0cdc2136 2536 il_set_bit(il, CSR_GP_CNTRL,
e7392364 2537 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
0cdc2136
SG		 2538 goto exit_unlock;
2539 }
2540
2541 q->write_actual = (q->write & ~0x7);
e7392364 2542 il_wr(il, rx_wrt_ptr_reg, q->write_actual);
0cdc2136 2543
e7392364 2544 /* Else device is assumed to be awake */
0cdc2136
SG		 2545 } else {
2546 /* Device expects a multiple of 8 */
2547 q->write_actual = (q->write & ~0x7);
e7392364 2548 il_wr(il, rx_wrt_ptr_reg, q->write_actual);
0cdc2136
SG		 2549 }
2550
2551 q->need_update = 0;
2552
e7392364 2553exit_unlock:
0cdc2136
SG		 2554 spin_unlock_irqrestore(&q->lock, flags);
2555}
2556EXPORT_SYMBOL(il_rx_queue_update_write_ptr);
2557
e7392364
SG		 2558int
2559il_rx_queue_alloc(struct il_priv *il)
0cdc2136
SG		 2560{
2561 struct il_rx_queue *rxq = &il->rxq;
2562 struct device *dev = &il->pci_dev->dev;
2563 int i;
2564
2565 spin_lock_init(&rxq->lock);
2566 INIT_LIST_HEAD(&rxq->rx_free);
2567 INIT_LIST_HEAD(&rxq->rx_used);
2568
2569 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
e7392364
SG		 2570 rxq->bd =
2571 dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
2572 GFP_KERNEL);
0cdc2136
SG		 2573 if (!rxq->bd)
2574 goto err_bd;
2575
e7392364
SG		 2576 rxq->rb_stts =
2577 dma_alloc_coherent(dev, sizeof(struct il_rb_status),
2578 &rxq->rb_stts_dma, GFP_KERNEL);
0cdc2136
SG		 2579 if (!rxq->rb_stts)
2580 goto err_rb;
2581
2582 /* Fill the rx_used queue with _all_ of the Rx buffers */
2583 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
2584 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
2585
2586 /* Set us so that we have processed and used all buffers, but have
2587 * not restocked the Rx queue with fresh buffers */
2588 rxq->read = rxq->write = 0;
2589 rxq->write_actual = 0;
2590 rxq->free_count = 0;
2591 rxq->need_update = 0;
2592 return 0;
2593
2594err_rb:
2595 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
2596 rxq->bd_dma);
2597err_bd:
2598 return -ENOMEM;
2599}
e7392364 2600EXPORT_SYMBOL(il_rx_queue_alloc);
0cdc2136 2601
e7392364
SG		 2602void
2603il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 2604{
2605 struct il_rx_pkt *pkt = rxb_addr(rxb);
2606 struct il_spectrum_notification *report = &(pkt->u.spectrum_notif);
2607
2608 if (!report->state) {
e7392364 2609 D_11H("Spectrum Measure Notification: Start\n");
0cdc2136
SG		 2610 return;
2611 }
2612
2613 memcpy(&il->measure_report, report, sizeof(*report));
2614 il->measurement_status |= MEASUREMENT_READY;
2615}
2616EXPORT_SYMBOL(il_hdl_spectrum_measurement);
2617
2618/*
2619 * returns non-zero if packet should be dropped
2620 */
e7392364
SG		 2621int
2622il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
2623 u32 decrypt_res, struct ieee80211_rx_status *stats)
0cdc2136
SG		 2624{
2625 u16 fc = le16_to_cpu(hdr->frame_control);
2626
2627 /*
2628 * All contexts have the same setting here due to it being
2629 * a module parameter, so OK to check any context.
2630 */
c8b03958 2631 if (il->active.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
0cdc2136
SG		 2632 return 0;
2633
2634 if (!(fc & IEEE80211_FCTL_PROTECTED))
2635 return 0;
2636
2637 D_RX("decrypt_res:0x%x\n", decrypt_res);
2638 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2639 case RX_RES_STATUS_SEC_TYPE_TKIP:
2640 /* The uCode has got a bad phase 1 Key, pushes the packet.
2641 * Decryption will be done in SW. */
2642 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2643 RX_RES_STATUS_BAD_KEY_TTAK)
2644 break;
2645
2646 case RX_RES_STATUS_SEC_TYPE_WEP:
2647 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2648 RX_RES_STATUS_BAD_ICV_MIC) {
2649 /* bad ICV, the packet is destroyed since the
2650 * decryption is inplace, drop it */
2651 D_RX("Packet destroyed\n");
2652 return -1;
2653 }
2654 case RX_RES_STATUS_SEC_TYPE_CCMP:
2655 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2656 RX_RES_STATUS_DECRYPT_OK) {
2657 D_RX("hw decrypt successfully!!!\n");
2658 stats->flag |= RX_FLAG_DECRYPTED;
2659 }
2660 break;
2661
2662 default:
2663 break;
2664 }
2665 return 0;
2666}
2667EXPORT_SYMBOL(il_set_decrypted_flag);
2668
2669/**
2670 * il_txq_update_write_ptr - Send new write idx to hardware
2671 */
2672void
2673il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq)
2674{
2675 u32 reg = 0;
2676 int txq_id = txq->q.id;
2677
2678 if (txq->need_update == 0)
2679 return;
2680
2681 /* if we're trying to save power */
2682 if (test_bit(S_POWER_PMI, &il->status)) {
2683 /* wake up nic if it's powered down ...
2684 * uCode will wake up, and interrupt us again, so next
2685 * time we'll skip this part. */
2686 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2687
2688 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
e7392364
SG		 2689 D_INFO("Tx queue %d requesting wakeup," " GP1 = 0x%x\n",
2690 txq_id, reg);
0cdc2136 2691 il_set_bit(il, CSR_GP_CNTRL,
e7392364 2692 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
0cdc2136
SG		 2693 return;
2694 }
2695
e7392364 2696 il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
0cdc2136
SG		 2697
2698 /*
2699 * else not in power-save mode,
2700 * uCode will never sleep when we're
2701 * trying to tx (during RFKILL, we're not trying to tx).
2702 */
2703 } else
e7392364 2704 _il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
0cdc2136
SG		 2705 txq->need_update = 0;
2706}
2707EXPORT_SYMBOL(il_txq_update_write_ptr);
2708
2709/**
2710 * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
2711 */
e7392364
SG		 2712void
2713il_tx_queue_unmap(struct il_priv *il, int txq_id)
0cdc2136
SG		 2714{
2715 struct il_tx_queue *txq = &il->txq[txq_id];
2716 struct il_queue *q = &txq->q;
2717
2718 if (q->n_bd == 0)
2719 return;
2720
2721 while (q->write_ptr != q->read_ptr) {
1600b875 2722 il->ops->txq_free_tfd(il, txq);
0cdc2136
SG		 2723 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2724 }
2725}
2726EXPORT_SYMBOL(il_tx_queue_unmap);
2727
2728/**
2729 * il_tx_queue_free - Deallocate DMA queue.
2730 * @txq: Transmit queue to deallocate.
2731 *
2732 * Empty queue by removing and destroying all BD's.
2733 * Free all buffers.
2734 * 0-fill, but do not free "txq" descriptor structure.
2735 */
e7392364
SG		 2736void
2737il_tx_queue_free(struct il_priv *il, int txq_id)
0cdc2136
SG		 2738{
2739 struct il_tx_queue *txq = &il->txq[txq_id];
2740 struct device *dev = &il->pci_dev->dev;
2741 int i;
2742
2743 il_tx_queue_unmap(il, txq_id);
2744
2745 /* De-alloc array of command/tx buffers */
2746 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
2747 kfree(txq->cmd[i]);
2748
2749 /* De-alloc circular buffer of TFDs */
2750 if (txq->q.n_bd)
e7392364
SG		 2751 dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
2752 txq->tfds, txq->q.dma_addr);
0cdc2136
SG		 2753
2754 /* De-alloc array of per-TFD driver data */
00ea99e1
SG		 2755 kfree(txq->skbs);
2756 txq->skbs = NULL;
0cdc2136
SG		 2757
2758 /* deallocate arrays */
2759 kfree(txq->cmd);
2760 kfree(txq->meta);
2761 txq->cmd = NULL;
2762 txq->meta = NULL;
2763
2764 /* 0-fill queue descriptor structure */
2765 memset(txq, 0, sizeof(*txq));
2766}
2767EXPORT_SYMBOL(il_tx_queue_free);
2768
2769/**
2770 * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
2771 */
e7392364
SG		 2772void
2773il_cmd_queue_unmap(struct il_priv *il)
0cdc2136
SG		 2774{
2775 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2776 struct il_queue *q = &txq->q;
2777 int i;
2778
2779 if (q->n_bd == 0)
2780 return;
2781
2782 while (q->read_ptr != q->write_ptr) {
2783 i = il_get_cmd_idx(q, q->read_ptr, 0);
2784
2785 if (txq->meta[i].flags & CMD_MAPPED) {
2786 pci_unmap_single(il->pci_dev,
2787 dma_unmap_addr(&txq->meta[i], mapping),
2788 dma_unmap_len(&txq->meta[i], len),
2789 PCI_DMA_BIDIRECTIONAL);
2790 txq->meta[i].flags = 0;
2791 }
2792
2793 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2794 }
2795
2796 i = q->n_win;
2797 if (txq->meta[i].flags & CMD_MAPPED) {
2798 pci_unmap_single(il->pci_dev,
2799 dma_unmap_addr(&txq->meta[i], mapping),
2800 dma_unmap_len(&txq->meta[i], len),
2801 PCI_DMA_BIDIRECTIONAL);
2802 txq->meta[i].flags = 0;
2803 }
2804}
2805EXPORT_SYMBOL(il_cmd_queue_unmap);
2806
2807/**
2808 * il_cmd_queue_free - Deallocate DMA queue.
2809 * @txq: Transmit queue to deallocate.
2810 *
2811 * Empty queue by removing and destroying all BD's.
2812 * Free all buffers.
2813 * 0-fill, but do not free "txq" descriptor structure.
2814 */
e7392364
SG		 2815void
2816il_cmd_queue_free(struct il_priv *il)
0cdc2136
SG		 2817{
2818 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2819 struct device *dev = &il->pci_dev->dev;
2820 int i;
2821
2822 il_cmd_queue_unmap(il);
2823
2824 /* De-alloc array of command/tx buffers */
2825 for (i = 0; i <= TFD_CMD_SLOTS; i++)
2826 kfree(txq->cmd[i]);
2827
2828 /* De-alloc circular buffer of TFDs */
2829 if (txq->q.n_bd)
2830 dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
2831 txq->tfds, txq->q.dma_addr);
2832
2833 /* deallocate arrays */
2834 kfree(txq->cmd);
2835 kfree(txq->meta);
2836 txq->cmd = NULL;
2837 txq->meta = NULL;
2838
2839 /* 0-fill queue descriptor structure */
2840 memset(txq, 0, sizeof(*txq));
2841}
2842EXPORT_SYMBOL(il_cmd_queue_free);
2843
2844/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
2845 * DMA services
2846 *
2847 * Theory of operation
2848 *
2849 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
2850 * of buffer descriptors, each of which points to one or more data buffers for
2851 * the device to read from or fill. Driver and device exchange status of each
2852 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
2853 * entries in each circular buffer, to protect against confusing empty and full
2854 * queue states.
2855 *
2856 * The device reads or writes the data in the queues via the device's several
2857 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
2858 *
2859 * For Tx queue, there are low mark and high mark limits. If, after queuing
2860 * the packet for Tx, free space become < low mark, Tx queue stopped. When
2861 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
2862 * Tx queue resumed.
2863 *
2864 * See more detailed info in 4965.h.
2865 ***************************************************/
2866
e7392364
SG		 2867int
2868il_queue_space(const struct il_queue *q)
0cdc2136
SG		 2869{
2870 int s = q->read_ptr - q->write_ptr;
2871
2872 if (q->read_ptr > q->write_ptr)
2873 s -= q->n_bd;
2874
2875 if (s <= 0)
2876 s += q->n_win;
2877 /* keep some reserve to not confuse empty and full situations */
2878 s -= 2;
2879 if (s < 0)
2880 s = 0;
2881 return s;
2882}
2883EXPORT_SYMBOL(il_queue_space);
2884
2885
2886/**
2887 * il_queue_init - Initialize queue's high/low-water and read/write idxes
2888 */
e7392364 2889static int
d87c771f 2890il_queue_init(struct il_priv *il, struct il_queue *q, int slots, u32 id)
0cdc2136 2891{
d87c771f
SG		 2892 /*
2893 * TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
2894 * il_queue_inc_wrap and il_queue_dec_wrap are broken.
2895 */
2896 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
2897 /* FIXME: remove q->n_bd */
2898 q->n_bd = TFD_QUEUE_SIZE_MAX;
0cdc2136 2899
d87c771f
SG		 2900 q->n_win = slots;
2901 q->id = id;
0cdc2136 2902
d87c771f 2903 /* slots_must be power-of-two size, otherwise
0cdc2136 2904 * il_get_cmd_idx is broken. */
d87c771f 2905 BUG_ON(!is_power_of_2(slots));
0cdc2136
SG		 2906
2907 q->low_mark = q->n_win / 4;
2908 if (q->low_mark < 4)
2909 q->low_mark = 4;
2910
2911 q->high_mark = q->n_win / 8;
2912 if (q->high_mark < 2)
2913 q->high_mark = 2;
2914
2915 q->write_ptr = q->read_ptr = 0;
2916
2917 return 0;
2918}
2919
2920/**
2921 * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
2922 */
e7392364
SG		 2923static int
2924il_tx_queue_alloc(struct il_priv *il, struct il_tx_queue *txq, u32 id)
0cdc2136
SG		 2925{
2926 struct device *dev = &il->pci_dev->dev;
2927 size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
2928
2929 /* Driver ilate data, only for Tx (not command) queues,
2930 * not shared with device. */
2931 if (id != il->cmd_queue) {
00ea99e1
SG		 2932 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX, sizeof(struct skb *),
2933 GFP_KERNEL);
2934 if (!txq->skbs) {
2935 IL_ERR("Fail to alloc skbs\n");
0cdc2136
SG		 2936 goto error;
2937 }
00ea99e1
SG		 2938 } else
2939 txq->skbs = NULL;
0cdc2136
SG		 2940
2941 /* Circular buffer of transmit frame descriptors (TFDs),
2942 * shared with device */
e7392364
SG		 2943 txq->tfds =
2944 dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, GFP_KERNEL);
0cdc2136 2945 if (!txq->tfds) {
00ea99e1 2946 IL_ERR("Fail to alloc TFDs\n");
0cdc2136
SG		 2947 goto error;
2948 }
2949 txq->q.id = id;
2950
2951 return 0;
2952
e7392364 2953error:
00ea99e1
SG		 2954 kfree(txq->skbs);
2955 txq->skbs = NULL;
0cdc2136
SG		 2956
2957 return -ENOMEM;
2958}
2959
2960/**
2961 * il_tx_queue_init - Allocate and initialize one tx/cmd queue
2962 */
e7392364 2963int
d87c771f 2964il_tx_queue_init(struct il_priv *il, u32 txq_id)
0cdc2136 2965{
d87c771f
SG		 2966 int i, len, ret;
2967 int slots, actual_slots;
2968 struct il_tx_queue *txq = &il->txq[txq_id];
0cdc2136
SG		 2969
2970 /*
2971 * Alloc buffer array for commands (Tx or other types of commands).
2972 * For the command queue (#4/#9), allocate command space + one big
2973 * command for scan, since scan command is very huge; the system will
2974 * not have two scans at the same time, so only one is needed.
2975 * For normal Tx queues (all other queues), no super-size command
2976 * space is needed.
2977 */
d87c771f
SG		 2978 if (txq_id == il->cmd_queue) {
2979 slots = TFD_CMD_SLOTS;
2980 actual_slots = slots + 1;
2981 } else {
2982 slots = TFD_TX_CMD_SLOTS;
2983 actual_slots = slots;
2984 }
0cdc2136 2985
e7392364
SG		 2986 txq->meta =
2987 kzalloc(sizeof(struct il_cmd_meta) * actual_slots, GFP_KERNEL);
2988 txq->cmd =
2989 kzalloc(sizeof(struct il_device_cmd *) * actual_slots, GFP_KERNEL);
0cdc2136
SG		 2990
2991 if (!txq->meta || !txq->cmd)
2992 goto out_free_arrays;
2993
2994 len = sizeof(struct il_device_cmd);
2995 for (i = 0; i < actual_slots; i++) {
2996 /* only happens for cmd queue */
d87c771f 2997 if (i == slots)
0cdc2136
SG		 2998 len = IL_MAX_CMD_SIZE;
2999
3000 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
3001 if (!txq->cmd[i])
3002 goto err;
3003 }
3004
3005 /* Alloc driver data array and TFD circular buffer */
3006 ret = il_tx_queue_alloc(il, txq, txq_id);
3007 if (ret)
3008 goto err;
3009
3010 txq->need_update = 0;
3011
3012 /*
3013 * For the default queues 0-3, set up the swq_id
3014 * already -- all others need to get one later
3015 * (if they need one at all).
3016 */
3017 if (txq_id < 4)
3018 il_set_swq_id(txq, txq_id, txq_id);
3019
0cdc2136 3020 /* Initialize queue's high/low-water marks, and head/tail idxes */
d87c771f 3021 il_queue_init(il, &txq->q, slots, txq_id);
0cdc2136
SG		 3022
3023 /* Tell device where to find queue */
1600b875 3024 il->ops->txq_init(il, txq);
0cdc2136
SG		 3025
3026 return 0;
3027err:
3028 for (i = 0; i < actual_slots; i++)
3029 kfree(txq->cmd[i]);
3030out_free_arrays:
3031 kfree(txq->meta);
3032 kfree(txq->cmd);
3033
3034 return -ENOMEM;
3035}
3036EXPORT_SYMBOL(il_tx_queue_init);
3037
e7392364 3038void
d87c771f 3039il_tx_queue_reset(struct il_priv *il, u32 txq_id)
0cdc2136 3040{
d87c771f
SG		 3041 int slots, actual_slots;
3042 struct il_tx_queue *txq = &il->txq[txq_id];
0cdc2136 3043
d87c771f
SG		 3044 if (txq_id == il->cmd_queue) {
3045 slots = TFD_CMD_SLOTS;
3046 actual_slots = TFD_CMD_SLOTS + 1;
3047 } else {
3048 slots = TFD_TX_CMD_SLOTS;
3049 actual_slots = TFD_TX_CMD_SLOTS;
3050 }
0cdc2136
SG		 3051
3052 memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots);
0cdc2136
SG		 3053 txq->need_update = 0;
3054
3055 /* Initialize queue's high/low-water marks, and head/tail idxes */
d87c771f 3056 il_queue_init(il, &txq->q, slots, txq_id);
0cdc2136
SG		 3057
3058 /* Tell device where to find queue */
1600b875 3059 il->ops->txq_init(il, txq);
0cdc2136
SG		 3060}
3061EXPORT_SYMBOL(il_tx_queue_reset);
3062
3063/*************** HOST COMMAND QUEUE FUNCTIONS *****/
3064
3065/**
3066 * il_enqueue_hcmd - enqueue a uCode command
3067 * @il: device ilate data point
3068 * @cmd: a point to the ucode command structure
3069 *
3070 * The function returns < 0 values to indicate the operation is
3071 * failed. On success, it turns the idx (> 0) of command in the
3072 * command queue.
3073 */
e7392364
SG		 3074int
3075il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG		 3076{
3077 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
3078 struct il_queue *q = &txq->q;
3079 struct il_device_cmd *out_cmd;
3080 struct il_cmd_meta *out_meta;
3081 dma_addr_t phys_addr;
3082 unsigned long flags;
3083 int len;
3084 u32 idx;
3085 u16 fix_size;
3086
c9363551 3087 cmd->len = il->ops->get_hcmd_size(cmd->id, cmd->len);
e7392364 3088 fix_size = (u16) (cmd->len + sizeof(out_cmd->hdr));
0cdc2136
SG		 3089
3090 /* If any of the command structures end up being larger than
3091 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
3092 * we will need to increase the size of the TFD entries
3093 * Also, check to see if command buffer should not exceed the size
3094 * of device_cmd and max_cmd_size. */
3095 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
3096 !(cmd->flags & CMD_SIZE_HUGE));
3097 BUG_ON(fix_size > IL_MAX_CMD_SIZE);
3098
3099 if (il_is_rfkill(il) || il_is_ctkill(il)) {
3100 IL_WARN("Not sending command - %s KILL\n",
e7392364 3101 il_is_rfkill(il) ? "RF" : "CT");
0cdc2136
SG		 3102 return -EIO;
3103 }
3104
3105 spin_lock_irqsave(&il->hcmd_lock, flags);
3106
3107 if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
3108 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3109
3110 IL_ERR("Restarting adapter due to command queue full\n");
3111 queue_work(il->workqueue, &il->restart);
3112 return -ENOSPC;
3113 }
3114
3115 idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
3116 out_cmd = txq->cmd[idx];
3117 out_meta = &txq->meta[idx];
3118
3119 if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
3120 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3121 return -ENOSPC;
3122 }
3123
3124 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
3125 out_meta->flags = cmd->flags | CMD_MAPPED;
3126 if (cmd->flags & CMD_WANT_SKB)
3127 out_meta->source = cmd;
3128 if (cmd->flags & CMD_ASYNC)
3129 out_meta->callback = cmd->callback;
3130
3131 out_cmd->hdr.cmd = cmd->id;
3132 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
3133
3134 /* At this point, the out_cmd now has all of the incoming cmd
3135 * information */
3136
3137 out_cmd->hdr.flags = 0;
e7392364
SG		 3138 out_cmd->hdr.sequence =
3139 cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) | IDX_TO_SEQ(q->write_ptr));
0cdc2136
SG		 3140 if (cmd->flags & CMD_SIZE_HUGE)
3141 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
3142 len = sizeof(struct il_device_cmd);
3143 if (idx == TFD_CMD_SLOTS)
3144 len = IL_MAX_CMD_SIZE;
3145
3146#ifdef CONFIG_IWLEGACY_DEBUG
3147 switch (out_cmd->hdr.cmd) {
3148 case C_TX_LINK_QUALITY_CMD:
3149 case C_SENSITIVITY:
e7392364
SG		 3150 D_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
3151 "%d bytes at %d[%d]:%d\n",
3152 il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
3153 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
3154 q->write_ptr, idx, il->cmd_queue);
0cdc2136
SG		 3155 break;
3156 default:
3157 D_HC("Sending command %s (#%x), seq: 0x%04X, "
e7392364
SG		 3158 "%d bytes at %d[%d]:%d\n",
3159 il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
3160 le16_to_cpu(out_cmd->hdr.sequence), fix_size, q->write_ptr,
3161 idx, il->cmd_queue);
0cdc2136
SG		 3162 }
3163#endif
3164 txq->need_update = 1;
3165
1600b875 3166 if (il->ops->txq_update_byte_cnt_tbl)
0cdc2136 3167 /* Set up entry in queue's byte count circular buffer */
1600b875 3168 il->ops->txq_update_byte_cnt_tbl(il, txq, 0);
0cdc2136 3169
e7392364
SG		 3170 phys_addr =
3171 pci_map_single(il->pci_dev, &out_cmd->hdr, fix_size,
3172 PCI_DMA_BIDIRECTIONAL);
0cdc2136
SG		 3173 dma_unmap_addr_set(out_meta, mapping, phys_addr);
3174 dma_unmap_len_set(out_meta, len, fix_size);
3175
1600b875 3176 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, fix_size, 1,
c39ae9fd 3177 U32_PAD(cmd->len));
0cdc2136
SG		 3178
3179 /* Increment and update queue's write idx */
3180 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
3181 il_txq_update_write_ptr(il, txq);
3182
3183 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3184 return idx;
3185}
3186
3187/**
3188 * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
3189 *
3190 * When FW advances 'R' idx, all entries between old and new 'R' idx
3191 * need to be reclaimed. As result, some free space forms. If there is
3192 * enough free space (> low mark), wake the stack that feeds us.
3193 */
e7392364
SG		 3194static void
3195il_hcmd_queue_reclaim(struct il_priv *il, int txq_id, int idx, int cmd_idx)
0cdc2136
SG		 3196{
3197 struct il_tx_queue *txq = &il->txq[txq_id];
3198 struct il_queue *q = &txq->q;
3199 int nfreed = 0;
3200
3201 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
3202 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
e7392364
SG		 3203 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
3204 q->write_ptr, q->read_ptr);
0cdc2136
SG		 3205 return;
3206 }
3207
3208 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
3209 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3210
3211 if (nfreed++ > 0) {
3212 IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx,
e7392364 3213 q->write_ptr, q->read_ptr);
0cdc2136
SG		 3214 queue_work(il->workqueue, &il->restart);
3215 }
3216
3217 }
3218}
3219
3220/**
3221 * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
3222 * @rxb: Rx buffer to reclaim
3223 *
3224 * If an Rx buffer has an async callback associated with it the callback
3225 * will be executed. The attached skb (if present) will only be freed
3226 * if the callback returns 1
3227 */
3228void
3229il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb)
3230{
3231 struct il_rx_pkt *pkt = rxb_addr(rxb);
3232 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3233 int txq_id = SEQ_TO_QUEUE(sequence);
3234 int idx = SEQ_TO_IDX(sequence);
3235 int cmd_idx;
3236 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
3237 struct il_device_cmd *cmd;
3238 struct il_cmd_meta *meta;
3239 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
3240 unsigned long flags;
3241
3242 /* If a Tx command is being handled and it isn't in the actual
3243 * command queue then there a command routing bug has been introduced
3244 * in the queue management code. */
e7392364
SG		 3245 if (WARN
3246 (txq_id != il->cmd_queue,
3247 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
3248 txq_id, il->cmd_queue, sequence, il->txq[il->cmd_queue].q.read_ptr,
3249 il->txq[il->cmd_queue].q.write_ptr)) {
0cdc2136
SG		 3250 il_print_hex_error(il, pkt, 32);
3251 return;
3252 }
3253
3254 cmd_idx = il_get_cmd_idx(&txq->q, idx, huge);
3255 cmd = txq->cmd[cmd_idx];
3256 meta = &txq->meta[cmd_idx];
3257
3258 txq->time_stamp = jiffies;
3259
e7392364
SG		 3260 pci_unmap_single(il->pci_dev, dma_unmap_addr(meta, mapping),
3261 dma_unmap_len(meta, len), PCI_DMA_BIDIRECTIONAL);
0cdc2136
SG		 3262
3263 /* Input error checking is done when commands are added to queue. */
3264 if (meta->flags & CMD_WANT_SKB) {
3265 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
3266 rxb->page = NULL;
3267 } else if (meta->callback)
3268 meta->callback(il, cmd, pkt);
3269
3270 spin_lock_irqsave(&il->hcmd_lock, flags);
3271
3272 il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx);
3273
3274 if (!(meta->flags & CMD_ASYNC)) {
3275 clear_bit(S_HCMD_ACTIVE, &il->status);
3276 D_INFO("Clearing HCMD_ACTIVE for command %s\n",
e7392364 3277 il_get_cmd_string(cmd->hdr.cmd));
0cdc2136
SG		 3278 wake_up(&il->wait_command_queue);
3279 }
3280
3281 /* Mark as unmapped */
3282 meta->flags = 0;
3283
3284 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3285}
3286EXPORT_SYMBOL(il_tx_cmd_complete);
be663ab6
WYG		 3287
3288MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965");
3289MODULE_VERSION(IWLWIFI_VERSION);
3290MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
3291MODULE_LICENSE("GPL");
3292
3293/*
3294 * set bt_coex_active to true, uCode will do kill/defer
3295 * every time the priority line is asserted (BT is sending signals on the
3296 * priority line in the PCIx).
3297 * set bt_coex_active to false, uCode will ignore the BT activity and
3298 * perform the normal operation
3299 *
3300 * User might experience transmit issue on some platform due to WiFi/BT
3301 * co-exist problem. The possible behaviors are:
3302 * Able to scan and finding all the available AP
3303 * Not able to associate with any AP
3304 * On those platforms, WiFi communication can be restored by set
3305 * "bt_coex_active" module parameter to "false"
3306 *
3307 * default: bt_coex_active = true (BT_COEX_ENABLE)
3308 */
ef33417d 3309static bool bt_coex_active = true;
be663ab6
WYG		 3310module_param(bt_coex_active, bool, S_IRUGO);
3311MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
3312
d2ddf621
SG		 3313u32 il_debug_level;
3314EXPORT_SYMBOL(il_debug_level);
be663ab6 3315
d2ddf621 3316const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
e7392364 3317EXPORT_SYMBOL(il_bcast_addr);
be663ab6 3318
e7392364
SG		 3319#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
3320#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
3321static void
3322il_init_ht_hw_capab(const struct il_priv *il,
3323 struct ieee80211_sta_ht_cap *ht_info,
3324 enum ieee80211_band band)
be663ab6
WYG		 3325{
3326 u16 max_bit_rate = 0;
46bc8d4b
SG		 3327 u8 rx_chains_num = il->hw_params.rx_chains_num;
3328 u8 tx_chains_num = il->hw_params.tx_chains_num;
be663ab6
WYG		 3329
3330 ht_info->cap = 0;
3331 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
3332
3333 ht_info->ht_supported = true;
3334
3335 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
3336 max_bit_rate = MAX_BIT_RATE_20_MHZ;
46bc8d4b 3337 if (il->hw_params.ht40_channel & BIT(band)) {
be663ab6
WYG		 3338 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
3339 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
3340 ht_info->mcs.rx_mask[4] = 0x01;
3341 max_bit_rate = MAX_BIT_RATE_40_MHZ;
3342 }
3343
46bc8d4b 3344 if (il->cfg->mod_params->amsdu_size_8K)
be663ab6
WYG		 3345 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
3346
3347 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3348 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3349
3350 ht_info->mcs.rx_mask[0] = 0xFF;
3351 if (rx_chains_num >= 2)
3352 ht_info->mcs.rx_mask[1] = 0xFF;
3353 if (rx_chains_num >= 3)
3354 ht_info->mcs.rx_mask[2] = 0xFF;
3355
3356 /* Highest supported Rx data rate */
3357 max_bit_rate *= rx_chains_num;
3358 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
3359 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
3360
3361 /* Tx MCS capabilities */
3362 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
3363 if (tx_chains_num != rx_chains_num) {
3364 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
e7392364
SG		 3365 ht_info->mcs.tx_params |=
3366 ((tx_chains_num -
3367 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
be663ab6
WYG		 3368 }
3369}
3370
3371/**
e2ebc833 3372 * il_init_geos - Initialize mac80211's geo/channel info based from eeprom
be663ab6 3373 */
e7392364
SG		 3374int
3375il_init_geos(struct il_priv *il)
be663ab6 3376{
e2ebc833 3377 struct il_channel_info *ch;
be663ab6
WYG		 3378 struct ieee80211_supported_band *sband;
3379 struct ieee80211_channel *channels;
3380 struct ieee80211_channel *geo_ch;
3381 struct ieee80211_rate *rates;
3382 int i = 0;
332704a5 3383 s8 max_tx_power = 0;
be663ab6 3384
46bc8d4b
SG		 3385 if (il->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
3386 il->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
58de00a4 3387 D_INFO("Geography modes already initialized.\n");
a6766ccd 3388 set_bit(S_GEO_CONFIGURED, &il->status);
be663ab6
WYG		 3389 return 0;
3390 }
3391
e7392364
SG		 3392 channels =
3393 kzalloc(sizeof(struct ieee80211_channel) * il->channel_count,
3394 GFP_KERNEL);
be663ab6
WYG		 3395 if (!channels)
3396 return -ENOMEM;
3397
e7392364
SG		 3398 rates =
3399 kzalloc((sizeof(struct ieee80211_rate) * RATE_COUNT_LEGACY),
3400 GFP_KERNEL);
be663ab6
WYG		 3401 if (!rates) {
3402 kfree(channels);
3403 return -ENOMEM;
3404 }
3405
3406 /* 5.2GHz channels start after the 2.4GHz channels */
46bc8d4b 3407 sband = &il->bands[IEEE80211_BAND_5GHZ];
d2ddf621 3408 sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)];
be663ab6 3409 /* just OFDM */
e2ebc833 3410 sband->bitrates = &rates[IL_FIRST_OFDM_RATE];
2eb05816 3411 sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE;
be663ab6 3412
46bc8d4b 3413 if (il->cfg->sku & IL_SKU_N)
e7392364 3414 il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_5GHZ);
be663ab6 3415
46bc8d4b 3416 sband = &il->bands[IEEE80211_BAND_2GHZ];
be663ab6
WYG		 3417 sband->channels = channels;
3418 /* OFDM & CCK */
3419 sband->bitrates = rates;
2eb05816 3420 sband->n_bitrates = RATE_COUNT_LEGACY;
be663ab6 3421
46bc8d4b 3422 if (il->cfg->sku & IL_SKU_N)
e7392364 3423 il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_2GHZ);
be663ab6 3424
46bc8d4b
SG		 3425 il->ieee_channels = channels;
3426 il->ieee_rates = rates;
be663ab6 3427
e7392364 3428 for (i = 0; i < il->channel_count; i++) {
46bc8d4b 3429 ch = &il->channel_info[i];
be663ab6 3430
e2ebc833 3431 if (!il_is_channel_valid(ch))
be663ab6
WYG		 3432 continue;
3433
46bc8d4b 3434 sband = &il->bands[ch->band];
be663ab6
WYG		 3435
3436 geo_ch = &sband->channels[sband->n_channels++];
3437
3438 geo_ch->center_freq =
e7392364 3439 ieee80211_channel_to_frequency(ch->channel, ch->band);
be663ab6
WYG		 3440 geo_ch->max_power = ch->max_power_avg;
3441 geo_ch->max_antenna_gain = 0xff;
3442 geo_ch->hw_value = ch->channel;
3443
e2ebc833 3444 if (il_is_channel_valid(ch)) {
be663ab6
WYG		 3445 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
3446 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
3447
3448 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
3449 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
3450
3451 if (ch->flags & EEPROM_CHANNEL_RADAR)
3452 geo_ch->flags |= IEEE80211_CHAN_RADAR;
3453
3454 geo_ch->flags |= ch->ht40_extension_channel;
3455
332704a5
SG		 3456 if (ch->max_power_avg > max_tx_power)
3457 max_tx_power = ch->max_power_avg;
be663ab6
WYG		 3458 } else {
3459 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
3460 }
3461
e7392364
SG		 3462 D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", ch->channel,
3463 geo_ch->center_freq,
3464 il_is_channel_a_band(ch) ? "5.2" : "2.4",
3465 geo_ch->
3466 flags & IEEE80211_CHAN_DISABLED ? "restricted" : "valid",
3467 geo_ch->flags);
be663ab6
WYG		 3468 }
3469
46bc8d4b
SG		 3470 il->tx_power_device_lmt = max_tx_power;
3471 il->tx_power_user_lmt = max_tx_power;
3472 il->tx_power_next = max_tx_power;
332704a5 3473
232913b5
SG		 3474 if (il->bands[IEEE80211_BAND_5GHZ].n_channels == 0 &&
3475 (il->cfg->sku & IL_SKU_A)) {
9406f797 3476 IL_INFO("Incorrectly detected BG card as ABG. "
be663ab6 3477 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
e7392364 3478 il->pci_dev->device, il->pci_dev->subsystem_device);
46bc8d4b 3479 il->cfg->sku &= ~IL_SKU_A;
be663ab6
WYG		 3480 }
3481
9406f797 3482 IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n",
e7392364
SG		 3483 il->bands[IEEE80211_BAND_2GHZ].n_channels,
3484 il->bands[IEEE80211_BAND_5GHZ].n_channels);
be663ab6 3485
a6766ccd 3486 set_bit(S_GEO_CONFIGURED, &il->status);
be663ab6
WYG		 3487
3488 return 0;
3489}
e2ebc833 3490EXPORT_SYMBOL(il_init_geos);
be663ab6
WYG		 3491
3492/*
e2ebc833 3493 * il_free_geos - undo allocations in il_init_geos
be663ab6 3494 */
e7392364
SG		 3495void
3496il_free_geos(struct il_priv *il)
be663ab6 3497{
46bc8d4b
SG		 3498 kfree(il->ieee_channels);
3499 kfree(il->ieee_rates);
a6766ccd 3500 clear_bit(S_GEO_CONFIGURED, &il->status);
be663ab6 3501}
e2ebc833 3502EXPORT_SYMBOL(il_free_geos);
be663ab6 3503
e7392364
SG		 3504static bool
3505il_is_channel_extension(struct il_priv *il, enum ieee80211_band band,
3506 u16 channel, u8 extension_chan_offset)
be663ab6 3507{
e2ebc833 3508 const struct il_channel_info *ch_info;
be663ab6 3509
46bc8d4b 3510 ch_info = il_get_channel_info(il, band, channel);
e2ebc833 3511 if (!il_is_channel_valid(ch_info))
be663ab6
WYG		 3512 return false;
3513
3514 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
e7392364
SG		 3515 return !(ch_info->
3516 ht40_extension_channel & IEEE80211_CHAN_NO_HT40PLUS);
be663ab6 3517 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
e7392364
SG		 3518 return !(ch_info->
3519 ht40_extension_channel & IEEE80211_CHAN_NO_HT40MINUS);
be663ab6
WYG		 3520
3521 return false;
3522}
3523
e7392364 3524bool
83007196 3525il_is_ht40_tx_allowed(struct il_priv *il, struct ieee80211_sta_ht_cap *ht_cap)
be663ab6 3526{
1c03c462 3527 if (!il->ht.enabled || !il->ht.is_40mhz)
be663ab6
WYG		 3528 return false;
3529
3530 /*
3531 * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
3532 * the bit will not set if it is pure 40MHz case
3533 */
3534 if (ht_cap && !ht_cap->ht_supported)
3535 return false;
3536
d3175167 3537#ifdef CONFIG_IWLEGACY_DEBUGFS
46bc8d4b 3538 if (il->disable_ht40)
be663ab6
WYG		 3539 return false;
3540#endif
3541
46bc8d4b 3542 return il_is_channel_extension(il, il->band,
c8b03958 3543 le16_to_cpu(il->staging.channel),
1c03c462 3544 il->ht.extension_chan_offset);
be663ab6 3545}
e2ebc833 3546EXPORT_SYMBOL(il_is_ht40_tx_allowed);
be663ab6 3547
e7392364
SG		 3548static u16
3549il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
be663ab6
WYG		 3550{
3551 u16 new_val;
3552 u16 beacon_factor;
3553
3554 /*
3555 * If mac80211 hasn't given us a beacon interval, program
3556 * the default into the device.
3557 */
3558 if (!beacon_val)
3559 return DEFAULT_BEACON_INTERVAL;
3560
3561 /*
3562 * If the beacon interval we obtained from the peer
3563 * is too large, we'll have to wake up more often
3564 * (and in IBSS case, we'll beacon too much)
3565 *
3566 * For example, if max_beacon_val is 4096, and the
3567 * requested beacon interval is 7000, we'll have to
3568 * use 3500 to be able to wake up on the beacons.
3569 *
3570 * This could badly influence beacon detection stats.
3571 */
3572
3573 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
3574 new_val = beacon_val / beacon_factor;
3575
3576 if (!new_val)
3577 new_val = max_beacon_val;
3578
3579 return new_val;
3580}
3581
3582int
83007196 3583il_send_rxon_timing(struct il_priv *il)
be663ab6
WYG		 3584{
3585 u64 tsf;
3586 s32 interval_tm, rem;
3587 struct ieee80211_conf *conf = NULL;
3588 u16 beacon_int;
83007196 3589 struct ieee80211_vif *vif = il->vif;
be663ab6 3590
6278ddab 3591 conf = &il->hw->conf;
be663ab6 3592
46bc8d4b 3593 lockdep_assert_held(&il->mutex);
be663ab6 3594
c8b03958 3595 memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd));
be663ab6 3596
c8b03958
SG		 3597 il->timing.timestamp = cpu_to_le64(il->timestamp);
3598 il->timing.listen_interval = cpu_to_le16(conf->listen_interval);
be663ab6
WYG		 3599
3600 beacon_int = vif ? vif->bss_conf.beacon_int : 0;
3601
3602 /*
6ce1dc45 3603 * TODO: For IBSS we need to get atim_win from mac80211,
e7392364 3604 * for now just always use 0
be663ab6 3605 */
c8b03958 3606 il->timing.atim_win = 0;
be663ab6 3607
e7392364
SG		 3608 beacon_int =
3609 il_adjust_beacon_interval(beacon_int,
3610 il->hw_params.max_beacon_itrvl *
3611 TIME_UNIT);
c8b03958 3612 il->timing.beacon_interval = cpu_to_le16(beacon_int);
be663ab6 3613
e7392364 3614 tsf = il->timestamp; /* tsf is modifed by do_div: copy it */
be663ab6
WYG		 3615 interval_tm = beacon_int * TIME_UNIT;
3616 rem = do_div(tsf, interval_tm);
c8b03958 3617 il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
be663ab6 3618
c8b03958 3619 il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1;
be663ab6 3620
e7392364 3621 D_ASSOC("beacon interval %d beacon timer %d beacon tim %d\n",
c8b03958
SG		 3622 le16_to_cpu(il->timing.beacon_interval),
3623 le32_to_cpu(il->timing.beacon_init_val),
3624 le16_to_cpu(il->timing.atim_win));
be663ab6 3625
63d0f0c5 3626 return il_send_cmd_pdu(il, C_RXON_TIMING, sizeof(il->timing),
c8b03958 3627 &il->timing);
be663ab6 3628}
e2ebc833 3629EXPORT_SYMBOL(il_send_rxon_timing);
be663ab6
WYG		 3630
3631void
83007196 3632il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt)
be663ab6 3633{
c8b03958 3634 struct il_rxon_cmd *rxon = &il->staging;
be663ab6
WYG		 3635
3636 if (hw_decrypt)
3637 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
3638 else
3639 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
3640
3641}
e2ebc833 3642EXPORT_SYMBOL(il_set_rxon_hwcrypto);
be663ab6
WYG		 3643
3644/* validate RXON structure is valid */
3645int
83007196 3646il_check_rxon_cmd(struct il_priv *il)
be663ab6 3647{
c8b03958 3648 struct il_rxon_cmd *rxon = &il->staging;
be663ab6
WYG		 3649 bool error = false;
3650
3651 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
3652 if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
9406f797 3653 IL_WARN("check 2.4G: wrong narrow\n");
be663ab6
WYG		 3654 error = true;
3655 }
3656 if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
9406f797 3657 IL_WARN("check 2.4G: wrong radar\n");
be663ab6
WYG		 3658 error = true;
3659 }
3660 } else {
3661 if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
9406f797 3662 IL_WARN("check 5.2G: not short slot!\n");
be663ab6
WYG		 3663 error = true;
3664 }
3665 if (rxon->flags & RXON_FLG_CCK_MSK) {
9406f797 3666 IL_WARN("check 5.2G: CCK!\n");
be663ab6
WYG		 3667 error = true;
3668 }
3669 }
3670 if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
9406f797 3671 IL_WARN("mac/bssid mcast!\n");
be663ab6
WYG		 3672 error = true;
3673 }
3674
3675 /* make sure basic rates 6Mbps and 1Mbps are supported */
2eb05816
SG		 3676 if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 &&
3677 (rxon->cck_basic_rates & RATE_1M_MASK) == 0) {
9406f797 3678 IL_WARN("neither 1 nor 6 are basic\n");
be663ab6
WYG		 3679 error = true;
3680 }
3681
3682 if (le16_to_cpu(rxon->assoc_id) > 2007) {
9406f797 3683 IL_WARN("aid > 2007\n");
be663ab6
WYG		 3684 error = true;
3685 }
3686
e7392364
SG		 3687 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) ==
3688 (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
9406f797 3689 IL_WARN("CCK and short slot\n");
be663ab6
WYG		 3690 error = true;
3691 }
3692
e7392364
SG		 3693 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) ==
3694 (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
9406f797 3695 IL_WARN("CCK and auto detect");
be663ab6
WYG		 3696 error = true;
3697 }
3698
e7392364
SG		 3699 if ((rxon->
3700 flags & (RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK)) ==
3701 RXON_FLG_TGG_PROTECT_MSK) {
9406f797 3702 IL_WARN("TGg but no auto-detect\n");
be663ab6
WYG		 3703 error = true;
3704 }
3705
3706 if (error)
e7392364 3707 IL_WARN("Tuning to channel %d\n", le16_to_cpu(rxon->channel));
be663ab6
WYG		 3708
3709 if (error) {
9406f797 3710 IL_ERR("Invalid RXON\n");
be663ab6
WYG		 3711 return -EINVAL;
3712 }
3713 return 0;
3714}
e2ebc833 3715EXPORT_SYMBOL(il_check_rxon_cmd);
be663ab6
WYG		 3716
3717/**
e2ebc833 3718 * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
46bc8d4b 3719 * @il: staging_rxon is compared to active_rxon
be663ab6
WYG		 3720 *
3721 * If the RXON structure is changing enough to require a new tune,
3722 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
3723 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
3724 */
e7392364 3725int
83007196 3726il_full_rxon_required(struct il_priv *il)
be663ab6 3727{
c8b03958
SG		 3728 const struct il_rxon_cmd *staging = &il->staging;
3729 const struct il_rxon_cmd *active = &il->active;
be663ab6
WYG		 3730
3731#define CHK(cond) \
3732 if ((cond)) { \
58de00a4 3733 D_INFO("need full RXON - " #cond "\n"); \
be663ab6
WYG		 3734 return 1; \
3735 }
3736
3737#define CHK_NEQ(c1, c2) \
3738 if ((c1) != (c2)) { \
58de00a4 3739 D_INFO("need full RXON - " \
be663ab6
WYG		 3740 #c1 " != " #c2 " - %d != %d\n", \
3741 (c1), (c2)); \
3742 return 1; \
3743 }
3744
3745 /* These items are only settable from the full RXON command */
c8b03958 3746 CHK(!il_is_associated(il));
2e42e474
JP		 3747 CHK(!ether_addr_equal(staging->bssid_addr, active->bssid_addr));
3748 CHK(!ether_addr_equal(staging->node_addr, active->node_addr));
3749 CHK(!ether_addr_equal(staging->wlap_bssid_addr,
3750 active->wlap_bssid_addr));
be663ab6
WYG		 3751 CHK_NEQ(staging->dev_type, active->dev_type);
3752 CHK_NEQ(staging->channel, active->channel);
3753 CHK_NEQ(staging->air_propagation, active->air_propagation);
3754 CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
3755 active->ofdm_ht_single_stream_basic_rates);
3756 CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
3757 active->ofdm_ht_dual_stream_basic_rates);
3758 CHK_NEQ(staging->assoc_id, active->assoc_id);
3759
3760 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
3761 * be updated with the RXON_ASSOC command -- however only some
3762 * flag transitions are allowed using RXON_ASSOC */
3763
3764 /* Check if we are not switching bands */
3765 CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
3766 active->flags & RXON_FLG_BAND_24G_MSK);
3767
3768 /* Check if we are switching association toggle */
3769 CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
3770 active->filter_flags & RXON_FILTER_ASSOC_MSK);
3771
3772#undef CHK
3773#undef CHK_NEQ
3774
3775 return 0;
3776}
e2ebc833 3777EXPORT_SYMBOL(il_full_rxon_required);
be663ab6 3778
e7392364 3779u8
83007196 3780il_get_lowest_plcp(struct il_priv *il)
be663ab6
WYG		 3781{
3782 /*
3783 * Assign the lowest rate -- should really get this from
3784 * the beacon skb from mac80211.
3785 */
c8b03958 3786 if (il->staging.flags & RXON_FLG_BAND_24G_MSK)
2eb05816 3787 return RATE_1M_PLCP;
be663ab6 3788 else
2eb05816 3789 return RATE_6M_PLCP;
be663ab6 3790}
e2ebc833 3791EXPORT_SYMBOL(il_get_lowest_plcp);
be663ab6 3792
e7392364 3793static void
83007196 3794_il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
be663ab6 3795{
c8b03958 3796 struct il_rxon_cmd *rxon = &il->staging;
be663ab6 3797
1c03c462 3798 if (!il->ht.enabled) {
e7392364
SG		 3799 rxon->flags &=
3800 ~(RXON_FLG_CHANNEL_MODE_MSK |
3801 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | RXON_FLG_HT40_PROT_MSK
3802 | RXON_FLG_HT_PROT_MSK);
be663ab6
WYG		 3803 return;
3804 }
3805
e7392364 3806 rxon->flags |=
1c03c462 3807 cpu_to_le32(il->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS);
be663ab6
WYG		 3808
3809 /* Set up channel bandwidth:
3810 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
3811 /* clear the HT channel mode before set the mode */
e7392364
SG		 3812 rxon->flags &=
3813 ~(RXON_FLG_CHANNEL_MODE_MSK | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
83007196 3814 if (il_is_ht40_tx_allowed(il, NULL)) {
be663ab6 3815 /* pure ht40 */
1c03c462 3816 if (il->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
be663ab6
WYG		 3817 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
3818 /* Note: control channel is opposite of extension channel */
1c03c462 3819 switch (il->ht.extension_chan_offset) {
be663ab6
WYG		 3820 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3821 rxon->flags &=
e7392364 3822 ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG		 3823 break;
3824 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
e7392364 3825 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG		 3826 break;
3827 }
3828 } else {
3829 /* Note: control channel is opposite of extension channel */
1c03c462 3830 switch (il->ht.extension_chan_offset) {
be663ab6
WYG		 3831 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3832 rxon->flags &=
e7392364 3833 ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
be663ab6
WYG		 3834 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3835 break;
3836 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
e7392364 3837 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG		 3838 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3839 break;
3840 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
3841 default:
3842 /* channel location only valid if in Mixed mode */
e7392364 3843 IL_ERR("invalid extension channel offset\n");
be663ab6
WYG		 3844 break;
3845 }
3846 }
3847 } else {
3848 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
3849 }
3850
c9363551
SG		 3851 if (il->ops->set_rxon_chain)
3852 il->ops->set_rxon_chain(il);
be663ab6 3853
58de00a4 3854 D_ASSOC("rxon flags 0x%X operation mode :0x%X "
e7392364 3855 "extension channel offset 0x%x\n", le32_to_cpu(rxon->flags),
1c03c462 3856 il->ht.protection, il->ht.extension_chan_offset);
be663ab6
WYG		 3857}
3858
e7392364
SG		 3859void
3860il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
be663ab6 3861{
83007196 3862 _il_set_rxon_ht(il, ht_conf);
be663ab6 3863}
e2ebc833 3864EXPORT_SYMBOL(il_set_rxon_ht);
be663ab6
WYG		 3865
3866/* Return valid, unused, channel for a passive scan to reset the RF */
e7392364
SG		 3867u8
3868il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band)
be663ab6 3869{
e2ebc833 3870 const struct il_channel_info *ch_info;
be663ab6
WYG		 3871 int i;
3872 u8 channel = 0;
3873 u8 min, max;
be663ab6
WYG		 3874
3875 if (band == IEEE80211_BAND_5GHZ) {
3876 min = 14;
46bc8d4b 3877 max = il->channel_count;
be663ab6
WYG		 3878 } else {
3879 min = 0;
3880 max = 14;
3881 }
3882
3883 for (i = min; i < max; i++) {
17d6e557 3884 channel = il->channel_info[i].channel;
c8b03958 3885 if (channel == le16_to_cpu(il->staging.channel))
be663ab6
WYG		 3886 continue;
3887
46bc8d4b 3888 ch_info = il_get_channel_info(il, band, channel);
e2ebc833 3889 if (il_is_channel_valid(ch_info))
be663ab6
WYG		 3890 break;
3891 }
3892
3893 return channel;
3894}
e2ebc833 3895EXPORT_SYMBOL(il_get_single_channel_number);
be663ab6
WYG		 3896
3897/**
e2ebc833 3898 * il_set_rxon_channel - Set the band and channel values in staging RXON
be663ab6
WYG		 3899 * @ch: requested channel as a pointer to struct ieee80211_channel
3900
3901 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
3902 * in the staging RXON flag structure based on the ch->band
3903 */
3904int
83007196 3905il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch)
be663ab6
WYG		 3906{
3907 enum ieee80211_band band = ch->band;
3908 u16 channel = ch->hw_value;
3909
c8b03958 3910 if (le16_to_cpu(il->staging.channel) == channel && il->band == band)
be663ab6
WYG		 3911 return 0;
3912
c8b03958 3913 il->staging.channel = cpu_to_le16(channel);
be663ab6 3914 if (band == IEEE80211_BAND_5GHZ)
c8b03958 3915 il->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
be663ab6 3916 else
c8b03958 3917 il->staging.flags |= RXON_FLG_BAND_24G_MSK;
be663ab6 3918
46bc8d4b 3919 il->band = band;
be663ab6 3920
58de00a4 3921 D_INFO("Staging channel set to %d [%d]\n", channel, band);
be663ab6
WYG		 3922
3923 return 0;
3924}
e2ebc833 3925EXPORT_SYMBOL(il_set_rxon_channel);
be663ab6 3926
e7392364 3927void
83007196
SG		 3928il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band,
3929 struct ieee80211_vif *vif)
be663ab6
WYG		 3930{
3931 if (band == IEEE80211_BAND_5GHZ) {
c8b03958 3932 il->staging.flags &=
e7392364
SG		 3933 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
3934 RXON_FLG_CCK_MSK);
c8b03958 3935 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3936 } else {
e2ebc833 3937 /* Copied from il_post_associate() */
be663ab6 3938 if (vif && vif->bss_conf.use_short_slot)
c8b03958 3939 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3940 else
c8b03958 3941 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3942
c8b03958
SG		 3943 il->staging.flags |= RXON_FLG_BAND_24G_MSK;
3944 il->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
3945 il->staging.flags &= ~RXON_FLG_CCK_MSK;
be663ab6
WYG		 3946 }
3947}
e2ebc833 3948EXPORT_SYMBOL(il_set_flags_for_band);
be663ab6
WYG		 3949
3950/*
3951 * initialize rxon structure with default values from eeprom
3952 */
e7392364 3953void
83007196 3954il_connection_init_rx_config(struct il_priv *il)
be663ab6 3955{
e2ebc833 3956 const struct il_channel_info *ch_info;
be663ab6 3957
c8b03958 3958 memset(&il->staging, 0, sizeof(il->staging));
be663ab6 3959
83007196 3960 if (!il->vif) {
0f8b90f5 3961 il->staging.dev_type = RXON_DEV_TYPE_ESS;
83007196
SG		 3962 } else if (il->vif->type == NL80211_IFTYPE_STATION) {
3963 il->staging.dev_type = RXON_DEV_TYPE_ESS;
3964 il->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
3965 } else if (il->vif->type == NL80211_IFTYPE_ADHOC) {
3966 il->staging.dev_type = RXON_DEV_TYPE_IBSS;
3967 il->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
3968 il->staging.filter_flags =
3969 RXON_FILTER_BCON_AWARE_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
3970 } else {
3971 IL_ERR("Unsupported interface type %d\n", il->vif->type);
3972 return;
3973 }
be663ab6
WYG		 3974
3975#if 0
3976 /* TODO: Figure out when short_preamble would be set and cache from
3977 * that */
46bc8d4b 3978 if (!hw_to_local(il->hw)->short_preamble)
c8b03958 3979 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6 3980 else
c8b03958 3981 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6
WYG		 3982#endif
3983
e7392364 3984 ch_info =
c8b03958 3985 il_get_channel_info(il, il->band, le16_to_cpu(il->active.channel));
be663ab6
WYG		 3986
3987 if (!ch_info)
46bc8d4b 3988 ch_info = &il->channel_info[0];
be663ab6 3989
c8b03958 3990 il->staging.channel = cpu_to_le16(ch_info->channel);
46bc8d4b 3991 il->band = ch_info->band;
be663ab6 3992
83007196 3993 il_set_flags_for_band(il, il->band, il->vif);
be663ab6 3994
c8b03958 3995 il->staging.ofdm_basic_rates =
e2ebc833 3996 (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
c8b03958 3997 il->staging.cck_basic_rates =
e2ebc833 3998 (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
be663ab6
WYG		 3999
4000 /* clear both MIX and PURE40 mode flag */
c8b03958 4001 il->staging.flags &=
e7392364 4002 ~(RXON_FLG_CHANNEL_MODE_MIXED | RXON_FLG_CHANNEL_MODE_PURE_40);
83007196
SG		 4003 if (il->vif)
4004 memcpy(il->staging.node_addr, il->vif->addr, ETH_ALEN);
be663ab6 4005
c8b03958
SG		 4006 il->staging.ofdm_ht_single_stream_basic_rates = 0xff;
4007 il->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
be663ab6 4008}
e2ebc833 4009EXPORT_SYMBOL(il_connection_init_rx_config);
be663ab6 4010
e7392364
SG		 4011void
4012il_set_rate(struct il_priv *il)
be663ab6
WYG		 4013{
4014 const struct ieee80211_supported_band *hw = NULL;
4015 struct ieee80211_rate *rate;
be663ab6
WYG		 4016 int i;
4017
46bc8d4b 4018 hw = il_get_hw_mode(il, il->band);
be663ab6 4019 if (!hw) {
9406f797 4020 IL_ERR("Failed to set rate: unable to get hw mode\n");
be663ab6
WYG		 4021 return;
4022 }
4023
46bc8d4b 4024 il->active_rate = 0;
be663ab6
WYG		 4025
4026 for (i = 0; i < hw->n_bitrates; i++) {
4027 rate = &(hw->bitrates[i]);
2eb05816 4028 if (rate->hw_value < RATE_COUNT_LEGACY)
46bc8d4b 4029 il->active_rate |= (1 << rate->hw_value);
be663ab6
WYG		 4030 }
4031
58de00a4 4032 D_RATE("Set active_rate = %0x\n", il->active_rate);
be663ab6 4033
c8b03958 4034 il->staging.cck_basic_rates =
e7392364 4035 (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
be663ab6 4036
c8b03958 4037 il->staging.ofdm_basic_rates =
e7392364 4038 (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
be663ab6 4039}
e2ebc833 4040EXPORT_SYMBOL(il_set_rate);
be663ab6 4041
e7392364
SG		 4042void
4043il_chswitch_done(struct il_priv *il, bool is_success)
be663ab6 4044{
a6766ccd 4045 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4046 return;
4047
a6766ccd 4048 if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
83007196 4049 ieee80211_chswitch_done(il->vif, is_success);
be663ab6 4050}
e2ebc833 4051EXPORT_SYMBOL(il_chswitch_done);
be663ab6 4052
e7392364
SG		 4053void
4054il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4055{
dcae1c64 4056 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4057 struct il_csa_notification *csa = &(pkt->u.csa_notif);
c8b03958 4058 struct il_rxon_cmd *rxon = (void *)&il->active;
be663ab6 4059
a6766ccd 4060 if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
51e65257
SG		 4061 return;
4062
46bc8d4b 4063 if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) {
51e65257 4064 rxon->channel = csa->channel;
c8b03958 4065 il->staging.channel = csa->channel;
e7392364 4066 D_11H("CSA notif: channel %d\n", le16_to_cpu(csa->channel));
46bc8d4b 4067 il_chswitch_done(il, true);
51e65257 4068 } else {
9406f797 4069 IL_ERR("CSA notif (fail) : channel %d\n",
e7392364 4070 le16_to_cpu(csa->channel));
46bc8d4b 4071 il_chswitch_done(il, false);
be663ab6
WYG		 4072 }
4073}
d2dfb33e 4074EXPORT_SYMBOL(il_hdl_csa);
be663ab6 4075
d3175167 4076#ifdef CONFIG_IWLEGACY_DEBUG
e7392364 4077void
83007196 4078il_print_rx_config_cmd(struct il_priv *il)
be663ab6 4079{
c8b03958 4080 struct il_rxon_cmd *rxon = &il->staging;
be663ab6 4081
58de00a4 4082 D_RADIO("RX CONFIG:\n");
46bc8d4b 4083 il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e7392364 4084 D_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
58de00a4 4085 D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
e7392364 4086 D_RADIO("u32 filter_flags: 0x%08x\n", le32_to_cpu(rxon->filter_flags));
58de00a4 4087 D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
e7392364
SG		 4088 D_RADIO("u8 ofdm_basic_rates: 0x%02x\n", rxon->ofdm_basic_rates);
4089 D_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
58de00a4
SG		 4090 D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
4091 D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
e7392364 4092 D_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
be663ab6 4093}
e2ebc833 4094EXPORT_SYMBOL(il_print_rx_config_cmd);
be663ab6
WYG		 4095#endif
4096/**
e2ebc833 4097 * il_irq_handle_error - called for HW or SW error interrupt from card
be663ab6 4098 */
e7392364
SG		 4099void
4100il_irq_handle_error(struct il_priv *il)
be663ab6 4101{
e2ebc833 4102 /* Set the FW error flag -- cleared on il_down */
a6766ccd 4103 set_bit(S_FW_ERROR, &il->status);
be663ab6
WYG		 4104
4105 /* Cancel currently queued command. */
a6766ccd 4106 clear_bit(S_HCMD_ACTIVE, &il->status);
be663ab6 4107
e7392364 4108 IL_ERR("Loaded firmware version: %s\n", il->hw->wiphy->fw_version);
be663ab6 4109
1600b875
SG		 4110 il->ops->dump_nic_error_log(il);
4111 if (il->ops->dump_fh)
4112 il->ops->dump_fh(il, NULL, false);
d3175167 4113#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4114 if (il_get_debug_level(il) & IL_DL_FW_ERRORS)
83007196 4115 il_print_rx_config_cmd(il);
be663ab6
WYG		 4116#endif
4117
46bc8d4b 4118 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4119
4120 /* Keep the restart process from trying to send host
4121 * commands by clearing the INIT status bit */
a6766ccd 4122 clear_bit(S_READY, &il->status);
be663ab6 4123
a6766ccd 4124 if (!test_bit(S_EXIT_PENDING, &il->status)) {
58de00a4 4125 IL_DBG(IL_DL_FW_ERRORS,
e7392364 4126 "Restarting adapter due to uCode error.\n");
be663ab6 4127
46bc8d4b
SG		 4128 if (il->cfg->mod_params->restart_fw)
4129 queue_work(il->workqueue, &il->restart);
be663ab6
WYG		 4130 }
4131}
e2ebc833 4132EXPORT_SYMBOL(il_irq_handle_error);
be663ab6 4133
e7392364 4134static int
775ed8ab 4135_il_apm_stop_master(struct il_priv *il)
be663ab6
WYG		 4136{
4137 int ret = 0;
4138
4139 /* stop device's busmaster DMA activity */
775ed8ab 4140 _il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
be663ab6 4141
e7392364
SG		 4142 ret =
4143 _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
4144 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
586e45e3 4145 if (ret < 0)
9406f797 4146 IL_WARN("Master Disable Timed Out, 100 usec\n");
be663ab6 4147
58de00a4 4148 D_INFO("stop master\n");
be663ab6
WYG		 4149
4150 return ret;
4151}
4152
e7392364 4153void
775ed8ab 4154_il_apm_stop(struct il_priv *il)
be663ab6 4155{
775ed8ab
SG		 4156 lockdep_assert_held(&il->reg_lock);
4157
58de00a4 4158 D_INFO("Stop card, put in low power state\n");
be663ab6
WYG		 4159
4160 /* Stop device's DMA activity */
775ed8ab 4161 _il_apm_stop_master(il);
be663ab6
WYG		 4162
4163 /* Reset the entire device */
775ed8ab 4164 _il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
be663ab6
WYG		 4165
4166 udelay(10);
4167
4168 /*
4169 * Clear "initialization complete" bit to move adapter from
4170 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
4171 */
775ed8ab
SG		 4172 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
4173}
4174EXPORT_SYMBOL(_il_apm_stop);
4175
4176void
4177il_apm_stop(struct il_priv *il)
4178{
4179 unsigned long flags;
4180
4181 spin_lock_irqsave(&il->reg_lock, flags);
4182 _il_apm_stop(il);
4183 spin_unlock_irqrestore(&il->reg_lock, flags);
be663ab6 4184}
e7392364 4185EXPORT_SYMBOL(il_apm_stop);
be663ab6
WYG		 4186
4187/*
4188 * Start up NIC's basic functionality after it has been reset
e2ebc833 4189 * (e.g. after platform boot, or shutdown via il_apm_stop())
be663ab6
WYG		 4190 * NOTE: This does not load uCode nor start the embedded processor
4191 */
e7392364
SG		 4192int
4193il_apm_init(struct il_priv *il)
be663ab6
WYG		 4194{
4195 int ret = 0;
4196 u16 lctl;
4197
58de00a4 4198 D_INFO("Init card's basic functions\n");
be663ab6
WYG		 4199
4200 /*
4201 * Use "set_bit" below rather than "write", to preserve any hardware
4202 * bits already set by default after reset.
4203 */
4204
4205 /* Disable L0S exit timer (platform NMI Work/Around) */
46bc8d4b 4206 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
e7392364 4207 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
be663ab6
WYG		 4208
4209 /*
4210 * Disable L0s without affecting L1;
4211 * don't wait for ICH L0s (ICH bug W/A)
4212 */
46bc8d4b 4213 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
e7392364 4214 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
be663ab6
WYG		 4215
4216 /* Set FH wait threshold to maximum (HW error during stress W/A) */
e7392364 4217 il_set_bit(il, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
be663ab6
WYG		 4218
4219 /*
4220 * Enable HAP INTA (interrupt from management bus) to
4221 * wake device's PCI Express link L1a -> L0s
25985edc 4222 * NOTE: This is no-op for 3945 (non-existent bit)
be663ab6 4223 */
46bc8d4b 4224 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 4225 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
be663ab6
WYG		 4226
4227 /*
4228 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
4229 * Check if BIOS (or OS) enabled L1-ASPM on this device.
4230 * If so (likely), disable L0S, so device moves directly L0->L1;
4231 * costs negligible amount of power savings.
4232 * If not (unlikely), enable L0S, so there is at least some
4233 * power savings, even without L1.
4234 */
89ef1ed2 4235 if (il->cfg->set_l0s) {
46bc8d4b 4236 lctl = il_pcie_link_ctl(il);
be663ab6 4237 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
e7392364 4238 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
be663ab6 4239 /* L1-ASPM enabled; disable(!) L0S */
46bc8d4b 4240 il_set_bit(il, CSR_GIO_REG,
e7392364 4241 CSR_GIO_REG_VAL_L0S_ENABLED);
58de00a4 4242 D_POWER("L1 Enabled; Disabling L0S\n");
be663ab6
WYG		 4243 } else {
4244 /* L1-ASPM disabled; enable(!) L0S */
46bc8d4b 4245 il_clear_bit(il, CSR_GIO_REG,
e7392364 4246 CSR_GIO_REG_VAL_L0S_ENABLED);
58de00a4 4247 D_POWER("L1 Disabled; Enabling L0S\n");
be663ab6
WYG		 4248 }
4249 }
4250
4251 /* Configure analog phase-lock-loop before activating to D0A */
89ef1ed2 4252 if (il->cfg->pll_cfg_val)
46bc8d4b 4253 il_set_bit(il, CSR_ANA_PLL_CFG,
89ef1ed2 4254 il->cfg->pll_cfg_val);
be663ab6
WYG		 4255
4256 /*
4257 * Set "initialization complete" bit to move adapter from
4258 * D0U* --> D0A* (powered-up active) state.
4259 */
46bc8d4b 4260 il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
be663ab6
WYG		 4261
4262 /*
4263 * Wait for clock stabilization; once stabilized, access to
db54eb57 4264 * device-internal resources is supported, e.g. il_wr_prph()
be663ab6
WYG		 4265 * and accesses to uCode SRAM.
4266 */
e7392364
SG		 4267 ret =
4268 _il_poll_bit(il, CSR_GP_CNTRL,
4269 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
4270 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
be663ab6 4271 if (ret < 0) {
58de00a4 4272 D_INFO("Failed to init the card\n");
be663ab6
WYG		 4273 goto out;
4274 }
4275
4276 /*
4277 * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
4278 * BSM (Boostrap State Machine) is only in 3945 and 4965.
4279 *
4280 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
4281 * do not disable clocks. This preserves any hardware bits already
4282 * set by default in "CLK_CTRL_REG" after reset.
4283 */
89ef1ed2 4284 if (il->cfg->use_bsm)
db54eb57 4285 il_wr_prph(il, APMG_CLK_EN_REG,
e7392364 4286 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
be663ab6 4287 else
e7392364 4288 il_wr_prph(il, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
be663ab6
WYG		 4289 udelay(20);
4290
4291 /* Disable L1-Active */
46bc8d4b 4292 il_set_bits_prph(il, APMG_PCIDEV_STT_REG,
e7392364 4293 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
be663ab6
WYG		 4294
4295out:
4296 return ret;
4297}
e7392364 4298EXPORT_SYMBOL(il_apm_init);
be663ab6 4299
e7392364
SG		 4300int
4301il_set_tx_power(struct il_priv *il, s8 tx_power, bool force)
be663ab6
WYG		 4302{
4303 int ret;
4304 s8 prev_tx_power;
43f12d47 4305 bool defer;
be663ab6 4306
46bc8d4b 4307 lockdep_assert_held(&il->mutex);
be663ab6 4308
46bc8d4b 4309 if (il->tx_power_user_lmt == tx_power && !force)
be663ab6
WYG		 4310 return 0;
4311
1600b875 4312 if (!il->ops->send_tx_power)
be663ab6
WYG		 4313 return -EOPNOTSUPP;
4314
332704a5
SG		 4315 /* 0 dBm mean 1 milliwatt */
4316 if (tx_power < 0) {
e7392364 4317 IL_WARN("Requested user TXPOWER %d below 1 mW.\n", tx_power);
be663ab6
WYG		 4318 return -EINVAL;
4319 }
4320
46bc8d4b 4321 if (tx_power > il->tx_power_device_lmt) {
e7392364
SG		 4322 IL_WARN("Requested user TXPOWER %d above upper limit %d.\n",
4323 tx_power, il->tx_power_device_lmt);
be663ab6
WYG		 4324 return -EINVAL;
4325 }
4326
46bc8d4b 4327 if (!il_is_ready_rf(il))
be663ab6
WYG		 4328 return -EIO;
4329
43f12d47
SG		 4330 /* scan complete and commit_rxon use tx_power_next value,
4331 * it always need to be updated for newest request */
46bc8d4b 4332 il->tx_power_next = tx_power;
43f12d47
SG		 4333
4334 /* do not set tx power when scanning or channel changing */
a6766ccd 4335 defer = test_bit(S_SCANNING, &il->status) ||
c8b03958 4336 memcmp(&il->active, &il->staging, sizeof(il->staging));
43f12d47 4337 if (defer && !force) {
58de00a4 4338 D_INFO("Deferring tx power set\n");
be663ab6
WYG		 4339 return 0;
4340 }
4341
46bc8d4b
SG		 4342 prev_tx_power = il->tx_power_user_lmt;
4343 il->tx_power_user_lmt = tx_power;
be663ab6 4344
1600b875 4345 ret = il->ops->send_tx_power(il);
be663ab6
WYG		 4346
4347 /* if fail to set tx_power, restore the orig. tx power */
4348 if (ret) {
46bc8d4b
SG		 4349 il->tx_power_user_lmt = prev_tx_power;
4350 il->tx_power_next = prev_tx_power;
be663ab6
WYG		 4351 }
4352 return ret;
4353}
e2ebc833 4354EXPORT_SYMBOL(il_set_tx_power);
be663ab6 4355
e7392364
SG		 4356void
4357il_send_bt_config(struct il_priv *il)
be663ab6 4358{
e2ebc833 4359 struct il_bt_cmd bt_cmd = {
be663ab6
WYG		 4360 .lead_time = BT_LEAD_TIME_DEF,
4361 .max_kill = BT_MAX_KILL_DEF,
4362 .kill_ack_mask = 0,
4363 .kill_cts_mask = 0,
4364 };
4365
4366 if (!bt_coex_active)
4367 bt_cmd.flags = BT_COEX_DISABLE;
4368 else
4369 bt_cmd.flags = BT_COEX_ENABLE;
4370
58de00a4 4371 D_INFO("BT coex %s\n",
e7392364 4372 (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
be663ab6 4373
e7392364 4374 if (il_send_cmd_pdu(il, C_BT_CONFIG, sizeof(struct il_bt_cmd), &bt_cmd))
9406f797 4375 IL_ERR("failed to send BT Coex Config\n");
be663ab6 4376}
e2ebc833 4377EXPORT_SYMBOL(il_send_bt_config);
be663ab6 4378
e7392364
SG		 4379int
4380il_send_stats_request(struct il_priv *il, u8 flags, bool clear)
be663ab6 4381{
ebf0d90d 4382 struct il_stats_cmd stats_cmd = {
e7392364 4383 .configuration_flags = clear ? IL_STATS_CONF_CLEAR_STATS : 0,
be663ab6
WYG		 4384 };
4385
4386 if (flags & CMD_ASYNC)
e7392364
SG		 4387 return il_send_cmd_pdu_async(il, C_STATS, sizeof(struct il_stats_cmd),
4388 &stats_cmd, NULL);
be663ab6 4389 else
e7392364
SG		 4390 return il_send_cmd_pdu(il, C_STATS, sizeof(struct il_stats_cmd),
4391 &stats_cmd);
be663ab6 4392}
ebf0d90d 4393EXPORT_SYMBOL(il_send_stats_request);
be663ab6 4394
e7392364
SG		 4395void
4396il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4397{
d3175167 4398#ifdef CONFIG_IWLEGACY_DEBUG
dcae1c64 4399 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4400 struct il_sleep_notification *sleep = &(pkt->u.sleep_notif);
58de00a4 4401 D_RX("sleep mode: %d, src: %d\n",
1722f8e1 4402 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
be663ab6
WYG		 4403#endif
4404}
d2dfb33e 4405EXPORT_SYMBOL(il_hdl_pm_sleep);
be663ab6 4406
e7392364
SG		 4407void
4408il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4409{
dcae1c64 4410 struct il_rx_pkt *pkt = rxb_addr(rxb);
e94a4099 4411 u32 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
e7392364
SG		 4412 D_RADIO("Dumping %d bytes of unhandled notification for %s:\n", len,
4413 il_get_cmd_string(pkt->hdr.cmd));
46bc8d4b 4414 il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len);
be663ab6 4415}
d2dfb33e 4416EXPORT_SYMBOL(il_hdl_pm_debug_stats);
be663ab6 4417
e7392364
SG		 4418void
4419il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4420{
dcae1c64 4421 struct il_rx_pkt *pkt = rxb_addr(rxb);
be663ab6 4422
9406f797 4423 IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) "
e7392364
SG		 4424 "seq 0x%04X ser 0x%08X\n",
4425 le32_to_cpu(pkt->u.err_resp.error_type),
4426 il_get_cmd_string(pkt->u.err_resp.cmd_id),
4427 pkt->u.err_resp.cmd_id,
4428 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
4429 le32_to_cpu(pkt->u.err_resp.error_info));
be663ab6 4430}
6e9848b4 4431EXPORT_SYMBOL(il_hdl_error);
be663ab6 4432
e7392364
SG		 4433void
4434il_clear_isr_stats(struct il_priv *il)
be663ab6 4435{
46bc8d4b 4436 memset(&il->isr_stats, 0, sizeof(il->isr_stats));
be663ab6
WYG		 4437}
4438
e7392364
SG		 4439int
4440il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
4441 const struct ieee80211_tx_queue_params *params)
be663ab6 4442{
46bc8d4b 4443 struct il_priv *il = hw->priv;
be663ab6
WYG		 4444 unsigned long flags;
4445 int q;
4446
58de00a4 4447 D_MAC80211("enter\n");
be663ab6 4448
46bc8d4b 4449 if (!il_is_ready_rf(il)) {
58de00a4 4450 D_MAC80211("leave - RF not ready\n");
be663ab6
WYG		 4451 return -EIO;
4452 }
4453
4454 if (queue >= AC_NUM) {
58de00a4 4455 D_MAC80211("leave - queue >= AC_NUM %d\n", queue);
be663ab6
WYG		 4456 return 0;
4457 }
4458
4459 q = AC_NUM - 1 - queue;
4460
46bc8d4b 4461 spin_lock_irqsave(&il->lock, flags);
be663ab6 4462
8d44f2bd 4463 il->qos_data.def_qos_parm.ac[q].cw_min =
e7392364 4464 cpu_to_le16(params->cw_min);
8d44f2bd 4465 il->qos_data.def_qos_parm.ac[q].cw_max =
e7392364 4466 cpu_to_le16(params->cw_max);
8d44f2bd
SG		 4467 il->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
4468 il->qos_data.def_qos_parm.ac[q].edca_txop =
e7392364 4469 cpu_to_le16((params->txop * 32));
be663ab6 4470
8d44f2bd 4471 il->qos_data.def_qos_parm.ac[q].reserved1 = 0;
be663ab6 4472
46bc8d4b 4473 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 4474
58de00a4 4475 D_MAC80211("leave\n");
be663ab6
WYG		 4476 return 0;
4477}
e2ebc833 4478EXPORT_SYMBOL(il_mac_conf_tx);
be663ab6 4479
e7392364
SG		 4480int
4481il_mac_tx_last_beacon(struct ieee80211_hw *hw)
be663ab6 4482{
46bc8d4b 4483 struct il_priv *il = hw->priv;
9ce7b73c 4484 int ret;
be663ab6 4485
9ce7b73c
SG		 4486 D_MAC80211("enter\n");
4487
4488 ret = (il->ibss_manager == IL_IBSS_MANAGER);
4489
4490 D_MAC80211("leave ret %d\n", ret);
4491 return ret;
be663ab6 4492}
e2ebc833 4493EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon);
be663ab6
WYG		 4494
4495static int
83007196 4496il_set_mode(struct il_priv *il)
be663ab6 4497{
83007196 4498 il_connection_init_rx_config(il);
be663ab6 4499
c9363551
SG		 4500 if (il->ops->set_rxon_chain)
4501 il->ops->set_rxon_chain(il);
be663ab6 4502
83007196 4503 return il_commit_rxon(il);
be663ab6
WYG		 4504}
4505
be663ab6 4506int
e2ebc833 4507il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 4508{
46bc8d4b 4509 struct il_priv *il = hw->priv;
be663ab6 4510 int err;
883a649b 4511 bool reset;
be663ab6 4512
46bc8d4b 4513 mutex_lock(&il->mutex);
9ce7b73c 4514 D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
be663ab6 4515
46bc8d4b 4516 if (!il_is_ready_rf(il)) {
9406f797 4517 IL_WARN("Try to add interface when device not ready\n");
be663ab6
WYG		 4518 err = -EINVAL;
4519 goto out;
4520 }
4521
883a649b
SG		 4522 /*
4523 * We do not support multiple virtual interfaces, but on hardware reset
4524 * we have to add the same interface again.
4525 */
4526 reset = (il->vif == vif);
4527 if (il->vif && !reset) {
be663ab6
WYG		 4528 err = -EOPNOTSUPP;
4529 goto out;
4530 }
4531
83007196 4532 il->vif = vif;
20c47eba 4533 il->iw_mode = vif->type;
be663ab6 4534
83007196 4535 err = il_set_mode(il);
17d6e557 4536 if (err) {
883a649b
SG		 4537 IL_WARN("Fail to set mode %d\n", vif->type);
4538 if (!reset) {
4539 il->vif = NULL;
4540 il->iw_mode = NL80211_IFTYPE_STATION;
4541 }
17d6e557 4542 }
be663ab6 4543
e7392364 4544out:
9ce7b73c 4545 D_MAC80211("leave err %d\n", err);
46bc8d4b 4546 mutex_unlock(&il->mutex);
be663ab6 4547
be663ab6
WYG		 4548 return err;
4549}
e2ebc833 4550EXPORT_SYMBOL(il_mac_add_interface);
be663ab6 4551
e7392364
SG		 4552static void
4553il_teardown_interface(struct il_priv *il, struct ieee80211_vif *vif,
4554 bool mode_change)
be663ab6 4555{
46bc8d4b 4556 lockdep_assert_held(&il->mutex);
be663ab6 4557
46bc8d4b
SG		 4558 if (il->scan_vif == vif) {
4559 il_scan_cancel_timeout(il, 200);
4560 il_force_scan_end(il);
be663ab6
WYG		 4561 }
4562
dee9a09e 4563 if (!mode_change)
83007196 4564 il_set_mode(il);
dee9a09e 4565
be663ab6
WYG		 4566}
4567
e7392364
SG		 4568void
4569il_mac_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 4570{
46bc8d4b 4571 struct il_priv *il = hw->priv;
be663ab6 4572
46bc8d4b 4573 mutex_lock(&il->mutex);
9ce7b73c 4574 D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
be663ab6 4575
83007196
SG		 4576 WARN_ON(il->vif != vif);
4577 il->vif = NULL;
be663ab6 4578
46bc8d4b 4579 il_teardown_interface(il, vif, false);
46bc8d4b 4580 memset(il->bssid, 0, ETH_ALEN);
be663ab6 4581
58de00a4 4582 D_MAC80211("leave\n");
9ce7b73c 4583 mutex_unlock(&il->mutex);
be663ab6 4584}
e2ebc833 4585EXPORT_SYMBOL(il_mac_remove_interface);
be663ab6 4586
e7392364
SG		 4587int
4588il_alloc_txq_mem(struct il_priv *il)
be663ab6 4589{
46bc8d4b 4590 if (!il->txq)
e7392364
SG		 4591 il->txq =
4592 kzalloc(sizeof(struct il_tx_queue) *
89ef1ed2 4593 il->cfg->num_of_queues, GFP_KERNEL);
46bc8d4b 4594 if (!il->txq) {
9406f797 4595 IL_ERR("Not enough memory for txq\n");
be663ab6
WYG		 4596 return -ENOMEM;
4597 }
4598 return 0;
4599}
e2ebc833 4600EXPORT_SYMBOL(il_alloc_txq_mem);
be663ab6 4601
e7392364 4602void
6668e4eb 4603il_free_txq_mem(struct il_priv *il)
be663ab6 4604{
46bc8d4b
SG		 4605 kfree(il->txq);
4606 il->txq = NULL;
be663ab6 4607}
6668e4eb 4608EXPORT_SYMBOL(il_free_txq_mem);
be663ab6 4609
e7392364
SG		 4610int
4611il_force_reset(struct il_priv *il, bool external)
be663ab6 4612{
e2ebc833 4613 struct il_force_reset *force_reset;
be663ab6 4614
a6766ccd 4615 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4616 return -EINVAL;
4617
46bc8d4b 4618 force_reset = &il->force_reset;
be663ab6
WYG		 4619 force_reset->reset_request_count++;
4620 if (!external) {
4621 if (force_reset->last_force_reset_jiffies &&
4622 time_after(force_reset->last_force_reset_jiffies +
e7392364 4623 force_reset->reset_duration, jiffies)) {
58de00a4 4624 D_INFO("force reset rejected\n");
be663ab6
WYG		 4625 force_reset->reset_reject_count++;
4626 return -EAGAIN;
4627 }
4628 }
4629 force_reset->reset_success_count++;
4630 force_reset->last_force_reset_jiffies = jiffies;
dd6d2a8a
SG		 4631
4632 /*
4633 * if the request is from external(ex: debugfs),
4634 * then always perform the request in regardless the module
4635 * parameter setting
4636 * if the request is from internal (uCode error or driver
4637 * detect failure), then fw_restart module parameter
4638 * need to be check before performing firmware reload
4639 */
4640
46bc8d4b 4641 if (!external && !il->cfg->mod_params->restart_fw) {
58de00a4 4642 D_INFO("Cancel firmware reload based on "
e7392364 4643 "module parameter setting\n");
dd6d2a8a 4644 return 0;
be663ab6 4645 }
dd6d2a8a 4646
9406f797 4647 IL_ERR("On demand firmware reload\n");
dd6d2a8a 4648
e2ebc833 4649 /* Set the FW error flag -- cleared on il_down */
a6766ccd 4650 set_bit(S_FW_ERROR, &il->status);
46bc8d4b 4651 wake_up(&il->wait_command_queue);
dd6d2a8a
SG		 4652 /*
4653 * Keep the restart process from trying to send host
4654 * commands by clearing the INIT status bit
4655 */
a6766ccd 4656 clear_bit(S_READY, &il->status);
46bc8d4b 4657 queue_work(il->workqueue, &il->restart);
dd6d2a8a 4658
be663ab6
WYG		 4659 return 0;
4660}
4661
4662int
e7392364 4663il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
be663ab6
WYG		 4664 enum nl80211_iftype newtype, bool newp2p)
4665{
46bc8d4b 4666 struct il_priv *il = hw->priv;
be663ab6
WYG		 4667 int err;
4668
46bc8d4b 4669 mutex_lock(&il->mutex);
9ce7b73c
SG		 4670 D_MAC80211("enter: type %d, addr %pM newtype %d newp2p %d\n",
4671 vif->type, vif->addr, newtype, newp2p);
4672
4673 if (newp2p) {
4674 err = -EOPNOTSUPP;
4675 goto out;
4676 }
be663ab6 4677
83007196 4678 if (!il->vif || !il_is_ready_rf(il)) {
ffd8c746
JB		 4679 /*
4680 * Huh? But wait ... this can maybe happen when
4681 * we're in the middle of a firmware restart!
4682 */
4683 err = -EBUSY;
4684 goto out;
4685 }
4686
be663ab6 4687 /* success */
46bc8d4b 4688 il_teardown_interface(il, vif, true);
be663ab6 4689 vif->type = newtype;
8c9c48d5 4690 vif->p2p = false;
83007196 4691 err = il_set_mode(il);
be663ab6
WYG		 4692 WARN_ON(err);
4693 /*
4694 * We've switched internally, but submitting to the
4695 * device may have failed for some reason. Mask this
4696 * error, because otherwise mac80211 will not switch
4697 * (and set the interface type back) and we'll be
4698 * out of sync with it.
4699 */
4700 err = 0;
4701
e7392364 4702out:
9ce7b73c 4703 D_MAC80211("leave err %d\n", err);
46bc8d4b 4704 mutex_unlock(&il->mutex);
9ce7b73c 4705
be663ab6
WYG		 4706 return err;
4707}
e2ebc833 4708EXPORT_SYMBOL(il_mac_change_interface);
be663ab6
WYG		 4709
4710/*
4711 * On every watchdog tick we check (latest) time stamp. If it does not
4712 * change during timeout period and queue is not empty we reset firmware.
4713 */
e7392364
SG		 4714static int
4715il_check_stuck_queue(struct il_priv *il, int cnt)
be663ab6 4716{
46bc8d4b 4717 struct il_tx_queue *txq = &il->txq[cnt];
e2ebc833 4718 struct il_queue *q = &txq->q;
be663ab6
WYG		 4719 unsigned long timeout;
4720 int ret;
4721
4722 if (q->read_ptr == q->write_ptr) {
4723 txq->time_stamp = jiffies;
4724 return 0;
4725 }
4726
e7392364
SG		 4727 timeout =
4728 txq->time_stamp +
89ef1ed2 4729 msecs_to_jiffies(il->cfg->wd_timeout);
be663ab6
WYG		 4730
4731 if (time_after(jiffies, timeout)) {
e7392364 4732 IL_ERR("Queue %d stuck for %u ms.\n", q->id,
89ef1ed2 4733 il->cfg->wd_timeout);
46bc8d4b 4734 ret = il_force_reset(il, false);
be663ab6
WYG		 4735 return (ret == -EAGAIN) ? 0 : 1;
4736 }
4737
4738 return 0;
4739}
4740
4741/*
4742 * Making watchdog tick be a quarter of timeout assure we will
4743 * discover the queue hung between timeout and 1.25*timeout
4744 */
e2ebc833 4745#define IL_WD_TICK(timeout) ((timeout) / 4)
be663ab6
WYG		 4746
4747/*
4748 * Watchdog timer callback, we check each tx queue for stuck, if if hung
4749 * we reset the firmware. If everything is fine just rearm the timer.
4750 */
e7392364
SG		 4751void
4752il_bg_watchdog(unsigned long data)
be663ab6 4753{
46bc8d4b 4754 struct il_priv *il = (struct il_priv *)data;
be663ab6
WYG		 4755 int cnt;
4756 unsigned long timeout;
4757
a6766ccd 4758 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4759 return;
4760
89ef1ed2 4761 timeout = il->cfg->wd_timeout;
be663ab6
WYG		 4762 if (timeout == 0)
4763 return;
4764
4765 /* monitor and check for stuck cmd queue */
46bc8d4b 4766 if (il_check_stuck_queue(il, il->cmd_queue))
be663ab6
WYG		 4767 return;
4768
4769 /* monitor and check for other stuck queues */
46bc8d4b
SG		 4770 if (il_is_any_associated(il)) {
4771 for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) {
be663ab6 4772 /* skip as we already checked the command queue */
46bc8d4b 4773 if (cnt == il->cmd_queue)
be663ab6 4774 continue;
46bc8d4b 4775 if (il_check_stuck_queue(il, cnt))
be663ab6
WYG		 4776 return;
4777 }
4778 }
4779
e7392364
SG		 4780 mod_timer(&il->watchdog,
4781 jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
be663ab6 4782}
e2ebc833 4783EXPORT_SYMBOL(il_bg_watchdog);
be663ab6 4784
e7392364
SG		 4785void
4786il_setup_watchdog(struct il_priv *il)
be663ab6 4787{
89ef1ed2 4788 unsigned int timeout = il->cfg->wd_timeout;
be663ab6
WYG		 4789
4790 if (timeout)
46bc8d4b 4791 mod_timer(&il->watchdog,
e2ebc833 4792 jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
be663ab6 4793 else
46bc8d4b 4794 del_timer(&il->watchdog);
be663ab6 4795}
e2ebc833 4796EXPORT_SYMBOL(il_setup_watchdog);
be663ab6
WYG		 4797
4798/*
4799 * extended beacon time format
4800 * time in usec will be changed into a 32-bit value in extended:internal format
4801 * the extended part is the beacon counts
4802 * the internal part is the time in usec within one beacon interval
4803 */
4804u32
e7392364 4805il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval)
be663ab6
WYG		 4806{
4807 u32 quot;
4808 u32 rem;
4809 u32 interval = beacon_interval * TIME_UNIT;
4810
4811 if (!interval || !usec)
4812 return 0;
4813
e7392364
SG		 4814 quot =
4815 (usec /
4816 interval) & (il_beacon_time_mask_high(il,
4817 il->hw_params.
4818 beacon_time_tsf_bits) >> il->
4819 hw_params.beacon_time_tsf_bits);
4820 rem =
4821 (usec % interval) & il_beacon_time_mask_low(il,
4822 il->hw_params.
4823 beacon_time_tsf_bits);
be663ab6 4824
46bc8d4b 4825 return (quot << il->hw_params.beacon_time_tsf_bits) + rem;
be663ab6 4826}
e2ebc833 4827EXPORT_SYMBOL(il_usecs_to_beacons);
be663ab6
WYG		 4828
4829/* base is usually what we get from ucode with each received frame,
4830 * the same as HW timer counter counting down
4831 */
e7392364 4832__le32
1722f8e1 4833il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
e7392364 4834 u32 beacon_interval)
be663ab6 4835{
46bc8d4b 4836 u32 base_low = base & il_beacon_time_mask_low(il,
e7392364
SG		 4837 il->hw_params.
4838 beacon_time_tsf_bits);
46bc8d4b 4839 u32 addon_low = addon & il_beacon_time_mask_low(il,
e7392364
SG		 4840 il->hw_params.
4841 beacon_time_tsf_bits);
be663ab6 4842 u32 interval = beacon_interval * TIME_UNIT;
46bc8d4b 4843 u32 res = (base & il_beacon_time_mask_high(il,
e7392364
SG		 4844 il->hw_params.
4845 beacon_time_tsf_bits)) +
4846 (addon & il_beacon_time_mask_high(il,
4847 il->hw_params.
4848 beacon_time_tsf_bits));
be663ab6
WYG		 4849
4850 if (base_low > addon_low)
4851 res += base_low - addon_low;
4852 else if (base_low < addon_low) {
4853 res += interval + base_low - addon_low;
46bc8d4b 4854 res += (1 << il->hw_params.beacon_time_tsf_bits);
be663ab6 4855 } else
46bc8d4b 4856 res += (1 << il->hw_params.beacon_time_tsf_bits);
be663ab6
WYG		 4857
4858 return cpu_to_le32(res);
4859}
e2ebc833 4860EXPORT_SYMBOL(il_add_beacon_time);
be663ab6
WYG		 4861
4862#ifdef CONFIG_PM
4863
e7392364
SG		 4864int
4865il_pci_suspend(struct device *device)
be663ab6
WYG		 4866{
4867 struct pci_dev *pdev = to_pci_dev(device);
46bc8d4b 4868 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 4869
4870 /*
4871 * This function is called when system goes into suspend state
e2ebc833
SG		 4872 * mac80211 will call il_mac_stop() from the mac80211 suspend function
4873 * first but since il_mac_stop() has no knowledge of who the caller is,
be663ab6
WYG		 4874 * it will not call apm_ops.stop() to stop the DMA operation.
4875 * Calling apm_ops.stop here to make sure we stop the DMA.
4876 */
46bc8d4b 4877 il_apm_stop(il);
be663ab6
WYG		 4878
4879 return 0;
4880}
e2ebc833 4881EXPORT_SYMBOL(il_pci_suspend);
be663ab6 4882
e7392364
SG		 4883int
4884il_pci_resume(struct device *device)
be663ab6
WYG		 4885{
4886 struct pci_dev *pdev = to_pci_dev(device);
46bc8d4b 4887 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 4888 bool hw_rfkill = false;
4889
4890 /*
4891 * We disable the RETRY_TIMEOUT register (0x41) to keep
4892 * PCI Tx retries from interfering with C3 CPU state.
4893 */
4894 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4895
46bc8d4b 4896 il_enable_interrupts(il);
be663ab6 4897
e7392364 4898 if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
be663ab6
WYG		 4899 hw_rfkill = true;
4900
4901 if (hw_rfkill)
bc269a8e 4902 set_bit(S_RFKILL, &il->status);
be663ab6 4903 else
bc269a8e 4904 clear_bit(S_RFKILL, &il->status);
be663ab6 4905
46bc8d4b 4906 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill);
be663ab6
WYG		 4907
4908 return 0;
4909}
e2ebc833 4910EXPORT_SYMBOL(il_pci_resume);
be663ab6 4911
e2ebc833
SG		 4912const struct dev_pm_ops il_pm_ops = {
4913 .suspend = il_pci_suspend,
4914 .resume = il_pci_resume,
4915 .freeze = il_pci_suspend,
4916 .thaw = il_pci_resume,
4917 .poweroff = il_pci_suspend,
4918 .restore = il_pci_resume,
be663ab6 4919};
e2ebc833 4920EXPORT_SYMBOL(il_pm_ops);
be663ab6
WYG		 4921
4922#endif /* CONFIG_PM */
4923
4924static void
83007196 4925il_update_qos(struct il_priv *il)
be663ab6 4926{
a6766ccd 4927 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4928 return;
4929
8d44f2bd 4930 il->qos_data.def_qos_parm.qos_flags = 0;
be663ab6 4931
8d44f2bd
SG		 4932 if (il->qos_data.qos_active)
4933 il->qos_data.def_qos_parm.qos_flags |=
e7392364 4934 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
be663ab6 4935
1c03c462 4936 if (il->ht.enabled)
8d44f2bd 4937 il->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
be663ab6 4938
58de00a4 4939 D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
8d44f2bd 4940 il->qos_data.qos_active, il->qos_data.def_qos_parm.qos_flags);
be663ab6 4941
b96ed60c 4942 il_send_cmd_pdu_async(il, C_QOS_PARAM, sizeof(struct il_qosparam_cmd),
8d44f2bd 4943 &il->qos_data.def_qos_parm, NULL);
be663ab6
WYG		 4944}
4945
4946/**
e2ebc833 4947 * il_mac_config - mac80211 config callback
be663ab6 4948 */
e7392364
SG		 4949int
4950il_mac_config(struct ieee80211_hw *hw, u32 changed)
be663ab6 4951{
46bc8d4b 4952 struct il_priv *il = hw->priv;
e2ebc833 4953 const struct il_channel_info *ch_info;
be663ab6
WYG		 4954 struct ieee80211_conf *conf = &hw->conf;
4955 struct ieee80211_channel *channel = conf->channel;
46bc8d4b 4956 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6
WYG		 4957 unsigned long flags = 0;
4958 int ret = 0;
4959 u16 ch;
4960 int scan_active = 0;
7c2cde2e 4961 bool ht_changed = false;
be663ab6 4962
46bc8d4b 4963 mutex_lock(&il->mutex);
9ce7b73c 4964 D_MAC80211("enter: channel %d changed 0x%X\n", channel->hw_value,
e7392364 4965 changed);
be663ab6 4966
a6766ccd 4967 if (unlikely(test_bit(S_SCANNING, &il->status))) {
be663ab6 4968 scan_active = 1;
58de00a4 4969 D_MAC80211("scan active\n");
be663ab6
WYG		 4970 }
4971
e7392364
SG		 4972 if (changed &
4973 (IEEE80211_CONF_CHANGE_SMPS | IEEE80211_CONF_CHANGE_CHANNEL)) {
be663ab6 4974 /* mac80211 uses static for non-HT which is what we want */
46bc8d4b 4975 il->current_ht_config.smps = conf->smps_mode;
be663ab6
WYG		 4976
4977 /*
4978 * Recalculate chain counts.
4979 *
4980 * If monitor mode is enabled then mac80211 will
4981 * set up the SM PS mode to OFF if an HT channel is
4982 * configured.
4983 */
c9363551
SG		 4984 if (il->ops->set_rxon_chain)
4985 il->ops->set_rxon_chain(il);
be663ab6
WYG		 4986 }
4987
4988 /* during scanning mac80211 will delay channel setting until
4989 * scan finish with changed = 0
4990 */
4991 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
17d6e557 4992
be663ab6
WYG		 4993 if (scan_active)
4994 goto set_ch_out;
4995
4996 ch = channel->hw_value;
46bc8d4b 4997 ch_info = il_get_channel_info(il, channel->band, ch);
e2ebc833 4998 if (!il_is_channel_valid(ch_info)) {
58de00a4 4999 D_MAC80211("leave - invalid channel\n");
be663ab6
WYG		 5000 ret = -EINVAL;
5001 goto set_ch_out;
5002 }
5003
46bc8d4b 5004 if (il->iw_mode == NL80211_IFTYPE_ADHOC &&
e2ebc833 5005 !il_is_channel_ibss(ch_info)) {
58de00a4 5006 D_MAC80211("leave - not IBSS channel\n");
eb85de3f
SG		 5007 ret = -EINVAL;
5008 goto set_ch_out;
5009 }
5010
46bc8d4b 5011 spin_lock_irqsave(&il->lock, flags);
be663ab6 5012
17d6e557 5013 /* Configure HT40 channels */
1c03c462
SG		 5014 if (il->ht.enabled != conf_is_ht(conf)) {
5015 il->ht.enabled = conf_is_ht(conf);
17d6e557
SG		 5016 ht_changed = true;
5017 }
1c03c462 5018 if (il->ht.enabled) {
17d6e557 5019 if (conf_is_ht40_minus(conf)) {
1c03c462 5020 il->ht.extension_chan_offset =
e7392364 5021 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
1c03c462 5022 il->ht.is_40mhz = true;
17d6e557 5023 } else if (conf_is_ht40_plus(conf)) {
1c03c462 5024 il->ht.extension_chan_offset =
e7392364 5025 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
1c03c462 5026 il->ht.is_40mhz = true;
17d6e557 5027 } else {
1c03c462 5028 il->ht.extension_chan_offset =
e7392364 5029 IEEE80211_HT_PARAM_CHA_SEC_NONE;
1c03c462 5030 il->ht.is_40mhz = false;
17d6e557
SG		 5031 }
5032 } else
1c03c462 5033 il->ht.is_40mhz = false;
be663ab6 5034
17d6e557
SG		 5035 /*
5036 * Default to no protection. Protection mode will
5037 * later be set from BSS config in il_ht_conf
5038 */
1c03c462 5039 il->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
be663ab6 5040
17d6e557
SG		 5041 /* if we are switching from ht to 2.4 clear flags
5042 * from any ht related info since 2.4 does not
5043 * support ht */
c8b03958
SG		 5044 if ((le16_to_cpu(il->staging.channel) != ch))
5045 il->staging.flags = 0;
be663ab6 5046
83007196 5047 il_set_rxon_channel(il, channel);
17d6e557 5048 il_set_rxon_ht(il, ht_conf);
be663ab6 5049
83007196 5050 il_set_flags_for_band(il, channel->band, il->vif);
be663ab6 5051
46bc8d4b 5052 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5053
c9363551
SG		 5054 if (il->ops->update_bcast_stations)
5055 ret = il->ops->update_bcast_stations(il);
be663ab6 5056
e7392364 5057set_ch_out:
be663ab6
WYG		 5058 /* The list of supported rates and rate mask can be different
5059 * for each band; since the band may have changed, reset
5060 * the rate mask to what mac80211 lists */
46bc8d4b 5061 il_set_rate(il);
be663ab6
WYG		 5062 }
5063
e7392364 5064 if (changed & (IEEE80211_CONF_CHANGE_PS | IEEE80211_CONF_CHANGE_IDLE)) {
46bc8d4b 5065 ret = il_power_update_mode(il, false);
be663ab6 5066 if (ret)
58de00a4 5067 D_MAC80211("Error setting sleep level\n");
be663ab6
WYG		 5068 }
5069
5070 if (changed & IEEE80211_CONF_CHANGE_POWER) {
e7392364
SG		 5071 D_MAC80211("TX Power old=%d new=%d\n", il->tx_power_user_lmt,
5072 conf->power_level);
be663ab6 5073
46bc8d4b 5074 il_set_tx_power(il, conf->power_level, false);
be663ab6
WYG		 5075 }
5076
46bc8d4b 5077 if (!il_is_ready(il)) {
58de00a4 5078 D_MAC80211("leave - not ready\n");
be663ab6
WYG		 5079 goto out;
5080 }
5081
5082 if (scan_active)
5083 goto out;
5084
c8b03958 5085 if (memcmp(&il->active, &il->staging, sizeof(il->staging)))
83007196 5086 il_commit_rxon(il);
17d6e557
SG		 5087 else
5088 D_INFO("Not re-sending same RXON configuration.\n");
5089 if (ht_changed)
83007196 5090 il_update_qos(il);
be663ab6
WYG		 5091
5092out:
9ce7b73c 5093 D_MAC80211("leave ret %d\n", ret);
46bc8d4b 5094 mutex_unlock(&il->mutex);
9ce7b73c 5095
be663ab6
WYG		 5096 return ret;
5097}
e2ebc833 5098EXPORT_SYMBOL(il_mac_config);
be663ab6 5099
e7392364
SG		 5100void
5101il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 5102{
46bc8d4b 5103 struct il_priv *il = hw->priv;
be663ab6 5104 unsigned long flags;
be663ab6 5105
46bc8d4b 5106 mutex_lock(&il->mutex);
9ce7b73c 5107 D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
be663ab6 5108
46bc8d4b 5109 spin_lock_irqsave(&il->lock, flags);
be663ab6 5110
9ce7b73c 5111 memset(&il->current_ht_config, 0, sizeof(struct il_ht_config));
be663ab6
WYG		 5112
5113 /* new association get rid of ibss beacon skb */
46bc8d4b
SG		 5114 if (il->beacon_skb)
5115 dev_kfree_skb(il->beacon_skb);
46bc8d4b 5116 il->beacon_skb = NULL;
46bc8d4b 5117 il->timestamp = 0;
be663ab6 5118
46bc8d4b 5119 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5120
46bc8d4b
SG		 5121 il_scan_cancel_timeout(il, 100);
5122 if (!il_is_ready_rf(il)) {
58de00a4 5123 D_MAC80211("leave - not ready\n");
46bc8d4b 5124 mutex_unlock(&il->mutex);
be663ab6
WYG		 5125 return;
5126 }
5127
9ce7b73c 5128 /* we are restarting association process */
c8b03958 5129 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
83007196 5130 il_commit_rxon(il);
be663ab6 5131
46bc8d4b 5132 il_set_rate(il);
be663ab6 5133
58de00a4 5134 D_MAC80211("leave\n");
9ce7b73c 5135 mutex_unlock(&il->mutex);
be663ab6 5136}
e2ebc833 5137EXPORT_SYMBOL(il_mac_reset_tsf);
be663ab6 5138
e7392364
SG		 5139static void
5140il_ht_conf(struct il_priv *il, struct ieee80211_vif *vif)
be663ab6 5141{
46bc8d4b 5142 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6
WYG		 5143 struct ieee80211_sta *sta;
5144 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
be663ab6 5145
58de00a4 5146 D_ASSOC("enter:\n");
be663ab6 5147
1c03c462 5148 if (!il->ht.enabled)
be663ab6
WYG		 5149 return;
5150
1c03c462 5151 il->ht.protection =
e7392364 5152 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
1c03c462 5153 il->ht.non_gf_sta_present =
e7392364
SG		 5154 !!(bss_conf->
5155 ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
be663ab6
WYG		 5156
5157 ht_conf->single_chain_sufficient = false;
5158
5159 switch (vif->type) {
5160 case NL80211_IFTYPE_STATION:
5161 rcu_read_lock();
5162 sta = ieee80211_find_sta(vif, bss_conf->bssid);
5163 if (sta) {
5164 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
5165 int maxstreams;
5166
e7392364
SG		 5167 maxstreams =
5168 (ht_cap->mcs.
5169 tx_params & IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
5170 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
be663ab6
WYG		 5171 maxstreams += 1;
5172
232913b5
SG		 5173 if (ht_cap->mcs.rx_mask[1] == 0 &&
5174 ht_cap->mcs.rx_mask[2] == 0)
be663ab6
WYG		 5175 ht_conf->single_chain_sufficient = true;
5176 if (maxstreams <= 1)
5177 ht_conf->single_chain_sufficient = true;
5178 } else {
5179 /*
5180 * If at all, this can only happen through a race
5181 * when the AP disconnects us while we're still
5182 * setting up the connection, in that case mac80211
5183 * will soon tell us about that.
5184 */
5185 ht_conf->single_chain_sufficient = true;
5186 }
5187 rcu_read_unlock();
5188 break;
5189 case NL80211_IFTYPE_ADHOC:
5190 ht_conf->single_chain_sufficient = true;
5191 break;
5192 default:
5193 break;
5194 }
5195
58de00a4 5196 D_ASSOC("leave\n");
be663ab6
WYG		 5197}
5198
e7392364
SG		 5199static inline void
5200il_set_no_assoc(struct il_priv *il, struct ieee80211_vif *vif)
be663ab6 5201{
be663ab6
WYG		 5202 /*
5203 * inform the ucode that there is no longer an
5204 * association and that no more packets should be
5205 * sent
5206 */
c8b03958
SG		 5207 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5208 il->staging.assoc_id = 0;
83007196 5209 il_commit_rxon(il);
be663ab6
WYG		 5210}
5211
e7392364
SG		 5212static void
5213il_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 5214{
46bc8d4b 5215 struct il_priv *il = hw->priv;
be663ab6
WYG		 5216 unsigned long flags;
5217 __le64 timestamp;
5218 struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
5219
5220 if (!skb)
5221 return;
5222
58de00a4 5223 D_MAC80211("enter\n");
be663ab6 5224
46bc8d4b 5225 lockdep_assert_held(&il->mutex);
be663ab6 5226
83007196
SG		 5227 if (!il->beacon_enabled) {
5228 IL_ERR("update beacon with no beaconing enabled\n");
be663ab6
WYG		 5229 dev_kfree_skb(skb);
5230 return;
5231 }
5232
46bc8d4b 5233 spin_lock_irqsave(&il->lock, flags);
be663ab6 5234
46bc8d4b
SG		 5235 if (il->beacon_skb)
5236 dev_kfree_skb(il->beacon_skb);
be663ab6 5237
46bc8d4b 5238 il->beacon_skb = skb;
be663ab6
WYG		 5239
5240 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
46bc8d4b 5241 il->timestamp = le64_to_cpu(timestamp);
be663ab6 5242
58de00a4 5243 D_MAC80211("leave\n");
46bc8d4b 5244 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5245
46bc8d4b 5246 if (!il_is_ready_rf(il)) {
58de00a4 5247 D_MAC80211("leave - RF not ready\n");
be663ab6
WYG		 5248 return;
5249 }
5250
c9363551 5251 il->ops->post_associate(il);
be663ab6
WYG		 5252}
5253
e7392364
SG		 5254void
5255il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5256 struct ieee80211_bss_conf *bss_conf, u32 changes)
be663ab6 5257{
46bc8d4b 5258 struct il_priv *il = hw->priv;
be663ab6
WYG		 5259 int ret;
5260
46bc8d4b 5261 mutex_lock(&il->mutex);
9ce7b73c 5262 D_MAC80211("enter: changes 0x%x\n", changes);
be663ab6 5263
46bc8d4b 5264 if (!il_is_alive(il)) {
9ce7b73c 5265 D_MAC80211("leave - not alive\n");
46bc8d4b 5266 mutex_unlock(&il->mutex);
28a6e577
SG		 5267 return;
5268 }
5269
be663ab6
WYG		 5270 if (changes & BSS_CHANGED_QOS) {
5271 unsigned long flags;
5272
46bc8d4b 5273 spin_lock_irqsave(&il->lock, flags);
8d44f2bd 5274 il->qos_data.qos_active = bss_conf->qos;
83007196 5275 il_update_qos(il);
46bc8d4b 5276 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5277 }
5278
5279 if (changes & BSS_CHANGED_BEACON_ENABLED) {
83007196 5280 /* FIXME: can we remove beacon_enabled ? */
be663ab6 5281 if (vif->bss_conf.enable_beacon)
83007196 5282 il->beacon_enabled = true;
be663ab6 5283 else
83007196 5284 il->beacon_enabled = false;
be663ab6
WYG		 5285 }
5286
5287 if (changes & BSS_CHANGED_BSSID) {
58de00a4 5288 D_MAC80211("BSSID %pM\n", bss_conf->bssid);
be663ab6
WYG		 5289
5290 /*
e92109be
SG		 5291 * If there is currently a HW scan going on in the background,
5292 * then we need to cancel it, otherwise sometimes we are not
5293 * able to authenticate (FIXME: why ?)
be663ab6 5294 */
46bc8d4b 5295 if (il_scan_cancel_timeout(il, 100)) {
9ce7b73c 5296 D_MAC80211("leave - scan abort failed\n");
46bc8d4b 5297 mutex_unlock(&il->mutex);
be663ab6
WYG		 5298 return;
5299 }
5300
5301 /* mac80211 only sets assoc when in STATION mode */
e92109be 5302 memcpy(il->staging.bssid_addr, bss_conf->bssid, ETH_ALEN);
be663ab6 5303
e92109be
SG		 5304 /* FIXME: currently needed in a few places */
5305 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
be663ab6
WYG		 5306 }
5307
5308 /*
5309 * This needs to be after setting the BSSID in case
5310 * mac80211 decides to do both changes at once because
5311 * it will invoke post_associate.
5312 */
232913b5 5313 if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON))
e2ebc833 5314 il_beacon_update(hw, vif);
be663ab6
WYG		 5315
5316 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
e7392364 5317 D_MAC80211("ERP_PREAMBLE %d\n", bss_conf->use_short_preamble);
be663ab6 5318 if (bss_conf->use_short_preamble)
c8b03958 5319 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6 5320 else
c8b03958 5321 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6
WYG		 5322 }
5323
5324 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
e7392364 5325 D_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
232913b5 5326 if (bss_conf->use_cts_prot && il->band != IEEE80211_BAND_5GHZ)
c8b03958 5327 il->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
be663ab6 5328 else
c8b03958 5329 il->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
be663ab6 5330 if (bss_conf->use_cts_prot)
c8b03958 5331 il->staging.flags |= RXON_FLG_SELF_CTS_EN;
be663ab6 5332 else
c8b03958 5333 il->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
be663ab6
WYG		 5334 }
5335
5336 if (changes & BSS_CHANGED_BASIC_RATES) {
5337 /* XXX use this information
5338 *
e2ebc833 5339 * To do that, remove code from il_set_rate() and put something
be663ab6
WYG		 5340 * like this here:
5341 *
e7392364 5342 if (A-band)
c8b03958 5343 il->staging.ofdm_basic_rates =
e7392364
SG		 5344 bss_conf->basic_rates;
5345 else
c8b03958 5346 il->staging.ofdm_basic_rates =
e7392364 5347 bss_conf->basic_rates >> 4;
c8b03958 5348 il->staging.cck_basic_rates =
e7392364 5349 bss_conf->basic_rates & 0xF;
be663ab6
WYG		 5350 */
5351 }
5352
5353 if (changes & BSS_CHANGED_HT) {
46bc8d4b 5354 il_ht_conf(il, vif);
be663ab6 5355
c9363551
SG		 5356 if (il->ops->set_rxon_chain)
5357 il->ops->set_rxon_chain(il);
be663ab6
WYG		 5358 }
5359
5360 if (changes & BSS_CHANGED_ASSOC) {
58de00a4 5361 D_MAC80211("ASSOC %d\n", bss_conf->assoc);
be663ab6 5362 if (bss_conf->assoc) {
e9ac0745 5363 il->timestamp = bss_conf->last_tsf;
be663ab6 5364
46bc8d4b 5365 if (!il_is_rfkill(il))
c9363551 5366 il->ops->post_associate(il);
be663ab6 5367 } else
46bc8d4b 5368 il_set_no_assoc(il, vif);
be663ab6
WYG		 5369 }
5370
c8b03958 5371 if (changes && il_is_associated(il) && bss_conf->aid) {
e7392364 5372 D_MAC80211("Changes (%#x) while associated\n", changes);
83007196 5373 ret = il_send_rxon_assoc(il);
be663ab6
WYG		 5374 if (!ret) {
5375 /* Sync active_rxon with latest change. */
c8b03958 5376 memcpy((void *)&il->active, &il->staging,
e7392364 5377 sizeof(struct il_rxon_cmd));
be663ab6
WYG		 5378 }
5379 }
5380
5381 if (changes & BSS_CHANGED_BEACON_ENABLED) {
5382 if (vif->bss_conf.enable_beacon) {
c8b03958 5383 memcpy(il->staging.bssid_addr, bss_conf->bssid,
e7392364 5384 ETH_ALEN);
46bc8d4b 5385 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
c9363551 5386 il->ops->config_ap(il);
be663ab6 5387 } else
46bc8d4b 5388 il_set_no_assoc(il, vif);
be663ab6
WYG		 5389 }
5390
5391 if (changes & BSS_CHANGED_IBSS) {
9ce7b73c
SG		 5392 ret = il->ops->manage_ibss_station(il, vif,
5393 bss_conf->ibss_joined);
be663ab6 5394 if (ret)
9406f797 5395 IL_ERR("failed to %s IBSS station %pM\n",
e7392364
SG		 5396 bss_conf->ibss_joined ? "add" : "remove",
5397 bss_conf->bssid);
be663ab6
WYG		 5398 }
5399
58de00a4 5400 D_MAC80211("leave\n");
9ce7b73c 5401 mutex_unlock(&il->mutex);
be663ab6 5402}
e2ebc833 5403EXPORT_SYMBOL(il_mac_bss_info_changed);
be663ab6 5404
e7392364
SG		 5405irqreturn_t
5406il_isr(int irq, void *data)
be663ab6 5407{
46bc8d4b 5408 struct il_priv *il = data;
be663ab6
WYG		 5409 u32 inta, inta_mask;
5410 u32 inta_fh;
5411 unsigned long flags;
46bc8d4b 5412 if (!il)
be663ab6
WYG		 5413 return IRQ_NONE;
5414
46bc8d4b 5415 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 5416
5417 /* Disable (but don't clear!) interrupts here to avoid
5418 * back-to-back ISRs and sporadic interrupts from our NIC.
5419 * If we have something to service, the tasklet will re-enable ints.
5420 * If we *don't* have something, we'll re-enable before leaving here. */
e7392364 5421 inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */
841b2cca 5422 _il_wr(il, CSR_INT_MASK, 0x00000000);
be663ab6
WYG		 5423
5424 /* Discover which interrupts are active/pending */
841b2cca
SG		 5425 inta = _il_rd(il, CSR_INT);
5426 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
be663ab6
WYG		 5427
5428 /* Ignore interrupt if there's nothing in NIC to service.
5429 * This may be due to IRQ shared with another device,
5430 * or due to sporadic interrupts thrown from our NIC. */
5431 if (!inta && !inta_fh) {
e7392364 5432 D_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
be663ab6
WYG		 5433 goto none;
5434 }
5435
232913b5 5436 if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) {
be663ab6
WYG		 5437 /* Hardware disappeared. It might have already raised
5438 * an interrupt */
9406f797 5439 IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta);
be663ab6
WYG		 5440 goto unplugged;
5441 }
5442
e7392364
SG		 5443 D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, inta_mask,
5444 inta_fh);
be663ab6
WYG		 5445
5446 inta &= ~CSR_INT_BIT_SCD;
5447
e2ebc833 5448 /* il_irq_tasklet() will service interrupts and re-enable them */
be663ab6 5449 if (likely(inta || inta_fh))
46bc8d4b 5450 tasklet_schedule(&il->irq_tasklet);
be663ab6
WYG		 5451
5452unplugged:
46bc8d4b 5453 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5454 return IRQ_HANDLED;
5455
5456none:
5457 /* re-enable interrupts here since we don't have anything to service. */
93fd74e3 5458 /* only Re-enable if disabled by irq */
a6766ccd 5459 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b
SG		 5460 il_enable_interrupts(il);
5461 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5462 return IRQ_NONE;
5463}
e2ebc833 5464EXPORT_SYMBOL(il_isr);
be663ab6
WYG		 5465
5466/*
e2ebc833 5467 * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
be663ab6
WYG		 5468 * function.
5469 */
e7392364
SG		 5470void
5471il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1722f8e1 5472 __le16 fc, __le32 *tx_flags)
be663ab6
WYG		 5473{
5474 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
5475 *tx_flags |= TX_CMD_FLG_RTS_MSK;
5476 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
5477 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5478
5479 if (!ieee80211_is_mgmt(fc))
5480 return;
5481
5482 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
5483 case cpu_to_le16(IEEE80211_STYPE_AUTH):
5484 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
5485 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
5486 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
5487 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5488 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5489 break;
5490 }
e7392364
SG		 5491 } else if (info->control.rates[0].
5492 flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
be663ab6
WYG		 5493 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5494 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5495 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5496 }
5497}
e2ebc833 5498EXPORT_SYMBOL(il_tx_cmd_protection);
Linux kernel - Deliverables
This page took 0.520716 seconds and 5 git commands to generate.