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1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
01f8162a | 8 | * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. |
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9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of version 2 of the GNU General Public License as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * Intel Linux Wireless <ilw@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
01f8162a | 33 | * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. |
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34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
63 | #ifndef __iwl_3945_fh_h__ | |
64 | #define __iwl_3945_fh_h__ | |
65 | ||
66 | /************************************/ | |
67 | /* iwl3945 Flow Handler Definitions */ | |
68 | /************************************/ | |
69 | ||
70 | /** | |
71 | * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) | |
72 | * Addresses are offsets from device's PCI hardware base address. | |
73 | */ | |
74 | #define FH39_MEM_LOWER_BOUND (0x0800) | |
75 | #define FH39_MEM_UPPER_BOUND (0x1000) | |
76 | ||
77 | #define FH39_CBCC_TABLE (FH39_MEM_LOWER_BOUND + 0x140) | |
78 | #define FH39_TFDB_TABLE (FH39_MEM_LOWER_BOUND + 0x180) | |
79 | #define FH39_RCSR_TABLE (FH39_MEM_LOWER_BOUND + 0x400) | |
80 | #define FH39_RSSR_TABLE (FH39_MEM_LOWER_BOUND + 0x4c0) | |
81 | #define FH39_TCSR_TABLE (FH39_MEM_LOWER_BOUND + 0x500) | |
82 | #define FH39_TSSR_TABLE (FH39_MEM_LOWER_BOUND + 0x680) | |
83 | ||
84 | /* TFDB (Transmit Frame Buffer Descriptor) */ | |
85 | #define FH39_TFDB(_ch, buf) (FH39_TFDB_TABLE + \ | |
86 | ((_ch) * 2 + (buf)) * 0x28) | |
87 | #define FH39_TFDB_CHNL_BUF_CTRL_REG(_ch) (FH39_TFDB_TABLE + 0x50 * (_ch)) | |
88 | ||
89 | /* CBCC channel is [0,2] */ | |
90 | #define FH39_CBCC(_ch) (FH39_CBCC_TABLE + (_ch) * 0x8) | |
91 | #define FH39_CBCC_CTRL(_ch) (FH39_CBCC(_ch) + 0x00) | |
92 | #define FH39_CBCC_BASE(_ch) (FH39_CBCC(_ch) + 0x04) | |
93 | ||
94 | /* RCSR channel is [0,2] */ | |
95 | #define FH39_RCSR(_ch) (FH39_RCSR_TABLE + (_ch) * 0x40) | |
96 | #define FH39_RCSR_CONFIG(_ch) (FH39_RCSR(_ch) + 0x00) | |
97 | #define FH39_RCSR_RBD_BASE(_ch) (FH39_RCSR(_ch) + 0x04) | |
98 | #define FH39_RCSR_WPTR(_ch) (FH39_RCSR(_ch) + 0x20) | |
99 | #define FH39_RCSR_RPTR_ADDR(_ch) (FH39_RCSR(_ch) + 0x24) | |
100 | ||
101 | #define FH39_RSCSR_CHNL0_WPTR (FH39_RCSR_WPTR(0)) | |
102 | ||
103 | /* RSSR */ | |
104 | #define FH39_RSSR_CTRL (FH39_RSSR_TABLE + 0x000) | |
105 | #define FH39_RSSR_STATUS (FH39_RSSR_TABLE + 0x004) | |
106 | ||
107 | /* TCSR */ | |
108 | #define FH39_TCSR(_ch) (FH39_TCSR_TABLE + (_ch) * 0x20) | |
109 | #define FH39_TCSR_CONFIG(_ch) (FH39_TCSR(_ch) + 0x00) | |
110 | #define FH39_TCSR_CREDIT(_ch) (FH39_TCSR(_ch) + 0x04) | |
111 | #define FH39_TCSR_BUFF_STTS(_ch) (FH39_TCSR(_ch) + 0x08) | |
112 | ||
113 | /* TSSR */ | |
114 | #define FH39_TSSR_CBB_BASE (FH39_TSSR_TABLE + 0x000) | |
115 | #define FH39_TSSR_MSG_CONFIG (FH39_TSSR_TABLE + 0x008) | |
116 | #define FH39_TSSR_TX_STATUS (FH39_TSSR_TABLE + 0x010) | |
117 | ||
118 | ||
119 | /* DBM */ | |
120 | ||
121 | #define FH39_SRVC_CHNL (6) | |
122 | ||
123 | #define FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20) | |
124 | #define FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4) | |
125 | ||
126 | #define FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000) | |
127 | ||
128 | #define FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000) | |
129 | ||
130 | #define FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000) | |
131 | ||
132 | #define FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000) | |
133 | ||
134 | #define FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000) | |
135 | ||
136 | #define FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000) | |
137 | ||
138 | #define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) | |
139 | #define FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001) | |
140 | ||
141 | #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) | |
142 | #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) | |
143 | ||
144 | #define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) | |
145 | ||
146 | #define FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) | |
147 | ||
148 | #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) | |
149 | #define FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) | |
150 | ||
151 | #define FH39_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000) | |
152 | ||
153 | #define FH39_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001) | |
154 | ||
155 | #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000) | |
156 | #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000) | |
157 | ||
158 | #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400) | |
159 | ||
160 | #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100) | |
161 | #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080) | |
162 | ||
163 | #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020) | |
164 | #define FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005) | |
165 | ||
166 | #define FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) (BIT(_ch) << 24) | |
167 | #define FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch) (BIT(_ch) << 16) | |
168 | ||
169 | #define FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_ch) \ | |
170 | (FH39_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_ch) | \ | |
171 | FH39_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_ch)) | |
172 | ||
173 | #define FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) | |
174 | ||
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175 | struct iwl3945_tfd_tb { |
176 | __le32 addr; | |
177 | __le32 len; | |
178 | } __attribute__ ((packed)); | |
179 | ||
180 | struct iwl3945_tfd { | |
181 | __le32 control_flags; | |
182 | struct iwl3945_tfd_tb tbs[4]; | |
183 | u8 __pad[28]; | |
184 | } __attribute__ ((packed)); | |
185 | ||
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186 | |
187 | #endif /* __iwl_3945_fh_h__ */ | |
188 |