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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
01f8162a | 8 | * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
01ebd063 | 11 | * it under the terms of version 2 of the GNU General Public License as |
b481de9c ZY |
12 | * published by the Free Software Foundation. |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
759ef89f | 28 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
01f8162a | 33 | * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
fcd427bb BC |
63 | /* |
64 | * Please use this file (iwl-3945-hw.h) only for hardware-related definitions. | |
65 | * Please use iwl-3945-commands.h for uCode API definitions. | |
66 | * Please use iwl-3945.h for driver implementation definitions. | |
67 | */ | |
b481de9c ZY |
68 | |
69 | #ifndef __iwl_3945_hw__ | |
70 | #define __iwl_3945_hw__ | |
71 | ||
0f741d99 SO |
72 | #include "iwl-eeprom.h" |
73 | ||
1fea8e88 BC |
74 | /* |
75 | * uCode queue management definitions ... | |
76 | * Queue #4 is the command queue for 3945 and 4965. | |
77 | */ | |
69d00d27 | 78 | #define IWL_CMD_QUEUE_NUM 4 |
5d08cd1d CH |
79 | |
80 | /* Time constants */ | |
81 | #define SHORT_SLOT_TIME 9 | |
82 | #define LONG_SLOT_TIME 20 | |
83 | ||
84 | /* RSSI to dBm */ | |
250bdd21 | 85 | #define IWL39_RSSI_OFFSET 95 |
5d08cd1d CH |
86 | |
87 | /* | |
796083cb | 88 | * EEPROM related constants, enums, and structures. |
5d08cd1d | 89 | */ |
5d08cd1d CH |
90 | #define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7) |
91 | ||
5d08cd1d CH |
92 | /* |
93 | * Mapping of a Tx power level, at factory calibration temperature, | |
94 | * to a radio/DSP gain table index. | |
95 | * One for each of 5 "sample" power levels in each band. | |
96 | * v_det is measured at the factory, using the 3945's built-in power amplifier | |
97 | * (PA) output voltage detector. This same detector is used during Tx of | |
98 | * long packets in normal operation to provide feedback as to proper output | |
99 | * level. | |
100 | * Data copied from EEPROM. | |
796083cb | 101 | * DO NOT ALTER THIS STRUCTURE!!! |
5d08cd1d | 102 | */ |
bb8c093b | 103 | struct iwl3945_eeprom_txpower_sample { |
5d08cd1d CH |
104 | u8 gain_index; /* index into power (gain) setup table ... */ |
105 | s8 power; /* ... for this pwr level for this chnl group */ | |
106 | u16 v_det; /* PA output voltage */ | |
107 | } __attribute__ ((packed)); | |
108 | ||
109 | /* | |
110 | * Mappings of Tx power levels -> nominal radio/DSP gain table indexes. | |
111 | * One for each channel group (a.k.a. "band") (1 for BG, 4 for A). | |
112 | * Tx power setup code interpolates between the 5 "sample" power levels | |
113 | * to determine the nominal setup for a requested power level. | |
114 | * Data copied from EEPROM. | |
115 | * DO NOT ALTER THIS STRUCTURE!!! | |
116 | */ | |
bb8c093b | 117 | struct iwl3945_eeprom_txpower_group { |
796083cb | 118 | struct iwl3945_eeprom_txpower_sample samples[5]; /* 5 power levels */ |
5d08cd1d CH |
119 | s32 a, b, c, d, e; /* coefficients for voltage->power |
120 | * formula (signed) */ | |
121 | s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on | |
796083cb | 122 | * frequency (signed) */ |
5d08cd1d CH |
123 | s8 saturation_power; /* highest power possible by h/w in this |
124 | * band */ | |
125 | u8 group_channel; /* "representative" channel # in this band */ | |
126 | s16 temperature; /* h/w temperature at factory calib this band | |
127 | * (signed) */ | |
128 | } __attribute__ ((packed)); | |
129 | ||
130 | /* | |
131 | * Temperature-based Tx-power compensation data, not band-specific. | |
132 | * These coefficients are use to modify a/b/c/d/e coeffs based on | |
133 | * difference between current temperature and factory calib temperature. | |
134 | * Data copied from EEPROM. | |
135 | */ | |
bb8c093b | 136 | struct iwl3945_eeprom_temperature_corr { |
5d08cd1d CH |
137 | u32 Ta; |
138 | u32 Tb; | |
139 | u32 Tc; | |
140 | u32 Td; | |
141 | u32 Te; | |
142 | } __attribute__ ((packed)); | |
143 | ||
796083cb BC |
144 | /* |
145 | * EEPROM map | |
146 | */ | |
bb8c093b | 147 | struct iwl3945_eeprom { |
5d08cd1d | 148 | u8 reserved0[16]; |
5d08cd1d CH |
149 | u16 device_id; /* abs.ofs: 16 */ |
150 | u8 reserved1[2]; | |
5d08cd1d CH |
151 | u16 pmc; /* abs.ofs: 20 */ |
152 | u8 reserved2[20]; | |
5d08cd1d CH |
153 | u8 mac_address[6]; /* abs.ofs: 42 */ |
154 | u8 reserved3[58]; | |
5d08cd1d CH |
155 | u16 board_revision; /* abs.ofs: 106 */ |
156 | u8 reserved4[11]; | |
5d08cd1d CH |
157 | u8 board_pba_number[9]; /* abs.ofs: 119 */ |
158 | u8 reserved5[8]; | |
5d08cd1d | 159 | u16 version; /* abs.ofs: 136 */ |
5d08cd1d | 160 | u8 sku_cap; /* abs.ofs: 138 */ |
5d08cd1d | 161 | u8 leds_mode; /* abs.ofs: 139 */ |
5d08cd1d | 162 | u16 oem_mode; |
5d08cd1d | 163 | u16 wowlan_mode; /* abs.ofs: 142 */ |
5d08cd1d | 164 | u16 leds_time_interval; /* abs.ofs: 144 */ |
5d08cd1d | 165 | u8 leds_off_time; /* abs.ofs: 146 */ |
5d08cd1d | 166 | u8 leds_on_time; /* abs.ofs: 147 */ |
5d08cd1d | 167 | u8 almgor_m_version; /* abs.ofs: 148 */ |
5d08cd1d CH |
168 | u8 antenna_switch_type; /* abs.ofs: 149 */ |
169 | u8 reserved6[42]; | |
5d08cd1d | 170 | u8 sku_id[4]; /* abs.ofs: 192 */ |
796083cb BC |
171 | |
172 | /* | |
173 | * Per-channel regulatory data. | |
174 | * | |
175 | * Each channel that *might* be supported by 3945 or 4965 has a fixed location | |
176 | * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory | |
177 | * txpower (MSB). | |
178 | * | |
179 | * Entries immediately below are for 20 MHz channel width. FAT (40 MHz) | |
180 | * channels (only for 4965, not supported by 3945) appear later in the EEPROM. | |
181 | * | |
182 | * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 | |
183 | */ | |
5d08cd1d | 184 | u16 band_1_count; /* abs.ofs: 196 */ |
e6148917 | 185 | struct iwl_eeprom_channel band_1_channels[14]; /* abs.ofs: 198 */ |
796083cb BC |
186 | |
187 | /* | |
188 | * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196, | |
189 | * 5.0 GHz channels 7, 8, 11, 12, 16 | |
190 | * (4915-5080MHz) (none of these is ever supported) | |
191 | */ | |
5d08cd1d | 192 | u16 band_2_count; /* abs.ofs: 226 */ |
0f741d99 | 193 | struct iwl_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */ |
796083cb BC |
194 | |
195 | /* | |
196 | * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 | |
197 | * (5170-5320MHz) | |
198 | */ | |
5d08cd1d | 199 | u16 band_3_count; /* abs.ofs: 254 */ |
0f741d99 | 200 | struct iwl_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */ |
796083cb BC |
201 | |
202 | /* | |
203 | * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 | |
204 | * (5500-5700MHz) | |
205 | */ | |
5d08cd1d | 206 | u16 band_4_count; /* abs.ofs: 280 */ |
0f741d99 | 207 | struct iwl_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */ |
796083cb BC |
208 | |
209 | /* | |
210 | * 5.7 GHz channels 145, 149, 153, 157, 161, 165 | |
211 | * (5725-5825MHz) | |
212 | */ | |
5d08cd1d | 213 | u16 band_5_count; /* abs.ofs: 304 */ |
0f741d99 | 214 | struct iwl_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */ |
5d08cd1d CH |
215 | |
216 | u8 reserved9[194]; | |
217 | ||
796083cb BC |
218 | /* |
219 | * 3945 Txpower calibration data. | |
220 | */ | |
5d08cd1d | 221 | #define IWL_NUM_TX_CALIB_GROUPS 5 |
bb8c093b | 222 | struct iwl3945_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS]; |
5d08cd1d | 223 | /* abs.ofs: 512 */ |
796083cb | 224 | struct iwl3945_eeprom_temperature_corr corrections; /* abs.ofs: 832 */ |
5d08cd1d CH |
225 | u8 reserved16[172]; /* fill out to full 1024 byte block */ |
226 | } __attribute__ ((packed)); | |
227 | ||
e6148917 | 228 | #define IWL3945_EEPROM_IMG_SIZE 1024 |
5d08cd1d | 229 | |
796083cb BC |
230 | /* End of EEPROM */ |
231 | ||
5d08cd1d CH |
232 | #define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */ |
233 | #define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */ | |
234 | ||
5d08cd1d | 235 | #define TFD_QUEUE_MIN 0 |
21c02a1a | 236 | #define TFD_QUEUE_MAX 5 /* 4 DATA + 1 CMD */ |
5d08cd1d | 237 | |
5d08cd1d CH |
238 | #define IWL_NUM_SCAN_RATES (2) |
239 | ||
5d08cd1d | 240 | #define IWL_DEFAULT_TX_RETRY 15 |
5d08cd1d CH |
241 | |
242 | /*********************************************/ | |
243 | ||
244 | #define RFD_SIZE 4 | |
245 | #define NUM_TFD_CHUNKS 4 | |
246 | ||
247 | #define RX_QUEUE_SIZE 256 | |
248 | #define RX_QUEUE_MASK 255 | |
249 | #define RX_QUEUE_SIZE_LOG 8 | |
250 | ||
5d08cd1d CH |
251 | #define U32_PAD(n) ((4-(n))&0x3) |
252 | ||
8a1b0245 RC |
253 | #define TFD_CTL_COUNT_SET(n) (n << 24) |
254 | #define TFD_CTL_COUNT_GET(ctl) ((ctl >> 24) & 7) | |
255 | #define TFD_CTL_PAD_SET(n) (n << 28) | |
256 | #define TFD_CTL_PAD_GET(ctl) (ctl >> 28) | |
5d08cd1d | 257 | |
5d08cd1d CH |
258 | /* |
259 | * RX related structures and functions | |
260 | */ | |
261 | #define RX_FREE_BUFFERS 64 | |
262 | #define RX_LOW_WATERMARK 8 | |
263 | ||
fcd427bb BC |
264 | /* Sizes and addresses for instruction and data memory (SRAM) in |
265 | * 3945's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */ | |
250bdd21 SO |
266 | #define IWL39_RTC_INST_LOWER_BOUND (0x000000) |
267 | #define IWL39_RTC_INST_UPPER_BOUND (0x014000) | |
fcd427bb | 268 | |
250bdd21 SO |
269 | #define IWL39_RTC_DATA_LOWER_BOUND (0x800000) |
270 | #define IWL39_RTC_DATA_UPPER_BOUND (0x808000) | |
b481de9c | 271 | |
250bdd21 SO |
272 | #define IWL39_RTC_INST_SIZE (IWL39_RTC_INST_UPPER_BOUND - \ |
273 | IWL39_RTC_INST_LOWER_BOUND) | |
274 | #define IWL39_RTC_DATA_SIZE (IWL39_RTC_DATA_UPPER_BOUND - \ | |
275 | IWL39_RTC_DATA_LOWER_BOUND) | |
b481de9c | 276 | |
250bdd21 SO |
277 | #define IWL39_MAX_INST_SIZE IWL39_RTC_INST_SIZE |
278 | #define IWL39_MAX_DATA_SIZE IWL39_RTC_DATA_SIZE | |
fcd427bb BC |
279 | |
280 | /* Size of uCode instruction memory in bootstrap state machine */ | |
250bdd21 | 281 | #define IWL39_MAX_BSM_SIZE IWL39_RTC_INST_SIZE |
fcd427bb | 282 | |
dfe7d458 | 283 | #define IWL39_MAX_NUM_QUEUES 8 |
b481de9c | 284 | |
bb8c093b | 285 | static inline int iwl3945_hw_valid_rtc_data_addr(u32 addr) |
b481de9c | 286 | { |
250bdd21 SO |
287 | return (addr >= IWL39_RTC_DATA_LOWER_BOUND) && |
288 | (addr < IWL39_RTC_DATA_UPPER_BOUND); | |
b481de9c ZY |
289 | } |
290 | ||
bb8c093b CH |
291 | /* Base physical address of iwl3945_shared is provided to FH_TSSR_CBB_BASE |
292 | * and &iwl3945_shared.rx_read_ptr[0] is provided to FH_RCSR_RPTR_ADDR(0) */ | |
293 | struct iwl3945_shared { | |
b481de9c | 294 | __le32 tx_base_ptr[8]; |
b481de9c ZY |
295 | } __attribute__ ((packed)); |
296 | ||
bb8c093b | 297 | static inline u8 iwl3945_hw_get_rate(__le16 rate_n_flags) |
b481de9c ZY |
298 | { |
299 | return le16_to_cpu(rate_n_flags) & 0xFF; | |
300 | } | |
301 | ||
bb8c093b | 302 | static inline u16 iwl3945_hw_get_rate_n_flags(__le16 rate_n_flags) |
b481de9c ZY |
303 | { |
304 | return le16_to_cpu(rate_n_flags); | |
305 | } | |
306 | ||
bb8c093b | 307 | static inline __le16 iwl3945_hw_set_rate_n_flags(u8 rate, u16 flags) |
b481de9c ZY |
308 | { |
309 | return cpu_to_le16((u16)rate|flags); | |
310 | } | |
311 | #endif |