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iwlwifi: specify the valid tx/rx chain in device config structure
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
dbb6654c 41#include "iwl-fh.h"
bddadf86 42#include "iwl-3945-fh.h"
600c0e11 43#include "iwl-commands.h"
17f841cd 44#include "iwl-sta.h"
b481de9c 45#include "iwl-3945.h"
e6148917 46#include "iwl-eeprom.h"
5d08cd1d 47#include "iwl-helpers.h"
5747d47f 48#include "iwl-core.h"
e932a609
JB		 49#include "iwl-led.h"
50#include "iwl-3945-led.h"
b481de9c
ZY		 51
52#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
53 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 60 IWL_RATE_##np##M_INDEX, \
61 IWL_RATE_##r##M_INDEX_TABLE, \
62 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 63
64/*
65 * Parameter order:
66 * rate, prev rate, next rate, prev tgg rate, next tgg rate
67 *
68 * If there isn't a valid next or previous rate then INV is used which
69 * maps to IWL_RATE_INVALID
70 *
71 */
d9829a67 72const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 73 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
74 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
75 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
76 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 77 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
78 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
79 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
80 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
81 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
82 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
83 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
84 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 85};
86
bb8c093b 87/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 88#define IWL_EVT_DISABLE (0)
89#define IWL_EVT_DISABLE_SIZE (1532/32)
90
91/**
bb8c093b 92 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 93 *
94 * Disable an event by writing "1"s into "disable"
95 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
96 * Default values of 0 enable uCode events to be logged.
97 * Use for only special debugging. This function is just a placeholder as-is,
98 * you'll need to provide the special bits! ...
99 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 100void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 101{
b481de9c
ZY		 102 int i;
103 u32 base; /* SRAM address of event log header */
104 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
105 u32 array_size; /* # of u32 entries in array */
106 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
107 0x00000000, /* 31 - 0 Event id numbers */
108 0x00000000, /* 63 - 32 */
109 0x00000000, /* 95 - 64 */
110 0x00000000, /* 127 - 96 */
111 0x00000000, /* 159 - 128 */
112 0x00000000, /* 191 - 160 */
113 0x00000000, /* 223 - 192 */
114 0x00000000, /* 255 - 224 */
115 0x00000000, /* 287 - 256 */
116 0x00000000, /* 319 - 288 */
117 0x00000000, /* 351 - 320 */
118 0x00000000, /* 383 - 352 */
119 0x00000000, /* 415 - 384 */
120 0x00000000, /* 447 - 416 */
121 0x00000000, /* 479 - 448 */
122 0x00000000, /* 511 - 480 */
123 0x00000000, /* 543 - 512 */
124 0x00000000, /* 575 - 544 */
125 0x00000000, /* 607 - 576 */
126 0x00000000, /* 639 - 608 */
127 0x00000000, /* 671 - 640 */
128 0x00000000, /* 703 - 672 */
129 0x00000000, /* 735 - 704 */
130 0x00000000, /* 767 - 736 */
131 0x00000000, /* 799 - 768 */
132 0x00000000, /* 831 - 800 */
133 0x00000000, /* 863 - 832 */
134 0x00000000, /* 895 - 864 */
135 0x00000000, /* 927 - 896 */
136 0x00000000, /* 959 - 928 */
137 0x00000000, /* 991 - 960 */
138 0x00000000, /* 1023 - 992 */
139 0x00000000, /* 1055 - 1024 */
140 0x00000000, /* 1087 - 1056 */
141 0x00000000, /* 1119 - 1088 */
142 0x00000000, /* 1151 - 1120 */
143 0x00000000, /* 1183 - 1152 */
144 0x00000000, /* 1215 - 1184 */
145 0x00000000, /* 1247 - 1216 */
146 0x00000000, /* 1279 - 1248 */
147 0x00000000, /* 1311 - 1280 */
148 0x00000000, /* 1343 - 1312 */
149 0x00000000, /* 1375 - 1344 */
150 0x00000000, /* 1407 - 1376 */
151 0x00000000, /* 1439 - 1408 */
152 0x00000000, /* 1471 - 1440 */
153 0x00000000, /* 1503 - 1472 */
154 };
155
156 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 157 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 158 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 159 return;
160 }
161
5d49f498
AK		 162 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
163 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
b481de9c
ZY		 164
165 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
e1623446 166 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
b481de9c 167 disable_ptr);
b481de9c 168 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 169 iwl_write_targ_mem(priv,
af7cca2a
TW		 170 disable_ptr + (i * sizeof(u32)),
171 evt_disable[i]);
b481de9c 172
b481de9c 173 } else {
e1623446
TW		 174 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
175 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
176 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
b481de9c
ZY		 177 disable_ptr, array_size);
178 }
179
180}
181
17744ff6
TW		 182static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
183{
184 int idx;
185
186 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
187 if (iwl3945_rates[idx].plcp == plcp)
188 return idx;
189 return -1;
190}
191
d08853a3 192#ifdef CONFIG_IWLWIFI_DEBUG
91c066f2
TW		 193#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
194
195static const char *iwl3945_get_tx_fail_reason(u32 status)
196{
197 switch (status & TX_STATUS_MSK) {
198 case TX_STATUS_SUCCESS:
199 return "SUCCESS";
200 TX_STATUS_ENTRY(SHORT_LIMIT);
201 TX_STATUS_ENTRY(LONG_LIMIT);
202 TX_STATUS_ENTRY(FIFO_UNDERRUN);
203 TX_STATUS_ENTRY(MGMNT_ABORT);
204 TX_STATUS_ENTRY(NEXT_FRAG);
205 TX_STATUS_ENTRY(LIFE_EXPIRE);
206 TX_STATUS_ENTRY(DEST_PS);
207 TX_STATUS_ENTRY(ABORTED);
208 TX_STATUS_ENTRY(BT_RETRY);
209 TX_STATUS_ENTRY(STA_INVALID);
210 TX_STATUS_ENTRY(FRAG_DROPPED);
211 TX_STATUS_ENTRY(TID_DISABLE);
212 TX_STATUS_ENTRY(FRAME_FLUSHED);
213 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
214 TX_STATUS_ENTRY(TX_LOCKED);
215 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
216 }
217
218 return "UNKNOWN";
219}
220#else
221static inline const char *iwl3945_get_tx_fail_reason(u32 status)
222{
223 return "";
224}
225#endif
226
e6a9854b
JB		 227/*
228 * get ieee prev rate from rate scale table.
229 * for A and B mode we need to overright prev
230 * value
231 */
4a8a4322 232int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 233{
234 int next_rate = iwl3945_get_prev_ieee_rate(rate);
235
236 switch (priv->band) {
237 case IEEE80211_BAND_5GHZ:
238 if (rate == IWL_RATE_12M_INDEX)
239 next_rate = IWL_RATE_9M_INDEX;
240 else if (rate == IWL_RATE_6M_INDEX)
241 next_rate = IWL_RATE_6M_INDEX;
242 break;
7262796a
AM		 243 case IEEE80211_BAND_2GHZ:
244 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 245 iwl_is_associated(priv)) {
7262796a
AM		 246 if (rate == IWL_RATE_11M_INDEX)
247 next_rate = IWL_RATE_5M_INDEX;
248 }
e6a9854b 249 break;
7262796a 250
e6a9854b
JB		 251 default:
252 break;
253 }
254
255 return next_rate;
256}
257
91c066f2
TW		 258
259/**
260 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
261 *
262 * When FW advances 'R' index, all entries between old and new 'R' index
263 * need to be reclaimed. As result, some free space forms. If there is
264 * enough free space (> low mark), wake the stack that feeds us.
265 */
4a8a4322 266static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 267 int txq_id, int index)
268{
188cf6c7 269 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 270 struct iwl_queue *q = &txq->q;
dbb6654c 271 struct iwl_tx_info *tx_info;
91c066f2
TW		 272
273 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
274
275 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
276 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
277
278 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 279 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 280 tx_info->skb[0] = NULL;
7aaa1d79 281 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 282 }
283
d20b3c65 284 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 285 (txq_id != IWL_CMD_QUEUE_NUM) &&
286 priv->mac80211_registered)
e4e72fb4 287 iwl_wake_queue(priv, txq_id);
91c066f2
TW		 288}
289
290/**
291 * iwl3945_rx_reply_tx - Handle Tx response
292 */
4a8a4322 293static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 294 struct iwl_rx_mem_buffer *rxb)
91c066f2 295{
2f301227 296 struct iwl_rx_packet *pkt = rxb_addr(rxb);
91c066f2
TW		 297 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
298 int txq_id = SEQ_TO_QUEUE(sequence);
299 int index = SEQ_TO_INDEX(sequence);
188cf6c7 300 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 301 struct ieee80211_tx_info *info;
91c066f2
TW		 302 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
303 u32 status = le32_to_cpu(tx_resp->status);
304 int rate_idx;
74221d07 305 int fail;
91c066f2 306
625a381a 307 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 308 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 309 "is out of range [0-%d] %d %d\n", txq_id,
310 index, txq->q.n_bd, txq->q.write_ptr,
311 txq->q.read_ptr);
312 return;
313 }
314
e039fa4a 315 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 316 ieee80211_tx_info_clear_status(info);
317
318 /* Fill the MRR chain with some info about on-chip retransmissions */
319 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
320 if (info->band == IEEE80211_BAND_5GHZ)
321 rate_idx -= IWL_FIRST_OFDM_RATE;
322
323 fail = tx_resp->failure_frame;
74221d07
AM		 324
325 info->status.rates[0].idx = rate_idx;
326 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 327
91c066f2 328 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 329 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
330 IEEE80211_TX_STAT_ACK : 0;
91c066f2 331
e1623446 332 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
91c066f2
TW		 333 txq_id, iwl3945_get_tx_fail_reason(status), status,
334 tx_resp->rate, tx_resp->failure_frame);
335
e1623446 336 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
91c066f2
TW		 337 iwl3945_tx_queue_reclaim(priv, txq_id, index);
338
339 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 340 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 341}
342
343
344
b481de9c
ZY		 345/*****************************************************************************
346 *
347 * Intel PRO/Wireless 3945ABG/BG Network Connection
348 *
349 * RX handler implementations
350 *
b481de9c
ZY		 351 *****************************************************************************/
352
396887a2
DH		 353void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
354 struct iwl_rx_mem_buffer *rxb)
b481de9c 355{
2f301227 356 struct iwl_rx_packet *pkt = rxb_addr(rxb);
e1623446 357 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
bb8c093b 358 (int)sizeof(struct iwl3945_notif_statistics),
396887a2 359 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
b481de9c 360
f2c7e521 361 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
b481de9c
ZY		 362}
363
17744ff6
TW		 364/******************************************************************************
365 *
366 * Misc. internal state and helper functions
367 *
368 ******************************************************************************/
d08853a3 369#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 370
371/**
372 * iwl3945_report_frame - dump frame to syslog during debug sessions
373 *
374 * You may hack this function to show different aspects of received frames,
375 * including selective frame dumps.
376 * group100 parameter selects whether to show 1 out of 100 good frames.
377 */
d08853a3 378static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 379 struct iwl_rx_packet *pkt,
17744ff6
TW		 380 struct ieee80211_hdr *header, int group100)
381{
382 u32 to_us;
383 u32 print_summary = 0;
384 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
385 u32 hundred = 0;
386 u32 dataframe = 0;
fd7c8a40 387 __le16 fc;
17744ff6
TW		 388 u16 seq_ctl;
389 u16 channel;
390 u16 phy_flags;
391 u16 length;
392 u16 status;
393 u16 bcn_tmr;
394 u32 tsf_low;
395 u64 tsf;
396 u8 rssi;
397 u8 agc;
398 u16 sig_avg;
399 u16 noise_diff;
400 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
401 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
402 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
403 u8 *data = IWL_RX_DATA(pkt);
404
405 /* MAC header */
fd7c8a40 406 fc = header->frame_control;
17744ff6
TW		 407 seq_ctl = le16_to_cpu(header->seq_ctrl);
408
409 /* metadata */
410 channel = le16_to_cpu(rx_hdr->channel);
411 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
412 length = le16_to_cpu(rx_hdr->len);
413
414 /* end-of-frame status and timestamp */
415 status = le32_to_cpu(rx_end->status);
416 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
417 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
418 tsf = le64_to_cpu(rx_end->timestamp);
419
420 /* signal statistics */
421 rssi = rx_stats->rssi;
422 agc = rx_stats->agc;
423 sig_avg = le16_to_cpu(rx_stats->sig_avg);
424 noise_diff = le16_to_cpu(rx_stats->noise_diff);
425
426 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
427
428 /* if data frame is to us and all is good,
429 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 430 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
431 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 432 dataframe = 1;
433 if (!group100)
434 print_summary = 1; /* print each frame */
435 else if (priv->framecnt_to_us < 100) {
436 priv->framecnt_to_us++;
437 print_summary = 0;
438 } else {
439 priv->framecnt_to_us = 0;
440 print_summary = 1;
441 hundred = 1;
442 }
443 } else {
444 /* print summary for all other frames */
445 print_summary = 1;
446 }
447
448 if (print_summary) {
449 char *title;
0ff1cca0 450 int rate;
17744ff6
TW		 451
452 if (hundred)
453 title = "100Frames";
fd7c8a40 454 else if (ieee80211_has_retry(fc))
17744ff6 455 title = "Retry";
fd7c8a40 456 else if (ieee80211_is_assoc_resp(fc))
17744ff6 457 title = "AscRsp";
fd7c8a40 458 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 459 title = "RasRsp";
fd7c8a40 460 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 461 title = "PrbRsp";
462 print_dump = 1; /* dump frame contents */
463 } else if (ieee80211_is_beacon(fc)) {
464 title = "Beacon";
465 print_dump = 1; /* dump frame contents */
466 } else if (ieee80211_is_atim(fc))
467 title = "ATIM";
468 else if (ieee80211_is_auth(fc))
469 title = "Auth";
470 else if (ieee80211_is_deauth(fc))
471 title = "DeAuth";
472 else if (ieee80211_is_disassoc(fc))
473 title = "DisAssoc";
474 else
475 title = "Frame";
476
477 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
478 if (rate == -1)
479 rate = 0;
480 else
481 rate = iwl3945_rates[rate].ieee / 2;
482
483 /* print frame summary.
484 * MAC addresses show just the last byte (for brevity),
485 * but you can hack it to show more, if you'd like to. */
486 if (dataframe)
e1623446 487 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 488 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 489 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 490 length, rssi, channel, rate);
491 else {
492 /* src/dst addresses assume managed mode */
e1623446 493 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
17744ff6
TW		 494 "src=0x%02x, rssi=%u, tim=%lu usec, "
495 "phy=0x%02x, chnl=%d\n",
fd7c8a40 496 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 497 header->addr3[5], rssi,
498 tsf_low - priv->scan_start_tsf,
499 phy_flags, channel);
500 }
501 }
502 if (print_dump)
3d816c77 503 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6 504}
d08853a3
SO		 505
506static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
507 struct iwl_rx_packet *pkt,
508 struct ieee80211_hdr *header, int group100)
509{
3d816c77 510 if (iwl_get_debug_level(priv) & IWL_DL_RX)
d08853a3
SO		 511 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
512}
513
17744ff6 514#else
4a8a4322 515static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 516 struct iwl_rx_packet *pkt,
17744ff6
TW		 517 struct ieee80211_hdr *header, int group100)
518{
519}
520#endif
521
4bd9b4f3 522/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 523static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 524 struct ieee80211_hdr *header)
525{
526 /* Filter incoming packets to determine if they are targeted toward
527 * this network, discarding packets coming from ourselves */
528 switch (priv->iw_mode) {
05c914fe 529 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 530 /* packets to our IBSS update information */
531 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 532 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 533 /* packets to our IBSS update information */
534 return !compare_ether_addr(header->addr2, priv->bssid);
535 default:
536 return 1;
537 }
538}
17744ff6 539
4a8a4322 540static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 541 struct iwl_rx_mem_buffer *rxb,
12342c47 542 struct ieee80211_rx_status *stats)
b481de9c 543{
2f301227 544 struct iwl_rx_packet *pkt = rxb_addr(rxb);
4bd9b4f3 545 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
bb8c093b
CH		 546 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
547 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
2f301227
ZY		 548 u16 len = le16_to_cpu(rx_hdr->len);
549 struct sk_buff *skb;
550 int ret;
b481de9c
ZY		 551
552 /* We received data from the HW, so stop the watchdog */
2f301227
ZY		 553 if (unlikely(len + IWL39_RX_FRAME_SIZE >
554 PAGE_SIZE << priv->hw_params.rx_page_order)) {
e1623446 555 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
b481de9c
ZY		 556 return;
557 }
558
559 /* We only process data packets if the interface is open */
560 if (unlikely(!priv->is_open)) {
e1623446
TW		 561 IWL_DEBUG_DROP_LIMIT(priv,
562 "Dropping packet while interface is not open.\n");
b481de9c
ZY		 563 return;
564 }
b481de9c 565
2f301227
ZY		 566 skb = alloc_skb(IWL_LINK_HDR_MAX, GFP_ATOMIC);
567 if (!skb) {
568 IWL_ERR(priv, "alloc_skb failed\n");
569 return;
570 }
b481de9c 571
9c74d9fb 572 if (!iwl3945_mod_params.sw_crypto)
8ccde88a 573 iwl_set_decrypted_flag(priv,
2f301227 574 (struct ieee80211_hdr *)rxb_addr(rxb),
b481de9c
ZY		 575 le32_to_cpu(rx_end->status), stats);
576
2f301227
ZY		 577 skb_add_rx_frag(skb, 0, rxb->page,
578 (void *)rx_hdr->payload - (void *)pkt, len);
579
580 /* mac80211 currently doesn't support paged SKB. Convert it to
581 * linear SKB for management frame and data frame requires
582 * software decryption or software defragementation. */
583 if (ieee80211_is_mgmt(hdr->frame_control) ||
584 ieee80211_has_protected(hdr->frame_control) ||
585 ieee80211_has_morefrags(hdr->frame_control) ||
586 le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)
587 ret = skb_linearize(skb);
588 else
589 ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ?
590 0 : -ENOMEM;
591
592 if (ret) {
593 kfree_skb(skb);
594 goto out;
595 }
596
22fdf3c9
WYG		 597 iwl_update_stats(priv, false, hdr->frame_control, len);
598
2f301227
ZY		 599 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
600 ieee80211_rx(priv->hw, skb);
601
602 out:
603 priv->alloc_rxb_page--;
604 rxb->page = NULL;
b481de9c
ZY		 605}
606
7878a5a4
MA		 607#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
608
4a8a4322 609static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 610 struct iwl_rx_mem_buffer *rxb)
b481de9c 611{
17744ff6
TW		 612 struct ieee80211_hdr *header;
613 struct ieee80211_rx_status rx_status;
2f301227 614 struct iwl_rx_packet *pkt = rxb_addr(rxb);
bb8c093b
CH		 615 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
616 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
617 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 618 int snr;
b481de9c
ZY		 619 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
620 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 621 u8 network_packet;
17744ff6 622
17744ff6
TW		 623 rx_status.flag = 0;
624 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 625 rx_status.freq =
c0186078 626 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 627 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
628 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
629
630 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 631 if (rx_status.band == IEEE80211_BAND_5GHZ)
632 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 633
9024adf5 634 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
6f0a2c4d
BR		 635 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
636
637 /* set the preamble flag if appropriate */
638 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
639 rx_status.flag |= RX_FLAG_SHORTPRE;
640
b481de9c 641 if ((unlikely(rx_stats->phy_count > 20))) {
e1623446
TW		 642 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
643 rx_stats->phy_count);
b481de9c
ZY		 644 return;
645 }
646
647 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
648 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e1623446 649 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
b481de9c
ZY		 650 return;
651 }
652
56decd3c 653
b481de9c
ZY		 654
655 /* Convert 3945's rssi indicator to dBm */
250bdd21 656 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 657
658 /* Set default noise value to -127 */
659 if (priv->last_rx_noise == 0)
660 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
661
662 /* 3945 provides noise info for OFDM frames only.
663 * sig_avg and noise_diff are measured by the 3945's digital signal
664 * processor (DSP), and indicate linear levels of signal level and
665 * distortion/noise within the packet preamble after
666 * automatic gain control (AGC). sig_avg should stay fairly
667 * constant if the radio's AGC is working well.
668 * Since these values are linear (not dB or dBm), linear
669 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
670 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
671 * to obtain noise level in dBm.
17744ff6 672 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 673 if (rx_stats_noise_diff) {
674 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 675 rx_status.noise = rx_status.signal -
17744ff6 676 iwl3945_calc_db_from_ratio(snr);
566bfe5a 677 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 678 rx_status.noise);
b481de9c
ZY		 679
680 /* If noise info not available, calculate signal quality indicator (%)
681 * using just the dBm signal level. */
682 } else {
17744ff6 683 rx_status.noise = priv->last_rx_noise;
566bfe5a 684 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 685 }
686
687
e1623446 688 IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 689 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 690 rx_stats_sig_avg, rx_stats_noise_diff);
691
b481de9c
ZY		 692 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
693
bb8c093b 694 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 695
e1623446 696 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
17744ff6
TW		 697 network_packet ? '*' : ' ',
698 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 699 rx_status.signal, rx_status.signal,
700 rx_status.noise, rx_status.rate_idx);
b481de9c 701
d08853a3
SO		 702 /* Set "1" to report good data frames in groups of 100 */
703 iwl3945_dbg_report_frame(priv, pkt, header, 1);
20594eb0 704 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
b481de9c
ZY		 705
706 if (network_packet) {
707 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
708 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 709 priv->last_rx_rssi = rx_status.signal;
17744ff6 710 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 711 }
712
12e5e22d 713 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 714}
715
7aaa1d79
SO		 716int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
717 struct iwl_tx_queue *txq,
718 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 719{
720 int count;
7aaa1d79 721 struct iwl_queue *q;
59606ffa 722 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 723
724 q = &txq->q;
59606ffa
SO		 725 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
726 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 727
728 if (reset)
729 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 730
731 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 732
733 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 734 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 735 NUM_TFD_CHUNKS);
736 return -EINVAL;
737 }
738
dbb6654c
WT		 739 tfd->tbs[count].addr = cpu_to_le32(addr);
740 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 741
742 count++;
743
744 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
745 TFD_CTL_PAD_SET(pad));
746
747 return 0;
748}
749
750/**
bb8c093b 751 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 752 *
753 * Does NOT advance any indexes
754 */
7aaa1d79 755void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 756{
59606ffa 757 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
fd9377ee
RC		 758 int index = txq->q.read_ptr;
759 struct iwl3945_tfd *tfd = &tfd_tmp[index];
b481de9c
ZY		 760 struct pci_dev *dev = priv->pci_dev;
761 int i;
762 int counter;
763
b481de9c 764 /* sanity check */
dbb6654c 765 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 766 if (counter > NUM_TFD_CHUNKS) {
15b1687c 767 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 768 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 769 return;
b481de9c
ZY		 770 }
771
fd9377ee
RC		 772 /* Unmap tx_cmd */
773 if (counter)
774 pci_unmap_single(dev,
c2acea8e
JB		 775 pci_unmap_addr(&txq->meta[index], mapping),
776 pci_unmap_len(&txq->meta[index], len),
fd9377ee
RC		 777 PCI_DMA_TODEVICE);
778
b481de9c
ZY		 779 /* unmap chunks if any */
780
781 for (i = 1; i < counter; i++) {
dbb6654c
WT		 782 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
783 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 784 if (txq->txb[txq->q.read_ptr].skb[0]) {
785 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
786 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 787 /* Can be called from interrupt context */
788 dev_kfree_skb_any(skb);
fc4b6853 789 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 790 }
791 }
792 }
7aaa1d79 793 return ;
b481de9c
ZY		 794}
795
b481de9c 796/**
bb8c093b 797 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 798 *
799*/
c2acea8e
JB		 800void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
801 struct iwl_device_cmd *cmd,
802 struct ieee80211_tx_info *info,
803 struct ieee80211_hdr *hdr,
804 int sta_id, int tx_id)
b481de9c 805{
e039fa4a 806 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 807 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 808 u16 rate_mask;
809 int rate;
810 u8 rts_retry_limit;
811 u8 data_retry_limit;
812 __le32 tx_flags;
fd7c8a40 813 __le16 fc = hdr->frame_control;
9744c91f 814 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 815
bb8c093b 816 rate = iwl3945_rates[rate_index].plcp;
9744c91f 817 tx_flags = tx_cmd->tx_flags;
b481de9c
ZY		 818
819 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 820 * in this running context */
b481de9c
ZY		 821 rate_mask = IWL_RATES_MASK;
822
768db982
AK		 823
824 /* Set retry limit on DATA packets and Probe Responses*/
825 if (ieee80211_is_probe_resp(fc))
826 data_retry_limit = 3;
827 else
828 data_retry_limit = IWL_DEFAULT_TX_RETRY;
829 tx_cmd->data_retry_limit = data_retry_limit;
830
b481de9c
ZY		 831 if (tx_id >= IWL_CMD_QUEUE_NUM)
832 rts_retry_limit = 3;
833 else
834 rts_retry_limit = 7;
835
768db982
AK		 836 if (data_retry_limit < rts_retry_limit)
837 rts_retry_limit = data_retry_limit;
838 tx_cmd->rts_retry_limit = rts_retry_limit;
b481de9c 839
fd7c8a40
HH		 840 if (ieee80211_is_mgmt(fc)) {
841 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
842 case cpu_to_le16(IEEE80211_STYPE_AUTH):
843 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
844 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
845 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 846 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
847 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
848 tx_flags |= TX_CMD_FLG_CTS_MSK;
849 }
850 break;
851 default:
852 break;
853 }
854 }
855
9744c91f
AK		 856 tx_cmd->rate = rate;
857 tx_cmd->tx_flags = tx_flags;
b481de9c
ZY		 858
859 /* OFDM */
9744c91f 860 tx_cmd->supp_rates[0] =
14577f23 861 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 862
863 /* CCK */
9744c91f 864 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
b481de9c 865
e1623446 866 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
b481de9c 867 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
9744c91f
AK		 868 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
869 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
b481de9c
ZY		 870}
871
4a8a4322 872u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 873{
874 unsigned long flags_spin;
c587de0b 875 struct iwl_station_entry *station;
b481de9c
ZY		 876
877 if (sta_id == IWL_INVALID_STATION)
878 return IWL_INVALID_STATION;
879
880 spin_lock_irqsave(&priv->sta_lock, flags_spin);
c587de0b 881 station = &priv->stations[sta_id];
b481de9c
ZY		 882
883 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
884 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 885 station->sta.mode = STA_CONTROL_MODIFY_MSK;
886
887 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
888
c587de0b 889 iwl_send_add_sta(priv, &station->sta, flags);
e1623446 890 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
b481de9c
ZY		 891 sta_id, tx_rate);
892 return sta_id;
893}
894
854682ed 895static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 896{
854682ed 897 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 898 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
5d49f498 899 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 900 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
901 ~APMG_PS_CTRL_MSK_PWR_SRC);
b481de9c 902
5d49f498 903 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 904 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
905 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
3fdb68de 906 }
b481de9c 907 } else {
5d49f498 908 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 909 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
910 ~APMG_PS_CTRL_MSK_PWR_SRC);
911
5d49f498 912 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 913 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
914 }
b481de9c 915
a8b50a0a 916 return 0;
b481de9c
ZY		 917}
918
4a8a4322 919static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c 920{
5d49f498 921 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 922 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 923 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
924 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 925 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
926 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
927 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
928 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
929 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
930 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
931 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
932 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 933
934 /* fake read to flush all prev I/O */
5d49f498 935 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 936
b481de9c
ZY		 937 return 0;
938}
939
4a8a4322 940static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c 941{
b481de9c
ZY		 942
943 /* bypass mode */
5d49f498 944 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 945
946 /* RA 0 is active */
5d49f498 947 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 948
949 /* all 6 fifo are active */
5d49f498 950 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 951
5d49f498
AK		 952 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
953 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
954 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
955 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 956
5d49f498 957 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
3832ec9d 958 priv->shared_phys);
b481de9c 959
5d49f498 960 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 961 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
962 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
963 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
964 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
965 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
966 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
967 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 968
b481de9c
ZY		 969
970 return 0;
971}
972
973/**
974 * iwl3945_txq_ctx_reset - Reset TX queue context
975 *
976 * Destroys all DMA structures and initialize them again
977 */
4a8a4322 978static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 979{
980 int rc;
981 int txq_id, slots_num;
982
bb8c093b 983 iwl3945_hw_txq_ctx_free(priv);
b481de9c 984
88804e2b
WYG		 985 /* allocate tx queue structure */
986 rc = iwl_alloc_txq_mem(priv);
987 if (rc)
988 return rc;
989
b481de9c
ZY		 990 /* Tx CMD queue */
991 rc = iwl3945_tx_reset(priv);
992 if (rc)
993 goto error;
994
995 /* Tx queue(s) */
5905a1aa 996 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 997 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
998 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 999 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1000 txq_id);
b481de9c 1001 if (rc) {
15b1687c 1002 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 1003 goto error;
1004 }
1005 }
1006
1007 return rc;
1008
1009 error:
bb8c093b 1010 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1011 return rc;
1012}
1013
fadb3582 1014
f33269b8 1015/*
fadb3582
BC		 1016 * Start up 3945's basic functionality after it has been reset
1017 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
f33269b8
BC		 1018 * NOTE: This does not load uCode nor start the embedded processor
1019 */
01ec616d 1020static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 1021{
fadb3582 1022 int ret = iwl_apm_init(priv);
01ec616d 1023
f33269b8
BC		 1024 /* Clear APMG (NIC's internal power management) interrupts */
1025 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1026 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1027
1028 /* Reset radio chip */
1029 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1030 udelay(5);
1031 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1032
01ec616d
KA		 1033 return ret;
1034}
b481de9c 1035
01ec616d
KA		 1036static void iwl3945_nic_config(struct iwl_priv *priv)
1037{
e6148917 1038 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 1039 unsigned long flags;
1040 u8 rev_id = 0;
b481de9c 1041
b481de9c
ZY		 1042 spin_lock_irqsave(&priv->lock, flags);
1043
43121432
AK		 1044 /* Determine HW type */
1045 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1046
1047 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1048
b481de9c 1049 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
e1623446 1050 IWL_DEBUG_INFO(priv, "RTP type \n");
b481de9c 1051 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
e1623446 1052 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
5d49f498 1053 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1054 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1055 } else {
e1623446 1056 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
5d49f498 1057 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1058 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1059 }
1060
e6148917 1061 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
e1623446 1062 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
5d49f498 1063 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1064 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c 1065 } else
e1623446 1066 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
b481de9c 1067
e6148917 1068 if ((eeprom->board_revision & 0xF0) == 0xD0) {
e1623446 1069 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1070 eeprom->board_revision);
5d49f498 1071 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1072 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c 1073 } else {
e1623446 1074 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1075 eeprom->board_revision);
5d49f498 1076 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1077 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1078 }
1079
e6148917 1080 if (eeprom->almgor_m_version <= 1) {
5d49f498 1081 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1082 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
e1623446 1083 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
e6148917 1084 eeprom->almgor_m_version);
b481de9c 1085 } else {
e1623446 1086 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
e6148917 1087 eeprom->almgor_m_version);
5d49f498 1088 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1089 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1090 }
1091 spin_unlock_irqrestore(&priv->lock, flags);
1092
e6148917 1093 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
e1623446 1094 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
b481de9c 1095
e6148917 1096 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
e1623446 1097 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1098}
1099
1100int iwl3945_hw_nic_init(struct iwl_priv *priv)
1101{
01ec616d
KA		 1102 int rc;
1103 unsigned long flags;
1104 struct iwl_rx_queue *rxq = &priv->rxq;
1105
1106 spin_lock_irqsave(&priv->lock, flags);
1107 priv->cfg->ops->lib->apm_ops.init(priv);
1108 spin_unlock_irqrestore(&priv->lock, flags);
1109
854682ed 1110 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1e680233 1111 if (rc)
854682ed
KA		 1112 return rc;
1113
01ec616d 1114 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1115
1116 /* Allocate the RX queue, or reset if it is already allocated */
1117 if (!rxq->bd) {
51af3d3f 1118 rc = iwl_rx_queue_alloc(priv);
b481de9c 1119 if (rc) {
15b1687c 1120 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1121 return -ENOMEM;
1122 }
1123 } else
df833b1d 1124 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1125
bb8c093b 1126 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1127
1128 iwl3945_rx_init(priv, rxq);
1129
b481de9c
ZY		 1130
1131 /* Look at using this instead:
1132 rxq->need_update = 1;
141c43a3 1133 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1134 */
1135
5d49f498 1136 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
b481de9c
ZY		 1137
1138 rc = iwl3945_txq_ctx_reset(priv);
1139 if (rc)
1140 return rc;
1141
1142 set_bit(STATUS_INIT, &priv->status);
1143
1144 return 0;
1145}
1146
1147/**
bb8c093b 1148 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1149 *
1150 * Destroy all TX DMA queues and structures
1151 */
4a8a4322 1152void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1153{
1154 int txq_id;
1155
1156 /* Tx queues */
88804e2b
WYG		 1157 if (priv->txq)
1158 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1159 txq_id++)
1160 if (txq_id == IWL_CMD_QUEUE_NUM)
1161 iwl_cmd_queue_free(priv);
1162 else
1163 iwl_tx_queue_free(priv, txq_id);
3e5d238f 1164
88804e2b
WYG		 1165 /* free tx queue structure */
1166 iwl_free_txq_mem(priv);
b481de9c
ZY		 1167}
1168
4a8a4322 1169void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1170{
bddadf86 1171 int txq_id;
b481de9c
ZY		 1172
1173 /* stop SCD */
5d49f498 1174 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1f80989e 1175 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
b481de9c
ZY		 1176
1177 /* reset TFD queues */
5905a1aa 1178 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
5d49f498
AK		 1179 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1180 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1181 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1182 1000);
1183 }
1184
bb8c093b 1185 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1186}
1187
b481de9c 1188/**
bb8c093b 1189 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1190 * return index delta into power gain settings table
1191*/
bb8c093b 1192static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1193{
1194 return (new_reading - old_reading) * (-11) / 100;
1195}
1196
1197/**
bb8c093b 1198 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1199 */
bb8c093b 1200static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1201{
3ac7f146 1202 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1203}
1204
4a8a4322 1205int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1206{
5d49f498 1207 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1208}
1209
1210/**
bb8c093b 1211 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1212 * get the current temperature by reading from NIC
1213*/
4a8a4322 1214static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1215{
e6148917 1216 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1217 int temperature;
1218
bb8c093b 1219 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1220
1221 /* driver's okay range is -260 to +25.
1222 * human readable okay range is 0 to +285 */
e1623446 1223 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
b481de9c
ZY		 1224
1225 /* handle insane temp reading */
bb8c093b 1226 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1227 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1228
1229 /* if really really hot(?),
1230 * substitute the 3rd band/group's temp measured at factory */
1231 if (priv->last_temperature > 100)
e6148917 1232 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1233 else /* else use most recent "sane" value from driver */
1234 temperature = priv->last_temperature;
1235 }
1236
1237 return temperature; /* raw, not "human readable" */
1238}
1239
1240/* Adjust Txpower only if temperature variance is greater than threshold.
1241 *
1242 * Both are lower than older versions' 9 degrees */
1243#define IWL_TEMPERATURE_LIMIT_TIMER 6
1244
1245/**
1246 * is_temp_calib_needed - determines if new calibration is needed
1247 *
1248 * records new temperature in tx_mgr->temperature.
1249 * replaces tx_mgr->last_temperature *only* if calib needed
1250 * (assumes caller will actually do the calibration!). */
4a8a4322 1251static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1252{
1253 int temp_diff;
1254
bb8c093b 1255 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1256 temp_diff = priv->temperature - priv->last_temperature;
1257
1258 /* get absolute value */
1259 if (temp_diff < 0) {
e1623446 1260 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
b481de9c
ZY		 1261 temp_diff = -temp_diff;
1262 } else if (temp_diff == 0)
e1623446 1263 IWL_DEBUG_POWER(priv, "Same temp,\n");
b481de9c 1264 else
e1623446 1265 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
b481de9c
ZY		 1266
1267 /* if we don't need calibration, *don't* update last_temperature */
1268 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
e1623446 1269 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
b481de9c
ZY		 1270 return 0;
1271 }
1272
e1623446 1273 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
b481de9c
ZY		 1274
1275 /* assume that caller will actually do calib ...
1276 * update the "last temperature" value */
1277 priv->last_temperature = priv->temperature;
1278 return 1;
1279}
1280
1281#define IWL_MAX_GAIN_ENTRIES 78
1282#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1283#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1284
1285/* radio and DSP power table, each step is 1/2 dB.
1286 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1287static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1288 {
1289 {251, 127}, /* 2.4 GHz, highest power */
1290 {251, 127},
1291 {251, 127},
1292 {251, 127},
1293 {251, 125},
1294 {251, 110},
1295 {251, 105},
1296 {251, 98},
1297 {187, 125},
1298 {187, 115},
1299 {187, 108},
1300 {187, 99},
1301 {243, 119},
1302 {243, 111},
1303 {243, 105},
1304 {243, 97},
1305 {243, 92},
1306 {211, 106},
1307 {211, 100},
1308 {179, 120},
1309 {179, 113},
1310 {179, 107},
1311 {147, 125},
1312 {147, 119},
1313 {147, 112},
1314 {147, 106},
1315 {147, 101},
1316 {147, 97},
1317 {147, 91},
1318 {115, 107},
1319 {235, 121},
1320 {235, 115},
1321 {235, 109},
1322 {203, 127},
1323 {203, 121},
1324 {203, 115},
1325 {203, 108},
1326 {203, 102},
1327 {203, 96},
1328 {203, 92},
1329 {171, 110},
1330 {171, 104},
1331 {171, 98},
1332 {139, 116},
1333 {227, 125},
1334 {227, 119},
1335 {227, 113},
1336 {227, 107},
1337 {227, 101},
1338 {227, 96},
1339 {195, 113},
1340 {195, 106},
1341 {195, 102},
1342 {195, 95},
1343 {163, 113},
1344 {163, 106},
1345 {163, 102},
1346 {163, 95},
1347 {131, 113},
1348 {131, 106},
1349 {131, 102},
1350 {131, 95},
1351 {99, 113},
1352 {99, 106},
1353 {99, 102},
1354 {99, 95},
1355 {67, 113},
1356 {67, 106},
1357 {67, 102},
1358 {67, 95},
1359 {35, 113},
1360 {35, 106},
1361 {35, 102},
1362 {35, 95},
1363 {3, 113},
1364 {3, 106},
1365 {3, 102},
1366 {3, 95} }, /* 2.4 GHz, lowest power */
1367 {
1368 {251, 127}, /* 5.x GHz, highest power */
1369 {251, 120},
1370 {251, 114},
1371 {219, 119},
1372 {219, 101},
1373 {187, 113},
1374 {187, 102},
1375 {155, 114},
1376 {155, 103},
1377 {123, 117},
1378 {123, 107},
1379 {123, 99},
1380 {123, 92},
1381 {91, 108},
1382 {59, 125},
1383 {59, 118},
1384 {59, 109},
1385 {59, 102},
1386 {59, 96},
1387 {59, 90},
1388 {27, 104},
1389 {27, 98},
1390 {27, 92},
1391 {115, 118},
1392 {115, 111},
1393 {115, 104},
1394 {83, 126},
1395 {83, 121},
1396 {83, 113},
1397 {83, 105},
1398 {83, 99},
1399 {51, 118},
1400 {51, 111},
1401 {51, 104},
1402 {51, 98},
1403 {19, 116},
1404 {19, 109},
1405 {19, 102},
1406 {19, 98},
1407 {19, 93},
1408 {171, 113},
1409 {171, 107},
1410 {171, 99},
1411 {139, 120},
1412 {139, 113},
1413 {139, 107},
1414 {139, 99},
1415 {107, 120},
1416 {107, 113},
1417 {107, 107},
1418 {107, 99},
1419 {75, 120},
1420 {75, 113},
1421 {75, 107},
1422 {75, 99},
1423 {43, 120},
1424 {43, 113},
1425 {43, 107},
1426 {43, 99},
1427 {11, 120},
1428 {11, 113},
1429 {11, 107},
1430 {11, 99},
1431 {131, 107},
1432 {131, 99},
1433 {99, 120},
1434 {99, 113},
1435 {99, 107},
1436 {99, 99},
1437 {67, 120},
1438 {67, 113},
1439 {67, 107},
1440 {67, 99},
1441 {35, 120},
1442 {35, 113},
1443 {35, 107},
1444 {35, 99},
1445 {3, 120} } /* 5.x GHz, lowest power */
1446};
1447
bb8c093b 1448static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1449{
1450 if (index < 0)
1451 return 0;
1452 if (index >= IWL_MAX_GAIN_ENTRIES)
1453 return IWL_MAX_GAIN_ENTRIES - 1;
1454 return (u8) index;
1455}
1456
1457/* Kick off thermal recalibration check every 60 seconds */
1458#define REG_RECALIB_PERIOD (60)
1459
1460/**
bb8c093b 1461 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1462 *
1463 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1464 * or 6 Mbit (OFDM) rates.
1465 */
4a8a4322 1466static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1467 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1468 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1469 int band_index)
1470{
bb8c093b 1471 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1472 s8 power;
1473 u8 power_index;
1474
1475 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1476
1477 /* use this channel group's 6Mbit clipping/saturation pwr,
1478 * but cap at regulatory scan power restriction (set during init
1479 * based on eeprom channel data) for this channel. */
14577f23 1480 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1481
1482 /* further limit to user's max power preference.
1483 * FIXME: Other spectrum management power limitations do not
1484 * seem to apply?? */
62ea9c5b 1485 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1486 scan_power_info->requested_power = power;
1487
1488 /* find difference between new scan *power* and current "normal"
1489 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1490 * current "normal" temperature-compensated Tx power *index* for
1491 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1492 * *index*. */
1493 power_index = ch_info->power_info[rate_index].power_table_index
1494 - (power - ch_info->power_info
14577f23 1495 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1496
1497 /* store reference index that we use when adjusting *all* scan
1498 * powers. So we can accommodate user (all channel) or spectrum
1499 * management (single channel) power changes "between" temperature
1500 * feedback compensation procedures.
1501 * don't force fit this reference index into gain table; it may be a
1502 * negative number. This will help avoid errors when we're at
1503 * the lower bounds (highest gains, for warmest temperatures)
1504 * of the table. */
1505
1506 /* don't exceed table bounds for "real" setting */
bb8c093b 1507 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1508
1509 scan_power_info->power_table_index = power_index;
1510 scan_power_info->tpc.tx_gain =
1511 power_gain_table[band_index][power_index].tx_gain;
1512 scan_power_info->tpc.dsp_atten =
1513 power_gain_table[band_index][power_index].dsp_atten;
1514}
1515
1516/**
75bcfae9 1517 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1518 *
1519 * Configures power settings for all rates for the current channel,
1520 * using values from channel info struct, and send to NIC
1521 */
dfb39e82 1522static int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1523{
14577f23 1524 int rate_idx, i;
d20b3c65 1525 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1526 struct iwl3945_txpowertable_cmd txpower = {
8ccde88a 1527 .channel = priv->active_rxon.channel,
b481de9c
ZY		 1528 };
1529
8318d78a 1530 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1531 ch_info = iwl_get_channel_info(priv,
8318d78a 1532 priv->band,
8ccde88a 1533 le16_to_cpu(priv->active_rxon.channel));
b481de9c 1534 if (!ch_info) {
15b1687c
WT		 1535 IWL_ERR(priv,
1536 "Failed to get channel info for channel %d [%d]\n",
8ccde88a 1537 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1538 return -EINVAL;
1539 }
1540
1541 if (!is_channel_valid(ch_info)) {
e1623446 1542 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
b481de9c
ZY		 1543 "non-Tx channel.\n");
1544 return 0;
1545 }
1546
1547 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1548 /* Fill OFDM rate */
1549 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1550 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1551
1552 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1553 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c 1554
e1623446 1555 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
b481de9c
ZY		 1556 le16_to_cpu(txpower.channel),
1557 txpower.band,
14577f23
MA		 1558 txpower.power[i].tpc.tx_gain,
1559 txpower.power[i].tpc.dsp_atten,
1560 txpower.power[i].rate);
1561 }
1562 /* Fill CCK rates */
1563 for (rate_idx = IWL_FIRST_CCK_RATE;
1564 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1565 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1566 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23 1567
e1623446 1568 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
14577f23
MA		 1569 le16_to_cpu(txpower.channel),
1570 txpower.band,
1571 txpower.power[i].tpc.tx_gain,
1572 txpower.power[i].tpc.dsp_atten,
1573 txpower.power[i].rate);
b481de9c
ZY		 1574 }
1575
518099a8
SO		 1576 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1577 sizeof(struct iwl3945_txpowertable_cmd),
1578 &txpower);
b481de9c
ZY		 1579
1580}
1581
1582/**
bb8c093b 1583 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1584 * @ch_info: Channel to update. Uses power_info.requested_power.
1585 *
1586 * Replace requested_power and base_power_index ch_info fields for
1587 * one channel.
1588 *
1589 * Called if user or spectrum management changes power preferences.
1590 * Takes into account h/w and modulation limitations (clip power).
1591 *
1592 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1593 *
1594 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1595 * properly fill out the scan powers, and actual h/w gain settings,
1596 * and send changes to NIC
1597 */
4a8a4322 1598static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1599 struct iwl_channel_info *ch_info)
b481de9c 1600{
bb8c093b 1601 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1602 int power_changed = 0;
1603 int i;
1604 const s8 *clip_pwrs;
1605 int power;
1606
1607 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1608 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1609
1610 /* Get this channel's rate-to-current-power settings table */
1611 power_info = ch_info->power_info;
1612
1613 /* update OFDM Txpower settings */
14577f23 1614 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1615 i++, ++power_info) {
1616 int delta_idx;
1617
1618 /* limit new power to be no more than h/w capability */
1619 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1620 if (power == power_info->requested_power)
1621 continue;
1622
1623 /* find difference between old and new requested powers,
1624 * update base (non-temp-compensated) power index */
1625 delta_idx = (power - power_info->requested_power) * 2;
1626 power_info->base_power_index -= delta_idx;
1627
1628 /* save new requested power value */
1629 power_info->requested_power = power;
1630
1631 power_changed = 1;
1632 }
1633
1634 /* update CCK Txpower settings, based on OFDM 12M setting ...
1635 * ... all CCK power settings for a given channel are the *same*. */
1636 if (power_changed) {
1637 power =
14577f23 1638 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1639 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1640
bb8c093b 1641 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1642 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1643 power_info->requested_power = power;
1644 power_info->base_power_index =
14577f23 1645 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1646 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1647 ++power_info;
1648 }
1649 }
1650
1651 return 0;
1652}
1653
1654/**
bb8c093b 1655 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1656 *
1657 * NOTE: Returned power limit may be less (but not more) than requested,
1658 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1659 * (no consideration for h/w clipping limitations).
1660 */
d20b3c65 1661static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1662{
1663 s8 max_power;
1664
1665#if 0
1666 /* if we're using TGd limits, use lower of TGd or EEPROM */
1667 if (ch_info->tgd_data.max_power != 0)
1668 max_power = min(ch_info->tgd_data.max_power,
1669 ch_info->eeprom.max_power_avg);
1670
1671 /* else just use EEPROM limits */
1672 else
1673#endif
1674 max_power = ch_info->eeprom.max_power_avg;
1675
1676 return min(max_power, ch_info->max_power_avg);
1677}
1678
1679/**
bb8c093b 1680 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1681 *
1682 * Compensate txpower settings of *all* channels for temperature.
1683 * This only accounts for the difference between current temperature
1684 * and the factory calibration temperatures, and bases the new settings
1685 * on the channel's base_power_index.
1686 *
1687 * If RxOn is "associated", this sends the new Txpower to NIC!
1688 */
4a8a4322 1689static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1690{
d20b3c65 1691 struct iwl_channel_info *ch_info = NULL;
e6148917 1692 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1693 int delta_index;
1694 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1695 u8 a_band;
1696 u8 rate_index;
1697 u8 scan_tbl_index;
1698 u8 i;
1699 int ref_temp;
1700 int temperature = priv->temperature;
1701
1702 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1703 for (i = 0; i < priv->channel_count; i++) {
1704 ch_info = &priv->channel_info[i];
1705 a_band = is_channel_a_band(ch_info);
1706
1707 /* Get this chnlgrp's factory calibration temperature */
e6148917 1708 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1709 temperature;
1710
a96a27f9 1711 /* get power index adjustment based on current and factory
b481de9c 1712 * temps */
bb8c093b 1713 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1714 ref_temp);
1715
1716 /* set tx power value for all rates, OFDM and CCK */
1717 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1718 rate_index++) {
1719 int power_idx =
1720 ch_info->power_info[rate_index].base_power_index;
1721
1722 /* temperature compensate */
1723 power_idx += delta_index;
1724
1725 /* stay within table range */
bb8c093b 1726 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1727 ch_info->power_info[rate_index].
1728 power_table_index = (u8) power_idx;
1729 ch_info->power_info[rate_index].tpc =
1730 power_gain_table[a_band][power_idx];
1731 }
1732
1733 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1734 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1735
1736 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1737 for (scan_tbl_index = 0;
1738 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1739 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1740 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1741 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1742 actual_index, clip_pwrs,
1743 ch_info, a_band);
1744 }
1745 }
1746
1747 /* send Txpower command for current channel to ucode */
75bcfae9 1748 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1749}
1750
4a8a4322 1751int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1752{
d20b3c65 1753 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1754 s8 max_power;
1755 u8 a_band;
1756 u8 i;
1757
62ea9c5b 1758 if (priv->tx_power_user_lmt == power) {
e1623446 1759 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
b481de9c
ZY		 1760 "limit: %ddBm.\n", power);
1761 return 0;
1762 }
1763
e1623446 1764 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1765 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1766
1767 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1768
1769 for (i = 0; i < priv->channel_count; i++) {
1770 ch_info = &priv->channel_info[i];
1771 a_band = is_channel_a_band(ch_info);
1772
1773 /* find minimum power of all user and regulatory constraints
1774 * (does not consider h/w clipping limitations) */
bb8c093b 1775 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1776 max_power = min(power, max_power);
1777 if (max_power != ch_info->curr_txpow) {
1778 ch_info->curr_txpow = max_power;
1779
1780 /* this considers the h/w clipping limitations */
bb8c093b 1781 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1782 }
1783 }
1784
1785 /* update txpower settings for all channels,
1786 * send to NIC if associated. */
1787 is_temp_calib_needed(priv);
bb8c093b 1788 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1789
1790 return 0;
1791}
1792
5bbe233b
AK		 1793static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1794{
1795 int rc = 0;
2f301227 1796 struct iwl_rx_packet *pkt;
5bbe233b
AK		 1797 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1798 struct iwl_host_cmd cmd = {
1799 .id = REPLY_RXON_ASSOC,
1800 .len = sizeof(rxon_assoc),
c2acea8e 1801 .flags = CMD_WANT_SKB,
5bbe233b
AK		 1802 .data = &rxon_assoc,
1803 };
1804 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1805 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1806
1807 if ((rxon1->flags == rxon2->flags) &&
1808 (rxon1->filter_flags == rxon2->filter_flags) &&
1809 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1810 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1811 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1812 return 0;
1813 }
1814
1815 rxon_assoc.flags = priv->staging_rxon.flags;
1816 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1817 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1818 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1819 rxon_assoc.reserved = 0;
1820
1821 rc = iwl_send_cmd_sync(priv, &cmd);
1822 if (rc)
1823 return rc;
1824
2f301227
ZY		 1825 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1826 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
5bbe233b
AK		 1827 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1828 rc = -EIO;
1829 }
1830
2f301227
ZY		 1831 priv->alloc_rxb_page--;
1832 free_pages(cmd.reply_page, priv->hw_params.rx_page_order);
5bbe233b
AK		 1833
1834 return rc;
1835}
1836
e0158e61
AK		 1837/**
1838 * iwl3945_commit_rxon - commit staging_rxon to hardware
1839 *
1840 * The RXON command in staging_rxon is committed to the hardware and
1841 * the active_rxon structure is updated with the new data. This
1842 * function correctly transitions out of the RXON_ASSOC_MSK state if
1843 * a HW tune is required based on the RXON structure changes.
1844 */
1845static int iwl3945_commit_rxon(struct iwl_priv *priv)
1846{
1847 /* cast away the const for active_rxon in this function */
1848 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1849 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1850 int rc = 0;
1851 bool new_assoc =
1852 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1853
1854 if (!iwl_is_alive(priv))
1855 return -1;
1856
1857 /* always get timestamp with Rx frame */
1858 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1859
1860 /* select antenna */
1861 staging_rxon->flags &=
1862 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1863 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1864
1865 rc = iwl_check_rxon_cmd(priv);
1866 if (rc) {
1867 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1868 return -EINVAL;
1869 }
1870
1871 /* If we don't need to send a full RXON, we can use
1872 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1873 * and other flags for the current radio configuration. */
1874 if (!iwl_full_rxon_required(priv)) {
1875 rc = iwl_send_rxon_assoc(priv);
1876 if (rc) {
1877 IWL_ERR(priv, "Error setting RXON_ASSOC "
1878 "configuration (%d).\n", rc);
1879 return rc;
1880 }
1881
1882 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1883
1884 return 0;
1885 }
1886
1887 /* If we are currently associated and the new config requires
1888 * an RXON_ASSOC and the new config wants the associated mask enabled,
1889 * we must clear the associated from the active configuration
1890 * before we apply the new config */
1891 if (iwl_is_associated(priv) && new_assoc) {
1892 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1893 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1894
1895 /*
1896 * reserved4 and 5 could have been filled by the iwlcore code.
1897 * Let's clear them before pushing to the 3945.
1898 */
1899 active_rxon->reserved4 = 0;
1900 active_rxon->reserved5 = 0;
1901 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1902 sizeof(struct iwl3945_rxon_cmd),
1903 &priv->active_rxon);
1904
1905 /* If the mask clearing failed then we set
1906 * active_rxon back to what it was previously */
1907 if (rc) {
1908 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1909 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1910 "configuration (%d).\n", rc);
1911 return rc;
1912 }
1913 }
1914
1915 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1916 "* with%s RXON_FILTER_ASSOC_MSK\n"
1917 "* channel = %d\n"
1918 "* bssid = %pM\n",
1919 (new_assoc ? "" : "out"),
1920 le16_to_cpu(staging_rxon->channel),
1921 staging_rxon->bssid_addr);
1922
1923 /*
1924 * reserved4 and 5 could have been filled by the iwlcore code.
1925 * Let's clear them before pushing to the 3945.
1926 */
1927 staging_rxon->reserved4 = 0;
1928 staging_rxon->reserved5 = 0;
1929
90e8e424 1930 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
e0158e61
AK		 1931
1932 /* Apply the new configuration */
1933 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1934 sizeof(struct iwl3945_rxon_cmd),
1935 staging_rxon);
1936 if (rc) {
1937 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1938 return rc;
1939 }
1940
1941 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1942
c587de0b 1943 iwl_clear_stations_table(priv);
e0158e61
AK		 1944
1945 /* If we issue a new RXON command which required a tune then we must
1946 * send a new TXPOWER command or we won't be able to Tx any frames */
1947 rc = priv->cfg->ops->lib->send_tx_power(priv);
1948 if (rc) {
1949 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1950 return rc;
1951 }
1952
1953 /* Add the broadcast address so we can send broadcast frames */
c587de0b 1954 if (iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL) ==
e0158e61
AK		 1955 IWL_INVALID_STATION) {
1956 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
1957 return -EIO;
1958 }
1959
1960 /* If we have set the ASSOC_MSK and we are in BSS mode then
1961 * add the IWL_AP_ID to the station rate table */
1962 if (iwl_is_associated(priv) &&
1963 (priv->iw_mode == NL80211_IFTYPE_STATION))
c587de0b
TW		 1964 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
1965 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
e0158e61
AK		 1966 IWL_ERR(priv, "Error adding AP address for transmit\n");
1967 return -EIO;
1968 }
1969
1970 /* Init the hardware's rate fallback order based on the band */
1971 rc = iwl3945_init_hw_rate_table(priv);
1972 if (rc) {
1973 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1974 return -EIO;
1975 }
1976
1977 return 0;
1978}
1979
b481de9c 1980/* will add 3945 channel switch cmd handling later */
4a8a4322 1981int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1982{
1983 return 0;
1984}
1985
1986/**
1987 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1988 *
1989 * -- reset periodic timer
1990 * -- see if temp has changed enough to warrant re-calibration ... if so:
1991 * -- correct coeffs for temp (can reset temp timer)
1992 * -- save this temp as "last",
1993 * -- send new set of gain settings to NIC
1994 * NOTE: This should continue working, even when we're not associated,
1995 * so we can keep our internal table of scan powers current. */
4a8a4322 1996void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 1997{
1998 /* This will kick in the "brute force"
bb8c093b 1999 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 2000 if (!is_temp_calib_needed(priv))
2001 goto reschedule;
2002
2003 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2004 * This is based *only* on current temperature,
2005 * ignoring any previous power measurements */
bb8c093b 2006 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2007
2008 reschedule:
2009 queue_delayed_work(priv->workqueue,
2010 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2011}
2012
416e1438 2013static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2014{
4a8a4322 2015 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 2016 thermal_periodic.work);
2017
2018 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2019 return;
2020
2021 mutex_lock(&priv->mutex);
2022 iwl3945_reg_txpower_periodic(priv);
2023 mutex_unlock(&priv->mutex);
2024}
2025
2026/**
bb8c093b 2027 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2028 * for the channel.
2029 *
2030 * This function is used when initializing channel-info structs.
2031 *
2032 * NOTE: These channel groups do *NOT* match the bands above!
2033 * These channel groups are based on factory-tested channels;
2034 * on A-band, EEPROM's "group frequency" entries represent the top
2035 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2036 */
4a8a4322 2037static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2038 const struct iwl_channel_info *ch_info)
b481de9c 2039{
e6148917
SO		 2040 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2041 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 2042 u8 group;
2043 u16 group_index = 0; /* based on factory calib frequencies */
2044 u8 grp_channel;
2045
2046 /* Find the group index for the channel ... don't use index 1(?) */
2047 if (is_channel_a_band(ch_info)) {
2048 for (group = 1; group < 5; group++) {
2049 grp_channel = ch_grp[group].group_channel;
2050 if (ch_info->channel <= grp_channel) {
2051 group_index = group;
2052 break;
2053 }
2054 }
2055 /* group 4 has a few channels *above* its factory cal freq */
2056 if (group == 5)
2057 group_index = 4;
2058 } else
2059 group_index = 0; /* 2.4 GHz, group 0 */
2060
e1623446 2061 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
b481de9c
ZY		 2062 group_index);
2063 return group_index;
2064}
2065
2066/**
bb8c093b 2067 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2068 *
2069 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2070 * into radio/DSP gain settings table for requested power.
2071 */
4a8a4322 2072static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2073 s8 requested_power,
2074 s32 setting_index, s32 *new_index)
2075{
bb8c093b 2076 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 2077 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2078 s32 index0, index1;
2079 s32 power = 2 * requested_power;
2080 s32 i;
bb8c093b 2081 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2082 s32 gains0, gains1;
2083 s32 res;
2084 s32 denominator;
2085
e6148917 2086 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 2087 samples = chnl_grp->samples;
2088 for (i = 0; i < 5; i++) {
2089 if (power == samples[i].power) {
2090 *new_index = samples[i].gain_index;
2091 return 0;
2092 }
2093 }
2094
2095 if (power > samples[1].power) {
2096 index0 = 0;
2097 index1 = 1;
2098 } else if (power > samples[2].power) {
2099 index0 = 1;
2100 index1 = 2;
2101 } else if (power > samples[3].power) {
2102 index0 = 2;
2103 index1 = 3;
2104 } else {
2105 index0 = 3;
2106 index1 = 4;
2107 }
2108
2109 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2110 if (denominator == 0)
2111 return -EINVAL;
2112 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2113 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2114 res = gains0 + (gains1 - gains0) *
2115 ((s32) power - (s32) samples[index0].power) / denominator +
2116 (1 << 18);
2117 *new_index = res >> 19;
2118 return 0;
2119}
2120
4a8a4322 2121static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2122{
2123 u32 i;
2124 s32 rate_index;
e6148917 2125 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2126 const struct iwl3945_eeprom_txpower_group *group;
b481de9c 2127
e1623446 2128 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
b481de9c
ZY		 2129
2130 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2131 s8 *clip_pwrs; /* table of power levels for each rate */
2132 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2133 group = &eeprom->groups[i];
b481de9c
ZY		 2134
2135 /* sanity check on factory saturation power value */
2136 if (group->saturation_power < 40) {
39aadf8c 2137 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2138 "less than minimum expected 40\n",
2139 group->saturation_power);
2140 return;
2141 }
2142
2143 /*
2144 * Derive requested power levels for each rate, based on
2145 * hardware capabilities (saturation power for band).
2146 * Basic value is 3dB down from saturation, with further
2147 * power reductions for highest 3 data rates. These
2148 * backoffs provide headroom for high rate modulation
2149 * power peaks, without too much distortion (clipping).
2150 */
2151 /* we'll fill in this array with h/w max power levels */
f2c7e521 2152 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
b481de9c
ZY		 2153
2154 /* divide factory saturation power by 2 to find -3dB level */
2155 satur_pwr = (s8) (group->saturation_power >> 1);
2156
2157 /* fill in channel group's nominal powers for each rate */
2158 for (rate_index = 0;
2159 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2160 switch (rate_index) {
14577f23 2161 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2162 if (i == 0) /* B/G */
2163 *clip_pwrs = satur_pwr;
2164 else /* A */
2165 *clip_pwrs = satur_pwr - 5;
2166 break;
14577f23 2167 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2168 if (i == 0)
2169 *clip_pwrs = satur_pwr - 7;
2170 else
2171 *clip_pwrs = satur_pwr - 10;
2172 break;
14577f23 2173 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2174 if (i == 0)
2175 *clip_pwrs = satur_pwr - 9;
2176 else
2177 *clip_pwrs = satur_pwr - 12;
2178 break;
2179 default:
2180 *clip_pwrs = satur_pwr;
2181 break;
2182 }
2183 }
2184 }
2185}
2186
2187/**
2188 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2189 *
2190 * Second pass (during init) to set up priv->channel_info
2191 *
2192 * Set up Tx-power settings in our channel info database for each VALID
2193 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2194 * and current temperature.
2195 *
2196 * Since this is based on current temperature (at init time), these values may
2197 * not be valid for very long, but it gives us a starting/default point,
2198 * and allows us to active (i.e. using Tx) scan.
2199 *
2200 * This does *not* write values to NIC, just sets up our internal table.
2201 */
4a8a4322 2202int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2203{
d20b3c65 2204 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2205 struct iwl3945_channel_power_info *pwr_info;
e6148917 2206 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2207 int delta_index;
2208 u8 rate_index;
2209 u8 scan_tbl_index;
2210 const s8 *clip_pwrs; /* array of power levels for each rate */
2211 u8 gain, dsp_atten;
2212 s8 power;
2213 u8 pwr_index, base_pwr_index, a_band;
2214 u8 i;
2215 int temperature;
2216
2217 /* save temperature reference,
2218 * so we can determine next time to calibrate */
bb8c093b 2219 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2220 priv->last_temperature = temperature;
2221
bb8c093b 2222 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2223
2224 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2225 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2226 i++, ch_info++) {
2227 a_band = is_channel_a_band(ch_info);
2228 if (!is_channel_valid(ch_info))
2229 continue;
2230
2231 /* find this channel's channel group (*not* "band") index */
2232 ch_info->group_index =
bb8c093b 2233 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2234
2235 /* Get this chnlgrp's rate->max/clip-powers table */
f2c7e521 2236 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2237
2238 /* calculate power index *adjustment* value according to
2239 * diff between current temperature and factory temperature */
bb8c093b 2240 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2241 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2242 temperature);
2243
e1623446 2244 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
b481de9c
ZY		 2245 ch_info->channel, delta_index, temperature +
2246 IWL_TEMP_CONVERT);
2247
2248 /* set tx power value for all OFDM rates */
2249 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2250 rate_index++) {
25a4ccea 2251 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2252 int rc;
2253
2254 /* use channel group's clip-power table,
2255 * but don't exceed channel's max power */
2256 s8 pwr = min(ch_info->max_power_avg,
2257 clip_pwrs[rate_index]);
2258
2259 pwr_info = &ch_info->power_info[rate_index];
2260
2261 /* get base (i.e. at factory-measured temperature)
2262 * power table index for this rate's power */
bb8c093b 2263 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2264 ch_info->group_index,
2265 &power_idx);
2266 if (rc) {
15b1687c 2267 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2268 return rc;
2269 }
2270 pwr_info->base_power_index = (u8) power_idx;
2271
2272 /* temperature compensate */
2273 power_idx += delta_index;
2274
2275 /* stay within range of gain table */
bb8c093b 2276 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2277
bb8c093b 2278 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2279 pwr_info->requested_power = pwr;
2280 pwr_info->power_table_index = (u8) power_idx;
2281 pwr_info->tpc.tx_gain =
2282 power_gain_table[a_band][power_idx].tx_gain;
2283 pwr_info->tpc.dsp_atten =
2284 power_gain_table[a_band][power_idx].dsp_atten;
2285 }
2286
2287 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2288 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2289 power = pwr_info->requested_power +
2290 IWL_CCK_FROM_OFDM_POWER_DIFF;
2291 pwr_index = pwr_info->power_table_index +
2292 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2293 base_pwr_index = pwr_info->base_power_index +
2294 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2295
2296 /* stay within table range */
bb8c093b 2297 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2298 gain = power_gain_table[a_band][pwr_index].tx_gain;
2299 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2300
bb8c093b 2301 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2302 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2303 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2304 for (rate_index = 0;
2305 rate_index < IWL_CCK_RATES; rate_index++) {
2306 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2307 pwr_info->requested_power = power;
2308 pwr_info->power_table_index = pwr_index;
2309 pwr_info->base_power_index = base_pwr_index;
2310 pwr_info->tpc.tx_gain = gain;
2311 pwr_info->tpc.dsp_atten = dsp_atten;
2312 }
2313
2314 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2315 for (scan_tbl_index = 0;
2316 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2317 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2318 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2319 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2320 actual_index, clip_pwrs, ch_info, a_band);
2321 }
2322 }
2323
2324 return 0;
2325}
2326
4a8a4322 2327int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2328{
2329 int rc;
b481de9c 2330
5d49f498
AK		 2331 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2332 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2333 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2334 if (rc < 0)
15b1687c 2335 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2336
b481de9c
ZY		 2337 return 0;
2338}
2339
188cf6c7 2340int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 2341{
b481de9c
ZY		 2342 int txq_id = txq->q.id;
2343
3832ec9d 2344 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2345
2346 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2347
5d49f498
AK		 2348 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2349 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2350
5d49f498 2351 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2352 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2353 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2354 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2355 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2356 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
b481de9c
ZY		 2357
2358 /* fake read to flush all prev. writes */
5d49f498 2359 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2360
2361 return 0;
2362}
2363
42427b4e
KA		 2364/*
2365 * HCMD utils
2366 */
2367static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2368{
2369 switch (cmd_id) {
2370 case REPLY_RXON:
d25aabb0
WT		 2371 return sizeof(struct iwl3945_rxon_cmd);
2372 case POWER_TABLE_CMD:
2373 return sizeof(struct iwl3945_powertable_cmd);
42427b4e
KA		 2374 default:
2375 return len;
2376 }
2377}
2378
c587de0b 2379
17f841cd
SO		 2380static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2381{
c587de0b
TW		 2382 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2383 addsta->mode = cmd->mode;
2384 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2385 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2386 addsta->station_flags = cmd->station_flags;
2387 addsta->station_flags_msk = cmd->station_flags_msk;
2388 addsta->tid_disable_tx = cpu_to_le16(0);
2389 addsta->rate_n_flags = cmd->rate_n_flags;
2390 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2391 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2392 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2393
2394 return (u16)sizeof(struct iwl3945_addsta_cmd);
17f841cd
SO		 2395}
2396
c587de0b 2397
b481de9c
ZY		 2398/**
2399 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2400 */
4a8a4322 2401int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2402{
14577f23 2403 int rc, i, index, prev_index;
bb8c093b 2404 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2405 .reserved = {0, 0, 0},
2406 };
bb8c093b 2407 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2408
bb8c093b
CH		 2409 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2410 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2411
2412 table[index].rate_n_flags =
bb8c093b 2413 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2414 table[index].try_cnt = priv->retry_rate;
bb8c093b 2415 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2416 table[index].next_rate_index =
2417 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2418 }
2419
8318d78a
JB		 2420 switch (priv->band) {
2421 case IEEE80211_BAND_5GHZ:
e1623446 2422 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
b481de9c
ZY		 2423 /* If one of the following CCK rates is used,
2424 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2425 for (i = IWL_RATE_1M_INDEX_TABLE;
2426 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2427 table[i].next_rate_index =
2428 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2429
2430 /* Don't fall back to CCK rates */
7262796a
AM		 2431 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2432 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2433
2434 /* Don't drop out of OFDM rates */
14577f23 2435 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2436 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2437 break;
2438
8318d78a 2439 case IEEE80211_BAND_2GHZ:
e1623446 2440 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
b481de9c
ZY		 2441 /* If an OFDM rate is used, have it fall back to the
2442 * 1M CCK rates */
b481de9c 2443
7262796a 2444 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 2445 iwl_is_associated(priv)) {
7262796a
AM		 2446
2447 index = IWL_FIRST_CCK_RATE;
2448 for (i = IWL_RATE_6M_INDEX_TABLE;
2449 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2450 table[i].next_rate_index =
2451 iwl3945_rates[index].table_rs_index;
2452
2453 index = IWL_RATE_11M_INDEX_TABLE;
2454 /* CCK shouldn't fall back to OFDM... */
2455 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2456 }
b481de9c
ZY		 2457 break;
2458
2459 default:
8318d78a 2460 WARN_ON(1);
b481de9c
ZY		 2461 break;
2462 }
2463
2464 /* Update the rate scaling for control frame Tx */
2465 rate_cmd.table_id = 0;
518099a8 2466 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2467 &rate_cmd);
2468 if (rc)
2469 return rc;
2470
2471 /* Update the rate scaling for data frame Tx */
2472 rate_cmd.table_id = 1;
518099a8 2473 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2474 &rate_cmd);
2475}
2476
796083cb 2477/* Called when initializing driver */
4a8a4322 2478int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2479{
3832ec9d
AK		 2480 memset((void *)&priv->hw_params, 0,
2481 sizeof(struct iwl_hw_params));
b481de9c 2482
3832ec9d 2483 priv->shared_virt =
b481de9c 2484 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2485 sizeof(struct iwl3945_shared),
3832ec9d 2486 &priv->shared_phys);
b481de9c 2487
3832ec9d 2488 if (!priv->shared_virt) {
15b1687c 2489 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2490 mutex_unlock(&priv->mutex);
2491 return -ENOMEM;
2492 }
2493
21c02a1a 2494 /* Assign number of Usable TX queues */
88804e2b 2495 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
21c02a1a 2496
a8e74e27 2497 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2f301227 2498 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
3832ec9d
AK		 2499 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2500 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2501 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2502 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2503
141c43a3 2504 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2c2f3b33 2505 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
141c43a3 2506
b481de9c
ZY		 2507 return 0;
2508}
2509
4a8a4322 2510unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2511 struct iwl3945_frame *frame, u8 rate)
b481de9c 2512{
bb8c093b 2513 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2514 unsigned int frame_size;
2515
bb8c093b 2516 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2517 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2518
3832ec9d 2519 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2520 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2521
bb8c093b 2522 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2523 tx_beacon_cmd->frame,
b481de9c
ZY		 2524 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2525
2526 BUG_ON(frame_size > MAX_MPDU_SIZE);
2527 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2528
2529 tx_beacon_cmd->tx.rate = rate;
2530 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2531 TX_CMD_FLG_TSF_MSK);
2532
14577f23
MA		 2533 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2534 tx_beacon_cmd->tx.supp_rates[0] =
2535 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2536
b481de9c 2537 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2538 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2539
3ac7f146 2540 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2541}
2542
4a8a4322 2543void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2544{
91c066f2 2545 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2546 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2547}
2548
4a8a4322 2549void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2550{
2551 INIT_DELAYED_WORK(&priv->thermal_periodic,
2552 iwl3945_bg_reg_txpower_periodic);
2553}
2554
4a8a4322 2555void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2556{
2557 cancel_delayed_work(&priv->thermal_periodic);
2558}
2559
0164b9b4
KA		 2560/* check contents of special bootstrap uCode SRAM */
2561static int iwl3945_verify_bsm(struct iwl_priv *priv)
2562 {
2563 __le32 *image = priv->ucode_boot.v_addr;
2564 u32 len = priv->ucode_boot.len;
2565 u32 reg;
2566 u32 val;
2567
e1623446 2568 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
0164b9b4
KA		 2569
2570 /* verify BSM SRAM contents */
2571 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2572 for (reg = BSM_SRAM_LOWER_BOUND;
2573 reg < BSM_SRAM_LOWER_BOUND + len;
2574 reg += sizeof(u32), image++) {
2575 val = iwl_read_prph(priv, reg);
2576 if (val != le32_to_cpu(*image)) {
2577 IWL_ERR(priv, "BSM uCode verification failed at "
2578 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2579 BSM_SRAM_LOWER_BOUND,
2580 reg - BSM_SRAM_LOWER_BOUND, len,
2581 val, le32_to_cpu(*image));
2582 return -EIO;
2583 }
2584 }
2585
e1623446 2586 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
0164b9b4
KA		 2587
2588 return 0;
2589}
2590
e6148917
SO		 2591
2592/******************************************************************************
2593 *
2594 * EEPROM related functions
2595 *
2596 ******************************************************************************/
2597
2598/*
2599 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2600 * embedded controller) as EEPROM reader; each read is a series of pulses
2601 * to/from the EEPROM chip, not a single event, so even reads could conflict
2602 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2603 * simply claims ownership, which should be safe when this function is called
2604 * (i.e. before loading uCode!).
2605 */
2606static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2607{
2608 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2609 return 0;
2610}
2611
2612
2613static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2614{
2615 return;
2616}
2617
0164b9b4
KA		 2618 /**
2619 * iwl3945_load_bsm - Load bootstrap instructions
2620 *
2621 * BSM operation:
2622 *
2623 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2624 * in special SRAM that does not power down during RFKILL. When powering back
2625 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2626 * the bootstrap program into the on-board processor, and starts it.
2627 *
2628 * The bootstrap program loads (via DMA) instructions and data for a new
2629 * program from host DRAM locations indicated by the host driver in the
2630 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2631 * automatically.
2632 *
2633 * When initializing the NIC, the host driver points the BSM to the
2634 * "initialize" uCode image. This uCode sets up some internal data, then
2635 * notifies host via "initialize alive" that it is complete.
2636 *
2637 * The host then replaces the BSM_DRAM_* pointer values to point to the
2638 * normal runtime uCode instructions and a backup uCode data cache buffer
2639 * (filled initially with starting data values for the on-board processor),
2640 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2641 * which begins normal operation.
2642 *
2643 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2644 * the backup data cache in DRAM before SRAM is powered down.
2645 *
2646 * When powering back up, the BSM loads the bootstrap program. This reloads
2647 * the runtime uCode instructions and the backup data cache into SRAM,
2648 * and re-launches the runtime uCode from where it left off.
2649 */
2650static int iwl3945_load_bsm(struct iwl_priv *priv)
2651{
2652 __le32 *image = priv->ucode_boot.v_addr;
2653 u32 len = priv->ucode_boot.len;
2654 dma_addr_t pinst;
2655 dma_addr_t pdata;
2656 u32 inst_len;
2657 u32 data_len;
2658 int rc;
2659 int i;
2660 u32 done;
2661 u32 reg_offset;
2662
e1623446 2663 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
0164b9b4
KA		 2664
2665 /* make sure bootstrap program is no larger than BSM's SRAM size */
2666 if (len > IWL39_MAX_BSM_SIZE)
2667 return -EINVAL;
2668
2669 /* Tell bootstrap uCode where to find the "Initialize" uCode
2670 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2671 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2672 * after the "initialize" uCode has run, to point to
2673 * runtime/protocol instructions and backup data cache. */
2674 pinst = priv->ucode_init.p_addr;
2675 pdata = priv->ucode_init_data.p_addr;
2676 inst_len = priv->ucode_init.len;
2677 data_len = priv->ucode_init_data.len;
2678
0164b9b4
KA		 2679 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2680 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2681 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2682 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2683
2684 /* Fill BSM memory with bootstrap instructions */
2685 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2686 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2687 reg_offset += sizeof(u32), image++)
2688 _iwl_write_prph(priv, reg_offset,
2689 le32_to_cpu(*image));
2690
2691 rc = iwl3945_verify_bsm(priv);
a8b50a0a 2692 if (rc)
0164b9b4 2693 return rc;
0164b9b4
KA		 2694
2695 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2696 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2697 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2698 IWL39_RTC_INST_LOWER_BOUND);
2699 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2700
2701 /* Load bootstrap code into instruction SRAM now,
2702 * to prepare to load "initialize" uCode */
2703 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2704 BSM_WR_CTRL_REG_BIT_START);
2705
2706 /* Wait for load of bootstrap uCode to finish */
2707 for (i = 0; i < 100; i++) {
2708 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2709 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2710 break;
2711 udelay(10);
2712 }
2713 if (i < 100)
e1623446 2714 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
0164b9b4
KA		 2715 else {
2716 IWL_ERR(priv, "BSM write did not complete!\n");
2717 return -EIO;
2718 }
2719
2720 /* Enable future boot loads whenever power management unit triggers it
2721 * (e.g. when powering back up after power-save shutdown) */
2722 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2723 BSM_WR_CTRL_REG_BIT_START_EN);
2724
0164b9b4
KA		 2725 return 0;
2726}
2727
cc0f555d
JS		 2728#define IWL3945_UCODE_GET(item) \
2729static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2730 u32 api_ver) \
2731{ \
2732 return le32_to_cpu(ucode->u.v1.item); \
2733}
2734
2735static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2736{
2737 return UCODE_HEADER_SIZE(1);
2738}
2739static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2740 u32 api_ver)
2741{
2742 return 0;
2743}
2744static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2745 u32 api_ver)
2746{
2747 return (u8 *) ucode->u.v1.data;
2748}
2749
2750IWL3945_UCODE_GET(inst_size);
2751IWL3945_UCODE_GET(data_size);
2752IWL3945_UCODE_GET(init_size);
2753IWL3945_UCODE_GET(init_data_size);
2754IWL3945_UCODE_GET(boot_size);
2755
5bbe233b
AK		 2756static struct iwl_hcmd_ops iwl3945_hcmd = {
2757 .rxon_assoc = iwl3945_send_rxon_assoc,
e0158e61 2758 .commit_rxon = iwl3945_commit_rxon,
5bbe233b
AK		 2759};
2760
cc0f555d
JS		 2761static struct iwl_ucode_ops iwl3945_ucode = {
2762 .get_header_size = iwl3945_ucode_get_header_size,
2763 .get_build = iwl3945_ucode_get_build,
2764 .get_inst_size = iwl3945_ucode_get_inst_size,
2765 .get_data_size = iwl3945_ucode_get_data_size,
2766 .get_init_size = iwl3945_ucode_get_init_size,
2767 .get_init_data_size = iwl3945_ucode_get_init_data_size,
2768 .get_boot_size = iwl3945_ucode_get_boot_size,
2769 .get_data = iwl3945_ucode_get_data,
2770};
2771
0164b9b4 2772static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2773 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2774 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2775 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2776 .load_ucode = iwl3945_load_bsm,
b7a79404
RC		 2777 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2778 .dump_nic_error_log = iwl3945_dump_nic_error_log,
01ec616d
KA		 2779 .apm_ops = {
2780 .init = iwl3945_apm_init,
d68b603c 2781 .stop = iwl_apm_stop,
01ec616d 2782 .config = iwl3945_nic_config,
854682ed 2783 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2784 },
e6148917
SO		 2785 .eeprom_ops = {
2786 .regulatory_bands = {
2787 EEPROM_REGULATORY_BAND_1_CHANNELS,
2788 EEPROM_REGULATORY_BAND_2_CHANNELS,
2789 EEPROM_REGULATORY_BAND_3_CHANNELS,
2790 EEPROM_REGULATORY_BAND_4_CHANNELS,
2791 EEPROM_REGULATORY_BAND_5_CHANNELS,
7aafef1c
WYG		 2792 EEPROM_REGULATORY_BAND_NO_HT40,
2793 EEPROM_REGULATORY_BAND_NO_HT40,
e6148917
SO		 2794 },
2795 .verify_signature = iwlcore_eeprom_verify_signature,
2796 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2797 .release_semaphore = iwl3945_eeprom_release_semaphore,
2798 .query_addr = iwlcore_eeprom_query_addr,
2799 },
75bcfae9 2800 .send_tx_power = iwl3945_send_tx_power,
c2436980 2801 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
5bbe233b 2802 .post_associate = iwl3945_post_associate,
ef850d7c 2803 .isr = iwl_isr_legacy,
60690a6a 2804 .config_ap = iwl3945_config_ap,
0164b9b4
KA		 2805};
2806
42427b4e
KA		 2807static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2808 .get_hcmd_size = iwl3945_get_hcmd_size,
17f841cd 2809 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
37dc70fe 2810 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
42427b4e
KA		 2811};
2812
0164b9b4 2813static struct iwl_ops iwl3945_ops = {
cc0f555d 2814 .ucode = &iwl3945_ucode,
0164b9b4 2815 .lib = &iwl3945_lib,
5bbe233b 2816 .hcmd = &iwl3945_hcmd,
42427b4e 2817 .utils = &iwl3945_hcmd_utils,
e932a609 2818 .led = &iwl3945_led_ops,
0164b9b4
KA		 2819};
2820
c0f20d91 2821static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2822 .name = "3945BG",
a0987a8d
RC		 2823 .fw_name_pre = IWL3945_FW_PRE,
2824 .ucode_api_max = IWL3945_UCODE_API_MAX,
2825 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2826 .sku = IWL_SKU_G,
e6148917
SO		 2827 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2828 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2829 .ops = &iwl3945_ops,
88804e2b 2830 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2831 .mod_params = &iwl3945_mod_params,
fadb3582
BC		 2832 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2833 .set_l0s = false,
2834 .use_bsm = true,
b261793d
DH		 2835 .use_isr_legacy = true,
2836 .ht_greenfield_support = false,
f2d0d0e2 2837 .led_compensation = 64,
82b9a121
TW		 2838};
2839
c0f20d91 2840static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2841 .name = "3945ABG",
a0987a8d
RC		 2842 .fw_name_pre = IWL3945_FW_PRE,
2843 .ucode_api_max = IWL3945_UCODE_API_MAX,
2844 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2845 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2846 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2847 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2848 .ops = &iwl3945_ops,
88804e2b 2849 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2850 .mod_params = &iwl3945_mod_params,
b261793d
DH		 2851 .use_isr_legacy = true,
2852 .ht_greenfield_support = false,
f2d0d0e2 2853 .led_compensation = 64,
82b9a121
TW		 2854};
2855
bb8c093b 2856struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2857 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2858 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2859 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2860 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2861 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2862 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2863 {0}
2864};
2865
bb8c093b 2866MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Linux kernel - Deliverables
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