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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved. |
b481de9c ZY |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
759ef89f | 22 | * Intel Linux Wireless <ilw@linux.intel.com> |
b481de9c ZY |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
24 | * | |
25 | *****************************************************************************/ | |
26 | ||
27 | #include <linux/kernel.h> | |
28 | #include <linux/module.h> | |
b481de9c ZY |
29 | #include <linux/init.h> |
30 | #include <linux/pci.h> | |
31 | #include <linux/dma-mapping.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/skbuff.h> | |
34 | #include <linux/netdevice.h> | |
35 | #include <linux/wireless.h> | |
36 | #include <linux/firmware.h> | |
b481de9c | 37 | #include <linux/etherdevice.h> |
12342c47 ZY |
38 | #include <asm/unaligned.h> |
39 | #include <net/mac80211.h> | |
b481de9c | 40 | |
dbb6654c | 41 | #include "iwl-fh.h" |
bddadf86 | 42 | #include "iwl-3945-fh.h" |
600c0e11 | 43 | #include "iwl-commands.h" |
b481de9c | 44 | #include "iwl-3945.h" |
5d08cd1d | 45 | #include "iwl-helpers.h" |
5747d47f | 46 | #include "iwl-core.h" |
d9829a67 | 47 | #include "iwl-agn-rs.h" |
b481de9c ZY |
48 | |
49 | #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \ | |
50 | [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \ | |
51 | IWL_RATE_##r##M_IEEE, \ | |
52 | IWL_RATE_##ip##M_INDEX, \ | |
53 | IWL_RATE_##in##M_INDEX, \ | |
54 | IWL_RATE_##rp##M_INDEX, \ | |
55 | IWL_RATE_##rn##M_INDEX, \ | |
56 | IWL_RATE_##pp##M_INDEX, \ | |
14577f23 MA |
57 | IWL_RATE_##np##M_INDEX, \ |
58 | IWL_RATE_##r##M_INDEX_TABLE, \ | |
59 | IWL_RATE_##ip##M_INDEX_TABLE } | |
b481de9c ZY |
60 | |
61 | /* | |
62 | * Parameter order: | |
63 | * rate, prev rate, next rate, prev tgg rate, next tgg rate | |
64 | * | |
65 | * If there isn't a valid next or previous rate then INV is used which | |
66 | * maps to IWL_RATE_INVALID | |
67 | * | |
68 | */ | |
d9829a67 | 69 | const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = { |
14577f23 MA |
70 | IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */ |
71 | IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */ | |
72 | IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */ | |
73 | IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */ | |
b481de9c ZY |
74 | IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */ |
75 | IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */ | |
76 | IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */ | |
77 | IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */ | |
78 | IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */ | |
79 | IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */ | |
80 | IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */ | |
81 | IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */ | |
b481de9c ZY |
82 | }; |
83 | ||
bb8c093b | 84 | /* 1 = enable the iwl3945_disable_events() function */ |
b481de9c ZY |
85 | #define IWL_EVT_DISABLE (0) |
86 | #define IWL_EVT_DISABLE_SIZE (1532/32) | |
87 | ||
88 | /** | |
bb8c093b | 89 | * iwl3945_disable_events - Disable selected events in uCode event log |
b481de9c ZY |
90 | * |
91 | * Disable an event by writing "1"s into "disable" | |
92 | * bitmap in SRAM. Bit position corresponds to Event # (id/type). | |
93 | * Default values of 0 enable uCode events to be logged. | |
94 | * Use for only special debugging. This function is just a placeholder as-is, | |
95 | * you'll need to provide the special bits! ... | |
96 | * ... and set IWL_EVT_DISABLE to 1. */ | |
4a8a4322 | 97 | void iwl3945_disable_events(struct iwl_priv *priv) |
b481de9c | 98 | { |
af7cca2a | 99 | int ret; |
b481de9c ZY |
100 | int i; |
101 | u32 base; /* SRAM address of event log header */ | |
102 | u32 disable_ptr; /* SRAM address of event-disable bitmap array */ | |
103 | u32 array_size; /* # of u32 entries in array */ | |
104 | u32 evt_disable[IWL_EVT_DISABLE_SIZE] = { | |
105 | 0x00000000, /* 31 - 0 Event id numbers */ | |
106 | 0x00000000, /* 63 - 32 */ | |
107 | 0x00000000, /* 95 - 64 */ | |
108 | 0x00000000, /* 127 - 96 */ | |
109 | 0x00000000, /* 159 - 128 */ | |
110 | 0x00000000, /* 191 - 160 */ | |
111 | 0x00000000, /* 223 - 192 */ | |
112 | 0x00000000, /* 255 - 224 */ | |
113 | 0x00000000, /* 287 - 256 */ | |
114 | 0x00000000, /* 319 - 288 */ | |
115 | 0x00000000, /* 351 - 320 */ | |
116 | 0x00000000, /* 383 - 352 */ | |
117 | 0x00000000, /* 415 - 384 */ | |
118 | 0x00000000, /* 447 - 416 */ | |
119 | 0x00000000, /* 479 - 448 */ | |
120 | 0x00000000, /* 511 - 480 */ | |
121 | 0x00000000, /* 543 - 512 */ | |
122 | 0x00000000, /* 575 - 544 */ | |
123 | 0x00000000, /* 607 - 576 */ | |
124 | 0x00000000, /* 639 - 608 */ | |
125 | 0x00000000, /* 671 - 640 */ | |
126 | 0x00000000, /* 703 - 672 */ | |
127 | 0x00000000, /* 735 - 704 */ | |
128 | 0x00000000, /* 767 - 736 */ | |
129 | 0x00000000, /* 799 - 768 */ | |
130 | 0x00000000, /* 831 - 800 */ | |
131 | 0x00000000, /* 863 - 832 */ | |
132 | 0x00000000, /* 895 - 864 */ | |
133 | 0x00000000, /* 927 - 896 */ | |
134 | 0x00000000, /* 959 - 928 */ | |
135 | 0x00000000, /* 991 - 960 */ | |
136 | 0x00000000, /* 1023 - 992 */ | |
137 | 0x00000000, /* 1055 - 1024 */ | |
138 | 0x00000000, /* 1087 - 1056 */ | |
139 | 0x00000000, /* 1119 - 1088 */ | |
140 | 0x00000000, /* 1151 - 1120 */ | |
141 | 0x00000000, /* 1183 - 1152 */ | |
142 | 0x00000000, /* 1215 - 1184 */ | |
143 | 0x00000000, /* 1247 - 1216 */ | |
144 | 0x00000000, /* 1279 - 1248 */ | |
145 | 0x00000000, /* 1311 - 1280 */ | |
146 | 0x00000000, /* 1343 - 1312 */ | |
147 | 0x00000000, /* 1375 - 1344 */ | |
148 | 0x00000000, /* 1407 - 1376 */ | |
149 | 0x00000000, /* 1439 - 1408 */ | |
150 | 0x00000000, /* 1471 - 1440 */ | |
151 | 0x00000000, /* 1503 - 1472 */ | |
152 | }; | |
153 | ||
154 | base = le32_to_cpu(priv->card_alive.log_event_table_ptr); | |
bb8c093b | 155 | if (!iwl3945_hw_valid_rtc_data_addr(base)) { |
15b1687c | 156 | IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base); |
b481de9c ZY |
157 | return; |
158 | } | |
159 | ||
5d49f498 | 160 | ret = iwl_grab_nic_access(priv); |
af7cca2a | 161 | if (ret) { |
39aadf8c | 162 | IWL_WARN(priv, "Can not read from adapter at this time.\n"); |
b481de9c ZY |
163 | return; |
164 | } | |
165 | ||
5d49f498 AK |
166 | disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32))); |
167 | array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32))); | |
168 | iwl_release_nic_access(priv); | |
b481de9c ZY |
169 | |
170 | if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) { | |
171 | IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n", | |
172 | disable_ptr); | |
5d49f498 | 173 | ret = iwl_grab_nic_access(priv); |
b481de9c | 174 | for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++) |
5d49f498 | 175 | iwl_write_targ_mem(priv, |
af7cca2a TW |
176 | disable_ptr + (i * sizeof(u32)), |
177 | evt_disable[i]); | |
b481de9c | 178 | |
5d49f498 | 179 | iwl_release_nic_access(priv); |
b481de9c ZY |
180 | } else { |
181 | IWL_DEBUG_INFO("Selected uCode log events may be disabled\n"); | |
182 | IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n"); | |
183 | IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n", | |
184 | disable_ptr, array_size); | |
185 | } | |
186 | ||
187 | } | |
188 | ||
17744ff6 TW |
189 | static int iwl3945_hwrate_to_plcp_idx(u8 plcp) |
190 | { | |
191 | int idx; | |
192 | ||
193 | for (idx = 0; idx < IWL_RATE_COUNT; idx++) | |
194 | if (iwl3945_rates[idx].plcp == plcp) | |
195 | return idx; | |
196 | return -1; | |
197 | } | |
198 | ||
b481de9c ZY |
199 | /** |
200 | * iwl3945_get_antenna_flags - Get antenna flags for RXON command | |
201 | * @priv: eeprom and antenna fields are used to determine antenna flags | |
202 | * | |
f2c7e521 | 203 | * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed |
b481de9c ZY |
204 | * priv->antenna specifies the antenna diversity mode: |
205 | * | |
a96a27f9 | 206 | * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself |
b481de9c ZY |
207 | * IWL_ANTENNA_MAIN - Force MAIN antenna |
208 | * IWL_ANTENNA_AUX - Force AUX antenna | |
209 | */ | |
4a8a4322 | 210 | __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv) |
b481de9c ZY |
211 | { |
212 | switch (priv->antenna) { | |
213 | case IWL_ANTENNA_DIVERSITY: | |
214 | return 0; | |
215 | ||
216 | case IWL_ANTENNA_MAIN: | |
f2c7e521 | 217 | if (priv->eeprom39.antenna_switch_type) |
b481de9c ZY |
218 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; |
219 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; | |
220 | ||
221 | case IWL_ANTENNA_AUX: | |
f2c7e521 | 222 | if (priv->eeprom39.antenna_switch_type) |
b481de9c ZY |
223 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK; |
224 | return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK; | |
225 | } | |
226 | ||
227 | /* bad antenna selector value */ | |
15b1687c | 228 | IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", priv->antenna); |
b481de9c ZY |
229 | return 0; /* "diversity" is default if error */ |
230 | } | |
231 | ||
91c066f2 TW |
232 | #ifdef CONFIG_IWL3945_DEBUG |
233 | #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x | |
234 | ||
235 | static const char *iwl3945_get_tx_fail_reason(u32 status) | |
236 | { | |
237 | switch (status & TX_STATUS_MSK) { | |
238 | case TX_STATUS_SUCCESS: | |
239 | return "SUCCESS"; | |
240 | TX_STATUS_ENTRY(SHORT_LIMIT); | |
241 | TX_STATUS_ENTRY(LONG_LIMIT); | |
242 | TX_STATUS_ENTRY(FIFO_UNDERRUN); | |
243 | TX_STATUS_ENTRY(MGMNT_ABORT); | |
244 | TX_STATUS_ENTRY(NEXT_FRAG); | |
245 | TX_STATUS_ENTRY(LIFE_EXPIRE); | |
246 | TX_STATUS_ENTRY(DEST_PS); | |
247 | TX_STATUS_ENTRY(ABORTED); | |
248 | TX_STATUS_ENTRY(BT_RETRY); | |
249 | TX_STATUS_ENTRY(STA_INVALID); | |
250 | TX_STATUS_ENTRY(FRAG_DROPPED); | |
251 | TX_STATUS_ENTRY(TID_DISABLE); | |
252 | TX_STATUS_ENTRY(FRAME_FLUSHED); | |
253 | TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); | |
254 | TX_STATUS_ENTRY(TX_LOCKED); | |
255 | TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); | |
256 | } | |
257 | ||
258 | return "UNKNOWN"; | |
259 | } | |
260 | #else | |
261 | static inline const char *iwl3945_get_tx_fail_reason(u32 status) | |
262 | { | |
263 | return ""; | |
264 | } | |
265 | #endif | |
266 | ||
e6a9854b JB |
267 | /* |
268 | * get ieee prev rate from rate scale table. | |
269 | * for A and B mode we need to overright prev | |
270 | * value | |
271 | */ | |
4a8a4322 | 272 | int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate) |
e6a9854b JB |
273 | { |
274 | int next_rate = iwl3945_get_prev_ieee_rate(rate); | |
275 | ||
276 | switch (priv->band) { | |
277 | case IEEE80211_BAND_5GHZ: | |
278 | if (rate == IWL_RATE_12M_INDEX) | |
279 | next_rate = IWL_RATE_9M_INDEX; | |
280 | else if (rate == IWL_RATE_6M_INDEX) | |
281 | next_rate = IWL_RATE_6M_INDEX; | |
282 | break; | |
7262796a AM |
283 | case IEEE80211_BAND_2GHZ: |
284 | if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) && | |
285 | iwl3945_is_associated(priv)) { | |
286 | if (rate == IWL_RATE_11M_INDEX) | |
287 | next_rate = IWL_RATE_5M_INDEX; | |
288 | } | |
e6a9854b | 289 | break; |
7262796a | 290 | |
e6a9854b JB |
291 | default: |
292 | break; | |
293 | } | |
294 | ||
295 | return next_rate; | |
296 | } | |
297 | ||
91c066f2 TW |
298 | |
299 | /** | |
300 | * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd | |
301 | * | |
302 | * When FW advances 'R' index, all entries between old and new 'R' index | |
303 | * need to be reclaimed. As result, some free space forms. If there is | |
304 | * enough free space (> low mark), wake the stack that feeds us. | |
305 | */ | |
4a8a4322 | 306 | static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv, |
91c066f2 TW |
307 | int txq_id, int index) |
308 | { | |
188cf6c7 | 309 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; |
d20b3c65 | 310 | struct iwl_queue *q = &txq->q; |
dbb6654c | 311 | struct iwl_tx_info *tx_info; |
91c066f2 TW |
312 | |
313 | BUG_ON(txq_id == IWL_CMD_QUEUE_NUM); | |
314 | ||
315 | for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index; | |
316 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
317 | ||
318 | tx_info = &txq->txb[txq->q.read_ptr]; | |
e039fa4a | 319 | ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]); |
91c066f2 | 320 | tx_info->skb[0] = NULL; |
7aaa1d79 | 321 | priv->cfg->ops->lib->txq_free_tfd(priv, txq); |
91c066f2 TW |
322 | } |
323 | ||
d20b3c65 | 324 | if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) && |
91c066f2 TW |
325 | (txq_id != IWL_CMD_QUEUE_NUM) && |
326 | priv->mac80211_registered) | |
327 | ieee80211_wake_queue(priv->hw, txq_id); | |
328 | } | |
329 | ||
330 | /** | |
331 | * iwl3945_rx_reply_tx - Handle Tx response | |
332 | */ | |
4a8a4322 | 333 | static void iwl3945_rx_reply_tx(struct iwl_priv *priv, |
6100b588 | 334 | struct iwl_rx_mem_buffer *rxb) |
91c066f2 | 335 | { |
3d24a9f7 | 336 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
91c066f2 TW |
337 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
338 | int txq_id = SEQ_TO_QUEUE(sequence); | |
339 | int index = SEQ_TO_INDEX(sequence); | |
188cf6c7 | 340 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; |
e039fa4a | 341 | struct ieee80211_tx_info *info; |
91c066f2 TW |
342 | struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; |
343 | u32 status = le32_to_cpu(tx_resp->status); | |
344 | int rate_idx; | |
74221d07 | 345 | int fail; |
91c066f2 | 346 | |
625a381a | 347 | if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { |
15b1687c | 348 | IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d " |
91c066f2 TW |
349 | "is out of range [0-%d] %d %d\n", txq_id, |
350 | index, txq->q.n_bd, txq->q.write_ptr, | |
351 | txq->q.read_ptr); | |
352 | return; | |
353 | } | |
354 | ||
e039fa4a | 355 | info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); |
e6a9854b JB |
356 | ieee80211_tx_info_clear_status(info); |
357 | ||
358 | /* Fill the MRR chain with some info about on-chip retransmissions */ | |
359 | rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate); | |
360 | if (info->band == IEEE80211_BAND_5GHZ) | |
361 | rate_idx -= IWL_FIRST_OFDM_RATE; | |
362 | ||
363 | fail = tx_resp->failure_frame; | |
74221d07 AM |
364 | |
365 | info->status.rates[0].idx = rate_idx; | |
366 | info->status.rates[0].count = fail + 1; /* add final attempt */ | |
91c066f2 | 367 | |
91c066f2 | 368 | /* tx_status->rts_retry_count = tx_resp->failure_rts; */ |
e039fa4a JB |
369 | info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ? |
370 | IEEE80211_TX_STAT_ACK : 0; | |
91c066f2 TW |
371 | |
372 | IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n", | |
373 | txq_id, iwl3945_get_tx_fail_reason(status), status, | |
374 | tx_resp->rate, tx_resp->failure_frame); | |
375 | ||
91c066f2 TW |
376 | IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index); |
377 | iwl3945_tx_queue_reclaim(priv, txq_id, index); | |
378 | ||
379 | if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) | |
15b1687c | 380 | IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n"); |
91c066f2 TW |
381 | } |
382 | ||
383 | ||
384 | ||
b481de9c ZY |
385 | /***************************************************************************** |
386 | * | |
387 | * Intel PRO/Wireless 3945ABG/BG Network Connection | |
388 | * | |
389 | * RX handler implementations | |
390 | * | |
b481de9c ZY |
391 | *****************************************************************************/ |
392 | ||
4a8a4322 | 393 | void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) |
b481de9c | 394 | { |
3d24a9f7 | 395 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c | 396 | IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n", |
bb8c093b | 397 | (int)sizeof(struct iwl3945_notif_statistics), |
b481de9c ZY |
398 | le32_to_cpu(pkt->len)); |
399 | ||
f2c7e521 | 400 | memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39)); |
b481de9c | 401 | |
ab53d8af MA |
402 | iwl3945_led_background(priv); |
403 | ||
b481de9c ZY |
404 | priv->last_statistics_time = jiffies; |
405 | } | |
406 | ||
17744ff6 TW |
407 | /****************************************************************************** |
408 | * | |
409 | * Misc. internal state and helper functions | |
410 | * | |
411 | ******************************************************************************/ | |
412 | #ifdef CONFIG_IWL3945_DEBUG | |
413 | ||
414 | /** | |
415 | * iwl3945_report_frame - dump frame to syslog during debug sessions | |
416 | * | |
417 | * You may hack this function to show different aspects of received frames, | |
418 | * including selective frame dumps. | |
419 | * group100 parameter selects whether to show 1 out of 100 good frames. | |
420 | */ | |
4a8a4322 | 421 | static void iwl3945_dbg_report_frame(struct iwl_priv *priv, |
3d24a9f7 | 422 | struct iwl_rx_packet *pkt, |
17744ff6 TW |
423 | struct ieee80211_hdr *header, int group100) |
424 | { | |
425 | u32 to_us; | |
426 | u32 print_summary = 0; | |
427 | u32 print_dump = 0; /* set to 1 to dump all frames' contents */ | |
428 | u32 hundred = 0; | |
429 | u32 dataframe = 0; | |
fd7c8a40 | 430 | __le16 fc; |
17744ff6 TW |
431 | u16 seq_ctl; |
432 | u16 channel; | |
433 | u16 phy_flags; | |
434 | u16 length; | |
435 | u16 status; | |
436 | u16 bcn_tmr; | |
437 | u32 tsf_low; | |
438 | u64 tsf; | |
439 | u8 rssi; | |
440 | u8 agc; | |
441 | u16 sig_avg; | |
442 | u16 noise_diff; | |
443 | struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt); | |
444 | struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt); | |
445 | struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt); | |
446 | u8 *data = IWL_RX_DATA(pkt); | |
447 | ||
448 | /* MAC header */ | |
fd7c8a40 | 449 | fc = header->frame_control; |
17744ff6 TW |
450 | seq_ctl = le16_to_cpu(header->seq_ctrl); |
451 | ||
452 | /* metadata */ | |
453 | channel = le16_to_cpu(rx_hdr->channel); | |
454 | phy_flags = le16_to_cpu(rx_hdr->phy_flags); | |
455 | length = le16_to_cpu(rx_hdr->len); | |
456 | ||
457 | /* end-of-frame status and timestamp */ | |
458 | status = le32_to_cpu(rx_end->status); | |
459 | bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp); | |
460 | tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff; | |
461 | tsf = le64_to_cpu(rx_end->timestamp); | |
462 | ||
463 | /* signal statistics */ | |
464 | rssi = rx_stats->rssi; | |
465 | agc = rx_stats->agc; | |
466 | sig_avg = le16_to_cpu(rx_stats->sig_avg); | |
467 | noise_diff = le16_to_cpu(rx_stats->noise_diff); | |
468 | ||
469 | to_us = !compare_ether_addr(header->addr1, priv->mac_addr); | |
470 | ||
471 | /* if data frame is to us and all is good, | |
472 | * (optionally) print summary for only 1 out of every 100 */ | |
fd7c8a40 HH |
473 | if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) == |
474 | cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) { | |
17744ff6 TW |
475 | dataframe = 1; |
476 | if (!group100) | |
477 | print_summary = 1; /* print each frame */ | |
478 | else if (priv->framecnt_to_us < 100) { | |
479 | priv->framecnt_to_us++; | |
480 | print_summary = 0; | |
481 | } else { | |
482 | priv->framecnt_to_us = 0; | |
483 | print_summary = 1; | |
484 | hundred = 1; | |
485 | } | |
486 | } else { | |
487 | /* print summary for all other frames */ | |
488 | print_summary = 1; | |
489 | } | |
490 | ||
491 | if (print_summary) { | |
492 | char *title; | |
0ff1cca0 | 493 | int rate; |
17744ff6 TW |
494 | |
495 | if (hundred) | |
496 | title = "100Frames"; | |
fd7c8a40 | 497 | else if (ieee80211_has_retry(fc)) |
17744ff6 | 498 | title = "Retry"; |
fd7c8a40 | 499 | else if (ieee80211_is_assoc_resp(fc)) |
17744ff6 | 500 | title = "AscRsp"; |
fd7c8a40 | 501 | else if (ieee80211_is_reassoc_resp(fc)) |
17744ff6 | 502 | title = "RasRsp"; |
fd7c8a40 | 503 | else if (ieee80211_is_probe_resp(fc)) { |
17744ff6 TW |
504 | title = "PrbRsp"; |
505 | print_dump = 1; /* dump frame contents */ | |
506 | } else if (ieee80211_is_beacon(fc)) { | |
507 | title = "Beacon"; | |
508 | print_dump = 1; /* dump frame contents */ | |
509 | } else if (ieee80211_is_atim(fc)) | |
510 | title = "ATIM"; | |
511 | else if (ieee80211_is_auth(fc)) | |
512 | title = "Auth"; | |
513 | else if (ieee80211_is_deauth(fc)) | |
514 | title = "DeAuth"; | |
515 | else if (ieee80211_is_disassoc(fc)) | |
516 | title = "DisAssoc"; | |
517 | else | |
518 | title = "Frame"; | |
519 | ||
520 | rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate); | |
521 | if (rate == -1) | |
522 | rate = 0; | |
523 | else | |
524 | rate = iwl3945_rates[rate].ieee / 2; | |
525 | ||
526 | /* print frame summary. | |
527 | * MAC addresses show just the last byte (for brevity), | |
528 | * but you can hack it to show more, if you'd like to. */ | |
529 | if (dataframe) | |
530 | IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, " | |
0ff1cca0 | 531 | "len=%u, rssi=%d, chnl=%d, rate=%d, \n", |
fd7c8a40 | 532 | title, le16_to_cpu(fc), header->addr1[5], |
17744ff6 TW |
533 | length, rssi, channel, rate); |
534 | else { | |
535 | /* src/dst addresses assume managed mode */ | |
536 | IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, " | |
537 | "src=0x%02x, rssi=%u, tim=%lu usec, " | |
538 | "phy=0x%02x, chnl=%d\n", | |
fd7c8a40 | 539 | title, le16_to_cpu(fc), header->addr1[5], |
17744ff6 TW |
540 | header->addr3[5], rssi, |
541 | tsf_low - priv->scan_start_tsf, | |
542 | phy_flags, channel); | |
543 | } | |
544 | } | |
545 | if (print_dump) | |
40b8ec0b | 546 | iwl_print_hex_dump(priv, IWL_DL_RX, data, length); |
17744ff6 TW |
547 | } |
548 | #else | |
4a8a4322 | 549 | static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv, |
3d24a9f7 | 550 | struct iwl_rx_packet *pkt, |
17744ff6 TW |
551 | struct ieee80211_hdr *header, int group100) |
552 | { | |
553 | } | |
554 | #endif | |
555 | ||
4bd9b4f3 | 556 | /* This is necessary only for a number of statistics, see the caller. */ |
4a8a4322 | 557 | static int iwl3945_is_network_packet(struct iwl_priv *priv, |
4bd9b4f3 AG |
558 | struct ieee80211_hdr *header) |
559 | { | |
560 | /* Filter incoming packets to determine if they are targeted toward | |
561 | * this network, discarding packets coming from ourselves */ | |
562 | switch (priv->iw_mode) { | |
05c914fe | 563 | case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */ |
4bd9b4f3 AG |
564 | /* packets to our IBSS update information */ |
565 | return !compare_ether_addr(header->addr3, priv->bssid); | |
05c914fe | 566 | case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */ |
4bd9b4f3 AG |
567 | /* packets to our IBSS update information */ |
568 | return !compare_ether_addr(header->addr2, priv->bssid); | |
569 | default: | |
570 | return 1; | |
571 | } | |
572 | } | |
17744ff6 | 573 | |
4a8a4322 | 574 | static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv, |
6100b588 | 575 | struct iwl_rx_mem_buffer *rxb, |
12342c47 | 576 | struct ieee80211_rx_status *stats) |
b481de9c | 577 | { |
3d24a9f7 | 578 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; |
699669f3 | 579 | #ifdef CONFIG_IWL3945_LEDS |
4bd9b4f3 | 580 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt); |
699669f3 | 581 | #endif |
bb8c093b CH |
582 | struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt); |
583 | struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt); | |
b481de9c ZY |
584 | short len = le16_to_cpu(rx_hdr->len); |
585 | ||
586 | /* We received data from the HW, so stop the watchdog */ | |
3d24a9f7 | 587 | if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) { |
b481de9c ZY |
588 | IWL_DEBUG_DROP("Corruption detected!\n"); |
589 | return; | |
590 | } | |
591 | ||
592 | /* We only process data packets if the interface is open */ | |
593 | if (unlikely(!priv->is_open)) { | |
594 | IWL_DEBUG_DROP_LIMIT | |
595 | ("Dropping packet while interface is not open.\n"); | |
596 | return; | |
597 | } | |
b481de9c ZY |
598 | |
599 | skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt); | |
600 | /* Set the size of the skb to the size of the frame */ | |
601 | skb_put(rxb->skb, le16_to_cpu(rx_hdr->len)); | |
602 | ||
9c74d9fb | 603 | if (!iwl3945_mod_params.sw_crypto) |
bb8c093b | 604 | iwl3945_set_decrypted_flag(priv, rxb->skb, |
b481de9c ZY |
605 | le32_to_cpu(rx_end->status), stats); |
606 | ||
ab53d8af | 607 | #ifdef CONFIG_IWL3945_LEDS |
4bd9b4f3 | 608 | if (ieee80211_is_data(hdr->frame_control)) |
ab53d8af MA |
609 | priv->rxtxpackets += len; |
610 | #endif | |
b481de9c ZY |
611 | ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats); |
612 | rxb->skb = NULL; | |
613 | } | |
614 | ||
7878a5a4 MA |
615 | #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) |
616 | ||
4a8a4322 | 617 | static void iwl3945_rx_reply_rx(struct iwl_priv *priv, |
6100b588 | 618 | struct iwl_rx_mem_buffer *rxb) |
b481de9c | 619 | { |
17744ff6 TW |
620 | struct ieee80211_hdr *header; |
621 | struct ieee80211_rx_status rx_status; | |
3d24a9f7 | 622 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; |
bb8c093b CH |
623 | struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt); |
624 | struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt); | |
625 | struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt); | |
17744ff6 | 626 | int snr; |
b481de9c ZY |
627 | u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg); |
628 | u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff); | |
b481de9c | 629 | u8 network_packet; |
17744ff6 | 630 | |
17744ff6 TW |
631 | rx_status.flag = 0; |
632 | rx_status.mactime = le64_to_cpu(rx_end->timestamp); | |
dc92e497 | 633 | rx_status.freq = |
c0186078 | 634 | ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel)); |
17744ff6 TW |
635 | rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? |
636 | IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; | |
637 | ||
638 | rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate); | |
17744ff6 TW |
639 | if (rx_status.band == IEEE80211_BAND_5GHZ) |
640 | rx_status.rate_idx -= IWL_FIRST_OFDM_RATE; | |
b481de9c | 641 | |
6f0a2c4d BR |
642 | rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags & |
643 | RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4; | |
644 | ||
645 | /* set the preamble flag if appropriate */ | |
646 | if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK) | |
647 | rx_status.flag |= RX_FLAG_SHORTPRE; | |
648 | ||
b481de9c ZY |
649 | if ((unlikely(rx_stats->phy_count > 20))) { |
650 | IWL_DEBUG_DROP | |
651 | ("dsp size out of range [0,20]: " | |
652 | "%d/n", rx_stats->phy_count); | |
653 | return; | |
654 | } | |
655 | ||
656 | if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR) | |
657 | || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) { | |
658 | IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status); | |
659 | return; | |
660 | } | |
661 | ||
56decd3c | 662 | |
b481de9c ZY |
663 | |
664 | /* Convert 3945's rssi indicator to dBm */ | |
250bdd21 | 665 | rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET; |
b481de9c ZY |
666 | |
667 | /* Set default noise value to -127 */ | |
668 | if (priv->last_rx_noise == 0) | |
669 | priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
670 | ||
671 | /* 3945 provides noise info for OFDM frames only. | |
672 | * sig_avg and noise_diff are measured by the 3945's digital signal | |
673 | * processor (DSP), and indicate linear levels of signal level and | |
674 | * distortion/noise within the packet preamble after | |
675 | * automatic gain control (AGC). sig_avg should stay fairly | |
676 | * constant if the radio's AGC is working well. | |
677 | * Since these values are linear (not dB or dBm), linear | |
678 | * signal-to-noise ratio (SNR) is (sig_avg / noise_diff). | |
679 | * Convert linear SNR to dB SNR, then subtract that from rssi dBm | |
680 | * to obtain noise level in dBm. | |
17744ff6 | 681 | * Calculate rx_status.signal (quality indicator in %) based on SNR. */ |
b481de9c ZY |
682 | if (rx_stats_noise_diff) { |
683 | snr = rx_stats_sig_avg / rx_stats_noise_diff; | |
566bfe5a | 684 | rx_status.noise = rx_status.signal - |
17744ff6 | 685 | iwl3945_calc_db_from_ratio(snr); |
566bfe5a | 686 | rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, |
17744ff6 | 687 | rx_status.noise); |
b481de9c ZY |
688 | |
689 | /* If noise info not available, calculate signal quality indicator (%) | |
690 | * using just the dBm signal level. */ | |
691 | } else { | |
17744ff6 | 692 | rx_status.noise = priv->last_rx_noise; |
566bfe5a | 693 | rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0); |
b481de9c ZY |
694 | } |
695 | ||
696 | ||
697 | IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n", | |
566bfe5a | 698 | rx_status.signal, rx_status.noise, rx_status.qual, |
b481de9c ZY |
699 | rx_stats_sig_avg, rx_stats_noise_diff); |
700 | ||
b481de9c ZY |
701 | header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt); |
702 | ||
bb8c093b | 703 | network_packet = iwl3945_is_network_packet(priv, header); |
b481de9c | 704 | |
17744ff6 TW |
705 | IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n", |
706 | network_packet ? '*' : ' ', | |
707 | le16_to_cpu(rx_hdr->channel), | |
566bfe5a BR |
708 | rx_status.signal, rx_status.signal, |
709 | rx_status.noise, rx_status.rate_idx); | |
b481de9c | 710 | |
17744ff6 | 711 | #ifdef CONFIG_IWL3945_DEBUG |
40b8ec0b | 712 | if (priv->debug_level & (IWL_DL_RX)) |
b481de9c | 713 | /* Set "1" to report good data frames in groups of 100 */ |
17744ff6 | 714 | iwl3945_dbg_report_frame(priv, pkt, header, 1); |
b481de9c ZY |
715 | #endif |
716 | ||
717 | if (network_packet) { | |
718 | priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp); | |
719 | priv->last_tsf = le64_to_cpu(rx_end->timestamp); | |
566bfe5a | 720 | priv->last_rx_rssi = rx_status.signal; |
17744ff6 | 721 | priv->last_rx_noise = rx_status.noise; |
b481de9c ZY |
722 | } |
723 | ||
12e5e22d | 724 | iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status); |
b481de9c ZY |
725 | } |
726 | ||
7aaa1d79 SO |
727 | int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, |
728 | struct iwl_tx_queue *txq, | |
729 | dma_addr_t addr, u16 len, u8 reset, u8 pad) | |
b481de9c ZY |
730 | { |
731 | int count; | |
7aaa1d79 | 732 | struct iwl_queue *q; |
59606ffa | 733 | struct iwl3945_tfd *tfd, *tfd_tmp; |
7aaa1d79 SO |
734 | |
735 | q = &txq->q; | |
59606ffa SO |
736 | tfd_tmp = (struct iwl3945_tfd *)txq->tfds; |
737 | tfd = &tfd_tmp[q->write_ptr]; | |
7aaa1d79 SO |
738 | |
739 | if (reset) | |
740 | memset(tfd, 0, sizeof(*tfd)); | |
b481de9c ZY |
741 | |
742 | count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags)); | |
b481de9c ZY |
743 | |
744 | if ((count >= NUM_TFD_CHUNKS) || (count < 0)) { | |
15b1687c | 745 | IWL_ERR(priv, "Error can not send more than %d chunks\n", |
b481de9c ZY |
746 | NUM_TFD_CHUNKS); |
747 | return -EINVAL; | |
748 | } | |
749 | ||
dbb6654c WT |
750 | tfd->tbs[count].addr = cpu_to_le32(addr); |
751 | tfd->tbs[count].len = cpu_to_le32(len); | |
b481de9c ZY |
752 | |
753 | count++; | |
754 | ||
755 | tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) | | |
756 | TFD_CTL_PAD_SET(pad)); | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
761 | /** | |
bb8c093b | 762 | * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr] |
b481de9c ZY |
763 | * |
764 | * Does NOT advance any indexes | |
765 | */ | |
7aaa1d79 | 766 | void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
b481de9c | 767 | { |
59606ffa | 768 | struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds; |
dbb6654c | 769 | struct iwl3945_tfd *tfd = &tfd_tmp[txq->q.read_ptr]; |
b481de9c ZY |
770 | struct pci_dev *dev = priv->pci_dev; |
771 | int i; | |
772 | int counter; | |
773 | ||
774 | /* classify bd */ | |
775 | if (txq->q.id == IWL_CMD_QUEUE_NUM) | |
776 | /* nothing to cleanup after for host commands */ | |
7aaa1d79 | 777 | return; |
b481de9c ZY |
778 | |
779 | /* sanity check */ | |
dbb6654c | 780 | counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags)); |
b481de9c | 781 | if (counter > NUM_TFD_CHUNKS) { |
15b1687c | 782 | IWL_ERR(priv, "Too many chunks: %i\n", counter); |
b481de9c | 783 | /* @todo issue fatal error, it is quite serious situation */ |
7aaa1d79 | 784 | return; |
b481de9c ZY |
785 | } |
786 | ||
787 | /* unmap chunks if any */ | |
788 | ||
789 | for (i = 1; i < counter; i++) { | |
dbb6654c WT |
790 | pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr), |
791 | le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE); | |
fc4b6853 TW |
792 | if (txq->txb[txq->q.read_ptr].skb[0]) { |
793 | struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0]; | |
794 | if (txq->txb[txq->q.read_ptr].skb[0]) { | |
b481de9c ZY |
795 | /* Can be called from interrupt context */ |
796 | dev_kfree_skb_any(skb); | |
fc4b6853 | 797 | txq->txb[txq->q.read_ptr].skb[0] = NULL; |
b481de9c ZY |
798 | } |
799 | } | |
800 | } | |
7aaa1d79 | 801 | return ; |
b481de9c ZY |
802 | } |
803 | ||
4a8a4322 | 804 | u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr) |
b481de9c | 805 | { |
c93007ef | 806 | int i, start = IWL_AP_ID; |
b481de9c ZY |
807 | int ret = IWL_INVALID_STATION; |
808 | unsigned long flags; | |
809 | ||
c93007ef SO |
810 | if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) || |
811 | (priv->iw_mode == NL80211_IFTYPE_AP)) | |
812 | start = IWL_STA_ID; | |
813 | ||
814 | if (is_broadcast_ether_addr(addr)) | |
3832ec9d | 815 | return priv->hw_params.bcast_sta_id; |
c93007ef | 816 | |
b481de9c | 817 | spin_lock_irqsave(&priv->sta_lock, flags); |
3832ec9d | 818 | for (i = start; i < priv->hw_params.max_stations; i++) |
f2c7e521 | 819 | if ((priv->stations_39[i].used) && |
b481de9c | 820 | (!compare_ether_addr |
f2c7e521 | 821 | (priv->stations_39[i].sta.sta.addr, addr))) { |
b481de9c ZY |
822 | ret = i; |
823 | goto out; | |
824 | } | |
825 | ||
e174961c JB |
826 | IWL_DEBUG_INFO("can not find STA %pM (total %d)\n", |
827 | addr, priv->num_stations); | |
b481de9c ZY |
828 | out: |
829 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
830 | return ret; | |
831 | } | |
832 | ||
833 | /** | |
bb8c093b | 834 | * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD: |
b481de9c ZY |
835 | * |
836 | */ | |
c2d79b48 | 837 | void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd, |
e039fa4a | 838 | struct ieee80211_tx_info *info, |
b481de9c ZY |
839 | struct ieee80211_hdr *hdr, int sta_id, int tx_id) |
840 | { | |
e039fa4a | 841 | u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value; |
2e92e6f2 | 842 | u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1); |
b481de9c ZY |
843 | u16 rate_mask; |
844 | int rate; | |
845 | u8 rts_retry_limit; | |
846 | u8 data_retry_limit; | |
847 | __le32 tx_flags; | |
fd7c8a40 | 848 | __le16 fc = hdr->frame_control; |
c2d79b48 | 849 | struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload; |
b481de9c | 850 | |
bb8c093b | 851 | rate = iwl3945_rates[rate_index].plcp; |
c2d79b48 | 852 | tx_flags = tx->tx_flags; |
b481de9c ZY |
853 | |
854 | /* We need to figure out how to get the sta->supp_rates while | |
e039fa4a | 855 | * in this running context */ |
b481de9c ZY |
856 | rate_mask = IWL_RATES_MASK; |
857 | ||
b481de9c ZY |
858 | if (tx_id >= IWL_CMD_QUEUE_NUM) |
859 | rts_retry_limit = 3; | |
860 | else | |
861 | rts_retry_limit = 7; | |
862 | ||
fd7c8a40 | 863 | if (ieee80211_is_probe_resp(fc)) { |
b481de9c ZY |
864 | data_retry_limit = 3; |
865 | if (data_retry_limit < rts_retry_limit) | |
866 | rts_retry_limit = data_retry_limit; | |
867 | } else | |
868 | data_retry_limit = IWL_DEFAULT_TX_RETRY; | |
869 | ||
870 | if (priv->data_retry_limit != -1) | |
871 | data_retry_limit = priv->data_retry_limit; | |
872 | ||
fd7c8a40 HH |
873 | if (ieee80211_is_mgmt(fc)) { |
874 | switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) { | |
875 | case cpu_to_le16(IEEE80211_STYPE_AUTH): | |
876 | case cpu_to_le16(IEEE80211_STYPE_DEAUTH): | |
877 | case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ): | |
878 | case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ): | |
b481de9c ZY |
879 | if (tx_flags & TX_CMD_FLG_RTS_MSK) { |
880 | tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
881 | tx_flags |= TX_CMD_FLG_CTS_MSK; | |
882 | } | |
883 | break; | |
884 | default: | |
885 | break; | |
886 | } | |
887 | } | |
888 | ||
c2d79b48 WT |
889 | tx->rts_retry_limit = rts_retry_limit; |
890 | tx->data_retry_limit = data_retry_limit; | |
891 | tx->rate = rate; | |
892 | tx->tx_flags = tx_flags; | |
b481de9c ZY |
893 | |
894 | /* OFDM */ | |
c2d79b48 | 895 | tx->supp_rates[0] = |
14577f23 | 896 | ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF; |
b481de9c ZY |
897 | |
898 | /* CCK */ | |
c2d79b48 | 899 | tx->supp_rates[1] = (rate_mask & 0xF); |
b481de9c ZY |
900 | |
901 | IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X " | |
902 | "cck/ofdm mask: 0x%x/0x%x\n", sta_id, | |
c2d79b48 WT |
903 | tx->rate, le32_to_cpu(tx->tx_flags), |
904 | tx->supp_rates[1], tx->supp_rates[0]); | |
b481de9c ZY |
905 | } |
906 | ||
4a8a4322 | 907 | u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags) |
b481de9c ZY |
908 | { |
909 | unsigned long flags_spin; | |
bb8c093b | 910 | struct iwl3945_station_entry *station; |
b481de9c ZY |
911 | |
912 | if (sta_id == IWL_INVALID_STATION) | |
913 | return IWL_INVALID_STATION; | |
914 | ||
915 | spin_lock_irqsave(&priv->sta_lock, flags_spin); | |
f2c7e521 | 916 | station = &priv->stations_39[sta_id]; |
b481de9c ZY |
917 | |
918 | station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK; | |
919 | station->sta.rate_n_flags = cpu_to_le16(tx_rate); | |
b481de9c ZY |
920 | station->sta.mode = STA_CONTROL_MODIFY_MSK; |
921 | ||
922 | spin_unlock_irqrestore(&priv->sta_lock, flags_spin); | |
923 | ||
bb8c093b | 924 | iwl3945_send_add_station(priv, &station->sta, flags); |
b481de9c ZY |
925 | IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n", |
926 | sta_id, tx_rate); | |
927 | return sta_id; | |
928 | } | |
929 | ||
854682ed | 930 | static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) |
b481de9c ZY |
931 | { |
932 | int rc; | |
933 | unsigned long flags; | |
934 | ||
935 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 | 936 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
937 | if (rc) { |
938 | spin_unlock_irqrestore(&priv->lock, flags); | |
939 | return rc; | |
940 | } | |
941 | ||
854682ed | 942 | if (src == IWL_PWR_SRC_VAUX) { |
b481de9c ZY |
943 | u32 val; |
944 | ||
945 | rc = pci_read_config_dword(priv->pci_dev, | |
946 | PCI_POWER_SOURCE, &val); | |
947 | if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) { | |
5d49f498 | 948 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
b481de9c ZY |
949 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, |
950 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
5d49f498 | 951 | iwl_release_nic_access(priv); |
b481de9c | 952 | |
5d49f498 | 953 | iwl_poll_bit(priv, CSR_GPIO_IN, |
b481de9c ZY |
954 | CSR_GPIO_IN_VAL_VAUX_PWR_SRC, |
955 | CSR_GPIO_IN_BIT_AUX_POWER, 5000); | |
956 | } else | |
5d49f498 | 957 | iwl_release_nic_access(priv); |
b481de9c | 958 | } else { |
5d49f498 | 959 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
b481de9c ZY |
960 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, |
961 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
962 | ||
5d49f498 AK |
963 | iwl_release_nic_access(priv); |
964 | iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC, | |
b481de9c ZY |
965 | CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */ |
966 | } | |
967 | spin_unlock_irqrestore(&priv->lock, flags); | |
968 | ||
969 | return rc; | |
970 | } | |
971 | ||
4a8a4322 | 972 | static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq) |
b481de9c ZY |
973 | { |
974 | int rc; | |
975 | unsigned long flags; | |
976 | ||
977 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 | 978 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
979 | if (rc) { |
980 | spin_unlock_irqrestore(&priv->lock, flags); | |
981 | return rc; | |
982 | } | |
983 | ||
5d49f498 | 984 | iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr); |
8cd812bc | 985 | iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma); |
5d49f498 AK |
986 | iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0); |
987 | iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), | |
bddadf86 TW |
988 | FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE | |
989 | FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE | | |
990 | FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN | | |
991 | FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 | | |
992 | (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) | | |
993 | FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST | | |
994 | (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) | | |
995 | FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH); | |
b481de9c ZY |
996 | |
997 | /* fake read to flush all prev I/O */ | |
5d49f498 | 998 | iwl_read_direct32(priv, FH39_RSSR_CTRL); |
b481de9c | 999 | |
5d49f498 | 1000 | iwl_release_nic_access(priv); |
b481de9c ZY |
1001 | spin_unlock_irqrestore(&priv->lock, flags); |
1002 | ||
1003 | return 0; | |
1004 | } | |
1005 | ||
4a8a4322 | 1006 | static int iwl3945_tx_reset(struct iwl_priv *priv) |
b481de9c ZY |
1007 | { |
1008 | int rc; | |
1009 | unsigned long flags; | |
1010 | ||
1011 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 | 1012 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
1013 | if (rc) { |
1014 | spin_unlock_irqrestore(&priv->lock, flags); | |
1015 | return rc; | |
1016 | } | |
1017 | ||
1018 | /* bypass mode */ | |
5d49f498 | 1019 | iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2); |
b481de9c ZY |
1020 | |
1021 | /* RA 0 is active */ | |
5d49f498 | 1022 | iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01); |
b481de9c ZY |
1023 | |
1024 | /* all 6 fifo are active */ | |
5d49f498 | 1025 | iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f); |
b481de9c | 1026 | |
5d49f498 AK |
1027 | iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000); |
1028 | iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002); | |
1029 | iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004); | |
1030 | iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005); | |
b481de9c | 1031 | |
5d49f498 | 1032 | iwl_write_direct32(priv, FH39_TSSR_CBB_BASE, |
3832ec9d | 1033 | priv->shared_phys); |
b481de9c | 1034 | |
5d49f498 | 1035 | iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG, |
bddadf86 TW |
1036 | FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON | |
1037 | FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON | | |
1038 | FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B | | |
1039 | FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON | | |
1040 | FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON | | |
1041 | FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH | | |
1042 | FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH); | |
b481de9c | 1043 | |
5d49f498 | 1044 | iwl_release_nic_access(priv); |
b481de9c ZY |
1045 | spin_unlock_irqrestore(&priv->lock, flags); |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | /** | |
1051 | * iwl3945_txq_ctx_reset - Reset TX queue context | |
1052 | * | |
1053 | * Destroys all DMA structures and initialize them again | |
1054 | */ | |
4a8a4322 | 1055 | static int iwl3945_txq_ctx_reset(struct iwl_priv *priv) |
b481de9c ZY |
1056 | { |
1057 | int rc; | |
1058 | int txq_id, slots_num; | |
1059 | ||
bb8c093b | 1060 | iwl3945_hw_txq_ctx_free(priv); |
b481de9c ZY |
1061 | |
1062 | /* Tx CMD queue */ | |
1063 | rc = iwl3945_tx_reset(priv); | |
1064 | if (rc) | |
1065 | goto error; | |
1066 | ||
1067 | /* Tx queue(s) */ | |
1068 | for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) { | |
1069 | slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? | |
1070 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
188cf6c7 | 1071 | rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num, |
b481de9c ZY |
1072 | txq_id); |
1073 | if (rc) { | |
15b1687c | 1074 | IWL_ERR(priv, "Tx %d queue init failed\n", txq_id); |
b481de9c ZY |
1075 | goto error; |
1076 | } | |
1077 | } | |
1078 | ||
1079 | return rc; | |
1080 | ||
1081 | error: | |
bb8c093b | 1082 | iwl3945_hw_txq_ctx_free(priv); |
b481de9c ZY |
1083 | return rc; |
1084 | } | |
1085 | ||
01ec616d | 1086 | static int iwl3945_apm_init(struct iwl_priv *priv) |
b481de9c | 1087 | { |
01ec616d | 1088 | int ret = 0; |
b481de9c | 1089 | |
bb8c093b | 1090 | iwl3945_power_init_handle(priv); |
b481de9c | 1091 | |
5d49f498 | 1092 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, |
01ec616d KA |
1093 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
1094 | ||
1095 | /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */ | |
1096 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
1097 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | |
b481de9c | 1098 | |
01ec616d KA |
1099 | /* set "initialization complete" bit to move adapter |
1100 | * D0U* --> D0A* state */ | |
5d49f498 | 1101 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
01ec616d KA |
1102 | |
1103 | iwl_poll_direct_bit(priv, CSR_GP_CNTRL, | |
1104 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
1105 | if (ret < 0) { | |
b481de9c | 1106 | IWL_DEBUG_INFO("Failed to init the card\n"); |
01ec616d | 1107 | goto out; |
b481de9c ZY |
1108 | } |
1109 | ||
01ec616d KA |
1110 | ret = iwl_grab_nic_access(priv); |
1111 | if (ret) | |
1112 | goto out; | |
1113 | ||
1114 | /* enable DMA */ | |
1115 | iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT | | |
1116 | APMG_CLK_VAL_BSM_CLK_RQT); | |
1117 | ||
b481de9c | 1118 | udelay(20); |
01ec616d KA |
1119 | |
1120 | /* disable L1-Active */ | |
5d49f498 | 1121 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, |
01ec616d KA |
1122 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
1123 | ||
5d49f498 | 1124 | iwl_release_nic_access(priv); |
01ec616d KA |
1125 | out: |
1126 | return ret; | |
1127 | } | |
b481de9c | 1128 | |
01ec616d KA |
1129 | static void iwl3945_nic_config(struct iwl_priv *priv) |
1130 | { | |
1131 | unsigned long flags; | |
1132 | u8 rev_id = 0; | |
b481de9c | 1133 | |
b481de9c ZY |
1134 | spin_lock_irqsave(&priv->lock, flags); |
1135 | ||
1136 | if (rev_id & PCI_CFG_REV_ID_BIT_RTP) | |
1137 | IWL_DEBUG_INFO("RTP type \n"); | |
1138 | else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) { | |
6f83eaa1 | 1139 | IWL_DEBUG_INFO("3945 RADIO-MB type\n"); |
5d49f498 | 1140 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
6f83eaa1 | 1141 | CSR39_HW_IF_CONFIG_REG_BIT_3945_MB); |
b481de9c | 1142 | } else { |
6f83eaa1 | 1143 | IWL_DEBUG_INFO("3945 RADIO-MM type\n"); |
5d49f498 | 1144 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
6f83eaa1 | 1145 | CSR39_HW_IF_CONFIG_REG_BIT_3945_MM); |
b481de9c ZY |
1146 | } |
1147 | ||
f2c7e521 | 1148 | if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom39.sku_cap) { |
b481de9c | 1149 | IWL_DEBUG_INFO("SKU OP mode is mrc\n"); |
5d49f498 | 1150 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
6f83eaa1 | 1151 | CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC); |
b481de9c ZY |
1152 | } else |
1153 | IWL_DEBUG_INFO("SKU OP mode is basic\n"); | |
1154 | ||
f2c7e521 | 1155 | if ((priv->eeprom39.board_revision & 0xF0) == 0xD0) { |
b481de9c | 1156 | IWL_DEBUG_INFO("3945ABG revision is 0x%X\n", |
f2c7e521 | 1157 | priv->eeprom39.board_revision); |
5d49f498 | 1158 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
6f83eaa1 | 1159 | CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); |
b481de9c ZY |
1160 | } else { |
1161 | IWL_DEBUG_INFO("3945ABG revision is 0x%X\n", | |
f2c7e521 | 1162 | priv->eeprom39.board_revision); |
5d49f498 | 1163 | iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG, |
6f83eaa1 | 1164 | CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); |
b481de9c ZY |
1165 | } |
1166 | ||
f2c7e521 | 1167 | if (priv->eeprom39.almgor_m_version <= 1) { |
5d49f498 | 1168 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
6f83eaa1 | 1169 | CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A); |
b481de9c | 1170 | IWL_DEBUG_INFO("Card M type A version is 0x%X\n", |
f2c7e521 | 1171 | priv->eeprom39.almgor_m_version); |
b481de9c ZY |
1172 | } else { |
1173 | IWL_DEBUG_INFO("Card M type B version is 0x%X\n", | |
f2c7e521 | 1174 | priv->eeprom39.almgor_m_version); |
5d49f498 | 1175 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
6f83eaa1 | 1176 | CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B); |
b481de9c ZY |
1177 | } |
1178 | spin_unlock_irqrestore(&priv->lock, flags); | |
1179 | ||
f2c7e521 | 1180 | if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE) |
b481de9c ZY |
1181 | IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n"); |
1182 | ||
f2c7e521 | 1183 | if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE) |
b481de9c | 1184 | IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n"); |
01ec616d KA |
1185 | } |
1186 | ||
1187 | int iwl3945_hw_nic_init(struct iwl_priv *priv) | |
1188 | { | |
1189 | u8 rev_id; | |
1190 | int rc; | |
1191 | unsigned long flags; | |
1192 | struct iwl_rx_queue *rxq = &priv->rxq; | |
1193 | ||
1194 | spin_lock_irqsave(&priv->lock, flags); | |
1195 | priv->cfg->ops->lib->apm_ops.init(priv); | |
1196 | spin_unlock_irqrestore(&priv->lock, flags); | |
1197 | ||
1198 | /* Determine HW type */ | |
1199 | rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id); | |
1200 | if (rc) | |
1201 | return rc; | |
1202 | IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id); | |
1203 | ||
854682ed KA |
1204 | rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN); |
1205 | if(rc) | |
1206 | return rc; | |
1207 | ||
01ec616d | 1208 | priv->cfg->ops->lib->apm_ops.config(priv); |
b481de9c ZY |
1209 | |
1210 | /* Allocate the RX queue, or reset if it is already allocated */ | |
1211 | if (!rxq->bd) { | |
51af3d3f | 1212 | rc = iwl_rx_queue_alloc(priv); |
b481de9c | 1213 | if (rc) { |
15b1687c | 1214 | IWL_ERR(priv, "Unable to initialize Rx queue\n"); |
b481de9c ZY |
1215 | return -ENOMEM; |
1216 | } | |
1217 | } else | |
51af3d3f | 1218 | iwl_rx_queue_reset(priv, rxq); |
b481de9c | 1219 | |
bb8c093b | 1220 | iwl3945_rx_replenish(priv); |
b481de9c ZY |
1221 | |
1222 | iwl3945_rx_init(priv, rxq); | |
1223 | ||
1224 | spin_lock_irqsave(&priv->lock, flags); | |
1225 | ||
1226 | /* Look at using this instead: | |
1227 | rxq->need_update = 1; | |
141c43a3 | 1228 | iwl_rx_queue_update_write_ptr(priv, rxq); |
b481de9c ZY |
1229 | */ |
1230 | ||
5d49f498 | 1231 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
1232 | if (rc) { |
1233 | spin_unlock_irqrestore(&priv->lock, flags); | |
1234 | return rc; | |
1235 | } | |
5d49f498 AK |
1236 | iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7); |
1237 | iwl_release_nic_access(priv); | |
b481de9c ZY |
1238 | |
1239 | spin_unlock_irqrestore(&priv->lock, flags); | |
1240 | ||
1241 | rc = iwl3945_txq_ctx_reset(priv); | |
1242 | if (rc) | |
1243 | return rc; | |
1244 | ||
1245 | set_bit(STATUS_INIT, &priv->status); | |
1246 | ||
1247 | return 0; | |
1248 | } | |
1249 | ||
1250 | /** | |
bb8c093b | 1251 | * iwl3945_hw_txq_ctx_free - Free TXQ Context |
b481de9c ZY |
1252 | * |
1253 | * Destroy all TX DMA queues and structures | |
1254 | */ | |
4a8a4322 | 1255 | void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv) |
b481de9c ZY |
1256 | { |
1257 | int txq_id; | |
1258 | ||
1259 | /* Tx queues */ | |
1260 | for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) | |
188cf6c7 | 1261 | iwl3945_tx_queue_free(priv, &priv->txq[txq_id]); |
b481de9c ZY |
1262 | } |
1263 | ||
4a8a4322 | 1264 | void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv) |
b481de9c | 1265 | { |
bddadf86 | 1266 | int txq_id; |
b481de9c ZY |
1267 | unsigned long flags; |
1268 | ||
1269 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 | 1270 | if (iwl_grab_nic_access(priv)) { |
b481de9c | 1271 | spin_unlock_irqrestore(&priv->lock, flags); |
bb8c093b | 1272 | iwl3945_hw_txq_ctx_free(priv); |
b481de9c ZY |
1273 | return; |
1274 | } | |
1275 | ||
1276 | /* stop SCD */ | |
5d49f498 | 1277 | iwl_write_prph(priv, ALM_SCD_MODE_REG, 0); |
b481de9c ZY |
1278 | |
1279 | /* reset TFD queues */ | |
bddadf86 | 1280 | for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) { |
5d49f498 AK |
1281 | iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0); |
1282 | iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS, | |
bddadf86 | 1283 | FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id), |
b481de9c ZY |
1284 | 1000); |
1285 | } | |
1286 | ||
5d49f498 | 1287 | iwl_release_nic_access(priv); |
b481de9c ZY |
1288 | spin_unlock_irqrestore(&priv->lock, flags); |
1289 | ||
bb8c093b | 1290 | iwl3945_hw_txq_ctx_free(priv); |
b481de9c ZY |
1291 | } |
1292 | ||
01ec616d | 1293 | static int iwl3945_apm_stop_master(struct iwl_priv *priv) |
b481de9c | 1294 | { |
01ec616d | 1295 | int ret = 0; |
b481de9c ZY |
1296 | unsigned long flags; |
1297 | ||
1298 | spin_lock_irqsave(&priv->lock, flags); | |
1299 | ||
1300 | /* set stop master bit */ | |
5d49f498 | 1301 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); |
b481de9c | 1302 | |
01ec616d KA |
1303 | iwl_poll_direct_bit(priv, CSR_RESET, |
1304 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
b481de9c | 1305 | |
01ec616d KA |
1306 | if (ret < 0) |
1307 | goto out; | |
b481de9c | 1308 | |
01ec616d | 1309 | out: |
b481de9c ZY |
1310 | spin_unlock_irqrestore(&priv->lock, flags); |
1311 | IWL_DEBUG_INFO("stop master\n"); | |
1312 | ||
01ec616d KA |
1313 | return ret; |
1314 | } | |
1315 | ||
1316 | static void iwl3945_apm_stop(struct iwl_priv *priv) | |
1317 | { | |
1318 | unsigned long flags; | |
1319 | ||
1320 | iwl3945_apm_stop_master(priv); | |
1321 | ||
1322 | spin_lock_irqsave(&priv->lock, flags); | |
1323 | ||
1324 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
1325 | ||
1326 | udelay(10); | |
1327 | /* clear "init complete" move adapter D0A* --> D0U state */ | |
1328 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
1329 | spin_unlock_irqrestore(&priv->lock, flags); | |
b481de9c ZY |
1330 | } |
1331 | ||
e52119c5 | 1332 | static int iwl3945_apm_reset(struct iwl_priv *priv) |
b481de9c ZY |
1333 | { |
1334 | int rc; | |
1335 | unsigned long flags; | |
1336 | ||
01ec616d | 1337 | iwl3945_apm_stop_master(priv); |
b481de9c ZY |
1338 | |
1339 | spin_lock_irqsave(&priv->lock, flags); | |
1340 | ||
5d49f498 | 1341 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
e9414b6b AM |
1342 | udelay(10); |
1343 | ||
1344 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
b481de9c | 1345 | |
5d49f498 | 1346 | iwl_poll_direct_bit(priv, CSR_GP_CNTRL, |
73d7b5ac | 1347 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); |
b481de9c | 1348 | |
5d49f498 | 1349 | rc = iwl_grab_nic_access(priv); |
b481de9c | 1350 | if (!rc) { |
5d49f498 | 1351 | iwl_write_prph(priv, APMG_CLK_CTRL_REG, |
b481de9c ZY |
1352 | APMG_CLK_VAL_BSM_CLK_RQT); |
1353 | ||
5d49f498 AK |
1354 | iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0); |
1355 | iwl_write_prph(priv, APMG_RTC_INT_STT_REG, | |
b481de9c ZY |
1356 | 0xFFFFFFFF); |
1357 | ||
1358 | /* enable DMA */ | |
5d49f498 | 1359 | iwl_write_prph(priv, APMG_CLK_EN_REG, |
b481de9c ZY |
1360 | APMG_CLK_VAL_DMA_CLK_RQT | |
1361 | APMG_CLK_VAL_BSM_CLK_RQT); | |
1362 | udelay(10); | |
1363 | ||
5d49f498 | 1364 | iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, |
b481de9c ZY |
1365 | APMG_PS_CTRL_VAL_RESET_REQ); |
1366 | udelay(5); | |
5d49f498 | 1367 | iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, |
b481de9c | 1368 | APMG_PS_CTRL_VAL_RESET_REQ); |
5d49f498 | 1369 | iwl_release_nic_access(priv); |
b481de9c ZY |
1370 | } |
1371 | ||
1372 | /* Clear the 'host command active' bit... */ | |
1373 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
1374 | ||
1375 | wake_up_interruptible(&priv->wait_command_queue); | |
1376 | spin_unlock_irqrestore(&priv->lock, flags); | |
1377 | ||
1378 | return rc; | |
1379 | } | |
1380 | ||
1381 | /** | |
bb8c093b | 1382 | * iwl3945_hw_reg_adjust_power_by_temp |
bbc5807b IS |
1383 | * return index delta into power gain settings table |
1384 | */ | |
bb8c093b | 1385 | static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading) |
b481de9c ZY |
1386 | { |
1387 | return (new_reading - old_reading) * (-11) / 100; | |
1388 | } | |
1389 | ||
1390 | /** | |
bb8c093b | 1391 | * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range |
b481de9c | 1392 | */ |
bb8c093b | 1393 | static inline int iwl3945_hw_reg_temp_out_of_range(int temperature) |
b481de9c | 1394 | { |
3ac7f146 | 1395 | return ((temperature < -260) || (temperature > 25)) ? 1 : 0; |
b481de9c ZY |
1396 | } |
1397 | ||
4a8a4322 | 1398 | int iwl3945_hw_get_temperature(struct iwl_priv *priv) |
b481de9c | 1399 | { |
5d49f498 | 1400 | return iwl_read32(priv, CSR_UCODE_DRV_GP2); |
b481de9c ZY |
1401 | } |
1402 | ||
1403 | /** | |
bb8c093b | 1404 | * iwl3945_hw_reg_txpower_get_temperature |
bbc5807b IS |
1405 | * get the current temperature by reading from NIC |
1406 | */ | |
4a8a4322 | 1407 | static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv) |
b481de9c ZY |
1408 | { |
1409 | int temperature; | |
1410 | ||
bb8c093b | 1411 | temperature = iwl3945_hw_get_temperature(priv); |
b481de9c ZY |
1412 | |
1413 | /* driver's okay range is -260 to +25. | |
1414 | * human readable okay range is 0 to +285 */ | |
1415 | IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT); | |
1416 | ||
1417 | /* handle insane temp reading */ | |
bb8c093b | 1418 | if (iwl3945_hw_reg_temp_out_of_range(temperature)) { |
15b1687c | 1419 | IWL_ERR(priv, "Error bad temperature value %d\n", temperature); |
b481de9c ZY |
1420 | |
1421 | /* if really really hot(?), | |
1422 | * substitute the 3rd band/group's temp measured at factory */ | |
1423 | if (priv->last_temperature > 100) | |
f2c7e521 | 1424 | temperature = priv->eeprom39.groups[2].temperature; |
b481de9c ZY |
1425 | else /* else use most recent "sane" value from driver */ |
1426 | temperature = priv->last_temperature; | |
1427 | } | |
1428 | ||
1429 | return temperature; /* raw, not "human readable" */ | |
1430 | } | |
1431 | ||
1432 | /* Adjust Txpower only if temperature variance is greater than threshold. | |
1433 | * | |
1434 | * Both are lower than older versions' 9 degrees */ | |
1435 | #define IWL_TEMPERATURE_LIMIT_TIMER 6 | |
1436 | ||
1437 | /** | |
1438 | * is_temp_calib_needed - determines if new calibration is needed | |
1439 | * | |
1440 | * records new temperature in tx_mgr->temperature. | |
1441 | * replaces tx_mgr->last_temperature *only* if calib needed | |
1442 | * (assumes caller will actually do the calibration!). */ | |
4a8a4322 | 1443 | static int is_temp_calib_needed(struct iwl_priv *priv) |
b481de9c ZY |
1444 | { |
1445 | int temp_diff; | |
1446 | ||
bb8c093b | 1447 | priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv); |
b481de9c ZY |
1448 | temp_diff = priv->temperature - priv->last_temperature; |
1449 | ||
1450 | /* get absolute value */ | |
1451 | if (temp_diff < 0) { | |
1452 | IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff); | |
1453 | temp_diff = -temp_diff; | |
1454 | } else if (temp_diff == 0) | |
1455 | IWL_DEBUG_POWER("Same temp,\n"); | |
1456 | else | |
1457 | IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff); | |
1458 | ||
1459 | /* if we don't need calibration, *don't* update last_temperature */ | |
1460 | if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) { | |
1461 | IWL_DEBUG_POWER("Timed thermal calib not needed\n"); | |
1462 | return 0; | |
1463 | } | |
1464 | ||
1465 | IWL_DEBUG_POWER("Timed thermal calib needed\n"); | |
1466 | ||
1467 | /* assume that caller will actually do calib ... | |
1468 | * update the "last temperature" value */ | |
1469 | priv->last_temperature = priv->temperature; | |
1470 | return 1; | |
1471 | } | |
1472 | ||
1473 | #define IWL_MAX_GAIN_ENTRIES 78 | |
1474 | #define IWL_CCK_FROM_OFDM_POWER_DIFF -5 | |
1475 | #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10) | |
1476 | ||
1477 | /* radio and DSP power table, each step is 1/2 dB. | |
1478 | * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */ | |
bb8c093b | 1479 | static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = { |
b481de9c ZY |
1480 | { |
1481 | {251, 127}, /* 2.4 GHz, highest power */ | |
1482 | {251, 127}, | |
1483 | {251, 127}, | |
1484 | {251, 127}, | |
1485 | {251, 125}, | |
1486 | {251, 110}, | |
1487 | {251, 105}, | |
1488 | {251, 98}, | |
1489 | {187, 125}, | |
1490 | {187, 115}, | |
1491 | {187, 108}, | |
1492 | {187, 99}, | |
1493 | {243, 119}, | |
1494 | {243, 111}, | |
1495 | {243, 105}, | |
1496 | {243, 97}, | |
1497 | {243, 92}, | |
1498 | {211, 106}, | |
1499 | {211, 100}, | |
1500 | {179, 120}, | |
1501 | {179, 113}, | |
1502 | {179, 107}, | |
1503 | {147, 125}, | |
1504 | {147, 119}, | |
1505 | {147, 112}, | |
1506 | {147, 106}, | |
1507 | {147, 101}, | |
1508 | {147, 97}, | |
1509 | {147, 91}, | |
1510 | {115, 107}, | |
1511 | {235, 121}, | |
1512 | {235, 115}, | |
1513 | {235, 109}, | |
1514 | {203, 127}, | |
1515 | {203, 121}, | |
1516 | {203, 115}, | |
1517 | {203, 108}, | |
1518 | {203, 102}, | |
1519 | {203, 96}, | |
1520 | {203, 92}, | |
1521 | {171, 110}, | |
1522 | {171, 104}, | |
1523 | {171, 98}, | |
1524 | {139, 116}, | |
1525 | {227, 125}, | |
1526 | {227, 119}, | |
1527 | {227, 113}, | |
1528 | {227, 107}, | |
1529 | {227, 101}, | |
1530 | {227, 96}, | |
1531 | {195, 113}, | |
1532 | {195, 106}, | |
1533 | {195, 102}, | |
1534 | {195, 95}, | |
1535 | {163, 113}, | |
1536 | {163, 106}, | |
1537 | {163, 102}, | |
1538 | {163, 95}, | |
1539 | {131, 113}, | |
1540 | {131, 106}, | |
1541 | {131, 102}, | |
1542 | {131, 95}, | |
1543 | {99, 113}, | |
1544 | {99, 106}, | |
1545 | {99, 102}, | |
1546 | {99, 95}, | |
1547 | {67, 113}, | |
1548 | {67, 106}, | |
1549 | {67, 102}, | |
1550 | {67, 95}, | |
1551 | {35, 113}, | |
1552 | {35, 106}, | |
1553 | {35, 102}, | |
1554 | {35, 95}, | |
1555 | {3, 113}, | |
1556 | {3, 106}, | |
1557 | {3, 102}, | |
1558 | {3, 95} }, /* 2.4 GHz, lowest power */ | |
1559 | { | |
1560 | {251, 127}, /* 5.x GHz, highest power */ | |
1561 | {251, 120}, | |
1562 | {251, 114}, | |
1563 | {219, 119}, | |
1564 | {219, 101}, | |
1565 | {187, 113}, | |
1566 | {187, 102}, | |
1567 | {155, 114}, | |
1568 | {155, 103}, | |
1569 | {123, 117}, | |
1570 | {123, 107}, | |
1571 | {123, 99}, | |
1572 | {123, 92}, | |
1573 | {91, 108}, | |
1574 | {59, 125}, | |
1575 | {59, 118}, | |
1576 | {59, 109}, | |
1577 | {59, 102}, | |
1578 | {59, 96}, | |
1579 | {59, 90}, | |
1580 | {27, 104}, | |
1581 | {27, 98}, | |
1582 | {27, 92}, | |
1583 | {115, 118}, | |
1584 | {115, 111}, | |
1585 | {115, 104}, | |
1586 | {83, 126}, | |
1587 | {83, 121}, | |
1588 | {83, 113}, | |
1589 | {83, 105}, | |
1590 | {83, 99}, | |
1591 | {51, 118}, | |
1592 | {51, 111}, | |
1593 | {51, 104}, | |
1594 | {51, 98}, | |
1595 | {19, 116}, | |
1596 | {19, 109}, | |
1597 | {19, 102}, | |
1598 | {19, 98}, | |
1599 | {19, 93}, | |
1600 | {171, 113}, | |
1601 | {171, 107}, | |
1602 | {171, 99}, | |
1603 | {139, 120}, | |
1604 | {139, 113}, | |
1605 | {139, 107}, | |
1606 | {139, 99}, | |
1607 | {107, 120}, | |
1608 | {107, 113}, | |
1609 | {107, 107}, | |
1610 | {107, 99}, | |
1611 | {75, 120}, | |
1612 | {75, 113}, | |
1613 | {75, 107}, | |
1614 | {75, 99}, | |
1615 | {43, 120}, | |
1616 | {43, 113}, | |
1617 | {43, 107}, | |
1618 | {43, 99}, | |
1619 | {11, 120}, | |
1620 | {11, 113}, | |
1621 | {11, 107}, | |
1622 | {11, 99}, | |
1623 | {131, 107}, | |
1624 | {131, 99}, | |
1625 | {99, 120}, | |
1626 | {99, 113}, | |
1627 | {99, 107}, | |
1628 | {99, 99}, | |
1629 | {67, 120}, | |
1630 | {67, 113}, | |
1631 | {67, 107}, | |
1632 | {67, 99}, | |
1633 | {35, 120}, | |
1634 | {35, 113}, | |
1635 | {35, 107}, | |
1636 | {35, 99}, | |
1637 | {3, 120} } /* 5.x GHz, lowest power */ | |
1638 | }; | |
1639 | ||
bb8c093b | 1640 | static inline u8 iwl3945_hw_reg_fix_power_index(int index) |
b481de9c ZY |
1641 | { |
1642 | if (index < 0) | |
1643 | return 0; | |
1644 | if (index >= IWL_MAX_GAIN_ENTRIES) | |
1645 | return IWL_MAX_GAIN_ENTRIES - 1; | |
1646 | return (u8) index; | |
1647 | } | |
1648 | ||
1649 | /* Kick off thermal recalibration check every 60 seconds */ | |
1650 | #define REG_RECALIB_PERIOD (60) | |
1651 | ||
1652 | /** | |
bb8c093b | 1653 | * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests |
b481de9c ZY |
1654 | * |
1655 | * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK) | |
1656 | * or 6 Mbit (OFDM) rates. | |
1657 | */ | |
4a8a4322 | 1658 | static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index, |
b481de9c | 1659 | s32 rate_index, const s8 *clip_pwrs, |
d20b3c65 | 1660 | struct iwl_channel_info *ch_info, |
b481de9c ZY |
1661 | int band_index) |
1662 | { | |
bb8c093b | 1663 | struct iwl3945_scan_power_info *scan_power_info; |
b481de9c ZY |
1664 | s8 power; |
1665 | u8 power_index; | |
1666 | ||
1667 | scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index]; | |
1668 | ||
1669 | /* use this channel group's 6Mbit clipping/saturation pwr, | |
1670 | * but cap at regulatory scan power restriction (set during init | |
1671 | * based on eeprom channel data) for this channel. */ | |
14577f23 | 1672 | power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]); |
b481de9c ZY |
1673 | |
1674 | /* further limit to user's max power preference. | |
1675 | * FIXME: Other spectrum management power limitations do not | |
1676 | * seem to apply?? */ | |
62ea9c5b | 1677 | power = min(power, priv->tx_power_user_lmt); |
b481de9c ZY |
1678 | scan_power_info->requested_power = power; |
1679 | ||
1680 | /* find difference between new scan *power* and current "normal" | |
1681 | * Tx *power* for 6Mb. Use this difference (x2) to adjust the | |
1682 | * current "normal" temperature-compensated Tx power *index* for | |
1683 | * this rate (1Mb or 6Mb) to yield new temp-compensated scan power | |
1684 | * *index*. */ | |
1685 | power_index = ch_info->power_info[rate_index].power_table_index | |
1686 | - (power - ch_info->power_info | |
14577f23 | 1687 | [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2; |
b481de9c ZY |
1688 | |
1689 | /* store reference index that we use when adjusting *all* scan | |
1690 | * powers. So we can accommodate user (all channel) or spectrum | |
1691 | * management (single channel) power changes "between" temperature | |
1692 | * feedback compensation procedures. | |
1693 | * don't force fit this reference index into gain table; it may be a | |
1694 | * negative number. This will help avoid errors when we're at | |
1695 | * the lower bounds (highest gains, for warmest temperatures) | |
1696 | * of the table. */ | |
1697 | ||
1698 | /* don't exceed table bounds for "real" setting */ | |
bb8c093b | 1699 | power_index = iwl3945_hw_reg_fix_power_index(power_index); |
b481de9c ZY |
1700 | |
1701 | scan_power_info->power_table_index = power_index; | |
1702 | scan_power_info->tpc.tx_gain = | |
1703 | power_gain_table[band_index][power_index].tx_gain; | |
1704 | scan_power_info->tpc.dsp_atten = | |
1705 | power_gain_table[band_index][power_index].dsp_atten; | |
1706 | } | |
1707 | ||
1708 | /** | |
75bcfae9 | 1709 | * iwl3945_send_tx_power - fill in Tx Power command with gain settings |
b481de9c ZY |
1710 | * |
1711 | * Configures power settings for all rates for the current channel, | |
1712 | * using values from channel info struct, and send to NIC | |
1713 | */ | |
75bcfae9 | 1714 | int iwl3945_send_tx_power(struct iwl_priv *priv) |
b481de9c | 1715 | { |
14577f23 | 1716 | int rate_idx, i; |
d20b3c65 | 1717 | const struct iwl_channel_info *ch_info = NULL; |
bb8c093b | 1718 | struct iwl3945_txpowertable_cmd txpower = { |
f2c7e521 | 1719 | .channel = priv->active39_rxon.channel, |
b481de9c ZY |
1720 | }; |
1721 | ||
8318d78a | 1722 | txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1; |
bb8c093b | 1723 | ch_info = iwl3945_get_channel_info(priv, |
8318d78a | 1724 | priv->band, |
f2c7e521 | 1725 | le16_to_cpu(priv->active39_rxon.channel)); |
b481de9c | 1726 | if (!ch_info) { |
15b1687c WT |
1727 | IWL_ERR(priv, |
1728 | "Failed to get channel info for channel %d [%d]\n", | |
1729 | le16_to_cpu(priv->active39_rxon.channel), priv->band); | |
b481de9c ZY |
1730 | return -EINVAL; |
1731 | } | |
1732 | ||
1733 | if (!is_channel_valid(ch_info)) { | |
1734 | IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on " | |
1735 | "non-Tx channel.\n"); | |
1736 | return 0; | |
1737 | } | |
1738 | ||
1739 | /* fill cmd with power settings for all rates for current channel */ | |
14577f23 MA |
1740 | /* Fill OFDM rate */ |
1741 | for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0; | |
d9829a67 | 1742 | rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) { |
14577f23 MA |
1743 | |
1744 | txpower.power[i].tpc = ch_info->power_info[i].tpc; | |
bb8c093b | 1745 | txpower.power[i].rate = iwl3945_rates[rate_idx].plcp; |
b481de9c ZY |
1746 | |
1747 | IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n", | |
1748 | le16_to_cpu(txpower.channel), | |
1749 | txpower.band, | |
14577f23 MA |
1750 | txpower.power[i].tpc.tx_gain, |
1751 | txpower.power[i].tpc.dsp_atten, | |
1752 | txpower.power[i].rate); | |
1753 | } | |
1754 | /* Fill CCK rates */ | |
1755 | for (rate_idx = IWL_FIRST_CCK_RATE; | |
1756 | rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) { | |
1757 | txpower.power[i].tpc = ch_info->power_info[i].tpc; | |
bb8c093b | 1758 | txpower.power[i].rate = iwl3945_rates[rate_idx].plcp; |
14577f23 MA |
1759 | |
1760 | IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n", | |
1761 | le16_to_cpu(txpower.channel), | |
1762 | txpower.band, | |
1763 | txpower.power[i].tpc.tx_gain, | |
1764 | txpower.power[i].tpc.dsp_atten, | |
1765 | txpower.power[i].rate); | |
b481de9c ZY |
1766 | } |
1767 | ||
518099a8 SO |
1768 | return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, |
1769 | sizeof(struct iwl3945_txpowertable_cmd), | |
1770 | &txpower); | |
b481de9c ZY |
1771 | |
1772 | } | |
1773 | ||
1774 | /** | |
bb8c093b | 1775 | * iwl3945_hw_reg_set_new_power - Configures power tables at new levels |
b481de9c ZY |
1776 | * @ch_info: Channel to update. Uses power_info.requested_power. |
1777 | * | |
1778 | * Replace requested_power and base_power_index ch_info fields for | |
1779 | * one channel. | |
1780 | * | |
1781 | * Called if user or spectrum management changes power preferences. | |
1782 | * Takes into account h/w and modulation limitations (clip power). | |
1783 | * | |
1784 | * This does *not* send anything to NIC, just sets up ch_info for one channel. | |
1785 | * | |
1786 | * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to | |
1787 | * properly fill out the scan powers, and actual h/w gain settings, | |
1788 | * and send changes to NIC | |
1789 | */ | |
4a8a4322 | 1790 | static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv, |
d20b3c65 | 1791 | struct iwl_channel_info *ch_info) |
b481de9c | 1792 | { |
bb8c093b | 1793 | struct iwl3945_channel_power_info *power_info; |
b481de9c ZY |
1794 | int power_changed = 0; |
1795 | int i; | |
1796 | const s8 *clip_pwrs; | |
1797 | int power; | |
1798 | ||
1799 | /* Get this chnlgrp's rate-to-max/clip-powers table */ | |
f2c7e521 | 1800 | clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers; |
b481de9c ZY |
1801 | |
1802 | /* Get this channel's rate-to-current-power settings table */ | |
1803 | power_info = ch_info->power_info; | |
1804 | ||
1805 | /* update OFDM Txpower settings */ | |
14577f23 | 1806 | for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; |
b481de9c ZY |
1807 | i++, ++power_info) { |
1808 | int delta_idx; | |
1809 | ||
1810 | /* limit new power to be no more than h/w capability */ | |
1811 | power = min(ch_info->curr_txpow, clip_pwrs[i]); | |
1812 | if (power == power_info->requested_power) | |
1813 | continue; | |
1814 | ||
1815 | /* find difference between old and new requested powers, | |
1816 | * update base (non-temp-compensated) power index */ | |
1817 | delta_idx = (power - power_info->requested_power) * 2; | |
1818 | power_info->base_power_index -= delta_idx; | |
1819 | ||
1820 | /* save new requested power value */ | |
1821 | power_info->requested_power = power; | |
1822 | ||
1823 | power_changed = 1; | |
1824 | } | |
1825 | ||
1826 | /* update CCK Txpower settings, based on OFDM 12M setting ... | |
1827 | * ... all CCK power settings for a given channel are the *same*. */ | |
1828 | if (power_changed) { | |
1829 | power = | |
14577f23 | 1830 | ch_info->power_info[IWL_RATE_12M_INDEX_TABLE]. |
b481de9c ZY |
1831 | requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF; |
1832 | ||
bb8c093b | 1833 | /* do all CCK rates' iwl3945_channel_power_info structures */ |
14577f23 | 1834 | for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) { |
b481de9c ZY |
1835 | power_info->requested_power = power; |
1836 | power_info->base_power_index = | |
14577f23 | 1837 | ch_info->power_info[IWL_RATE_12M_INDEX_TABLE]. |
b481de9c ZY |
1838 | base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF; |
1839 | ++power_info; | |
1840 | } | |
1841 | } | |
1842 | ||
1843 | return 0; | |
1844 | } | |
1845 | ||
1846 | /** | |
bb8c093b | 1847 | * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel |
b481de9c ZY |
1848 | * |
1849 | * NOTE: Returned power limit may be less (but not more) than requested, | |
1850 | * based strictly on regulatory (eeprom and spectrum mgt) limitations | |
1851 | * (no consideration for h/w clipping limitations). | |
1852 | */ | |
d20b3c65 | 1853 | static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info) |
b481de9c ZY |
1854 | { |
1855 | s8 max_power; | |
1856 | ||
1857 | #if 0 | |
1858 | /* if we're using TGd limits, use lower of TGd or EEPROM */ | |
1859 | if (ch_info->tgd_data.max_power != 0) | |
1860 | max_power = min(ch_info->tgd_data.max_power, | |
1861 | ch_info->eeprom.max_power_avg); | |
1862 | ||
1863 | /* else just use EEPROM limits */ | |
1864 | else | |
1865 | #endif | |
1866 | max_power = ch_info->eeprom.max_power_avg; | |
1867 | ||
1868 | return min(max_power, ch_info->max_power_avg); | |
1869 | } | |
1870 | ||
1871 | /** | |
bb8c093b | 1872 | * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature |
b481de9c ZY |
1873 | * |
1874 | * Compensate txpower settings of *all* channels for temperature. | |
1875 | * This only accounts for the difference between current temperature | |
1876 | * and the factory calibration temperatures, and bases the new settings | |
1877 | * on the channel's base_power_index. | |
1878 | * | |
1879 | * If RxOn is "associated", this sends the new Txpower to NIC! | |
1880 | */ | |
4a8a4322 | 1881 | static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv) |
b481de9c | 1882 | { |
d20b3c65 | 1883 | struct iwl_channel_info *ch_info = NULL; |
b481de9c ZY |
1884 | int delta_index; |
1885 | const s8 *clip_pwrs; /* array of h/w max power levels for each rate */ | |
1886 | u8 a_band; | |
1887 | u8 rate_index; | |
1888 | u8 scan_tbl_index; | |
1889 | u8 i; | |
1890 | int ref_temp; | |
1891 | int temperature = priv->temperature; | |
1892 | ||
1893 | /* set up new Tx power info for each and every channel, 2.4 and 5.x */ | |
1894 | for (i = 0; i < priv->channel_count; i++) { | |
1895 | ch_info = &priv->channel_info[i]; | |
1896 | a_band = is_channel_a_band(ch_info); | |
1897 | ||
1898 | /* Get this chnlgrp's factory calibration temperature */ | |
f2c7e521 | 1899 | ref_temp = (s16)priv->eeprom39.groups[ch_info->group_index]. |
b481de9c ZY |
1900 | temperature; |
1901 | ||
a96a27f9 | 1902 | /* get power index adjustment based on current and factory |
b481de9c | 1903 | * temps */ |
bb8c093b | 1904 | delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature, |
b481de9c ZY |
1905 | ref_temp); |
1906 | ||
1907 | /* set tx power value for all rates, OFDM and CCK */ | |
1908 | for (rate_index = 0; rate_index < IWL_RATE_COUNT; | |
1909 | rate_index++) { | |
1910 | int power_idx = | |
1911 | ch_info->power_info[rate_index].base_power_index; | |
1912 | ||
1913 | /* temperature compensate */ | |
1914 | power_idx += delta_index; | |
1915 | ||
1916 | /* stay within table range */ | |
bb8c093b | 1917 | power_idx = iwl3945_hw_reg_fix_power_index(power_idx); |
b481de9c ZY |
1918 | ch_info->power_info[rate_index]. |
1919 | power_table_index = (u8) power_idx; | |
1920 | ch_info->power_info[rate_index].tpc = | |
1921 | power_gain_table[a_band][power_idx]; | |
1922 | } | |
1923 | ||
1924 | /* Get this chnlgrp's rate-to-max/clip-powers table */ | |
f2c7e521 | 1925 | clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers; |
b481de9c ZY |
1926 | |
1927 | /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */ | |
1928 | for (scan_tbl_index = 0; | |
1929 | scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) { | |
1930 | s32 actual_index = (scan_tbl_index == 0) ? | |
14577f23 | 1931 | IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE; |
bb8c093b | 1932 | iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index, |
b481de9c ZY |
1933 | actual_index, clip_pwrs, |
1934 | ch_info, a_band); | |
1935 | } | |
1936 | } | |
1937 | ||
1938 | /* send Txpower command for current channel to ucode */ | |
75bcfae9 | 1939 | return priv->cfg->ops->lib->send_tx_power(priv); |
b481de9c ZY |
1940 | } |
1941 | ||
4a8a4322 | 1942 | int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power) |
b481de9c | 1943 | { |
d20b3c65 | 1944 | struct iwl_channel_info *ch_info; |
b481de9c ZY |
1945 | s8 max_power; |
1946 | u8 a_band; | |
1947 | u8 i; | |
1948 | ||
62ea9c5b | 1949 | if (priv->tx_power_user_lmt == power) { |
b481de9c ZY |
1950 | IWL_DEBUG_POWER("Requested Tx power same as current " |
1951 | "limit: %ddBm.\n", power); | |
1952 | return 0; | |
1953 | } | |
1954 | ||
1955 | IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power); | |
62ea9c5b | 1956 | priv->tx_power_user_lmt = power; |
b481de9c ZY |
1957 | |
1958 | /* set up new Tx powers for each and every channel, 2.4 and 5.x */ | |
1959 | ||
1960 | for (i = 0; i < priv->channel_count; i++) { | |
1961 | ch_info = &priv->channel_info[i]; | |
1962 | a_band = is_channel_a_band(ch_info); | |
1963 | ||
1964 | /* find minimum power of all user and regulatory constraints | |
1965 | * (does not consider h/w clipping limitations) */ | |
bb8c093b | 1966 | max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info); |
b481de9c ZY |
1967 | max_power = min(power, max_power); |
1968 | if (max_power != ch_info->curr_txpow) { | |
1969 | ch_info->curr_txpow = max_power; | |
1970 | ||
1971 | /* this considers the h/w clipping limitations */ | |
bb8c093b | 1972 | iwl3945_hw_reg_set_new_power(priv, ch_info); |
b481de9c ZY |
1973 | } |
1974 | } | |
1975 | ||
1976 | /* update txpower settings for all channels, | |
1977 | * send to NIC if associated. */ | |
1978 | is_temp_calib_needed(priv); | |
bb8c093b | 1979 | iwl3945_hw_reg_comp_txpower_temp(priv); |
b481de9c ZY |
1980 | |
1981 | return 0; | |
1982 | } | |
1983 | ||
1984 | /* will add 3945 channel switch cmd handling later */ | |
4a8a4322 | 1985 | int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel) |
b481de9c ZY |
1986 | { |
1987 | return 0; | |
1988 | } | |
1989 | ||
1990 | /** | |
1991 | * iwl3945_reg_txpower_periodic - called when time to check our temperature. | |
1992 | * | |
1993 | * -- reset periodic timer | |
1994 | * -- see if temp has changed enough to warrant re-calibration ... if so: | |
1995 | * -- correct coeffs for temp (can reset temp timer) | |
1996 | * -- save this temp as "last", | |
1997 | * -- send new set of gain settings to NIC | |
1998 | * NOTE: This should continue working, even when we're not associated, | |
1999 | * so we can keep our internal table of scan powers current. */ | |
4a8a4322 | 2000 | void iwl3945_reg_txpower_periodic(struct iwl_priv *priv) |
b481de9c ZY |
2001 | { |
2002 | /* This will kick in the "brute force" | |
bb8c093b | 2003 | * iwl3945_hw_reg_comp_txpower_temp() below */ |
b481de9c ZY |
2004 | if (!is_temp_calib_needed(priv)) |
2005 | goto reschedule; | |
2006 | ||
2007 | /* Set up a new set of temp-adjusted TxPowers, send to NIC. | |
2008 | * This is based *only* on current temperature, | |
2009 | * ignoring any previous power measurements */ | |
bb8c093b | 2010 | iwl3945_hw_reg_comp_txpower_temp(priv); |
b481de9c ZY |
2011 | |
2012 | reschedule: | |
2013 | queue_delayed_work(priv->workqueue, | |
2014 | &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ); | |
2015 | } | |
2016 | ||
416e1438 | 2017 | static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work) |
b481de9c | 2018 | { |
4a8a4322 | 2019 | struct iwl_priv *priv = container_of(work, struct iwl_priv, |
b481de9c ZY |
2020 | thermal_periodic.work); |
2021 | ||
2022 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
2023 | return; | |
2024 | ||
2025 | mutex_lock(&priv->mutex); | |
2026 | iwl3945_reg_txpower_periodic(priv); | |
2027 | mutex_unlock(&priv->mutex); | |
2028 | } | |
2029 | ||
2030 | /** | |
bb8c093b | 2031 | * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4) |
b481de9c ZY |
2032 | * for the channel. |
2033 | * | |
2034 | * This function is used when initializing channel-info structs. | |
2035 | * | |
2036 | * NOTE: These channel groups do *NOT* match the bands above! | |
2037 | * These channel groups are based on factory-tested channels; | |
2038 | * on A-band, EEPROM's "group frequency" entries represent the top | |
2039 | * channel in each group 1-4. Group 5 All B/G channels are in group 0. | |
2040 | */ | |
4a8a4322 | 2041 | static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv, |
d20b3c65 | 2042 | const struct iwl_channel_info *ch_info) |
b481de9c | 2043 | { |
f2c7e521 | 2044 | struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom39.groups[0]; |
b481de9c ZY |
2045 | u8 group; |
2046 | u16 group_index = 0; /* based on factory calib frequencies */ | |
2047 | u8 grp_channel; | |
2048 | ||
2049 | /* Find the group index for the channel ... don't use index 1(?) */ | |
2050 | if (is_channel_a_band(ch_info)) { | |
2051 | for (group = 1; group < 5; group++) { | |
2052 | grp_channel = ch_grp[group].group_channel; | |
2053 | if (ch_info->channel <= grp_channel) { | |
2054 | group_index = group; | |
2055 | break; | |
2056 | } | |
2057 | } | |
2058 | /* group 4 has a few channels *above* its factory cal freq */ | |
2059 | if (group == 5) | |
2060 | group_index = 4; | |
2061 | } else | |
2062 | group_index = 0; /* 2.4 GHz, group 0 */ | |
2063 | ||
2064 | IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel, | |
2065 | group_index); | |
2066 | return group_index; | |
2067 | } | |
2068 | ||
2069 | /** | |
bb8c093b | 2070 | * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index |
b481de9c ZY |
2071 | * |
2072 | * Interpolate to get nominal (i.e. at factory calibration temperature) index | |
2073 | * into radio/DSP gain settings table for requested power. | |
2074 | */ | |
4a8a4322 | 2075 | static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv, |
b481de9c ZY |
2076 | s8 requested_power, |
2077 | s32 setting_index, s32 *new_index) | |
2078 | { | |
bb8c093b | 2079 | const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL; |
b481de9c ZY |
2080 | s32 index0, index1; |
2081 | s32 power = 2 * requested_power; | |
2082 | s32 i; | |
bb8c093b | 2083 | const struct iwl3945_eeprom_txpower_sample *samples; |
b481de9c ZY |
2084 | s32 gains0, gains1; |
2085 | s32 res; | |
2086 | s32 denominator; | |
2087 | ||
f2c7e521 | 2088 | chnl_grp = &priv->eeprom39.groups[setting_index]; |
b481de9c ZY |
2089 | samples = chnl_grp->samples; |
2090 | for (i = 0; i < 5; i++) { | |
2091 | if (power == samples[i].power) { | |
2092 | *new_index = samples[i].gain_index; | |
2093 | return 0; | |
2094 | } | |
2095 | } | |
2096 | ||
2097 | if (power > samples[1].power) { | |
2098 | index0 = 0; | |
2099 | index1 = 1; | |
2100 | } else if (power > samples[2].power) { | |
2101 | index0 = 1; | |
2102 | index1 = 2; | |
2103 | } else if (power > samples[3].power) { | |
2104 | index0 = 2; | |
2105 | index1 = 3; | |
2106 | } else { | |
2107 | index0 = 3; | |
2108 | index1 = 4; | |
2109 | } | |
2110 | ||
2111 | denominator = (s32) samples[index1].power - (s32) samples[index0].power; | |
2112 | if (denominator == 0) | |
2113 | return -EINVAL; | |
2114 | gains0 = (s32) samples[index0].gain_index * (1 << 19); | |
2115 | gains1 = (s32) samples[index1].gain_index * (1 << 19); | |
2116 | res = gains0 + (gains1 - gains0) * | |
2117 | ((s32) power - (s32) samples[index0].power) / denominator + | |
2118 | (1 << 18); | |
2119 | *new_index = res >> 19; | |
2120 | return 0; | |
2121 | } | |
2122 | ||
4a8a4322 | 2123 | static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv) |
b481de9c ZY |
2124 | { |
2125 | u32 i; | |
2126 | s32 rate_index; | |
bb8c093b | 2127 | const struct iwl3945_eeprom_txpower_group *group; |
b481de9c ZY |
2128 | |
2129 | IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n"); | |
2130 | ||
2131 | for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) { | |
2132 | s8 *clip_pwrs; /* table of power levels for each rate */ | |
2133 | s8 satur_pwr; /* saturation power for each chnl group */ | |
f2c7e521 | 2134 | group = &priv->eeprom39.groups[i]; |
b481de9c ZY |
2135 | |
2136 | /* sanity check on factory saturation power value */ | |
2137 | if (group->saturation_power < 40) { | |
39aadf8c | 2138 | IWL_WARN(priv, "Error: saturation power is %d, " |
b481de9c ZY |
2139 | "less than minimum expected 40\n", |
2140 | group->saturation_power); | |
2141 | return; | |
2142 | } | |
2143 | ||
2144 | /* | |
2145 | * Derive requested power levels for each rate, based on | |
2146 | * hardware capabilities (saturation power for band). | |
2147 | * Basic value is 3dB down from saturation, with further | |
2148 | * power reductions for highest 3 data rates. These | |
2149 | * backoffs provide headroom for high rate modulation | |
2150 | * power peaks, without too much distortion (clipping). | |
2151 | */ | |
2152 | /* we'll fill in this array with h/w max power levels */ | |
f2c7e521 | 2153 | clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers; |
b481de9c ZY |
2154 | |
2155 | /* divide factory saturation power by 2 to find -3dB level */ | |
2156 | satur_pwr = (s8) (group->saturation_power >> 1); | |
2157 | ||
2158 | /* fill in channel group's nominal powers for each rate */ | |
2159 | for (rate_index = 0; | |
2160 | rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) { | |
2161 | switch (rate_index) { | |
14577f23 | 2162 | case IWL_RATE_36M_INDEX_TABLE: |
b481de9c ZY |
2163 | if (i == 0) /* B/G */ |
2164 | *clip_pwrs = satur_pwr; | |
2165 | else /* A */ | |
2166 | *clip_pwrs = satur_pwr - 5; | |
2167 | break; | |
14577f23 | 2168 | case IWL_RATE_48M_INDEX_TABLE: |
b481de9c ZY |
2169 | if (i == 0) |
2170 | *clip_pwrs = satur_pwr - 7; | |
2171 | else | |
2172 | *clip_pwrs = satur_pwr - 10; | |
2173 | break; | |
14577f23 | 2174 | case IWL_RATE_54M_INDEX_TABLE: |
b481de9c ZY |
2175 | if (i == 0) |
2176 | *clip_pwrs = satur_pwr - 9; | |
2177 | else | |
2178 | *clip_pwrs = satur_pwr - 12; | |
2179 | break; | |
2180 | default: | |
2181 | *clip_pwrs = satur_pwr; | |
2182 | break; | |
2183 | } | |
2184 | } | |
2185 | } | |
2186 | } | |
2187 | ||
2188 | /** | |
2189 | * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM | |
2190 | * | |
2191 | * Second pass (during init) to set up priv->channel_info | |
2192 | * | |
2193 | * Set up Tx-power settings in our channel info database for each VALID | |
2194 | * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values | |
2195 | * and current temperature. | |
2196 | * | |
2197 | * Since this is based on current temperature (at init time), these values may | |
2198 | * not be valid for very long, but it gives us a starting/default point, | |
2199 | * and allows us to active (i.e. using Tx) scan. | |
2200 | * | |
2201 | * This does *not* write values to NIC, just sets up our internal table. | |
2202 | */ | |
4a8a4322 | 2203 | int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv) |
b481de9c | 2204 | { |
d20b3c65 | 2205 | struct iwl_channel_info *ch_info = NULL; |
bb8c093b | 2206 | struct iwl3945_channel_power_info *pwr_info; |
b481de9c ZY |
2207 | int delta_index; |
2208 | u8 rate_index; | |
2209 | u8 scan_tbl_index; | |
2210 | const s8 *clip_pwrs; /* array of power levels for each rate */ | |
2211 | u8 gain, dsp_atten; | |
2212 | s8 power; | |
2213 | u8 pwr_index, base_pwr_index, a_band; | |
2214 | u8 i; | |
2215 | int temperature; | |
2216 | ||
2217 | /* save temperature reference, | |
2218 | * so we can determine next time to calibrate */ | |
bb8c093b | 2219 | temperature = iwl3945_hw_reg_txpower_get_temperature(priv); |
b481de9c ZY |
2220 | priv->last_temperature = temperature; |
2221 | ||
bb8c093b | 2222 | iwl3945_hw_reg_init_channel_groups(priv); |
b481de9c ZY |
2223 | |
2224 | /* initialize Tx power info for each and every channel, 2.4 and 5.x */ | |
2225 | for (i = 0, ch_info = priv->channel_info; i < priv->channel_count; | |
2226 | i++, ch_info++) { | |
2227 | a_band = is_channel_a_band(ch_info); | |
2228 | if (!is_channel_valid(ch_info)) | |
2229 | continue; | |
2230 | ||
2231 | /* find this channel's channel group (*not* "band") index */ | |
2232 | ch_info->group_index = | |
bb8c093b | 2233 | iwl3945_hw_reg_get_ch_grp_index(priv, ch_info); |
b481de9c ZY |
2234 | |
2235 | /* Get this chnlgrp's rate->max/clip-powers table */ | |
f2c7e521 | 2236 | clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers; |
b481de9c ZY |
2237 | |
2238 | /* calculate power index *adjustment* value according to | |
2239 | * diff between current temperature and factory temperature */ | |
bb8c093b | 2240 | delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature, |
f2c7e521 | 2241 | priv->eeprom39.groups[ch_info->group_index]. |
b481de9c ZY |
2242 | temperature); |
2243 | ||
2244 | IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n", | |
2245 | ch_info->channel, delta_index, temperature + | |
2246 | IWL_TEMP_CONVERT); | |
2247 | ||
2248 | /* set tx power value for all OFDM rates */ | |
2249 | for (rate_index = 0; rate_index < IWL_OFDM_RATES; | |
2250 | rate_index++) { | |
25a4ccea | 2251 | s32 uninitialized_var(power_idx); |
b481de9c ZY |
2252 | int rc; |
2253 | ||
2254 | /* use channel group's clip-power table, | |
2255 | * but don't exceed channel's max power */ | |
2256 | s8 pwr = min(ch_info->max_power_avg, | |
2257 | clip_pwrs[rate_index]); | |
2258 | ||
2259 | pwr_info = &ch_info->power_info[rate_index]; | |
2260 | ||
2261 | /* get base (i.e. at factory-measured temperature) | |
2262 | * power table index for this rate's power */ | |
bb8c093b | 2263 | rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr, |
b481de9c ZY |
2264 | ch_info->group_index, |
2265 | &power_idx); | |
2266 | if (rc) { | |
15b1687c | 2267 | IWL_ERR(priv, "Invalid power index\n"); |
b481de9c ZY |
2268 | return rc; |
2269 | } | |
2270 | pwr_info->base_power_index = (u8) power_idx; | |
2271 | ||
2272 | /* temperature compensate */ | |
2273 | power_idx += delta_index; | |
2274 | ||
2275 | /* stay within range of gain table */ | |
bb8c093b | 2276 | power_idx = iwl3945_hw_reg_fix_power_index(power_idx); |
b481de9c | 2277 | |
bb8c093b | 2278 | /* fill 1 OFDM rate's iwl3945_channel_power_info struct */ |
b481de9c ZY |
2279 | pwr_info->requested_power = pwr; |
2280 | pwr_info->power_table_index = (u8) power_idx; | |
2281 | pwr_info->tpc.tx_gain = | |
2282 | power_gain_table[a_band][power_idx].tx_gain; | |
2283 | pwr_info->tpc.dsp_atten = | |
2284 | power_gain_table[a_band][power_idx].dsp_atten; | |
2285 | } | |
2286 | ||
2287 | /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/ | |
14577f23 | 2288 | pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE]; |
b481de9c ZY |
2289 | power = pwr_info->requested_power + |
2290 | IWL_CCK_FROM_OFDM_POWER_DIFF; | |
2291 | pwr_index = pwr_info->power_table_index + | |
2292 | IWL_CCK_FROM_OFDM_INDEX_DIFF; | |
2293 | base_pwr_index = pwr_info->base_power_index + | |
2294 | IWL_CCK_FROM_OFDM_INDEX_DIFF; | |
2295 | ||
2296 | /* stay within table range */ | |
bb8c093b | 2297 | pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index); |
b481de9c ZY |
2298 | gain = power_gain_table[a_band][pwr_index].tx_gain; |
2299 | dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten; | |
2300 | ||
bb8c093b | 2301 | /* fill each CCK rate's iwl3945_channel_power_info structure |
b481de9c ZY |
2302 | * NOTE: All CCK-rate Txpwrs are the same for a given chnl! |
2303 | * NOTE: CCK rates start at end of OFDM rates! */ | |
14577f23 MA |
2304 | for (rate_index = 0; |
2305 | rate_index < IWL_CCK_RATES; rate_index++) { | |
2306 | pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES]; | |
b481de9c ZY |
2307 | pwr_info->requested_power = power; |
2308 | pwr_info->power_table_index = pwr_index; | |
2309 | pwr_info->base_power_index = base_pwr_index; | |
2310 | pwr_info->tpc.tx_gain = gain; | |
2311 | pwr_info->tpc.dsp_atten = dsp_atten; | |
2312 | } | |
2313 | ||
2314 | /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */ | |
2315 | for (scan_tbl_index = 0; | |
2316 | scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) { | |
2317 | s32 actual_index = (scan_tbl_index == 0) ? | |
14577f23 | 2318 | IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE; |
bb8c093b | 2319 | iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index, |
b481de9c ZY |
2320 | actual_index, clip_pwrs, ch_info, a_band); |
2321 | } | |
2322 | } | |
2323 | ||
2324 | return 0; | |
2325 | } | |
2326 | ||
4a8a4322 | 2327 | int iwl3945_hw_rxq_stop(struct iwl_priv *priv) |
b481de9c ZY |
2328 | { |
2329 | int rc; | |
2330 | unsigned long flags; | |
2331 | ||
2332 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 | 2333 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
2334 | if (rc) { |
2335 | spin_unlock_irqrestore(&priv->lock, flags); | |
2336 | return rc; | |
2337 | } | |
2338 | ||
5d49f498 AK |
2339 | iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0); |
2340 | rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS, | |
bddadf86 | 2341 | FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); |
b481de9c | 2342 | if (rc < 0) |
15b1687c | 2343 | IWL_ERR(priv, "Can't stop Rx DMA.\n"); |
b481de9c | 2344 | |
5d49f498 | 2345 | iwl_release_nic_access(priv); |
b481de9c ZY |
2346 | spin_unlock_irqrestore(&priv->lock, flags); |
2347 | ||
2348 | return 0; | |
2349 | } | |
2350 | ||
188cf6c7 | 2351 | int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq) |
b481de9c ZY |
2352 | { |
2353 | int rc; | |
2354 | unsigned long flags; | |
2355 | int txq_id = txq->q.id; | |
2356 | ||
3832ec9d | 2357 | struct iwl3945_shared *shared_data = priv->shared_virt; |
b481de9c ZY |
2358 | |
2359 | shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr); | |
2360 | ||
2361 | spin_lock_irqsave(&priv->lock, flags); | |
5d49f498 | 2362 | rc = iwl_grab_nic_access(priv); |
b481de9c ZY |
2363 | if (rc) { |
2364 | spin_unlock_irqrestore(&priv->lock, flags); | |
2365 | return rc; | |
2366 | } | |
5d49f498 AK |
2367 | iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0); |
2368 | iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0); | |
bddadf86 | 2369 | |
5d49f498 | 2370 | iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), |
bddadf86 TW |
2371 | FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT | |
2372 | FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF | | |
2373 | FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD | | |
2374 | FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | | |
2375 | FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE); | |
5d49f498 | 2376 | iwl_release_nic_access(priv); |
b481de9c ZY |
2377 | |
2378 | /* fake read to flush all prev. writes */ | |
5d49f498 | 2379 | iwl_read32(priv, FH39_TSSR_CBB_BASE); |
b481de9c ZY |
2380 | spin_unlock_irqrestore(&priv->lock, flags); |
2381 | ||
2382 | return 0; | |
2383 | } | |
2384 | ||
42427b4e KA |
2385 | /* |
2386 | * HCMD utils | |
2387 | */ | |
2388 | static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len) | |
2389 | { | |
2390 | switch (cmd_id) { | |
2391 | case REPLY_RXON: | |
2392 | return (u16) sizeof(struct iwl3945_rxon_cmd); | |
2393 | default: | |
2394 | return len; | |
2395 | } | |
2396 | } | |
2397 | ||
b481de9c ZY |
2398 | /** |
2399 | * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table | |
2400 | */ | |
4a8a4322 | 2401 | int iwl3945_init_hw_rate_table(struct iwl_priv *priv) |
b481de9c | 2402 | { |
14577f23 | 2403 | int rc, i, index, prev_index; |
bb8c093b | 2404 | struct iwl3945_rate_scaling_cmd rate_cmd = { |
b481de9c ZY |
2405 | .reserved = {0, 0, 0}, |
2406 | }; | |
bb8c093b | 2407 | struct iwl3945_rate_scaling_info *table = rate_cmd.table; |
b481de9c | 2408 | |
bb8c093b CH |
2409 | for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) { |
2410 | index = iwl3945_rates[i].table_rs_index; | |
14577f23 MA |
2411 | |
2412 | table[index].rate_n_flags = | |
bb8c093b | 2413 | iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0); |
14577f23 | 2414 | table[index].try_cnt = priv->retry_rate; |
bb8c093b | 2415 | prev_index = iwl3945_get_prev_ieee_rate(i); |
7262796a AM |
2416 | table[index].next_rate_index = |
2417 | iwl3945_rates[prev_index].table_rs_index; | |
b481de9c ZY |
2418 | } |
2419 | ||
8318d78a JB |
2420 | switch (priv->band) { |
2421 | case IEEE80211_BAND_5GHZ: | |
b481de9c ZY |
2422 | IWL_DEBUG_RATE("Select A mode rate scale\n"); |
2423 | /* If one of the following CCK rates is used, | |
2424 | * have it fall back to the 6M OFDM rate */ | |
7262796a AM |
2425 | for (i = IWL_RATE_1M_INDEX_TABLE; |
2426 | i <= IWL_RATE_11M_INDEX_TABLE; i++) | |
2427 | table[i].next_rate_index = | |
2428 | iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index; | |
b481de9c ZY |
2429 | |
2430 | /* Don't fall back to CCK rates */ | |
7262796a AM |
2431 | table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = |
2432 | IWL_RATE_9M_INDEX_TABLE; | |
b481de9c ZY |
2433 | |
2434 | /* Don't drop out of OFDM rates */ | |
14577f23 | 2435 | table[IWL_RATE_6M_INDEX_TABLE].next_rate_index = |
bb8c093b | 2436 | iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index; |
b481de9c ZY |
2437 | break; |
2438 | ||
8318d78a JB |
2439 | case IEEE80211_BAND_2GHZ: |
2440 | IWL_DEBUG_RATE("Select B/G mode rate scale\n"); | |
b481de9c ZY |
2441 | /* If an OFDM rate is used, have it fall back to the |
2442 | * 1M CCK rates */ | |
b481de9c | 2443 | |
7262796a AM |
2444 | if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) && |
2445 | iwl3945_is_associated(priv)) { | |
2446 | ||
2447 | index = IWL_FIRST_CCK_RATE; | |
2448 | for (i = IWL_RATE_6M_INDEX_TABLE; | |
2449 | i <= IWL_RATE_54M_INDEX_TABLE; i++) | |
2450 | table[i].next_rate_index = | |
2451 | iwl3945_rates[index].table_rs_index; | |
2452 | ||
2453 | index = IWL_RATE_11M_INDEX_TABLE; | |
2454 | /* CCK shouldn't fall back to OFDM... */ | |
2455 | table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE; | |
2456 | } | |
b481de9c ZY |
2457 | break; |
2458 | ||
2459 | default: | |
8318d78a | 2460 | WARN_ON(1); |
b481de9c ZY |
2461 | break; |
2462 | } | |
2463 | ||
2464 | /* Update the rate scaling for control frame Tx */ | |
2465 | rate_cmd.table_id = 0; | |
518099a8 | 2466 | rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd), |
b481de9c ZY |
2467 | &rate_cmd); |
2468 | if (rc) | |
2469 | return rc; | |
2470 | ||
2471 | /* Update the rate scaling for data frame Tx */ | |
2472 | rate_cmd.table_id = 1; | |
518099a8 | 2473 | return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd), |
b481de9c ZY |
2474 | &rate_cmd); |
2475 | } | |
2476 | ||
796083cb | 2477 | /* Called when initializing driver */ |
4a8a4322 | 2478 | int iwl3945_hw_set_hw_params(struct iwl_priv *priv) |
b481de9c | 2479 | { |
3832ec9d AK |
2480 | memset((void *)&priv->hw_params, 0, |
2481 | sizeof(struct iwl_hw_params)); | |
b481de9c | 2482 | |
3832ec9d | 2483 | priv->shared_virt = |
b481de9c | 2484 | pci_alloc_consistent(priv->pci_dev, |
bb8c093b | 2485 | sizeof(struct iwl3945_shared), |
3832ec9d | 2486 | &priv->shared_phys); |
b481de9c | 2487 | |
3832ec9d | 2488 | if (!priv->shared_virt) { |
15b1687c | 2489 | IWL_ERR(priv, "failed to allocate pci memory\n"); |
b481de9c ZY |
2490 | mutex_unlock(&priv->mutex); |
2491 | return -ENOMEM; | |
2492 | } | |
2493 | ||
1e33dc64 | 2494 | priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K; |
3832ec9d AK |
2495 | priv->hw_params.max_pkt_size = 2342; |
2496 | priv->hw_params.max_rxq_size = RX_QUEUE_SIZE; | |
2497 | priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; | |
2498 | priv->hw_params.max_stations = IWL3945_STATION_COUNT; | |
2499 | priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID; | |
3e82a822 | 2500 | |
141c43a3 WT |
2501 | priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR; |
2502 | ||
b481de9c ZY |
2503 | return 0; |
2504 | } | |
2505 | ||
4a8a4322 | 2506 | unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv, |
bb8c093b | 2507 | struct iwl3945_frame *frame, u8 rate) |
b481de9c | 2508 | { |
bb8c093b | 2509 | struct iwl3945_tx_beacon_cmd *tx_beacon_cmd; |
b481de9c ZY |
2510 | unsigned int frame_size; |
2511 | ||
bb8c093b | 2512 | tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u; |
b481de9c ZY |
2513 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); |
2514 | ||
3832ec9d | 2515 | tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id; |
b481de9c ZY |
2516 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; |
2517 | ||
bb8c093b | 2518 | frame_size = iwl3945_fill_beacon_frame(priv, |
b481de9c | 2519 | tx_beacon_cmd->frame, |
b481de9c ZY |
2520 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
2521 | ||
2522 | BUG_ON(frame_size > MAX_MPDU_SIZE); | |
2523 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); | |
2524 | ||
2525 | tx_beacon_cmd->tx.rate = rate; | |
2526 | tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK | | |
2527 | TX_CMD_FLG_TSF_MSK); | |
2528 | ||
14577f23 MA |
2529 | /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/ |
2530 | tx_beacon_cmd->tx.supp_rates[0] = | |
2531 | (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; | |
2532 | ||
b481de9c | 2533 | tx_beacon_cmd->tx.supp_rates[1] = |
14577f23 | 2534 | (IWL_CCK_BASIC_RATES_MASK & 0xF); |
b481de9c | 2535 | |
3ac7f146 | 2536 | return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size; |
b481de9c ZY |
2537 | } |
2538 | ||
4a8a4322 | 2539 | void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv) |
b481de9c | 2540 | { |
91c066f2 | 2541 | priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx; |
b481de9c ZY |
2542 | priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx; |
2543 | } | |
2544 | ||
4a8a4322 | 2545 | void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv) |
b481de9c ZY |
2546 | { |
2547 | INIT_DELAYED_WORK(&priv->thermal_periodic, | |
2548 | iwl3945_bg_reg_txpower_periodic); | |
2549 | } | |
2550 | ||
4a8a4322 | 2551 | void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv) |
b481de9c ZY |
2552 | { |
2553 | cancel_delayed_work(&priv->thermal_periodic); | |
2554 | } | |
2555 | ||
0164b9b4 KA |
2556 | /* check contents of special bootstrap uCode SRAM */ |
2557 | static int iwl3945_verify_bsm(struct iwl_priv *priv) | |
2558 | { | |
2559 | __le32 *image = priv->ucode_boot.v_addr; | |
2560 | u32 len = priv->ucode_boot.len; | |
2561 | u32 reg; | |
2562 | u32 val; | |
2563 | ||
2564 | IWL_DEBUG_INFO("Begin verify bsm\n"); | |
2565 | ||
2566 | /* verify BSM SRAM contents */ | |
2567 | val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG); | |
2568 | for (reg = BSM_SRAM_LOWER_BOUND; | |
2569 | reg < BSM_SRAM_LOWER_BOUND + len; | |
2570 | reg += sizeof(u32), image++) { | |
2571 | val = iwl_read_prph(priv, reg); | |
2572 | if (val != le32_to_cpu(*image)) { | |
2573 | IWL_ERR(priv, "BSM uCode verification failed at " | |
2574 | "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", | |
2575 | BSM_SRAM_LOWER_BOUND, | |
2576 | reg - BSM_SRAM_LOWER_BOUND, len, | |
2577 | val, le32_to_cpu(*image)); | |
2578 | return -EIO; | |
2579 | } | |
2580 | } | |
2581 | ||
2582 | IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n"); | |
2583 | ||
2584 | return 0; | |
2585 | } | |
2586 | ||
2587 | /** | |
2588 | * iwl3945_load_bsm - Load bootstrap instructions | |
2589 | * | |
2590 | * BSM operation: | |
2591 | * | |
2592 | * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program | |
2593 | * in special SRAM that does not power down during RFKILL. When powering back | |
2594 | * up after power-saving sleeps (or during initial uCode load), the BSM loads | |
2595 | * the bootstrap program into the on-board processor, and starts it. | |
2596 | * | |
2597 | * The bootstrap program loads (via DMA) instructions and data for a new | |
2598 | * program from host DRAM locations indicated by the host driver in the | |
2599 | * BSM_DRAM_* registers. Once the new program is loaded, it starts | |
2600 | * automatically. | |
2601 | * | |
2602 | * When initializing the NIC, the host driver points the BSM to the | |
2603 | * "initialize" uCode image. This uCode sets up some internal data, then | |
2604 | * notifies host via "initialize alive" that it is complete. | |
2605 | * | |
2606 | * The host then replaces the BSM_DRAM_* pointer values to point to the | |
2607 | * normal runtime uCode instructions and a backup uCode data cache buffer | |
2608 | * (filled initially with starting data values for the on-board processor), | |
2609 | * then triggers the "initialize" uCode to load and launch the runtime uCode, | |
2610 | * which begins normal operation. | |
2611 | * | |
2612 | * When doing a power-save shutdown, runtime uCode saves data SRAM into | |
2613 | * the backup data cache in DRAM before SRAM is powered down. | |
2614 | * | |
2615 | * When powering back up, the BSM loads the bootstrap program. This reloads | |
2616 | * the runtime uCode instructions and the backup data cache into SRAM, | |
2617 | * and re-launches the runtime uCode from where it left off. | |
2618 | */ | |
2619 | static int iwl3945_load_bsm(struct iwl_priv *priv) | |
2620 | { | |
2621 | __le32 *image = priv->ucode_boot.v_addr; | |
2622 | u32 len = priv->ucode_boot.len; | |
2623 | dma_addr_t pinst; | |
2624 | dma_addr_t pdata; | |
2625 | u32 inst_len; | |
2626 | u32 data_len; | |
2627 | int rc; | |
2628 | int i; | |
2629 | u32 done; | |
2630 | u32 reg_offset; | |
2631 | ||
2632 | IWL_DEBUG_INFO("Begin load bsm\n"); | |
2633 | ||
2634 | /* make sure bootstrap program is no larger than BSM's SRAM size */ | |
2635 | if (len > IWL39_MAX_BSM_SIZE) | |
2636 | return -EINVAL; | |
2637 | ||
2638 | /* Tell bootstrap uCode where to find the "Initialize" uCode | |
2639 | * in host DRAM ... host DRAM physical address bits 31:0 for 3945. | |
2640 | * NOTE: iwl3945_initialize_alive_start() will replace these values, | |
2641 | * after the "initialize" uCode has run, to point to | |
2642 | * runtime/protocol instructions and backup data cache. */ | |
2643 | pinst = priv->ucode_init.p_addr; | |
2644 | pdata = priv->ucode_init_data.p_addr; | |
2645 | inst_len = priv->ucode_init.len; | |
2646 | data_len = priv->ucode_init_data.len; | |
2647 | ||
2648 | rc = iwl_grab_nic_access(priv); | |
2649 | if (rc) | |
2650 | return rc; | |
2651 | ||
2652 | iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); | |
2653 | iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); | |
2654 | iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); | |
2655 | iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); | |
2656 | ||
2657 | /* Fill BSM memory with bootstrap instructions */ | |
2658 | for (reg_offset = BSM_SRAM_LOWER_BOUND; | |
2659 | reg_offset < BSM_SRAM_LOWER_BOUND + len; | |
2660 | reg_offset += sizeof(u32), image++) | |
2661 | _iwl_write_prph(priv, reg_offset, | |
2662 | le32_to_cpu(*image)); | |
2663 | ||
2664 | rc = iwl3945_verify_bsm(priv); | |
2665 | if (rc) { | |
2666 | iwl_release_nic_access(priv); | |
2667 | return rc; | |
2668 | } | |
2669 | ||
2670 | /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ | |
2671 | iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0); | |
2672 | iwl_write_prph(priv, BSM_WR_MEM_DST_REG, | |
2673 | IWL39_RTC_INST_LOWER_BOUND); | |
2674 | iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); | |
2675 | ||
2676 | /* Load bootstrap code into instruction SRAM now, | |
2677 | * to prepare to load "initialize" uCode */ | |
2678 | iwl_write_prph(priv, BSM_WR_CTRL_REG, | |
2679 | BSM_WR_CTRL_REG_BIT_START); | |
2680 | ||
2681 | /* Wait for load of bootstrap uCode to finish */ | |
2682 | for (i = 0; i < 100; i++) { | |
2683 | done = iwl_read_prph(priv, BSM_WR_CTRL_REG); | |
2684 | if (!(done & BSM_WR_CTRL_REG_BIT_START)) | |
2685 | break; | |
2686 | udelay(10); | |
2687 | } | |
2688 | if (i < 100) | |
2689 | IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i); | |
2690 | else { | |
2691 | IWL_ERR(priv, "BSM write did not complete!\n"); | |
2692 | return -EIO; | |
2693 | } | |
2694 | ||
2695 | /* Enable future boot loads whenever power management unit triggers it | |
2696 | * (e.g. when powering back up after power-save shutdown) */ | |
2697 | iwl_write_prph(priv, BSM_WR_CTRL_REG, | |
2698 | BSM_WR_CTRL_REG_BIT_START_EN); | |
2699 | ||
2700 | iwl_release_nic_access(priv); | |
2701 | ||
2702 | return 0; | |
2703 | } | |
2704 | ||
2705 | static struct iwl_lib_ops iwl3945_lib = { | |
7aaa1d79 SO |
2706 | .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd, |
2707 | .txq_free_tfd = iwl3945_hw_txq_free_tfd, | |
0164b9b4 | 2708 | .load_ucode = iwl3945_load_bsm, |
01ec616d KA |
2709 | .apm_ops = { |
2710 | .init = iwl3945_apm_init, | |
2711 | .reset = iwl3945_apm_reset, | |
2712 | .stop = iwl3945_apm_stop, | |
2713 | .config = iwl3945_nic_config, | |
854682ed | 2714 | .set_pwr_src = iwl3945_set_pwr_src, |
01ec616d | 2715 | }, |
75bcfae9 | 2716 | .send_tx_power = iwl3945_send_tx_power, |
0164b9b4 KA |
2717 | }; |
2718 | ||
42427b4e KA |
2719 | static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = { |
2720 | .get_hcmd_size = iwl3945_get_hcmd_size, | |
2721 | }; | |
2722 | ||
0164b9b4 KA |
2723 | static struct iwl_ops iwl3945_ops = { |
2724 | .lib = &iwl3945_lib, | |
42427b4e | 2725 | .utils = &iwl3945_hcmd_utils, |
0164b9b4 KA |
2726 | }; |
2727 | ||
c0f20d91 | 2728 | static struct iwl_cfg iwl3945_bg_cfg = { |
82b9a121 | 2729 | .name = "3945BG", |
a0987a8d RC |
2730 | .fw_name_pre = IWL3945_FW_PRE, |
2731 | .ucode_api_max = IWL3945_UCODE_API_MAX, | |
2732 | .ucode_api_min = IWL3945_UCODE_API_MIN, | |
82b9a121 | 2733 | .sku = IWL_SKU_G, |
0164b9b4 | 2734 | .ops = &iwl3945_ops, |
df878d8f | 2735 | .mod_params = &iwl3945_mod_params |
82b9a121 TW |
2736 | }; |
2737 | ||
c0f20d91 | 2738 | static struct iwl_cfg iwl3945_abg_cfg = { |
82b9a121 | 2739 | .name = "3945ABG", |
a0987a8d RC |
2740 | .fw_name_pre = IWL3945_FW_PRE, |
2741 | .ucode_api_max = IWL3945_UCODE_API_MAX, | |
2742 | .ucode_api_min = IWL3945_UCODE_API_MIN, | |
82b9a121 | 2743 | .sku = IWL_SKU_A|IWL_SKU_G, |
0164b9b4 | 2744 | .ops = &iwl3945_ops, |
df878d8f | 2745 | .mod_params = &iwl3945_mod_params |
82b9a121 TW |
2746 | }; |
2747 | ||
bb8c093b | 2748 | struct pci_device_id iwl3945_hw_card_ids[] = { |
82b9a121 TW |
2749 | {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)}, |
2750 | {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)}, | |
2751 | {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)}, | |
2752 | {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)}, | |
2753 | {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)}, | |
2754 | {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)}, | |
b481de9c ZY |
2755 | {0} |
2756 | }; | |
2757 | ||
bb8c093b | 2758 | MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids); |