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cfg80211 API for channels/bitrates, mac80211 and driver conversion
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47
ZY		 39#include <asm/unaligned.h>
40#include <net/mac80211.h>
b481de9c 41
b481de9c 42#include "iwl-3945.h"
5d08cd1d 43#include "iwl-helpers.h"
b481de9c
ZY		 44#include "iwl-3945-rs.h"
45
46#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
47 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
48 IWL_RATE_##r##M_IEEE, \
49 IWL_RATE_##ip##M_INDEX, \
50 IWL_RATE_##in##M_INDEX, \
51 IWL_RATE_##rp##M_INDEX, \
52 IWL_RATE_##rn##M_INDEX, \
53 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 54 IWL_RATE_##np##M_INDEX, \
55 IWL_RATE_##r##M_INDEX_TABLE, \
56 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 57
58/*
59 * Parameter order:
60 * rate, prev rate, next rate, prev tgg rate, next tgg rate
61 *
62 * If there isn't a valid next or previous rate then INV is used which
63 * maps to IWL_RATE_INVALID
64 *
65 */
bb8c093b 66const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT] = {
14577f23
MA		 67 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
68 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
69 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
70 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 71 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
72 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
73 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
74 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
75 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
76 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
77 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
78 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 79};
80
bb8c093b 81/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 82#define IWL_EVT_DISABLE (0)
83#define IWL_EVT_DISABLE_SIZE (1532/32)
84
85/**
bb8c093b 86 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 87 *
88 * Disable an event by writing "1"s into "disable"
89 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
90 * Default values of 0 enable uCode events to be logged.
91 * Use for only special debugging. This function is just a placeholder as-is,
92 * you'll need to provide the special bits! ...
93 * ... and set IWL_EVT_DISABLE to 1. */
bb8c093b 94void iwl3945_disable_events(struct iwl3945_priv *priv)
b481de9c 95{
af7cca2a 96 int ret;
b481de9c
ZY		 97 int i;
98 u32 base; /* SRAM address of event log header */
99 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
100 u32 array_size; /* # of u32 entries in array */
101 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
102 0x00000000, /* 31 - 0 Event id numbers */
103 0x00000000, /* 63 - 32 */
104 0x00000000, /* 95 - 64 */
105 0x00000000, /* 127 - 96 */
106 0x00000000, /* 159 - 128 */
107 0x00000000, /* 191 - 160 */
108 0x00000000, /* 223 - 192 */
109 0x00000000, /* 255 - 224 */
110 0x00000000, /* 287 - 256 */
111 0x00000000, /* 319 - 288 */
112 0x00000000, /* 351 - 320 */
113 0x00000000, /* 383 - 352 */
114 0x00000000, /* 415 - 384 */
115 0x00000000, /* 447 - 416 */
116 0x00000000, /* 479 - 448 */
117 0x00000000, /* 511 - 480 */
118 0x00000000, /* 543 - 512 */
119 0x00000000, /* 575 - 544 */
120 0x00000000, /* 607 - 576 */
121 0x00000000, /* 639 - 608 */
122 0x00000000, /* 671 - 640 */
123 0x00000000, /* 703 - 672 */
124 0x00000000, /* 735 - 704 */
125 0x00000000, /* 767 - 736 */
126 0x00000000, /* 799 - 768 */
127 0x00000000, /* 831 - 800 */
128 0x00000000, /* 863 - 832 */
129 0x00000000, /* 895 - 864 */
130 0x00000000, /* 927 - 896 */
131 0x00000000, /* 959 - 928 */
132 0x00000000, /* 991 - 960 */
133 0x00000000, /* 1023 - 992 */
134 0x00000000, /* 1055 - 1024 */
135 0x00000000, /* 1087 - 1056 */
136 0x00000000, /* 1119 - 1088 */
137 0x00000000, /* 1151 - 1120 */
138 0x00000000, /* 1183 - 1152 */
139 0x00000000, /* 1215 - 1184 */
140 0x00000000, /* 1247 - 1216 */
141 0x00000000, /* 1279 - 1248 */
142 0x00000000, /* 1311 - 1280 */
143 0x00000000, /* 1343 - 1312 */
144 0x00000000, /* 1375 - 1344 */
145 0x00000000, /* 1407 - 1376 */
146 0x00000000, /* 1439 - 1408 */
147 0x00000000, /* 1471 - 1440 */
148 0x00000000, /* 1503 - 1472 */
149 };
150
151 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 152 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
b481de9c
ZY		 153 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
154 return;
155 }
156
bb8c093b 157 ret = iwl3945_grab_nic_access(priv);
af7cca2a 158 if (ret) {
b481de9c
ZY		 159 IWL_WARNING("Can not read from adapter at this time.\n");
160 return;
161 }
162
bb8c093b
CH		 163 disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32)));
164 array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32)));
165 iwl3945_release_nic_access(priv);
b481de9c
ZY		 166
167 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
168 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
169 disable_ptr);
bb8c093b 170 ret = iwl3945_grab_nic_access(priv);
b481de9c 171 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
bb8c093b 172 iwl3945_write_targ_mem(priv,
af7cca2a
TW		 173 disable_ptr + (i * sizeof(u32)),
174 evt_disable[i]);
b481de9c 175
bb8c093b 176 iwl3945_release_nic_access(priv);
b481de9c
ZY		 177 } else {
178 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
179 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
180 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
181 disable_ptr, array_size);
182 }
183
184}
185
186/**
187 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
188 * @priv: eeprom and antenna fields are used to determine antenna flags
189 *
190 * priv->eeprom is used to determine if antenna AUX/MAIN are reversed
191 * priv->antenna specifies the antenna diversity mode:
192 *
193 * IWL_ANTENNA_DIVERISTY - NIC selects best antenna by itself
194 * IWL_ANTENNA_MAIN - Force MAIN antenna
195 * IWL_ANTENNA_AUX - Force AUX antenna
196 */
bb8c093b 197__le32 iwl3945_get_antenna_flags(const struct iwl3945_priv *priv)
b481de9c
ZY		 198{
199 switch (priv->antenna) {
200 case IWL_ANTENNA_DIVERSITY:
201 return 0;
202
203 case IWL_ANTENNA_MAIN:
204 if (priv->eeprom.antenna_switch_type)
205 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
206 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
207
208 case IWL_ANTENNA_AUX:
209 if (priv->eeprom.antenna_switch_type)
210 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
211 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
212 }
213
214 /* bad antenna selector value */
215 IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
216 return 0; /* "diversity" is default if error */
217}
218
219/*****************************************************************************
220 *
221 * Intel PRO/Wireless 3945ABG/BG Network Connection
222 *
223 * RX handler implementations
224 *
225 * Used by iwl-base.c
226 *
227 *****************************************************************************/
228
bb8c093b 229void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
b481de9c 230{
bb8c093b 231 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 232 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
bb8c093b 233 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 234 le32_to_cpu(pkt->len));
235
236 memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics));
237
238 priv->last_statistics_time = jiffies;
239}
240
bd8a040e
RR		 241static void iwl3945_add_radiotap(struct iwl3945_priv *priv,
242 struct sk_buff *skb,
243 struct iwl3945_rx_frame_hdr *rx_hdr,
244 struct ieee80211_rx_status *stats)
12342c47
ZY		 245{
246 /* First cache any information we need before we overwrite
247 * the information provided in the skb from the hardware */
248 s8 signal = stats->ssi;
249 s8 noise = 0;
8318d78a 250 int rate = stats->rate_idx;
12342c47
ZY		 251 u64 tsf = stats->mactime;
252 __le16 phy_flags_hw = rx_hdr->phy_flags;
253
254 struct iwl3945_rt_rx_hdr {
255 struct ieee80211_radiotap_header rt_hdr;
256 __le64 rt_tsf; /* TSF */
257 u8 rt_flags; /* radiotap packet flags */
258 u8 rt_rate; /* rate in 500kb/s */
259 __le16 rt_channelMHz; /* channel in MHz */
260 __le16 rt_chbitmask; /* channel bitfield */
261 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
262 s8 rt_dbmnoise;
263 u8 rt_antenna; /* antenna number */
264 } __attribute__ ((packed)) *iwl3945_rt;
265
266 if (skb_headroom(skb) < sizeof(*iwl3945_rt)) {
267 if (net_ratelimit())
268 printk(KERN_ERR "not enough headroom [%d] for "
d2594d07 269 "radiotap head [%zd]\n",
12342c47
ZY		 270 skb_headroom(skb), sizeof(*iwl3945_rt));
271 return;
272 }
273
274 /* put radiotap header in front of 802.11 header and data */
275 iwl3945_rt = (void *)skb_push(skb, sizeof(*iwl3945_rt));
276
277 /* initialise radiotap header */
278 iwl3945_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
279 iwl3945_rt->rt_hdr.it_pad = 0;
280
281 /* total header + data */
282 put_unaligned(cpu_to_le16(sizeof(*iwl3945_rt)),
283 &iwl3945_rt->rt_hdr.it_len);
284
285 /* Indicate all the fields we add to the radiotap header */
286 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
287 (1 << IEEE80211_RADIOTAP_FLAGS) |
288 (1 << IEEE80211_RADIOTAP_RATE) |
289 (1 << IEEE80211_RADIOTAP_CHANNEL) |
290 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
291 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
292 (1 << IEEE80211_RADIOTAP_ANTENNA)),
293 &iwl3945_rt->rt_hdr.it_present);
294
295 /* Zero the flags, we'll add to them as we go */
296 iwl3945_rt->rt_flags = 0;
297
298 put_unaligned(cpu_to_le64(tsf), &iwl3945_rt->rt_tsf);
299
300 iwl3945_rt->rt_dbmsignal = signal;
301 iwl3945_rt->rt_dbmnoise = noise;
302
303 /* Convert the channel frequency and set the flags */
304 put_unaligned(cpu_to_le16(stats->freq), &iwl3945_rt->rt_channelMHz);
305 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
306 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
307 IEEE80211_CHAN_5GHZ),
308 &iwl3945_rt->rt_chbitmask);
309 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
310 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
311 IEEE80211_CHAN_2GHZ),
312 &iwl3945_rt->rt_chbitmask);
313 else /* 802.11g */
314 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
315 IEEE80211_CHAN_2GHZ),
316 &iwl3945_rt->rt_chbitmask);
317
12342c47
ZY		 318 if (rate == -1)
319 iwl3945_rt->rt_rate = 0;
320 else
321 iwl3945_rt->rt_rate = iwl3945_rates[rate].ieee;
322
323 /* antenna number */
324 iwl3945_rt->rt_antenna =
325 le16_to_cpu(phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
326
327 /* set the preamble flag if we have it */
328 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
329 iwl3945_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
330
331 stats->flag |= RX_FLAG_RADIOTAP;
332}
333
bb8c093b
CH		 334static void iwl3945_handle_data_packet(struct iwl3945_priv *priv, int is_data,
335 struct iwl3945_rx_mem_buffer *rxb,
12342c47 336 struct ieee80211_rx_status *stats)
b481de9c
ZY		 337{
338 struct ieee80211_hdr *hdr;
bb8c093b
CH		 339 struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
340 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
341 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 342 short len = le16_to_cpu(rx_hdr->len);
343
344 /* We received data from the HW, so stop the watchdog */
345 if (unlikely((len + IWL_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
346 IWL_DEBUG_DROP("Corruption detected!\n");
347 return;
348 }
349
350 /* We only process data packets if the interface is open */
351 if (unlikely(!priv->is_open)) {
352 IWL_DEBUG_DROP_LIMIT
353 ("Dropping packet while interface is not open.\n");
354 return;
355 }
b481de9c
ZY		 356
357 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
358 /* Set the size of the skb to the size of the frame */
359 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
360
361 hdr = (void *)rxb->skb->data;
362
bb8c093b
CH		 363 if (iwl3945_param_hwcrypto)
364 iwl3945_set_decrypted_flag(priv, rxb->skb,
b481de9c
ZY		 365 le32_to_cpu(rx_end->status), stats);
366
12342c47
ZY		 367 if (priv->add_radiotap)
368 iwl3945_add_radiotap(priv, rxb->skb, rx_hdr, stats);
369
b481de9c
ZY		 370 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
371 rxb->skb = NULL;
372}
373
7878a5a4
MA		 374#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
375
bb8c093b
CH		 376static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
377 struct iwl3945_rx_mem_buffer *rxb)
b481de9c 378{
bb8c093b
CH		 379 struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
380 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
381 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
382 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c 383 struct ieee80211_hdr *header;
b481de9c
ZY		 384 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
385 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
386 struct ieee80211_rx_status stats = {
387 .mactime = le64_to_cpu(rx_end->timestamp),
388 .freq = ieee80211chan2mhz(le16_to_cpu(rx_hdr->channel)),
8318d78a
JB		 389 .band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
390 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ,
b481de9c 391 .antenna = 0,
8318d78a 392 .rate_idx = iwl3945_rate_index_from_plcp(rx_hdr->rate),
b481de9c
ZY		 393 .flag = 0,
394 };
395 u8 network_packet;
396 int snr;
397
398 if ((unlikely(rx_stats->phy_count > 20))) {
399 IWL_DEBUG_DROP
400 ("dsp size out of range [0,20]: "
401 "%d/n", rx_stats->phy_count);
402 return;
403 }
404
405 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
406 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
407 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
408 return;
409 }
410
411 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
12342c47 412 iwl3945_handle_data_packet(priv, 1, rxb, &stats);
b481de9c
ZY		 413 return;
414 }
415
416 /* Convert 3945's rssi indicator to dBm */
417 stats.ssi = rx_stats->rssi - IWL_RSSI_OFFSET;
418
419 /* Set default noise value to -127 */
420 if (priv->last_rx_noise == 0)
421 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
422
423 /* 3945 provides noise info for OFDM frames only.
424 * sig_avg and noise_diff are measured by the 3945's digital signal
425 * processor (DSP), and indicate linear levels of signal level and
426 * distortion/noise within the packet preamble after
427 * automatic gain control (AGC). sig_avg should stay fairly
428 * constant if the radio's AGC is working well.
429 * Since these values are linear (not dB or dBm), linear
430 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
431 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
432 * to obtain noise level in dBm.
433 * Calculate stats.signal (quality indicator in %) based on SNR. */
434 if (rx_stats_noise_diff) {
435 snr = rx_stats_sig_avg / rx_stats_noise_diff;
bb8c093b
CH		 436 stats.noise = stats.ssi - iwl3945_calc_db_from_ratio(snr);
437 stats.signal = iwl3945_calc_sig_qual(stats.ssi, stats.noise);
b481de9c
ZY		 438
439 /* If noise info not available, calculate signal quality indicator (%)
440 * using just the dBm signal level. */
441 } else {
442 stats.noise = priv->last_rx_noise;
bb8c093b 443 stats.signal = iwl3945_calc_sig_qual(stats.ssi, 0);
b481de9c
ZY		 444 }
445
446
447 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
448 stats.ssi, stats.noise, stats.signal,
449 rx_stats_sig_avg, rx_stats_noise_diff);
450
bb8c093b 451 /* can be covered by iwl3945_report_frame() in most cases */
b481de9c
ZY		 452/* IWL_DEBUG_RX("RX status: 0x%08X\n", rx_end->status); */
453
454 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
455
bb8c093b 456 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 457
c8b0e6e1 458#ifdef CONFIG_IWL3945_DEBUG
bb8c093b 459 if (iwl3945_debug_level & IWL_DL_STATS && net_ratelimit())
b481de9c
ZY		 460 IWL_DEBUG_STATS
461 ("[%c] %d RSSI: %d Signal: %u, Noise: %u, Rate: %u\n",
462 network_packet ? '*' : ' ',
8318d78a
JB		 463 le16_to_cpu(rx_hdr->channel),
464 stats.ssi, stats.ssi,
465 stats.ssi, stats.rate_idx);
b481de9c 466
bb8c093b 467 if (iwl3945_debug_level & (IWL_DL_RX))
b481de9c 468 /* Set "1" to report good data frames in groups of 100 */
bb8c093b 469 iwl3945_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 470#endif
471
472 if (network_packet) {
473 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
474 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
475 priv->last_rx_rssi = stats.ssi;
476 priv->last_rx_noise = stats.noise;
477 }
478
479 switch (le16_to_cpu(header->frame_control) & IEEE80211_FCTL_FTYPE) {
480 case IEEE80211_FTYPE_MGMT:
481 switch (le16_to_cpu(header->frame_control) &
482 IEEE80211_FCTL_STYPE) {
483 case IEEE80211_STYPE_PROBE_RESP:
484 case IEEE80211_STYPE_BEACON:{
485 /* If this is a beacon or probe response for
486 * our network then cache the beacon
487 * timestamp */
488 if ((((priv->iw_mode == IEEE80211_IF_TYPE_STA)
489 && !compare_ether_addr(header->addr2,
490 priv->bssid)) ||
491 ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
492 && !compare_ether_addr(header->addr3,
493 priv->bssid)))) {
494 struct ieee80211_mgmt *mgmt =
495 (struct ieee80211_mgmt *)header;
496 __le32 *pos;
497 pos =
498 (__le32 *) & mgmt->u.beacon.
499 timestamp;
500 priv->timestamp0 = le32_to_cpu(pos[0]);
501 priv->timestamp1 = le32_to_cpu(pos[1]);
502 priv->beacon_int = le16_to_cpu(
503 mgmt->u.beacon.beacon_int);
504 if (priv->call_post_assoc_from_beacon &&
505 (priv->iw_mode ==
506 IEEE80211_IF_TYPE_STA))
507 queue_work(priv->workqueue,
508 &priv->post_associate.work);
509
510 priv->call_post_assoc_from_beacon = 0;
511 }
512
513 break;
514 }
515
516 case IEEE80211_STYPE_ACTION:
517 /* TODO: Parse 802.11h frames for CSA... */
518 break;
519
520 /*
471b3efd
JB		 521 * TODO: Use the new callback function from
522 * mac80211 instead of sniffing these packets.
b481de9c
ZY		 523 */
524 case IEEE80211_STYPE_ASSOC_RESP:
525 case IEEE80211_STYPE_REASSOC_RESP:{
526 struct ieee80211_mgmt *mgnt =
527 (struct ieee80211_mgmt *)header;
7878a5a4
MA		 528
529 /* We have just associated, give some
530 * time for the 4-way handshake if
531 * any. Don't start scan too early. */
532 priv->next_scan_jiffies = jiffies +
533 IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
534
b481de9c
ZY		 535 priv->assoc_id = (~((1 << 15) | (1 << 14)) &
536 le16_to_cpu(mgnt->u.
537 assoc_resp.aid));
538 priv->assoc_capability =
539 le16_to_cpu(mgnt->u.assoc_resp.capab_info);
540 if (priv->beacon_int)
541 queue_work(priv->workqueue,
542 &priv->post_associate.work);
543 else
544 priv->call_post_assoc_from_beacon = 1;
545 break;
546 }
547
548 case IEEE80211_STYPE_PROBE_REQ:{
0795af57
JP		 549 DECLARE_MAC_BUF(mac1);
550 DECLARE_MAC_BUF(mac2);
551 DECLARE_MAC_BUF(mac3);
b481de9c
ZY		 552 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
553 IWL_DEBUG_DROP
0795af57
JP		 554 ("Dropping (non network): %s"
555 ", %s, %s\n",
556 print_mac(mac1, header->addr1),
557 print_mac(mac2, header->addr2),
558 print_mac(mac3, header->addr3));
b481de9c
ZY		 559 return;
560 }
561 }
562
12342c47 563 iwl3945_handle_data_packet(priv, 0, rxb, &stats);
b481de9c
ZY		 564 break;
565
566 case IEEE80211_FTYPE_CTL:
567 break;
568
0795af57
JP		 569 case IEEE80211_FTYPE_DATA: {
570 DECLARE_MAC_BUF(mac1);
571 DECLARE_MAC_BUF(mac2);
572 DECLARE_MAC_BUF(mac3);
573
bb8c093b 574 if (unlikely(iwl3945_is_duplicate_packet(priv, header)))
0795af57
JP		 575 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
576 print_mac(mac1, header->addr1),
577 print_mac(mac2, header->addr2),
578 print_mac(mac3, header->addr3));
b481de9c 579 else
12342c47 580 iwl3945_handle_data_packet(priv, 1, rxb, &stats);
b481de9c
ZY		 581 break;
582 }
0795af57 583 }
b481de9c
ZY		 584}
585
bb8c093b 586int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr,
b481de9c
ZY		 587 dma_addr_t addr, u16 len)
588{
589 int count;
590 u32 pad;
bb8c093b 591 struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
b481de9c
ZY		 592
593 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
594 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
595
596 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
597 IWL_ERROR("Error can not send more than %d chunks\n",
598 NUM_TFD_CHUNKS);
599 return -EINVAL;
600 }
601
602 tfd->pa[count].addr = cpu_to_le32(addr);
603 tfd->pa[count].len = cpu_to_le32(len);
604
605 count++;
606
607 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
608 TFD_CTL_PAD_SET(pad));
609
610 return 0;
611}
612
613/**
bb8c093b 614 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 615 *
616 * Does NOT advance any indexes
617 */
bb8c093b 618int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 619{
bb8c093b
CH		 620 struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
621 struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 622 struct pci_dev *dev = priv->pci_dev;
623 int i;
624 int counter;
625
626 /* classify bd */
627 if (txq->q.id == IWL_CMD_QUEUE_NUM)
628 /* nothing to cleanup after for host commands */
629 return 0;
630
631 /* sanity check */
632 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
633 if (counter > NUM_TFD_CHUNKS) {
634 IWL_ERROR("Too many chunks: %i\n", counter);
635 /* @todo issue fatal error, it is quite serious situation */
636 return 0;
637 }
638
639 /* unmap chunks if any */
640
641 for (i = 1; i < counter; i++) {
642 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
643 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 644 if (txq->txb[txq->q.read_ptr].skb[0]) {
645 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
646 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 647 /* Can be called from interrupt context */
648 dev_kfree_skb_any(skb);
fc4b6853 649 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 650 }
651 }
652 }
653 return 0;
654}
655
bb8c093b 656u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr)
b481de9c
ZY		 657{
658 int i;
659 int ret = IWL_INVALID_STATION;
660 unsigned long flags;
0795af57 661 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 662
663 spin_lock_irqsave(&priv->sta_lock, flags);
664 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
665 if ((priv->stations[i].used) &&
666 (!compare_ether_addr
667 (priv->stations[i].sta.sta.addr, addr))) {
668 ret = i;
669 goto out;
670 }
671
0795af57
JP		 672 IWL_DEBUG_INFO("can not find STA %s (total %d)\n",
673 print_mac(mac, addr), priv->num_stations);
b481de9c
ZY		 674 out:
675 spin_unlock_irqrestore(&priv->sta_lock, flags);
676 return ret;
677}
678
679/**
bb8c093b 680 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 681 *
682*/
bb8c093b
CH		 683void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
684 struct iwl3945_cmd *cmd,
b481de9c
ZY		 685 struct ieee80211_tx_control *ctrl,
686 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
687{
688 unsigned long flags;
8318d78a 689 u16 rate_index = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 690 u16 rate_mask;
691 int rate;
692 u8 rts_retry_limit;
693 u8 data_retry_limit;
694 __le32 tx_flags;
695 u16 fc = le16_to_cpu(hdr->frame_control);
696
bb8c093b 697 rate = iwl3945_rates[rate_index].plcp;
b481de9c
ZY		 698 tx_flags = cmd->cmd.tx.tx_flags;
699
700 /* We need to figure out how to get the sta->supp_rates while
701 * in this running context; perhaps encoding into ctrl->tx_rate? */
702 rate_mask = IWL_RATES_MASK;
703
704 spin_lock_irqsave(&priv->sta_lock, flags);
705
706 priv->stations[sta_id].current_rate.rate_n_flags = rate;
707
708 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
709 (sta_id != IWL3945_BROADCAST_ID) &&
710 (sta_id != IWL_MULTICAST_ID))
711 priv->stations[IWL_STA_ID].current_rate.rate_n_flags = rate;
712
713 spin_unlock_irqrestore(&priv->sta_lock, flags);
714
715 if (tx_id >= IWL_CMD_QUEUE_NUM)
716 rts_retry_limit = 3;
717 else
718 rts_retry_limit = 7;
719
720 if (ieee80211_is_probe_response(fc)) {
721 data_retry_limit = 3;
722 if (data_retry_limit < rts_retry_limit)
723 rts_retry_limit = data_retry_limit;
724 } else
725 data_retry_limit = IWL_DEFAULT_TX_RETRY;
726
727 if (priv->data_retry_limit != -1)
728 data_retry_limit = priv->data_retry_limit;
729
730 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
731 switch (fc & IEEE80211_FCTL_STYPE) {
732 case IEEE80211_STYPE_AUTH:
733 case IEEE80211_STYPE_DEAUTH:
734 case IEEE80211_STYPE_ASSOC_REQ:
735 case IEEE80211_STYPE_REASSOC_REQ:
736 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
737 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
738 tx_flags |= TX_CMD_FLG_CTS_MSK;
739 }
740 break;
741 default:
742 break;
743 }
744 }
745
746 cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
747 cmd->cmd.tx.data_retry_limit = data_retry_limit;
748 cmd->cmd.tx.rate = rate;
749 cmd->cmd.tx.tx_flags = tx_flags;
750
751 /* OFDM */
14577f23
MA		 752 cmd->cmd.tx.supp_rates[0] =
753 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 754
755 /* CCK */
14577f23 756 cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 757
758 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
759 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
760 cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags),
761 cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]);
762}
763
bb8c093b 764u8 iwl3945_sync_sta(struct iwl3945_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 765{
766 unsigned long flags_spin;
bb8c093b 767 struct iwl3945_station_entry *station;
b481de9c
ZY		 768
769 if (sta_id == IWL_INVALID_STATION)
770 return IWL_INVALID_STATION;
771
772 spin_lock_irqsave(&priv->sta_lock, flags_spin);
773 station = &priv->stations[sta_id];
774
775 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
776 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
777 station->current_rate.rate_n_flags = tx_rate;
778 station->sta.mode = STA_CONTROL_MODIFY_MSK;
779
780 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
781
bb8c093b 782 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 783 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
784 sta_id, tx_rate);
785 return sta_id;
786}
787
bb8c093b 788static int iwl3945_nic_set_pwr_src(struct iwl3945_priv *priv, int pwr_max)
b481de9c
ZY		 789{
790 int rc;
791 unsigned long flags;
792
793 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 794 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 795 if (rc) {
796 spin_unlock_irqrestore(&priv->lock, flags);
797 return rc;
798 }
799
800 if (!pwr_max) {
801 u32 val;
802
803 rc = pci_read_config_dword(priv->pci_dev,
804 PCI_POWER_SOURCE, &val);
805 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
bb8c093b 806 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 807 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
808 ~APMG_PS_CTRL_MSK_PWR_SRC);
bb8c093b 809 iwl3945_release_nic_access(priv);
b481de9c 810
bb8c093b 811 iwl3945_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 812 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
813 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
814 } else
bb8c093b 815 iwl3945_release_nic_access(priv);
b481de9c 816 } else {
bb8c093b 817 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 818 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
819 ~APMG_PS_CTRL_MSK_PWR_SRC);
820
bb8c093b
CH		 821 iwl3945_release_nic_access(priv);
822 iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 823 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
824 }
825 spin_unlock_irqrestore(&priv->lock, flags);
826
827 return rc;
828}
829
bb8c093b 830static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
b481de9c
ZY		 831{
832 int rc;
833 unsigned long flags;
834
835 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 836 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 837 if (rc) {
838 spin_unlock_irqrestore(&priv->lock, flags);
839 return rc;
840 }
841
bb8c093b
CH		 842 iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
843 iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
b481de9c 844 priv->hw_setting.shared_phys +
bb8c093b
CH		 845 offsetof(struct iwl3945_shared, rx_read_ptr[0]));
846 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0);
847 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0),
b481de9c
ZY		 848 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
849 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
850 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
851 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
852 (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
853 ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
854 (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
855 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
856
857 /* fake read to flush all prev I/O */
bb8c093b 858 iwl3945_read_direct32(priv, FH_RSSR_CTRL);
b481de9c 859
bb8c093b 860 iwl3945_release_nic_access(priv);
b481de9c
ZY		 861 spin_unlock_irqrestore(&priv->lock, flags);
862
863 return 0;
864}
865
bb8c093b 866static int iwl3945_tx_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 867{
868 int rc;
869 unsigned long flags;
870
871 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 872 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 873 if (rc) {
874 spin_unlock_irqrestore(&priv->lock, flags);
875 return rc;
876 }
877
878 /* bypass mode */
bb8c093b 879 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 880
881 /* RA 0 is active */
bb8c093b 882 iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 883
884 /* all 6 fifo are active */
bb8c093b 885 iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 886
bb8c093b
CH		 887 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
888 iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
889 iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
890 iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 891
bb8c093b 892 iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE,
b481de9c
ZY		 893 priv->hw_setting.shared_phys);
894
bb8c093b 895 iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG,
b481de9c
ZY		 896 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
897 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
898 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
899 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
900 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
901 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
902 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
903
bb8c093b 904 iwl3945_release_nic_access(priv);
b481de9c
ZY		 905 spin_unlock_irqrestore(&priv->lock, flags);
906
907 return 0;
908}
909
910/**
911 * iwl3945_txq_ctx_reset - Reset TX queue context
912 *
913 * Destroys all DMA structures and initialize them again
914 */
bb8c093b 915static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 916{
917 int rc;
918 int txq_id, slots_num;
919
bb8c093b 920 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 921
922 /* Tx CMD queue */
923 rc = iwl3945_tx_reset(priv);
924 if (rc)
925 goto error;
926
927 /* Tx queue(s) */
928 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
929 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
930 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
bb8c093b 931 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 932 txq_id);
933 if (rc) {
934 IWL_ERROR("Tx %d queue init failed\n", txq_id);
935 goto error;
936 }
937 }
938
939 return rc;
940
941 error:
bb8c093b 942 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 943 return rc;
944}
945
bb8c093b 946int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
b481de9c
ZY		 947{
948 u8 rev_id;
949 int rc;
950 unsigned long flags;
bb8c093b 951 struct iwl3945_rx_queue *rxq = &priv->rxq;
b481de9c 952
bb8c093b 953 iwl3945_power_init_handle(priv);
b481de9c
ZY		 954
955 spin_lock_irqsave(&priv->lock, flags);
bb8c093b
CH		 956 iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, (1 << 24));
957 iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
b481de9c
ZY		 958 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
959
bb8c093b
CH		 960 iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
961 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 962 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
963 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
964 if (rc < 0) {
965 spin_unlock_irqrestore(&priv->lock, flags);
966 IWL_DEBUG_INFO("Failed to init the card\n");
967 return rc;
968 }
969
bb8c093b 970 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 971 if (rc) {
972 spin_unlock_irqrestore(&priv->lock, flags);
973 return rc;
974 }
bb8c093b 975 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 976 APMG_CLK_VAL_DMA_CLK_RQT |
977 APMG_CLK_VAL_BSM_CLK_RQT);
978 udelay(20);
bb8c093b 979 iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
b481de9c 980 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
bb8c093b 981 iwl3945_release_nic_access(priv);
b481de9c
ZY		 982 spin_unlock_irqrestore(&priv->lock, flags);
983
984 /* Determine HW type */
985 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
986 if (rc)
987 return rc;
988 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
989
990 iwl3945_nic_set_pwr_src(priv, 1);
991 spin_lock_irqsave(&priv->lock, flags);
992
993 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
994 IWL_DEBUG_INFO("RTP type \n");
995 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
996 IWL_DEBUG_INFO("ALM-MB type\n");
bb8c093b 997 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
b481de9c
ZY		 998 CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB);
999 } else {
1000 IWL_DEBUG_INFO("ALM-MM type\n");
bb8c093b 1001 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
b481de9c
ZY		 1002 CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM);
1003 }
1004
b481de9c
ZY		 1005 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) {
1006 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
bb8c093b 1007 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
b481de9c
ZY		 1008 CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1009 } else
1010 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1011
1012 if ((priv->eeprom.board_revision & 0xF0) == 0xD0) {
1013 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1014 priv->eeprom.board_revision);
bb8c093b 1015 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
b481de9c
ZY		 1016 CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1017 } else {
1018 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1019 priv->eeprom.board_revision);
bb8c093b 1020 iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
b481de9c
ZY		 1021 CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1022 }
1023
1024 if (priv->eeprom.almgor_m_version <= 1) {
bb8c093b 1025 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
b481de9c
ZY		 1026 CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1027 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1028 priv->eeprom.almgor_m_version);
1029 } else {
1030 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1031 priv->eeprom.almgor_m_version);
bb8c093b 1032 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
b481de9c
ZY		 1033 CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1034 }
1035 spin_unlock_irqrestore(&priv->lock, flags);
1036
1037 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1038 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1039
1040 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1041 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1042
1043 /* Allocate the RX queue, or reset if it is already allocated */
1044 if (!rxq->bd) {
bb8c093b 1045 rc = iwl3945_rx_queue_alloc(priv);
b481de9c
ZY		 1046 if (rc) {
1047 IWL_ERROR("Unable to initialize Rx queue\n");
1048 return -ENOMEM;
1049 }
1050 } else
bb8c093b 1051 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1052
bb8c093b 1053 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1054
1055 iwl3945_rx_init(priv, rxq);
1056
1057 spin_lock_irqsave(&priv->lock, flags);
1058
1059 /* Look at using this instead:
1060 rxq->need_update = 1;
bb8c093b 1061 iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1062 */
1063
bb8c093b 1064 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 1065 if (rc) {
1066 spin_unlock_irqrestore(&priv->lock, flags);
1067 return rc;
1068 }
bb8c093b
CH		 1069 iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
1070 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1071
1072 spin_unlock_irqrestore(&priv->lock, flags);
1073
1074 rc = iwl3945_txq_ctx_reset(priv);
1075 if (rc)
1076 return rc;
1077
1078 set_bit(STATUS_INIT, &priv->status);
1079
1080 return 0;
1081}
1082
1083/**
bb8c093b 1084 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1085 *
1086 * Destroy all TX DMA queues and structures
1087 */
bb8c093b 1088void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv)
b481de9c
ZY		 1089{
1090 int txq_id;
1091
1092 /* Tx queues */
1093 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
bb8c093b 1094 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c
ZY		 1095}
1096
bb8c093b 1097void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
b481de9c
ZY		 1098{
1099 int queue;
1100 unsigned long flags;
1101
1102 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 1103 if (iwl3945_grab_nic_access(priv)) {
b481de9c 1104 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 1105 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1106 return;
1107 }
1108
1109 /* stop SCD */
bb8c093b 1110 iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1111
1112 /* reset TFD queues */
1113 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
bb8c093b
CH		 1114 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
1115 iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
b481de9c
ZY		 1116 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
1117 1000);
1118 }
1119
bb8c093b 1120 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1121 spin_unlock_irqrestore(&priv->lock, flags);
1122
bb8c093b 1123 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1124}
1125
bb8c093b 1126int iwl3945_hw_nic_stop_master(struct iwl3945_priv *priv)
b481de9c
ZY		 1127{
1128 int rc = 0;
1129 u32 reg_val;
1130 unsigned long flags;
1131
1132 spin_lock_irqsave(&priv->lock, flags);
1133
1134 /* set stop master bit */
bb8c093b 1135 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1136
bb8c093b 1137 reg_val = iwl3945_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 1138
1139 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
1140 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
1141 IWL_DEBUG_INFO("Card in power save, master is already "
1142 "stopped\n");
1143 else {
bb8c093b 1144 rc = iwl3945_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 1145 CSR_RESET_REG_FLAG_MASTER_DISABLED,
1146 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1147 if (rc < 0) {
1148 spin_unlock_irqrestore(&priv->lock, flags);
1149 return rc;
1150 }
1151 }
1152
1153 spin_unlock_irqrestore(&priv->lock, flags);
1154 IWL_DEBUG_INFO("stop master\n");
1155
1156 return rc;
1157}
1158
bb8c093b 1159int iwl3945_hw_nic_reset(struct iwl3945_priv *priv)
b481de9c
ZY		 1160{
1161 int rc;
1162 unsigned long flags;
1163
bb8c093b 1164 iwl3945_hw_nic_stop_master(priv);
b481de9c
ZY		 1165
1166 spin_lock_irqsave(&priv->lock, flags);
1167
bb8c093b 1168 iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c 1169
bb8c093b 1170 rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1171 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1172 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1173
bb8c093b 1174 rc = iwl3945_grab_nic_access(priv);
b481de9c 1175 if (!rc) {
bb8c093b 1176 iwl3945_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 1177 APMG_CLK_VAL_BSM_CLK_RQT);
1178
1179 udelay(10);
1180
bb8c093b 1181 iwl3945_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1182 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1183
bb8c093b
CH		 1184 iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1185 iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1186 0xFFFFFFFF);
1187
1188 /* enable DMA */
bb8c093b 1189 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1190 APMG_CLK_VAL_DMA_CLK_RQT |
1191 APMG_CLK_VAL_BSM_CLK_RQT);
1192 udelay(10);
1193
bb8c093b 1194 iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1195 APMG_PS_CTRL_VAL_RESET_REQ);
1196 udelay(5);
bb8c093b 1197 iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1198 APMG_PS_CTRL_VAL_RESET_REQ);
bb8c093b 1199 iwl3945_release_nic_access(priv);
b481de9c
ZY		 1200 }
1201
1202 /* Clear the 'host command active' bit... */
1203 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1204
1205 wake_up_interruptible(&priv->wait_command_queue);
1206 spin_unlock_irqrestore(&priv->lock, flags);
1207
1208 return rc;
1209}
1210
1211/**
bb8c093b 1212 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1213 * return index delta into power gain settings table
1214*/
bb8c093b 1215static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1216{
1217 return (new_reading - old_reading) * (-11) / 100;
1218}
1219
1220/**
bb8c093b 1221 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1222 */
bb8c093b 1223static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c
ZY		 1224{
1225 return (((temperature < -260) || (temperature > 25)) ? 1 : 0);
1226}
1227
bb8c093b 1228int iwl3945_hw_get_temperature(struct iwl3945_priv *priv)
b481de9c 1229{
bb8c093b 1230 return iwl3945_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1231}
1232
1233/**
bb8c093b 1234 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1235 * get the current temperature by reading from NIC
1236*/
bb8c093b 1237static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv)
b481de9c
ZY		 1238{
1239 int temperature;
1240
bb8c093b 1241 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1242
1243 /* driver's okay range is -260 to +25.
1244 * human readable okay range is 0 to +285 */
1245 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1246
1247 /* handle insane temp reading */
bb8c093b 1248 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
b481de9c
ZY		 1249 IWL_ERROR("Error bad temperature value %d\n", temperature);
1250
1251 /* if really really hot(?),
1252 * substitute the 3rd band/group's temp measured at factory */
1253 if (priv->last_temperature > 100)
1254 temperature = priv->eeprom.groups[2].temperature;
1255 else /* else use most recent "sane" value from driver */
1256 temperature = priv->last_temperature;
1257 }
1258
1259 return temperature; /* raw, not "human readable" */
1260}
1261
1262/* Adjust Txpower only if temperature variance is greater than threshold.
1263 *
1264 * Both are lower than older versions' 9 degrees */
1265#define IWL_TEMPERATURE_LIMIT_TIMER 6
1266
1267/**
1268 * is_temp_calib_needed - determines if new calibration is needed
1269 *
1270 * records new temperature in tx_mgr->temperature.
1271 * replaces tx_mgr->last_temperature *only* if calib needed
1272 * (assumes caller will actually do the calibration!). */
bb8c093b 1273static int is_temp_calib_needed(struct iwl3945_priv *priv)
b481de9c
ZY		 1274{
1275 int temp_diff;
1276
bb8c093b 1277 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1278 temp_diff = priv->temperature - priv->last_temperature;
1279
1280 /* get absolute value */
1281 if (temp_diff < 0) {
1282 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1283 temp_diff = -temp_diff;
1284 } else if (temp_diff == 0)
1285 IWL_DEBUG_POWER("Same temp,\n");
1286 else
1287 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1288
1289 /* if we don't need calibration, *don't* update last_temperature */
1290 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1291 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1292 return 0;
1293 }
1294
1295 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1296
1297 /* assume that caller will actually do calib ...
1298 * update the "last temperature" value */
1299 priv->last_temperature = priv->temperature;
1300 return 1;
1301}
1302
1303#define IWL_MAX_GAIN_ENTRIES 78
1304#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1305#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1306
1307/* radio and DSP power table, each step is 1/2 dB.
1308 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1309static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1310 {
1311 {251, 127}, /* 2.4 GHz, highest power */
1312 {251, 127},
1313 {251, 127},
1314 {251, 127},
1315 {251, 125},
1316 {251, 110},
1317 {251, 105},
1318 {251, 98},
1319 {187, 125},
1320 {187, 115},
1321 {187, 108},
1322 {187, 99},
1323 {243, 119},
1324 {243, 111},
1325 {243, 105},
1326 {243, 97},
1327 {243, 92},
1328 {211, 106},
1329 {211, 100},
1330 {179, 120},
1331 {179, 113},
1332 {179, 107},
1333 {147, 125},
1334 {147, 119},
1335 {147, 112},
1336 {147, 106},
1337 {147, 101},
1338 {147, 97},
1339 {147, 91},
1340 {115, 107},
1341 {235, 121},
1342 {235, 115},
1343 {235, 109},
1344 {203, 127},
1345 {203, 121},
1346 {203, 115},
1347 {203, 108},
1348 {203, 102},
1349 {203, 96},
1350 {203, 92},
1351 {171, 110},
1352 {171, 104},
1353 {171, 98},
1354 {139, 116},
1355 {227, 125},
1356 {227, 119},
1357 {227, 113},
1358 {227, 107},
1359 {227, 101},
1360 {227, 96},
1361 {195, 113},
1362 {195, 106},
1363 {195, 102},
1364 {195, 95},
1365 {163, 113},
1366 {163, 106},
1367 {163, 102},
1368 {163, 95},
1369 {131, 113},
1370 {131, 106},
1371 {131, 102},
1372 {131, 95},
1373 {99, 113},
1374 {99, 106},
1375 {99, 102},
1376 {99, 95},
1377 {67, 113},
1378 {67, 106},
1379 {67, 102},
1380 {67, 95},
1381 {35, 113},
1382 {35, 106},
1383 {35, 102},
1384 {35, 95},
1385 {3, 113},
1386 {3, 106},
1387 {3, 102},
1388 {3, 95} }, /* 2.4 GHz, lowest power */
1389 {
1390 {251, 127}, /* 5.x GHz, highest power */
1391 {251, 120},
1392 {251, 114},
1393 {219, 119},
1394 {219, 101},
1395 {187, 113},
1396 {187, 102},
1397 {155, 114},
1398 {155, 103},
1399 {123, 117},
1400 {123, 107},
1401 {123, 99},
1402 {123, 92},
1403 {91, 108},
1404 {59, 125},
1405 {59, 118},
1406 {59, 109},
1407 {59, 102},
1408 {59, 96},
1409 {59, 90},
1410 {27, 104},
1411 {27, 98},
1412 {27, 92},
1413 {115, 118},
1414 {115, 111},
1415 {115, 104},
1416 {83, 126},
1417 {83, 121},
1418 {83, 113},
1419 {83, 105},
1420 {83, 99},
1421 {51, 118},
1422 {51, 111},
1423 {51, 104},
1424 {51, 98},
1425 {19, 116},
1426 {19, 109},
1427 {19, 102},
1428 {19, 98},
1429 {19, 93},
1430 {171, 113},
1431 {171, 107},
1432 {171, 99},
1433 {139, 120},
1434 {139, 113},
1435 {139, 107},
1436 {139, 99},
1437 {107, 120},
1438 {107, 113},
1439 {107, 107},
1440 {107, 99},
1441 {75, 120},
1442 {75, 113},
1443 {75, 107},
1444 {75, 99},
1445 {43, 120},
1446 {43, 113},
1447 {43, 107},
1448 {43, 99},
1449 {11, 120},
1450 {11, 113},
1451 {11, 107},
1452 {11, 99},
1453 {131, 107},
1454 {131, 99},
1455 {99, 120},
1456 {99, 113},
1457 {99, 107},
1458 {99, 99},
1459 {67, 120},
1460 {67, 113},
1461 {67, 107},
1462 {67, 99},
1463 {35, 120},
1464 {35, 113},
1465 {35, 107},
1466 {35, 99},
1467 {3, 120} } /* 5.x GHz, lowest power */
1468};
1469
bb8c093b 1470static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1471{
1472 if (index < 0)
1473 return 0;
1474 if (index >= IWL_MAX_GAIN_ENTRIES)
1475 return IWL_MAX_GAIN_ENTRIES - 1;
1476 return (u8) index;
1477}
1478
1479/* Kick off thermal recalibration check every 60 seconds */
1480#define REG_RECALIB_PERIOD (60)
1481
1482/**
bb8c093b 1483 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1484 *
1485 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1486 * or 6 Mbit (OFDM) rates.
1487 */
bb8c093b 1488static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tbl_index,
b481de9c 1489 s32 rate_index, const s8 *clip_pwrs,
bb8c093b 1490 struct iwl3945_channel_info *ch_info,
b481de9c
ZY		 1491 int band_index)
1492{
bb8c093b 1493 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1494 s8 power;
1495 u8 power_index;
1496
1497 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1498
1499 /* use this channel group's 6Mbit clipping/saturation pwr,
1500 * but cap at regulatory scan power restriction (set during init
1501 * based on eeprom channel data) for this channel. */
14577f23 1502 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1503
1504 /* further limit to user's max power preference.
1505 * FIXME: Other spectrum management power limitations do not
1506 * seem to apply?? */
1507 power = min(power, priv->user_txpower_limit);
1508 scan_power_info->requested_power = power;
1509
1510 /* find difference between new scan *power* and current "normal"
1511 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1512 * current "normal" temperature-compensated Tx power *index* for
1513 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1514 * *index*. */
1515 power_index = ch_info->power_info[rate_index].power_table_index
1516 - (power - ch_info->power_info
14577f23 1517 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1518
1519 /* store reference index that we use when adjusting *all* scan
1520 * powers. So we can accommodate user (all channel) or spectrum
1521 * management (single channel) power changes "between" temperature
1522 * feedback compensation procedures.
1523 * don't force fit this reference index into gain table; it may be a
1524 * negative number. This will help avoid errors when we're at
1525 * the lower bounds (highest gains, for warmest temperatures)
1526 * of the table. */
1527
1528 /* don't exceed table bounds for "real" setting */
bb8c093b 1529 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1530
1531 scan_power_info->power_table_index = power_index;
1532 scan_power_info->tpc.tx_gain =
1533 power_gain_table[band_index][power_index].tx_gain;
1534 scan_power_info->tpc.dsp_atten =
1535 power_gain_table[band_index][power_index].dsp_atten;
1536}
1537
1538/**
bb8c093b 1539 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
b481de9c
ZY		 1540 *
1541 * Configures power settings for all rates for the current channel,
1542 * using values from channel info struct, and send to NIC
1543 */
bb8c093b 1544int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv)
b481de9c 1545{
14577f23 1546 int rate_idx, i;
bb8c093b
CH		 1547 const struct iwl3945_channel_info *ch_info = NULL;
1548 struct iwl3945_txpowertable_cmd txpower = {
b481de9c
ZY		 1549 .channel = priv->active_rxon.channel,
1550 };
1551
8318d78a 1552 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
bb8c093b 1553 ch_info = iwl3945_get_channel_info(priv,
8318d78a 1554 priv->band,
b481de9c
ZY		 1555 le16_to_cpu(priv->active_rxon.channel));
1556 if (!ch_info) {
1557 IWL_ERROR
1558 ("Failed to get channel info for channel %d [%d]\n",
8318d78a 1559 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1560 return -EINVAL;
1561 }
1562
1563 if (!is_channel_valid(ch_info)) {
1564 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1565 "non-Tx channel.\n");
1566 return 0;
1567 }
1568
1569 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1570 /* Fill OFDM rate */
1571 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1572 rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) {
1573
1574 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1575 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c
ZY		 1576
1577 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1578 le16_to_cpu(txpower.channel),
1579 txpower.band,
14577f23
MA		 1580 txpower.power[i].tpc.tx_gain,
1581 txpower.power[i].tpc.dsp_atten,
1582 txpower.power[i].rate);
1583 }
1584 /* Fill CCK rates */
1585 for (rate_idx = IWL_FIRST_CCK_RATE;
1586 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1587 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1588 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23
MA		 1589
1590 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1591 le16_to_cpu(txpower.channel),
1592 txpower.band,
1593 txpower.power[i].tpc.tx_gain,
1594 txpower.power[i].tpc.dsp_atten,
1595 txpower.power[i].rate);
b481de9c
ZY		 1596 }
1597
bb8c093b
CH		 1598 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1599 sizeof(struct iwl3945_txpowertable_cmd), &txpower);
b481de9c
ZY		 1600
1601}
1602
1603/**
bb8c093b 1604 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1605 * @ch_info: Channel to update. Uses power_info.requested_power.
1606 *
1607 * Replace requested_power and base_power_index ch_info fields for
1608 * one channel.
1609 *
1610 * Called if user or spectrum management changes power preferences.
1611 * Takes into account h/w and modulation limitations (clip power).
1612 *
1613 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1614 *
1615 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1616 * properly fill out the scan powers, and actual h/w gain settings,
1617 * and send changes to NIC
1618 */
bb8c093b
CH		 1619static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv,
1620 struct iwl3945_channel_info *ch_info)
b481de9c 1621{
bb8c093b 1622 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1623 int power_changed = 0;
1624 int i;
1625 const s8 *clip_pwrs;
1626 int power;
1627
1628 /* Get this chnlgrp's rate-to-max/clip-powers table */
1629 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1630
1631 /* Get this channel's rate-to-current-power settings table */
1632 power_info = ch_info->power_info;
1633
1634 /* update OFDM Txpower settings */
14577f23 1635 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1636 i++, ++power_info) {
1637 int delta_idx;
1638
1639 /* limit new power to be no more than h/w capability */
1640 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1641 if (power == power_info->requested_power)
1642 continue;
1643
1644 /* find difference between old and new requested powers,
1645 * update base (non-temp-compensated) power index */
1646 delta_idx = (power - power_info->requested_power) * 2;
1647 power_info->base_power_index -= delta_idx;
1648
1649 /* save new requested power value */
1650 power_info->requested_power = power;
1651
1652 power_changed = 1;
1653 }
1654
1655 /* update CCK Txpower settings, based on OFDM 12M setting ...
1656 * ... all CCK power settings for a given channel are the *same*. */
1657 if (power_changed) {
1658 power =
14577f23 1659 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1660 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1661
bb8c093b 1662 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1663 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1664 power_info->requested_power = power;
1665 power_info->base_power_index =
14577f23 1666 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1667 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1668 ++power_info;
1669 }
1670 }
1671
1672 return 0;
1673}
1674
1675/**
bb8c093b 1676 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1677 *
1678 * NOTE: Returned power limit may be less (but not more) than requested,
1679 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1680 * (no consideration for h/w clipping limitations).
1681 */
bb8c093b 1682static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl3945_channel_info *ch_info)
b481de9c
ZY		 1683{
1684 s8 max_power;
1685
1686#if 0
1687 /* if we're using TGd limits, use lower of TGd or EEPROM */
1688 if (ch_info->tgd_data.max_power != 0)
1689 max_power = min(ch_info->tgd_data.max_power,
1690 ch_info->eeprom.max_power_avg);
1691
1692 /* else just use EEPROM limits */
1693 else
1694#endif
1695 max_power = ch_info->eeprom.max_power_avg;
1696
1697 return min(max_power, ch_info->max_power_avg);
1698}
1699
1700/**
bb8c093b 1701 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1702 *
1703 * Compensate txpower settings of *all* channels for temperature.
1704 * This only accounts for the difference between current temperature
1705 * and the factory calibration temperatures, and bases the new settings
1706 * on the channel's base_power_index.
1707 *
1708 * If RxOn is "associated", this sends the new Txpower to NIC!
1709 */
bb8c093b 1710static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv)
b481de9c 1711{
bb8c093b 1712 struct iwl3945_channel_info *ch_info = NULL;
b481de9c
ZY		 1713 int delta_index;
1714 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1715 u8 a_band;
1716 u8 rate_index;
1717 u8 scan_tbl_index;
1718 u8 i;
1719 int ref_temp;
1720 int temperature = priv->temperature;
1721
1722 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1723 for (i = 0; i < priv->channel_count; i++) {
1724 ch_info = &priv->channel_info[i];
1725 a_band = is_channel_a_band(ch_info);
1726
1727 /* Get this chnlgrp's factory calibration temperature */
1728 ref_temp = (s16)priv->eeprom.groups[ch_info->group_index].
1729 temperature;
1730
1731 /* get power index adjustment based on curr and factory
1732 * temps */
bb8c093b 1733 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1734 ref_temp);
1735
1736 /* set tx power value for all rates, OFDM and CCK */
1737 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1738 rate_index++) {
1739 int power_idx =
1740 ch_info->power_info[rate_index].base_power_index;
1741
1742 /* temperature compensate */
1743 power_idx += delta_index;
1744
1745 /* stay within table range */
bb8c093b 1746 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1747 ch_info->power_info[rate_index].
1748 power_table_index = (u8) power_idx;
1749 ch_info->power_info[rate_index].tpc =
1750 power_gain_table[a_band][power_idx];
1751 }
1752
1753 /* Get this chnlgrp's rate-to-max/clip-powers table */
1754 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1755
1756 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1757 for (scan_tbl_index = 0;
1758 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1759 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1760 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1761 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1762 actual_index, clip_pwrs,
1763 ch_info, a_band);
1764 }
1765 }
1766
1767 /* send Txpower command for current channel to ucode */
bb8c093b 1768 return iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1769}
1770
bb8c093b 1771int iwl3945_hw_reg_set_txpower(struct iwl3945_priv *priv, s8 power)
b481de9c 1772{
bb8c093b 1773 struct iwl3945_channel_info *ch_info;
b481de9c
ZY		 1774 s8 max_power;
1775 u8 a_band;
1776 u8 i;
1777
1778 if (priv->user_txpower_limit == power) {
1779 IWL_DEBUG_POWER("Requested Tx power same as current "
1780 "limit: %ddBm.\n", power);
1781 return 0;
1782 }
1783
1784 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1785 priv->user_txpower_limit = power;
1786
1787 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1788
1789 for (i = 0; i < priv->channel_count; i++) {
1790 ch_info = &priv->channel_info[i];
1791 a_band = is_channel_a_band(ch_info);
1792
1793 /* find minimum power of all user and regulatory constraints
1794 * (does not consider h/w clipping limitations) */
bb8c093b 1795 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1796 max_power = min(power, max_power);
1797 if (max_power != ch_info->curr_txpow) {
1798 ch_info->curr_txpow = max_power;
1799
1800 /* this considers the h/w clipping limitations */
bb8c093b 1801 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1802 }
1803 }
1804
1805 /* update txpower settings for all channels,
1806 * send to NIC if associated. */
1807 is_temp_calib_needed(priv);
bb8c093b 1808 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1809
1810 return 0;
1811}
1812
1813/* will add 3945 channel switch cmd handling later */
bb8c093b 1814int iwl3945_hw_channel_switch(struct iwl3945_priv *priv, u16 channel)
b481de9c
ZY		 1815{
1816 return 0;
1817}
1818
1819/**
1820 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1821 *
1822 * -- reset periodic timer
1823 * -- see if temp has changed enough to warrant re-calibration ... if so:
1824 * -- correct coeffs for temp (can reset temp timer)
1825 * -- save this temp as "last",
1826 * -- send new set of gain settings to NIC
1827 * NOTE: This should continue working, even when we're not associated,
1828 * so we can keep our internal table of scan powers current. */
bb8c093b 1829void iwl3945_reg_txpower_periodic(struct iwl3945_priv *priv)
b481de9c
ZY		 1830{
1831 /* This will kick in the "brute force"
bb8c093b 1832 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 1833 if (!is_temp_calib_needed(priv))
1834 goto reschedule;
1835
1836 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1837 * This is based *only* on current temperature,
1838 * ignoring any previous power measurements */
bb8c093b 1839 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1840
1841 reschedule:
1842 queue_delayed_work(priv->workqueue,
1843 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1844}
1845
416e1438 1846static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 1847{
bb8c093b 1848 struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv,
b481de9c
ZY		 1849 thermal_periodic.work);
1850
1851 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1852 return;
1853
1854 mutex_lock(&priv->mutex);
1855 iwl3945_reg_txpower_periodic(priv);
1856 mutex_unlock(&priv->mutex);
1857}
1858
1859/**
bb8c093b 1860 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 1861 * for the channel.
1862 *
1863 * This function is used when initializing channel-info structs.
1864 *
1865 * NOTE: These channel groups do *NOT* match the bands above!
1866 * These channel groups are based on factory-tested channels;
1867 * on A-band, EEPROM's "group frequency" entries represent the top
1868 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1869 */
bb8c093b
CH		 1870static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl3945_priv *priv,
1871 const struct iwl3945_channel_info *ch_info)
b481de9c 1872{
bb8c093b 1873 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0];
b481de9c
ZY		 1874 u8 group;
1875 u16 group_index = 0; /* based on factory calib frequencies */
1876 u8 grp_channel;
1877
1878 /* Find the group index for the channel ... don't use index 1(?) */
1879 if (is_channel_a_band(ch_info)) {
1880 for (group = 1; group < 5; group++) {
1881 grp_channel = ch_grp[group].group_channel;
1882 if (ch_info->channel <= grp_channel) {
1883 group_index = group;
1884 break;
1885 }
1886 }
1887 /* group 4 has a few channels *above* its factory cal freq */
1888 if (group == 5)
1889 group_index = 4;
1890 } else
1891 group_index = 0; /* 2.4 GHz, group 0 */
1892
1893 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
1894 group_index);
1895 return group_index;
1896}
1897
1898/**
bb8c093b 1899 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 1900 *
1901 * Interpolate to get nominal (i.e. at factory calibration temperature) index
1902 * into radio/DSP gain settings table for requested power.
1903 */
bb8c093b 1904static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv,
b481de9c
ZY		 1905 s8 requested_power,
1906 s32 setting_index, s32 *new_index)
1907{
bb8c093b 1908 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
b481de9c
ZY		 1909 s32 index0, index1;
1910 s32 power = 2 * requested_power;
1911 s32 i;
bb8c093b 1912 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 1913 s32 gains0, gains1;
1914 s32 res;
1915 s32 denominator;
1916
1917 chnl_grp = &priv->eeprom.groups[setting_index];
1918 samples = chnl_grp->samples;
1919 for (i = 0; i < 5; i++) {
1920 if (power == samples[i].power) {
1921 *new_index = samples[i].gain_index;
1922 return 0;
1923 }
1924 }
1925
1926 if (power > samples[1].power) {
1927 index0 = 0;
1928 index1 = 1;
1929 } else if (power > samples[2].power) {
1930 index0 = 1;
1931 index1 = 2;
1932 } else if (power > samples[3].power) {
1933 index0 = 2;
1934 index1 = 3;
1935 } else {
1936 index0 = 3;
1937 index1 = 4;
1938 }
1939
1940 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
1941 if (denominator == 0)
1942 return -EINVAL;
1943 gains0 = (s32) samples[index0].gain_index * (1 << 19);
1944 gains1 = (s32) samples[index1].gain_index * (1 << 19);
1945 res = gains0 + (gains1 - gains0) *
1946 ((s32) power - (s32) samples[index0].power) / denominator +
1947 (1 << 18);
1948 *new_index = res >> 19;
1949 return 0;
1950}
1951
bb8c093b 1952static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv)
b481de9c
ZY		 1953{
1954 u32 i;
1955 s32 rate_index;
bb8c093b 1956 const struct iwl3945_eeprom_txpower_group *group;
b481de9c
ZY		 1957
1958 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
1959
1960 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
1961 s8 *clip_pwrs; /* table of power levels for each rate */
1962 s8 satur_pwr; /* saturation power for each chnl group */
1963 group = &priv->eeprom.groups[i];
1964
1965 /* sanity check on factory saturation power value */
1966 if (group->saturation_power < 40) {
1967 IWL_WARNING("Error: saturation power is %d, "
1968 "less than minimum expected 40\n",
1969 group->saturation_power);
1970 return;
1971 }
1972
1973 /*
1974 * Derive requested power levels for each rate, based on
1975 * hardware capabilities (saturation power for band).
1976 * Basic value is 3dB down from saturation, with further
1977 * power reductions for highest 3 data rates. These
1978 * backoffs provide headroom for high rate modulation
1979 * power peaks, without too much distortion (clipping).
1980 */
1981 /* we'll fill in this array with h/w max power levels */
1982 clip_pwrs = (s8 *) priv->clip_groups[i].clip_powers;
1983
1984 /* divide factory saturation power by 2 to find -3dB level */
1985 satur_pwr = (s8) (group->saturation_power >> 1);
1986
1987 /* fill in channel group's nominal powers for each rate */
1988 for (rate_index = 0;
1989 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
1990 switch (rate_index) {
14577f23 1991 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 1992 if (i == 0) /* B/G */
1993 *clip_pwrs = satur_pwr;
1994 else /* A */
1995 *clip_pwrs = satur_pwr - 5;
1996 break;
14577f23 1997 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 1998 if (i == 0)
1999 *clip_pwrs = satur_pwr - 7;
2000 else
2001 *clip_pwrs = satur_pwr - 10;
2002 break;
14577f23 2003 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2004 if (i == 0)
2005 *clip_pwrs = satur_pwr - 9;
2006 else
2007 *clip_pwrs = satur_pwr - 12;
2008 break;
2009 default:
2010 *clip_pwrs = satur_pwr;
2011 break;
2012 }
2013 }
2014 }
2015}
2016
2017/**
2018 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2019 *
2020 * Second pass (during init) to set up priv->channel_info
2021 *
2022 * Set up Tx-power settings in our channel info database for each VALID
2023 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2024 * and current temperature.
2025 *
2026 * Since this is based on current temperature (at init time), these values may
2027 * not be valid for very long, but it gives us a starting/default point,
2028 * and allows us to active (i.e. using Tx) scan.
2029 *
2030 * This does *not* write values to NIC, just sets up our internal table.
2031 */
bb8c093b 2032int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv)
b481de9c 2033{
bb8c093b
CH		 2034 struct iwl3945_channel_info *ch_info = NULL;
2035 struct iwl3945_channel_power_info *pwr_info;
b481de9c
ZY		 2036 int delta_index;
2037 u8 rate_index;
2038 u8 scan_tbl_index;
2039 const s8 *clip_pwrs; /* array of power levels for each rate */
2040 u8 gain, dsp_atten;
2041 s8 power;
2042 u8 pwr_index, base_pwr_index, a_band;
2043 u8 i;
2044 int temperature;
2045
2046 /* save temperature reference,
2047 * so we can determine next time to calibrate */
bb8c093b 2048 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2049 priv->last_temperature = temperature;
2050
bb8c093b 2051 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2052
2053 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2054 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2055 i++, ch_info++) {
2056 a_band = is_channel_a_band(ch_info);
2057 if (!is_channel_valid(ch_info))
2058 continue;
2059
2060 /* find this channel's channel group (*not* "band") index */
2061 ch_info->group_index =
bb8c093b 2062 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2063
2064 /* Get this chnlgrp's rate->max/clip-powers table */
2065 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
2066
2067 /* calculate power index *adjustment* value according to
2068 * diff between current temperature and factory temperature */
bb8c093b 2069 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 2070 priv->eeprom.groups[ch_info->group_index].
2071 temperature);
2072
2073 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2074 ch_info->channel, delta_index, temperature +
2075 IWL_TEMP_CONVERT);
2076
2077 /* set tx power value for all OFDM rates */
2078 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2079 rate_index++) {
2080 s32 power_idx;
2081 int rc;
2082
2083 /* use channel group's clip-power table,
2084 * but don't exceed channel's max power */
2085 s8 pwr = min(ch_info->max_power_avg,
2086 clip_pwrs[rate_index]);
2087
2088 pwr_info = &ch_info->power_info[rate_index];
2089
2090 /* get base (i.e. at factory-measured temperature)
2091 * power table index for this rate's power */
bb8c093b 2092 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2093 ch_info->group_index,
2094 &power_idx);
2095 if (rc) {
2096 IWL_ERROR("Invalid power index\n");
2097 return rc;
2098 }
2099 pwr_info->base_power_index = (u8) power_idx;
2100
2101 /* temperature compensate */
2102 power_idx += delta_index;
2103
2104 /* stay within range of gain table */
bb8c093b 2105 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2106
bb8c093b 2107 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2108 pwr_info->requested_power = pwr;
2109 pwr_info->power_table_index = (u8) power_idx;
2110 pwr_info->tpc.tx_gain =
2111 power_gain_table[a_band][power_idx].tx_gain;
2112 pwr_info->tpc.dsp_atten =
2113 power_gain_table[a_band][power_idx].dsp_atten;
2114 }
2115
2116 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2117 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2118 power = pwr_info->requested_power +
2119 IWL_CCK_FROM_OFDM_POWER_DIFF;
2120 pwr_index = pwr_info->power_table_index +
2121 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2122 base_pwr_index = pwr_info->base_power_index +
2123 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2124
2125 /* stay within table range */
bb8c093b 2126 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2127 gain = power_gain_table[a_band][pwr_index].tx_gain;
2128 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2129
bb8c093b 2130 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2131 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2132 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2133 for (rate_index = 0;
2134 rate_index < IWL_CCK_RATES; rate_index++) {
2135 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2136 pwr_info->requested_power = power;
2137 pwr_info->power_table_index = pwr_index;
2138 pwr_info->base_power_index = base_pwr_index;
2139 pwr_info->tpc.tx_gain = gain;
2140 pwr_info->tpc.dsp_atten = dsp_atten;
2141 }
2142
2143 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2144 for (scan_tbl_index = 0;
2145 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2146 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2147 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2148 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2149 actual_index, clip_pwrs, ch_info, a_band);
2150 }
2151 }
2152
2153 return 0;
2154}
2155
bb8c093b 2156int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv)
b481de9c
ZY		 2157{
2158 int rc;
2159 unsigned long flags;
2160
2161 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2162 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 2163 if (rc) {
2164 spin_unlock_irqrestore(&priv->lock, flags);
2165 return rc;
2166 }
2167
bb8c093b
CH		 2168 iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
2169 rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000);
b481de9c
ZY		 2170 if (rc < 0)
2171 IWL_ERROR("Can't stop Rx DMA.\n");
2172
bb8c093b 2173 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2174 spin_unlock_irqrestore(&priv->lock, flags);
2175
2176 return 0;
2177}
2178
bb8c093b 2179int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c
ZY		 2180{
2181 int rc;
2182 unsigned long flags;
2183 int txq_id = txq->q.id;
2184
bb8c093b 2185 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 2186
2187 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2188
2189 spin_lock_irqsave(&priv->lock, flags);
bb8c093b 2190 rc = iwl3945_grab_nic_access(priv);
b481de9c
ZY		 2191 if (rc) {
2192 spin_unlock_irqrestore(&priv->lock, flags);
2193 return rc;
2194 }
bb8c093b
CH		 2195 iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
2196 iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
b481de9c 2197
bb8c093b 2198 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
b481de9c
ZY		 2199 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2200 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2201 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2202 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2203 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
bb8c093b 2204 iwl3945_release_nic_access(priv);
b481de9c
ZY		 2205
2206 /* fake read to flush all prev. writes */
bb8c093b 2207 iwl3945_read32(priv, FH_TSSR_CBB_BASE);
b481de9c
ZY		 2208 spin_unlock_irqrestore(&priv->lock, flags);
2209
2210 return 0;
2211}
2212
bb8c093b 2213int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv)
b481de9c 2214{
bb8c093b 2215 struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 2216
2217 return le32_to_cpu(shared_data->rx_read_ptr[0]);
2218}
2219
2220/**
2221 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2222 */
bb8c093b 2223int iwl3945_init_hw_rate_table(struct iwl3945_priv *priv)
b481de9c 2224{
14577f23 2225 int rc, i, index, prev_index;
bb8c093b 2226 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2227 .reserved = {0, 0, 0},
2228 };
bb8c093b 2229 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2230
bb8c093b
CH		 2231 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2232 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2233
2234 table[index].rate_n_flags =
bb8c093b 2235 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2236 table[index].try_cnt = priv->retry_rate;
bb8c093b
CH		 2237 prev_index = iwl3945_get_prev_ieee_rate(i);
2238 table[index].next_rate_index = iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2239 }
2240
8318d78a
JB		 2241 switch (priv->band) {
2242 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 2243 IWL_DEBUG_RATE("Select A mode rate scale\n");
2244 /* If one of the following CCK rates is used,
2245 * have it fall back to the 6M OFDM rate */
14577f23 2246 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++)
bb8c093b 2247 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2248
2249 /* Don't fall back to CCK rates */
14577f23 2250 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2251
2252 /* Don't drop out of OFDM rates */
14577f23 2253 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2254 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2255 break;
2256
8318d78a
JB		 2257 case IEEE80211_BAND_2GHZ:
2258 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
b481de9c
ZY		 2259 /* If an OFDM rate is used, have it fall back to the
2260 * 1M CCK rates */
14577f23 2261 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; i++)
bb8c093b 2262 table[i].next_rate_index = iwl3945_rates[IWL_FIRST_CCK_RATE].table_rs_index;
b481de9c
ZY		 2263
2264 /* CCK shouldn't fall back to OFDM... */
14577f23 2265 table[IWL_RATE_11M_INDEX_TABLE].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
b481de9c
ZY		 2266 break;
2267
2268 default:
8318d78a 2269 WARN_ON(1);
b481de9c
ZY		 2270 break;
2271 }
2272
2273 /* Update the rate scaling for control frame Tx */
2274 rate_cmd.table_id = 0;
bb8c093b 2275 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2276 &rate_cmd);
2277 if (rc)
2278 return rc;
2279
2280 /* Update the rate scaling for data frame Tx */
2281 rate_cmd.table_id = 1;
bb8c093b 2282 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2283 &rate_cmd);
2284}
2285
796083cb 2286/* Called when initializing driver */
bb8c093b 2287int iwl3945_hw_set_hw_setting(struct iwl3945_priv *priv)
b481de9c
ZY		 2288{
2289 memset((void *)&priv->hw_setting, 0,
bb8c093b 2290 sizeof(struct iwl3945_driver_hw_info));
b481de9c
ZY		 2291
2292 priv->hw_setting.shared_virt =
2293 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2294 sizeof(struct iwl3945_shared),
b481de9c
ZY		 2295 &priv->hw_setting.shared_phys);
2296
2297 if (!priv->hw_setting.shared_virt) {
2298 IWL_ERROR("failed to allocate pci memory\n");
2299 mutex_unlock(&priv->mutex);
2300 return -ENOMEM;
2301 }
2302
2303 priv->hw_setting.ac_queue_count = AC_NUM;
9ee1ba47
RR		 2304 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE;
2305 priv->hw_setting.max_pkt_size = 2342;
bb8c093b 2306 priv->hw_setting.tx_cmd_len = sizeof(struct iwl3945_tx_cmd);
b481de9c
ZY		 2307 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
2308 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
b481de9c
ZY		 2309 priv->hw_setting.max_stations = IWL3945_STATION_COUNT;
2310 priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID;
2311 return 0;
2312}
2313
bb8c093b
CH		 2314unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv,
2315 struct iwl3945_frame *frame, u8 rate)
b481de9c 2316{
bb8c093b 2317 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2318 unsigned int frame_size;
2319
bb8c093b 2320 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2321 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2322
2323 tx_beacon_cmd->tx.sta_id = IWL3945_BROADCAST_ID;
2324 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2325
bb8c093b 2326 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2327 tx_beacon_cmd->frame,
bb8c093b 2328 iwl3945_broadcast_addr,
b481de9c
ZY		 2329 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2330
2331 BUG_ON(frame_size > MAX_MPDU_SIZE);
2332 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2333
2334 tx_beacon_cmd->tx.rate = rate;
2335 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2336 TX_CMD_FLG_TSF_MSK);
2337
14577f23
MA		 2338 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2339 tx_beacon_cmd->tx.supp_rates[0] =
2340 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2341
b481de9c 2342 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2343 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2344
bb8c093b 2345 return (sizeof(struct iwl3945_tx_beacon_cmd) + frame_size);
b481de9c
ZY		 2346}
2347
bb8c093b 2348void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv)
b481de9c
ZY		 2349{
2350 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2351}
2352
bb8c093b 2353void iwl3945_hw_setup_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 2354{
2355 INIT_DELAYED_WORK(&priv->thermal_periodic,
2356 iwl3945_bg_reg_txpower_periodic);
2357}
2358
bb8c093b 2359void iwl3945_hw_cancel_deferred_work(struct iwl3945_priv *priv)
b481de9c
ZY		 2360{
2361 cancel_delayed_work(&priv->thermal_periodic);
2362}
2363
bb8c093b 2364struct pci_device_id iwl3945_hw_card_ids[] = {
3567c11d
ZY		 2365 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4222)},
2366 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4227)},
b481de9c
ZY		 2367 {0}
2368};
2369
bb8c093b 2370MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Linux kernel - Deliverables
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