projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
iwlwifi: beacon format related helper function
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c 29#include <linux/init.h>
5a0e3ad6 30#include <linux/slab.h>
b481de9c
ZY		 31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
d43c36dc 34#include <linux/sched.h>
b481de9c
ZY		 35#include <linux/skbuff.h>
36#include <linux/netdevice.h>
37#include <linux/wireless.h>
38#include <linux/firmware.h>
b481de9c 39#include <linux/etherdevice.h>
12342c47
ZY		 40#include <asm/unaligned.h>
41#include <net/mac80211.h>
b481de9c 42
dbb6654c 43#include "iwl-fh.h"
bddadf86 44#include "iwl-3945-fh.h"
600c0e11 45#include "iwl-commands.h"
17f841cd 46#include "iwl-sta.h"
b481de9c 47#include "iwl-3945.h"
e6148917 48#include "iwl-eeprom.h"
5747d47f 49#include "iwl-core.h"
4a6547c7 50#include "iwl-helpers.h"
e932a609
JB		 51#include "iwl-led.h"
52#include "iwl-3945-led.h"
17f36fc6 53#include "iwl-3945-debugfs.h"
b481de9c
ZY		 54
55#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
56 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
57 IWL_RATE_##r##M_IEEE, \
58 IWL_RATE_##ip##M_INDEX, \
59 IWL_RATE_##in##M_INDEX, \
60 IWL_RATE_##rp##M_INDEX, \
61 IWL_RATE_##rn##M_INDEX, \
62 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 63 IWL_RATE_##np##M_INDEX, \
64 IWL_RATE_##r##M_INDEX_TABLE, \
65 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 66
67/*
68 * Parameter order:
69 * rate, prev rate, next rate, prev tgg rate, next tgg rate
70 *
71 * If there isn't a valid next or previous rate then INV is used which
72 * maps to IWL_RATE_INVALID
73 *
74 */
d9829a67 75const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 76 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
77 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
78 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
79 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 80 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
81 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
82 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
83 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
84 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
85 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
86 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
87 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 88};
89
bb8c093b 90/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 91#define IWL_EVT_DISABLE (0)
92#define IWL_EVT_DISABLE_SIZE (1532/32)
93
94/**
bb8c093b 95 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 96 *
97 * Disable an event by writing "1"s into "disable"
98 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
99 * Default values of 0 enable uCode events to be logged.
100 * Use for only special debugging. This function is just a placeholder as-is,
101 * you'll need to provide the special bits! ...
102 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 103void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 104{
b481de9c
ZY		 105 int i;
106 u32 base; /* SRAM address of event log header */
107 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
108 u32 array_size; /* # of u32 entries in array */
109 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
110 0x00000000, /* 31 - 0 Event id numbers */
111 0x00000000, /* 63 - 32 */
112 0x00000000, /* 95 - 64 */
113 0x00000000, /* 127 - 96 */
114 0x00000000, /* 159 - 128 */
115 0x00000000, /* 191 - 160 */
116 0x00000000, /* 223 - 192 */
117 0x00000000, /* 255 - 224 */
118 0x00000000, /* 287 - 256 */
119 0x00000000, /* 319 - 288 */
120 0x00000000, /* 351 - 320 */
121 0x00000000, /* 383 - 352 */
122 0x00000000, /* 415 - 384 */
123 0x00000000, /* 447 - 416 */
124 0x00000000, /* 479 - 448 */
125 0x00000000, /* 511 - 480 */
126 0x00000000, /* 543 - 512 */
127 0x00000000, /* 575 - 544 */
128 0x00000000, /* 607 - 576 */
129 0x00000000, /* 639 - 608 */
130 0x00000000, /* 671 - 640 */
131 0x00000000, /* 703 - 672 */
132 0x00000000, /* 735 - 704 */
133 0x00000000, /* 767 - 736 */
134 0x00000000, /* 799 - 768 */
135 0x00000000, /* 831 - 800 */
136 0x00000000, /* 863 - 832 */
137 0x00000000, /* 895 - 864 */
138 0x00000000, /* 927 - 896 */
139 0x00000000, /* 959 - 928 */
140 0x00000000, /* 991 - 960 */
141 0x00000000, /* 1023 - 992 */
142 0x00000000, /* 1055 - 1024 */
143 0x00000000, /* 1087 - 1056 */
144 0x00000000, /* 1119 - 1088 */
145 0x00000000, /* 1151 - 1120 */
146 0x00000000, /* 1183 - 1152 */
147 0x00000000, /* 1215 - 1184 */
148 0x00000000, /* 1247 - 1216 */
149 0x00000000, /* 1279 - 1248 */
150 0x00000000, /* 1311 - 1280 */
151 0x00000000, /* 1343 - 1312 */
152 0x00000000, /* 1375 - 1344 */
153 0x00000000, /* 1407 - 1376 */
154 0x00000000, /* 1439 - 1408 */
155 0x00000000, /* 1471 - 1440 */
156 0x00000000, /* 1503 - 1472 */
157 };
158
159 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 160 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 161 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 162 return;
163 }
164
5d49f498
AK		 165 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
166 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
b481de9c
ZY		 167
168 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
e1623446 169 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
b481de9c 170 disable_ptr);
b481de9c 171 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 172 iwl_write_targ_mem(priv,
af7cca2a
TW		 173 disable_ptr + (i * sizeof(u32)),
174 evt_disable[i]);
b481de9c 175
b481de9c 176 } else {
e1623446
TW		 177 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
178 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
179 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
b481de9c
ZY		 180 disable_ptr, array_size);
181 }
182
183}
184
17744ff6
TW		 185static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
186{
187 int idx;
188
1d79e53c 189 for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
17744ff6
TW		 190 if (iwl3945_rates[idx].plcp == plcp)
191 return idx;
192 return -1;
193}
194
d08853a3 195#ifdef CONFIG_IWLWIFI_DEBUG
04569cbe 196#define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
91c066f2
TW		 197
198static const char *iwl3945_get_tx_fail_reason(u32 status)
199{
200 switch (status & TX_STATUS_MSK) {
04569cbe 201 case TX_3945_STATUS_SUCCESS:
91c066f2
TW		 202 return "SUCCESS";
203 TX_STATUS_ENTRY(SHORT_LIMIT);
204 TX_STATUS_ENTRY(LONG_LIMIT);
205 TX_STATUS_ENTRY(FIFO_UNDERRUN);
206 TX_STATUS_ENTRY(MGMNT_ABORT);
207 TX_STATUS_ENTRY(NEXT_FRAG);
208 TX_STATUS_ENTRY(LIFE_EXPIRE);
209 TX_STATUS_ENTRY(DEST_PS);
210 TX_STATUS_ENTRY(ABORTED);
211 TX_STATUS_ENTRY(BT_RETRY);
212 TX_STATUS_ENTRY(STA_INVALID);
213 TX_STATUS_ENTRY(FRAG_DROPPED);
214 TX_STATUS_ENTRY(TID_DISABLE);
215 TX_STATUS_ENTRY(FRAME_FLUSHED);
216 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
217 TX_STATUS_ENTRY(TX_LOCKED);
218 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
219 }
220
221 return "UNKNOWN";
222}
223#else
224static inline const char *iwl3945_get_tx_fail_reason(u32 status)
225{
226 return "";
227}
228#endif
229
e6a9854b
JB		 230/*
231 * get ieee prev rate from rate scale table.
232 * for A and B mode we need to overright prev
233 * value
234 */
4a8a4322 235int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 236{
237 int next_rate = iwl3945_get_prev_ieee_rate(rate);
238
239 switch (priv->band) {
240 case IEEE80211_BAND_5GHZ:
241 if (rate == IWL_RATE_12M_INDEX)
242 next_rate = IWL_RATE_9M_INDEX;
243 else if (rate == IWL_RATE_6M_INDEX)
244 next_rate = IWL_RATE_6M_INDEX;
245 break;
7262796a 246 case IEEE80211_BAND_2GHZ:
ee525d13 247 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 248 iwl_is_associated(priv)) {
7262796a
AM		 249 if (rate == IWL_RATE_11M_INDEX)
250 next_rate = IWL_RATE_5M_INDEX;
251 }
e6a9854b 252 break;
7262796a 253
e6a9854b
JB		 254 default:
255 break;
256 }
257
258 return next_rate;
259}
260
91c066f2
TW		 261
262/**
263 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
264 *
265 * When FW advances 'R' index, all entries between old and new 'R' index
266 * need to be reclaimed. As result, some free space forms. If there is
267 * enough free space (> low mark), wake the stack that feeds us.
268 */
4a8a4322 269static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 270 int txq_id, int index)
271{
188cf6c7 272 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 273 struct iwl_queue *q = &txq->q;
dbb6654c 274 struct iwl_tx_info *tx_info;
91c066f2
TW		 275
276 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
277
278 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
279 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
280
281 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 282 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 283 tx_info->skb[0] = NULL;
7aaa1d79 284 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 285 }
286
d20b3c65 287 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 288 (txq_id != IWL_CMD_QUEUE_NUM) &&
289 priv->mac80211_registered)
e4e72fb4 290 iwl_wake_queue(priv, txq_id);
91c066f2
TW		 291}
292
293/**
294 * iwl3945_rx_reply_tx - Handle Tx response
295 */
4a8a4322 296static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
17f36fc6 297 struct iwl_rx_mem_buffer *rxb)
91c066f2 298{
2f301227 299 struct iwl_rx_packet *pkt = rxb_addr(rxb);
91c066f2
TW		 300 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
301 int txq_id = SEQ_TO_QUEUE(sequence);
302 int index = SEQ_TO_INDEX(sequence);
188cf6c7 303 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 304 struct ieee80211_tx_info *info;
91c066f2
TW		 305 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
306 u32 status = le32_to_cpu(tx_resp->status);
307 int rate_idx;
74221d07 308 int fail;
91c066f2 309
625a381a 310 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 311 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 312 "is out of range [0-%d] %d %d\n", txq_id,
313 index, txq->q.n_bd, txq->q.write_ptr,
314 txq->q.read_ptr);
315 return;
316 }
317
e039fa4a 318 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 319 ieee80211_tx_info_clear_status(info);
320
321 /* Fill the MRR chain with some info about on-chip retransmissions */
322 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
323 if (info->band == IEEE80211_BAND_5GHZ)
324 rate_idx -= IWL_FIRST_OFDM_RATE;
325
326 fail = tx_resp->failure_frame;
74221d07
AM		 327
328 info->status.rates[0].idx = rate_idx;
329 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 330
91c066f2 331 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 332 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
333 IEEE80211_TX_STAT_ACK : 0;
91c066f2 334
e1623446 335 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
91c066f2
TW		 336 txq_id, iwl3945_get_tx_fail_reason(status), status,
337 tx_resp->rate, tx_resp->failure_frame);
338
e1623446 339 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
91c066f2
TW		 340 iwl3945_tx_queue_reclaim(priv, txq_id, index);
341
342 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 343 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 344}
345
346
347
b481de9c
ZY		 348/*****************************************************************************
349 *
350 * Intel PRO/Wireless 3945ABG/BG Network Connection
351 *
352 * RX handler implementations
353 *
b481de9c 354 *****************************************************************************/
d73e4923 355#ifdef CONFIG_IWLWIFI_DEBUGFS
17f36fc6
AK		 356/*
357 * based on the assumption of all statistics counter are in DWORD
358 * FIXME: This function is for debugging, do not deal with
359 * the case of counters roll-over.
360 */
361static void iwl3945_accumulative_statistics(struct iwl_priv *priv,
362 __le32 *stats)
363{
364 int i;
365 __le32 *prev_stats;
366 u32 *accum_stats;
367 u32 *delta, *max_delta;
368
369 prev_stats = (__le32 *)&priv->_3945.statistics;
370 accum_stats = (u32 *)&priv->_3945.accum_statistics;
371 delta = (u32 *)&priv->_3945.delta_statistics;
372 max_delta = (u32 *)&priv->_3945.max_delta;
373
374 for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics);
375 i += sizeof(__le32), stats++, prev_stats++, delta++,
376 max_delta++, accum_stats++) {
377 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
378 *delta = (le32_to_cpu(*stats) -
379 le32_to_cpu(*prev_stats));
380 *accum_stats += *delta;
381 if (*delta > *max_delta)
382 *max_delta = *delta;
383 }
384 }
385
386 /* reset accumulative statistics for "no-counter" type statistics */
387 priv->_3945.accum_statistics.general.temperature =
388 priv->_3945.statistics.general.temperature;
389 priv->_3945.accum_statistics.general.ttl_timestamp =
390 priv->_3945.statistics.general.ttl_timestamp;
391}
392#endif
b481de9c 393
a29576a7
AK		 394/**
395 * iwl3945_good_plcp_health - checks for plcp error.
396 *
397 * When the plcp error is exceeding the thresholds, reset the radio
398 * to improve the throughput.
399 */
400static bool iwl3945_good_plcp_health(struct iwl_priv *priv,
401 struct iwl_rx_packet *pkt)
402{
403 bool rc = true;
404 struct iwl3945_notif_statistics current_stat;
405 int combined_plcp_delta;
406 unsigned int plcp_msec;
407 unsigned long plcp_received_jiffies;
408
409 memcpy(&current_stat, pkt->u.raw, sizeof(struct
410 iwl3945_notif_statistics));
411 /*
412 * check for plcp_err and trigger radio reset if it exceeds
413 * the plcp error threshold plcp_delta.
414 */
415 plcp_received_jiffies = jiffies;
416 plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies -
417 (long) priv->plcp_jiffies);
418 priv->plcp_jiffies = plcp_received_jiffies;
419 /*
420 * check to make sure plcp_msec is not 0 to prevent division
421 * by zero.
422 */
423 if (plcp_msec) {
424 combined_plcp_delta =
425 (le32_to_cpu(current_stat.rx.ofdm.plcp_err) -
426 le32_to_cpu(priv->_3945.statistics.rx.ofdm.plcp_err));
427
428 if ((combined_plcp_delta > 0) &&
429 ((combined_plcp_delta * 100) / plcp_msec) >
430 priv->cfg->plcp_delta_threshold) {
431 /*
432 * if plcp_err exceed the threshold, the following
433 * data is printed in csv format:
434 * Text: plcp_err exceeded %d,
435 * Received ofdm.plcp_err,
436 * Current ofdm.plcp_err,
437 * combined_plcp_delta,
438 * plcp_msec
439 */
440 IWL_DEBUG_RADIO(priv, "plcp_err exceeded %u, "
441 "%u, %d, %u mSecs\n",
442 priv->cfg->plcp_delta_threshold,
443 le32_to_cpu(current_stat.rx.ofdm.plcp_err),
444 combined_plcp_delta, plcp_msec);
445 /*
446 * Reset the RF radio due to the high plcp
447 * error rate
448 */
449 rc = false;
450 }
451 }
452 return rc;
453}
454
396887a2
DH		 455void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
456 struct iwl_rx_mem_buffer *rxb)
b481de9c 457{
2f301227 458 struct iwl_rx_packet *pkt = rxb_addr(rxb);
17f36fc6 459
e1623446 460 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
bb8c093b 461 (int)sizeof(struct iwl3945_notif_statistics),
396887a2 462 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
d73e4923 463#ifdef CONFIG_IWLWIFI_DEBUGFS
17f36fc6
AK		 464 iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
465#endif
a29576a7 466 iwl_recover_from_statistics(priv, pkt);
b481de9c 467
ee525d13 468 memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
b481de9c
ZY		 469}
470
17f36fc6
AK		 471void iwl3945_reply_statistics(struct iwl_priv *priv,
472 struct iwl_rx_mem_buffer *rxb)
473{
474 struct iwl_rx_packet *pkt = rxb_addr(rxb);
475 __le32 *flag = (__le32 *)&pkt->u.raw;
476
477 if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
d73e4923 478#ifdef CONFIG_IWLWIFI_DEBUGFS
17f36fc6
AK		 479 memset(&priv->_3945.accum_statistics, 0,
480 sizeof(struct iwl3945_notif_statistics));
481 memset(&priv->_3945.delta_statistics, 0,
482 sizeof(struct iwl3945_notif_statistics));
483 memset(&priv->_3945.max_delta, 0,
484 sizeof(struct iwl3945_notif_statistics));
485#endif
486 IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
487 }
488 iwl3945_hw_rx_statistics(priv, rxb);
489}
490
491
17744ff6
TW		 492/******************************************************************************
493 *
494 * Misc. internal state and helper functions
495 *
496 ******************************************************************************/
17744ff6 497
4bd9b4f3 498/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 499static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 500 struct ieee80211_hdr *header)
501{
502 /* Filter incoming packets to determine if they are targeted toward
503 * this network, discarding packets coming from ourselves */
504 switch (priv->iw_mode) {
05c914fe 505 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 506 /* packets to our IBSS update information */
507 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 508 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 509 /* packets to our IBSS update information */
510 return !compare_ether_addr(header->addr2, priv->bssid);
511 default:
512 return 1;
513 }
514}
17744ff6 515
4a8a4322 516static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 517 struct iwl_rx_mem_buffer *rxb,
12342c47 518 struct ieee80211_rx_status *stats)
b481de9c 519{
2f301227 520 struct iwl_rx_packet *pkt = rxb_addr(rxb);
4bd9b4f3 521 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
bb8c093b
CH		 522 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
523 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
2f301227
ZY		 524 u16 len = le16_to_cpu(rx_hdr->len);
525 struct sk_buff *skb;
29b1b268 526 __le16 fc = hdr->frame_control;
b481de9c
ZY		 527
528 /* We received data from the HW, so stop the watchdog */
2f301227
ZY		 529 if (unlikely(len + IWL39_RX_FRAME_SIZE >
530 PAGE_SIZE << priv->hw_params.rx_page_order)) {
e1623446 531 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
b481de9c
ZY		 532 return;
533 }
534
535 /* We only process data packets if the interface is open */
536 if (unlikely(!priv->is_open)) {
e1623446
TW		 537 IWL_DEBUG_DROP_LIMIT(priv,
538 "Dropping packet while interface is not open.\n");
b481de9c
ZY		 539 return;
540 }
b481de9c 541
ecdf94b8 542 skb = dev_alloc_skb(128);
2f301227 543 if (!skb) {
ecdf94b8 544 IWL_ERR(priv, "dev_alloc_skb failed\n");
2f301227
ZY		 545 return;
546 }
b481de9c 547
9c74d9fb 548 if (!iwl3945_mod_params.sw_crypto)
8ccde88a 549 iwl_set_decrypted_flag(priv,
2f301227 550 (struct ieee80211_hdr *)rxb_addr(rxb),
b481de9c
ZY		 551 le32_to_cpu(rx_end->status), stats);
552
2f301227
ZY		 553 skb_add_rx_frag(skb, 0, rxb->page,
554 (void *)rx_hdr->payload - (void *)pkt, len);
555
29b1b268 556 iwl_update_stats(priv, false, fc, len);
2f301227 557 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
2f301227 558
29b1b268 559 ieee80211_rx(priv->hw, skb);
2f301227
ZY		 560 priv->alloc_rxb_page--;
561 rxb->page = NULL;
b481de9c
ZY		 562}
563
7878a5a4
MA		 564#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
565
4a8a4322 566static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 567 struct iwl_rx_mem_buffer *rxb)
b481de9c 568{
17744ff6
TW		 569 struct ieee80211_hdr *header;
570 struct ieee80211_rx_status rx_status;
2f301227 571 struct iwl_rx_packet *pkt = rxb_addr(rxb);
bb8c093b
CH		 572 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
573 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
574 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
f875f518
RC		 575 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
576 u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
b481de9c 577 u8 network_packet;
17744ff6 578
17744ff6
TW		 579 rx_status.flag = 0;
580 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 581 rx_status.freq =
c0186078 582 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 583 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
584 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
585
586 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 587 if (rx_status.band == IEEE80211_BAND_5GHZ)
588 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 589
9024adf5 590 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
6f0a2c4d
BR		 591 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
592
593 /* set the preamble flag if appropriate */
594 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
595 rx_status.flag |= RX_FLAG_SHORTPRE;
596
b481de9c 597 if ((unlikely(rx_stats->phy_count > 20))) {
e1623446
TW		 598 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
599 rx_stats->phy_count);
b481de9c
ZY		 600 return;
601 }
602
603 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
604 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e1623446 605 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
b481de9c
ZY		 606 return;
607 }
608
56decd3c 609
b481de9c
ZY		 610
611 /* Convert 3945's rssi indicator to dBm */
250bdd21 612 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c 613
ed1b6e99
JB		 614 IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
615 rx_status.signal, rx_stats_sig_avg,
616 rx_stats_noise_diff);
b481de9c 617
b481de9c
ZY		 618 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
619
bb8c093b 620 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 621
ed1b6e99 622 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
17744ff6
TW		 623 network_packet ? '*' : ' ',
624 le16_to_cpu(rx_hdr->channel),
566bfe5a 625 rx_status.signal, rx_status.signal,
ed1b6e99 626 rx_status.rate_idx);
b481de9c 627
20594eb0 628 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
b481de9c
ZY		 629
630 if (network_packet) {
e99f168c
JB		 631 priv->_3945.last_beacon_time =
632 le32_to_cpu(rx_end->beacon_timestamp);
633 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
634 priv->_3945.last_rx_rssi = rx_status.signal;
b481de9c
ZY		 635 }
636
12e5e22d 637 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 638}
639
7aaa1d79
SO		 640int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
641 struct iwl_tx_queue *txq,
642 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 643{
644 int count;
7aaa1d79 645 struct iwl_queue *q;
59606ffa 646 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 647
648 q = &txq->q;
59606ffa
SO		 649 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
650 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 651
652 if (reset)
653 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 654
655 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 656
657 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 658 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 659 NUM_TFD_CHUNKS);
660 return -EINVAL;
661 }
662
dbb6654c
WT		 663 tfd->tbs[count].addr = cpu_to_le32(addr);
664 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 665
666 count++;
667
668 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
669 TFD_CTL_PAD_SET(pad));
670
671 return 0;
672}
673
674/**
bb8c093b 675 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 676 *
677 * Does NOT advance any indexes
678 */
7aaa1d79 679void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 680{
59606ffa 681 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
fd9377ee
RC		 682 int index = txq->q.read_ptr;
683 struct iwl3945_tfd *tfd = &tfd_tmp[index];
b481de9c
ZY		 684 struct pci_dev *dev = priv->pci_dev;
685 int i;
686 int counter;
687
b481de9c 688 /* sanity check */
dbb6654c 689 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 690 if (counter > NUM_TFD_CHUNKS) {
15b1687c 691 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 692 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 693 return;
b481de9c
ZY		 694 }
695
fd9377ee
RC		 696 /* Unmap tx_cmd */
697 if (counter)
698 pci_unmap_single(dev,
2e724443
FT		 699 dma_unmap_addr(&txq->meta[index], mapping),
700 dma_unmap_len(&txq->meta[index], len),
fd9377ee
RC		 701 PCI_DMA_TODEVICE);
702
b481de9c
ZY		 703 /* unmap chunks if any */
704
705 for (i = 1; i < counter; i++) {
dbb6654c
WT		 706 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
707 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 708 if (txq->txb[txq->q.read_ptr].skb[0]) {
709 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
710 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 711 /* Can be called from interrupt context */
712 dev_kfree_skb_any(skb);
fc4b6853 713 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 714 }
715 }
716 }
7aaa1d79 717 return ;
b481de9c
ZY		 718}
719
b481de9c 720/**
bb8c093b 721 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 722 *
723*/
c2acea8e
JB		 724void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
725 struct iwl_device_cmd *cmd,
726 struct ieee80211_tx_info *info,
727 struct ieee80211_hdr *hdr,
728 int sta_id, int tx_id)
b481de9c 729{
e039fa4a 730 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
1d79e53c 731 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
b481de9c
ZY		 732 u16 rate_mask;
733 int rate;
734 u8 rts_retry_limit;
735 u8 data_retry_limit;
736 __le32 tx_flags;
fd7c8a40 737 __le16 fc = hdr->frame_control;
9744c91f 738 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 739
bb8c093b 740 rate = iwl3945_rates[rate_index].plcp;
9744c91f 741 tx_flags = tx_cmd->tx_flags;
b481de9c
ZY		 742
743 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 744 * in this running context */
b481de9c
ZY		 745 rate_mask = IWL_RATES_MASK;
746
768db982
AK		 747
748 /* Set retry limit on DATA packets and Probe Responses*/
749 if (ieee80211_is_probe_resp(fc))
750 data_retry_limit = 3;
751 else
752 data_retry_limit = IWL_DEFAULT_TX_RETRY;
753 tx_cmd->data_retry_limit = data_retry_limit;
754
b481de9c
ZY		 755 if (tx_id >= IWL_CMD_QUEUE_NUM)
756 rts_retry_limit = 3;
757 else
758 rts_retry_limit = 7;
759
768db982
AK		 760 if (data_retry_limit < rts_retry_limit)
761 rts_retry_limit = data_retry_limit;
762 tx_cmd->rts_retry_limit = rts_retry_limit;
b481de9c 763
fd7c8a40
HH		 764 if (ieee80211_is_mgmt(fc)) {
765 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
766 case cpu_to_le16(IEEE80211_STYPE_AUTH):
767 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
768 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
769 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 770 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
771 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
772 tx_flags |= TX_CMD_FLG_CTS_MSK;
773 }
774 break;
775 default:
776 break;
777 }
778 }
779
9744c91f
AK		 780 tx_cmd->rate = rate;
781 tx_cmd->tx_flags = tx_flags;
b481de9c
ZY		 782
783 /* OFDM */
9744c91f 784 tx_cmd->supp_rates[0] =
14577f23 785 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 786
787 /* CCK */
9744c91f 788 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
b481de9c 789
e1623446 790 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
b481de9c 791 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
9744c91f
AK		 792 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
793 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
b481de9c
ZY		 794}
795
9c5ac091 796static u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate)
b481de9c
ZY		 797{
798 unsigned long flags_spin;
c587de0b 799 struct iwl_station_entry *station;
b481de9c
ZY		 800
801 if (sta_id == IWL_INVALID_STATION)
802 return IWL_INVALID_STATION;
803
804 spin_lock_irqsave(&priv->sta_lock, flags_spin);
c587de0b 805 station = &priv->stations[sta_id];
b481de9c
ZY		 806
807 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
808 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c 809 station->sta.mode = STA_CONTROL_MODIFY_MSK;
9c5ac091 810 iwl_send_add_sta(priv, &station->sta, CMD_ASYNC);
b481de9c
ZY		 811 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
812
e1623446 813 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
b481de9c
ZY		 814 sta_id, tx_rate);
815 return sta_id;
816}
817
854682ed 818static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 819{
854682ed 820 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 821 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
5d49f498 822 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 823 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
824 ~APMG_PS_CTRL_MSK_PWR_SRC);
b481de9c 825
5d49f498 826 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 827 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
828 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
3fdb68de 829 }
b481de9c 830 } else {
5d49f498 831 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 832 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
833 ~APMG_PS_CTRL_MSK_PWR_SRC);
834
5d49f498 835 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 836 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
837 }
b481de9c 838
a8b50a0a 839 return 0;
b481de9c
ZY		 840}
841
4a8a4322 842static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c 843{
5d49f498 844 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 845 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 846 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
847 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 848 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
849 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
850 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
851 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
852 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
853 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
854 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
855 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 856
857 /* fake read to flush all prev I/O */
5d49f498 858 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 859
b481de9c
ZY		 860 return 0;
861}
862
4a8a4322 863static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c 864{
b481de9c
ZY		 865
866 /* bypass mode */
5d49f498 867 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 868
869 /* RA 0 is active */
5d49f498 870 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 871
872 /* all 6 fifo are active */
5d49f498 873 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 874
5d49f498
AK		 875 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
876 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
877 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
878 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 879
5d49f498 880 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
ee525d13 881 priv->_3945.shared_phys);
b481de9c 882
5d49f498 883 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 884 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
885 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
886 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
887 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
888 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
889 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
890 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 891
b481de9c
ZY		 892
893 return 0;
894}
895
896/**
897 * iwl3945_txq_ctx_reset - Reset TX queue context
898 *
899 * Destroys all DMA structures and initialize them again
900 */
4a8a4322 901static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 902{
903 int rc;
904 int txq_id, slots_num;
905
bb8c093b 906 iwl3945_hw_txq_ctx_free(priv);
b481de9c 907
88804e2b
WYG		 908 /* allocate tx queue structure */
909 rc = iwl_alloc_txq_mem(priv);
910 if (rc)
911 return rc;
912
b481de9c
ZY		 913 /* Tx CMD queue */
914 rc = iwl3945_tx_reset(priv);
915 if (rc)
916 goto error;
917
918 /* Tx queue(s) */
5905a1aa 919 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 920 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
921 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 922 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
923 txq_id);
b481de9c 924 if (rc) {
15b1687c 925 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 926 goto error;
927 }
928 }
929
930 return rc;
931
932 error:
bb8c093b 933 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 934 return rc;
935}
936
fadb3582 937
f33269b8 938/*
fadb3582
BC		 939 * Start up 3945's basic functionality after it has been reset
940 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
f33269b8
BC		 941 * NOTE: This does not load uCode nor start the embedded processor
942 */
01ec616d 943static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 944{
fadb3582 945 int ret = iwl_apm_init(priv);
01ec616d 946
f33269b8
BC		 947 /* Clear APMG (NIC's internal power management) interrupts */
948 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
949 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
950
951 /* Reset radio chip */
952 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
953 udelay(5);
954 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
955
01ec616d
KA		 956 return ret;
957}
b481de9c 958
01ec616d
KA		 959static void iwl3945_nic_config(struct iwl_priv *priv)
960{
e6148917 961 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 962 unsigned long flags;
963 u8 rev_id = 0;
b481de9c 964
b481de9c
ZY		 965 spin_lock_irqsave(&priv->lock, flags);
966
43121432
AK		 967 /* Determine HW type */
968 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
969
970 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
971
b481de9c 972 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
91dd6c27 973 IWL_DEBUG_INFO(priv, "RTP type\n");
b481de9c 974 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
e1623446 975 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
5d49f498 976 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 977 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 978 } else {
e1623446 979 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
5d49f498 980 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 981 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 982 }
983
e6148917 984 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
e1623446 985 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
5d49f498 986 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 987 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c 988 } else
e1623446 989 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
b481de9c 990
e6148917 991 if ((eeprom->board_revision & 0xF0) == 0xD0) {
e1623446 992 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 993 eeprom->board_revision);
5d49f498 994 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 995 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c 996 } else {
e1623446 997 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 998 eeprom->board_revision);
5d49f498 999 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1000 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1001 }
1002
e6148917 1003 if (eeprom->almgor_m_version <= 1) {
5d49f498 1004 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1005 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
e1623446 1006 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
e6148917 1007 eeprom->almgor_m_version);
b481de9c 1008 } else {
e1623446 1009 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
e6148917 1010 eeprom->almgor_m_version);
5d49f498 1011 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1012 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1013 }
1014 spin_unlock_irqrestore(&priv->lock, flags);
1015
e6148917 1016 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
e1623446 1017 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
b481de9c 1018
e6148917 1019 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
e1623446 1020 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1021}
1022
1023int iwl3945_hw_nic_init(struct iwl_priv *priv)
1024{
01ec616d
KA		 1025 int rc;
1026 unsigned long flags;
1027 struct iwl_rx_queue *rxq = &priv->rxq;
1028
1029 spin_lock_irqsave(&priv->lock, flags);
1030 priv->cfg->ops->lib->apm_ops.init(priv);
1031 spin_unlock_irqrestore(&priv->lock, flags);
1032
854682ed 1033 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1e680233 1034 if (rc)
854682ed
KA		 1035 return rc;
1036
01ec616d 1037 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1038
1039 /* Allocate the RX queue, or reset if it is already allocated */
1040 if (!rxq->bd) {
51af3d3f 1041 rc = iwl_rx_queue_alloc(priv);
b481de9c 1042 if (rc) {
15b1687c 1043 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1044 return -ENOMEM;
1045 }
1046 } else
df833b1d 1047 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1048
bb8c093b 1049 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1050
1051 iwl3945_rx_init(priv, rxq);
1052
b481de9c
ZY		 1053
1054 /* Look at using this instead:
1055 rxq->need_update = 1;
141c43a3 1056 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1057 */
1058
5d49f498 1059 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
b481de9c
ZY		 1060
1061 rc = iwl3945_txq_ctx_reset(priv);
1062 if (rc)
1063 return rc;
1064
1065 set_bit(STATUS_INIT, &priv->status);
1066
1067 return 0;
1068}
1069
1070/**
bb8c093b 1071 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1072 *
1073 * Destroy all TX DMA queues and structures
1074 */
4a8a4322 1075void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1076{
1077 int txq_id;
1078
1079 /* Tx queues */
88804e2b
WYG		 1080 if (priv->txq)
1081 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1082 txq_id++)
1083 if (txq_id == IWL_CMD_QUEUE_NUM)
1084 iwl_cmd_queue_free(priv);
1085 else
1086 iwl_tx_queue_free(priv, txq_id);
3e5d238f 1087
88804e2b
WYG		 1088 /* free tx queue structure */
1089 iwl_free_txq_mem(priv);
b481de9c
ZY		 1090}
1091
4a8a4322 1092void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1093{
bddadf86 1094 int txq_id;
b481de9c
ZY		 1095
1096 /* stop SCD */
5d49f498 1097 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1f80989e 1098 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
b481de9c
ZY		 1099
1100 /* reset TFD queues */
5905a1aa 1101 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
5d49f498
AK		 1102 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1103 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1104 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1105 1000);
1106 }
1107
bb8c093b 1108 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1109}
1110
b481de9c 1111/**
bb8c093b 1112 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1113 * return index delta into power gain settings table
1114*/
bb8c093b 1115static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1116{
1117 return (new_reading - old_reading) * (-11) / 100;
1118}
1119
1120/**
bb8c093b 1121 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1122 */
bb8c093b 1123static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1124{
3ac7f146 1125 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1126}
1127
4a8a4322 1128int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1129{
5d49f498 1130 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1131}
1132
1133/**
bb8c093b 1134 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1135 * get the current temperature by reading from NIC
1136*/
4a8a4322 1137static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1138{
e6148917 1139 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1140 int temperature;
1141
bb8c093b 1142 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1143
1144 /* driver's okay range is -260 to +25.
1145 * human readable okay range is 0 to +285 */
e1623446 1146 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
b481de9c
ZY		 1147
1148 /* handle insane temp reading */
bb8c093b 1149 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1150 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1151
1152 /* if really really hot(?),
1153 * substitute the 3rd band/group's temp measured at factory */
1154 if (priv->last_temperature > 100)
e6148917 1155 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1156 else /* else use most recent "sane" value from driver */
1157 temperature = priv->last_temperature;
1158 }
1159
1160 return temperature; /* raw, not "human readable" */
1161}
1162
1163/* Adjust Txpower only if temperature variance is greater than threshold.
1164 *
1165 * Both are lower than older versions' 9 degrees */
1166#define IWL_TEMPERATURE_LIMIT_TIMER 6
1167
1168/**
1169 * is_temp_calib_needed - determines if new calibration is needed
1170 *
1171 * records new temperature in tx_mgr->temperature.
1172 * replaces tx_mgr->last_temperature *only* if calib needed
1173 * (assumes caller will actually do the calibration!). */
4a8a4322 1174static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1175{
1176 int temp_diff;
1177
bb8c093b 1178 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1179 temp_diff = priv->temperature - priv->last_temperature;
1180
1181 /* get absolute value */
1182 if (temp_diff < 0) {
e1623446 1183 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
b481de9c
ZY		 1184 temp_diff = -temp_diff;
1185 } else if (temp_diff == 0)
e1623446 1186 IWL_DEBUG_POWER(priv, "Same temp,\n");
b481de9c 1187 else
e1623446 1188 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
b481de9c
ZY		 1189
1190 /* if we don't need calibration, *don't* update last_temperature */
1191 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
e1623446 1192 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
b481de9c
ZY		 1193 return 0;
1194 }
1195
e1623446 1196 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
b481de9c
ZY		 1197
1198 /* assume that caller will actually do calib ...
1199 * update the "last temperature" value */
1200 priv->last_temperature = priv->temperature;
1201 return 1;
1202}
1203
1204#define IWL_MAX_GAIN_ENTRIES 78
1205#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1206#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1207
1208/* radio and DSP power table, each step is 1/2 dB.
1209 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1210static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1211 {
1212 {251, 127}, /* 2.4 GHz, highest power */
1213 {251, 127},
1214 {251, 127},
1215 {251, 127},
1216 {251, 125},
1217 {251, 110},
1218 {251, 105},
1219 {251, 98},
1220 {187, 125},
1221 {187, 115},
1222 {187, 108},
1223 {187, 99},
1224 {243, 119},
1225 {243, 111},
1226 {243, 105},
1227 {243, 97},
1228 {243, 92},
1229 {211, 106},
1230 {211, 100},
1231 {179, 120},
1232 {179, 113},
1233 {179, 107},
1234 {147, 125},
1235 {147, 119},
1236 {147, 112},
1237 {147, 106},
1238 {147, 101},
1239 {147, 97},
1240 {147, 91},
1241 {115, 107},
1242 {235, 121},
1243 {235, 115},
1244 {235, 109},
1245 {203, 127},
1246 {203, 121},
1247 {203, 115},
1248 {203, 108},
1249 {203, 102},
1250 {203, 96},
1251 {203, 92},
1252 {171, 110},
1253 {171, 104},
1254 {171, 98},
1255 {139, 116},
1256 {227, 125},
1257 {227, 119},
1258 {227, 113},
1259 {227, 107},
1260 {227, 101},
1261 {227, 96},
1262 {195, 113},
1263 {195, 106},
1264 {195, 102},
1265 {195, 95},
1266 {163, 113},
1267 {163, 106},
1268 {163, 102},
1269 {163, 95},
1270 {131, 113},
1271 {131, 106},
1272 {131, 102},
1273 {131, 95},
1274 {99, 113},
1275 {99, 106},
1276 {99, 102},
1277 {99, 95},
1278 {67, 113},
1279 {67, 106},
1280 {67, 102},
1281 {67, 95},
1282 {35, 113},
1283 {35, 106},
1284 {35, 102},
1285 {35, 95},
1286 {3, 113},
1287 {3, 106},
1288 {3, 102},
1289 {3, 95} }, /* 2.4 GHz, lowest power */
1290 {
1291 {251, 127}, /* 5.x GHz, highest power */
1292 {251, 120},
1293 {251, 114},
1294 {219, 119},
1295 {219, 101},
1296 {187, 113},
1297 {187, 102},
1298 {155, 114},
1299 {155, 103},
1300 {123, 117},
1301 {123, 107},
1302 {123, 99},
1303 {123, 92},
1304 {91, 108},
1305 {59, 125},
1306 {59, 118},
1307 {59, 109},
1308 {59, 102},
1309 {59, 96},
1310 {59, 90},
1311 {27, 104},
1312 {27, 98},
1313 {27, 92},
1314 {115, 118},
1315 {115, 111},
1316 {115, 104},
1317 {83, 126},
1318 {83, 121},
1319 {83, 113},
1320 {83, 105},
1321 {83, 99},
1322 {51, 118},
1323 {51, 111},
1324 {51, 104},
1325 {51, 98},
1326 {19, 116},
1327 {19, 109},
1328 {19, 102},
1329 {19, 98},
1330 {19, 93},
1331 {171, 113},
1332 {171, 107},
1333 {171, 99},
1334 {139, 120},
1335 {139, 113},
1336 {139, 107},
1337 {139, 99},
1338 {107, 120},
1339 {107, 113},
1340 {107, 107},
1341 {107, 99},
1342 {75, 120},
1343 {75, 113},
1344 {75, 107},
1345 {75, 99},
1346 {43, 120},
1347 {43, 113},
1348 {43, 107},
1349 {43, 99},
1350 {11, 120},
1351 {11, 113},
1352 {11, 107},
1353 {11, 99},
1354 {131, 107},
1355 {131, 99},
1356 {99, 120},
1357 {99, 113},
1358 {99, 107},
1359 {99, 99},
1360 {67, 120},
1361 {67, 113},
1362 {67, 107},
1363 {67, 99},
1364 {35, 120},
1365 {35, 113},
1366 {35, 107},
1367 {35, 99},
1368 {3, 120} } /* 5.x GHz, lowest power */
1369};
1370
bb8c093b 1371static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1372{
1373 if (index < 0)
1374 return 0;
1375 if (index >= IWL_MAX_GAIN_ENTRIES)
1376 return IWL_MAX_GAIN_ENTRIES - 1;
1377 return (u8) index;
1378}
1379
1380/* Kick off thermal recalibration check every 60 seconds */
1381#define REG_RECALIB_PERIOD (60)
1382
1383/**
bb8c093b 1384 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1385 *
1386 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1387 * or 6 Mbit (OFDM) rates.
1388 */
4a8a4322 1389static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1390 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1391 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1392 int band_index)
1393{
bb8c093b 1394 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1395 s8 power;
1396 u8 power_index;
1397
1398 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1399
1400 /* use this channel group's 6Mbit clipping/saturation pwr,
1401 * but cap at regulatory scan power restriction (set during init
1402 * based on eeprom channel data) for this channel. */
14577f23 1403 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1404
1405 /* further limit to user's max power preference.
1406 * FIXME: Other spectrum management power limitations do not
1407 * seem to apply?? */
62ea9c5b 1408 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1409 scan_power_info->requested_power = power;
1410
1411 /* find difference between new scan *power* and current "normal"
1412 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1413 * current "normal" temperature-compensated Tx power *index* for
1414 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1415 * *index*. */
1416 power_index = ch_info->power_info[rate_index].power_table_index
1417 - (power - ch_info->power_info
14577f23 1418 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1419
1420 /* store reference index that we use when adjusting *all* scan
1421 * powers. So we can accommodate user (all channel) or spectrum
1422 * management (single channel) power changes "between" temperature
1423 * feedback compensation procedures.
1424 * don't force fit this reference index into gain table; it may be a
1425 * negative number. This will help avoid errors when we're at
1426 * the lower bounds (highest gains, for warmest temperatures)
1427 * of the table. */
1428
1429 /* don't exceed table bounds for "real" setting */
bb8c093b 1430 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1431
1432 scan_power_info->power_table_index = power_index;
1433 scan_power_info->tpc.tx_gain =
1434 power_gain_table[band_index][power_index].tx_gain;
1435 scan_power_info->tpc.dsp_atten =
1436 power_gain_table[band_index][power_index].dsp_atten;
1437}
1438
1439/**
75bcfae9 1440 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1441 *
1442 * Configures power settings for all rates for the current channel,
1443 * using values from channel info struct, and send to NIC
1444 */
dfb39e82 1445static int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1446{
14577f23 1447 int rate_idx, i;
d20b3c65 1448 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1449 struct iwl3945_txpowertable_cmd txpower = {
8ccde88a 1450 .channel = priv->active_rxon.channel,
b481de9c
ZY		 1451 };
1452
8318d78a 1453 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1454 ch_info = iwl_get_channel_info(priv,
8318d78a 1455 priv->band,
8ccde88a 1456 le16_to_cpu(priv->active_rxon.channel));
b481de9c 1457 if (!ch_info) {
15b1687c
WT		 1458 IWL_ERR(priv,
1459 "Failed to get channel info for channel %d [%d]\n",
8ccde88a 1460 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1461 return -EINVAL;
1462 }
1463
1464 if (!is_channel_valid(ch_info)) {
e1623446 1465 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
b481de9c
ZY		 1466 "non-Tx channel.\n");
1467 return 0;
1468 }
1469
1470 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1471 /* Fill OFDM rate */
1472 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1473 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1474
1475 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1476 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c 1477
e1623446 1478 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
b481de9c
ZY		 1479 le16_to_cpu(txpower.channel),
1480 txpower.band,
14577f23
MA		 1481 txpower.power[i].tpc.tx_gain,
1482 txpower.power[i].tpc.dsp_atten,
1483 txpower.power[i].rate);
1484 }
1485 /* Fill CCK rates */
1486 for (rate_idx = IWL_FIRST_CCK_RATE;
1487 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1488 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1489 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23 1490
e1623446 1491 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
14577f23
MA		 1492 le16_to_cpu(txpower.channel),
1493 txpower.band,
1494 txpower.power[i].tpc.tx_gain,
1495 txpower.power[i].tpc.dsp_atten,
1496 txpower.power[i].rate);
b481de9c
ZY		 1497 }
1498
518099a8
SO		 1499 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1500 sizeof(struct iwl3945_txpowertable_cmd),
1501 &txpower);
b481de9c
ZY		 1502
1503}
1504
1505/**
bb8c093b 1506 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1507 * @ch_info: Channel to update. Uses power_info.requested_power.
1508 *
1509 * Replace requested_power and base_power_index ch_info fields for
1510 * one channel.
1511 *
1512 * Called if user or spectrum management changes power preferences.
1513 * Takes into account h/w and modulation limitations (clip power).
1514 *
1515 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1516 *
1517 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1518 * properly fill out the scan powers, and actual h/w gain settings,
1519 * and send changes to NIC
1520 */
4a8a4322 1521static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1522 struct iwl_channel_info *ch_info)
b481de9c 1523{
bb8c093b 1524 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1525 int power_changed = 0;
1526 int i;
1527 const s8 *clip_pwrs;
1528 int power;
1529
1530 /* Get this chnlgrp's rate-to-max/clip-powers table */
67d613ae 1531 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1532
1533 /* Get this channel's rate-to-current-power settings table */
1534 power_info = ch_info->power_info;
1535
1536 /* update OFDM Txpower settings */
14577f23 1537 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1538 i++, ++power_info) {
1539 int delta_idx;
1540
1541 /* limit new power to be no more than h/w capability */
1542 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1543 if (power == power_info->requested_power)
1544 continue;
1545
1546 /* find difference between old and new requested powers,
1547 * update base (non-temp-compensated) power index */
1548 delta_idx = (power - power_info->requested_power) * 2;
1549 power_info->base_power_index -= delta_idx;
1550
1551 /* save new requested power value */
1552 power_info->requested_power = power;
1553
1554 power_changed = 1;
1555 }
1556
1557 /* update CCK Txpower settings, based on OFDM 12M setting ...
1558 * ... all CCK power settings for a given channel are the *same*. */
1559 if (power_changed) {
1560 power =
14577f23 1561 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1562 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1563
bb8c093b 1564 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1565 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1566 power_info->requested_power = power;
1567 power_info->base_power_index =
14577f23 1568 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1569 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1570 ++power_info;
1571 }
1572 }
1573
1574 return 0;
1575}
1576
1577/**
bb8c093b 1578 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1579 *
1580 * NOTE: Returned power limit may be less (but not more) than requested,
1581 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1582 * (no consideration for h/w clipping limitations).
1583 */
d20b3c65 1584static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1585{
1586 s8 max_power;
1587
1588#if 0
1589 /* if we're using TGd limits, use lower of TGd or EEPROM */
1590 if (ch_info->tgd_data.max_power != 0)
1591 max_power = min(ch_info->tgd_data.max_power,
1592 ch_info->eeprom.max_power_avg);
1593
1594 /* else just use EEPROM limits */
1595 else
1596#endif
1597 max_power = ch_info->eeprom.max_power_avg;
1598
1599 return min(max_power, ch_info->max_power_avg);
1600}
1601
1602/**
bb8c093b 1603 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1604 *
1605 * Compensate txpower settings of *all* channels for temperature.
1606 * This only accounts for the difference between current temperature
1607 * and the factory calibration temperatures, and bases the new settings
1608 * on the channel's base_power_index.
1609 *
1610 * If RxOn is "associated", this sends the new Txpower to NIC!
1611 */
4a8a4322 1612static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1613{
d20b3c65 1614 struct iwl_channel_info *ch_info = NULL;
e6148917 1615 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1616 int delta_index;
1617 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1618 u8 a_band;
1619 u8 rate_index;
1620 u8 scan_tbl_index;
1621 u8 i;
1622 int ref_temp;
1623 int temperature = priv->temperature;
1624
4e7033ef
WYG		 1625 if (priv->disable_tx_power_cal ||
1626 test_bit(STATUS_SCANNING, &priv->status)) {
1627 /* do not perform tx power calibration */
1628 return 0;
1629 }
b481de9c
ZY		 1630 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1631 for (i = 0; i < priv->channel_count; i++) {
1632 ch_info = &priv->channel_info[i];
1633 a_band = is_channel_a_band(ch_info);
1634
1635 /* Get this chnlgrp's factory calibration temperature */
e6148917 1636 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1637 temperature;
1638
a96a27f9 1639 /* get power index adjustment based on current and factory
b481de9c 1640 * temps */
bb8c093b 1641 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1642 ref_temp);
1643
1644 /* set tx power value for all rates, OFDM and CCK */
1645 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1646 rate_index++) {
1647 int power_idx =
1648 ch_info->power_info[rate_index].base_power_index;
1649
1650 /* temperature compensate */
1651 power_idx += delta_index;
1652
1653 /* stay within table range */
bb8c093b 1654 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1655 ch_info->power_info[rate_index].
1656 power_table_index = (u8) power_idx;
1657 ch_info->power_info[rate_index].tpc =
1658 power_gain_table[a_band][power_idx];
1659 }
1660
1661 /* Get this chnlgrp's rate-to-max/clip-powers table */
67d613ae 1662 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1663
1664 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1665 for (scan_tbl_index = 0;
1666 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1667 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1668 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1669 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1670 actual_index, clip_pwrs,
1671 ch_info, a_band);
1672 }
1673 }
1674
1675 /* send Txpower command for current channel to ucode */
75bcfae9 1676 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1677}
1678
4a8a4322 1679int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1680{
d20b3c65 1681 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1682 s8 max_power;
1683 u8 a_band;
1684 u8 i;
1685
62ea9c5b 1686 if (priv->tx_power_user_lmt == power) {
e1623446 1687 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
b481de9c
ZY		 1688 "limit: %ddBm.\n", power);
1689 return 0;
1690 }
1691
e1623446 1692 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1693 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1694
1695 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1696
1697 for (i = 0; i < priv->channel_count; i++) {
1698 ch_info = &priv->channel_info[i];
1699 a_band = is_channel_a_band(ch_info);
1700
1701 /* find minimum power of all user and regulatory constraints
1702 * (does not consider h/w clipping limitations) */
bb8c093b 1703 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1704 max_power = min(power, max_power);
1705 if (max_power != ch_info->curr_txpow) {
1706 ch_info->curr_txpow = max_power;
1707
1708 /* this considers the h/w clipping limitations */
bb8c093b 1709 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1710 }
1711 }
1712
1713 /* update txpower settings for all channels,
1714 * send to NIC if associated. */
1715 is_temp_calib_needed(priv);
bb8c093b 1716 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1717
1718 return 0;
1719}
1720
5bbe233b
AK		 1721static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1722{
1723 int rc = 0;
2f301227 1724 struct iwl_rx_packet *pkt;
5bbe233b
AK		 1725 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1726 struct iwl_host_cmd cmd = {
1727 .id = REPLY_RXON_ASSOC,
1728 .len = sizeof(rxon_assoc),
c2acea8e 1729 .flags = CMD_WANT_SKB,
5bbe233b
AK		 1730 .data = &rxon_assoc,
1731 };
1732 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1733 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1734
1735 if ((rxon1->flags == rxon2->flags) &&
1736 (rxon1->filter_flags == rxon2->filter_flags) &&
1737 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1738 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1739 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1740 return 0;
1741 }
1742
1743 rxon_assoc.flags = priv->staging_rxon.flags;
1744 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1745 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1746 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1747 rxon_assoc.reserved = 0;
1748
1749 rc = iwl_send_cmd_sync(priv, &cmd);
1750 if (rc)
1751 return rc;
1752
2f301227
ZY		 1753 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1754 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
5bbe233b
AK		 1755 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1756 rc = -EIO;
1757 }
1758
64a76b50 1759 iwl_free_pages(priv, cmd.reply_page);
5bbe233b
AK		 1760
1761 return rc;
1762}
1763
e0158e61
AK		 1764/**
1765 * iwl3945_commit_rxon - commit staging_rxon to hardware
1766 *
1767 * The RXON command in staging_rxon is committed to the hardware and
1768 * the active_rxon structure is updated with the new data. This
1769 * function correctly transitions out of the RXON_ASSOC_MSK state if
1770 * a HW tune is required based on the RXON structure changes.
1771 */
1772static int iwl3945_commit_rxon(struct iwl_priv *priv)
1773{
1774 /* cast away the const for active_rxon in this function */
1775 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1776 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1777 int rc = 0;
1778 bool new_assoc =
1779 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1780
1781 if (!iwl_is_alive(priv))
1782 return -1;
1783
1784 /* always get timestamp with Rx frame */
1785 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1786
1787 /* select antenna */
1788 staging_rxon->flags &=
1789 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1790 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1791
1792 rc = iwl_check_rxon_cmd(priv);
1793 if (rc) {
1794 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1795 return -EINVAL;
1796 }
1797
1798 /* If we don't need to send a full RXON, we can use
1799 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1800 * and other flags for the current radio configuration. */
1801 if (!iwl_full_rxon_required(priv)) {
1802 rc = iwl_send_rxon_assoc(priv);
1803 if (rc) {
1804 IWL_ERR(priv, "Error setting RXON_ASSOC "
1805 "configuration (%d).\n", rc);
1806 return rc;
1807 }
1808
1809 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1810
1811 return 0;
1812 }
1813
1814 /* If we are currently associated and the new config requires
1815 * an RXON_ASSOC and the new config wants the associated mask enabled,
1816 * we must clear the associated from the active configuration
1817 * before we apply the new config */
1818 if (iwl_is_associated(priv) && new_assoc) {
1819 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1820 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1821
1822 /*
1823 * reserved4 and 5 could have been filled by the iwlcore code.
1824 * Let's clear them before pushing to the 3945.
1825 */
1826 active_rxon->reserved4 = 0;
1827 active_rxon->reserved5 = 0;
1828 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1829 sizeof(struct iwl3945_rxon_cmd),
1830 &priv->active_rxon);
1831
1832 /* If the mask clearing failed then we set
1833 * active_rxon back to what it was previously */
1834 if (rc) {
1835 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1836 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1837 "configuration (%d).\n", rc);
1838 return rc;
1839 }
2c810ccd 1840 iwl_clear_ucode_stations(priv);
7e246191 1841 iwl_restore_stations(priv);
e0158e61
AK		 1842 }
1843
1844 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1845 "* with%s RXON_FILTER_ASSOC_MSK\n"
1846 "* channel = %d\n"
1847 "* bssid = %pM\n",
1848 (new_assoc ? "" : "out"),
1849 le16_to_cpu(staging_rxon->channel),
1850 staging_rxon->bssid_addr);
1851
1852 /*
1853 * reserved4 and 5 could have been filled by the iwlcore code.
1854 * Let's clear them before pushing to the 3945.
1855 */
1856 staging_rxon->reserved4 = 0;
1857 staging_rxon->reserved5 = 0;
1858
90e8e424 1859 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
e0158e61
AK		 1860
1861 /* Apply the new configuration */
1862 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1863 sizeof(struct iwl3945_rxon_cmd),
1864 staging_rxon);
1865 if (rc) {
1866 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1867 return rc;
1868 }
1869
1870 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1871
7e246191 1872 if (!new_assoc) {
2c810ccd 1873 iwl_clear_ucode_stations(priv);
7e246191
RC		 1874 iwl_restore_stations(priv);
1875 }
e0158e61
AK		 1876
1877 /* If we issue a new RXON command which required a tune then we must
1878 * send a new TXPOWER command or we won't be able to Tx any frames */
1879 rc = priv->cfg->ops->lib->send_tx_power(priv);
1880 if (rc) {
1881 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1882 return rc;
1883 }
1884
e0158e61
AK		 1885 /* Init the hardware's rate fallback order based on the band */
1886 rc = iwl3945_init_hw_rate_table(priv);
1887 if (rc) {
1888 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1889 return -EIO;
1890 }
1891
1892 return 0;
1893}
1894
b481de9c
ZY		 1895/**
1896 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1897 *
1898 * -- reset periodic timer
1899 * -- see if temp has changed enough to warrant re-calibration ... if so:
1900 * -- correct coeffs for temp (can reset temp timer)
1901 * -- save this temp as "last",
1902 * -- send new set of gain settings to NIC
1903 * NOTE: This should continue working, even when we're not associated,
1904 * so we can keep our internal table of scan powers current. */
4a8a4322 1905void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 1906{
1907 /* This will kick in the "brute force"
bb8c093b 1908 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 1909 if (!is_temp_calib_needed(priv))
1910 goto reschedule;
1911
1912 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1913 * This is based *only* on current temperature,
1914 * ignoring any previous power measurements */
bb8c093b 1915 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1916
1917 reschedule:
1918 queue_delayed_work(priv->workqueue,
ee525d13 1919 &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
b481de9c
ZY		 1920}
1921
416e1438 1922static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 1923{
4a8a4322 1924 struct iwl_priv *priv = container_of(work, struct iwl_priv,
ee525d13 1925 _3945.thermal_periodic.work);
b481de9c
ZY		 1926
1927 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1928 return;
1929
1930 mutex_lock(&priv->mutex);
1931 iwl3945_reg_txpower_periodic(priv);
1932 mutex_unlock(&priv->mutex);
1933}
1934
1935/**
bb8c093b 1936 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 1937 * for the channel.
1938 *
1939 * This function is used when initializing channel-info structs.
1940 *
1941 * NOTE: These channel groups do *NOT* match the bands above!
1942 * These channel groups are based on factory-tested channels;
1943 * on A-band, EEPROM's "group frequency" entries represent the top
1944 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1945 */
4a8a4322 1946static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 1947 const struct iwl_channel_info *ch_info)
b481de9c 1948{
e6148917
SO		 1949 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1950 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 1951 u8 group;
1952 u16 group_index = 0; /* based on factory calib frequencies */
1953 u8 grp_channel;
1954
1955 /* Find the group index for the channel ... don't use index 1(?) */
1956 if (is_channel_a_band(ch_info)) {
1957 for (group = 1; group < 5; group++) {
1958 grp_channel = ch_grp[group].group_channel;
1959 if (ch_info->channel <= grp_channel) {
1960 group_index = group;
1961 break;
1962 }
1963 }
1964 /* group 4 has a few channels *above* its factory cal freq */
1965 if (group == 5)
1966 group_index = 4;
1967 } else
1968 group_index = 0; /* 2.4 GHz, group 0 */
1969
e1623446 1970 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
b481de9c
ZY		 1971 group_index);
1972 return group_index;
1973}
1974
1975/**
bb8c093b 1976 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 1977 *
1978 * Interpolate to get nominal (i.e. at factory calibration temperature) index
1979 * into radio/DSP gain settings table for requested power.
1980 */
4a8a4322 1981static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 1982 s8 requested_power,
1983 s32 setting_index, s32 *new_index)
1984{
bb8c093b 1985 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 1986 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1987 s32 index0, index1;
1988 s32 power = 2 * requested_power;
1989 s32 i;
bb8c093b 1990 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 1991 s32 gains0, gains1;
1992 s32 res;
1993 s32 denominator;
1994
e6148917 1995 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 1996 samples = chnl_grp->samples;
1997 for (i = 0; i < 5; i++) {
1998 if (power == samples[i].power) {
1999 *new_index = samples[i].gain_index;
2000 return 0;
2001 }
2002 }
2003
2004 if (power > samples[1].power) {
2005 index0 = 0;
2006 index1 = 1;
2007 } else if (power > samples[2].power) {
2008 index0 = 1;
2009 index1 = 2;
2010 } else if (power > samples[3].power) {
2011 index0 = 2;
2012 index1 = 3;
2013 } else {
2014 index0 = 3;
2015 index1 = 4;
2016 }
2017
2018 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2019 if (denominator == 0)
2020 return -EINVAL;
2021 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2022 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2023 res = gains0 + (gains1 - gains0) *
2024 ((s32) power - (s32) samples[index0].power) / denominator +
2025 (1 << 18);
2026 *new_index = res >> 19;
2027 return 0;
2028}
2029
4a8a4322 2030static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2031{
2032 u32 i;
2033 s32 rate_index;
e6148917 2034 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2035 const struct iwl3945_eeprom_txpower_group *group;
b481de9c 2036
e1623446 2037 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
b481de9c
ZY		 2038
2039 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2040 s8 *clip_pwrs; /* table of power levels for each rate */
2041 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2042 group = &eeprom->groups[i];
b481de9c
ZY		 2043
2044 /* sanity check on factory saturation power value */
2045 if (group->saturation_power < 40) {
39aadf8c 2046 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2047 "less than minimum expected 40\n",
2048 group->saturation_power);
2049 return;
2050 }
2051
2052 /*
2053 * Derive requested power levels for each rate, based on
2054 * hardware capabilities (saturation power for band).
2055 * Basic value is 3dB down from saturation, with further
2056 * power reductions for highest 3 data rates. These
2057 * backoffs provide headroom for high rate modulation
2058 * power peaks, without too much distortion (clipping).
2059 */
2060 /* we'll fill in this array with h/w max power levels */
67d613ae 2061 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
b481de9c
ZY		 2062
2063 /* divide factory saturation power by 2 to find -3dB level */
2064 satur_pwr = (s8) (group->saturation_power >> 1);
2065
2066 /* fill in channel group's nominal powers for each rate */
2067 for (rate_index = 0;
1d79e53c 2068 rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
b481de9c 2069 switch (rate_index) {
14577f23 2070 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2071 if (i == 0) /* B/G */
2072 *clip_pwrs = satur_pwr;
2073 else /* A */
2074 *clip_pwrs = satur_pwr - 5;
2075 break;
14577f23 2076 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2077 if (i == 0)
2078 *clip_pwrs = satur_pwr - 7;
2079 else
2080 *clip_pwrs = satur_pwr - 10;
2081 break;
14577f23 2082 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2083 if (i == 0)
2084 *clip_pwrs = satur_pwr - 9;
2085 else
2086 *clip_pwrs = satur_pwr - 12;
2087 break;
2088 default:
2089 *clip_pwrs = satur_pwr;
2090 break;
2091 }
2092 }
2093 }
2094}
2095
2096/**
2097 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2098 *
2099 * Second pass (during init) to set up priv->channel_info
2100 *
2101 * Set up Tx-power settings in our channel info database for each VALID
2102 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2103 * and current temperature.
2104 *
2105 * Since this is based on current temperature (at init time), these values may
2106 * not be valid for very long, but it gives us a starting/default point,
2107 * and allows us to active (i.e. using Tx) scan.
2108 *
2109 * This does *not* write values to NIC, just sets up our internal table.
2110 */
4a8a4322 2111int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2112{
d20b3c65 2113 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2114 struct iwl3945_channel_power_info *pwr_info;
e6148917 2115 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2116 int delta_index;
2117 u8 rate_index;
2118 u8 scan_tbl_index;
2119 const s8 *clip_pwrs; /* array of power levels for each rate */
2120 u8 gain, dsp_atten;
2121 s8 power;
2122 u8 pwr_index, base_pwr_index, a_band;
2123 u8 i;
2124 int temperature;
2125
2126 /* save temperature reference,
2127 * so we can determine next time to calibrate */
bb8c093b 2128 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2129 priv->last_temperature = temperature;
2130
bb8c093b 2131 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2132
2133 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2134 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2135 i++, ch_info++) {
2136 a_band = is_channel_a_band(ch_info);
2137 if (!is_channel_valid(ch_info))
2138 continue;
2139
2140 /* find this channel's channel group (*not* "band") index */
2141 ch_info->group_index =
bb8c093b 2142 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2143
2144 /* Get this chnlgrp's rate->max/clip-powers table */
67d613ae 2145 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2146
2147 /* calculate power index *adjustment* value according to
2148 * diff between current temperature and factory temperature */
bb8c093b 2149 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2150 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2151 temperature);
2152
e1623446 2153 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
b481de9c
ZY		 2154 ch_info->channel, delta_index, temperature +
2155 IWL_TEMP_CONVERT);
2156
2157 /* set tx power value for all OFDM rates */
2158 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2159 rate_index++) {
25a4ccea 2160 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2161 int rc;
2162
2163 /* use channel group's clip-power table,
2164 * but don't exceed channel's max power */
2165 s8 pwr = min(ch_info->max_power_avg,
2166 clip_pwrs[rate_index]);
2167
2168 pwr_info = &ch_info->power_info[rate_index];
2169
2170 /* get base (i.e. at factory-measured temperature)
2171 * power table index for this rate's power */
bb8c093b 2172 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2173 ch_info->group_index,
2174 &power_idx);
2175 if (rc) {
15b1687c 2176 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2177 return rc;
2178 }
2179 pwr_info->base_power_index = (u8) power_idx;
2180
2181 /* temperature compensate */
2182 power_idx += delta_index;
2183
2184 /* stay within range of gain table */
bb8c093b 2185 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2186
bb8c093b 2187 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2188 pwr_info->requested_power = pwr;
2189 pwr_info->power_table_index = (u8) power_idx;
2190 pwr_info->tpc.tx_gain =
2191 power_gain_table[a_band][power_idx].tx_gain;
2192 pwr_info->tpc.dsp_atten =
2193 power_gain_table[a_band][power_idx].dsp_atten;
2194 }
2195
2196 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2197 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2198 power = pwr_info->requested_power +
2199 IWL_CCK_FROM_OFDM_POWER_DIFF;
2200 pwr_index = pwr_info->power_table_index +
2201 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2202 base_pwr_index = pwr_info->base_power_index +
2203 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2204
2205 /* stay within table range */
bb8c093b 2206 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2207 gain = power_gain_table[a_band][pwr_index].tx_gain;
2208 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2209
bb8c093b 2210 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2211 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2212 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2213 for (rate_index = 0;
2214 rate_index < IWL_CCK_RATES; rate_index++) {
2215 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2216 pwr_info->requested_power = power;
2217 pwr_info->power_table_index = pwr_index;
2218 pwr_info->base_power_index = base_pwr_index;
2219 pwr_info->tpc.tx_gain = gain;
2220 pwr_info->tpc.dsp_atten = dsp_atten;
2221 }
2222
2223 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2224 for (scan_tbl_index = 0;
2225 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2226 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2227 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2228 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2229 actual_index, clip_pwrs, ch_info, a_band);
2230 }
2231 }
2232
2233 return 0;
2234}
2235
4a8a4322 2236int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2237{
2238 int rc;
b481de9c 2239
5d49f498
AK		 2240 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2241 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2242 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2243 if (rc < 0)
15b1687c 2244 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2245
b481de9c
ZY		 2246 return 0;
2247}
2248
188cf6c7 2249int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 2250{
b481de9c
ZY		 2251 int txq_id = txq->q.id;
2252
ee525d13 2253 struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
b481de9c
ZY		 2254
2255 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2256
5d49f498
AK		 2257 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2258 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2259
5d49f498 2260 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2261 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2262 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2263 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2264 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2265 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
b481de9c
ZY		 2266
2267 /* fake read to flush all prev. writes */
5d49f498 2268 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2269
2270 return 0;
2271}
2272
42427b4e
KA		 2273/*
2274 * HCMD utils
2275 */
2276static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2277{
2278 switch (cmd_id) {
2279 case REPLY_RXON:
d25aabb0
WT		 2280 return sizeof(struct iwl3945_rxon_cmd);
2281 case POWER_TABLE_CMD:
2282 return sizeof(struct iwl3945_powertable_cmd);
42427b4e
KA		 2283 default:
2284 return len;
2285 }
2286}
2287
c587de0b 2288
17f841cd
SO		 2289static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2290{
c587de0b
TW		 2291 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2292 addsta->mode = cmd->mode;
2293 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2294 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2295 addsta->station_flags = cmd->station_flags;
2296 addsta->station_flags_msk = cmd->station_flags_msk;
2297 addsta->tid_disable_tx = cpu_to_le16(0);
2298 addsta->rate_n_flags = cmd->rate_n_flags;
2299 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2300 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2301 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2302
2303 return (u16)sizeof(struct iwl3945_addsta_cmd);
17f841cd
SO		 2304}
2305
1fa61b2e
JB		 2306static int iwl3945_manage_ibss_station(struct iwl_priv *priv,
2307 struct ieee80211_vif *vif, bool add)
2308{
fd1af15d 2309 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1fa61b2e
JB		 2310 int ret;
2311
1fa61b2e 2312 if (add) {
57f8db89 2313 ret = iwl_add_bssid_station(priv, vif->bss_conf.bssid, false,
fd1af15d 2314 &vif_priv->ibss_bssid_sta_id);
1fa61b2e
JB		 2315 if (ret)
2316 return ret;
2317
fd1af15d 2318 iwl3945_sync_sta(priv, vif_priv->ibss_bssid_sta_id,
1fa61b2e 2319 (priv->band == IEEE80211_BAND_5GHZ) ?
9c5ac091 2320 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP);
fd1af15d 2321 iwl3945_rate_scale_init(priv->hw, vif_priv->ibss_bssid_sta_id);
1fa61b2e
JB		 2322
2323 return 0;
2324 }
2325
fd1af15d
JB		 2326 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
2327 vif->bss_conf.bssid);
1fa61b2e 2328}
c587de0b 2329
b481de9c
ZY		 2330/**
2331 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2332 */
4a8a4322 2333int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2334{
14577f23 2335 int rc, i, index, prev_index;
bb8c093b 2336 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2337 .reserved = {0, 0, 0},
2338 };
bb8c093b 2339 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2340
bb8c093b
CH		 2341 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2342 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2343
2344 table[index].rate_n_flags =
bb8c093b 2345 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2346 table[index].try_cnt = priv->retry_rate;
bb8c093b 2347 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2348 table[index].next_rate_index =
2349 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2350 }
2351
8318d78a
JB		 2352 switch (priv->band) {
2353 case IEEE80211_BAND_5GHZ:
e1623446 2354 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
b481de9c
ZY		 2355 /* If one of the following CCK rates is used,
2356 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2357 for (i = IWL_RATE_1M_INDEX_TABLE;
2358 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2359 table[i].next_rate_index =
2360 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2361
2362 /* Don't fall back to CCK rates */
7262796a
AM		 2363 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2364 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2365
2366 /* Don't drop out of OFDM rates */
14577f23 2367 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2368 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2369 break;
2370
8318d78a 2371 case IEEE80211_BAND_2GHZ:
e1623446 2372 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
b481de9c
ZY		 2373 /* If an OFDM rate is used, have it fall back to the
2374 * 1M CCK rates */
b481de9c 2375
ee525d13 2376 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 2377 iwl_is_associated(priv)) {
7262796a
AM		 2378
2379 index = IWL_FIRST_CCK_RATE;
2380 for (i = IWL_RATE_6M_INDEX_TABLE;
2381 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2382 table[i].next_rate_index =
2383 iwl3945_rates[index].table_rs_index;
2384
2385 index = IWL_RATE_11M_INDEX_TABLE;
2386 /* CCK shouldn't fall back to OFDM... */
2387 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2388 }
b481de9c
ZY		 2389 break;
2390
2391 default:
8318d78a 2392 WARN_ON(1);
b481de9c
ZY		 2393 break;
2394 }
2395
2396 /* Update the rate scaling for control frame Tx */
2397 rate_cmd.table_id = 0;
518099a8 2398 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2399 &rate_cmd);
2400 if (rc)
2401 return rc;
2402
2403 /* Update the rate scaling for data frame Tx */
2404 rate_cmd.table_id = 1;
518099a8 2405 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2406 &rate_cmd);
2407}
2408
796083cb 2409/* Called when initializing driver */
4a8a4322 2410int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2411{
3832ec9d
AK		 2412 memset((void *)&priv->hw_params, 0,
2413 sizeof(struct iwl_hw_params));
b481de9c 2414
ee525d13
JB		 2415 priv->_3945.shared_virt =
2416 dma_alloc_coherent(&priv->pci_dev->dev,
2417 sizeof(struct iwl3945_shared),
2418 &priv->_3945.shared_phys, GFP_KERNEL);
2419 if (!priv->_3945.shared_virt) {
15b1687c 2420 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2421 return -ENOMEM;
2422 }
2423
21c02a1a 2424 /* Assign number of Usable TX queues */
88804e2b 2425 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
21c02a1a 2426
a8e74e27 2427 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2f301227 2428 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
3832ec9d
AK		 2429 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2430 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2431 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2432 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2433
141c43a3 2434 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2c2f3b33 2435 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
a0ee74cf 2436 priv->hw_params.beacon_time_tsf_bits = IWL3945_EXT_BEACON_TIME_POS;
141c43a3 2437
b481de9c
ZY		 2438 return 0;
2439}
2440
4a8a4322 2441unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2442 struct iwl3945_frame *frame, u8 rate)
b481de9c 2443{
bb8c093b 2444 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2445 unsigned int frame_size;
2446
bb8c093b 2447 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2448 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2449
3832ec9d 2450 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2451 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2452
bb8c093b 2453 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2454 tx_beacon_cmd->frame,
b481de9c
ZY		 2455 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2456
2457 BUG_ON(frame_size > MAX_MPDU_SIZE);
2458 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2459
2460 tx_beacon_cmd->tx.rate = rate;
2461 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2462 TX_CMD_FLG_TSF_MSK);
2463
14577f23
MA		 2464 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2465 tx_beacon_cmd->tx.supp_rates[0] =
2466 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2467
b481de9c 2468 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2469 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2470
3ac7f146 2471 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2472}
2473
4a8a4322 2474void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2475{
91c066f2 2476 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2477 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2478}
2479
4a8a4322 2480void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c 2481{
ee525d13 2482 INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
b481de9c
ZY		 2483 iwl3945_bg_reg_txpower_periodic);
2484}
2485
4a8a4322 2486void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2487{
ee525d13 2488 cancel_delayed_work(&priv->_3945.thermal_periodic);
b481de9c
ZY		 2489}
2490
0164b9b4
KA		 2491/* check contents of special bootstrap uCode SRAM */
2492static int iwl3945_verify_bsm(struct iwl_priv *priv)
2493 {
2494 __le32 *image = priv->ucode_boot.v_addr;
2495 u32 len = priv->ucode_boot.len;
2496 u32 reg;
2497 u32 val;
2498
e1623446 2499 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
0164b9b4
KA		 2500
2501 /* verify BSM SRAM contents */
2502 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2503 for (reg = BSM_SRAM_LOWER_BOUND;
2504 reg < BSM_SRAM_LOWER_BOUND + len;
2505 reg += sizeof(u32), image++) {
2506 val = iwl_read_prph(priv, reg);
2507 if (val != le32_to_cpu(*image)) {
2508 IWL_ERR(priv, "BSM uCode verification failed at "
2509 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2510 BSM_SRAM_LOWER_BOUND,
2511 reg - BSM_SRAM_LOWER_BOUND, len,
2512 val, le32_to_cpu(*image));
2513 return -EIO;
2514 }
2515 }
2516
e1623446 2517 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
0164b9b4
KA		 2518
2519 return 0;
2520}
2521
e6148917
SO		 2522
2523/******************************************************************************
2524 *
2525 * EEPROM related functions
2526 *
2527 ******************************************************************************/
2528
2529/*
2530 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2531 * embedded controller) as EEPROM reader; each read is a series of pulses
2532 * to/from the EEPROM chip, not a single event, so even reads could conflict
2533 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2534 * simply claims ownership, which should be safe when this function is called
2535 * (i.e. before loading uCode!).
2536 */
2537static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2538{
2539 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2540 return 0;
2541}
2542
2543
2544static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2545{
2546 return;
2547}
2548
0164b9b4
KA		 2549 /**
2550 * iwl3945_load_bsm - Load bootstrap instructions
2551 *
2552 * BSM operation:
2553 *
2554 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2555 * in special SRAM that does not power down during RFKILL. When powering back
2556 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2557 * the bootstrap program into the on-board processor, and starts it.
2558 *
2559 * The bootstrap program loads (via DMA) instructions and data for a new
2560 * program from host DRAM locations indicated by the host driver in the
2561 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2562 * automatically.
2563 *
2564 * When initializing the NIC, the host driver points the BSM to the
2565 * "initialize" uCode image. This uCode sets up some internal data, then
2566 * notifies host via "initialize alive" that it is complete.
2567 *
2568 * The host then replaces the BSM_DRAM_* pointer values to point to the
2569 * normal runtime uCode instructions and a backup uCode data cache buffer
2570 * (filled initially with starting data values for the on-board processor),
2571 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2572 * which begins normal operation.
2573 *
2574 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2575 * the backup data cache in DRAM before SRAM is powered down.
2576 *
2577 * When powering back up, the BSM loads the bootstrap program. This reloads
2578 * the runtime uCode instructions and the backup data cache into SRAM,
2579 * and re-launches the runtime uCode from where it left off.
2580 */
2581static int iwl3945_load_bsm(struct iwl_priv *priv)
2582{
2583 __le32 *image = priv->ucode_boot.v_addr;
2584 u32 len = priv->ucode_boot.len;
2585 dma_addr_t pinst;
2586 dma_addr_t pdata;
2587 u32 inst_len;
2588 u32 data_len;
2589 int rc;
2590 int i;
2591 u32 done;
2592 u32 reg_offset;
2593
e1623446 2594 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
0164b9b4
KA		 2595
2596 /* make sure bootstrap program is no larger than BSM's SRAM size */
2597 if (len > IWL39_MAX_BSM_SIZE)
2598 return -EINVAL;
2599
2600 /* Tell bootstrap uCode where to find the "Initialize" uCode
2601 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2602 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2603 * after the "initialize" uCode has run, to point to
2604 * runtime/protocol instructions and backup data cache. */
2605 pinst = priv->ucode_init.p_addr;
2606 pdata = priv->ucode_init_data.p_addr;
2607 inst_len = priv->ucode_init.len;
2608 data_len = priv->ucode_init_data.len;
2609
0164b9b4
KA		 2610 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2611 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2612 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2613 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2614
2615 /* Fill BSM memory with bootstrap instructions */
2616 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2617 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2618 reg_offset += sizeof(u32), image++)
2619 _iwl_write_prph(priv, reg_offset,
2620 le32_to_cpu(*image));
2621
2622 rc = iwl3945_verify_bsm(priv);
a8b50a0a 2623 if (rc)
0164b9b4 2624 return rc;
0164b9b4
KA		 2625
2626 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2627 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2628 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2629 IWL39_RTC_INST_LOWER_BOUND);
2630 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2631
2632 /* Load bootstrap code into instruction SRAM now,
2633 * to prepare to load "initialize" uCode */
2634 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2635 BSM_WR_CTRL_REG_BIT_START);
2636
2637 /* Wait for load of bootstrap uCode to finish */
2638 for (i = 0; i < 100; i++) {
2639 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2640 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2641 break;
2642 udelay(10);
2643 }
2644 if (i < 100)
e1623446 2645 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
0164b9b4
KA		 2646 else {
2647 IWL_ERR(priv, "BSM write did not complete!\n");
2648 return -EIO;
2649 }
2650
2651 /* Enable future boot loads whenever power management unit triggers it
2652 * (e.g. when powering back up after power-save shutdown) */
2653 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2654 BSM_WR_CTRL_REG_BIT_START_EN);
2655
0164b9b4
KA		 2656 return 0;
2657}
2658
5bbe233b
AK		 2659static struct iwl_hcmd_ops iwl3945_hcmd = {
2660 .rxon_assoc = iwl3945_send_rxon_assoc,
e0158e61 2661 .commit_rxon = iwl3945_commit_rxon,
65b52bde 2662 .send_bt_config = iwl_send_bt_config,
5bbe233b
AK		 2663};
2664
0164b9b4 2665static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2666 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2667 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2668 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2669 .load_ucode = iwl3945_load_bsm,
b7a79404
RC		 2670 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2671 .dump_nic_error_log = iwl3945_dump_nic_error_log,
01ec616d
KA		 2672 .apm_ops = {
2673 .init = iwl3945_apm_init,
d68b603c 2674 .stop = iwl_apm_stop,
01ec616d 2675 .config = iwl3945_nic_config,
854682ed 2676 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2677 },
e6148917
SO		 2678 .eeprom_ops = {
2679 .regulatory_bands = {
2680 EEPROM_REGULATORY_BAND_1_CHANNELS,
2681 EEPROM_REGULATORY_BAND_2_CHANNELS,
2682 EEPROM_REGULATORY_BAND_3_CHANNELS,
2683 EEPROM_REGULATORY_BAND_4_CHANNELS,
2684 EEPROM_REGULATORY_BAND_5_CHANNELS,
7aafef1c
WYG		 2685 EEPROM_REGULATORY_BAND_NO_HT40,
2686 EEPROM_REGULATORY_BAND_NO_HT40,
e6148917
SO		 2687 },
2688 .verify_signature = iwlcore_eeprom_verify_signature,
2689 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2690 .release_semaphore = iwl3945_eeprom_release_semaphore,
2691 .query_addr = iwlcore_eeprom_query_addr,
2692 },
75bcfae9 2693 .send_tx_power = iwl3945_send_tx_power,
c2436980 2694 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
5bbe233b 2695 .post_associate = iwl3945_post_associate,
ef850d7c 2696 .isr = iwl_isr_legacy,
60690a6a 2697 .config_ap = iwl3945_config_ap,
1fa61b2e 2698 .manage_ibss_station = iwl3945_manage_ibss_station,
a29576a7 2699 .check_plcp_health = iwl3945_good_plcp_health,
17f36fc6
AK		 2700
2701 .debugfs_ops = {
2702 .rx_stats_read = iwl3945_ucode_rx_stats_read,
2703 .tx_stats_read = iwl3945_ucode_tx_stats_read,
2704 .general_stats_read = iwl3945_ucode_general_stats_read,
2705 },
0164b9b4
KA		 2706};
2707
42427b4e
KA		 2708static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2709 .get_hcmd_size = iwl3945_get_hcmd_size,
17f841cd 2710 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
37dc70fe 2711 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
b6e4c55a 2712 .request_scan = iwl3945_request_scan,
42427b4e
KA		 2713};
2714
45d5d805 2715static const struct iwl_ops iwl3945_ops = {
0164b9b4 2716 .lib = &iwl3945_lib,
5bbe233b 2717 .hcmd = &iwl3945_hcmd,
42427b4e 2718 .utils = &iwl3945_hcmd_utils,
e932a609 2719 .led = &iwl3945_led_ops,
0164b9b4
KA		 2720};
2721
c0f20d91 2722static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2723 .name = "3945BG",
a0987a8d
RC		 2724 .fw_name_pre = IWL3945_FW_PRE,
2725 .ucode_api_max = IWL3945_UCODE_API_MAX,
2726 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2727 .sku = IWL_SKU_G,
e6148917
SO		 2728 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2729 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2730 .ops = &iwl3945_ops,
88804e2b 2731 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2732 .mod_params = &iwl3945_mod_params,
fadb3582
BC		 2733 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2734 .set_l0s = false,
2735 .use_bsm = true,
b261793d
DH		 2736 .use_isr_legacy = true,
2737 .ht_greenfield_support = false,
f2d0d0e2 2738 .led_compensation = 64,
bc45a670 2739 .broken_powersave = true,
a29576a7 2740 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
b74e31a9 2741 .monitor_recover_period = IWL_MONITORING_PERIOD,
678b385d 2742 .max_event_log_size = 512,
4e7033ef 2743 .tx_power_by_driver = true,
82b9a121
TW		 2744};
2745
c0f20d91 2746static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2747 .name = "3945ABG",
a0987a8d
RC		 2748 .fw_name_pre = IWL3945_FW_PRE,
2749 .ucode_api_max = IWL3945_UCODE_API_MAX,
2750 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2751 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2752 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2753 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2754 .ops = &iwl3945_ops,
88804e2b 2755 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2756 .mod_params = &iwl3945_mod_params,
b261793d
DH		 2757 .use_isr_legacy = true,
2758 .ht_greenfield_support = false,
f2d0d0e2 2759 .led_compensation = 64,
bc45a670 2760 .broken_powersave = true,
a29576a7 2761 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
b74e31a9 2762 .monitor_recover_period = IWL_MONITORING_PERIOD,
678b385d 2763 .max_event_log_size = 512,
4e7033ef 2764 .tx_power_by_driver = true,
82b9a121
TW		 2765};
2766
a3aa1884 2767DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
82b9a121
TW		 2768 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2769 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2770 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2771 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2772 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2773 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2774 {0}
2775};
2776
bb8c093b 2777MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Linux kernel - Deliverables
This page took 0.734026 seconds and 5 git commands to generate.