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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
eb7ae89c | 8 | * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved. |
b481de9c ZY |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
01ebd063 | 11 | * it under the terms of version 2 of the GNU General Public License as |
b481de9c ZY |
12 | * published by the Free Software Foundation. |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
eb7ae89c | 33 | * Copyright(c) 2005 - 2008 Intel Corporation. All rights reserved. |
b481de9c ZY |
34 | * All rights reserved. |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
fcd427bb BC |
63 | /* |
64 | * Please use this file (iwl-4965-hw.h) only for hardware-related definitions. | |
65 | * Use iwl-4965-commands.h for uCode API definitions. | |
66 | * Use iwl-4965.h for driver implementation definitions. | |
67 | */ | |
b481de9c ZY |
68 | |
69 | #ifndef __iwl_4965_hw_h__ | |
70 | #define __iwl_4965_hw_h__ | |
71 | ||
1fea8e88 BC |
72 | /* |
73 | * uCode queue management definitions ... | |
74 | * Queue #4 is the command queue for 3945 and 4965; map it to Tx FIFO chnl 4. | |
75 | * The first queue used for block-ack aggregation is #7 (4965 only). | |
76 | * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7. | |
77 | */ | |
5d08cd1d CH |
78 | #define IWL_CMD_QUEUE_NUM 4 |
79 | #define IWL_CMD_FIFO_NUM 4 | |
80 | #define IWL_BACK_QUEUE_FIRST_ID 7 | |
81 | ||
82 | /* Tx rates */ | |
83 | #define IWL_CCK_RATES 4 | |
84 | #define IWL_OFDM_RATES 8 | |
5d08cd1d | 85 | #define IWL_HT_RATES 16 |
5d08cd1d CH |
86 | #define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES) |
87 | ||
88 | /* Time constants */ | |
89 | #define SHORT_SLOT_TIME 9 | |
90 | #define LONG_SLOT_TIME 20 | |
91 | ||
92 | /* RSSI to dBm */ | |
93 | #define IWL_RSSI_OFFSET 44 | |
94 | ||
5d08cd1d CH |
95 | |
96 | #include "iwl-4965-commands.h" | |
97 | ||
98 | #define PCI_LINK_CTRL 0x0F0 | |
99 | #define PCI_POWER_SOURCE 0x0C8 | |
100 | #define PCI_REG_WUM8 0x0E8 | |
101 | #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000) | |
102 | ||
5d08cd1d CH |
103 | #define TFD_QUEUE_SIZE_MAX (256) |
104 | ||
5d08cd1d CH |
105 | #define IWL_NUM_SCAN_RATES (2) |
106 | ||
5d08cd1d | 107 | #define IWL_DEFAULT_TX_RETRY 15 |
5d08cd1d CH |
108 | |
109 | #define RX_QUEUE_SIZE 256 | |
110 | #define RX_QUEUE_MASK 255 | |
111 | #define RX_QUEUE_SIZE_LOG 8 | |
112 | ||
5d08cd1d CH |
113 | #define TFD_TX_CMD_SLOTS 256 |
114 | #define TFD_CMD_SLOTS 32 | |
115 | ||
5d08cd1d CH |
116 | /* |
117 | * RX related structures and functions | |
118 | */ | |
119 | #define RX_FREE_BUFFERS 64 | |
120 | #define RX_LOW_WATERMARK 8 | |
121 | ||
fcd427bb | 122 | /* Size of one Rx buffer in host DRAM */ |
9ee1ba47 RR |
123 | #define IWL_RX_BUF_SIZE_4K (4 * 1024) |
124 | #define IWL_RX_BUF_SIZE_8K (8 * 1024) | |
fcd427bb BC |
125 | |
126 | /* Sizes and addresses for instruction and data memory (SRAM) in | |
127 | * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */ | |
128 | #define RTC_INST_LOWER_BOUND (0x000000) | |
b481de9c | 129 | #define KDR_RTC_INST_UPPER_BOUND (0x018000) |
fcd427bb BC |
130 | |
131 | #define RTC_DATA_LOWER_BOUND (0x800000) | |
b481de9c | 132 | #define KDR_RTC_DATA_UPPER_BOUND (0x80A000) |
fcd427bb | 133 | |
b481de9c ZY |
134 | #define KDR_RTC_INST_SIZE (KDR_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND) |
135 | #define KDR_RTC_DATA_SIZE (KDR_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND) | |
136 | ||
137 | #define IWL_MAX_INST_SIZE KDR_RTC_INST_SIZE | |
138 | #define IWL_MAX_DATA_SIZE KDR_RTC_DATA_SIZE | |
139 | ||
fcd427bb BC |
140 | /* Size of uCode instruction memory in bootstrap state machine */ |
141 | #define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE | |
142 | ||
bb8c093b | 143 | static inline int iwl4965_hw_valid_rtc_data_addr(u32 addr) |
b481de9c ZY |
144 | { |
145 | return (addr >= RTC_DATA_LOWER_BOUND) && | |
146 | (addr < KDR_RTC_DATA_UPPER_BOUND); | |
147 | } | |
148 | ||
5991b419 | 149 | /********************* START TEMPERATURE *************************************/ |
b481de9c | 150 | |
0c434c5a | 151 | /** |
5991b419 BC |
152 | * 4965 temperature calculation. |
153 | * | |
154 | * The driver must calculate the device temperature before calculating | |
155 | * a txpower setting (amplifier gain is temperature dependent). The | |
156 | * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration | |
157 | * values used for the life of the driver, and one of which (R4) is the | |
158 | * real-time temperature indicator. | |
159 | * | |
160 | * uCode provides all 4 values to the driver via the "initialize alive" | |
161 | * notification (see struct iwl4965_init_alive_resp). After the runtime uCode | |
162 | * image loads, uCode updates the R4 value via statistics notifications | |
163 | * (see STATISTICS_NOTIFICATION), which occur after each received beacon | |
164 | * when associated, or can be requested via REPLY_STATISTICS_CMD. | |
165 | * | |
166 | * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver | |
167 | * must sign-extend to 32 bits before applying formula below. | |
168 | * | |
169 | * Formula: | |
170 | * | |
171 | * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8 | |
172 | * | |
173 | * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is | |
174 | * an additional correction, which should be centered around 0 degrees | |
175 | * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for | |
176 | * centering the 97/100 correction around 0 degrees K. | |
177 | * | |
178 | * Add 273 to Kelvin value to find degrees Celsius, for comparing current | |
179 | * temperature with factory-measured temperatures when calculating txpower | |
180 | * settings. | |
181 | */ | |
b481de9c ZY |
182 | #define TEMPERATURE_CALIB_KELVIN_OFFSET 8 |
183 | #define TEMPERATURE_CALIB_A_VAL 259 | |
184 | ||
5991b419 | 185 | /* Limit range of calculated temperature to be between these Kelvin values */ |
b481de9c ZY |
186 | #define IWL_TX_POWER_TEMPERATURE_MIN (263) |
187 | #define IWL_TX_POWER_TEMPERATURE_MAX (410) | |
188 | ||
189 | #define IWL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \ | |
190 | (((t) < IWL_TX_POWER_TEMPERATURE_MIN) || \ | |
191 | ((t) > IWL_TX_POWER_TEMPERATURE_MAX)) | |
192 | ||
5991b419 BC |
193 | /********************* END TEMPERATURE ***************************************/ |
194 | ||
195 | /********************* START TXPOWER *****************************************/ | |
196 | ||
0c434c5a BC |
197 | /** |
198 | * 4965 txpower calculations rely on information from three sources: | |
199 | * | |
200 | * 1) EEPROM | |
201 | * 2) "initialize" alive notification | |
202 | * 3) statistics notifications | |
203 | * | |
204 | * EEPROM data consists of: | |
205 | * | |
206 | * 1) Regulatory information (max txpower and channel usage flags) is provided | |
207 | * separately for each channel that can possibly supported by 4965. | |
208 | * 40 MHz wide (.11n fat) channels are listed separately from 20 MHz | |
209 | * (legacy) channels. | |
210 | * | |
211 | * See struct iwl4965_eeprom_channel for format, and struct iwl4965_eeprom | |
212 | * for locations in EEPROM. | |
213 | * | |
214 | * 2) Factory txpower calibration information is provided separately for | |
215 | * sub-bands of contiguous channels. 2.4GHz has just one sub-band, | |
216 | * but 5 GHz has several sub-bands. | |
217 | * | |
218 | * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided. | |
219 | * | |
220 | * See struct iwl4965_eeprom_calib_info (and the tree of structures | |
221 | * contained within it) for format, and struct iwl4965_eeprom for | |
222 | * locations in EEPROM. | |
223 | * | |
224 | * "Initialization alive" notification (see struct iwl4965_init_alive_resp) | |
225 | * consists of: | |
226 | * | |
227 | * 1) Temperature calculation parameters. | |
228 | * | |
229 | * 2) Power supply voltage measurement. | |
230 | * | |
231 | * 3) Tx gain compensation to balance 2 transmitters for MIMO use. | |
232 | * | |
233 | * Statistics notifications deliver: | |
234 | * | |
235 | * 1) Current values for temperature param R4. | |
236 | */ | |
5991b419 | 237 | |
0c434c5a BC |
238 | /** |
239 | * To calculate a txpower setting for a given desired target txpower, channel, | |
240 | * modulation bit rate, and transmitter chain (4965 has 2 transmitters to | |
241 | * support MIMO and transmit diversity), driver must do the following: | |
242 | * | |
243 | * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel. | |
244 | * Do not exceed regulatory limit; reduce target txpower if necessary. | |
245 | * | |
246 | * If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31), | |
247 | * 2 transmitters will be used simultaneously; driver must reduce the | |
248 | * regulatory limit by 3 dB (half-power) for each transmitter, so the | |
249 | * combined total output of the 2 transmitters is within regulatory limits. | |
250 | * | |
251 | * | |
252 | * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by | |
253 | * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]); | |
254 | * reduce target txpower if necessary. | |
255 | * | |
256 | * Backoff values below are in 1/2 dB units (equivalent to steps in | |
257 | * txpower gain tables): | |
258 | * | |
259 | * OFDM 6 - 36 MBit: 10 steps (5 dB) | |
260 | * OFDM 48 MBit: 15 steps (7.5 dB) | |
261 | * OFDM 54 MBit: 17 steps (8.5 dB) | |
262 | * OFDM 60 MBit: 20 steps (10 dB) | |
263 | * CCK all rates: 10 steps (5 dB) | |
264 | * | |
265 | * Backoff values apply to saturation txpower on a per-transmitter basis; | |
266 | * when using MIMO (2 transmitters), each transmitter uses the same | |
267 | * saturation level provided in EEPROM, and the same backoff values; | |
268 | * no reduction (such as with regulatory txpower limits) is required. | |
269 | * | |
270 | * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel | |
271 | * widths and 40 Mhz (.11n fat) channel widths; there is no separate | |
272 | * factory measurement for fat channels. | |
273 | * | |
274 | * The result of this step is the final target txpower. The rest of | |
275 | * the steps figure out the proper settings for the device to achieve | |
276 | * that target txpower. | |
277 | * | |
278 | * | |
279 | * 3) Determine (EEPROM) calibration subband for the target channel, by | |
280 | * comparing against first and last channels in each subband | |
281 | * (see struct iwl4965_eeprom_calib_subband_info). | |
282 | * | |
283 | * | |
284 | * 4) Linearly interpolate (EEPROM) factory calibration measurement sets, | |
285 | * referencing the 2 factory-measured (sample) channels within the subband. | |
286 | * | |
287 | * Interpolation is based on difference between target channel's frequency | |
288 | * and the sample channels' frequencies. Since channel numbers are based | |
289 | * on frequency (5 MHz between each channel number), this is equivalent | |
290 | * to interpolating based on channel number differences. | |
291 | * | |
292 | * Note that the sample channels may or may not be the channels at the | |
293 | * edges of the subband. The target channel may be "outside" of the | |
294 | * span of the sampled channels. | |
295 | * | |
296 | * Driver may choose the pair (for 2 Tx chains) of measurements (see | |
297 | * struct iwl4965_eeprom_calib_ch_info) for which the actual measured | |
298 | * txpower comes closest to the desired txpower. Usually, though, | |
299 | * the middle set of measurements is closest to the regulatory limits, | |
300 | * and is therefore a good choice for all txpower calculations (this | |
301 | * assumes that high accuracy is needed for maximizing legal txpower, | |
302 | * while lower txpower configurations do not need as much accuracy). | |
303 | * | |
304 | * Driver should interpolate both members of the chosen measurement pair, | |
305 | * i.e. for both Tx chains (radio transmitters), unless the driver knows | |
306 | * that only one of the chains will be used (e.g. only one tx antenna | |
307 | * connected, but this should be unusual). The rate scaling algorithm | |
308 | * switches antennas to find best performance, so both Tx chains will | |
309 | * be used (although only one at a time) even for non-MIMO transmissions. | |
310 | * | |
311 | * Driver should interpolate factory values for temperature, gain table | |
312 | * index, and actual power. The power amplifier detector values are | |
313 | * not used by the driver. | |
314 | * | |
315 | * Sanity check: If the target channel happens to be one of the sample | |
316 | * channels, the results should agree with the sample channel's | |
317 | * measurements! | |
318 | * | |
319 | * | |
320 | * 5) Find difference between desired txpower and (interpolated) | |
321 | * factory-measured txpower. Using (interpolated) factory gain table index | |
322 | * (shown elsewhere) as a starting point, adjust this index lower to | |
323 | * increase txpower, or higher to decrease txpower, until the target | |
324 | * txpower is reached. Each step in the gain table is 1/2 dB. | |
325 | * | |
326 | * For example, if factory measured txpower is 16 dBm, and target txpower | |
327 | * is 13 dBm, add 6 steps to the factory gain index to reduce txpower | |
328 | * by 3 dB. | |
329 | * | |
330 | * | |
331 | * 6) Find difference between current device temperature and (interpolated) | |
332 | * factory-measured temperature for sub-band. Factory values are in | |
333 | * degrees Celsius. To calculate current temperature, see comments for | |
334 | * "4965 temperature calculation". | |
335 | * | |
336 | * If current temperature is higher than factory temperature, driver must | |
337 | * increase gain (lower gain table index), and vice versa. | |
338 | * | |
339 | * Temperature affects gain differently for different channels: | |
340 | * | |
341 | * 2.4 GHz all channels: 3.5 degrees per half-dB step | |
342 | * 5 GHz channels 34-43: 4.5 degrees per half-dB step | |
343 | * 5 GHz channels >= 44: 4.0 degrees per half-dB step | |
344 | * | |
345 | * NOTE: Temperature can increase rapidly when transmitting, especially | |
346 | * with heavy traffic at high txpowers. Driver should update | |
347 | * temperature calculations often under these conditions to | |
348 | * maintain strong txpower in the face of rising temperature. | |
349 | * | |
350 | * | |
351 | * 7) Find difference between current power supply voltage indicator | |
352 | * (from "initialize alive") and factory-measured power supply voltage | |
353 | * indicator (EEPROM). | |
354 | * | |
355 | * If the current voltage is higher (indicator is lower) than factory | |
356 | * voltage, gain should be reduced (gain table index increased) by: | |
357 | * | |
358 | * (eeprom - current) / 7 | |
359 | * | |
360 | * If the current voltage is lower (indicator is higher) than factory | |
361 | * voltage, gain should be increased (gain table index decreased) by: | |
362 | * | |
363 | * 2 * (current - eeprom) / 7 | |
364 | * | |
365 | * If number of index steps in either direction turns out to be > 2, | |
366 | * something is wrong ... just use 0. | |
367 | * | |
368 | * NOTE: Voltage compensation is independent of band/channel. | |
369 | * | |
370 | * NOTE: "Initialize" uCode measures current voltage, which is assumed | |
371 | * to be constant after this initial measurement. Voltage | |
372 | * compensation for txpower (number of steps in gain table) | |
373 | * may be calculated once and used until the next uCode bootload. | |
374 | * | |
375 | * | |
376 | * 8) If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31), | |
377 | * adjust txpower for each transmitter chain, so txpower is balanced | |
378 | * between the two chains. There are 5 pairs of tx_atten[group][chain] | |
379 | * values in "initialize alive", one pair for each of 5 channel ranges: | |
380 | * | |
381 | * Group 0: 5 GHz channel 34-43 | |
382 | * Group 1: 5 GHz channel 44-70 | |
383 | * Group 2: 5 GHz channel 71-124 | |
384 | * Group 3: 5 GHz channel 125-200 | |
385 | * Group 4: 2.4 GHz all channels | |
386 | * | |
387 | * Add the tx_atten[group][chain] value to the index for the target chain. | |
388 | * The values are signed, but are in pairs of 0 and a non-negative number, | |
389 | * so as to reduce gain (if necessary) of the "hotter" channel. This | |
390 | * avoids any need to double-check for regulatory compliance after | |
391 | * this step. | |
392 | * | |
393 | * | |
394 | * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation | |
395 | * value to the index: | |
396 | * | |
397 | * Hardware rev B: 9 steps (4.5 dB) | |
398 | * Hardware rev C: 5 steps (2.5 dB) | |
399 | * | |
400 | * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG, | |
401 | * bits [3:2], 1 = B, 2 = C. | |
402 | * | |
403 | * NOTE: This compensation is in addition to any saturation backoff that | |
404 | * might have been applied in an earlier step. | |
405 | * | |
406 | * | |
407 | * 10) Select the gain table, based on band (2.4 vs 5 GHz). | |
408 | * | |
409 | * Limit the adjusted index to stay within the table! | |
410 | * | |
411 | * | |
412 | * 11) Read gain table entries for DSP and radio gain, place into appropriate | |
413 | * location(s) in command (struct iwl4965_txpowertable_cmd). | |
414 | */ | |
b481de9c | 415 | |
0c434c5a | 416 | /* Limit range of txpower output target to be between these values */ |
b481de9c ZY |
417 | #define IWL_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm = 1 milliwatt */ |
418 | #define IWL_TX_POWER_TARGET_POWER_MAX (16) /* 16 dBm */ | |
419 | ||
0c434c5a BC |
420 | /** |
421 | * When MIMO is used (2 transmitters operating simultaneously), driver should | |
422 | * limit each transmitter to deliver a max of 3 dB below the regulatory limit | |
423 | * for the device. That is, use half power for each transmitter, so total | |
424 | * txpower is within regulatory limits. | |
425 | * | |
426 | * The value "6" represents number of steps in gain table to reduce power 3 dB. | |
427 | * Each step is 1/2 dB. | |
428 | */ | |
429 | #define IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6) | |
430 | ||
431 | /** | |
432 | * CCK gain compensation. | |
433 | * | |
434 | * When calculating txpowers for CCK, after making sure that the target power | |
435 | * is within regulatory and saturation limits, driver must additionally | |
436 | * back off gain by adding these values to the gain table index. | |
437 | * | |
438 | * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG, | |
439 | * bits [3:2], 1 = B, 2 = C. | |
440 | */ | |
441 | #define IWL_TX_POWER_CCK_COMPENSATION_B_STEP (9) | |
442 | #define IWL_TX_POWER_CCK_COMPENSATION_C_STEP (5) | |
443 | ||
444 | /* | |
445 | * 4965 power supply voltage compensation for txpower | |
446 | */ | |
447 | #define TX_POWER_IWL_VOLTAGE_CODES_PER_03V (7) | |
448 | ||
449 | /** | |
450 | * Gain tables. | |
451 | * | |
452 | * The following tables contain pair of values for setting txpower, i.e. | |
453 | * gain settings for the output of the device's digital signal processor (DSP), | |
454 | * and for the analog gain structure of the transmitter. | |
455 | * | |
456 | * Each entry in the gain tables represents a step of 1/2 dB. Note that these | |
457 | * are *relative* steps, not indications of absolute output power. Output | |
458 | * power varies with temperature, voltage, and channel frequency, and also | |
459 | * requires consideration of average power (to satisfy regulatory constraints), | |
460 | * and peak power (to avoid distortion of the output signal). | |
461 | * | |
462 | * Each entry contains two values: | |
463 | * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained | |
464 | * linear value that multiplies the output of the digital signal processor, | |
465 | * before being sent to the analog radio. | |
466 | * 2) Radio gain. This sets the analog gain of the radio Tx path. | |
467 | * It is a coarser setting, and behaves in a logarithmic (dB) fashion. | |
468 | * | |
469 | * EEPROM contains factory calibration data for txpower. This maps actual | |
470 | * measured txpower levels to gain settings in the "well known" tables | |
471 | * below ("well-known" means here that both factory calibration *and* the | |
472 | * driver work with the same table). | |
473 | * | |
474 | * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table | |
475 | * has an extension (into negative indexes), in case the driver needs to | |
476 | * boost power setting for high device temperatures (higher than would be | |
477 | * present during factory calibration). A 5 Ghz EEPROM index of "40" | |
478 | * corresponds to the 49th entry in the table used by the driver. | |
479 | */ | |
480 | #define MIN_TX_GAIN_INDEX (0) /* highest gain, lowest idx, 2.4 */ | |
481 | #define MIN_TX_GAIN_INDEX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */ | |
482 | ||
483 | /** | |
484 | * 2.4 GHz gain table | |
485 | * | |
486 | * Index Dsp gain Radio gain | |
487 | * 0 110 0x3f (highest gain) | |
488 | * 1 104 0x3f | |
489 | * 2 98 0x3f | |
490 | * 3 110 0x3e | |
491 | * 4 104 0x3e | |
492 | * 5 98 0x3e | |
493 | * 6 110 0x3d | |
494 | * 7 104 0x3d | |
495 | * 8 98 0x3d | |
496 | * 9 110 0x3c | |
497 | * 10 104 0x3c | |
498 | * 11 98 0x3c | |
499 | * 12 110 0x3b | |
500 | * 13 104 0x3b | |
501 | * 14 98 0x3b | |
502 | * 15 110 0x3a | |
503 | * 16 104 0x3a | |
504 | * 17 98 0x3a | |
505 | * 18 110 0x39 | |
506 | * 19 104 0x39 | |
507 | * 20 98 0x39 | |
508 | * 21 110 0x38 | |
509 | * 22 104 0x38 | |
510 | * 23 98 0x38 | |
511 | * 24 110 0x37 | |
512 | * 25 104 0x37 | |
513 | * 26 98 0x37 | |
514 | * 27 110 0x36 | |
515 | * 28 104 0x36 | |
516 | * 29 98 0x36 | |
517 | * 30 110 0x35 | |
518 | * 31 104 0x35 | |
519 | * 32 98 0x35 | |
520 | * 33 110 0x34 | |
521 | * 34 104 0x34 | |
522 | * 35 98 0x34 | |
523 | * 36 110 0x33 | |
524 | * 37 104 0x33 | |
525 | * 38 98 0x33 | |
526 | * 39 110 0x32 | |
527 | * 40 104 0x32 | |
528 | * 41 98 0x32 | |
529 | * 42 110 0x31 | |
530 | * 43 104 0x31 | |
531 | * 44 98 0x31 | |
532 | * 45 110 0x30 | |
533 | * 46 104 0x30 | |
534 | * 47 98 0x30 | |
535 | * 48 110 0x6 | |
536 | * 49 104 0x6 | |
537 | * 50 98 0x6 | |
538 | * 51 110 0x5 | |
539 | * 52 104 0x5 | |
540 | * 53 98 0x5 | |
541 | * 54 110 0x4 | |
542 | * 55 104 0x4 | |
543 | * 56 98 0x4 | |
544 | * 57 110 0x3 | |
545 | * 58 104 0x3 | |
546 | * 59 98 0x3 | |
547 | * 60 110 0x2 | |
548 | * 61 104 0x2 | |
549 | * 62 98 0x2 | |
550 | * 63 110 0x1 | |
551 | * 64 104 0x1 | |
552 | * 65 98 0x1 | |
553 | * 66 110 0x0 | |
554 | * 67 104 0x0 | |
555 | * 68 98 0x0 | |
556 | * 69 97 0 | |
557 | * 70 96 0 | |
558 | * 71 95 0 | |
559 | * 72 94 0 | |
560 | * 73 93 0 | |
561 | * 74 92 0 | |
562 | * 75 91 0 | |
563 | * 76 90 0 | |
564 | * 77 89 0 | |
565 | * 78 88 0 | |
566 | * 79 87 0 | |
567 | * 80 86 0 | |
568 | * 81 85 0 | |
569 | * 82 84 0 | |
570 | * 83 83 0 | |
571 | * 84 82 0 | |
572 | * 85 81 0 | |
573 | * 86 80 0 | |
574 | * 87 79 0 | |
575 | * 88 78 0 | |
576 | * 89 77 0 | |
577 | * 90 76 0 | |
578 | * 91 75 0 | |
579 | * 92 74 0 | |
580 | * 93 73 0 | |
581 | * 94 72 0 | |
582 | * 95 71 0 | |
583 | * 96 70 0 | |
584 | * 97 69 0 | |
585 | * 98 68 0 | |
586 | */ | |
587 | ||
588 | /** | |
589 | * 5 GHz gain table | |
590 | * | |
591 | * Index Dsp gain Radio gain | |
592 | * -9 123 0x3F (highest gain) | |
593 | * -8 117 0x3F | |
594 | * -7 110 0x3F | |
595 | * -6 104 0x3F | |
596 | * -5 98 0x3F | |
597 | * -4 110 0x3E | |
598 | * -3 104 0x3E | |
599 | * -2 98 0x3E | |
600 | * -1 110 0x3D | |
601 | * 0 104 0x3D | |
602 | * 1 98 0x3D | |
603 | * 2 110 0x3C | |
604 | * 3 104 0x3C | |
605 | * 4 98 0x3C | |
606 | * 5 110 0x3B | |
607 | * 6 104 0x3B | |
608 | * 7 98 0x3B | |
609 | * 8 110 0x3A | |
610 | * 9 104 0x3A | |
611 | * 10 98 0x3A | |
612 | * 11 110 0x39 | |
613 | * 12 104 0x39 | |
614 | * 13 98 0x39 | |
615 | * 14 110 0x38 | |
616 | * 15 104 0x38 | |
617 | * 16 98 0x38 | |
618 | * 17 110 0x37 | |
619 | * 18 104 0x37 | |
620 | * 19 98 0x37 | |
621 | * 20 110 0x36 | |
622 | * 21 104 0x36 | |
623 | * 22 98 0x36 | |
624 | * 23 110 0x35 | |
625 | * 24 104 0x35 | |
626 | * 25 98 0x35 | |
627 | * 26 110 0x34 | |
628 | * 27 104 0x34 | |
629 | * 28 98 0x34 | |
630 | * 29 110 0x33 | |
631 | * 30 104 0x33 | |
632 | * 31 98 0x33 | |
633 | * 32 110 0x32 | |
634 | * 33 104 0x32 | |
635 | * 34 98 0x32 | |
636 | * 35 110 0x31 | |
637 | * 36 104 0x31 | |
638 | * 37 98 0x31 | |
639 | * 38 110 0x30 | |
640 | * 39 104 0x30 | |
641 | * 40 98 0x30 | |
642 | * 41 110 0x25 | |
643 | * 42 104 0x25 | |
644 | * 43 98 0x25 | |
645 | * 44 110 0x24 | |
646 | * 45 104 0x24 | |
647 | * 46 98 0x24 | |
648 | * 47 110 0x23 | |
649 | * 48 104 0x23 | |
650 | * 49 98 0x23 | |
651 | * 50 110 0x22 | |
652 | * 51 104 0x18 | |
653 | * 52 98 0x18 | |
654 | * 53 110 0x17 | |
655 | * 54 104 0x17 | |
656 | * 55 98 0x17 | |
657 | * 56 110 0x16 | |
658 | * 57 104 0x16 | |
659 | * 58 98 0x16 | |
660 | * 59 110 0x15 | |
661 | * 60 104 0x15 | |
662 | * 61 98 0x15 | |
663 | * 62 110 0x14 | |
664 | * 63 104 0x14 | |
665 | * 64 98 0x14 | |
666 | * 65 110 0x13 | |
667 | * 66 104 0x13 | |
668 | * 67 98 0x13 | |
669 | * 68 110 0x12 | |
670 | * 69 104 0x08 | |
671 | * 70 98 0x08 | |
672 | * 71 110 0x07 | |
673 | * 72 104 0x07 | |
674 | * 73 98 0x07 | |
675 | * 74 110 0x06 | |
676 | * 75 104 0x06 | |
677 | * 76 98 0x06 | |
678 | * 77 110 0x05 | |
679 | * 78 104 0x05 | |
680 | * 79 98 0x05 | |
681 | * 80 110 0x04 | |
682 | * 81 104 0x04 | |
683 | * 82 98 0x04 | |
684 | * 83 110 0x03 | |
685 | * 84 104 0x03 | |
686 | * 85 98 0x03 | |
687 | * 86 110 0x02 | |
688 | * 87 104 0x02 | |
689 | * 88 98 0x02 | |
690 | * 89 110 0x01 | |
691 | * 90 104 0x01 | |
692 | * 91 98 0x01 | |
693 | * 92 110 0x00 | |
694 | * 93 104 0x00 | |
695 | * 94 98 0x00 | |
696 | * 95 93 0x00 | |
697 | * 96 88 0x00 | |
698 | * 97 83 0x00 | |
699 | * 98 78 0x00 | |
700 | */ | |
b481de9c | 701 | |
0c434c5a BC |
702 | |
703 | /** | |
704 | * Sanity checks and default values for EEPROM regulatory levels. | |
705 | * If EEPROM values fall outside MIN/MAX range, use default values. | |
706 | * | |
707 | * Regulatory limits refer to the maximum average txpower allowed by | |
708 | * regulatory agencies in the geographies in which the device is meant | |
709 | * to be operated. These limits are SKU-specific (i.e. geography-specific), | |
710 | * and channel-specific; each channel has an individual regulatory limit | |
711 | * listed in the EEPROM. | |
712 | * | |
713 | * Units are in half-dBm (i.e. "34" means 17 dBm). | |
714 | */ | |
b481de9c ZY |
715 | #define IWL_TX_POWER_DEFAULT_REGULATORY_24 (34) |
716 | #define IWL_TX_POWER_DEFAULT_REGULATORY_52 (34) | |
717 | #define IWL_TX_POWER_REGULATORY_MIN (0) | |
718 | #define IWL_TX_POWER_REGULATORY_MAX (34) | |
0c434c5a BC |
719 | |
720 | /** | |
721 | * Sanity checks and default values for EEPROM saturation levels. | |
722 | * If EEPROM values fall outside MIN/MAX range, use default values. | |
723 | * | |
724 | * Saturation is the highest level that the output power amplifier can produce | |
725 | * without significant clipping distortion. This is a "peak" power level. | |
726 | * Different types of modulation (i.e. various "rates", and OFDM vs. CCK) | |
727 | * require differing amounts of backoff, relative to their average power output, | |
728 | * in order to avoid clipping distortion. | |
729 | * | |
730 | * Driver must make sure that it is violating neither the saturation limit, | |
731 | * nor the regulatory limit, when calculating Tx power settings for various | |
732 | * rates. | |
733 | * | |
734 | * Units are in half-dBm (i.e. "38" means 19 dBm). | |
735 | */ | |
b481de9c ZY |
736 | #define IWL_TX_POWER_DEFAULT_SATURATION_24 (38) |
737 | #define IWL_TX_POWER_DEFAULT_SATURATION_52 (38) | |
738 | #define IWL_TX_POWER_SATURATION_MIN (20) | |
739 | #define IWL_TX_POWER_SATURATION_MAX (50) | |
740 | ||
0c434c5a BC |
741 | /** |
742 | * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance) | |
743 | * and thermal Txpower calibration. | |
744 | * | |
745 | * When calculating txpower, driver must compensate for current device | |
746 | * temperature; higher temperature requires higher gain. Driver must calculate | |
747 | * current temperature (see "4965 temperature calculation"), then compare vs. | |
748 | * factory calibration temperature in EEPROM; if current temperature is higher | |
749 | * than factory temperature, driver must *increase* gain by proportions shown | |
750 | * in table below. If current temperature is lower than factory, driver must | |
751 | * *decrease* gain. | |
752 | * | |
753 | * Different frequency ranges require different compensation, as shown below. | |
754 | */ | |
755 | /* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */ | |
b481de9c ZY |
756 | #define CALIB_IWL_TX_ATTEN_GR1_FCH 34 |
757 | #define CALIB_IWL_TX_ATTEN_GR1_LCH 43 | |
0c434c5a BC |
758 | |
759 | /* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */ | |
b481de9c ZY |
760 | #define CALIB_IWL_TX_ATTEN_GR2_FCH 44 |
761 | #define CALIB_IWL_TX_ATTEN_GR2_LCH 70 | |
0c434c5a BC |
762 | |
763 | /* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */ | |
b481de9c ZY |
764 | #define CALIB_IWL_TX_ATTEN_GR3_FCH 71 |
765 | #define CALIB_IWL_TX_ATTEN_GR3_LCH 124 | |
0c434c5a BC |
766 | |
767 | /* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */ | |
b481de9c ZY |
768 | #define CALIB_IWL_TX_ATTEN_GR4_FCH 125 |
769 | #define CALIB_IWL_TX_ATTEN_GR4_LCH 200 | |
0c434c5a BC |
770 | |
771 | /* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */ | |
b481de9c ZY |
772 | #define CALIB_IWL_TX_ATTEN_GR5_FCH 1 |
773 | #define CALIB_IWL_TX_ATTEN_GR5_LCH 20 | |
774 | ||
0c434c5a BC |
775 | enum { |
776 | CALIB_CH_GROUP_1 = 0, | |
777 | CALIB_CH_GROUP_2 = 1, | |
778 | CALIB_CH_GROUP_3 = 2, | |
779 | CALIB_CH_GROUP_4 = 3, | |
780 | CALIB_CH_GROUP_5 = 4, | |
781 | CALIB_CH_GROUP_MAX | |
782 | }; | |
783 | ||
b481de9c ZY |
784 | /********************* END TXPOWER *****************************************/ |
785 | ||
aad14143 | 786 | /****************************/ |
b481de9c | 787 | /* Flow Handler Definitions */ |
aad14143 | 788 | /****************************/ |
b481de9c | 789 | |
4d3cf5f7 | 790 | /** |
aad14143 BC |
791 | * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) |
792 | * Addresses are offsets from device's PCI hardware base address. | |
793 | */ | |
b481de9c ZY |
794 | #define FH_MEM_LOWER_BOUND (0x1000) |
795 | #define FH_MEM_UPPER_BOUND (0x1EF0) | |
796 | ||
aad14143 BC |
797 | /** |
798 | * Keep-Warm (KW) buffer base address. | |
799 | * | |
800 | * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the | |
801 | * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency | |
802 | * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host | |
803 | * from going into a power-savings mode that would cause higher DRAM latency, | |
804 | * and possible data over/under-runs, before all Tx/Rx is complete. | |
805 | * | |
806 | * Driver loads IWL_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) | |
807 | * of the buffer, which must be 4K aligned. Once this is set up, the 4965 | |
808 | * automatically invokes keep-warm accesses when normal accesses might not | |
809 | * be sufficient to maintain fast DRAM response. | |
810 | * | |
811 | * Bit fields: | |
812 | * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned | |
813 | */ | |
b481de9c ZY |
814 | #define IWL_FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) |
815 | ||
aad14143 | 816 | |
4d3cf5f7 BC |
817 | /** |
818 | * TFD Circular Buffers Base (CBBC) addresses | |
819 | * | |
820 | * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident | |
821 | * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) | |
822 | * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04 | |
823 | * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte | |
824 | * aligned (address bits 0-7 must be 0). | |
825 | * | |
826 | * Bit fields in each pointer register: | |
827 | * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned | |
828 | */ | |
b481de9c ZY |
829 | #define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) |
830 | #define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) | |
4d3cf5f7 BC |
831 | |
832 | /* Find TFD CB base pointer for given queue (range 0-15). */ | |
b481de9c ZY |
833 | #define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4) |
834 | ||
4d3cf5f7 BC |
835 | |
836 | /** | |
837 | * Rx SRAM Control and Status Registers (RSCSR) | |
838 | * | |
839 | * These registers provide handshake between driver and 4965 for the Rx queue | |
840 | * (this queue handles *all* command responses, notifications, Rx data, etc. | |
841 | * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx | |
842 | * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can | |
843 | * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer | |
844 | * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 | |
845 | * mapping between RBDs and RBs. | |
846 | * | |
847 | * Driver must allocate host DRAM memory for the following, and set the | |
848 | * physical address of each into 4965 registers: | |
849 | * | |
850 | * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 | |
851 | * entries (although any power of 2, up to 4096, is selectable by driver). | |
852 | * Each entry (1 dword) points to a receive buffer (RB) of consistent size | |
853 | * (typically 4K, although 8K or 16K are also selectable by driver). | |
854 | * Driver sets up RB size and number of RBDs in the CB via Rx config | |
855 | * register FH_MEM_RCSR_CHNL0_CONFIG_REG. | |
856 | * | |
857 | * Bit fields within one RBD: | |
858 | * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned | |
859 | * | |
860 | * Driver sets physical address [35:8] of base of RBD circular buffer | |
861 | * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. | |
862 | * | |
863 | * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers | |
864 | * (RBs) have been filled, via a "write pointer", actually the index of | |
865 | * the RB's corresponding RBD within the circular buffer. Driver sets | |
866 | * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. | |
867 | * | |
868 | * Bit fields in lower dword of Rx status buffer (upper dword not used | |
869 | * by driver; see struct iwl4965_shared, val0): | |
870 | * 31-12: Not used by driver | |
871 | * 11- 0: Index of last filled Rx buffer descriptor | |
872 | * (4965 writes, driver reads this value) | |
873 | * | |
874 | * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must | |
875 | * enter pointers to these RBs into contiguous RBD circular buffer entries, | |
876 | * and update the 4965's "write" index register, FH_RSCSR_CHNL0_RBDCB_WPTR_REG. | |
877 | * | |
878 | * This "write" index corresponds to the *next* RBD that the driver will make | |
879 | * available, i.e. one RBD past the tail of the ready-to-fill RBDs within | |
880 | * the circular buffer. This value should initially be 0 (before preparing any | |
881 | * RBs), should be 8 after preparing the first 8 RBs (for example), and must | |
882 | * wrap back to 0 at the end of the circular buffer (but don't wrap before | |
883 | * "read" index has advanced past 1! See below). | |
884 | * NOTE: 4965 EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. | |
885 | * | |
886 | * As the 4965 fills RBs (referenced from contiguous RBDs within the circular | |
887 | * buffer), it updates the Rx status buffer in host DRAM, 2) described above, | |
888 | * to tell the driver the index of the latest filled RBD. The driver must | |
889 | * read this "read" index from DRAM after receiving an Rx interrupt from 4965. | |
890 | * | |
891 | * The driver must also internally keep track of a third index, which is the | |
892 | * next RBD to process. When receiving an Rx interrupt, driver should process | |
893 | * all filled but unprocessed RBs up to, but not including, the RB | |
894 | * corresponding to the "read" index. For example, if "read" index becomes "1", | |
895 | * driver may process the RB pointed to by RBD 0. Depending on volume of | |
896 | * traffic, there may be many RBs to process. | |
897 | * | |
898 | * If read index == write index, 4965 thinks there is no room to put new data. | |
899 | * Due to this, the maximum number of filled RBs is 255, instead of 256. To | |
900 | * be safe, make sure that there is a gap of at least 2 RBDs between "write" | |
901 | * and "read" indexes; that is, make sure that there are no more than 254 | |
902 | * buffers waiting to be filled. | |
903 | */ | |
b481de9c ZY |
904 | #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) |
905 | #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) | |
906 | #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) | |
907 | ||
4d3cf5f7 BC |
908 | /** |
909 | * Physical base address of 8-byte Rx Status buffer. | |
910 | * Bit fields: | |
911 | * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. | |
912 | */ | |
b481de9c | 913 | #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) |
4d3cf5f7 BC |
914 | |
915 | /** | |
916 | * Physical base address of Rx Buffer Descriptor Circular Buffer. | |
917 | * Bit fields: | |
918 | * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. | |
919 | */ | |
b481de9c | 920 | #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) |
4d3cf5f7 BC |
921 | |
922 | /** | |
923 | * Rx write pointer (index, really!). | |
924 | * Bit fields: | |
925 | * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. | |
926 | * NOTE: For 256-entry circular buffer, use only bits [7:0]. | |
927 | */ | |
b481de9c | 928 | #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) |
483fd7e5 | 929 | #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG) |
b481de9c | 930 | |
4d3cf5f7 BC |
931 | |
932 | /** | |
933 | * Rx Config/Status Registers (RCSR) | |
934 | * Rx Config Reg for channel 0 (only channel used) | |
935 | * | |
936 | * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for | |
937 | * normal operation (see bit fields). | |
938 | * | |
939 | * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. | |
940 | * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for | |
941 | * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. | |
942 | * | |
943 | * Bit fields: | |
944 | * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, | |
945 | * '10' operate normally | |
946 | * 29-24: reserved | |
947 | * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), | |
948 | * min "5" for 32 RBDs, max "12" for 4096 RBDs. | |
949 | * 19-18: reserved | |
950 | * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, | |
951 | * '10' 12K, '11' 16K. | |
952 | * 15-14: reserved | |
953 | * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) | |
954 | * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) | |
955 | * typical value 0x10 (about 1/2 msec) | |
956 | * 3- 0: reserved | |
957 | */ | |
b481de9c ZY |
958 | #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) |
959 | #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) | |
960 | #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) | |
961 | ||
962 | #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) | |
963 | ||
4d3cf5f7 BC |
964 | #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MASK (0x00000FF0) /* bit 4-11 */ |
965 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MASK (0x00001000) /* bit 12 */ | |
966 | #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MASK (0x00008000) /* bit 15 */ | |
967 | #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MASK (0x00030000) /* bits 16-17 */ | |
968 | #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MASK (0x00F00000) /* bits 20-23 */ | |
969 | #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */ | |
970 | ||
971 | #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20) | |
9ee1ba47 RR |
972 | #define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_BITSHIFT (4) |
973 | #define RX_RB_TIMEOUT (0x10) | |
4d3cf5f7 BC |
974 | |
975 | #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) | |
976 | #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) | |
977 | #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) | |
978 | ||
9ee1ba47 RR |
979 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) |
980 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) | |
981 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) | |
982 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) | |
4d3cf5f7 BC |
983 | |
984 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) | |
985 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) | |
986 | ||
987 | ||
988 | /** | |
989 | * Rx Shared Status Registers (RSSR) | |
990 | * | |
991 | * After stopping Rx DMA channel (writing 0 to FH_MEM_RCSR_CHNL0_CONFIG_REG), | |
992 | * driver must poll FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. | |
993 | * | |
994 | * Bit fields: | |
995 | * 24: 1 = Channel 0 is idle | |
996 | * | |
997 | * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV contain | |
998 | * default values that should not be altered by the driver. | |
999 | */ | |
b481de9c ZY |
1000 | #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) |
1001 | #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) | |
4d3cf5f7 | 1002 | |
b481de9c ZY |
1003 | #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) |
1004 | #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) | |
1005 | #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008) | |
1006 | ||
4d3cf5f7 BC |
1007 | #define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) |
1008 | ||
483fd7e5 BC |
1009 | |
1010 | /** | |
1011 | * Transmit DMA Channel Control/Status Registers (TCSR) | |
1012 | * | |
1013 | * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels | |
1014 | * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, | |
1015 | * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. | |
1016 | * | |
1017 | * To use a Tx DMA channel, driver must initialize its | |
1018 | * IWL_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: | |
1019 | * | |
1020 | * IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
1021 | * IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | |
1022 | * | |
1023 | * All other bits should be 0. | |
1024 | * | |
1025 | * Bit fields: | |
1026 | * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, | |
1027 | * '10' operate normally | |
1028 | * 29- 4: Reserved, set to "0" | |
1029 | * 3: Enable internal DMA requests (1, normal operation), disable (0) | |
1030 | * 2- 0: Reserved, set to "0" | |
1031 | */ | |
aad14143 BC |
1032 | #define IWL_FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) |
1033 | #define IWL_FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60) | |
b481de9c | 1034 | |
483fd7e5 | 1035 | /* Find Control/Status reg for given Tx DMA/FIFO channel */ |
b481de9c ZY |
1036 | #define IWL_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ |
1037 | (IWL_FH_TCSR_LOWER_BOUND + 0x20 * _chnl) | |
1038 | ||
483fd7e5 BC |
1039 | #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) |
1040 | #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) | |
1041 | ||
1042 | #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) | |
1043 | #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) | |
1044 | #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) | |
1045 | ||
1046 | /** | |
1047 | * Tx Shared Status Registers (TSSR) | |
1048 | * | |
1049 | * After stopping Tx DMA channel (writing 0 to | |
1050 | * IWL_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll | |
1051 | * IWL_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle | |
1052 | * (channel's buffers empty | no pending requests). | |
1053 | * | |
1054 | * Bit fields: | |
1055 | * 31-24: 1 = Channel buffers empty (channel 7:0) | |
1056 | * 23-16: 1 = No pending requests (channel 7:0) | |
1057 | */ | |
aad14143 BC |
1058 | #define IWL_FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0) |
1059 | #define IWL_FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0) | |
b481de9c | 1060 | |
b481de9c ZY |
1061 | #define IWL_FH_TSSR_TX_STATUS_REG (IWL_FH_TSSR_LOWER_BOUND + 0x010) |
1062 | ||
b481de9c ZY |
1063 | #define IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \ |
1064 | ((1 << (_chnl)) << 24) | |
1065 | #define IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \ | |
1066 | ((1 << (_chnl)) << 16) | |
1067 | ||
1068 | #define IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \ | |
1069 | (IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \ | |
1070 | IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl)) | |
1071 | ||
b481de9c | 1072 | |
e3851447 BC |
1073 | /********************* START TX SCHEDULER *************************************/ |
1074 | ||
1075 | /** | |
1076 | * 4965 Tx Scheduler | |
1077 | * | |
1078 | * The Tx Scheduler selects the next frame to be transmitted, chosing TFDs | |
1079 | * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in | |
1080 | * host DRAM. It steers each frame's Tx command (which contains the frame | |
1081 | * data) into one of up to 7 prioritized Tx DMA FIFO channels within the | |
1082 | * device. A queue maps to only one (selectable by driver) Tx DMA channel, | |
1083 | * but one DMA channel may take input from several queues. | |
1084 | * | |
1085 | * Tx DMA channels have dedicated purposes. For 4965, they are used as follows: | |
1086 | * | |
1087 | * 0 -- EDCA BK (background) frames, lowest priority | |
1088 | * 1 -- EDCA BE (best effort) frames, normal priority | |
1089 | * 2 -- EDCA VI (video) frames, higher priority | |
1090 | * 3 -- EDCA VO (voice) and management frames, highest priority | |
1091 | * 4 -- Commands (e.g. RXON, etc.) | |
1092 | * 5 -- HCCA short frames | |
1093 | * 6 -- HCCA long frames | |
1094 | * 7 -- not used by driver (device-internal only) | |
1095 | * | |
1096 | * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. | |
1097 | * In addition, driver can map queues 7-15 to Tx DMA/FIFO channels 0-3 to | |
1098 | * support 11n aggregation via EDCA DMA channels. | |
1099 | * | |
1100 | * The driver sets up each queue to work in one of two modes: | |
1101 | * | |
1102 | * 1) Scheduler-Ack, in which the scheduler automatically supports a | |
1103 | * block-ack (BA) window of up to 64 TFDs. In this mode, each queue | |
1104 | * contains TFDs for a unique combination of Recipient Address (RA) | |
1105 | * and Traffic Identifier (TID), that is, traffic of a given | |
1106 | * Quality-Of-Service (QOS) priority, destined for a single station. | |
1107 | * | |
1108 | * In scheduler-ack mode, the scheduler keeps track of the Tx status of | |
1109 | * each frame within the BA window, including whether it's been transmitted, | |
1110 | * and whether it's been acknowledged by the receiving station. The device | |
1111 | * automatically processes block-acks received from the receiving STA, | |
1112 | * and reschedules un-acked frames to be retransmitted (successful | |
1113 | * Tx completion may end up being out-of-order). | |
1114 | * | |
1115 | * The driver must maintain the queue's Byte Count table in host DRAM | |
1116 | * (struct iwl4965_sched_queue_byte_cnt_tbl) for this mode. | |
1117 | * This mode does not support fragmentation. | |
1118 | * | |
1119 | * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. | |
1120 | * The device may automatically retry Tx, but will retry only one frame | |
1121 | * at a time, until receiving ACK from receiving station, or reaching | |
1122 | * retry limit and giving up. | |
1123 | * | |
1124 | * The command queue (#4) must use this mode! | |
1125 | * This mode does not require use of the Byte Count table in host DRAM. | |
1126 | * | |
1127 | * Driver controls scheduler operation via 3 means: | |
1128 | * 1) Scheduler registers | |
1129 | * 2) Shared scheduler data base in internal 4956 SRAM | |
1130 | * 3) Shared data in host DRAM | |
1131 | * | |
1132 | * Initialization: | |
1133 | * | |
1134 | * When loading, driver should allocate memory for: | |
1135 | * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. | |
1136 | * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory | |
1137 | * (1024 bytes for each queue). | |
1138 | * | |
1139 | * After receiving "Alive" response from uCode, driver must initialize | |
1140 | * the scheduler (especially for queue #4, the command queue, otherwise | |
1141 | * the driver can't issue commands!): | |
1142 | */ | |
1143 | ||
1144 | /** | |
1145 | * Max Tx window size is the max number of contiguous TFDs that the scheduler | |
1146 | * can keep track of at one time when creating block-ack chains of frames. | |
1147 | * Note that "64" matches the number of ack bits in a block-ack packet. | |
1148 | * Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize | |
1149 | * SCD_CONTEXT_QUEUE_OFFSET(x) values. | |
1150 | */ | |
b481de9c ZY |
1151 | #define SCD_WIN_SIZE 64 |
1152 | #define SCD_FRAME_LIMIT 64 | |
1153 | ||
e3851447 BC |
1154 | /* SCD registers are internal, must be accessed via HBUS_TARG_PRPH regs */ |
1155 | #define SCD_START_OFFSET 0xa02c00 | |
1156 | ||
1157 | /* | |
1158 | * 4965 tells driver SRAM address for internal scheduler structs via this reg. | |
1159 | * Value is valid only after "Alive" response from uCode. | |
1160 | */ | |
1161 | #define SCD_SRAM_BASE_ADDR (SCD_START_OFFSET + 0x0) | |
b481de9c | 1162 | |
e3851447 BC |
1163 | /* |
1164 | * Driver may need to update queue-empty bits after changing queue's | |
1165 | * write and read pointers (indexes) during (re-)initialization (i.e. when | |
1166 | * scheduler is not tracking what's happening). | |
1167 | * Bit fields: | |
1168 | * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit | |
1169 | * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty | |
1170 | * NOTE: This register is not used by Linux driver. | |
1171 | */ | |
1172 | #define SCD_EMPTY_BITS (SCD_START_OFFSET + 0x4) | |
1173 | ||
1174 | /* | |
1175 | * Physical base address of array of byte count (BC) circular buffers (CBs). | |
1176 | * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode. | |
1177 | * This register points to BC CB for queue 0, must be on 1024-byte boundary. | |
1178 | * Others are spaced by 1024 bytes. | |
1179 | * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad. | |
1180 | * (Index into a queue's BC CB) = (index into queue's TFD CB) = (SSN & 0xff). | |
1181 | * Bit fields: | |
1182 | * 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned. | |
1183 | */ | |
1184 | #define SCD_DRAM_BASE_ADDR (SCD_START_OFFSET + 0x10) | |
1185 | ||
1186 | /* | |
1187 | * Enables any/all Tx DMA/FIFO channels. | |
1188 | * Scheduler generates requests for only the active channels. | |
1189 | * Set this to 0xff to enable all 8 channels (normal usage). | |
1190 | * Bit fields: | |
1191 | * 7- 0: Enable (1), disable (0), one bit for each channel 0-7 | |
1192 | */ | |
1193 | #define SCD_TXFACT (SCD_START_OFFSET + 0x1c) | |
1194 | ||
1195 | /* Mask to enable contiguous Tx DMA/FIFO channels between "lo" and "hi". */ | |
b481de9c | 1196 | #define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \ |
8a1b0245 | 1197 | ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) |
b481de9c | 1198 | |
e3851447 BC |
1199 | /* |
1200 | * Queue (x) Write Pointers (indexes, really!), one for each Tx queue. | |
1201 | * Initialized and updated by driver as new TFDs are added to queue. | |
1202 | * NOTE: If using Block Ack, index must correspond to frame's | |
1203 | * Start Sequence Number; index = (SSN & 0xff) | |
1204 | * NOTE: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses? | |
1205 | */ | |
1206 | #define SCD_QUEUE_WRPTR(x) (SCD_START_OFFSET + 0x24 + (x) * 4) | |
1207 | ||
1208 | /* | |
1209 | * Queue (x) Read Pointers (indexes, really!), one for each Tx queue. | |
1210 | * For FIFO mode, index indicates next frame to transmit. | |
1211 | * For Scheduler-ACK mode, index indicates first frame in Tx window. | |
1212 | * Initialized by driver, updated by scheduler. | |
1213 | */ | |
1214 | #define SCD_QUEUE_RDPTR(x) (SCD_START_OFFSET + 0x64 + (x) * 4) | |
1215 | ||
1216 | /* | |
1217 | * Select which queues work in chain mode (1) vs. not (0). | |
1218 | * Use chain mode to build chains of aggregated frames. | |
1219 | * Bit fields: | |
1220 | * 31-16: Reserved | |
1221 | * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time | |
1222 | * NOTE: If driver sets up queue for chain mode, it should be also set up | |
1223 | * Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x). | |
1224 | */ | |
1225 | #define SCD_QUEUECHAIN_SEL (SCD_START_OFFSET + 0xd0) | |
1226 | ||
1227 | /* | |
1228 | * Select which queues interrupt driver when scheduler increments | |
1229 | * a queue's read pointer (index). | |
1230 | * Bit fields: | |
1231 | * 31-16: Reserved | |
1232 | * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled | |
1233 | * NOTE: This functionality is apparently a no-op; driver relies on interrupts | |
1234 | * from Rx queue to read Tx command responses and update Tx queues. | |
1235 | */ | |
1236 | #define SCD_INTERRUPT_MASK (SCD_START_OFFSET + 0xe4) | |
1237 | ||
1238 | /* | |
1239 | * Queue search status registers. One for each queue. | |
1240 | * Sets up queue mode and assigns queue to Tx DMA channel. | |
1241 | * Bit fields: | |
1242 | * 19-10: Write mask/enable bits for bits 0-9 | |
1243 | * 9: Driver should init to "0" | |
1244 | * 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0). | |
1245 | * Driver should init to "1" for aggregation mode, or "0" otherwise. | |
1246 | * 7-6: Driver should init to "0" | |
1247 | * 5: Window Size Left; indicates whether scheduler can request | |
1248 | * another TFD, based on window size, etc. Driver should init | |
1249 | * this bit to "1" for aggregation mode, or "0" for non-agg. | |
1250 | * 4-1: Tx FIFO to use (range 0-7). | |
1251 | * 0: Queue is active (1), not active (0). | |
1252 | * Other bits should be written as "0" | |
1253 | * | |
1254 | * NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled | |
1255 | * via SCD_QUEUECHAIN_SEL. | |
1256 | */ | |
1257 | #define SCD_QUEUE_STATUS_BITS(x) (SCD_START_OFFSET + 0x104 + (x) * 4) | |
1258 | ||
1259 | /* Bit field positions */ | |
b481de9c ZY |
1260 | #define SCD_QUEUE_STTS_REG_POS_ACTIVE (0) |
1261 | #define SCD_QUEUE_STTS_REG_POS_TXF (1) | |
1262 | #define SCD_QUEUE_STTS_REG_POS_WSL (5) | |
1263 | #define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8) | |
e3851447 BC |
1264 | |
1265 | /* Write masks */ | |
b481de9c ZY |
1266 | #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10) |
1267 | #define SCD_QUEUE_STTS_REG_MSK (0x0007FC00) | |
1268 | ||
e3851447 BC |
1269 | /** |
1270 | * 4965 internal SRAM structures for scheduler, shared with driver ... | |
1271 | * | |
1272 | * Driver should clear and initialize the following areas after receiving | |
1273 | * "Alive" response from 4965 uCode, i.e. after initial | |
1274 | * uCode load, or after a uCode load done for error recovery: | |
1275 | * | |
1276 | * SCD_CONTEXT_DATA_OFFSET (size 128 bytes) | |
1277 | * SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes) | |
1278 | * SCD_TRANSLATE_TBL_OFFSET (size 32 bytes) | |
1279 | * | |
1280 | * Driver accesses SRAM via HBUS_TARG_MEM_* registers. | |
1281 | * Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR. | |
1282 | * All OFFSET values must be added to this base address. | |
1283 | */ | |
1284 | ||
1285 | /* | |
1286 | * Queue context. One 8-byte entry for each of 16 queues. | |
1287 | * | |
1288 | * Driver should clear this entire area (size 0x80) to 0 after receiving | |
1289 | * "Alive" notification from uCode. Additionally, driver should init | |
1290 | * each queue's entry as follows: | |
1291 | * | |
1292 | * LS Dword bit fields: | |
1293 | * 0-06: Max Tx window size for Scheduler-ACK. Driver should init to 64. | |
1294 | * | |
1295 | * MS Dword bit fields: | |
1296 | * 16-22: Frame limit. Driver should init to 10 (0xa). | |
1297 | * | |
1298 | * Driver should init all other bits to 0. | |
1299 | * | |
1300 | * Init must be done after driver receives "Alive" response from 4965 uCode, | |
1301 | * and when setting up queue for aggregation. | |
1302 | */ | |
1303 | #define SCD_CONTEXT_DATA_OFFSET 0x380 | |
1304 | #define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8)) | |
1305 | ||
b481de9c ZY |
1306 | #define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0) |
1307 | #define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F) | |
b481de9c ZY |
1308 | #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) |
1309 | #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) | |
1310 | ||
e3851447 BC |
1311 | /* |
1312 | * Tx Status Bitmap | |
1313 | * | |
1314 | * Driver should clear this entire area (size 0x100) to 0 after receiving | |
1315 | * "Alive" notification from uCode. Area is used only by device itself; | |
1316 | * no other support (besides clearing) is required from driver. | |
1317 | */ | |
1318 | #define SCD_TX_STTS_BITMAP_OFFSET 0x400 | |
1319 | ||
1320 | /* | |
1321 | * RAxTID to queue translation mapping. | |
1322 | * | |
1323 | * When queue is in Scheduler-ACK mode, frames placed in a that queue must be | |
1324 | * for only one combination of receiver address (RA) and traffic ID (TID), i.e. | |
1325 | * one QOS priority level destined for one station (for this wireless link, | |
1326 | * not final destination). The SCD_TRANSLATE_TABLE area provides 16 16-bit | |
1327 | * mappings, one for each of the 16 queues. If queue is not in Scheduler-ACK | |
1328 | * mode, the device ignores the mapping value. | |
1329 | * | |
1330 | * Bit fields, for each 16-bit map: | |
1331 | * 15-9: Reserved, set to 0 | |
1332 | * 8-4: Index into device's station table for recipient station | |
1333 | * 3-0: Traffic ID (tid), range 0-15 | |
1334 | * | |
1335 | * Driver should clear this entire area (size 32 bytes) to 0 after receiving | |
1336 | * "Alive" notification from uCode. To update a 16-bit map value, driver | |
1337 | * must read a dword-aligned value from device SRAM, replace the 16-bit map | |
1338 | * value of interest, and write the dword value back into device SRAM. | |
1339 | */ | |
1340 | #define SCD_TRANSLATE_TBL_OFFSET 0x500 | |
1341 | ||
1342 | /* Find translation table dword to read/write for given queue */ | |
1343 | #define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ | |
1344 | ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc) | |
1345 | ||
1346 | #define SCD_TXFIFO_POS_TID (0) | |
1347 | #define SCD_TXFIFO_POS_RA (4) | |
1348 | #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) | |
1349 | ||
1350 | /*********************** END TX SCHEDULER *************************************/ | |
1351 | ||
bb8c093b | 1352 | static inline u8 iwl4965_hw_get_rate(__le32 rate_n_flags) |
b481de9c ZY |
1353 | { |
1354 | return le32_to_cpu(rate_n_flags) & 0xFF; | |
1355 | } | |
bb8c093b | 1356 | static inline u16 iwl4965_hw_get_rate_n_flags(__le32 rate_n_flags) |
b481de9c ZY |
1357 | { |
1358 | return le32_to_cpu(rate_n_flags) & 0xFFFF; | |
1359 | } | |
bb8c093b | 1360 | static inline __le32 iwl4965_hw_set_rate_n_flags(u8 rate, u16 flags) |
b481de9c ZY |
1361 | { |
1362 | return cpu_to_le32(flags|(u16)rate); | |
1363 | } | |
1364 | ||
5d5456fe BC |
1365 | |
1366 | /** | |
1367 | * Tx/Rx Queues | |
1368 | * | |
1369 | * Most communication between driver and 4965 is via queues of data buffers. | |
1370 | * For example, all commands that the driver issues to device's embedded | |
1371 | * controller (uCode) are via the command queue (one of the Tx queues). All | |
1372 | * uCode command responses/replies/notifications, including Rx frames, are | |
1373 | * conveyed from uCode to driver via the Rx queue. | |
1374 | * | |
1375 | * Most support for these queues, including handshake support, resides in | |
1376 | * structures in host DRAM, shared between the driver and the device. When | |
1377 | * allocating this memory, the driver must make sure that data written by | |
1378 | * the host CPU updates DRAM immediately (and does not get "stuck" in CPU's | |
1379 | * cache memory), so DRAM and cache are consistent, and the device can | |
1380 | * immediately see changes made by the driver. | |
1381 | * | |
1382 | * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via | |
1383 | * up to 7 DMA channels (FIFOs). Each Tx queue is supported by a circular array | |
1384 | * in DRAM containing 256 Transmit Frame Descriptors (TFDs). | |
1385 | */ | |
1386 | #define IWL4965_MAX_WIN_SIZE 64 | |
1387 | #define IWL4965_QUEUE_SIZE 256 | |
1388 | #define IWL4965_NUM_FIFOS 7 | |
1389 | #define IWL_MAX_NUM_QUEUES 16 | |
1390 | ||
1391 | ||
1392 | /** | |
1393 | * struct iwl4965_tfd_frame_data | |
1394 | * | |
1395 | * Describes up to 2 buffers containing (contiguous) portions of a Tx frame. | |
1396 | * Each buffer must be on dword boundary. | |
1397 | * Up to 10 iwl_tfd_frame_data structures, describing up to 20 buffers, | |
1398 | * may be filled within a TFD (iwl_tfd_frame). | |
1399 | * | |
1400 | * Bit fields in tb1_addr: | |
1401 | * 31- 0: Tx buffer 1 address bits [31:0] | |
1402 | * | |
1403 | * Bit fields in val1: | |
1404 | * 31-16: Tx buffer 2 address bits [15:0] | |
1405 | * 15- 4: Tx buffer 1 length (bytes) | |
1406 | * 3- 0: Tx buffer 1 address bits [32:32] | |
1407 | * | |
1408 | * Bit fields in val2: | |
1409 | * 31-20: Tx buffer 2 length (bytes) | |
1410 | * 19- 0: Tx buffer 2 address bits [35:16] | |
1411 | */ | |
bb8c093b | 1412 | struct iwl4965_tfd_frame_data { |
b481de9c ZY |
1413 | __le32 tb1_addr; |
1414 | ||
1415 | __le32 val1; | |
1416 | /* __le32 ptb1_32_35:4; */ | |
1417 | #define IWL_tb1_addr_hi_POS 0 | |
1418 | #define IWL_tb1_addr_hi_LEN 4 | |
1419 | #define IWL_tb1_addr_hi_SYM val1 | |
1420 | /* __le32 tb_len1:12; */ | |
1421 | #define IWL_tb1_len_POS 4 | |
1422 | #define IWL_tb1_len_LEN 12 | |
1423 | #define IWL_tb1_len_SYM val1 | |
1424 | /* __le32 ptb2_0_15:16; */ | |
1425 | #define IWL_tb2_addr_lo16_POS 16 | |
1426 | #define IWL_tb2_addr_lo16_LEN 16 | |
1427 | #define IWL_tb2_addr_lo16_SYM val1 | |
1428 | ||
1429 | __le32 val2; | |
1430 | /* __le32 ptb2_16_35:20; */ | |
1431 | #define IWL_tb2_addr_hi20_POS 0 | |
1432 | #define IWL_tb2_addr_hi20_LEN 20 | |
1433 | #define IWL_tb2_addr_hi20_SYM val2 | |
1434 | /* __le32 tb_len2:12; */ | |
1435 | #define IWL_tb2_len_POS 20 | |
1436 | #define IWL_tb2_len_LEN 12 | |
1437 | #define IWL_tb2_len_SYM val2 | |
1438 | } __attribute__ ((packed)); | |
1439 | ||
5d5456fe BC |
1440 | |
1441 | /** | |
1442 | * struct iwl4965_tfd_frame | |
1443 | * | |
1444 | * Transmit Frame Descriptor (TFD) | |
1445 | * | |
1446 | * 4965 supports up to 16 Tx queues resident in host DRAM. | |
1447 | * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. | |
1448 | * Both driver and device share these circular buffers, each of which must be | |
1449 | * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes for 4965. | |
1450 | * | |
1451 | * Driver must indicate the physical address of the base of each | |
1452 | * circular buffer via the 4965's FH_MEM_CBBC_QUEUE registers. | |
1453 | * | |
1454 | * Each TFD contains pointer/size information for up to 20 data buffers | |
1455 | * in host DRAM. These buffers collectively contain the (one) frame described | |
1456 | * by the TFD. Each buffer must be a single contiguous block of memory within | |
1457 | * itself, but buffers may be scattered in host DRAM. Each buffer has max size | |
1458 | * of (4K - 4). The 4965 concatenates all of a TFD's buffers into a single | |
1459 | * Tx frame, up to 8 KBytes in size. | |
1460 | * | |
1461 | * Bit fields in the control dword (val0): | |
1462 | * 31-30: # dwords (0-3) of padding required at end of frame for 16-byte bound | |
1463 | * 29: reserved | |
1464 | * 28-24: # Transmit Buffer Descriptors in TFD | |
1465 | * 23- 0: reserved | |
1466 | * | |
1467 | * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. | |
1468 | */ | |
bb8c093b | 1469 | struct iwl4965_tfd_frame { |
b481de9c ZY |
1470 | __le32 val0; |
1471 | /* __le32 rsvd1:24; */ | |
1472 | /* __le32 num_tbs:5; */ | |
1473 | #define IWL_num_tbs_POS 24 | |
1474 | #define IWL_num_tbs_LEN 5 | |
1475 | #define IWL_num_tbs_SYM val0 | |
1476 | /* __le32 rsvd2:1; */ | |
1477 | /* __le32 padding:2; */ | |
bb8c093b | 1478 | struct iwl4965_tfd_frame_data pa[10]; |
b481de9c ZY |
1479 | __le32 reserved; |
1480 | } __attribute__ ((packed)); | |
1481 | ||
b481de9c | 1482 | |
5d5456fe BC |
1483 | /** |
1484 | * struct iwl4965_queue_byte_cnt_entry | |
1485 | * | |
1486 | * Byte Count Table Entry | |
1487 | * | |
1488 | * Bit fields: | |
1489 | * 15-12: reserved | |
1490 | * 11- 0: total to-be-transmitted byte count of frame (does not include command) | |
1491 | */ | |
b481de9c ZY |
1492 | struct iwl4965_queue_byte_cnt_entry { |
1493 | __le16 val; | |
1494 | /* __le16 byte_cnt:12; */ | |
1495 | #define IWL_byte_cnt_POS 0 | |
1496 | #define IWL_byte_cnt_LEN 12 | |
1497 | #define IWL_byte_cnt_SYM val | |
1498 | /* __le16 rsvd:4; */ | |
1499 | } __attribute__ ((packed)); | |
1500 | ||
5d5456fe BC |
1501 | |
1502 | /** | |
1503 | * struct iwl4965_sched_queue_byte_cnt_tbl | |
1504 | * | |
1505 | * Byte Count table | |
1506 | * | |
1507 | * Each Tx queue uses a byte-count table containing 320 entries: | |
1508 | * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that | |
1509 | * duplicate the first 64 entries (to avoid wrap-around within a Tx window; | |
1510 | * max Tx window is 64 TFDs). | |
1511 | * | |
1512 | * When driver sets up a new TFD, it must also enter the total byte count | |
1513 | * of the frame to be transmitted into the corresponding entry in the byte | |
1514 | * count table for the chosen Tx queue. If the TFD index is 0-63, the driver | |
1515 | * must duplicate the byte count entry in corresponding index 256-319. | |
1516 | * | |
1517 | * "dont_care" padding puts each byte count table on a 1024-byte boundary; | |
1518 | * 4965 assumes tables are separated by 1024 bytes. | |
1519 | */ | |
b481de9c ZY |
1520 | struct iwl4965_sched_queue_byte_cnt_tbl { |
1521 | struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL4965_QUEUE_SIZE + | |
1522 | IWL4965_MAX_WIN_SIZE]; | |
1523 | u8 dont_care[1024 - | |
1524 | (IWL4965_QUEUE_SIZE + IWL4965_MAX_WIN_SIZE) * | |
1525 | sizeof(__le16)]; | |
1526 | } __attribute__ ((packed)); | |
1527 | ||
5d5456fe BC |
1528 | |
1529 | /** | |
1530 | * struct iwl4965_shared - handshake area for Tx and Rx | |
1531 | * | |
1532 | * For convenience in allocating memory, this structure combines 2 areas of | |
1533 | * DRAM which must be shared between driver and 4965. These do not need to | |
1534 | * be combined, if better allocation would result from keeping them separate: | |
1535 | * | |
1536 | * 1) The Tx byte count tables occupy 1024 bytes each (16 KBytes total for | |
1537 | * 16 queues). Driver uses SCD_DRAM_BASE_ADDR to tell 4965 where to find | |
1538 | * the first of these tables. 4965 assumes tables are 1024 bytes apart. | |
1539 | * | |
1540 | * 2) The Rx status (val0 and val1) occupies only 8 bytes. Driver uses | |
1541 | * FH_RSCSR_CHNL0_STTS_WPTR_REG to tell 4965 where to find this area. | |
1542 | * Driver reads val0 to determine the latest Receive Buffer Descriptor (RBD) | |
1543 | * that has been filled by the 4965. | |
1544 | * | |
1545 | * Bit fields val0: | |
1546 | * 31-12: Not used | |
1547 | * 11- 0: Index of last filled Rx buffer descriptor (4965 writes, driver reads) | |
1548 | * | |
1549 | * Bit fields val1: | |
1550 | * 31- 0: Not used | |
1551 | */ | |
bb8c093b | 1552 | struct iwl4965_shared { |
b481de9c ZY |
1553 | struct iwl4965_sched_queue_byte_cnt_tbl |
1554 | queues_byte_cnt_tbls[IWL_MAX_NUM_QUEUES]; | |
1555 | __le32 val0; | |
1556 | ||
1557 | /* __le32 rb_closed_stts_rb_num:12; */ | |
1558 | #define IWL_rb_closed_stts_rb_num_POS 0 | |
1559 | #define IWL_rb_closed_stts_rb_num_LEN 12 | |
1560 | #define IWL_rb_closed_stts_rb_num_SYM val0 | |
1561 | /* __le32 rsrv1:4; */ | |
1562 | /* __le32 rb_closed_stts_rx_frame_num:12; */ | |
1563 | #define IWL_rb_closed_stts_rx_frame_num_POS 16 | |
1564 | #define IWL_rb_closed_stts_rx_frame_num_LEN 12 | |
1565 | #define IWL_rb_closed_stts_rx_frame_num_SYM val0 | |
1566 | /* __le32 rsrv2:4; */ | |
1567 | ||
1568 | __le32 val1; | |
1569 | /* __le32 frame_finished_stts_rb_num:12; */ | |
1570 | #define IWL_frame_finished_stts_rb_num_POS 0 | |
1571 | #define IWL_frame_finished_stts_rb_num_LEN 12 | |
1572 | #define IWL_frame_finished_stts_rb_num_SYM val1 | |
1573 | /* __le32 rsrv3:4; */ | |
1574 | /* __le32 frame_finished_stts_rx_frame_num:12; */ | |
1575 | #define IWL_frame_finished_stts_rx_frame_num_POS 16 | |
1576 | #define IWL_frame_finished_stts_rx_frame_num_LEN 12 | |
1577 | #define IWL_frame_finished_stts_rx_frame_num_SYM val1 | |
1578 | /* __le32 rsrv4:4; */ | |
1579 | ||
1580 | __le32 padding1; /* so that allocation will be aligned to 16B */ | |
1581 | __le32 padding2; | |
1582 | } __attribute__ ((packed)); | |
1583 | ||
bb8c093b | 1584 | #endif /* __iwl4965_4965_hw_h__ */ |