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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
8 | * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
01ebd063 | 11 | * it under the terms of version 2 of the GNU General Public License as |
b481de9c ZY |
12 | * published by the Free Software Foundation. |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but | |
15 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
22 | * USA | |
23 | * | |
24 | * The full GNU General Public License is included in this distribution | |
25 | * in the file called LICENSE.GPL. | |
26 | * | |
27 | * Contact Information: | |
28 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
29 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
30 | * | |
31 | * BSD LICENSE | |
32 | * | |
33 | * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved. | |
34 | * All rights reserved. | |
35 | * | |
36 | * Redistribution and use in source and binary forms, with or without | |
37 | * modification, are permitted provided that the following conditions | |
38 | * are met: | |
39 | * | |
40 | * * Redistributions of source code must retain the above copyright | |
41 | * notice, this list of conditions and the following disclaimer. | |
42 | * * Redistributions in binary form must reproduce the above copyright | |
43 | * notice, this list of conditions and the following disclaimer in | |
44 | * the documentation and/or other materials provided with the | |
45 | * distribution. | |
46 | * * Neither the name Intel Corporation nor the names of its | |
47 | * contributors may be used to endorse or promote products derived | |
48 | * from this software without specific prior written permission. | |
49 | * | |
50 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
51 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
52 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
53 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
54 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
55 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
56 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
57 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
58 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
59 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
60 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
61 | * | |
62 | *****************************************************************************/ | |
fcd427bb BC |
63 | /* |
64 | * Please use this file (iwl-4965-hw.h) only for hardware-related definitions. | |
65 | * Use iwl-4965-commands.h for uCode API definitions. | |
66 | * Use iwl-4965.h for driver implementation definitions. | |
67 | */ | |
b481de9c ZY |
68 | |
69 | #ifndef __iwl_4965_hw_h__ | |
70 | #define __iwl_4965_hw_h__ | |
71 | ||
1fea8e88 BC |
72 | /* |
73 | * uCode queue management definitions ... | |
74 | * Queue #4 is the command queue for 3945 and 4965; map it to Tx FIFO chnl 4. | |
75 | * The first queue used for block-ack aggregation is #7 (4965 only). | |
76 | * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7. | |
77 | */ | |
5d08cd1d CH |
78 | #define IWL_CMD_QUEUE_NUM 4 |
79 | #define IWL_CMD_FIFO_NUM 4 | |
80 | #define IWL_BACK_QUEUE_FIRST_ID 7 | |
81 | ||
82 | /* Tx rates */ | |
83 | #define IWL_CCK_RATES 4 | |
84 | #define IWL_OFDM_RATES 8 | |
5d08cd1d | 85 | #define IWL_HT_RATES 16 |
5d08cd1d CH |
86 | #define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES) |
87 | ||
88 | /* Time constants */ | |
89 | #define SHORT_SLOT_TIME 9 | |
90 | #define LONG_SLOT_TIME 20 | |
91 | ||
92 | /* RSSI to dBm */ | |
93 | #define IWL_RSSI_OFFSET 44 | |
94 | ||
95 | /* | |
796083cb | 96 | * EEPROM related constants, enums, and structures. |
5d08cd1d CH |
97 | */ |
98 | ||
796083cb BC |
99 | /* |
100 | * EEPROM access time values: | |
101 | * | |
102 | * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG, | |
103 | * then clearing (with subsequent read/modify/write) CSR_EEPROM_REG bit | |
104 | * CSR_EEPROM_REG_BIT_CMD (0x2). | |
105 | * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). | |
106 | * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. | |
107 | * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. | |
108 | */ | |
5d08cd1d CH |
109 | #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ |
110 | #define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */ | |
796083cb | 111 | |
796083cb BC |
112 | /* |
113 | * Regulatory channel usage flags in EEPROM struct iwl4965_eeprom_channel.flags. | |
114 | * | |
115 | * IBSS and/or AP operation is allowed *only* on those channels with | |
116 | * (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because | |
117 | * RADAR detection is not supported by the 4965 driver, but is a | |
118 | * requirement for establishing a new network for legal operation on channels | |
119 | * requiring RADAR detection or restricting ACTIVE scanning. | |
120 | * | |
121 | * NOTE: "WIDE" flag does not indicate anything about "FAT" 40 MHz channels. | |
122 | * It only indicates that 20 MHz channel use is supported; FAT channel | |
123 | * usage is indicated by a separate set of regulatory flags for each | |
124 | * FAT channel pair. | |
125 | * | |
126 | * NOTE: Using a channel inappropriately will result in a uCode error! | |
127 | */ | |
5d08cd1d CH |
128 | enum { |
129 | EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */ | |
796083cb | 130 | EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */ |
5d08cd1d CH |
131 | /* Bit 2 Reserved */ |
132 | EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ | |
133 | EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ | |
796083cb | 134 | EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */ |
2248d8d8 | 135 | EEPROM_CHANNEL_NARROW = (1 << 6), /* 10 MHz channel (not used) */ |
5d08cd1d CH |
136 | EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ |
137 | }; | |
138 | ||
5d08cd1d CH |
139 | /* SKU Capabilities */ |
140 | #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0) | |
141 | #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1) | |
5d08cd1d | 142 | |
796083cb BC |
143 | /* *regulatory* channel data format in eeprom, one for each channel. |
144 | * There are separate entries for FAT (40 MHz) vs. normal (20 MHz) channels. */ | |
bb8c093b | 145 | struct iwl4965_eeprom_channel { |
796083cb | 146 | u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */ |
5d08cd1d CH |
147 | s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */ |
148 | } __attribute__ ((packed)); | |
149 | ||
796083cb | 150 | /* 4965 has two radio transmitters (and 3 radio receivers) */ |
5d08cd1d | 151 | #define EEPROM_TX_POWER_TX_CHAINS (2) |
796083cb BC |
152 | |
153 | /* 4965 has room for up to 8 sets of txpower calibration data */ | |
5d08cd1d | 154 | #define EEPROM_TX_POWER_BANDS (8) |
796083cb BC |
155 | |
156 | /* 4965 factory calibration measures txpower gain settings for | |
157 | * each of 3 target output levels */ | |
5d08cd1d | 158 | #define EEPROM_TX_POWER_MEASUREMENTS (3) |
796083cb | 159 | |
796083cb BC |
160 | /* 4965 driver does not work with txpower calibration version < 5. |
161 | * Look for this in calib_version member of struct iwl4965_eeprom. */ | |
5d08cd1d CH |
162 | #define EEPROM_TX_POWER_VERSION_NEW (5) |
163 | ||
796083cb BC |
164 | |
165 | /* | |
166 | * 4965 factory calibration data for one txpower level, on one channel, | |
167 | * measured on one of the 2 tx chains (radio transmitter and associated | |
168 | * antenna). EEPROM contains: | |
169 | * | |
170 | * 1) Temperature (degrees Celsius) of device when measurement was made. | |
171 | * | |
172 | * 2) Gain table index used to achieve the target measurement power. | |
173 | * This refers to the "well-known" gain tables (see iwl-4965-hw.h). | |
174 | * | |
175 | * 3) Actual measured output power, in half-dBm ("34" = 17 dBm). | |
176 | * | |
177 | * 4) RF power amplifier detector level measurement (not used). | |
178 | */ | |
bb8c093b | 179 | struct iwl4965_eeprom_calib_measure { |
796083cb BC |
180 | u8 temperature; /* Device temperature (Celsius) */ |
181 | u8 gain_idx; /* Index into gain table */ | |
182 | u8 actual_pow; /* Measured RF output power, half-dBm */ | |
183 | s8 pa_det; /* Power amp detector level (not used) */ | |
5d08cd1d CH |
184 | } __attribute__ ((packed)); |
185 | ||
796083cb BC |
186 | |
187 | /* | |
188 | * 4965 measurement set for one channel. EEPROM contains: | |
189 | * | |
190 | * 1) Channel number measured | |
191 | * | |
192 | * 2) Measurements for each of 3 power levels for each of 2 radio transmitters | |
193 | * (a.k.a. "tx chains") (6 measurements altogether) | |
194 | */ | |
bb8c093b | 195 | struct iwl4965_eeprom_calib_ch_info { |
5d08cd1d | 196 | u8 ch_num; |
bb8c093b | 197 | struct iwl4965_eeprom_calib_measure measurements[EEPROM_TX_POWER_TX_CHAINS] |
5d08cd1d CH |
198 | [EEPROM_TX_POWER_MEASUREMENTS]; |
199 | } __attribute__ ((packed)); | |
200 | ||
796083cb BC |
201 | /* |
202 | * 4965 txpower subband info. | |
203 | * | |
204 | * For each frequency subband, EEPROM contains the following: | |
205 | * | |
206 | * 1) First and last channels within range of the subband. "0" values | |
207 | * indicate that this sample set is not being used. | |
208 | * | |
209 | * 2) Sample measurement sets for 2 channels close to the range endpoints. | |
210 | */ | |
bb8c093b | 211 | struct iwl4965_eeprom_calib_subband_info { |
796083cb BC |
212 | u8 ch_from; /* channel number of lowest channel in subband */ |
213 | u8 ch_to; /* channel number of highest channel in subband */ | |
bb8c093b CH |
214 | struct iwl4965_eeprom_calib_ch_info ch1; |
215 | struct iwl4965_eeprom_calib_ch_info ch2; | |
5d08cd1d CH |
216 | } __attribute__ ((packed)); |
217 | ||
796083cb BC |
218 | |
219 | /* | |
220 | * 4965 txpower calibration info. EEPROM contains: | |
221 | * | |
222 | * 1) Factory-measured saturation power levels (maximum levels at which | |
223 | * tx power amplifier can output a signal without too much distortion). | |
224 | * There is one level for 2.4 GHz band and one for 5 GHz band. These | |
225 | * values apply to all channels within each of the bands. | |
226 | * | |
227 | * 2) Factory-measured power supply voltage level. This is assumed to be | |
228 | * constant (i.e. same value applies to all channels/bands) while the | |
229 | * factory measurements are being made. | |
230 | * | |
231 | * 3) Up to 8 sets of factory-measured txpower calibration values. | |
232 | * These are for different frequency ranges, since txpower gain | |
233 | * characteristics of the analog radio circuitry vary with frequency. | |
234 | * | |
235 | * Not all sets need to be filled with data; | |
236 | * struct iwl4965_eeprom_calib_subband_info contains range of channels | |
237 | * (0 if unused) for each set of data. | |
238 | */ | |
bb8c093b | 239 | struct iwl4965_eeprom_calib_info { |
796083cb BC |
240 | u8 saturation_power24; /* half-dBm (e.g. "34" = 17 dBm) */ |
241 | u8 saturation_power52; /* half-dBm */ | |
5d08cd1d | 242 | s16 voltage; /* signed */ |
bb8c093b | 243 | struct iwl4965_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS]; |
5d08cd1d CH |
244 | } __attribute__ ((packed)); |
245 | ||
246 | ||
796083cb BC |
247 | /* |
248 | * 4965 EEPROM map | |
249 | */ | |
bb8c093b | 250 | struct iwl4965_eeprom { |
5d08cd1d CH |
251 | u8 reserved0[16]; |
252 | #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ | |
796083cb | 253 | u16 device_id; /* abs.ofs: 16 */ |
5d08cd1d CH |
254 | u8 reserved1[2]; |
255 | #define EEPROM_PMC (2*0x0A) /* 2 bytes */ | |
256 | u16 pmc; /* abs.ofs: 20 */ | |
257 | u8 reserved2[20]; | |
258 | #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */ | |
259 | u8 mac_address[6]; /* abs.ofs: 42 */ | |
260 | u8 reserved3[58]; | |
261 | #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */ | |
262 | u16 board_revision; /* abs.ofs: 106 */ | |
263 | u8 reserved4[11]; | |
264 | #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */ | |
265 | u8 board_pba_number[9]; /* abs.ofs: 119 */ | |
266 | u8 reserved5[8]; | |
267 | #define EEPROM_VERSION (2*0x44) /* 2 bytes */ | |
268 | u16 version; /* abs.ofs: 136 */ | |
269 | #define EEPROM_SKU_CAP (2*0x45) /* 1 bytes */ | |
270 | u8 sku_cap; /* abs.ofs: 138 */ | |
271 | #define EEPROM_LEDS_MODE (2*0x45+1) /* 1 bytes */ | |
272 | u8 leds_mode; /* abs.ofs: 139 */ | |
273 | #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */ | |
274 | u16 oem_mode; | |
275 | #define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */ | |
276 | u16 wowlan_mode; /* abs.ofs: 142 */ | |
277 | #define EEPROM_LEDS_TIME_INTERVAL (2*0x48) /* 2 bytes */ | |
278 | u16 leds_time_interval; /* abs.ofs: 144 */ | |
279 | #define EEPROM_LEDS_OFF_TIME (2*0x49) /* 1 bytes */ | |
280 | u8 leds_off_time; /* abs.ofs: 146 */ | |
281 | #define EEPROM_LEDS_ON_TIME (2*0x49+1) /* 1 bytes */ | |
282 | u8 leds_on_time; /* abs.ofs: 147 */ | |
283 | #define EEPROM_ALMGOR_M_VERSION (2*0x4A) /* 1 bytes */ | |
284 | u8 almgor_m_version; /* abs.ofs: 148 */ | |
285 | #define EEPROM_ANTENNA_SWITCH_TYPE (2*0x4A+1) /* 1 bytes */ | |
286 | u8 antenna_switch_type; /* abs.ofs: 149 */ | |
287 | u8 reserved6[8]; | |
288 | #define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */ | |
289 | u16 board_revision_4965; /* abs.ofs: 158 */ | |
290 | u8 reserved7[13]; | |
291 | #define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */ | |
292 | u8 board_pba_number_4965[9]; /* abs.ofs: 173 */ | |
293 | u8 reserved8[10]; | |
294 | #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */ | |
295 | u8 sku_id[4]; /* abs.ofs: 192 */ | |
796083cb BC |
296 | |
297 | /* | |
298 | * Per-channel regulatory data. | |
299 | * | |
300 | * Each channel that *might* be supported by 3945 or 4965 has a fixed location | |
301 | * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory | |
302 | * txpower (MSB). | |
303 | * | |
304 | * Entries immediately below are for 20 MHz channel width. FAT (40 MHz) | |
305 | * channels (only for 4965, not supported by 3945) appear later in the EEPROM. | |
306 | * | |
307 | * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 | |
308 | */ | |
5d08cd1d CH |
309 | #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */ |
310 | u16 band_1_count; /* abs.ofs: 196 */ | |
311 | #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */ | |
796083cb BC |
312 | struct iwl4965_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */ |
313 | ||
314 | /* | |
315 | * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196, | |
316 | * 5.0 GHz channels 7, 8, 11, 12, 16 | |
317 | * (4915-5080MHz) (none of these is ever supported) | |
318 | */ | |
5d08cd1d CH |
319 | #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */ |
320 | u16 band_2_count; /* abs.ofs: 226 */ | |
321 | #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */ | |
796083cb BC |
322 | struct iwl4965_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */ |
323 | ||
324 | /* | |
325 | * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 | |
326 | * (5170-5320MHz) | |
327 | */ | |
5d08cd1d CH |
328 | #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */ |
329 | u16 band_3_count; /* abs.ofs: 254 */ | |
330 | #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */ | |
796083cb BC |
331 | struct iwl4965_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */ |
332 | ||
333 | /* | |
334 | * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 | |
335 | * (5500-5700MHz) | |
336 | */ | |
5d08cd1d CH |
337 | #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */ |
338 | u16 band_4_count; /* abs.ofs: 280 */ | |
339 | #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */ | |
796083cb BC |
340 | struct iwl4965_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */ |
341 | ||
342 | /* | |
343 | * 5.7 GHz channels 145, 149, 153, 157, 161, 165 | |
344 | * (5725-5825MHz) | |
345 | */ | |
5d08cd1d CH |
346 | #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */ |
347 | u16 band_5_count; /* abs.ofs: 304 */ | |
348 | #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */ | |
796083cb | 349 | struct iwl4965_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */ |
5d08cd1d CH |
350 | |
351 | u8 reserved10[2]; | |
796083cb BC |
352 | |
353 | ||
354 | /* | |
355 | * 2.4 GHz FAT channels 1 (5), 2 (6), 3 (7), 4 (8), 5 (9), 6 (10), 7 (11) | |
356 | * | |
357 | * The channel listed is the center of the lower 20 MHz half of the channel. | |
358 | * The overall center frequency is actually 2 channels (10 MHz) above that, | |
359 | * and the upper half of each FAT channel is centered 4 channels (20 MHz) away | |
360 | * from the lower half; e.g. the upper half of FAT channel 1 is channel 5, | |
361 | * and the overall FAT channel width centers on channel 3. | |
362 | * | |
363 | * NOTE: The RXON command uses 20 MHz channel numbers to specify the | |
364 | * control channel to which to tune. RXON also specifies whether the | |
365 | * control channel is the upper or lower half of a FAT channel. | |
366 | * | |
367 | * NOTE: 4965 does not support FAT channels on 2.4 GHz. | |
368 | */ | |
5d08cd1d | 369 | #define EEPROM_REGULATORY_BAND_24_FAT_CHANNELS (2*0xA0) /* 14 bytes */ |
796083cb | 370 | struct iwl4965_eeprom_channel band_24_channels[7]; /* abs.ofs: 320 */ |
5d08cd1d | 371 | u8 reserved11[2]; |
796083cb BC |
372 | |
373 | /* | |
374 | * 5.2 GHz FAT channels 36 (40), 44 (48), 52 (56), 60 (64), | |
375 | * 100 (104), 108 (112), 116 (120), 124 (128), 132 (136), 149 (153), 157 (161) | |
376 | */ | |
5d08cd1d | 377 | #define EEPROM_REGULATORY_BAND_52_FAT_CHANNELS (2*0xA8) /* 22 bytes */ |
796083cb | 378 | struct iwl4965_eeprom_channel band_52_channels[11]; /* abs.ofs: 336 */ |
5d08cd1d | 379 | u8 reserved12[6]; |
796083cb BC |
380 | |
381 | /* | |
382 | * 4965 driver requires txpower calibration format version 5 or greater. | |
383 | * Driver does not work with txpower calibration version < 5. | |
384 | * This value is simply a 16-bit number, no major/minor versions here. | |
385 | */ | |
5d08cd1d CH |
386 | #define EEPROM_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */ |
387 | u16 calib_version; /* abs.ofs: 364 */ | |
388 | u8 reserved13[2]; | |
40ac81a3 | 389 | u8 reserved14[96]; /* abs.ofs: 368 */ |
796083cb BC |
390 | |
391 | /* | |
392 | * 4965 Txpower calibration data. | |
393 | */ | |
5d08cd1d | 394 | #define EEPROM_IWL_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */ |
bb8c093b | 395 | struct iwl4965_eeprom_calib_info calib_info; /* abs.ofs: 464 */ |
5d08cd1d CH |
396 | |
397 | u8 reserved16[140]; /* fill out to full 1024 byte block */ | |
398 | ||
399 | ||
400 | } __attribute__ ((packed)); | |
401 | ||
402 | #define IWL_EEPROM_IMAGE_SIZE 1024 | |
403 | ||
796083cb | 404 | /* End of EEPROM */ |
5d08cd1d CH |
405 | |
406 | #include "iwl-4965-commands.h" | |
407 | ||
408 | #define PCI_LINK_CTRL 0x0F0 | |
409 | #define PCI_POWER_SOURCE 0x0C8 | |
410 | #define PCI_REG_WUM8 0x0E8 | |
411 | #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000) | |
412 | ||
413 | /*=== CSR (control and status registers) ===*/ | |
414 | #define CSR_BASE (0x000) | |
415 | ||
416 | #define CSR_SW_VER (CSR_BASE+0x000) | |
417 | #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ | |
418 | #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ | |
419 | #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ | |
420 | #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ | |
421 | #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/ | |
422 | #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ | |
423 | #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ | |
424 | #define CSR_GP_CNTRL (CSR_BASE+0x024) | |
1fea8e88 BC |
425 | |
426 | /* | |
427 | * Hardware revision info | |
428 | * Bit fields: | |
429 | * 31-8: Reserved | |
430 | * 7-4: Type of device: 0x0 = 4965, 0xd = 3945 | |
431 | * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D | |
432 | * 1-0: "Dash" value, as in A-1, etc. | |
433 | * | |
434 | * NOTE: Revision step affects calculation of CCK txpower for 4965. | |
435 | */ | |
5d08cd1d | 436 | #define CSR_HW_REV (CSR_BASE+0x028) |
1fea8e88 BC |
437 | |
438 | /* EEPROM reads */ | |
5d08cd1d CH |
439 | #define CSR_EEPROM_REG (CSR_BASE+0x02c) |
440 | #define CSR_EEPROM_GP (CSR_BASE+0x030) | |
441 | #define CSR_GP_UCODE (CSR_BASE+0x044) | |
442 | #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) | |
443 | #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) | |
444 | #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) | |
445 | #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) | |
5d08cd1d | 446 | #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) |
1fea8e88 BC |
447 | |
448 | /* | |
449 | * Indicates hardware rev, to determine CCK backoff for txpower calculation. | |
450 | * Bit fields: | |
451 | * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step | |
452 | */ | |
5d08cd1d CH |
453 | #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) |
454 | ||
5d08cd1d CH |
455 | /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), |
456 | * acknowledged (reset) by host writing "1" to flagged bits. */ | |
457 | #define CSR_INT_BIT_FH_RX (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */ | |
458 | #define CSR_INT_BIT_HW_ERR (1<<29) /* DMA hardware error FH_INT[31] */ | |
459 | #define CSR_INT_BIT_DNLD (1<<28) /* uCode Download */ | |
460 | #define CSR_INT_BIT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */ | |
461 | #define CSR_INT_BIT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */ | |
462 | #define CSR_INT_BIT_SW_ERR (1<<25) /* uCode error */ | |
463 | #define CSR_INT_BIT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */ | |
464 | #define CSR_INT_BIT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */ | |
465 | #define CSR_INT_BIT_SW_RX (1<<3) /* Rx, command responses, 3945 */ | |
466 | #define CSR_INT_BIT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */ | |
467 | #define CSR_INT_BIT_ALIVE (1<<0) /* uCode interrupts once it initializes */ | |
468 | ||
469 | #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ | |
470 | CSR_INT_BIT_HW_ERR | \ | |
471 | CSR_INT_BIT_FH_TX | \ | |
472 | CSR_INT_BIT_SW_ERR | \ | |
473 | CSR_INT_BIT_RF_KILL | \ | |
474 | CSR_INT_BIT_SW_RX | \ | |
475 | CSR_INT_BIT_WAKEUP | \ | |
476 | CSR_INT_BIT_ALIVE) | |
477 | ||
478 | /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ | |
479 | #define CSR_FH_INT_BIT_ERR (1<<31) /* Error */ | |
480 | #define CSR_FH_INT_BIT_HI_PRIOR (1<<30) /* High priority Rx, bypass coalescing */ | |
5d08cd1d CH |
481 | #define CSR_FH_INT_BIT_RX_CHNL1 (1<<17) /* Rx channel 1 */ |
482 | #define CSR_FH_INT_BIT_RX_CHNL0 (1<<16) /* Rx channel 0 */ | |
5d08cd1d CH |
483 | #define CSR_FH_INT_BIT_TX_CHNL1 (1<<1) /* Tx channel 1 */ |
484 | #define CSR_FH_INT_BIT_TX_CHNL0 (1<<0) /* Tx channel 0 */ | |
485 | ||
486 | #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ | |
5d08cd1d CH |
487 | CSR_FH_INT_BIT_RX_CHNL1 | \ |
488 | CSR_FH_INT_BIT_RX_CHNL0) | |
489 | ||
2248d8d8 | 490 | #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ |
93a3b607 | 491 | CSR_FH_INT_BIT_TX_CHNL0) |
5d08cd1d CH |
492 | |
493 | ||
494 | /* RESET */ | |
495 | #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) | |
496 | #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) | |
497 | #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) | |
498 | #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) | |
499 | #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) | |
500 | ||
501 | /* GP (general purpose) CONTROL */ | |
502 | #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) | |
503 | #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) | |
504 | #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) | |
505 | #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) | |
506 | ||
507 | #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) | |
508 | ||
509 | #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) | |
510 | #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000) | |
511 | #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) | |
512 | ||
513 | ||
514 | /* EEPROM REG */ | |
515 | #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) | |
516 | #define CSR_EEPROM_REG_BIT_CMD (0x00000002) | |
517 | ||
518 | /* EEPROM GP */ | |
519 | #define CSR_EEPROM_GP_VALID_MSK (0x00000006) | |
520 | #define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000) | |
521 | #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) | |
522 | ||
523 | /* UCODE DRV GP */ | |
524 | #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) | |
525 | #define CSR_UCODE_SW_BIT_RFKILL (0x00000002) | |
526 | #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) | |
527 | #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) | |
528 | ||
529 | /* GPIO */ | |
530 | #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) | |
531 | #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) | |
532 | #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER | |
533 | ||
534 | /* GI Chicken Bits */ | |
535 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) | |
536 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) | |
537 | ||
5d08cd1d CH |
538 | /*=== HBUS (Host-side Bus) ===*/ |
539 | #define HBUS_BASE (0x400) | |
540 | ||
1fea8e88 BC |
541 | /* |
542 | * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM | |
543 | * structures, error log, event log, verifying uCode load). | |
544 | * First write to address register, then read from or write to data register | |
545 | * to complete the job. Once the address register is set up, accesses to | |
546 | * data registers auto-increment the address by one dword. | |
547 | * Bit usage for address registers (read or write): | |
548 | * 0-31: memory address within device | |
549 | */ | |
5d08cd1d CH |
550 | #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) |
551 | #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) | |
552 | #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) | |
553 | #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) | |
1fea8e88 BC |
554 | |
555 | /* | |
556 | * Registers for accessing device's internal peripheral registers | |
557 | * (e.g. SCD, BSM, etc.). First write to address register, | |
558 | * then read from or write to data register to complete the job. | |
559 | * Bit usage for address registers (read or write): | |
560 | * 0-15: register address (offset) within device | |
561 | * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) | |
562 | */ | |
5d08cd1d CH |
563 | #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) |
564 | #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) | |
565 | #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) | |
566 | #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) | |
1fea8e88 BC |
567 | |
568 | /* | |
569 | * Per-Tx-queue write pointer (index, really!) (3945 and 4965). | |
483fd7e5 BC |
570 | * Driver sets this to indicate index to next TFD that driver will fill |
571 | * (1 past latest filled). | |
1fea8e88 BC |
572 | * Bit usage: |
573 | * 0-7: queue write index (0-255) | |
574 | * 11-8: queue selector (0-15) | |
575 | */ | |
5d08cd1d CH |
576 | #define HBUS_TARG_WRPTR (HBUS_BASE+0x060) |
577 | ||
578 | #define HBUS_TARG_MBX_C (HBUS_BASE+0x030) | |
579 | ||
5d08cd1d CH |
580 | #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) |
581 | ||
5d08cd1d CH |
582 | #define TFD_QUEUE_SIZE_MAX (256) |
583 | ||
5d08cd1d CH |
584 | #define IWL_NUM_SCAN_RATES (2) |
585 | ||
5d08cd1d | 586 | #define IWL_DEFAULT_TX_RETRY 15 |
5d08cd1d CH |
587 | |
588 | #define RX_QUEUE_SIZE 256 | |
589 | #define RX_QUEUE_MASK 255 | |
590 | #define RX_QUEUE_SIZE_LOG 8 | |
591 | ||
5d08cd1d CH |
592 | #define TFD_TX_CMD_SLOTS 256 |
593 | #define TFD_CMD_SLOTS 32 | |
594 | ||
bb8c093b CH |
595 | #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl4965_cmd) - \ |
596 | sizeof(struct iwl4965_cmd_meta)) | |
5d08cd1d CH |
597 | |
598 | /* | |
599 | * RX related structures and functions | |
600 | */ | |
601 | #define RX_FREE_BUFFERS 64 | |
602 | #define RX_LOW_WATERMARK 8 | |
603 | ||
fcd427bb | 604 | /* Size of one Rx buffer in host DRAM */ |
b481de9c | 605 | #define IWL_RX_BUF_SIZE (4 * 1024) |
fcd427bb BC |
606 | |
607 | /* Sizes and addresses for instruction and data memory (SRAM) in | |
608 | * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */ | |
609 | #define RTC_INST_LOWER_BOUND (0x000000) | |
b481de9c | 610 | #define KDR_RTC_INST_UPPER_BOUND (0x018000) |
fcd427bb BC |
611 | |
612 | #define RTC_DATA_LOWER_BOUND (0x800000) | |
b481de9c | 613 | #define KDR_RTC_DATA_UPPER_BOUND (0x80A000) |
fcd427bb | 614 | |
b481de9c ZY |
615 | #define KDR_RTC_INST_SIZE (KDR_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND) |
616 | #define KDR_RTC_DATA_SIZE (KDR_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND) | |
617 | ||
618 | #define IWL_MAX_INST_SIZE KDR_RTC_INST_SIZE | |
619 | #define IWL_MAX_DATA_SIZE KDR_RTC_DATA_SIZE | |
620 | ||
fcd427bb BC |
621 | /* Size of uCode instruction memory in bootstrap state machine */ |
622 | #define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE | |
623 | ||
bb8c093b | 624 | static inline int iwl4965_hw_valid_rtc_data_addr(u32 addr) |
b481de9c ZY |
625 | { |
626 | return (addr >= RTC_DATA_LOWER_BOUND) && | |
627 | (addr < KDR_RTC_DATA_UPPER_BOUND); | |
628 | } | |
629 | ||
5991b419 | 630 | /********************* START TEMPERATURE *************************************/ |
b481de9c | 631 | |
0c434c5a | 632 | /** |
5991b419 BC |
633 | * 4965 temperature calculation. |
634 | * | |
635 | * The driver must calculate the device temperature before calculating | |
636 | * a txpower setting (amplifier gain is temperature dependent). The | |
637 | * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration | |
638 | * values used for the life of the driver, and one of which (R4) is the | |
639 | * real-time temperature indicator. | |
640 | * | |
641 | * uCode provides all 4 values to the driver via the "initialize alive" | |
642 | * notification (see struct iwl4965_init_alive_resp). After the runtime uCode | |
643 | * image loads, uCode updates the R4 value via statistics notifications | |
644 | * (see STATISTICS_NOTIFICATION), which occur after each received beacon | |
645 | * when associated, or can be requested via REPLY_STATISTICS_CMD. | |
646 | * | |
647 | * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver | |
648 | * must sign-extend to 32 bits before applying formula below. | |
649 | * | |
650 | * Formula: | |
651 | * | |
652 | * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8 | |
653 | * | |
654 | * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is | |
655 | * an additional correction, which should be centered around 0 degrees | |
656 | * Celsius (273 degrees Kelvin). The 8 (3 percent of 273) compensates for | |
657 | * centering the 97/100 correction around 0 degrees K. | |
658 | * | |
659 | * Add 273 to Kelvin value to find degrees Celsius, for comparing current | |
660 | * temperature with factory-measured temperatures when calculating txpower | |
661 | * settings. | |
662 | */ | |
b481de9c ZY |
663 | #define TEMPERATURE_CALIB_KELVIN_OFFSET 8 |
664 | #define TEMPERATURE_CALIB_A_VAL 259 | |
665 | ||
5991b419 | 666 | /* Limit range of calculated temperature to be between these Kelvin values */ |
b481de9c ZY |
667 | #define IWL_TX_POWER_TEMPERATURE_MIN (263) |
668 | #define IWL_TX_POWER_TEMPERATURE_MAX (410) | |
669 | ||
670 | #define IWL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \ | |
671 | (((t) < IWL_TX_POWER_TEMPERATURE_MIN) || \ | |
672 | ((t) > IWL_TX_POWER_TEMPERATURE_MAX)) | |
673 | ||
5991b419 BC |
674 | /********************* END TEMPERATURE ***************************************/ |
675 | ||
676 | /********************* START TXPOWER *****************************************/ | |
677 | ||
0c434c5a BC |
678 | /** |
679 | * 4965 txpower calculations rely on information from three sources: | |
680 | * | |
681 | * 1) EEPROM | |
682 | * 2) "initialize" alive notification | |
683 | * 3) statistics notifications | |
684 | * | |
685 | * EEPROM data consists of: | |
686 | * | |
687 | * 1) Regulatory information (max txpower and channel usage flags) is provided | |
688 | * separately for each channel that can possibly supported by 4965. | |
689 | * 40 MHz wide (.11n fat) channels are listed separately from 20 MHz | |
690 | * (legacy) channels. | |
691 | * | |
692 | * See struct iwl4965_eeprom_channel for format, and struct iwl4965_eeprom | |
693 | * for locations in EEPROM. | |
694 | * | |
695 | * 2) Factory txpower calibration information is provided separately for | |
696 | * sub-bands of contiguous channels. 2.4GHz has just one sub-band, | |
697 | * but 5 GHz has several sub-bands. | |
698 | * | |
699 | * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided. | |
700 | * | |
701 | * See struct iwl4965_eeprom_calib_info (and the tree of structures | |
702 | * contained within it) for format, and struct iwl4965_eeprom for | |
703 | * locations in EEPROM. | |
704 | * | |
705 | * "Initialization alive" notification (see struct iwl4965_init_alive_resp) | |
706 | * consists of: | |
707 | * | |
708 | * 1) Temperature calculation parameters. | |
709 | * | |
710 | * 2) Power supply voltage measurement. | |
711 | * | |
712 | * 3) Tx gain compensation to balance 2 transmitters for MIMO use. | |
713 | * | |
714 | * Statistics notifications deliver: | |
715 | * | |
716 | * 1) Current values for temperature param R4. | |
717 | */ | |
5991b419 | 718 | |
0c434c5a BC |
719 | /** |
720 | * To calculate a txpower setting for a given desired target txpower, channel, | |
721 | * modulation bit rate, and transmitter chain (4965 has 2 transmitters to | |
722 | * support MIMO and transmit diversity), driver must do the following: | |
723 | * | |
724 | * 1) Compare desired txpower vs. (EEPROM) regulatory limit for this channel. | |
725 | * Do not exceed regulatory limit; reduce target txpower if necessary. | |
726 | * | |
727 | * If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31), | |
728 | * 2 transmitters will be used simultaneously; driver must reduce the | |
729 | * regulatory limit by 3 dB (half-power) for each transmitter, so the | |
730 | * combined total output of the 2 transmitters is within regulatory limits. | |
731 | * | |
732 | * | |
733 | * 2) Compare target txpower vs. (EEPROM) saturation txpower *reduced by | |
734 | * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]); | |
735 | * reduce target txpower if necessary. | |
736 | * | |
737 | * Backoff values below are in 1/2 dB units (equivalent to steps in | |
738 | * txpower gain tables): | |
739 | * | |
740 | * OFDM 6 - 36 MBit: 10 steps (5 dB) | |
741 | * OFDM 48 MBit: 15 steps (7.5 dB) | |
742 | * OFDM 54 MBit: 17 steps (8.5 dB) | |
743 | * OFDM 60 MBit: 20 steps (10 dB) | |
744 | * CCK all rates: 10 steps (5 dB) | |
745 | * | |
746 | * Backoff values apply to saturation txpower on a per-transmitter basis; | |
747 | * when using MIMO (2 transmitters), each transmitter uses the same | |
748 | * saturation level provided in EEPROM, and the same backoff values; | |
749 | * no reduction (such as with regulatory txpower limits) is required. | |
750 | * | |
751 | * Saturation and Backoff values apply equally to 20 Mhz (legacy) channel | |
752 | * widths and 40 Mhz (.11n fat) channel widths; there is no separate | |
753 | * factory measurement for fat channels. | |
754 | * | |
755 | * The result of this step is the final target txpower. The rest of | |
756 | * the steps figure out the proper settings for the device to achieve | |
757 | * that target txpower. | |
758 | * | |
759 | * | |
760 | * 3) Determine (EEPROM) calibration subband for the target channel, by | |
761 | * comparing against first and last channels in each subband | |
762 | * (see struct iwl4965_eeprom_calib_subband_info). | |
763 | * | |
764 | * | |
765 | * 4) Linearly interpolate (EEPROM) factory calibration measurement sets, | |
766 | * referencing the 2 factory-measured (sample) channels within the subband. | |
767 | * | |
768 | * Interpolation is based on difference between target channel's frequency | |
769 | * and the sample channels' frequencies. Since channel numbers are based | |
770 | * on frequency (5 MHz between each channel number), this is equivalent | |
771 | * to interpolating based on channel number differences. | |
772 | * | |
773 | * Note that the sample channels may or may not be the channels at the | |
774 | * edges of the subband. The target channel may be "outside" of the | |
775 | * span of the sampled channels. | |
776 | * | |
777 | * Driver may choose the pair (for 2 Tx chains) of measurements (see | |
778 | * struct iwl4965_eeprom_calib_ch_info) for which the actual measured | |
779 | * txpower comes closest to the desired txpower. Usually, though, | |
780 | * the middle set of measurements is closest to the regulatory limits, | |
781 | * and is therefore a good choice for all txpower calculations (this | |
782 | * assumes that high accuracy is needed for maximizing legal txpower, | |
783 | * while lower txpower configurations do not need as much accuracy). | |
784 | * | |
785 | * Driver should interpolate both members of the chosen measurement pair, | |
786 | * i.e. for both Tx chains (radio transmitters), unless the driver knows | |
787 | * that only one of the chains will be used (e.g. only one tx antenna | |
788 | * connected, but this should be unusual). The rate scaling algorithm | |
789 | * switches antennas to find best performance, so both Tx chains will | |
790 | * be used (although only one at a time) even for non-MIMO transmissions. | |
791 | * | |
792 | * Driver should interpolate factory values for temperature, gain table | |
793 | * index, and actual power. The power amplifier detector values are | |
794 | * not used by the driver. | |
795 | * | |
796 | * Sanity check: If the target channel happens to be one of the sample | |
797 | * channels, the results should agree with the sample channel's | |
798 | * measurements! | |
799 | * | |
800 | * | |
801 | * 5) Find difference between desired txpower and (interpolated) | |
802 | * factory-measured txpower. Using (interpolated) factory gain table index | |
803 | * (shown elsewhere) as a starting point, adjust this index lower to | |
804 | * increase txpower, or higher to decrease txpower, until the target | |
805 | * txpower is reached. Each step in the gain table is 1/2 dB. | |
806 | * | |
807 | * For example, if factory measured txpower is 16 dBm, and target txpower | |
808 | * is 13 dBm, add 6 steps to the factory gain index to reduce txpower | |
809 | * by 3 dB. | |
810 | * | |
811 | * | |
812 | * 6) Find difference between current device temperature and (interpolated) | |
813 | * factory-measured temperature for sub-band. Factory values are in | |
814 | * degrees Celsius. To calculate current temperature, see comments for | |
815 | * "4965 temperature calculation". | |
816 | * | |
817 | * If current temperature is higher than factory temperature, driver must | |
818 | * increase gain (lower gain table index), and vice versa. | |
819 | * | |
820 | * Temperature affects gain differently for different channels: | |
821 | * | |
822 | * 2.4 GHz all channels: 3.5 degrees per half-dB step | |
823 | * 5 GHz channels 34-43: 4.5 degrees per half-dB step | |
824 | * 5 GHz channels >= 44: 4.0 degrees per half-dB step | |
825 | * | |
826 | * NOTE: Temperature can increase rapidly when transmitting, especially | |
827 | * with heavy traffic at high txpowers. Driver should update | |
828 | * temperature calculations often under these conditions to | |
829 | * maintain strong txpower in the face of rising temperature. | |
830 | * | |
831 | * | |
832 | * 7) Find difference between current power supply voltage indicator | |
833 | * (from "initialize alive") and factory-measured power supply voltage | |
834 | * indicator (EEPROM). | |
835 | * | |
836 | * If the current voltage is higher (indicator is lower) than factory | |
837 | * voltage, gain should be reduced (gain table index increased) by: | |
838 | * | |
839 | * (eeprom - current) / 7 | |
840 | * | |
841 | * If the current voltage is lower (indicator is higher) than factory | |
842 | * voltage, gain should be increased (gain table index decreased) by: | |
843 | * | |
844 | * 2 * (current - eeprom) / 7 | |
845 | * | |
846 | * If number of index steps in either direction turns out to be > 2, | |
847 | * something is wrong ... just use 0. | |
848 | * | |
849 | * NOTE: Voltage compensation is independent of band/channel. | |
850 | * | |
851 | * NOTE: "Initialize" uCode measures current voltage, which is assumed | |
852 | * to be constant after this initial measurement. Voltage | |
853 | * compensation for txpower (number of steps in gain table) | |
854 | * may be calculated once and used until the next uCode bootload. | |
855 | * | |
856 | * | |
857 | * 8) If setting up txpowers for MIMO rates (rate indexes 8-15, 24-31), | |
858 | * adjust txpower for each transmitter chain, so txpower is balanced | |
859 | * between the two chains. There are 5 pairs of tx_atten[group][chain] | |
860 | * values in "initialize alive", one pair for each of 5 channel ranges: | |
861 | * | |
862 | * Group 0: 5 GHz channel 34-43 | |
863 | * Group 1: 5 GHz channel 44-70 | |
864 | * Group 2: 5 GHz channel 71-124 | |
865 | * Group 3: 5 GHz channel 125-200 | |
866 | * Group 4: 2.4 GHz all channels | |
867 | * | |
868 | * Add the tx_atten[group][chain] value to the index for the target chain. | |
869 | * The values are signed, but are in pairs of 0 and a non-negative number, | |
870 | * so as to reduce gain (if necessary) of the "hotter" channel. This | |
871 | * avoids any need to double-check for regulatory compliance after | |
872 | * this step. | |
873 | * | |
874 | * | |
875 | * 9) If setting up for a CCK rate, lower the gain by adding a CCK compensation | |
876 | * value to the index: | |
877 | * | |
878 | * Hardware rev B: 9 steps (4.5 dB) | |
879 | * Hardware rev C: 5 steps (2.5 dB) | |
880 | * | |
881 | * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG, | |
882 | * bits [3:2], 1 = B, 2 = C. | |
883 | * | |
884 | * NOTE: This compensation is in addition to any saturation backoff that | |
885 | * might have been applied in an earlier step. | |
886 | * | |
887 | * | |
888 | * 10) Select the gain table, based on band (2.4 vs 5 GHz). | |
889 | * | |
890 | * Limit the adjusted index to stay within the table! | |
891 | * | |
892 | * | |
893 | * 11) Read gain table entries for DSP and radio gain, place into appropriate | |
894 | * location(s) in command (struct iwl4965_txpowertable_cmd). | |
895 | */ | |
b481de9c | 896 | |
0c434c5a | 897 | /* Limit range of txpower output target to be between these values */ |
b481de9c ZY |
898 | #define IWL_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm = 1 milliwatt */ |
899 | #define IWL_TX_POWER_TARGET_POWER_MAX (16) /* 16 dBm */ | |
900 | ||
0c434c5a BC |
901 | /** |
902 | * When MIMO is used (2 transmitters operating simultaneously), driver should | |
903 | * limit each transmitter to deliver a max of 3 dB below the regulatory limit | |
904 | * for the device. That is, use half power for each transmitter, so total | |
905 | * txpower is within regulatory limits. | |
906 | * | |
907 | * The value "6" represents number of steps in gain table to reduce power 3 dB. | |
908 | * Each step is 1/2 dB. | |
909 | */ | |
910 | #define IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6) | |
911 | ||
912 | /** | |
913 | * CCK gain compensation. | |
914 | * | |
915 | * When calculating txpowers for CCK, after making sure that the target power | |
916 | * is within regulatory and saturation limits, driver must additionally | |
917 | * back off gain by adding these values to the gain table index. | |
918 | * | |
919 | * Hardware rev for 4965 can be determined by reading CSR_HW_REV_WA_REG, | |
920 | * bits [3:2], 1 = B, 2 = C. | |
921 | */ | |
922 | #define IWL_TX_POWER_CCK_COMPENSATION_B_STEP (9) | |
923 | #define IWL_TX_POWER_CCK_COMPENSATION_C_STEP (5) | |
924 | ||
925 | /* | |
926 | * 4965 power supply voltage compensation for txpower | |
927 | */ | |
928 | #define TX_POWER_IWL_VOLTAGE_CODES_PER_03V (7) | |
929 | ||
930 | /** | |
931 | * Gain tables. | |
932 | * | |
933 | * The following tables contain pair of values for setting txpower, i.e. | |
934 | * gain settings for the output of the device's digital signal processor (DSP), | |
935 | * and for the analog gain structure of the transmitter. | |
936 | * | |
937 | * Each entry in the gain tables represents a step of 1/2 dB. Note that these | |
938 | * are *relative* steps, not indications of absolute output power. Output | |
939 | * power varies with temperature, voltage, and channel frequency, and also | |
940 | * requires consideration of average power (to satisfy regulatory constraints), | |
941 | * and peak power (to avoid distortion of the output signal). | |
942 | * | |
943 | * Each entry contains two values: | |
944 | * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained | |
945 | * linear value that multiplies the output of the digital signal processor, | |
946 | * before being sent to the analog radio. | |
947 | * 2) Radio gain. This sets the analog gain of the radio Tx path. | |
948 | * It is a coarser setting, and behaves in a logarithmic (dB) fashion. | |
949 | * | |
950 | * EEPROM contains factory calibration data for txpower. This maps actual | |
951 | * measured txpower levels to gain settings in the "well known" tables | |
952 | * below ("well-known" means here that both factory calibration *and* the | |
953 | * driver work with the same table). | |
954 | * | |
955 | * There are separate tables for 2.4 GHz and 5 GHz bands. The 5 GHz table | |
956 | * has an extension (into negative indexes), in case the driver needs to | |
957 | * boost power setting for high device temperatures (higher than would be | |
958 | * present during factory calibration). A 5 Ghz EEPROM index of "40" | |
959 | * corresponds to the 49th entry in the table used by the driver. | |
960 | */ | |
961 | #define MIN_TX_GAIN_INDEX (0) /* highest gain, lowest idx, 2.4 */ | |
962 | #define MIN_TX_GAIN_INDEX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */ | |
963 | ||
964 | /** | |
965 | * 2.4 GHz gain table | |
966 | * | |
967 | * Index Dsp gain Radio gain | |
968 | * 0 110 0x3f (highest gain) | |
969 | * 1 104 0x3f | |
970 | * 2 98 0x3f | |
971 | * 3 110 0x3e | |
972 | * 4 104 0x3e | |
973 | * 5 98 0x3e | |
974 | * 6 110 0x3d | |
975 | * 7 104 0x3d | |
976 | * 8 98 0x3d | |
977 | * 9 110 0x3c | |
978 | * 10 104 0x3c | |
979 | * 11 98 0x3c | |
980 | * 12 110 0x3b | |
981 | * 13 104 0x3b | |
982 | * 14 98 0x3b | |
983 | * 15 110 0x3a | |
984 | * 16 104 0x3a | |
985 | * 17 98 0x3a | |
986 | * 18 110 0x39 | |
987 | * 19 104 0x39 | |
988 | * 20 98 0x39 | |
989 | * 21 110 0x38 | |
990 | * 22 104 0x38 | |
991 | * 23 98 0x38 | |
992 | * 24 110 0x37 | |
993 | * 25 104 0x37 | |
994 | * 26 98 0x37 | |
995 | * 27 110 0x36 | |
996 | * 28 104 0x36 | |
997 | * 29 98 0x36 | |
998 | * 30 110 0x35 | |
999 | * 31 104 0x35 | |
1000 | * 32 98 0x35 | |
1001 | * 33 110 0x34 | |
1002 | * 34 104 0x34 | |
1003 | * 35 98 0x34 | |
1004 | * 36 110 0x33 | |
1005 | * 37 104 0x33 | |
1006 | * 38 98 0x33 | |
1007 | * 39 110 0x32 | |
1008 | * 40 104 0x32 | |
1009 | * 41 98 0x32 | |
1010 | * 42 110 0x31 | |
1011 | * 43 104 0x31 | |
1012 | * 44 98 0x31 | |
1013 | * 45 110 0x30 | |
1014 | * 46 104 0x30 | |
1015 | * 47 98 0x30 | |
1016 | * 48 110 0x6 | |
1017 | * 49 104 0x6 | |
1018 | * 50 98 0x6 | |
1019 | * 51 110 0x5 | |
1020 | * 52 104 0x5 | |
1021 | * 53 98 0x5 | |
1022 | * 54 110 0x4 | |
1023 | * 55 104 0x4 | |
1024 | * 56 98 0x4 | |
1025 | * 57 110 0x3 | |
1026 | * 58 104 0x3 | |
1027 | * 59 98 0x3 | |
1028 | * 60 110 0x2 | |
1029 | * 61 104 0x2 | |
1030 | * 62 98 0x2 | |
1031 | * 63 110 0x1 | |
1032 | * 64 104 0x1 | |
1033 | * 65 98 0x1 | |
1034 | * 66 110 0x0 | |
1035 | * 67 104 0x0 | |
1036 | * 68 98 0x0 | |
1037 | * 69 97 0 | |
1038 | * 70 96 0 | |
1039 | * 71 95 0 | |
1040 | * 72 94 0 | |
1041 | * 73 93 0 | |
1042 | * 74 92 0 | |
1043 | * 75 91 0 | |
1044 | * 76 90 0 | |
1045 | * 77 89 0 | |
1046 | * 78 88 0 | |
1047 | * 79 87 0 | |
1048 | * 80 86 0 | |
1049 | * 81 85 0 | |
1050 | * 82 84 0 | |
1051 | * 83 83 0 | |
1052 | * 84 82 0 | |
1053 | * 85 81 0 | |
1054 | * 86 80 0 | |
1055 | * 87 79 0 | |
1056 | * 88 78 0 | |
1057 | * 89 77 0 | |
1058 | * 90 76 0 | |
1059 | * 91 75 0 | |
1060 | * 92 74 0 | |
1061 | * 93 73 0 | |
1062 | * 94 72 0 | |
1063 | * 95 71 0 | |
1064 | * 96 70 0 | |
1065 | * 97 69 0 | |
1066 | * 98 68 0 | |
1067 | */ | |
1068 | ||
1069 | /** | |
1070 | * 5 GHz gain table | |
1071 | * | |
1072 | * Index Dsp gain Radio gain | |
1073 | * -9 123 0x3F (highest gain) | |
1074 | * -8 117 0x3F | |
1075 | * -7 110 0x3F | |
1076 | * -6 104 0x3F | |
1077 | * -5 98 0x3F | |
1078 | * -4 110 0x3E | |
1079 | * -3 104 0x3E | |
1080 | * -2 98 0x3E | |
1081 | * -1 110 0x3D | |
1082 | * 0 104 0x3D | |
1083 | * 1 98 0x3D | |
1084 | * 2 110 0x3C | |
1085 | * 3 104 0x3C | |
1086 | * 4 98 0x3C | |
1087 | * 5 110 0x3B | |
1088 | * 6 104 0x3B | |
1089 | * 7 98 0x3B | |
1090 | * 8 110 0x3A | |
1091 | * 9 104 0x3A | |
1092 | * 10 98 0x3A | |
1093 | * 11 110 0x39 | |
1094 | * 12 104 0x39 | |
1095 | * 13 98 0x39 | |
1096 | * 14 110 0x38 | |
1097 | * 15 104 0x38 | |
1098 | * 16 98 0x38 | |
1099 | * 17 110 0x37 | |
1100 | * 18 104 0x37 | |
1101 | * 19 98 0x37 | |
1102 | * 20 110 0x36 | |
1103 | * 21 104 0x36 | |
1104 | * 22 98 0x36 | |
1105 | * 23 110 0x35 | |
1106 | * 24 104 0x35 | |
1107 | * 25 98 0x35 | |
1108 | * 26 110 0x34 | |
1109 | * 27 104 0x34 | |
1110 | * 28 98 0x34 | |
1111 | * 29 110 0x33 | |
1112 | * 30 104 0x33 | |
1113 | * 31 98 0x33 | |
1114 | * 32 110 0x32 | |
1115 | * 33 104 0x32 | |
1116 | * 34 98 0x32 | |
1117 | * 35 110 0x31 | |
1118 | * 36 104 0x31 | |
1119 | * 37 98 0x31 | |
1120 | * 38 110 0x30 | |
1121 | * 39 104 0x30 | |
1122 | * 40 98 0x30 | |
1123 | * 41 110 0x25 | |
1124 | * 42 104 0x25 | |
1125 | * 43 98 0x25 | |
1126 | * 44 110 0x24 | |
1127 | * 45 104 0x24 | |
1128 | * 46 98 0x24 | |
1129 | * 47 110 0x23 | |
1130 | * 48 104 0x23 | |
1131 | * 49 98 0x23 | |
1132 | * 50 110 0x22 | |
1133 | * 51 104 0x18 | |
1134 | * 52 98 0x18 | |
1135 | * 53 110 0x17 | |
1136 | * 54 104 0x17 | |
1137 | * 55 98 0x17 | |
1138 | * 56 110 0x16 | |
1139 | * 57 104 0x16 | |
1140 | * 58 98 0x16 | |
1141 | * 59 110 0x15 | |
1142 | * 60 104 0x15 | |
1143 | * 61 98 0x15 | |
1144 | * 62 110 0x14 | |
1145 | * 63 104 0x14 | |
1146 | * 64 98 0x14 | |
1147 | * 65 110 0x13 | |
1148 | * 66 104 0x13 | |
1149 | * 67 98 0x13 | |
1150 | * 68 110 0x12 | |
1151 | * 69 104 0x08 | |
1152 | * 70 98 0x08 | |
1153 | * 71 110 0x07 | |
1154 | * 72 104 0x07 | |
1155 | * 73 98 0x07 | |
1156 | * 74 110 0x06 | |
1157 | * 75 104 0x06 | |
1158 | * 76 98 0x06 | |
1159 | * 77 110 0x05 | |
1160 | * 78 104 0x05 | |
1161 | * 79 98 0x05 | |
1162 | * 80 110 0x04 | |
1163 | * 81 104 0x04 | |
1164 | * 82 98 0x04 | |
1165 | * 83 110 0x03 | |
1166 | * 84 104 0x03 | |
1167 | * 85 98 0x03 | |
1168 | * 86 110 0x02 | |
1169 | * 87 104 0x02 | |
1170 | * 88 98 0x02 | |
1171 | * 89 110 0x01 | |
1172 | * 90 104 0x01 | |
1173 | * 91 98 0x01 | |
1174 | * 92 110 0x00 | |
1175 | * 93 104 0x00 | |
1176 | * 94 98 0x00 | |
1177 | * 95 93 0x00 | |
1178 | * 96 88 0x00 | |
1179 | * 97 83 0x00 | |
1180 | * 98 78 0x00 | |
1181 | */ | |
b481de9c | 1182 | |
0c434c5a BC |
1183 | |
1184 | /** | |
1185 | * Sanity checks and default values for EEPROM regulatory levels. | |
1186 | * If EEPROM values fall outside MIN/MAX range, use default values. | |
1187 | * | |
1188 | * Regulatory limits refer to the maximum average txpower allowed by | |
1189 | * regulatory agencies in the geographies in which the device is meant | |
1190 | * to be operated. These limits are SKU-specific (i.e. geography-specific), | |
1191 | * and channel-specific; each channel has an individual regulatory limit | |
1192 | * listed in the EEPROM. | |
1193 | * | |
1194 | * Units are in half-dBm (i.e. "34" means 17 dBm). | |
1195 | */ | |
b481de9c ZY |
1196 | #define IWL_TX_POWER_DEFAULT_REGULATORY_24 (34) |
1197 | #define IWL_TX_POWER_DEFAULT_REGULATORY_52 (34) | |
1198 | #define IWL_TX_POWER_REGULATORY_MIN (0) | |
1199 | #define IWL_TX_POWER_REGULATORY_MAX (34) | |
0c434c5a BC |
1200 | |
1201 | /** | |
1202 | * Sanity checks and default values for EEPROM saturation levels. | |
1203 | * If EEPROM values fall outside MIN/MAX range, use default values. | |
1204 | * | |
1205 | * Saturation is the highest level that the output power amplifier can produce | |
1206 | * without significant clipping distortion. This is a "peak" power level. | |
1207 | * Different types of modulation (i.e. various "rates", and OFDM vs. CCK) | |
1208 | * require differing amounts of backoff, relative to their average power output, | |
1209 | * in order to avoid clipping distortion. | |
1210 | * | |
1211 | * Driver must make sure that it is violating neither the saturation limit, | |
1212 | * nor the regulatory limit, when calculating Tx power settings for various | |
1213 | * rates. | |
1214 | * | |
1215 | * Units are in half-dBm (i.e. "38" means 19 dBm). | |
1216 | */ | |
b481de9c ZY |
1217 | #define IWL_TX_POWER_DEFAULT_SATURATION_24 (38) |
1218 | #define IWL_TX_POWER_DEFAULT_SATURATION_52 (38) | |
1219 | #define IWL_TX_POWER_SATURATION_MIN (20) | |
1220 | #define IWL_TX_POWER_SATURATION_MAX (50) | |
1221 | ||
0c434c5a BC |
1222 | /** |
1223 | * Channel groups used for Tx Attenuation calibration (MIMO tx channel balance) | |
1224 | * and thermal Txpower calibration. | |
1225 | * | |
1226 | * When calculating txpower, driver must compensate for current device | |
1227 | * temperature; higher temperature requires higher gain. Driver must calculate | |
1228 | * current temperature (see "4965 temperature calculation"), then compare vs. | |
1229 | * factory calibration temperature in EEPROM; if current temperature is higher | |
1230 | * than factory temperature, driver must *increase* gain by proportions shown | |
1231 | * in table below. If current temperature is lower than factory, driver must | |
1232 | * *decrease* gain. | |
1233 | * | |
1234 | * Different frequency ranges require different compensation, as shown below. | |
1235 | */ | |
1236 | /* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */ | |
b481de9c ZY |
1237 | #define CALIB_IWL_TX_ATTEN_GR1_FCH 34 |
1238 | #define CALIB_IWL_TX_ATTEN_GR1_LCH 43 | |
0c434c5a BC |
1239 | |
1240 | /* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */ | |
b481de9c ZY |
1241 | #define CALIB_IWL_TX_ATTEN_GR2_FCH 44 |
1242 | #define CALIB_IWL_TX_ATTEN_GR2_LCH 70 | |
0c434c5a BC |
1243 | |
1244 | /* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */ | |
b481de9c ZY |
1245 | #define CALIB_IWL_TX_ATTEN_GR3_FCH 71 |
1246 | #define CALIB_IWL_TX_ATTEN_GR3_LCH 124 | |
0c434c5a BC |
1247 | |
1248 | /* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */ | |
b481de9c ZY |
1249 | #define CALIB_IWL_TX_ATTEN_GR4_FCH 125 |
1250 | #define CALIB_IWL_TX_ATTEN_GR4_LCH 200 | |
0c434c5a BC |
1251 | |
1252 | /* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */ | |
b481de9c ZY |
1253 | #define CALIB_IWL_TX_ATTEN_GR5_FCH 1 |
1254 | #define CALIB_IWL_TX_ATTEN_GR5_LCH 20 | |
1255 | ||
0c434c5a BC |
1256 | enum { |
1257 | CALIB_CH_GROUP_1 = 0, | |
1258 | CALIB_CH_GROUP_2 = 1, | |
1259 | CALIB_CH_GROUP_3 = 2, | |
1260 | CALIB_CH_GROUP_4 = 3, | |
1261 | CALIB_CH_GROUP_5 = 4, | |
1262 | CALIB_CH_GROUP_MAX | |
1263 | }; | |
1264 | ||
b481de9c ZY |
1265 | /********************* END TXPOWER *****************************************/ |
1266 | ||
aad14143 | 1267 | /****************************/ |
b481de9c | 1268 | /* Flow Handler Definitions */ |
aad14143 | 1269 | /****************************/ |
b481de9c | 1270 | |
4d3cf5f7 | 1271 | /** |
aad14143 BC |
1272 | * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) |
1273 | * Addresses are offsets from device's PCI hardware base address. | |
1274 | */ | |
b481de9c ZY |
1275 | #define FH_MEM_LOWER_BOUND (0x1000) |
1276 | #define FH_MEM_UPPER_BOUND (0x1EF0) | |
1277 | ||
aad14143 BC |
1278 | /** |
1279 | * Keep-Warm (KW) buffer base address. | |
1280 | * | |
1281 | * Driver must allocate a 4KByte buffer that is used by 4965 for keeping the | |
1282 | * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency | |
1283 | * DRAM access when 4965 is Txing or Rxing. The dummy accesses prevent host | |
1284 | * from going into a power-savings mode that would cause higher DRAM latency, | |
1285 | * and possible data over/under-runs, before all Tx/Rx is complete. | |
1286 | * | |
1287 | * Driver loads IWL_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) | |
1288 | * of the buffer, which must be 4K aligned. Once this is set up, the 4965 | |
1289 | * automatically invokes keep-warm accesses when normal accesses might not | |
1290 | * be sufficient to maintain fast DRAM response. | |
1291 | * | |
1292 | * Bit fields: | |
1293 | * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned | |
1294 | */ | |
b481de9c ZY |
1295 | #define IWL_FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) |
1296 | ||
aad14143 | 1297 | |
4d3cf5f7 BC |
1298 | /** |
1299 | * TFD Circular Buffers Base (CBBC) addresses | |
1300 | * | |
1301 | * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident | |
1302 | * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) | |
1303 | * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04 | |
1304 | * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte | |
1305 | * aligned (address bits 0-7 must be 0). | |
1306 | * | |
1307 | * Bit fields in each pointer register: | |
1308 | * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned | |
1309 | */ | |
b481de9c ZY |
1310 | #define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) |
1311 | #define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) | |
4d3cf5f7 BC |
1312 | |
1313 | /* Find TFD CB base pointer for given queue (range 0-15). */ | |
b481de9c ZY |
1314 | #define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4) |
1315 | ||
4d3cf5f7 BC |
1316 | |
1317 | /** | |
1318 | * Rx SRAM Control and Status Registers (RSCSR) | |
1319 | * | |
1320 | * These registers provide handshake between driver and 4965 for the Rx queue | |
1321 | * (this queue handles *all* command responses, notifications, Rx data, etc. | |
1322 | * sent from 4965 uCode to host driver). Unlike Tx, there is only one Rx | |
1323 | * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can | |
1324 | * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer | |
1325 | * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 | |
1326 | * mapping between RBDs and RBs. | |
1327 | * | |
1328 | * Driver must allocate host DRAM memory for the following, and set the | |
1329 | * physical address of each into 4965 registers: | |
1330 | * | |
1331 | * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 | |
1332 | * entries (although any power of 2, up to 4096, is selectable by driver). | |
1333 | * Each entry (1 dword) points to a receive buffer (RB) of consistent size | |
1334 | * (typically 4K, although 8K or 16K are also selectable by driver). | |
1335 | * Driver sets up RB size and number of RBDs in the CB via Rx config | |
1336 | * register FH_MEM_RCSR_CHNL0_CONFIG_REG. | |
1337 | * | |
1338 | * Bit fields within one RBD: | |
1339 | * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned | |
1340 | * | |
1341 | * Driver sets physical address [35:8] of base of RBD circular buffer | |
1342 | * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. | |
1343 | * | |
1344 | * 2) Rx status buffer, 8 bytes, in which 4965 indicates which Rx Buffers | |
1345 | * (RBs) have been filled, via a "write pointer", actually the index of | |
1346 | * the RB's corresponding RBD within the circular buffer. Driver sets | |
1347 | * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. | |
1348 | * | |
1349 | * Bit fields in lower dword of Rx status buffer (upper dword not used | |
1350 | * by driver; see struct iwl4965_shared, val0): | |
1351 | * 31-12: Not used by driver | |
1352 | * 11- 0: Index of last filled Rx buffer descriptor | |
1353 | * (4965 writes, driver reads this value) | |
1354 | * | |
1355 | * As the driver prepares Receive Buffers (RBs) for 4965 to fill, driver must | |
1356 | * enter pointers to these RBs into contiguous RBD circular buffer entries, | |
1357 | * and update the 4965's "write" index register, FH_RSCSR_CHNL0_RBDCB_WPTR_REG. | |
1358 | * | |
1359 | * This "write" index corresponds to the *next* RBD that the driver will make | |
1360 | * available, i.e. one RBD past the tail of the ready-to-fill RBDs within | |
1361 | * the circular buffer. This value should initially be 0 (before preparing any | |
1362 | * RBs), should be 8 after preparing the first 8 RBs (for example), and must | |
1363 | * wrap back to 0 at the end of the circular buffer (but don't wrap before | |
1364 | * "read" index has advanced past 1! See below). | |
1365 | * NOTE: 4965 EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. | |
1366 | * | |
1367 | * As the 4965 fills RBs (referenced from contiguous RBDs within the circular | |
1368 | * buffer), it updates the Rx status buffer in host DRAM, 2) described above, | |
1369 | * to tell the driver the index of the latest filled RBD. The driver must | |
1370 | * read this "read" index from DRAM after receiving an Rx interrupt from 4965. | |
1371 | * | |
1372 | * The driver must also internally keep track of a third index, which is the | |
1373 | * next RBD to process. When receiving an Rx interrupt, driver should process | |
1374 | * all filled but unprocessed RBs up to, but not including, the RB | |
1375 | * corresponding to the "read" index. For example, if "read" index becomes "1", | |
1376 | * driver may process the RB pointed to by RBD 0. Depending on volume of | |
1377 | * traffic, there may be many RBs to process. | |
1378 | * | |
1379 | * If read index == write index, 4965 thinks there is no room to put new data. | |
1380 | * Due to this, the maximum number of filled RBs is 255, instead of 256. To | |
1381 | * be safe, make sure that there is a gap of at least 2 RBDs between "write" | |
1382 | * and "read" indexes; that is, make sure that there are no more than 254 | |
1383 | * buffers waiting to be filled. | |
1384 | */ | |
b481de9c ZY |
1385 | #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) |
1386 | #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) | |
1387 | #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) | |
1388 | ||
4d3cf5f7 BC |
1389 | /** |
1390 | * Physical base address of 8-byte Rx Status buffer. | |
1391 | * Bit fields: | |
1392 | * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. | |
1393 | */ | |
b481de9c | 1394 | #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) |
4d3cf5f7 BC |
1395 | |
1396 | /** | |
1397 | * Physical base address of Rx Buffer Descriptor Circular Buffer. | |
1398 | * Bit fields: | |
1399 | * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. | |
1400 | */ | |
b481de9c | 1401 | #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) |
4d3cf5f7 BC |
1402 | |
1403 | /** | |
1404 | * Rx write pointer (index, really!). | |
1405 | * Bit fields: | |
1406 | * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. | |
1407 | * NOTE: For 256-entry circular buffer, use only bits [7:0]. | |
1408 | */ | |
b481de9c | 1409 | #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) |
483fd7e5 | 1410 | #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG) |
b481de9c | 1411 | |
4d3cf5f7 BC |
1412 | |
1413 | /** | |
1414 | * Rx Config/Status Registers (RCSR) | |
1415 | * Rx Config Reg for channel 0 (only channel used) | |
1416 | * | |
1417 | * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for | |
1418 | * normal operation (see bit fields). | |
1419 | * | |
1420 | * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. | |
1421 | * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for | |
1422 | * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. | |
1423 | * | |
1424 | * Bit fields: | |
1425 | * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, | |
1426 | * '10' operate normally | |
1427 | * 29-24: reserved | |
1428 | * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), | |
1429 | * min "5" for 32 RBDs, max "12" for 4096 RBDs. | |
1430 | * 19-18: reserved | |
1431 | * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, | |
1432 | * '10' 12K, '11' 16K. | |
1433 | * 15-14: reserved | |
1434 | * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) | |
1435 | * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) | |
1436 | * typical value 0x10 (about 1/2 msec) | |
1437 | * 3- 0: reserved | |
1438 | */ | |
b481de9c ZY |
1439 | #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) |
1440 | #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) | |
1441 | #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) | |
1442 | ||
1443 | #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) | |
1444 | ||
4d3cf5f7 BC |
1445 | #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MASK (0x00000FF0) /* bit 4-11 */ |
1446 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MASK (0x00001000) /* bit 12 */ | |
1447 | #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MASK (0x00008000) /* bit 15 */ | |
1448 | #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MASK (0x00030000) /* bits 16-17 */ | |
1449 | #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MASK (0x00F00000) /* bits 20-23 */ | |
1450 | #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */ | |
1451 | ||
1452 | #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20) | |
1453 | #define FH_RCSR_RX_CONFIG_RB_SIZE_BITSHIFT (16) | |
1454 | ||
1455 | #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) | |
1456 | #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) | |
1457 | #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) | |
1458 | ||
1459 | #define IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) | |
1460 | ||
1461 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) | |
1462 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) | |
1463 | ||
1464 | ||
1465 | /** | |
1466 | * Rx Shared Status Registers (RSSR) | |
1467 | * | |
1468 | * After stopping Rx DMA channel (writing 0 to FH_MEM_RCSR_CHNL0_CONFIG_REG), | |
1469 | * driver must poll FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. | |
1470 | * | |
1471 | * Bit fields: | |
1472 | * 24: 1 = Channel 0 is idle | |
1473 | * | |
1474 | * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV contain | |
1475 | * default values that should not be altered by the driver. | |
1476 | */ | |
b481de9c ZY |
1477 | #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) |
1478 | #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) | |
4d3cf5f7 | 1479 | |
b481de9c ZY |
1480 | #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) |
1481 | #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) | |
1482 | #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008) | |
1483 | ||
4d3cf5f7 BC |
1484 | #define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) |
1485 | ||
483fd7e5 BC |
1486 | |
1487 | /** | |
1488 | * Transmit DMA Channel Control/Status Registers (TCSR) | |
1489 | * | |
1490 | * 4965 has one configuration register for each of 8 Tx DMA/FIFO channels | |
1491 | * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, | |
1492 | * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. | |
1493 | * | |
1494 | * To use a Tx DMA channel, driver must initialize its | |
1495 | * IWL_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: | |
1496 | * | |
1497 | * IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
1498 | * IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | |
1499 | * | |
1500 | * All other bits should be 0. | |
1501 | * | |
1502 | * Bit fields: | |
1503 | * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, | |
1504 | * '10' operate normally | |
1505 | * 29- 4: Reserved, set to "0" | |
1506 | * 3: Enable internal DMA requests (1, normal operation), disable (0) | |
1507 | * 2- 0: Reserved, set to "0" | |
1508 | */ | |
aad14143 BC |
1509 | #define IWL_FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) |
1510 | #define IWL_FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60) | |
b481de9c | 1511 | |
483fd7e5 | 1512 | /* Find Control/Status reg for given Tx DMA/FIFO channel */ |
b481de9c ZY |
1513 | #define IWL_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ |
1514 | (IWL_FH_TCSR_LOWER_BOUND + 0x20 * _chnl) | |
1515 | ||
483fd7e5 BC |
1516 | #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000) |
1517 | #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008) | |
1518 | ||
1519 | #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) | |
1520 | #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) | |
1521 | #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) | |
1522 | ||
1523 | /** | |
1524 | * Tx Shared Status Registers (TSSR) | |
1525 | * | |
1526 | * After stopping Tx DMA channel (writing 0 to | |
1527 | * IWL_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll | |
1528 | * IWL_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle | |
1529 | * (channel's buffers empty | no pending requests). | |
1530 | * | |
1531 | * Bit fields: | |
1532 | * 31-24: 1 = Channel buffers empty (channel 7:0) | |
1533 | * 23-16: 1 = No pending requests (channel 7:0) | |
1534 | */ | |
aad14143 BC |
1535 | #define IWL_FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0) |
1536 | #define IWL_FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0) | |
b481de9c | 1537 | |
b481de9c ZY |
1538 | #define IWL_FH_TSSR_TX_STATUS_REG (IWL_FH_TSSR_LOWER_BOUND + 0x010) |
1539 | ||
b481de9c ZY |
1540 | #define IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \ |
1541 | ((1 << (_chnl)) << 24) | |
1542 | #define IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \ | |
1543 | ((1 << (_chnl)) << 16) | |
1544 | ||
1545 | #define IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \ | |
1546 | (IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \ | |
1547 | IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl)) | |
1548 | ||
b481de9c | 1549 | |
b481de9c ZY |
1550 | #define SCD_WIN_SIZE 64 |
1551 | #define SCD_FRAME_LIMIT 64 | |
1552 | ||
b481de9c ZY |
1553 | /* SRAM structures */ |
1554 | #define SCD_CONTEXT_DATA_OFFSET 0x380 | |
1555 | #define SCD_TX_STTS_BITMAP_OFFSET 0x400 | |
1556 | #define SCD_TRANSLATE_TBL_OFFSET 0x500 | |
1557 | #define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8)) | |
1558 | #define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ | |
1559 | ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc) | |
1560 | ||
1561 | #define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \ | |
1562 | ((1<<(hi))|((1<<(hi))-(1<<(lo)))) | |
1563 | ||
b481de9c ZY |
1564 | #define SCD_QUEUE_STTS_REG_POS_ACTIVE (0) |
1565 | #define SCD_QUEUE_STTS_REG_POS_TXF (1) | |
1566 | #define SCD_QUEUE_STTS_REG_POS_WSL (5) | |
1567 | #define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8) | |
1568 | #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10) | |
1569 | #define SCD_QUEUE_STTS_REG_MSK (0x0007FC00) | |
1570 | ||
b481de9c ZY |
1571 | #define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0) |
1572 | #define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F) | |
2248d8d8 | 1573 | |
b481de9c ZY |
1574 | #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) |
1575 | #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) | |
1576 | ||
1577 | #define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R (0x00000010) | |
1578 | #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00) | |
1579 | #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) | |
1580 | #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) | |
fcd427bb | 1581 | #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) |
b481de9c | 1582 | |
bb8c093b | 1583 | static inline u8 iwl4965_hw_get_rate(__le32 rate_n_flags) |
b481de9c ZY |
1584 | { |
1585 | return le32_to_cpu(rate_n_flags) & 0xFF; | |
1586 | } | |
bb8c093b | 1587 | static inline u16 iwl4965_hw_get_rate_n_flags(__le32 rate_n_flags) |
b481de9c ZY |
1588 | { |
1589 | return le32_to_cpu(rate_n_flags) & 0xFFFF; | |
1590 | } | |
bb8c093b | 1591 | static inline __le32 iwl4965_hw_set_rate_n_flags(u8 rate, u16 flags) |
b481de9c ZY |
1592 | { |
1593 | return cpu_to_le32(flags|(u16)rate); | |
1594 | } | |
1595 | ||
bb8c093b | 1596 | struct iwl4965_tfd_frame_data { |
b481de9c ZY |
1597 | __le32 tb1_addr; |
1598 | ||
1599 | __le32 val1; | |
1600 | /* __le32 ptb1_32_35:4; */ | |
1601 | #define IWL_tb1_addr_hi_POS 0 | |
1602 | #define IWL_tb1_addr_hi_LEN 4 | |
1603 | #define IWL_tb1_addr_hi_SYM val1 | |
1604 | /* __le32 tb_len1:12; */ | |
1605 | #define IWL_tb1_len_POS 4 | |
1606 | #define IWL_tb1_len_LEN 12 | |
1607 | #define IWL_tb1_len_SYM val1 | |
1608 | /* __le32 ptb2_0_15:16; */ | |
1609 | #define IWL_tb2_addr_lo16_POS 16 | |
1610 | #define IWL_tb2_addr_lo16_LEN 16 | |
1611 | #define IWL_tb2_addr_lo16_SYM val1 | |
1612 | ||
1613 | __le32 val2; | |
1614 | /* __le32 ptb2_16_35:20; */ | |
1615 | #define IWL_tb2_addr_hi20_POS 0 | |
1616 | #define IWL_tb2_addr_hi20_LEN 20 | |
1617 | #define IWL_tb2_addr_hi20_SYM val2 | |
1618 | /* __le32 tb_len2:12; */ | |
1619 | #define IWL_tb2_len_POS 20 | |
1620 | #define IWL_tb2_len_LEN 12 | |
1621 | #define IWL_tb2_len_SYM val2 | |
1622 | } __attribute__ ((packed)); | |
1623 | ||
bb8c093b | 1624 | struct iwl4965_tfd_frame { |
b481de9c ZY |
1625 | __le32 val0; |
1626 | /* __le32 rsvd1:24; */ | |
1627 | /* __le32 num_tbs:5; */ | |
1628 | #define IWL_num_tbs_POS 24 | |
1629 | #define IWL_num_tbs_LEN 5 | |
1630 | #define IWL_num_tbs_SYM val0 | |
1631 | /* __le32 rsvd2:1; */ | |
1632 | /* __le32 padding:2; */ | |
bb8c093b | 1633 | struct iwl4965_tfd_frame_data pa[10]; |
b481de9c ZY |
1634 | __le32 reserved; |
1635 | } __attribute__ ((packed)); | |
1636 | ||
1637 | #define IWL4965_MAX_WIN_SIZE 64 | |
1638 | #define IWL4965_QUEUE_SIZE 256 | |
1639 | #define IWL4965_NUM_FIFOS 7 | |
1640 | #define IWL_MAX_NUM_QUEUES 16 | |
1641 | ||
1642 | struct iwl4965_queue_byte_cnt_entry { | |
1643 | __le16 val; | |
1644 | /* __le16 byte_cnt:12; */ | |
1645 | #define IWL_byte_cnt_POS 0 | |
1646 | #define IWL_byte_cnt_LEN 12 | |
1647 | #define IWL_byte_cnt_SYM val | |
1648 | /* __le16 rsvd:4; */ | |
1649 | } __attribute__ ((packed)); | |
1650 | ||
1651 | struct iwl4965_sched_queue_byte_cnt_tbl { | |
1652 | struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL4965_QUEUE_SIZE + | |
1653 | IWL4965_MAX_WIN_SIZE]; | |
1654 | u8 dont_care[1024 - | |
1655 | (IWL4965_QUEUE_SIZE + IWL4965_MAX_WIN_SIZE) * | |
1656 | sizeof(__le16)]; | |
1657 | } __attribute__ ((packed)); | |
1658 | ||
bb8c093b CH |
1659 | /* Base physical address of iwl4965_shared is provided to KDR_SCD_DRAM_BASE_ADDR |
1660 | * and &iwl4965_shared.val0 is provided to FH_RSCSR_CHNL0_STTS_WPTR_REG */ | |
1661 | struct iwl4965_shared { | |
b481de9c ZY |
1662 | struct iwl4965_sched_queue_byte_cnt_tbl |
1663 | queues_byte_cnt_tbls[IWL_MAX_NUM_QUEUES]; | |
1664 | __le32 val0; | |
1665 | ||
1666 | /* __le32 rb_closed_stts_rb_num:12; */ | |
1667 | #define IWL_rb_closed_stts_rb_num_POS 0 | |
1668 | #define IWL_rb_closed_stts_rb_num_LEN 12 | |
1669 | #define IWL_rb_closed_stts_rb_num_SYM val0 | |
1670 | /* __le32 rsrv1:4; */ | |
1671 | /* __le32 rb_closed_stts_rx_frame_num:12; */ | |
1672 | #define IWL_rb_closed_stts_rx_frame_num_POS 16 | |
1673 | #define IWL_rb_closed_stts_rx_frame_num_LEN 12 | |
1674 | #define IWL_rb_closed_stts_rx_frame_num_SYM val0 | |
1675 | /* __le32 rsrv2:4; */ | |
1676 | ||
1677 | __le32 val1; | |
1678 | /* __le32 frame_finished_stts_rb_num:12; */ | |
1679 | #define IWL_frame_finished_stts_rb_num_POS 0 | |
1680 | #define IWL_frame_finished_stts_rb_num_LEN 12 | |
1681 | #define IWL_frame_finished_stts_rb_num_SYM val1 | |
1682 | /* __le32 rsrv3:4; */ | |
1683 | /* __le32 frame_finished_stts_rx_frame_num:12; */ | |
1684 | #define IWL_frame_finished_stts_rx_frame_num_POS 16 | |
1685 | #define IWL_frame_finished_stts_rx_frame_num_LEN 12 | |
1686 | #define IWL_frame_finished_stts_rx_frame_num_SYM val1 | |
1687 | /* __le32 rsrv4:4; */ | |
1688 | ||
1689 | __le32 padding1; /* so that allocation will be aligned to 16B */ | |
1690 | __le32 padding2; | |
1691 | } __attribute__ ((packed)); | |
1692 | ||
bb8c093b | 1693 | #endif /* __iwl4965_4965_hw_h__ */ |