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iwlwifi: perform bss_info_changed post association work right away
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <net/mac80211.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47 39#include <asm/unaligned.h>
b481de9c 40
6bc913bd 41#include "iwl-eeprom.h"
b481de9c 42#include "iwl-4965.h"
fee1247a 43#include "iwl-core.h"
3395f6e9 44#include "iwl-io.h"
b481de9c
ZY		 45#include "iwl-helpers.h"
46
1ea87396
AK		 47/* module parameters */
48static struct iwl_mod_params iwl4965_mod_params = {
49 .num_of_queues = IWL_MAX_NUM_QUEUES,
50 .enable_qos = 1,
51 .amsdu_size_8K = 1,
52 /* the rest are 0 by default */
53};
54
c79dd5b5 55static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
416e1438 56
b481de9c
ZY		 57#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
58 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
59 IWL_RATE_SISO_##s##M_PLCP, \
60 IWL_RATE_MIMO_##s##M_PLCP, \
61 IWL_RATE_##r##M_IEEE, \
62 IWL_RATE_##ip##M_INDEX, \
63 IWL_RATE_##in##M_INDEX, \
64 IWL_RATE_##rp##M_INDEX, \
65 IWL_RATE_##rn##M_INDEX, \
66 IWL_RATE_##pp##M_INDEX, \
67 IWL_RATE_##np##M_INDEX }
68
69/*
70 * Parameter order:
71 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
72 *
73 * If there isn't a valid next or previous rate then INV is used which
74 * maps to IWL_RATE_INVALID
75 *
76 */
bb8c093b 77const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
b481de9c
ZY		 78 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
79 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
80 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
81 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
82 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
83 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
84 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
85 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
86 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
87 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
88 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
89 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
90 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
91};
92
fe01b477
RR		 93#ifdef CONFIG_IWL4965_HT
94
95static const u16 default_tid_to_tx_fifo[] = {
96 IWL_TX_FIFO_AC1,
97 IWL_TX_FIFO_AC0,
98 IWL_TX_FIFO_AC0,
99 IWL_TX_FIFO_AC1,
100 IWL_TX_FIFO_AC2,
101 IWL_TX_FIFO_AC2,
102 IWL_TX_FIFO_AC3,
103 IWL_TX_FIFO_AC3,
104 IWL_TX_FIFO_NONE,
105 IWL_TX_FIFO_NONE,
106 IWL_TX_FIFO_NONE,
107 IWL_TX_FIFO_NONE,
108 IWL_TX_FIFO_NONE,
109 IWL_TX_FIFO_NONE,
110 IWL_TX_FIFO_NONE,
111 IWL_TX_FIFO_NONE,
112 IWL_TX_FIFO_AC3
113};
114
115#endif /*CONFIG_IWL4965_HT */
116
57aab75a
TW		 117/* check contents of special bootstrap uCode SRAM */
118static int iwl4965_verify_bsm(struct iwl_priv *priv)
119{
120 __le32 *image = priv->ucode_boot.v_addr;
121 u32 len = priv->ucode_boot.len;
122 u32 reg;
123 u32 val;
124
125 IWL_DEBUG_INFO("Begin verify bsm\n");
126
127 /* verify BSM SRAM contents */
128 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
129 for (reg = BSM_SRAM_LOWER_BOUND;
130 reg < BSM_SRAM_LOWER_BOUND + len;
131 reg += sizeof(u32), image++) {
132 val = iwl_read_prph(priv, reg);
133 if (val != le32_to_cpu(*image)) {
134 IWL_ERROR("BSM uCode verification failed at "
135 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
136 BSM_SRAM_LOWER_BOUND,
137 reg - BSM_SRAM_LOWER_BOUND, len,
138 val, le32_to_cpu(*image));
139 return -EIO;
140 }
141 }
142
143 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
144
145 return 0;
146}
147
148/**
149 * iwl4965_load_bsm - Load bootstrap instructions
150 *
151 * BSM operation:
152 *
153 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
154 * in special SRAM that does not power down during RFKILL. When powering back
155 * up after power-saving sleeps (or during initial uCode load), the BSM loads
156 * the bootstrap program into the on-board processor, and starts it.
157 *
158 * The bootstrap program loads (via DMA) instructions and data for a new
159 * program from host DRAM locations indicated by the host driver in the
160 * BSM_DRAM_* registers. Once the new program is loaded, it starts
161 * automatically.
162 *
163 * When initializing the NIC, the host driver points the BSM to the
164 * "initialize" uCode image. This uCode sets up some internal data, then
165 * notifies host via "initialize alive" that it is complete.
166 *
167 * The host then replaces the BSM_DRAM_* pointer values to point to the
168 * normal runtime uCode instructions and a backup uCode data cache buffer
169 * (filled initially with starting data values for the on-board processor),
170 * then triggers the "initialize" uCode to load and launch the runtime uCode,
171 * which begins normal operation.
172 *
173 * When doing a power-save shutdown, runtime uCode saves data SRAM into
174 * the backup data cache in DRAM before SRAM is powered down.
175 *
176 * When powering back up, the BSM loads the bootstrap program. This reloads
177 * the runtime uCode instructions and the backup data cache into SRAM,
178 * and re-launches the runtime uCode from where it left off.
179 */
180static int iwl4965_load_bsm(struct iwl_priv *priv)
181{
182 __le32 *image = priv->ucode_boot.v_addr;
183 u32 len = priv->ucode_boot.len;
184 dma_addr_t pinst;
185 dma_addr_t pdata;
186 u32 inst_len;
187 u32 data_len;
188 int i;
189 u32 done;
190 u32 reg_offset;
191 int ret;
192
193 IWL_DEBUG_INFO("Begin load bsm\n");
194
195 /* make sure bootstrap program is no larger than BSM's SRAM size */
196 if (len > IWL_MAX_BSM_SIZE)
197 return -EINVAL;
198
199 /* Tell bootstrap uCode where to find the "Initialize" uCode
200 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
201 * NOTE: iwl4965_initialize_alive_start() will replace these values,
202 * after the "initialize" uCode has run, to point to
203 * runtime/protocol instructions and backup data cache. */
204 pinst = priv->ucode_init.p_addr >> 4;
205 pdata = priv->ucode_init_data.p_addr >> 4;
206 inst_len = priv->ucode_init.len;
207 data_len = priv->ucode_init_data.len;
208
209 ret = iwl_grab_nic_access(priv);
210 if (ret)
211 return ret;
212
213 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
214 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
215 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
216 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
217
218 /* Fill BSM memory with bootstrap instructions */
219 for (reg_offset = BSM_SRAM_LOWER_BOUND;
220 reg_offset < BSM_SRAM_LOWER_BOUND + len;
221 reg_offset += sizeof(u32), image++)
222 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
223
224 ret = iwl4965_verify_bsm(priv);
225 if (ret) {
226 iwl_release_nic_access(priv);
227 return ret;
228 }
229
230 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
231 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
232 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
233 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
234
235 /* Load bootstrap code into instruction SRAM now,
236 * to prepare to load "initialize" uCode */
237 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
238
239 /* Wait for load of bootstrap uCode to finish */
240 for (i = 0; i < 100; i++) {
241 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
242 if (!(done & BSM_WR_CTRL_REG_BIT_START))
243 break;
244 udelay(10);
245 }
246 if (i < 100)
247 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
248 else {
249 IWL_ERROR("BSM write did not complete!\n");
250 return -EIO;
251 }
252
253 /* Enable future boot loads whenever power management unit triggers it
254 * (e.g. when powering back up after power-save shutdown) */
255 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
256
257 iwl_release_nic_access(priv);
258
259 return 0;
260}
261
bf85ea4f
AK		 262static int iwl4965_init_drv(struct iwl_priv *priv)
263{
264 int ret;
265 int i;
266
1ea87396 267 priv->antenna = (enum iwl4965_antenna)priv->cfg->mod_params->antenna;
bf85ea4f
AK		 268 priv->retry_rate = 1;
269 priv->ibss_beacon = NULL;
270
271 spin_lock_init(&priv->lock);
272 spin_lock_init(&priv->power_data.lock);
273 spin_lock_init(&priv->sta_lock);
274 spin_lock_init(&priv->hcmd_lock);
275 spin_lock_init(&priv->lq_mngr.lock);
276
277 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
278 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
279
280 INIT_LIST_HEAD(&priv->free_frames);
281
282 mutex_init(&priv->mutex);
283
284 /* Clear the driver's (not device's) station table */
285 iwlcore_clear_stations_table(priv);
286
287 priv->data_retry_limit = -1;
288 priv->ieee_channels = NULL;
289 priv->ieee_rates = NULL;
290 priv->band = IEEE80211_BAND_2GHZ;
291
292 priv->iw_mode = IEEE80211_IF_TYPE_STA;
293
294 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
295 priv->valid_antenna = 0x7; /* assume all 3 connected */
296 priv->ps_mode = IWL_MIMO_PS_NONE;
297
298 /* Choose which receivers/antennas to use */
299 iwl4965_set_rxon_chain(priv);
300
301 iwlcore_reset_qos(priv);
302
303 priv->qos_data.qos_active = 0;
304 priv->qos_data.qos_cap.val = 0;
305
306 iwlcore_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
307
308 priv->rates_mask = IWL_RATES_MASK;
309 /* If power management is turned on, default to AC mode */
310 priv->power_mode = IWL_POWER_AC;
311 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
312
313 ret = iwl_init_channel_map(priv);
314 if (ret) {
315 IWL_ERROR("initializing regulatory failed: %d\n", ret);
316 goto err;
317 }
318
319 ret = iwl4965_init_geos(priv);
320 if (ret) {
321 IWL_ERROR("initializing geos failed: %d\n", ret);
322 goto err_free_channel_map;
323 }
324
bf85ea4f
AK		 325 ret = ieee80211_register_hw(priv->hw);
326 if (ret) {
327 IWL_ERROR("Failed to register network device (error %d)\n",
328 ret);
329 goto err_free_geos;
330 }
331
332 priv->hw->conf.beacon_int = 100;
333 priv->mac80211_registered = 1;
334
335 return 0;
336
337err_free_geos:
338 iwl4965_free_geos(priv);
339err_free_channel_map:
340 iwl_free_channel_map(priv);
341err:
342 return ret;
343}
344
b481de9c
ZY		 345static int is_fat_channel(__le32 rxon_flags)
346{
347 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
348 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
349}
350
c79dd5b5 351static u8 is_single_stream(struct iwl_priv *priv)
b481de9c 352{
c8b0e6e1 353#ifdef CONFIG_IWL4965_HT
fd105e79
RR		 354 if (!priv->current_ht_config.is_ht ||
355 (priv->current_ht_config.supp_mcs_set[1] == 0) ||
b481de9c
ZY		 356 (priv->ps_mode == IWL_MIMO_PS_STATIC))
357 return 1;
358#else
359 return 1;
c8b0e6e1 360#endif /*CONFIG_IWL4965_HT */
b481de9c
ZY		 361 return 0;
362}
363
17744ff6
TW		 364int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
365{
366 int idx = 0;
367
368 /* 4965 HT rate format */
369 if (rate_n_flags & RATE_MCS_HT_MSK) {
370 idx = (rate_n_flags & 0xff);
371
372 if (idx >= IWL_RATE_MIMO_6M_PLCP)
373 idx = idx - IWL_RATE_MIMO_6M_PLCP;
374
375 idx += IWL_FIRST_OFDM_RATE;
376 /* skip 9M not supported in ht*/
377 if (idx >= IWL_RATE_9M_INDEX)
378 idx += 1;
379 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
380 return idx;
381
382 /* 4965 legacy rate format, search for match in table */
383 } else {
384 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
385 if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
386 return idx;
387 }
388
389 return -1;
390}
391
4c424e4c
RR		 392/**
393 * translate ucode response to mac80211 tx status control values
394 */
c79dd5b5 395void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
4c424e4c
RR		 396 struct ieee80211_tx_control *control)
397{
398 int rate_index;
399
400 control->antenna_sel_tx =
401 ((rate_n_flags & RATE_MCS_ANT_AB_MSK) >> RATE_MCS_ANT_A_POS);
402 if (rate_n_flags & RATE_MCS_HT_MSK)
403 control->flags |= IEEE80211_TXCTL_OFDM_HT;
404 if (rate_n_flags & RATE_MCS_GF_MSK)
405 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
406 if (rate_n_flags & RATE_MCS_FAT_MSK)
407 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
408 if (rate_n_flags & RATE_MCS_DUP_MSK)
409 control->flags |= IEEE80211_TXCTL_DUP_DATA;
410 if (rate_n_flags & RATE_MCS_SGI_MSK)
411 control->flags |= IEEE80211_TXCTL_SHORT_GI;
412 /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
413 * IEEE80211_BAND_2GHZ band as it contains all the rates */
414 rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
415 if (rate_index == -1)
416 control->tx_rate = NULL;
417 else
418 control->tx_rate =
419 &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
420}
17744ff6 421
b481de9c
ZY		 422/*
423 * Determine how many receiver/antenna chains to use.
424 * More provides better reception via diversity. Fewer saves power.
425 * MIMO (dual stream) requires at least 2, but works better with 3.
426 * This does not determine *which* chains to use, just how many.
427 */
c79dd5b5 428static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
b481de9c
ZY		 429 u8 *idle_state, u8 *rx_state)
430{
431 u8 is_single = is_single_stream(priv);
432 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
433
434 /* # of Rx chains to use when expecting MIMO. */
435 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
436 *rx_state = 2;
437 else
438 *rx_state = 3;
439
440 /* # Rx chains when idling and maybe trying to save power */
441 switch (priv->ps_mode) {
442 case IWL_MIMO_PS_STATIC:
443 case IWL_MIMO_PS_DYNAMIC:
444 *idle_state = (is_cam) ? 2 : 1;
445 break;
446 case IWL_MIMO_PS_NONE:
447 *idle_state = (is_cam) ? *rx_state : 1;
448 break;
449 default:
450 *idle_state = 1;
451 break;
452 }
453
454 return 0;
455}
456
c79dd5b5 457int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 458{
459 int rc;
460 unsigned long flags;
461
462 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 463 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 464 if (rc) {
465 spin_unlock_irqrestore(&priv->lock, flags);
466 return rc;
467 }
468
8b6eaea8 469 /* stop Rx DMA */
3395f6e9
TW		 470 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
471 rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
b481de9c
ZY		 472 (1 << 24), 1000);
473 if (rc < 0)
474 IWL_ERROR("Can't stop Rx DMA.\n");
475
3395f6e9 476 iwl_release_nic_access(priv);
b481de9c
ZY		 477 spin_unlock_irqrestore(&priv->lock, flags);
478
479 return 0;
480}
481
c79dd5b5 482u8 iwl4965_hw_find_station(struct iwl_priv *priv, const u8 *addr)
b481de9c
ZY		 483{
484 int i;
485 int start = 0;
486 int ret = IWL_INVALID_STATION;
487 unsigned long flags;
0795af57 488 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 489
490 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) ||
491 (priv->iw_mode == IEEE80211_IF_TYPE_AP))
492 start = IWL_STA_ID;
493
494 if (is_broadcast_ether_addr(addr))
a4062b8f 495 return priv->hw_setting.bcast_sta_id;
b481de9c
ZY		 496
497 spin_lock_irqsave(&priv->sta_lock, flags);
498 for (i = start; i < priv->hw_setting.max_stations; i++)
499 if ((priv->stations[i].used) &&
500 (!compare_ether_addr
501 (priv->stations[i].sta.sta.addr, addr))) {
502 ret = i;
503 goto out;
504 }
505
a50e2e3f 506 IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n",
0795af57 507 print_mac(mac, addr), priv->num_stations);
b481de9c
ZY		 508
509 out:
510 spin_unlock_irqrestore(&priv->sta_lock, flags);
511 return ret;
512}
513
c79dd5b5 514static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
b481de9c 515{
d8609652 516 int ret;
b481de9c
ZY		 517 unsigned long flags;
518
519 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 520 ret = iwl_grab_nic_access(priv);
d8609652 521 if (ret) {
b481de9c 522 spin_unlock_irqrestore(&priv->lock, flags);
d8609652 523 return ret;
b481de9c
ZY		 524 }
525
526 if (!pwr_max) {
527 u32 val;
528
d8609652 529 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
b481de9c
ZY		 530 &val);
531
532 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
3395f6e9 533 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 534 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
535 ~APMG_PS_CTRL_MSK_PWR_SRC);
536 } else
3395f6e9 537 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 538 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
539 ~APMG_PS_CTRL_MSK_PWR_SRC);
540
3395f6e9 541 iwl_release_nic_access(priv);
b481de9c
ZY		 542 spin_unlock_irqrestore(&priv->lock, flags);
543
d8609652 544 return ret;
b481de9c
ZY		 545}
546
c79dd5b5 547static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
b481de9c
ZY		 548{
549 int rc;
550 unsigned long flags;
9ee1ba47 551 unsigned int rb_size;
b481de9c
ZY		 552
553 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 554 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 555 if (rc) {
556 spin_unlock_irqrestore(&priv->lock, flags);
557 return rc;
558 }
559
1ea87396 560 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47
RR		 561 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
562 else
563 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
564
8b6eaea8 565 /* Stop Rx DMA */
3395f6e9 566 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
b481de9c 567
8b6eaea8 568 /* Reset driver's Rx queue write index */
3395f6e9 569 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
8b6eaea8
CB		 570
571 /* Tell device where to find RBD circular buffer in DRAM */
3395f6e9
TW		 572 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
573 rxq->dma_addr >> 8);
b481de9c 574
8b6eaea8 575 /* Tell device where in DRAM to update its Rx status */
3395f6e9
TW		 576 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
577 (priv->hw_setting.shared_phys +
578 offsetof(struct iwl4965_shared, val0)) >> 4);
b481de9c 579
8b6eaea8 580 /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
3395f6e9
TW		 581 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
582 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
583 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
584 rb_size |
b481de9c 585 /*0x10 << 4 | */
3395f6e9 586 (RX_QUEUE_SIZE_LOG <<
b481de9c
ZY		 587 FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
588
589 /*
3395f6e9 590 * iwl_write32(priv,CSR_INT_COAL_REG,0);
b481de9c
ZY		 591 */
592
3395f6e9 593 iwl_release_nic_access(priv);
b481de9c
ZY		 594 spin_unlock_irqrestore(&priv->lock, flags);
595
596 return 0;
597}
598
8b6eaea8 599/* Tell 4965 where to find the "keep warm" buffer */
c79dd5b5 600static int iwl4965_kw_init(struct iwl_priv *priv)
b481de9c
ZY		 601{
602 unsigned long flags;
603 int rc;
604
605 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 606 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 607 if (rc)
608 goto out;
609
3395f6e9 610 iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
b481de9c 611 priv->kw.dma_addr >> 4);
3395f6e9 612 iwl_release_nic_access(priv);
b481de9c
ZY		 613out:
614 spin_unlock_irqrestore(&priv->lock, flags);
615 return rc;
616}
617
c79dd5b5 618static int iwl4965_kw_alloc(struct iwl_priv *priv)
b481de9c
ZY		 619{
620 struct pci_dev *dev = priv->pci_dev;
bb8c093b 621 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 622
623 kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
624 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
625 if (!kw->v_addr)
626 return -ENOMEM;
627
628 return 0;
629}
630
8b6eaea8
CB		 631/**
632 * iwl4965_kw_free - Free the "keep warm" buffer
633 */
c79dd5b5 634static void iwl4965_kw_free(struct iwl_priv *priv)
b481de9c
ZY		 635{
636 struct pci_dev *dev = priv->pci_dev;
bb8c093b 637 struct iwl4965_kw *kw = &priv->kw;
b481de9c
ZY		 638
639 if (kw->v_addr) {
640 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
641 memset(kw, 0, sizeof(*kw));
642 }
643}
644
645/**
646 * iwl4965_txq_ctx_reset - Reset TX queue context
647 * Destroys all DMA structures and initialise them again
648 *
649 * @param priv
650 * @return error code
651 */
c79dd5b5 652static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 653{
654 int rc = 0;
655 int txq_id, slots_num;
656 unsigned long flags;
657
658 iwl4965_kw_free(priv);
659
8b6eaea8 660 /* Free all tx/cmd queues and keep-warm buffer */
bb8c093b 661 iwl4965_hw_txq_ctx_free(priv);
b481de9c 662
8b6eaea8 663 /* Alloc keep-warm buffer */
b481de9c
ZY		 664 rc = iwl4965_kw_alloc(priv);
665 if (rc) {
666 IWL_ERROR("Keep Warm allocation failed");
667 goto error_kw;
668 }
669
670 spin_lock_irqsave(&priv->lock, flags);
671
3395f6e9 672 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 673 if (unlikely(rc)) {
674 IWL_ERROR("TX reset failed");
675 spin_unlock_irqrestore(&priv->lock, flags);
676 goto error_reset;
677 }
678
8b6eaea8 679 /* Turn off all Tx DMA channels */
12a81f60 680 iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
3395f6e9 681 iwl_release_nic_access(priv);
b481de9c
ZY		 682 spin_unlock_irqrestore(&priv->lock, flags);
683
8b6eaea8 684 /* Tell 4965 where to find the keep-warm buffer */
b481de9c
ZY		 685 rc = iwl4965_kw_init(priv);
686 if (rc) {
687 IWL_ERROR("kw_init failed\n");
688 goto error_reset;
689 }
690
8b6eaea8
CB		 691 /* Alloc and init all (default 16) Tx queues,
692 * including the command queue (#4) */
b481de9c
ZY		 693 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
694 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
695 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
bb8c093b 696 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
b481de9c
ZY		 697 txq_id);
698 if (rc) {
699 IWL_ERROR("Tx %d queue init failed\n", txq_id);
700 goto error;
701 }
702 }
703
704 return rc;
705
706 error:
bb8c093b 707 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 708 error_reset:
709 iwl4965_kw_free(priv);
710 error_kw:
711 return rc;
712}
713
c79dd5b5 714int iwl4965_hw_nic_init(struct iwl_priv *priv)
b481de9c
ZY		 715{
716 int rc;
717 unsigned long flags;
bb8c093b 718 struct iwl4965_rx_queue *rxq = &priv->rxq;
b481de9c
ZY		 719 u8 rev_id;
720 u32 val;
721 u8 val_link;
722
bb8c093b 723 iwl4965_power_init_handle(priv);
b481de9c
ZY		 724
725 /* nic_init */
726 spin_lock_irqsave(&priv->lock, flags);
727
3395f6e9 728 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
b481de9c
ZY		 729 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
730
3395f6e9
TW		 731 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
732 rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 733 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
734 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
735 if (rc < 0) {
736 spin_unlock_irqrestore(&priv->lock, flags);
737 IWL_DEBUG_INFO("Failed to init the card\n");
738 return rc;
739 }
740
3395f6e9 741 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 742 if (rc) {
743 spin_unlock_irqrestore(&priv->lock, flags);
744 return rc;
745 }
746
3395f6e9 747 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
b481de9c 748
3395f6e9
TW		 749 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
750 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
751 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
b481de9c
ZY		 752
753 udelay(20);
754
3395f6e9
TW		 755 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
756 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 757
3395f6e9
TW		 758 iwl_release_nic_access(priv);
759 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
b481de9c
ZY		 760 spin_unlock_irqrestore(&priv->lock, flags);
761
762 /* Determine HW type */
763 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
764 if (rc)
765 return rc;
766
767 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
768
769 iwl4965_nic_set_pwr_src(priv, 1);
770 spin_lock_irqsave(&priv->lock, flags);
771
772 if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
773 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
774 /* Enable No Snoop field */
775 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
776 val & ~(1 << 11));
777 }
778
779 spin_unlock_irqrestore(&priv->lock, flags);
780
b481de9c
ZY		 781 if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) {
782 IWL_ERROR("Older EEPROM detected! Aborting.\n");
783 return -EINVAL;
784 }
785
786 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
787
788 /* disable L1 entry -- workaround for pre-B1 */
789 pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
790
791 spin_lock_irqsave(&priv->lock, flags);
792
793 /* set CSR_HW_CONFIG_REG for uCode use */
794
3395f6e9
TW		 795 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
796 CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
797 CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
798 CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 799
3395f6e9 800 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 801 if (rc < 0) {
802 spin_unlock_irqrestore(&priv->lock, flags);
803 IWL_DEBUG_INFO("Failed to init the card\n");
804 return rc;
805 }
806
3395f6e9
TW		 807 iwl_read_prph(priv, APMG_PS_CTRL_REG);
808 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
b481de9c 809 udelay(5);
3395f6e9 810 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
b481de9c 811
3395f6e9 812 iwl_release_nic_access(priv);
b481de9c
ZY		 813 spin_unlock_irqrestore(&priv->lock, flags);
814
bb8c093b 815 iwl4965_hw_card_show_info(priv);
b481de9c
ZY		 816
817 /* end nic_init */
818
819 /* Allocate the RX queue, or reset if it is already allocated */
820 if (!rxq->bd) {
bb8c093b 821 rc = iwl4965_rx_queue_alloc(priv);
b481de9c
ZY		 822 if (rc) {
823 IWL_ERROR("Unable to initialize Rx queue\n");
824 return -ENOMEM;
825 }
826 } else
bb8c093b 827 iwl4965_rx_queue_reset(priv, rxq);
b481de9c 828
bb8c093b 829 iwl4965_rx_replenish(priv);
b481de9c
ZY		 830
831 iwl4965_rx_init(priv, rxq);
832
833 spin_lock_irqsave(&priv->lock, flags);
834
835 rxq->need_update = 1;
bb8c093b 836 iwl4965_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 837
838 spin_unlock_irqrestore(&priv->lock, flags);
8b6eaea8
CB		 839
840 /* Allocate and init all Tx and Command queues */
b481de9c
ZY		 841 rc = iwl4965_txq_ctx_reset(priv);
842 if (rc)
843 return rc;
844
845 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
846 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
847
848 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
849 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
850
851 set_bit(STATUS_INIT, &priv->status);
852
853 return 0;
854}
855
c79dd5b5 856int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
b481de9c
ZY		 857{
858 int rc = 0;
859 u32 reg_val;
860 unsigned long flags;
861
862 spin_lock_irqsave(&priv->lock, flags);
863
864 /* set stop master bit */
3395f6e9 865 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 866
3395f6e9 867 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
b481de9c
ZY		 868
869 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
870 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
871 IWL_DEBUG_INFO("Card in power save, master is already "
872 "stopped\n");
873 else {
3395f6e9 874 rc = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 875 CSR_RESET_REG_FLAG_MASTER_DISABLED,
876 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
877 if (rc < 0) {
878 spin_unlock_irqrestore(&priv->lock, flags);
879 return rc;
880 }
881 }
882
883 spin_unlock_irqrestore(&priv->lock, flags);
884 IWL_DEBUG_INFO("stop master\n");
885
886 return rc;
887}
888
8b6eaea8
CB		 889/**
890 * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
891 */
c79dd5b5 892void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c
ZY		 893{
894
895 int txq_id;
896 unsigned long flags;
897
8b6eaea8 898 /* Stop each Tx DMA channel, and wait for it to be idle */
b481de9c
ZY		 899 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
900 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 901 if (iwl_grab_nic_access(priv)) {
b481de9c
ZY		 902 spin_unlock_irqrestore(&priv->lock, flags);
903 continue;
904 }
905
3395f6e9
TW		 906 iwl_write_direct32(priv,
907 IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
908 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
909 IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
910 (txq_id), 200);
911 iwl_release_nic_access(priv);
b481de9c
ZY		 912 spin_unlock_irqrestore(&priv->lock, flags);
913 }
914
8b6eaea8 915 /* Deallocate memory for all Tx queues */
bb8c093b 916 iwl4965_hw_txq_ctx_free(priv);
b481de9c
ZY		 917}
918
c79dd5b5 919int iwl4965_hw_nic_reset(struct iwl_priv *priv)
b481de9c
ZY		 920{
921 int rc = 0;
922 unsigned long flags;
923
bb8c093b 924 iwl4965_hw_nic_stop_master(priv);
b481de9c
ZY		 925
926 spin_lock_irqsave(&priv->lock, flags);
927
3395f6e9 928 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 929
930 udelay(10);
931
3395f6e9
TW		 932 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
933 rc = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 934 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
935 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
936
937 udelay(10);
938
3395f6e9 939 rc = iwl_grab_nic_access(priv);
b481de9c 940 if (!rc) {
3395f6e9
TW		 941 iwl_write_prph(priv, APMG_CLK_EN_REG,
942 APMG_CLK_VAL_DMA_CLK_RQT |
943 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 944
945 udelay(10);
946
3395f6e9
TW		 947 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
948 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 949
3395f6e9 950 iwl_release_nic_access(priv);
b481de9c
ZY		 951 }
952
953 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
954 wake_up_interruptible(&priv->wait_command_queue);
955
956 spin_unlock_irqrestore(&priv->lock, flags);
957
958 return rc;
959
960}
961
962#define REG_RECALIB_PERIOD (60)
963
964/**
965 * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
966 *
967 * This callback is provided in order to queue the statistics_work
968 * in work_queue context (v. softirq)
969 *
970 * This timer function is continually reset to execute within
971 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
972 * was received. We need to ensure we receive the statistics in order
973 * to update the temperature used for calibrating the TXPOWER. However,
974 * we can't send the statistics command from softirq context (which
975 * is the context which timers run at) so we have to queue off the
976 * statistics_work to actually send the command to the hardware.
977 */
978static void iwl4965_bg_statistics_periodic(unsigned long data)
979{
c79dd5b5 980 struct iwl_priv *priv = (struct iwl_priv *)data;
b481de9c
ZY		 981
982 queue_work(priv->workqueue, &priv->statistics_work);
983}
984
985/**
986 * iwl4965_bg_statistics_work - Send the statistics request to the hardware.
987 *
bb8c093b 988 * This is queued by iwl4965_bg_statistics_periodic.
b481de9c
ZY		 989 */
990static void iwl4965_bg_statistics_work(struct work_struct *work)
991{
c79dd5b5 992 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 993 statistics_work);
994
995 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
996 return;
997
998 mutex_lock(&priv->mutex);
bb8c093b 999 iwl4965_send_statistics_request(priv);
b481de9c
ZY		 1000 mutex_unlock(&priv->mutex);
1001}
1002
1003#define CT_LIMIT_CONST 259
1004#define TM_CT_KILL_THRESHOLD 110
1005
c79dd5b5 1006void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
b481de9c 1007{
bb8c093b 1008 struct iwl4965_ct_kill_config cmd;
b481de9c
ZY		 1009 u32 R1, R2, R3;
1010 u32 temp_th;
1011 u32 crit_temperature;
1012 unsigned long flags;
857485c0 1013 int ret = 0;
b481de9c
ZY		 1014
1015 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 1016 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
b481de9c
ZY		 1017 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1018 spin_unlock_irqrestore(&priv->lock, flags);
1019
1020 if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
1021 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1022 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1023 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1024 } else {
1025 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1026 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1027 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1028 }
1029
1030 temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
1031
1032 crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
1033 cmd.critical_temperature_R = cpu_to_le32(crit_temperature);
857485c0
TW		 1034 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1035 sizeof(cmd), &cmd);
1036 if (ret)
b481de9c
ZY		 1037 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1038 else
1039 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
1040}
1041
c8b0e6e1 1042#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 1043
1044/* "false alarms" are signals that our DSP tries to lock onto,
1045 * but then determines that they are either noise, or transmissions
1046 * from a distant wireless network (also "noise", really) that get
1047 * "stepped on" by stronger transmissions within our own network.
1048 * This algorithm attempts to set a sensitivity level that is high
1049 * enough to receive all of our own network traffic, but not so
1050 * high that our DSP gets too busy trying to lock onto non-network
1051 * activity/noise. */
c79dd5b5 1052static int iwl4965_sens_energy_cck(struct iwl_priv *priv,
b481de9c
ZY		 1053 u32 norm_fa,
1054 u32 rx_enable_time,
1055 struct statistics_general_data *rx_info)
1056{
1057 u32 max_nrg_cck = 0;
1058 int i = 0;
1059 u8 max_silence_rssi = 0;
1060 u32 silence_ref = 0;
1061 u8 silence_rssi_a = 0;
1062 u8 silence_rssi_b = 0;
1063 u8 silence_rssi_c = 0;
1064 u32 val;
1065
1066 /* "false_alarms" values below are cross-multiplications to assess the
1067 * numbers of false alarms within the measured period of actual Rx
1068 * (Rx is off when we're txing), vs the min/max expected false alarms
1069 * (some should be expected if rx is sensitive enough) in a
1070 * hypothetical listening period of 200 time units (TU), 204.8 msec:
1071 *
1072 * MIN_FA/fixed-time < false_alarms/actual-rx-time < MAX_FA/beacon-time
1073 *
1074 * */
1075 u32 false_alarms = norm_fa * 200 * 1024;
1076 u32 max_false_alarms = MAX_FA_CCK * rx_enable_time;
1077 u32 min_false_alarms = MIN_FA_CCK * rx_enable_time;
bb8c093b 1078 struct iwl4965_sensitivity_data *data = NULL;
b481de9c
ZY		 1079
1080 data = &(priv->sensitivity_data);
1081
1082 data->nrg_auto_corr_silence_diff = 0;
1083
1084 /* Find max silence rssi among all 3 receivers.
1085 * This is background noise, which may include transmissions from other
1086 * networks, measured during silence before our network's beacon */
1087 silence_rssi_a = (u8)((rx_info->beacon_silence_rssi_a &
8a1b0245 1088 ALL_BAND_FILTER) >> 8);
b481de9c 1089 silence_rssi_b = (u8)((rx_info->beacon_silence_rssi_b &
8a1b0245 1090 ALL_BAND_FILTER) >> 8);
b481de9c 1091 silence_rssi_c = (u8)((rx_info->beacon_silence_rssi_c &
8a1b0245 1092 ALL_BAND_FILTER) >> 8);
b481de9c
ZY		 1093
1094 val = max(silence_rssi_b, silence_rssi_c);
1095 max_silence_rssi = max(silence_rssi_a, (u8) val);
1096
1097 /* Store silence rssi in 20-beacon history table */
1098 data->nrg_silence_rssi[data->nrg_silence_idx] = max_silence_rssi;
1099 data->nrg_silence_idx++;
1100 if (data->nrg_silence_idx >= NRG_NUM_PREV_STAT_L)
1101 data->nrg_silence_idx = 0;
1102
1103 /* Find max silence rssi across 20 beacon history */
1104 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) {
1105 val = data->nrg_silence_rssi[i];
1106 silence_ref = max(silence_ref, val);
1107 }
1108 IWL_DEBUG_CALIB("silence a %u, b %u, c %u, 20-bcn max %u\n",
1109 silence_rssi_a, silence_rssi_b, silence_rssi_c,
1110 silence_ref);
1111
1112 /* Find max rx energy (min value!) among all 3 receivers,
1113 * measured during beacon frame.
1114 * Save it in 10-beacon history table. */
1115 i = data->nrg_energy_idx;
1116 val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c);
1117 data->nrg_value[i] = min(rx_info->beacon_energy_a, val);
1118
1119 data->nrg_energy_idx++;
1120 if (data->nrg_energy_idx >= 10)
1121 data->nrg_energy_idx = 0;
1122
1123 /* Find min rx energy (max value) across 10 beacon history.
1124 * This is the minimum signal level that we want to receive well.
1125 * Add backoff (margin so we don't miss slightly lower energy frames).
1126 * This establishes an upper bound (min value) for energy threshold. */
1127 max_nrg_cck = data->nrg_value[0];
1128 for (i = 1; i < 10; i++)
1129 max_nrg_cck = (u32) max(max_nrg_cck, (data->nrg_value[i]));
1130 max_nrg_cck += 6;
1131
1132 IWL_DEBUG_CALIB("rx energy a %u, b %u, c %u, 10-bcn max/min %u\n",
1133 rx_info->beacon_energy_a, rx_info->beacon_energy_b,
1134 rx_info->beacon_energy_c, max_nrg_cck - 6);
1135
1136 /* Count number of consecutive beacons with fewer-than-desired
1137 * false alarms. */
1138 if (false_alarms < min_false_alarms)
1139 data->num_in_cck_no_fa++;
1140 else
1141 data->num_in_cck_no_fa = 0;
1142 IWL_DEBUG_CALIB("consecutive bcns with few false alarms = %u\n",
1143 data->num_in_cck_no_fa);
1144
1145 /* If we got too many false alarms this time, reduce sensitivity */
1146 if (false_alarms > max_false_alarms) {
1147 IWL_DEBUG_CALIB("norm FA %u > max FA %u\n",
1148 false_alarms, max_false_alarms);
1149 IWL_DEBUG_CALIB("... reducing sensitivity\n");
1150 data->nrg_curr_state = IWL_FA_TOO_MANY;
1151
1152 if (data->auto_corr_cck > AUTO_CORR_MAX_TH_CCK) {
1153 /* Store for "fewer than desired" on later beacon */
1154 data->nrg_silence_ref = silence_ref;
1155
1156 /* increase energy threshold (reduce nrg value)
1157 * to decrease sensitivity */
1158 if (data->nrg_th_cck > (NRG_MAX_CCK + NRG_STEP_CCK))
1159 data->nrg_th_cck = data->nrg_th_cck
1160 - NRG_STEP_CCK;
1161 }
1162
1163 /* increase auto_corr values to decrease sensitivity */
1164 if (data->auto_corr_cck < AUTO_CORR_MAX_TH_CCK)
1165 data->auto_corr_cck = AUTO_CORR_MAX_TH_CCK + 1;
1166 else {
1167 val = data->auto_corr_cck + AUTO_CORR_STEP_CCK;
1168 data->auto_corr_cck = min((u32)AUTO_CORR_MAX_CCK, val);
1169 }
1170 val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK;
1171 data->auto_corr_cck_mrc = min((u32)AUTO_CORR_MAX_CCK_MRC, val);
1172
1173 /* Else if we got fewer than desired, increase sensitivity */
1174 } else if (false_alarms < min_false_alarms) {
1175 data->nrg_curr_state = IWL_FA_TOO_FEW;
1176
1177 /* Compare silence level with silence level for most recent
1178 * healthy number or too many false alarms */
1179 data->nrg_auto_corr_silence_diff = (s32)data->nrg_silence_ref -
1180 (s32)silence_ref;
1181
1182 IWL_DEBUG_CALIB("norm FA %u < min FA %u, silence diff %d\n",
1183 false_alarms, min_false_alarms,
1184 data->nrg_auto_corr_silence_diff);
1185
1186 /* Increase value to increase sensitivity, but only if:
1187 * 1a) previous beacon did *not* have *too many* false alarms
1188 * 1b) AND there's a significant difference in Rx levels
1189 * from a previous beacon with too many, or healthy # FAs
1190 * OR 2) We've seen a lot of beacons (100) with too few
1191 * false alarms */
1192 if ((data->nrg_prev_state != IWL_FA_TOO_MANY) &&
1193 ((data->nrg_auto_corr_silence_diff > NRG_DIFF) ||
1194 (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) {
1195
1196 IWL_DEBUG_CALIB("... increasing sensitivity\n");
1197 /* Increase nrg value to increase sensitivity */
1198 val = data->nrg_th_cck + NRG_STEP_CCK;
1199 data->nrg_th_cck = min((u32)NRG_MIN_CCK, val);
1200
1201 /* Decrease auto_corr values to increase sensitivity */
1202 val = data->auto_corr_cck - AUTO_CORR_STEP_CCK;
1203 data->auto_corr_cck = max((u32)AUTO_CORR_MIN_CCK, val);
1204
1205 val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK;
1206 data->auto_corr_cck_mrc =
1207 max((u32)AUTO_CORR_MIN_CCK_MRC, val);
1208
1209 } else
1210 IWL_DEBUG_CALIB("... but not changing sensitivity\n");
1211
1212 /* Else we got a healthy number of false alarms, keep status quo */
1213 } else {
1214 IWL_DEBUG_CALIB(" FA in safe zone\n");
1215 data->nrg_curr_state = IWL_FA_GOOD_RANGE;
1216
1217 /* Store for use in "fewer than desired" with later beacon */
1218 data->nrg_silence_ref = silence_ref;
1219
1220 /* If previous beacon had too many false alarms,
1221 * give it some extra margin by reducing sensitivity again
1222 * (but don't go below measured energy of desired Rx) */
1223 if (IWL_FA_TOO_MANY == data->nrg_prev_state) {
1224 IWL_DEBUG_CALIB("... increasing margin\n");
1225 data->nrg_th_cck -= NRG_MARGIN;
1226 }
1227 }
1228
1229 /* Make sure the energy threshold does not go above the measured
1230 * energy of the desired Rx signals (reduced by backoff margin),
1231 * or else we might start missing Rx frames.
1232 * Lower value is higher energy, so we use max()!
1233 */
1234 data->nrg_th_cck = max(max_nrg_cck, data->nrg_th_cck);
1235 IWL_DEBUG_CALIB("new nrg_th_cck %u\n", data->nrg_th_cck);
1236
1237 data->nrg_prev_state = data->nrg_curr_state;
1238
1239 return 0;
1240}
1241
1242
c79dd5b5 1243static int iwl4965_sens_auto_corr_ofdm(struct iwl_priv *priv,
b481de9c
ZY		 1244 u32 norm_fa,
1245 u32 rx_enable_time)
1246{
1247 u32 val;
1248 u32 false_alarms = norm_fa * 200 * 1024;
1249 u32 max_false_alarms = MAX_FA_OFDM * rx_enable_time;
1250 u32 min_false_alarms = MIN_FA_OFDM * rx_enable_time;
bb8c093b 1251 struct iwl4965_sensitivity_data *data = NULL;
b481de9c
ZY		 1252
1253 data = &(priv->sensitivity_data);
1254
1255 /* If we got too many false alarms this time, reduce sensitivity */
1256 if (false_alarms > max_false_alarms) {
1257
1258 IWL_DEBUG_CALIB("norm FA %u > max FA %u)\n",
1259 false_alarms, max_false_alarms);
1260
1261 val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM;
1262 data->auto_corr_ofdm =
1263 min((u32)AUTO_CORR_MAX_OFDM, val);
1264
1265 val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM;
1266 data->auto_corr_ofdm_mrc =
1267 min((u32)AUTO_CORR_MAX_OFDM_MRC, val);
1268
1269 val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM;
1270 data->auto_corr_ofdm_x1 =
1271 min((u32)AUTO_CORR_MAX_OFDM_X1, val);
1272
1273 val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM;
1274 data->auto_corr_ofdm_mrc_x1 =
1275 min((u32)AUTO_CORR_MAX_OFDM_MRC_X1, val);
1276 }
1277
1278 /* Else if we got fewer than desired, increase sensitivity */
1279 else if (false_alarms < min_false_alarms) {
1280
1281 IWL_DEBUG_CALIB("norm FA %u < min FA %u\n",
1282 false_alarms, min_false_alarms);
1283
1284 val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM;
1285 data->auto_corr_ofdm =
1286 max((u32)AUTO_CORR_MIN_OFDM, val);
1287
1288 val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM;
1289 data->auto_corr_ofdm_mrc =
1290 max((u32)AUTO_CORR_MIN_OFDM_MRC, val);
1291
1292 val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM;
1293 data->auto_corr_ofdm_x1 =
1294 max((u32)AUTO_CORR_MIN_OFDM_X1, val);
1295
1296 val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM;
1297 data->auto_corr_ofdm_mrc_x1 =
1298 max((u32)AUTO_CORR_MIN_OFDM_MRC_X1, val);
1299 }
1300
1301 else
1302 IWL_DEBUG_CALIB("min FA %u < norm FA %u < max FA %u OK\n",
1303 min_false_alarms, false_alarms, max_false_alarms);
1304
1305 return 0;
1306}
1307
c79dd5b5 1308static int iwl4965_sensitivity_callback(struct iwl_priv *priv,
857485c0 1309 struct iwl_cmd *cmd, struct sk_buff *skb)
b481de9c
ZY		 1310{
1311 /* We didn't cache the SKB; let the caller free it */
1312 return 1;
1313}
1314
1315/* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */
c79dd5b5 1316static int iwl4965_sensitivity_write(struct iwl_priv *priv, u8 flags)
b481de9c 1317{
bb8c093b
CH		 1318 struct iwl4965_sensitivity_cmd cmd ;
1319 struct iwl4965_sensitivity_data *data = NULL;
857485c0 1320 struct iwl_host_cmd cmd_out = {
b481de9c 1321 .id = SENSITIVITY_CMD,
bb8c093b 1322 .len = sizeof(struct iwl4965_sensitivity_cmd),
b481de9c
ZY		 1323 .meta.flags = flags,
1324 .data = &cmd,
1325 };
857485c0 1326 int ret;
b481de9c
ZY		 1327
1328 data = &(priv->sensitivity_data);
1329
1330 memset(&cmd, 0, sizeof(cmd));
1331
1332 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX] =
1333 cpu_to_le16((u16)data->auto_corr_ofdm);
1334 cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX] =
1335 cpu_to_le16((u16)data->auto_corr_ofdm_mrc);
1336 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX] =
1337 cpu_to_le16((u16)data->auto_corr_ofdm_x1);
1338 cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX] =
1339 cpu_to_le16((u16)data->auto_corr_ofdm_mrc_x1);
1340
1341 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX] =
1342 cpu_to_le16((u16)data->auto_corr_cck);
1343 cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX] =
1344 cpu_to_le16((u16)data->auto_corr_cck_mrc);
1345
1346 cmd.table[HD_MIN_ENERGY_CCK_DET_INDEX] =
1347 cpu_to_le16((u16)data->nrg_th_cck);
1348 cmd.table[HD_MIN_ENERGY_OFDM_DET_INDEX] =
1349 cpu_to_le16((u16)data->nrg_th_ofdm);
1350
1351 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_INDEX] =
1352 __constant_cpu_to_le16(190);
1353 cmd.table[HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX] =
1354 __constant_cpu_to_le16(390);
1355 cmd.table[HD_OFDM_ENERGY_TH_IN_INDEX] =
1356 __constant_cpu_to_le16(62);
1357
1358 IWL_DEBUG_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n",
1359 data->auto_corr_ofdm, data->auto_corr_ofdm_mrc,
1360 data->auto_corr_ofdm_x1, data->auto_corr_ofdm_mrc_x1,
1361 data->nrg_th_ofdm);
1362
1363 IWL_DEBUG_CALIB("cck: ac %u mrc %u thresh %u\n",
1364 data->auto_corr_cck, data->auto_corr_cck_mrc,
1365 data->nrg_th_cck);
1366
f7d09d7c 1367 /* Update uCode's "work" table, and copy it to DSP */
b481de9c
ZY		 1368 cmd.control = SENSITIVITY_CMD_CONTROL_WORK_TABLE;
1369
1370 if (flags & CMD_ASYNC)
bb8c093b 1371 cmd_out.meta.u.callback = iwl4965_sensitivity_callback;
b481de9c
ZY		 1372
1373 /* Don't send command to uCode if nothing has changed */
1374 if (!memcmp(&cmd.table[0], &(priv->sensitivity_tbl[0]),
1375 sizeof(u16)*HD_TABLE_SIZE)) {
1376 IWL_DEBUG_CALIB("No change in SENSITIVITY_CMD\n");
1377 return 0;
1378 }
1379
1380 /* Copy table for comparison next time */
1381 memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]),
1382 sizeof(u16)*HD_TABLE_SIZE);
1383
857485c0
TW		 1384 ret = iwl_send_cmd(priv, &cmd_out);
1385 if (ret)
1386 IWL_ERROR("SENSITIVITY_CMD failed\n");
b481de9c 1387
857485c0 1388 return ret;
b481de9c
ZY		 1389}
1390
c79dd5b5 1391void iwl4965_init_sensitivity(struct iwl_priv *priv, u8 flags, u8 force)
b481de9c 1392{
bb8c093b 1393 struct iwl4965_sensitivity_data *data = NULL;
857485c0
TW		 1394 int i;
1395 int ret = 0;
b481de9c
ZY		 1396
1397 IWL_DEBUG_CALIB("Start iwl4965_init_sensitivity\n");
1398
1399 if (force)
1400 memset(&(priv->sensitivity_tbl[0]), 0,
1401 sizeof(u16)*HD_TABLE_SIZE);
1402
1403 /* Clear driver's sensitivity algo data */
1404 data = &(priv->sensitivity_data);
bb8c093b 1405 memset(data, 0, sizeof(struct iwl4965_sensitivity_data));
b481de9c
ZY		 1406
1407 data->num_in_cck_no_fa = 0;
1408 data->nrg_curr_state = IWL_FA_TOO_MANY;
1409 data->nrg_prev_state = IWL_FA_TOO_MANY;
1410 data->nrg_silence_ref = 0;
1411 data->nrg_silence_idx = 0;
1412 data->nrg_energy_idx = 0;
1413
1414 for (i = 0; i < 10; i++)
1415 data->nrg_value[i] = 0;
1416
1417 for (i = 0; i < NRG_NUM_PREV_STAT_L; i++)
1418 data->nrg_silence_rssi[i] = 0;
1419
1420 data->auto_corr_ofdm = 90;
1421 data->auto_corr_ofdm_mrc = 170;
1422 data->auto_corr_ofdm_x1 = 105;
1423 data->auto_corr_ofdm_mrc_x1 = 220;
1424 data->auto_corr_cck = AUTO_CORR_CCK_MIN_VAL_DEF;
1425 data->auto_corr_cck_mrc = 200;
1426 data->nrg_th_cck = 100;
1427 data->nrg_th_ofdm = 100;
1428
1429 data->last_bad_plcp_cnt_ofdm = 0;
1430 data->last_fa_cnt_ofdm = 0;
1431 data->last_bad_plcp_cnt_cck = 0;
1432 data->last_fa_cnt_cck = 0;
1433
1434 /* Clear prior Sensitivity command data to force send to uCode */
1435 if (force)
1436 memset(&(priv->sensitivity_tbl[0]), 0,
1437 sizeof(u16)*HD_TABLE_SIZE);
1438
857485c0
TW		 1439 ret |= iwl4965_sensitivity_write(priv, flags);
1440 IWL_DEBUG_CALIB("<<return 0x%X\n", ret);
b481de9c
ZY		 1441
1442 return;
1443}
1444
1445
1446/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
1447 * Called after every association, but this runs only once!
1448 * ... once chain noise is calibrated the first time, it's good forever. */
c79dd5b5 1449void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 1450{
bb8c093b 1451 struct iwl4965_chain_noise_data *data = NULL;
b481de9c
ZY		 1452
1453 data = &(priv->chain_noise_data);
3109ece1 1454 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
bb8c093b 1455 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 1456
1457 memset(&cmd, 0, sizeof(cmd));
1458 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1459 cmd.diff_gain_a = 0;
1460 cmd.diff_gain_b = 0;
1461 cmd.diff_gain_c = 0;
e5472978
TW		 1462 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
1463 sizeof(cmd), &cmd, NULL);
b481de9c
ZY		 1464 msleep(4);
1465 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
1466 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
1467 }
1468 return;
1469}
1470
1471/*
1472 * Accumulate 20 beacons of signal and noise statistics for each of
1473 * 3 receivers/antennas/rx-chains, then figure out:
1474 * 1) Which antennas are connected.
1475 * 2) Differential rx gain settings to balance the 3 receivers.
1476 */
c79dd5b5 1477static void iwl4965_noise_calibration(struct iwl_priv *priv,
bb8c093b 1478 struct iwl4965_notif_statistics *stat_resp)
b481de9c 1479{
bb8c093b 1480 struct iwl4965_chain_noise_data *data = NULL;
857485c0 1481 int ret = 0;
b481de9c
ZY		 1482
1483 u32 chain_noise_a;
1484 u32 chain_noise_b;
1485 u32 chain_noise_c;
1486 u32 chain_sig_a;
1487 u32 chain_sig_b;
1488 u32 chain_sig_c;
1489 u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
1490 u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
1491 u32 max_average_sig;
1492 u16 max_average_sig_antenna_i;
1493 u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE;
1494 u16 min_average_noise_antenna_i = INITIALIZATION_VALUE;
1495 u16 i = 0;
1496 u16 chan_num = INITIALIZATION_VALUE;
1497 u32 band = INITIALIZATION_VALUE;
1498 u32 active_chains = 0;
1499 unsigned long flags;
1500 struct statistics_rx_non_phy *rx_info = &(stat_resp->rx.general);
1501
1502 data = &(priv->chain_noise_data);
1503
1504 /* Accumulate just the first 20 beacons after the first association,
1505 * then we're done forever. */
1506 if (data->state != IWL_CHAIN_NOISE_ACCUMULATE) {
1507 if (data->state == IWL_CHAIN_NOISE_ALIVE)
1508 IWL_DEBUG_CALIB("Wait for noise calib reset\n");
1509 return;
1510 }
1511
1512 spin_lock_irqsave(&priv->lock, flags);
1513 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
1514 IWL_DEBUG_CALIB(" << Interference data unavailable\n");
1515 spin_unlock_irqrestore(&priv->lock, flags);
1516 return;
1517 }
1518
1519 band = (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) ? 0 : 1;
1520 chan_num = le16_to_cpu(priv->staging_rxon.channel);
1521
1522 /* Make sure we accumulate data for just the associated channel
1523 * (even if scanning). */
1524 if ((chan_num != (le32_to_cpu(stat_resp->flag) >> 16)) ||
1525 ((STATISTICS_REPLY_FLG_BAND_24G_MSK ==
1526 (stat_resp->flag & STATISTICS_REPLY_FLG_BAND_24G_MSK)) && band)) {
1527 IWL_DEBUG_CALIB("Stats not from chan=%d, band=%d\n",
1528 chan_num, band);
1529 spin_unlock_irqrestore(&priv->lock, flags);
1530 return;
1531 }
1532
1533 /* Accumulate beacon statistics values across 20 beacons */
1534 chain_noise_a = le32_to_cpu(rx_info->beacon_silence_rssi_a) &
1535 IN_BAND_FILTER;
1536 chain_noise_b = le32_to_cpu(rx_info->beacon_silence_rssi_b) &
1537 IN_BAND_FILTER;
1538 chain_noise_c = le32_to_cpu(rx_info->beacon_silence_rssi_c) &
1539 IN_BAND_FILTER;
1540
1541 chain_sig_a = le32_to_cpu(rx_info->beacon_rssi_a) & IN_BAND_FILTER;
1542 chain_sig_b = le32_to_cpu(rx_info->beacon_rssi_b) & IN_BAND_FILTER;
1543 chain_sig_c = le32_to_cpu(rx_info->beacon_rssi_c) & IN_BAND_FILTER;
1544
1545 spin_unlock_irqrestore(&priv->lock, flags);
1546
1547 data->beacon_count++;
1548
1549 data->chain_noise_a = (chain_noise_a + data->chain_noise_a);
1550 data->chain_noise_b = (chain_noise_b + data->chain_noise_b);
1551 data->chain_noise_c = (chain_noise_c + data->chain_noise_c);
1552
1553 data->chain_signal_a = (chain_sig_a + data->chain_signal_a);
1554 data->chain_signal_b = (chain_sig_b + data->chain_signal_b);
1555 data->chain_signal_c = (chain_sig_c + data->chain_signal_c);
1556
1557 IWL_DEBUG_CALIB("chan=%d, band=%d, beacon=%d\n", chan_num, band,
1558 data->beacon_count);
1559 IWL_DEBUG_CALIB("chain_sig: a %d b %d c %d\n",
1560 chain_sig_a, chain_sig_b, chain_sig_c);
1561 IWL_DEBUG_CALIB("chain_noise: a %d b %d c %d\n",
1562 chain_noise_a, chain_noise_b, chain_noise_c);
1563
1564 /* If this is the 20th beacon, determine:
1565 * 1) Disconnected antennas (using signal strengths)
1566 * 2) Differential gain (using silence noise) to balance receivers */
1567 if (data->beacon_count == CAL_NUM_OF_BEACONS) {
1568
1569 /* Analyze signal for disconnected antenna */
1570 average_sig[0] = (data->chain_signal_a) / CAL_NUM_OF_BEACONS;
1571 average_sig[1] = (data->chain_signal_b) / CAL_NUM_OF_BEACONS;
1572 average_sig[2] = (data->chain_signal_c) / CAL_NUM_OF_BEACONS;
1573
1574 if (average_sig[0] >= average_sig[1]) {
1575 max_average_sig = average_sig[0];
1576 max_average_sig_antenna_i = 0;
1577 active_chains = (1 << max_average_sig_antenna_i);
1578 } else {
1579 max_average_sig = average_sig[1];
1580 max_average_sig_antenna_i = 1;
1581 active_chains = (1 << max_average_sig_antenna_i);
1582 }
1583
1584 if (average_sig[2] >= max_average_sig) {
1585 max_average_sig = average_sig[2];
1586 max_average_sig_antenna_i = 2;
1587 active_chains = (1 << max_average_sig_antenna_i);
1588 }
1589
1590 IWL_DEBUG_CALIB("average_sig: a %d b %d c %d\n",
1591 average_sig[0], average_sig[1], average_sig[2]);
1592 IWL_DEBUG_CALIB("max_average_sig = %d, antenna %d\n",
1593 max_average_sig, max_average_sig_antenna_i);
1594
1595 /* Compare signal strengths for all 3 receivers. */
1596 for (i = 0; i < NUM_RX_CHAINS; i++) {
1597 if (i != max_average_sig_antenna_i) {
1598 s32 rssi_delta = (max_average_sig -
1599 average_sig[i]);
1600
1601 /* If signal is very weak, compared with
1602 * strongest, mark it as disconnected. */
1603 if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
1604 data->disconn_array[i] = 1;
1605 else
1606 active_chains |= (1 << i);
1607 IWL_DEBUG_CALIB("i = %d rssiDelta = %d "
1608 "disconn_array[i] = %d\n",
1609 i, rssi_delta, data->disconn_array[i]);
1610 }
1611 }
1612
1613 /*If both chains A & B are disconnected -
1614 * connect B and leave A as is */
1615 if (data->disconn_array[CHAIN_A] &&
1616 data->disconn_array[CHAIN_B]) {
1617 data->disconn_array[CHAIN_B] = 0;
1618 active_chains |= (1 << CHAIN_B);
1619 IWL_DEBUG_CALIB("both A & B chains are disconnected! "
1620 "W/A - declare B as connected\n");
1621 }
1622
1623 IWL_DEBUG_CALIB("active_chains (bitwise) = 0x%x\n",
1624 active_chains);
1625
1626 /* Save for use within RXON, TX, SCAN commands, etc. */
1627 priv->valid_antenna = active_chains;
1628
1629 /* Analyze noise for rx balance */
1630 average_noise[0] = ((data->chain_noise_a)/CAL_NUM_OF_BEACONS);
1631 average_noise[1] = ((data->chain_noise_b)/CAL_NUM_OF_BEACONS);
1632 average_noise[2] = ((data->chain_noise_c)/CAL_NUM_OF_BEACONS);
1633
1634 for (i = 0; i < NUM_RX_CHAINS; i++) {
1635 if (!(data->disconn_array[i]) &&
1636 (average_noise[i] <= min_average_noise)) {
1637 /* This means that chain i is active and has
1638 * lower noise values so far: */
1639 min_average_noise = average_noise[i];
1640 min_average_noise_antenna_i = i;
1641 }
1642 }
1643
1644 data->delta_gain_code[min_average_noise_antenna_i] = 0;
1645
1646 IWL_DEBUG_CALIB("average_noise: a %d b %d c %d\n",
1647 average_noise[0], average_noise[1],
1648 average_noise[2]);
1649
1650 IWL_DEBUG_CALIB("min_average_noise = %d, antenna %d\n",
1651 min_average_noise, min_average_noise_antenna_i);
1652
1653 for (i = 0; i < NUM_RX_CHAINS; i++) {
1654 s32 delta_g = 0;
1655
1656 if (!(data->disconn_array[i]) &&
1657 (data->delta_gain_code[i] ==
1658 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
1659 delta_g = average_noise[i] - min_average_noise;
1660 data->delta_gain_code[i] = (u8)((delta_g *
1661 10) / 15);
1662 if (CHAIN_NOISE_MAX_DELTA_GAIN_CODE <
1663 data->delta_gain_code[i])
1664 data->delta_gain_code[i] =
1665 CHAIN_NOISE_MAX_DELTA_GAIN_CODE;
1666
1667 data->delta_gain_code[i] =
1668 (data->delta_gain_code[i] | (1 << 2));
1669 } else
1670 data->delta_gain_code[i] = 0;
1671 }
1672 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
1673 data->delta_gain_code[0],
1674 data->delta_gain_code[1],
1675 data->delta_gain_code[2]);
1676
1677 /* Differential gain gets sent to uCode only once */
1678 if (!data->radio_write) {
bb8c093b 1679 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 1680 data->radio_write = 1;
1681
1682 memset(&cmd, 0, sizeof(cmd));
1683 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1684 cmd.diff_gain_a = data->delta_gain_code[0];
1685 cmd.diff_gain_b = data->delta_gain_code[1];
1686 cmd.diff_gain_c = data->delta_gain_code[2];
857485c0 1687 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
b481de9c 1688 sizeof(cmd), &cmd);
857485c0 1689 if (ret)
b481de9c
ZY		 1690 IWL_DEBUG_CALIB("fail sending cmd "
1691 "REPLY_PHY_CALIBRATION_CMD \n");
1692
1693 /* TODO we might want recalculate
1694 * rx_chain in rxon cmd */
1695
1696 /* Mark so we run this algo only once! */
1697 data->state = IWL_CHAIN_NOISE_CALIBRATED;
1698 }
1699 data->chain_noise_a = 0;
1700 data->chain_noise_b = 0;
1701 data->chain_noise_c = 0;
1702 data->chain_signal_a = 0;
1703 data->chain_signal_b = 0;
1704 data->chain_signal_c = 0;
1705 data->beacon_count = 0;
1706 }
1707 return;
1708}
1709
c79dd5b5 1710static void iwl4965_sensitivity_calibration(struct iwl_priv *priv,
bb8c093b 1711 struct iwl4965_notif_statistics *resp)
b481de9c 1712{
b481de9c
ZY		 1713 u32 rx_enable_time;
1714 u32 fa_cck;
1715 u32 fa_ofdm;
1716 u32 bad_plcp_cck;
1717 u32 bad_plcp_ofdm;
1718 u32 norm_fa_ofdm;
1719 u32 norm_fa_cck;
bb8c093b 1720 struct iwl4965_sensitivity_data *data = NULL;
b481de9c
ZY		 1721 struct statistics_rx_non_phy *rx_info = &(resp->rx.general);
1722 struct statistics_rx *statistics = &(resp->rx);
1723 unsigned long flags;
1724 struct statistics_general_data statis;
857485c0 1725 int ret;
b481de9c
ZY		 1726
1727 data = &(priv->sensitivity_data);
1728
3109ece1 1729 if (!iwl_is_associated(priv)) {
b481de9c
ZY		 1730 IWL_DEBUG_CALIB("<< - not associated\n");
1731 return;
1732 }
1733
1734 spin_lock_irqsave(&priv->lock, flags);
1735 if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
1736 IWL_DEBUG_CALIB("<< invalid data.\n");
1737 spin_unlock_irqrestore(&priv->lock, flags);
1738 return;
1739 }
1740
1741 /* Extract Statistics: */
1742 rx_enable_time = le32_to_cpu(rx_info->channel_load);
1743 fa_cck = le32_to_cpu(statistics->cck.false_alarm_cnt);
1744 fa_ofdm = le32_to_cpu(statistics->ofdm.false_alarm_cnt);
1745 bad_plcp_cck = le32_to_cpu(statistics->cck.plcp_err);
1746 bad_plcp_ofdm = le32_to_cpu(statistics->ofdm.plcp_err);
1747
1748 statis.beacon_silence_rssi_a =
1749 le32_to_cpu(statistics->general.beacon_silence_rssi_a);
1750 statis.beacon_silence_rssi_b =
1751 le32_to_cpu(statistics->general.beacon_silence_rssi_b);
1752 statis.beacon_silence_rssi_c =
1753 le32_to_cpu(statistics->general.beacon_silence_rssi_c);
1754 statis.beacon_energy_a =
1755 le32_to_cpu(statistics->general.beacon_energy_a);
1756 statis.beacon_energy_b =
1757 le32_to_cpu(statistics->general.beacon_energy_b);
1758 statis.beacon_energy_c =
1759 le32_to_cpu(statistics->general.beacon_energy_c);
1760
1761 spin_unlock_irqrestore(&priv->lock, flags);
1762
1763 IWL_DEBUG_CALIB("rx_enable_time = %u usecs\n", rx_enable_time);
1764
1765 if (!rx_enable_time) {
1766 IWL_DEBUG_CALIB("<< RX Enable Time == 0! \n");
1767 return;
1768 }
1769
1770 /* These statistics increase monotonically, and do not reset
1771 * at each beacon. Calculate difference from last value, or just
1772 * use the new statistics value if it has reset or wrapped around. */
1773 if (data->last_bad_plcp_cnt_cck > bad_plcp_cck)
1774 data->last_bad_plcp_cnt_cck = bad_plcp_cck;
1775 else {
1776 bad_plcp_cck -= data->last_bad_plcp_cnt_cck;
1777 data->last_bad_plcp_cnt_cck += bad_plcp_cck;
1778 }
1779
1780 if (data->last_bad_plcp_cnt_ofdm > bad_plcp_ofdm)
1781 data->last_bad_plcp_cnt_ofdm = bad_plcp_ofdm;
1782 else {
1783 bad_plcp_ofdm -= data->last_bad_plcp_cnt_ofdm;
1784 data->last_bad_plcp_cnt_ofdm += bad_plcp_ofdm;
1785 }
1786
1787 if (data->last_fa_cnt_ofdm > fa_ofdm)
1788 data->last_fa_cnt_ofdm = fa_ofdm;
1789 else {
1790 fa_ofdm -= data->last_fa_cnt_ofdm;
1791 data->last_fa_cnt_ofdm += fa_ofdm;
1792 }
1793
1794 if (data->last_fa_cnt_cck > fa_cck)
1795 data->last_fa_cnt_cck = fa_cck;
1796 else {
1797 fa_cck -= data->last_fa_cnt_cck;
1798 data->last_fa_cnt_cck += fa_cck;
1799 }
1800
1801 /* Total aborted signal locks */
1802 norm_fa_ofdm = fa_ofdm + bad_plcp_ofdm;
1803 norm_fa_cck = fa_cck + bad_plcp_cck;
1804
1805 IWL_DEBUG_CALIB("cck: fa %u badp %u ofdm: fa %u badp %u\n", fa_cck,
1806 bad_plcp_cck, fa_ofdm, bad_plcp_ofdm);
1807
1808 iwl4965_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time);
1809 iwl4965_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis);
857485c0 1810 ret = iwl4965_sensitivity_write(priv, CMD_ASYNC);
b481de9c
ZY		 1811
1812 return;
1813}
1814
1815static void iwl4965_bg_sensitivity_work(struct work_struct *work)
1816{
c79dd5b5 1817 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1818 sensitivity_work);
1819
1820 mutex_lock(&priv->mutex);
1821
1822 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1823 test_bit(STATUS_SCANNING, &priv->status)) {
1824 mutex_unlock(&priv->mutex);
1825 return;
1826 }
1827
1828 if (priv->start_calib) {
1829 iwl4965_noise_calibration(priv, &priv->statistics);
1830
1831 if (priv->sensitivity_data.state ==
1832 IWL_SENS_CALIB_NEED_REINIT) {
1833 iwl4965_init_sensitivity(priv, CMD_ASYNC, 0);
1834 priv->sensitivity_data.state = IWL_SENS_CALIB_ALLOWED;
1835 } else
1836 iwl4965_sensitivity_calibration(priv,
1837 &priv->statistics);
1838 }
1839
1840 mutex_unlock(&priv->mutex);
1841 return;
1842}
c8b0e6e1 1843#endif /*CONFIG_IWL4965_SENSITIVITY*/
b481de9c
ZY		 1844
1845static void iwl4965_bg_txpower_work(struct work_struct *work)
1846{
c79dd5b5 1847 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 1848 txpower_work);
1849
1850 /* If a scan happened to start before we got here
1851 * then just return; the statistics notification will
1852 * kick off another scheduled work to compensate for
1853 * any temperature delta we missed here. */
1854 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1855 test_bit(STATUS_SCANNING, &priv->status))
1856 return;
1857
1858 mutex_lock(&priv->mutex);
1859
1860 /* Regardless of if we are assocaited, we must reconfigure the
1861 * TX power since frames can be sent on non-radar channels while
1862 * not associated */
bb8c093b 1863 iwl4965_hw_reg_send_txpower(priv);
b481de9c
ZY		 1864
1865 /* Update last_temperature to keep is_calib_needed from running
1866 * when it isn't needed... */
1867 priv->last_temperature = priv->temperature;
1868
1869 mutex_unlock(&priv->mutex);
1870}
1871
1872/*
1873 * Acquire priv->lock before calling this function !
1874 */
c79dd5b5 1875static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 1876{
3395f6e9 1877 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 1878 (index & 0xff) | (txq_id << 8));
12a81f60 1879 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 1880}
1881
8b6eaea8
CB		 1882/**
1883 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
1884 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
1885 * @scd_retry: (1) Indicates queue will be used in aggregation mode
1886 *
1887 * NOTE: Acquire priv->lock before calling this function !
b481de9c 1888 */
c79dd5b5 1889static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
bb8c093b 1890 struct iwl4965_tx_queue *txq,
b481de9c
ZY		 1891 int tx_fifo_id, int scd_retry)
1892{
1893 int txq_id = txq->q.id;
8b6eaea8
CB		 1894
1895 /* Find out whether to activate Tx queue */
b481de9c
ZY		 1896 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1897
8b6eaea8 1898 /* Set up and activate */
12a81f60 1899 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
b481de9c
ZY		 1900 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1901 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1902 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
1903 (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1904 SCD_QUEUE_STTS_REG_MSK);
1905
1906 txq->sched_retry = scd_retry;
1907
1908 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
8b6eaea8 1909 active ? "Activate" : "Deactivate",
b481de9c
ZY		 1910 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1911}
1912
1913static const u16 default_queue_to_tx_fifo[] = {
1914 IWL_TX_FIFO_AC3,
1915 IWL_TX_FIFO_AC2,
1916 IWL_TX_FIFO_AC1,
1917 IWL_TX_FIFO_AC0,
1918 IWL_CMD_FIFO_NUM,
1919 IWL_TX_FIFO_HCCA_1,
1920 IWL_TX_FIFO_HCCA_2
1921};
1922
c79dd5b5 1923static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1924{
1925 set_bit(txq_id, &priv->txq_ctx_active_msk);
1926}
1927
c79dd5b5 1928static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
b481de9c
ZY		 1929{
1930 clear_bit(txq_id, &priv->txq_ctx_active_msk);
1931}
1932
c79dd5b5 1933int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 1934{
1935 u32 a;
1936 int i = 0;
1937 unsigned long flags;
857485c0 1938 int ret;
b481de9c
ZY		 1939
1940 spin_lock_irqsave(&priv->lock, flags);
1941
c8b0e6e1 1942#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c 1943 memset(&(priv->sensitivity_data), 0,
bb8c093b 1944 sizeof(struct iwl4965_sensitivity_data));
b481de9c 1945 memset(&(priv->chain_noise_data), 0,
bb8c093b 1946 sizeof(struct iwl4965_chain_noise_data));
b481de9c
ZY		 1947 for (i = 0; i < NUM_RX_CHAINS; i++)
1948 priv->chain_noise_data.delta_gain_code[i] =
1949 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
c8b0e6e1 1950#endif /* CONFIG_IWL4965_SENSITIVITY*/
3395f6e9 1951 ret = iwl_grab_nic_access(priv);
857485c0 1952 if (ret) {
b481de9c 1953 spin_unlock_irqrestore(&priv->lock, flags);
857485c0 1954 return ret;
b481de9c
ZY		 1955 }
1956
8b6eaea8 1957 /* Clear 4965's internal Tx Scheduler data base */
12a81f60 1958 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
b481de9c
ZY		 1959 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1960 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
3395f6e9 1961 iwl_write_targ_mem(priv, a, 0);
b481de9c 1962 for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
3395f6e9 1963 iwl_write_targ_mem(priv, a, 0);
b481de9c 1964 for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
3395f6e9 1965 iwl_write_targ_mem(priv, a, 0);
b481de9c 1966
8b6eaea8 1967 /* Tel 4965 where to find Tx byte count tables */
12a81f60 1968 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
b481de9c 1969 (priv->hw_setting.shared_phys +
bb8c093b 1970 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
8b6eaea8
CB		 1971
1972 /* Disable chain mode for all queues */
12a81f60 1973 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
b481de9c 1974
8b6eaea8 1975 /* Initialize each Tx queue (including the command queue) */
b481de9c 1976 for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
8b6eaea8
CB		 1977
1978 /* TFD circular buffer read/write indexes */
12a81f60 1979 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
3395f6e9 1980 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
CB		 1981
1982 /* Max Tx Window size for Scheduler-ACK mode */
3395f6e9 1983 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1984 SCD_CONTEXT_QUEUE_OFFSET(i),
1985 (SCD_WIN_SIZE <<
1986 SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1987 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
CB		 1988
1989 /* Frame limit */
3395f6e9 1990 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 1991 SCD_CONTEXT_QUEUE_OFFSET(i) +
1992 sizeof(u32),
1993 (SCD_FRAME_LIMIT <<
1994 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1995 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1996
1997 }
12a81f60 1998 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
b481de9c
ZY		 1999 (1 << priv->hw_setting.max_txq_num) - 1);
2000
8b6eaea8 2001 /* Activate all Tx DMA/FIFO channels */
12a81f60 2002 iwl_write_prph(priv, IWL49_SCD_TXFACT,
b481de9c
ZY		 2003 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
2004
2005 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
CB		 2006
2007 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 2008 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
2009 int ac = default_queue_to_tx_fifo[i];
2010 iwl4965_txq_ctx_activate(priv, i);
2011 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
2012 }
2013
3395f6e9 2014 iwl_release_nic_access(priv);
b481de9c
ZY		 2015 spin_unlock_irqrestore(&priv->lock, flags);
2016
857485c0 2017 return ret;
b481de9c
ZY		 2018}
2019
8b6eaea8
CB		 2020/**
2021 * iwl4965_hw_set_hw_setting
2022 *
2023 * Called when initializing driver
2024 */
c79dd5b5 2025int iwl4965_hw_set_hw_setting(struct iwl_priv *priv)
b481de9c 2026{
316c30d9
AK		 2027 int ret = 0;
2028
1ea87396
AK		 2029 if ((priv->cfg->mod_params->num_of_queues > IWL_MAX_NUM_QUEUES) ||
2030 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
316c30d9
AK		 2031 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
2032 IWL_MIN_NUM_QUEUES, IWL_MAX_NUM_QUEUES);
2033 ret = -EINVAL;
2034 goto out;
2035 }
2036
8b6eaea8 2037 /* Allocate area for Tx byte count tables and Rx queue status */
b481de9c
ZY		 2038 priv->hw_setting.shared_virt =
2039 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2040 sizeof(struct iwl4965_shared),
b481de9c
ZY		 2041 &priv->hw_setting.shared_phys);
2042
316c30d9
AK		 2043 if (!priv->hw_setting.shared_virt) {
2044 ret = -ENOMEM;
2045 goto out;
2046 }
b481de9c 2047
bb8c093b 2048 memset(priv->hw_setting.shared_virt, 0, sizeof(struct iwl4965_shared));
b481de9c 2049
1ea87396 2050 priv->hw_setting.max_txq_num = priv->cfg->mod_params->num_of_queues;
bb8c093b 2051 priv->hw_setting.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
b481de9c
ZY		 2052 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
2053 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
1ea87396 2054 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47
RR		 2055 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_8K;
2056 else
2057 priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_4K;
2058 priv->hw_setting.max_pkt_size = priv->hw_setting.rx_buf_size - 256;
b481de9c
ZY		 2059 priv->hw_setting.max_stations = IWL4965_STATION_COUNT;
2060 priv->hw_setting.bcast_sta_id = IWL4965_BROADCAST_ID;
3e82a822
TW		 2061
2062 priv->hw_setting.tx_ant_num = 2;
2063
316c30d9
AK		 2064out:
2065 return ret;
b481de9c
ZY		 2066}
2067
2068/**
bb8c093b 2069 * iwl4965_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 2070 *
2071 * Destroy all TX DMA queues and structures
2072 */
c79dd5b5 2073void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 2074{
2075 int txq_id;
2076
2077 /* Tx queues */
2078 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
bb8c093b 2079 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
b481de9c 2080
8b6eaea8 2081 /* Keep-warm buffer */
b481de9c
ZY		 2082 iwl4965_kw_free(priv);
2083}
2084
2085/**
8b6eaea8 2086 * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
b481de9c 2087 *
8b6eaea8
CB		 2088 * Does NOT advance any TFD circular buffer read/write indexes
2089 * Does NOT free the TFD itself (which is within circular buffer)
b481de9c 2090 */
c79dd5b5 2091int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c 2092{
bb8c093b
CH		 2093 struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
2094 struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 2095 struct pci_dev *dev = priv->pci_dev;
2096 int i;
2097 int counter = 0;
2098 int index, is_odd;
2099
8b6eaea8 2100 /* Host command buffers stay mapped in memory, nothing to clean */
b481de9c 2101 if (txq->q.id == IWL_CMD_QUEUE_NUM)
b481de9c
ZY		 2102 return 0;
2103
8b6eaea8 2104 /* Sanity check on number of chunks */
b481de9c
ZY		 2105 counter = IWL_GET_BITS(*bd, num_tbs);
2106 if (counter > MAX_NUM_OF_TBS) {
2107 IWL_ERROR("Too many chunks: %i\n", counter);
2108 /* @todo issue fatal error, it is quite serious situation */
2109 return 0;
2110 }
2111
8b6eaea8
CB		 2112 /* Unmap chunks, if any.
2113 * TFD info for odd chunks is different format than for even chunks. */
b481de9c
ZY		 2114 for (i = 0; i < counter; i++) {
2115 index = i / 2;
2116 is_odd = i & 0x1;
2117
2118 if (is_odd)
2119 pci_unmap_single(
2120 dev,
2121 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
2122 (IWL_GET_BITS(bd->pa[index],
2123 tb2_addr_hi20) << 16),
2124 IWL_GET_BITS(bd->pa[index], tb2_len),
2125 PCI_DMA_TODEVICE);
2126
2127 else if (i > 0)
2128 pci_unmap_single(dev,
2129 le32_to_cpu(bd->pa[index].tb1_addr),
2130 IWL_GET_BITS(bd->pa[index], tb1_len),
2131 PCI_DMA_TODEVICE);
2132
8b6eaea8 2133 /* Free SKB, if any, for this chunk */
fc4b6853
TW		 2134 if (txq->txb[txq->q.read_ptr].skb[i]) {
2135 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
b481de9c
ZY		 2136
2137 dev_kfree_skb(skb);
fc4b6853 2138 txq->txb[txq->q.read_ptr].skb[i] = NULL;
b481de9c
ZY		 2139 }
2140 }
2141 return 0;
2142}
2143
c79dd5b5 2144int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 2145{
bb8c093b 2146 IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
b481de9c
ZY		 2147 return -EINVAL;
2148}
2149
2150static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
2151{
2152 s32 sign = 1;
2153
2154 if (num < 0) {
2155 sign = -sign;
2156 num = -num;
2157 }
2158 if (denom < 0) {
2159 sign = -sign;
2160 denom = -denom;
2161 }
2162 *res = 1;
2163 *res = ((num * 2 + denom) / (denom * 2)) * sign;
2164
2165 return 1;
2166}
2167
8b6eaea8
CB		 2168/**
2169 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
2170 *
2171 * Determines power supply voltage compensation for txpower calculations.
2172 * Returns number of 1/2-dB steps to subtract from gain table index,
2173 * to compensate for difference between power supply voltage during
2174 * factory measurements, vs. current power supply voltage.
2175 *
2176 * Voltage indication is higher for lower voltage.
2177 * Lower voltage requires more gain (lower gain table index).
2178 */
b481de9c
ZY		 2179static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
2180 s32 current_voltage)
2181{
2182 s32 comp = 0;
2183
2184 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
2185 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
2186 return 0;
2187
2188 iwl4965_math_div_round(current_voltage - eeprom_voltage,
2189 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
2190
2191 if (current_voltage > eeprom_voltage)
2192 comp *= 2;
2193 if ((comp < -2) || (comp > 2))
2194 comp = 0;
2195
2196 return comp;
2197}
2198
bf85ea4f 2199static const struct iwl_channel_info *
c79dd5b5 2200iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
8318d78a 2201 enum ieee80211_band band, u16 channel)
b481de9c 2202{
bf85ea4f 2203 const struct iwl_channel_info *ch_info;
b481de9c 2204
8622e705 2205 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 2206
2207 if (!is_channel_valid(ch_info))
2208 return NULL;
2209
2210 return ch_info;
2211}
2212
2213static s32 iwl4965_get_tx_atten_grp(u16 channel)
2214{
2215 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
2216 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
2217 return CALIB_CH_GROUP_5;
2218
2219 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
2220 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
2221 return CALIB_CH_GROUP_1;
2222
2223 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
2224 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
2225 return CALIB_CH_GROUP_2;
2226
2227 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
2228 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
2229 return CALIB_CH_GROUP_3;
2230
2231 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
2232 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
2233 return CALIB_CH_GROUP_4;
2234
2235 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
2236 return -1;
2237}
2238
c79dd5b5 2239static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 2240{
2241 s32 b = -1;
2242
2243 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
2244 if (priv->eeprom.calib_info.band_info[b].ch_from == 0)
2245 continue;
2246
2247 if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from)
2248 && (channel <= priv->eeprom.calib_info.band_info[b].ch_to))
2249 break;
2250 }
2251
2252 return b;
2253}
2254
2255static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
2256{
2257 s32 val;
2258
2259 if (x2 == x1)
2260 return y1;
2261 else {
2262 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
2263 return val + y2;
2264 }
2265}
2266
8b6eaea8
CB		 2267/**
2268 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
2269 *
2270 * Interpolates factory measurements from the two sample channels within a
2271 * sub-band, to apply to channel of interest. Interpolation is proportional to
2272 * differences in channel frequencies, which is proportional to differences
2273 * in channel number.
2274 */
c79dd5b5 2275static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
bb8c093b 2276 struct iwl4965_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 2277{
2278 s32 s = -1;
2279 u32 c;
2280 u32 m;
bb8c093b
CH		 2281 const struct iwl4965_eeprom_calib_measure *m1;
2282 const struct iwl4965_eeprom_calib_measure *m2;
2283 struct iwl4965_eeprom_calib_measure *omeas;
b481de9c
ZY		 2284 u32 ch_i1;
2285 u32 ch_i2;
2286
2287 s = iwl4965_get_sub_band(priv, channel);
2288 if (s >= EEPROM_TX_POWER_BANDS) {
2289 IWL_ERROR("Tx Power can not find channel %d ", channel);
2290 return -1;
2291 }
2292
2293 ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num;
2294 ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num;
2295 chan_info->ch_num = (u8) channel;
2296
2297 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
2298 channel, s, ch_i1, ch_i2);
2299
2300 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
2301 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
2302 m1 = &(priv->eeprom.calib_info.band_info[s].ch1.
2303 measurements[c][m]);
2304 m2 = &(priv->eeprom.calib_info.band_info[s].ch2.
2305 measurements[c][m]);
2306 omeas = &(chan_info->measurements[c][m]);
2307
2308 omeas->actual_pow =
2309 (u8) iwl4965_interpolate_value(channel, ch_i1,
2310 m1->actual_pow,
2311 ch_i2,
2312 m2->actual_pow);
2313 omeas->gain_idx =
2314 (u8) iwl4965_interpolate_value(channel, ch_i1,
2315 m1->gain_idx, ch_i2,
2316 m2->gain_idx);
2317 omeas->temperature =
2318 (u8) iwl4965_interpolate_value(channel, ch_i1,
2319 m1->temperature,
2320 ch_i2,
2321 m2->temperature);
2322 omeas->pa_det =
2323 (s8) iwl4965_interpolate_value(channel, ch_i1,
2324 m1->pa_det, ch_i2,
2325 m2->pa_det);
2326
2327 IWL_DEBUG_TXPOWER
2328 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
2329 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
2330 IWL_DEBUG_TXPOWER
2331 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
2332 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
2333 IWL_DEBUG_TXPOWER
2334 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
2335 m1->pa_det, m2->pa_det, omeas->pa_det);
2336 IWL_DEBUG_TXPOWER
2337 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
2338 m1->temperature, m2->temperature,
2339 omeas->temperature);
2340 }
2341 }
2342
2343 return 0;
2344}
2345
2346/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
2347 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
2348static s32 back_off_table[] = {
2349 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
2350 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
2351 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
2352 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
2353 10 /* CCK */
2354};
2355
2356/* Thermal compensation values for txpower for various frequency ranges ...
2357 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 2358static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 2359 s32 degrees_per_05db_a;
2360 s32 degrees_per_05db_a_denom;
2361} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
2362 {9, 2}, /* group 0 5.2, ch 34-43 */
2363 {4, 1}, /* group 1 5.2, ch 44-70 */
2364 {4, 1}, /* group 2 5.2, ch 71-124 */
2365 {4, 1}, /* group 3 5.2, ch 125-200 */
2366 {3, 1} /* group 4 2.4, ch all */
2367};
2368
2369static s32 get_min_power_index(s32 rate_power_index, u32 band)
2370{
2371 if (!band) {
2372 if ((rate_power_index & 7) <= 4)
2373 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
2374 }
2375 return MIN_TX_GAIN_INDEX;
2376}
2377
2378struct gain_entry {
2379 u8 dsp;
2380 u8 radio;
2381};
2382
2383static const struct gain_entry gain_table[2][108] = {
2384 /* 5.2GHz power gain index table */
2385 {
2386 {123, 0x3F}, /* highest txpower */
2387 {117, 0x3F},
2388 {110, 0x3F},
2389 {104, 0x3F},
2390 {98, 0x3F},
2391 {110, 0x3E},
2392 {104, 0x3E},
2393 {98, 0x3E},
2394 {110, 0x3D},
2395 {104, 0x3D},
2396 {98, 0x3D},
2397 {110, 0x3C},
2398 {104, 0x3C},
2399 {98, 0x3C},
2400 {110, 0x3B},
2401 {104, 0x3B},
2402 {98, 0x3B},
2403 {110, 0x3A},
2404 {104, 0x3A},
2405 {98, 0x3A},
2406 {110, 0x39},
2407 {104, 0x39},
2408 {98, 0x39},
2409 {110, 0x38},
2410 {104, 0x38},
2411 {98, 0x38},
2412 {110, 0x37},
2413 {104, 0x37},
2414 {98, 0x37},
2415 {110, 0x36},
2416 {104, 0x36},
2417 {98, 0x36},
2418 {110, 0x35},
2419 {104, 0x35},
2420 {98, 0x35},
2421 {110, 0x34},
2422 {104, 0x34},
2423 {98, 0x34},
2424 {110, 0x33},
2425 {104, 0x33},
2426 {98, 0x33},
2427 {110, 0x32},
2428 {104, 0x32},
2429 {98, 0x32},
2430 {110, 0x31},
2431 {104, 0x31},
2432 {98, 0x31},
2433 {110, 0x30},
2434 {104, 0x30},
2435 {98, 0x30},
2436 {110, 0x25},
2437 {104, 0x25},
2438 {98, 0x25},
2439 {110, 0x24},
2440 {104, 0x24},
2441 {98, 0x24},
2442 {110, 0x23},
2443 {104, 0x23},
2444 {98, 0x23},
2445 {110, 0x22},
2446 {104, 0x18},
2447 {98, 0x18},
2448 {110, 0x17},
2449 {104, 0x17},
2450 {98, 0x17},
2451 {110, 0x16},
2452 {104, 0x16},
2453 {98, 0x16},
2454 {110, 0x15},
2455 {104, 0x15},
2456 {98, 0x15},
2457 {110, 0x14},
2458 {104, 0x14},
2459 {98, 0x14},
2460 {110, 0x13},
2461 {104, 0x13},
2462 {98, 0x13},
2463 {110, 0x12},
2464 {104, 0x08},
2465 {98, 0x08},
2466 {110, 0x07},
2467 {104, 0x07},
2468 {98, 0x07},
2469 {110, 0x06},
2470 {104, 0x06},
2471 {98, 0x06},
2472 {110, 0x05},
2473 {104, 0x05},
2474 {98, 0x05},
2475 {110, 0x04},
2476 {104, 0x04},
2477 {98, 0x04},
2478 {110, 0x03},
2479 {104, 0x03},
2480 {98, 0x03},
2481 {110, 0x02},
2482 {104, 0x02},
2483 {98, 0x02},
2484 {110, 0x01},
2485 {104, 0x01},
2486 {98, 0x01},
2487 {110, 0x00},
2488 {104, 0x00},
2489 {98, 0x00},
2490 {93, 0x00},
2491 {88, 0x00},
2492 {83, 0x00},
2493 {78, 0x00},
2494 },
2495 /* 2.4GHz power gain index table */
2496 {
2497 {110, 0x3f}, /* highest txpower */
2498 {104, 0x3f},
2499 {98, 0x3f},
2500 {110, 0x3e},
2501 {104, 0x3e},
2502 {98, 0x3e},
2503 {110, 0x3d},
2504 {104, 0x3d},
2505 {98, 0x3d},
2506 {110, 0x3c},
2507 {104, 0x3c},
2508 {98, 0x3c},
2509 {110, 0x3b},
2510 {104, 0x3b},
2511 {98, 0x3b},
2512 {110, 0x3a},
2513 {104, 0x3a},
2514 {98, 0x3a},
2515 {110, 0x39},
2516 {104, 0x39},
2517 {98, 0x39},
2518 {110, 0x38},
2519 {104, 0x38},
2520 {98, 0x38},
2521 {110, 0x37},
2522 {104, 0x37},
2523 {98, 0x37},
2524 {110, 0x36},
2525 {104, 0x36},
2526 {98, 0x36},
2527 {110, 0x35},
2528 {104, 0x35},
2529 {98, 0x35},
2530 {110, 0x34},
2531 {104, 0x34},
2532 {98, 0x34},
2533 {110, 0x33},
2534 {104, 0x33},
2535 {98, 0x33},
2536 {110, 0x32},
2537 {104, 0x32},
2538 {98, 0x32},
2539 {110, 0x31},
2540 {104, 0x31},
2541 {98, 0x31},
2542 {110, 0x30},
2543 {104, 0x30},
2544 {98, 0x30},
2545 {110, 0x6},
2546 {104, 0x6},
2547 {98, 0x6},
2548 {110, 0x5},
2549 {104, 0x5},
2550 {98, 0x5},
2551 {110, 0x4},
2552 {104, 0x4},
2553 {98, 0x4},
2554 {110, 0x3},
2555 {104, 0x3},
2556 {98, 0x3},
2557 {110, 0x2},
2558 {104, 0x2},
2559 {98, 0x2},
2560 {110, 0x1},
2561 {104, 0x1},
2562 {98, 0x1},
2563 {110, 0x0},
2564 {104, 0x0},
2565 {98, 0x0},
2566 {97, 0},
2567 {96, 0},
2568 {95, 0},
2569 {94, 0},
2570 {93, 0},
2571 {92, 0},
2572 {91, 0},
2573 {90, 0},
2574 {89, 0},
2575 {88, 0},
2576 {87, 0},
2577 {86, 0},
2578 {85, 0},
2579 {84, 0},
2580 {83, 0},
2581 {82, 0},
2582 {81, 0},
2583 {80, 0},
2584 {79, 0},
2585 {78, 0},
2586 {77, 0},
2587 {76, 0},
2588 {75, 0},
2589 {74, 0},
2590 {73, 0},
2591 {72, 0},
2592 {71, 0},
2593 {70, 0},
2594 {69, 0},
2595 {68, 0},
2596 {67, 0},
2597 {66, 0},
2598 {65, 0},
2599 {64, 0},
2600 {63, 0},
2601 {62, 0},
2602 {61, 0},
2603 {60, 0},
2604 {59, 0},
2605 }
2606};
2607
c79dd5b5 2608static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 2609 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 2610 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 2611{
2612 u8 saturation_power;
2613 s32 target_power;
2614 s32 user_target_power;
2615 s32 power_limit;
2616 s32 current_temp;
2617 s32 reg_limit;
2618 s32 current_regulatory;
2619 s32 txatten_grp = CALIB_CH_GROUP_MAX;
2620 int i;
2621 int c;
bf85ea4f 2622 const struct iwl_channel_info *ch_info = NULL;
bb8c093b
CH		 2623 struct iwl4965_eeprom_calib_ch_info ch_eeprom_info;
2624 const struct iwl4965_eeprom_calib_measure *measurement;
b481de9c
ZY		 2625 s16 voltage;
2626 s32 init_voltage;
2627 s32 voltage_compensation;
2628 s32 degrees_per_05db_num;
2629 s32 degrees_per_05db_denom;
2630 s32 factory_temp;
2631 s32 temperature_comp[2];
2632 s32 factory_gain_index[2];
2633 s32 factory_actual_pwr[2];
2634 s32 power_index;
2635
2636 /* Sanity check requested level (dBm) */
2637 if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
2638 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
2639 priv->user_txpower_limit);
2640 return -EINVAL;
2641 }
2642 if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
2643 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
2644 priv->user_txpower_limit);
2645 return -EINVAL;
2646 }
2647
2648 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
2649 * are used for indexing into txpower table) */
2650 user_target_power = 2 * priv->user_txpower_limit;
2651
2652 /* Get current (RXON) channel, band, width */
2653 ch_info =
8318d78a 2654 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
b481de9c
ZY		 2655
2656 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
2657 is_fat);
2658
2659 if (!ch_info)
2660 return -EINVAL;
2661
2662 /* get txatten group, used to select 1) thermal txpower adjustment
2663 * and 2) mimo txpower balance between Tx chains. */
2664 txatten_grp = iwl4965_get_tx_atten_grp(channel);
2665 if (txatten_grp < 0)
2666 return -EINVAL;
2667
2668 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
2669 channel, txatten_grp);
2670
2671 if (is_fat) {
2672 if (ctrl_chan_high)
2673 channel -= 2;
2674 else
2675 channel += 2;
2676 }
2677
2678 /* hardware txpower limits ...
2679 * saturation (clipping distortion) txpowers are in half-dBm */
2680 if (band)
2681 saturation_power = priv->eeprom.calib_info.saturation_power24;
2682 else
2683 saturation_power = priv->eeprom.calib_info.saturation_power52;
2684
2685 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
2686 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
2687 if (band)
2688 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
2689 else
2690 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
2691 }
2692
2693 /* regulatory txpower limits ... reg_limit values are in half-dBm,
2694 * max_power_avg values are in dBm, convert * 2 */
2695 if (is_fat)
2696 reg_limit = ch_info->fat_max_power_avg * 2;
2697 else
2698 reg_limit = ch_info->max_power_avg * 2;
2699
2700 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
2701 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
2702 if (band)
2703 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
2704 else
2705 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
2706 }
2707
2708 /* Interpolate txpower calibration values for this channel,
2709 * based on factory calibration tests on spaced channels. */
2710 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
2711
2712 /* calculate tx gain adjustment based on power supply voltage */
2713 voltage = priv->eeprom.calib_info.voltage;
2714 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
2715 voltage_compensation =
2716 iwl4965_get_voltage_compensation(voltage, init_voltage);
2717
2718 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
2719 init_voltage,
2720 voltage, voltage_compensation);
2721
2722 /* get current temperature (Celsius) */
2723 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
2724 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
2725 current_temp = KELVIN_TO_CELSIUS(current_temp);
2726
2727 /* select thermal txpower adjustment params, based on channel group
2728 * (same frequency group used for mimo txatten adjustment) */
2729 degrees_per_05db_num =
2730 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
2731 degrees_per_05db_denom =
2732 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
2733
2734 /* get per-chain txpower values from factory measurements */
2735 for (c = 0; c < 2; c++) {
2736 measurement = &ch_eeprom_info.measurements[c][1];
2737
2738 /* txgain adjustment (in half-dB steps) based on difference
2739 * between factory and current temperature */
2740 factory_temp = measurement->temperature;
2741 iwl4965_math_div_round((current_temp - factory_temp) *
2742 degrees_per_05db_denom,
2743 degrees_per_05db_num,
2744 &temperature_comp[c]);
2745
2746 factory_gain_index[c] = measurement->gain_idx;
2747 factory_actual_pwr[c] = measurement->actual_pow;
2748
2749 IWL_DEBUG_TXPOWER("chain = %d\n", c);
2750 IWL_DEBUG_TXPOWER("fctry tmp %d, "
2751 "curr tmp %d, comp %d steps\n",
2752 factory_temp, current_temp,
2753 temperature_comp[c]);
2754
2755 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
2756 factory_gain_index[c],
2757 factory_actual_pwr[c]);
2758 }
2759
2760 /* for each of 33 bit-rates (including 1 for CCK) */
2761 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
2762 u8 is_mimo_rate;
bb8c093b 2763 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 2764
2765 /* for mimo, reduce each chain's txpower by half
2766 * (3dB, 6 steps), so total output power is regulatory
2767 * compliant. */
2768 if (i & 0x8) {
2769 current_regulatory = reg_limit -
2770 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
2771 is_mimo_rate = 1;
2772 } else {
2773 current_regulatory = reg_limit;
2774 is_mimo_rate = 0;
2775 }
2776
2777 /* find txpower limit, either hardware or regulatory */
2778 power_limit = saturation_power - back_off_table[i];
2779 if (power_limit > current_regulatory)
2780 power_limit = current_regulatory;
2781
2782 /* reduce user's txpower request if necessary
2783 * for this rate on this channel */
2784 target_power = user_target_power;
2785 if (target_power > power_limit)
2786 target_power = power_limit;
2787
2788 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
2789 i, saturation_power - back_off_table[i],
2790 current_regulatory, user_target_power,
2791 target_power);
2792
2793 /* for each of 2 Tx chains (radio transmitters) */
2794 for (c = 0; c < 2; c++) {
2795 s32 atten_value;
2796
2797 if (is_mimo_rate)
2798 atten_value =
2799 (s32)le32_to_cpu(priv->card_alive_init.
2800 tx_atten[txatten_grp][c]);
2801 else
2802 atten_value = 0;
2803
2804 /* calculate index; higher index means lower txpower */
2805 power_index = (u8) (factory_gain_index[c] -
2806 (target_power -
2807 factory_actual_pwr[c]) -
2808 temperature_comp[c] -
2809 voltage_compensation +
2810 atten_value);
2811
2812/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
2813 power_index); */
2814
2815 if (power_index < get_min_power_index(i, band))
2816 power_index = get_min_power_index(i, band);
2817
2818 /* adjust 5 GHz index to support negative indexes */
2819 if (!band)
2820 power_index += 9;
2821
2822 /* CCK, rate 32, reduce txpower for CCK */
2823 if (i == POWER_TABLE_CCK_ENTRY)
2824 power_index +=
2825 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
2826
2827 /* stay within the table! */
2828 if (power_index > 107) {
2829 IWL_WARNING("txpower index %d > 107\n",
2830 power_index);
2831 power_index = 107;
2832 }
2833 if (power_index < 0) {
2834 IWL_WARNING("txpower index %d < 0\n",
2835 power_index);
2836 power_index = 0;
2837 }
2838
2839 /* fill txpower command for this rate/chain */
2840 tx_power.s.radio_tx_gain[c] =
2841 gain_table[band][power_index].radio;
2842 tx_power.s.dsp_predis_atten[c] =
2843 gain_table[band][power_index].dsp;
2844
2845 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
2846 "gain 0x%02x dsp %d\n",
2847 c, atten_value, power_index,
2848 tx_power.s.radio_tx_gain[c],
2849 tx_power.s.dsp_predis_atten[c]);
2850 }/* for each chain */
2851
2852 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
2853
2854 }/* for each rate */
2855
2856 return 0;
2857}
2858
2859/**
bb8c093b 2860 * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
b481de9c
ZY		 2861 *
2862 * Uses the active RXON for channel, band, and characteristics (fat, high)
2863 * The power limit is taken from priv->user_txpower_limit.
2864 */
c79dd5b5 2865int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
b481de9c 2866{
bb8c093b 2867 struct iwl4965_txpowertable_cmd cmd = { 0 };
857485c0 2868 int ret;
b481de9c
ZY		 2869 u8 band = 0;
2870 u8 is_fat = 0;
2871 u8 ctrl_chan_high = 0;
2872
2873 if (test_bit(STATUS_SCANNING, &priv->status)) {
2874 /* If this gets hit a lot, switch it to a BUG() and catch
2875 * the stack trace to find out who is calling this during
2876 * a scan. */
2877 IWL_WARNING("TX Power requested while scanning!\n");
2878 return -EAGAIN;
2879 }
2880
8318d78a 2881 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 2882
2883 is_fat = is_fat_channel(priv->active_rxon.flags);
2884
2885 if (is_fat &&
2886 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2887 ctrl_chan_high = 1;
2888
2889 cmd.band = band;
2890 cmd.channel = priv->active_rxon.channel;
2891
857485c0 2892 ret = iwl4965_fill_txpower_tbl(priv, band,
b481de9c
ZY		 2893 le16_to_cpu(priv->active_rxon.channel),
2894 is_fat, ctrl_chan_high, &cmd.tx_power);
857485c0
TW		 2895 if (ret)
2896 goto out;
b481de9c 2897
857485c0
TW		 2898 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
2899
2900out:
2901 return ret;
b481de9c
ZY		 2902}
2903
c79dd5b5 2904int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 2905{
2906 int rc;
2907 u8 band = 0;
2908 u8 is_fat = 0;
2909 u8 ctrl_chan_high = 0;
bb8c093b 2910 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 2911 const struct iwl_channel_info *ch_info;
b481de9c 2912
8318d78a 2913 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 2914
8622e705 2915 ch_info = iwl_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 2916
2917 is_fat = is_fat_channel(priv->staging_rxon.flags);
2918
2919 if (is_fat &&
2920 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2921 ctrl_chan_high = 1;
2922
2923 cmd.band = band;
2924 cmd.expect_beacon = 0;
2925 cmd.channel = cpu_to_le16(channel);
2926 cmd.rxon_flags = priv->active_rxon.flags;
2927 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2928 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2929 if (ch_info)
2930 cmd.expect_beacon = is_channel_radar(ch_info);
2931 else
2932 cmd.expect_beacon = 1;
2933
2934 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2935 ctrl_chan_high, &cmd.tx_power);
2936 if (rc) {
2937 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
2938 return rc;
2939 }
2940
857485c0 2941 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 2942 return rc;
2943}
2944
2945#define RTS_HCCA_RETRY_LIMIT 3
2946#define RTS_DFAULT_RETRY_LIMIT 60
2947
c79dd5b5 2948void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
857485c0 2949 struct iwl_cmd *cmd,
b481de9c
ZY		 2950 struct ieee80211_tx_control *ctrl,
2951 struct ieee80211_hdr *hdr, int sta_id,
2952 int is_hcca)
2953{
87e4f7df 2954 struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
b481de9c
ZY		 2955 u8 rts_retry_limit = 0;
2956 u8 data_retry_limit = 0;
b481de9c 2957 u16 fc = le16_to_cpu(hdr->frame_control);
87e4f7df
TW		 2958 u8 rate_plcp;
2959 u16 rate_flags = 0;
8318d78a 2960 int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c 2961
87e4f7df 2962 rate_plcp = iwl4965_rates[rate_idx].plcp;
b481de9c
ZY		 2963
2964 rts_retry_limit = (is_hcca) ?
2965 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2966
87e4f7df
TW		 2967 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2968 rate_flags |= RATE_MCS_CCK_MSK;
2969
2970
b481de9c
ZY		 2971 if (ieee80211_is_probe_response(fc)) {
2972 data_retry_limit = 3;
2973 if (data_retry_limit < rts_retry_limit)
2974 rts_retry_limit = data_retry_limit;
2975 } else
2976 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2977
2978 if (priv->data_retry_limit != -1)
2979 data_retry_limit = priv->data_retry_limit;
2980
87e4f7df
TW		 2981
2982 if (ieee80211_is_data(fc)) {
2983 tx->initial_rate_index = 0;
2984 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2985 } else {
b481de9c
ZY		 2986 switch (fc & IEEE80211_FCTL_STYPE) {
2987 case IEEE80211_STYPE_AUTH:
2988 case IEEE80211_STYPE_DEAUTH:
2989 case IEEE80211_STYPE_ASSOC_REQ:
2990 case IEEE80211_STYPE_REASSOC_REQ:
87e4f7df
TW		 2991 if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2992 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2993 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
b481de9c
ZY		 2994 }
2995 break;
2996 default:
2997 break;
2998 }
87e4f7df
TW		 2999
3000 /* Alternate between antenna A and B for successive frames */
3001 if (priv->use_ant_b_for_management_frame) {
3002 priv->use_ant_b_for_management_frame = 0;
3003 rate_flags |= RATE_MCS_ANT_B_MSK;
3004 } else {
3005 priv->use_ant_b_for_management_frame = 1;
3006 rate_flags |= RATE_MCS_ANT_A_MSK;
3007 }
b481de9c
ZY		 3008 }
3009
87e4f7df
TW		 3010 tx->rts_retry_limit = rts_retry_limit;
3011 tx->data_retry_limit = data_retry_limit;
3012 tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
b481de9c
ZY		 3013}
3014
c79dd5b5 3015int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
b481de9c 3016{
bb8c093b 3017 struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c
ZY		 3018
3019 return IWL_GET_BITS(*shared_data, rb_closed_stts_rb_num);
3020}
3021
c79dd5b5 3022int iwl4965_hw_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 3023{
3024 return priv->temperature;
3025}
3026
c79dd5b5 3027unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 3028 struct iwl4965_frame *frame, u8 rate)
b481de9c 3029{
bb8c093b 3030 struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 3031 unsigned int frame_size;
3032
3033 tx_beacon_cmd = &frame->u.beacon;
3034 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
3035
a4062b8f 3036 tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id;
b481de9c
ZY		 3037 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
3038
bb8c093b 3039 frame_size = iwl4965_fill_beacon_frame(priv,
b481de9c 3040 tx_beacon_cmd->frame,
bb8c093b 3041 iwl4965_broadcast_addr,
b481de9c
ZY		 3042 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
3043
3044 BUG_ON(frame_size > MAX_MPDU_SIZE);
3045 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
3046
3047 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
3048 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 3049 iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
b481de9c
ZY		 3050 else
3051 tx_beacon_cmd->tx.rate_n_flags =
bb8c093b 3052 iwl4965_hw_set_rate_n_flags(rate, 0);
b481de9c
ZY		 3053
3054 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
3055 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
3056 return (sizeof(*tx_beacon_cmd) + frame_size);
3057}
3058
8b6eaea8
CB		 3059/*
3060 * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
3061 * given Tx queue, and enable the DMA channel used for that queue.
3062 *
3063 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
3064 * channels supported in hardware.
3065 */
c79dd5b5 3066int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
b481de9c
ZY		 3067{
3068 int rc;
3069 unsigned long flags;
3070 int txq_id = txq->q.id;
3071
3072 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 3073 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 3074 if (rc) {
3075 spin_unlock_irqrestore(&priv->lock, flags);
3076 return rc;
3077 }
3078
8b6eaea8 3079 /* Circular buffer (TFD queue in DRAM) physical base address */
3395f6e9 3080 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
b481de9c 3081 txq->q.dma_addr >> 8);
8b6eaea8
CB		 3082
3083 /* Enable DMA channel, using same id as for TFD queue */
3395f6e9 3084 iwl_write_direct32(
b481de9c
ZY		 3085 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
3086 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
3087 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
3395f6e9 3088 iwl_release_nic_access(priv);
b481de9c
ZY		 3089 spin_unlock_irqrestore(&priv->lock, flags);
3090
3091 return 0;
3092}
3093
c79dd5b5 3094int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
b481de9c
ZY		 3095 dma_addr_t addr, u16 len)
3096{
3097 int index, is_odd;
bb8c093b 3098 struct iwl4965_tfd_frame *tfd = ptr;
b481de9c
ZY		 3099 u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
3100
8b6eaea8 3101 /* Each TFD can point to a maximum 20 Tx buffers */
b481de9c
ZY		 3102 if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
3103 IWL_ERROR("Error can not send more than %d chunks\n",
3104 MAX_NUM_OF_TBS);
3105 return -EINVAL;
3106 }
3107
3108 index = num_tbs / 2;
3109 is_odd = num_tbs & 0x1;
3110
3111 if (!is_odd) {
3112 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
3113 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
6a218f6f 3114 iwl_get_dma_hi_address(addr));
b481de9c
ZY		 3115 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
3116 } else {
3117 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
3118 (u32) (addr & 0xffff));
3119 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
3120 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
3121 }
3122
3123 IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
3124
3125 return 0;
3126}
3127
c79dd5b5 3128static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
b481de9c
ZY		 3129{
3130 u16 hw_version = priv->eeprom.board_revision_4965;
3131
3132 IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
3133 ((hw_version >> 8) & 0x0F),
3134 ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
3135
3136 IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
3137 priv->eeprom.board_pba_number_4965);
3138}
3139
3140#define IWL_TX_CRC_SIZE 4
3141#define IWL_TX_DELIMITER_SIZE 4
3142
8b6eaea8 3143/**
e2a722eb 3144 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
8b6eaea8 3145 */
e2a722eb
TW		 3146static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
3147 struct iwl4965_tx_queue *txq,
3148 u16 byte_cnt)
b481de9c
ZY		 3149{
3150 int len;
3151 int txq_id = txq->q.id;
bb8c093b 3152 struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
b481de9c 3153
b481de9c
ZY		 3154 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
3155
8b6eaea8 3156 /* Set up byte count within first 256 entries */
b481de9c 3157 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 3158 tfd_offset[txq->q.write_ptr], byte_cnt, len);
b481de9c 3159
8b6eaea8 3160 /* If within first 64 entries, duplicate at end */
fc4b6853 3161 if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
b481de9c 3162 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 3163 tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
b481de9c 3164 byte_cnt, len);
b481de9c
ZY		 3165}
3166
8b6eaea8
CB		 3167/**
3168 * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
3169 *
3170 * Selects how many and which Rx receivers/antennas/chains to use.
3171 * This should not be used for scan command ... it puts data in wrong place.
3172 */
c79dd5b5 3173void iwl4965_set_rxon_chain(struct iwl_priv *priv)
b481de9c
ZY		 3174{
3175 u8 is_single = is_single_stream(priv);
3176 u8 idle_state, rx_state;
3177
3178 priv->staging_rxon.rx_chain = 0;
3179 rx_state = idle_state = 3;
3180
3181 /* Tell uCode which antennas are actually connected.
3182 * Before first association, we assume all antennas are connected.
3183 * Just after first association, iwl4965_noise_calibration()
3184 * checks which antennas actually *are* connected. */
3185 priv->staging_rxon.rx_chain |=
3186 cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
3187
3188 /* How many receivers should we use? */
3189 iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
3190 priv->staging_rxon.rx_chain |=
3191 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
3192 priv->staging_rxon.rx_chain |=
3193 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
3194
3195 if (!is_single && (rx_state >= 2) &&
3196 !test_bit(STATUS_POWER_PMI, &priv->status))
3197 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
3198 else
3199 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
3200
3201 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
3202}
3203
b481de9c
ZY		 3204/**
3205 * sign_extend - Sign extend a value using specified bit as sign-bit
3206 *
3207 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
3208 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
3209 *
3210 * @param oper value to sign extend
3211 * @param index 0 based bit index (0<=index<32) to sign bit
3212 */
3213static s32 sign_extend(u32 oper, int index)
3214{
3215 u8 shift = 31 - index;
3216
3217 return (s32)(oper << shift) >> shift;
3218}
3219
3220/**
3221 * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
3222 * @statistics: Provides the temperature reading from the uCode
3223 *
3224 * A return of <0 indicates bogus data in the statistics
3225 */
c79dd5b5 3226int iwl4965_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 3227{
3228 s32 temperature;
3229 s32 vt;
3230 s32 R1, R2, R3;
3231 u32 R4;
3232
3233 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
3234 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
3235 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
3236 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
3237 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
3238 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
3239 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
3240 } else {
3241 IWL_DEBUG_TEMP("Running temperature calibration\n");
3242 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
3243 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
3244 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
3245 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
3246 }
3247
3248 /*
8b6eaea8 3249 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 3250 *
3251 * NOTE If we haven't received a statistics notification yet
3252 * with an updated temperature, use R4 provided to us in the
8b6eaea8
CB		 3253 * "initialize" ALIVE response.
3254 */
b481de9c
ZY		 3255 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
3256 vt = sign_extend(R4, 23);
3257 else
3258 vt = sign_extend(
3259 le32_to_cpu(priv->statistics.general.temperature), 23);
3260
3261 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
3262 R1, R2, R3, vt);
3263
3264 if (R3 == R1) {
3265 IWL_ERROR("Calibration conflict R1 == R3\n");
3266 return -1;
3267 }
3268
3269 /* Calculate temperature in degrees Kelvin, adjust by 97%.
3270 * Add offset to center the adjustment around 0 degrees Centigrade. */
3271 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
3272 temperature /= (R3 - R1);
3273 temperature = (temperature * 97) / 100 +
3274 TEMPERATURE_CALIB_KELVIN_OFFSET;
3275
3276 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
3277 KELVIN_TO_CELSIUS(temperature));
3278
3279 return temperature;
3280}
3281
3282/* Adjust Txpower only if temperature variance is greater than threshold. */
3283#define IWL_TEMPERATURE_THRESHOLD 3
3284
3285/**
3286 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
3287 *
3288 * If the temperature changed has changed sufficiently, then a recalibration
3289 * is needed.
3290 *
3291 * Assumes caller will replace priv->last_temperature once calibration
3292 * executed.
3293 */
c79dd5b5 3294static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 3295{
3296 int temp_diff;
3297
3298 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
3299 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
3300 return 0;
3301 }
3302
3303 temp_diff = priv->temperature - priv->last_temperature;
3304
3305 /* get absolute value */
3306 if (temp_diff < 0) {
3307 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
3308 temp_diff = -temp_diff;
3309 } else if (temp_diff == 0)
3310 IWL_DEBUG_POWER("Same temp, \n");
3311 else
3312 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
3313
3314 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
3315 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
3316 return 0;
3317 }
3318
3319 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
3320
3321 return 1;
3322}
3323
3324/* Calculate noise level, based on measurements during network silence just
3325 * before arriving beacon. This measurement can be done only if we know
3326 * exactly when to expect beacons, therefore only when we're associated. */
c79dd5b5 3327static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
b481de9c
ZY		 3328{
3329 struct statistics_rx_non_phy *rx_info
3330 = &(priv->statistics.rx.general);
3331 int num_active_rx = 0;
3332 int total_silence = 0;
3333 int bcn_silence_a =
3334 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
3335 int bcn_silence_b =
3336 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
3337 int bcn_silence_c =
3338 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
3339
3340 if (bcn_silence_a) {
3341 total_silence += bcn_silence_a;
3342 num_active_rx++;
3343 }
3344 if (bcn_silence_b) {
3345 total_silence += bcn_silence_b;
3346 num_active_rx++;
3347 }
3348 if (bcn_silence_c) {
3349 total_silence += bcn_silence_c;
3350 num_active_rx++;
3351 }
3352
3353 /* Average among active antennas */
3354 if (num_active_rx)
3355 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
3356 else
3357 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3358
3359 IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
3360 bcn_silence_a, bcn_silence_b, bcn_silence_c,
3361 priv->last_rx_noise);
3362}
3363
c79dd5b5 3364void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3365{
bb8c093b 3366 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3367 int change;
3368 s32 temp;
3369
3370 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
3371 (int)sizeof(priv->statistics), pkt->len);
3372
3373 change = ((priv->statistics.general.temperature !=
3374 pkt->u.stats.general.temperature) ||
3375 ((priv->statistics.flag &
3376 STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
3377 (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
3378
3379 memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
3380
3381 set_bit(STATUS_STATISTICS, &priv->status);
3382
3383 /* Reschedule the statistics timer to occur in
3384 * REG_RECALIB_PERIOD seconds to ensure we get a
3385 * thermal update even if the uCode doesn't give
3386 * us one */
3387 mod_timer(&priv->statistics_periodic, jiffies +
3388 msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
3389
3390 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
3391 (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
3392 iwl4965_rx_calc_noise(priv);
c8b0e6e1 3393#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 3394 queue_work(priv->workqueue, &priv->sensitivity_work);
3395#endif
3396 }
3397
ab53d8af
MA		 3398 iwl_leds_background(priv);
3399
b481de9c
ZY		 3400 /* If the hardware hasn't reported a change in
3401 * temperature then don't bother computing a
3402 * calibrated temperature value */
3403 if (!change)
3404 return;
3405
3406 temp = iwl4965_get_temperature(priv);
3407 if (temp < 0)
3408 return;
3409
3410 if (priv->temperature != temp) {
3411 if (priv->temperature)
3412 IWL_DEBUG_TEMP("Temperature changed "
3413 "from %dC to %dC\n",
3414 KELVIN_TO_CELSIUS(priv->temperature),
3415 KELVIN_TO_CELSIUS(temp));
3416 else
3417 IWL_DEBUG_TEMP("Temperature "
3418 "initialized to %dC\n",
3419 KELVIN_TO_CELSIUS(temp));
3420 }
3421
3422 priv->temperature = temp;
3423 set_bit(STATUS_TEMPERATURE, &priv->status);
3424
3425 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
3426 iwl4965_is_temp_calib_needed(priv))
3427 queue_work(priv->workqueue, &priv->txpower_work);
3428}
3429
c79dd5b5 3430static void iwl4965_add_radiotap(struct iwl_priv *priv,
12342c47
ZY		 3431 struct sk_buff *skb,
3432 struct iwl4965_rx_phy_res *rx_start,
3433 struct ieee80211_rx_status *stats,
3434 u32 ampdu_status)
3435{
3436 s8 signal = stats->ssi;
3437 s8 noise = 0;
8318d78a 3438 int rate = stats->rate_idx;
12342c47 3439 u64 tsf = stats->mactime;
a0b484fe 3440 __le16 antenna;
12342c47
ZY		 3441 __le16 phy_flags_hw = rx_start->phy_flags;
3442 struct iwl4965_rt_rx_hdr {
3443 struct ieee80211_radiotap_header rt_hdr;
3444 __le64 rt_tsf; /* TSF */
3445 u8 rt_flags; /* radiotap packet flags */
3446 u8 rt_rate; /* rate in 500kb/s */
3447 __le16 rt_channelMHz; /* channel in MHz */
3448 __le16 rt_chbitmask; /* channel bitfield */
3449 s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
3450 s8 rt_dbmnoise;
3451 u8 rt_antenna; /* antenna number */
3452 } __attribute__ ((packed)) *iwl4965_rt;
3453
3454 /* TODO: We won't have enough headroom for HT frames. Fix it later. */
3455 if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
3456 if (net_ratelimit())
3457 printk(KERN_ERR "not enough headroom [%d] for "
01c20986 3458 "radiotap head [%zd]\n",
12342c47
ZY		 3459 skb_headroom(skb), sizeof(*iwl4965_rt));
3460 return;
3461 }
3462
3463 /* put radiotap header in front of 802.11 header and data */
3464 iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
3465
3466 /* initialise radiotap header */
3467 iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
3468 iwl4965_rt->rt_hdr.it_pad = 0;
3469
3470 /* total header + data */
3471 put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
3472 &iwl4965_rt->rt_hdr.it_len);
3473
3474 /* Indicate all the fields we add to the radiotap header */
3475 put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
3476 (1 << IEEE80211_RADIOTAP_FLAGS) |
3477 (1 << IEEE80211_RADIOTAP_RATE) |
3478 (1 << IEEE80211_RADIOTAP_CHANNEL) |
3479 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
3480 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
3481 (1 << IEEE80211_RADIOTAP_ANTENNA)),
3482 &iwl4965_rt->rt_hdr.it_present);
3483
3484 /* Zero the flags, we'll add to them as we go */
3485 iwl4965_rt->rt_flags = 0;
3486
3487 put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
3488
3489 iwl4965_rt->rt_dbmsignal = signal;
3490 iwl4965_rt->rt_dbmnoise = noise;
3491
3492 /* Convert the channel frequency and set the flags */
3493 put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
3494 if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
3495 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
3496 IEEE80211_CHAN_5GHZ),
3497 &iwl4965_rt->rt_chbitmask);
3498 else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
3499 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
3500 IEEE80211_CHAN_2GHZ),
3501 &iwl4965_rt->rt_chbitmask);
3502 else /* 802.11g */
3503 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
3504 IEEE80211_CHAN_2GHZ),
3505 &iwl4965_rt->rt_chbitmask);
3506
12342c47
ZY		 3507 if (rate == -1)
3508 iwl4965_rt->rt_rate = 0;
3509 else
3510 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
3511
3512 /*
3513 * "antenna number"
3514 *
3515 * It seems that the antenna field in the phy flags value
3516 * is actually a bitfield. This is undefined by radiotap,
3517 * it wants an actual antenna number but I always get "7"
3518 * for most legacy frames I receive indicating that the
3519 * same frame was received on all three RX chains.
3520 *
3521 * I think this field should be removed in favour of a
3522 * new 802.11n radiotap field "RX chains" that is defined
3523 * as a bitmask.
3524 */
a0b484fe
JB		 3525 antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
3526 iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
12342c47
ZY		 3527
3528 /* set the preamble flag if appropriate */
3529 if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
3530 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3531
3532 stats->flag |= RX_FLAG_RADIOTAP;
3533}
3534
19758bef
TW		 3535static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
3536{
3537 /* 0 - mgmt, 1 - cnt, 2 - data */
3538 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
3539 priv->rx_stats[idx].cnt++;
3540 priv->rx_stats[idx].bytes += len;
3541}
3542
17e476b8
EG		 3543static u32 iwl4965_translate_rx_status(u32 decrypt_in)
3544{
3545 u32 decrypt_out = 0;
3546
3547 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
3548 RX_RES_STATUS_STATION_FOUND)
3549 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
3550 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
3551
3552 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
3553
3554 /* packet was not encrypted */
3555 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
3556 RX_RES_STATUS_SEC_TYPE_NONE)
3557 return decrypt_out;
3558
3559 /* packet was encrypted with unknown alg */
3560 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
3561 RX_RES_STATUS_SEC_TYPE_ERR)
3562 return decrypt_out;
3563
3564 /* decryption was not done in HW */
3565 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
3566 RX_MPDU_RES_STATUS_DEC_DONE_MSK)
3567 return decrypt_out;
3568
3569 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
3570
3571 case RX_RES_STATUS_SEC_TYPE_CCMP:
3572 /* alg is CCM: check MIC only */
3573 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
3574 /* Bad MIC */
3575 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
3576 else
3577 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
3578
3579 break;
3580
3581 case RX_RES_STATUS_SEC_TYPE_TKIP:
3582 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
3583 /* Bad TTAK */
3584 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
3585 break;
3586 }
3587 /* fall through if TTAK OK */
3588 default:
3589 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
3590 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
3591 else
3592 decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
3593 break;
3594 };
3595
3596 IWL_DEBUG_RX("decrypt_in:0x%x decrypt_out = 0x%x\n",
3597 decrypt_in, decrypt_out);
3598
3599 return decrypt_out;
3600}
3601
c79dd5b5 3602static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
b481de9c 3603 int include_phy,
bb8c093b 3604 struct iwl4965_rx_mem_buffer *rxb,
b481de9c
ZY		 3605 struct ieee80211_rx_status *stats)
3606{
bb8c093b 3607 struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
b481de9c
ZY		 3608 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3609 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
3610 struct ieee80211_hdr *hdr;
3611 u16 len;
3612 __le32 *rx_end;
3613 unsigned int skblen;
3614 u32 ampdu_status;
17e476b8 3615 u32 ampdu_status_legacy;
b481de9c
ZY		 3616
3617 if (!include_phy && priv->last_phy_res[0])
3618 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3619
3620 if (!rx_start) {
3621 IWL_ERROR("MPDU frame without a PHY data\n");
3622 return;
3623 }
3624 if (include_phy) {
3625 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
3626 rx_start->cfg_phy_cnt);
3627
3628 len = le16_to_cpu(rx_start->byte_count);
3629
3630 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
3631 sizeof(struct iwl4965_rx_phy_res) +
3632 rx_start->cfg_phy_cnt + len);
3633
3634 } else {
3635 struct iwl4965_rx_mpdu_res_start *amsdu =
3636 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3637
3638 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
3639 sizeof(struct iwl4965_rx_mpdu_res_start));
3640 len = le16_to_cpu(amsdu->byte_count);
3641 rx_start->byte_count = amsdu->byte_count;
3642 rx_end = (__le32 *) (((u8 *) hdr) + len);
3643 }
9ee1ba47 3644 if (len > priv->hw_setting.max_pkt_size || len < 16) {
12342c47 3645 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
b481de9c
ZY		 3646 return;
3647 }
3648
3649 ampdu_status = le32_to_cpu(*rx_end);
3650 skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
3651
17e476b8
EG		 3652 if (!include_phy) {
3653 /* New status scheme, need to translate */
3654 ampdu_status_legacy = ampdu_status;
3655 ampdu_status = iwl4965_translate_rx_status(ampdu_status);
3656 }
3657
b481de9c
ZY		 3658 /* start from MAC */
3659 skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
3660 skb_put(rxb->skb, len); /* end where data ends */
3661
3662 /* We only process data packets if the interface is open */
3663 if (unlikely(!priv->is_open)) {
3664 IWL_DEBUG_DROP_LIMIT
3665 ("Dropping packet while interface is not open.\n");
3666 return;
3667 }
3668
b481de9c
ZY		 3669 stats->flag = 0;
3670 hdr = (struct ieee80211_hdr *)rxb->skb->data;
3671
1ea87396 3672 if (priv->cfg->mod_params->hw_crypto)
bb8c093b 3673 iwl4965_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
b481de9c 3674
12342c47
ZY		 3675 if (priv->add_radiotap)
3676 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
3677
19758bef 3678 iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
b481de9c
ZY		 3679 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3680 priv->alloc_rxb_skb--;
3681 rxb->skb = NULL;
b481de9c
ZY		 3682}
3683
3684/* Calc max signal level (dBm) among 3 possible receivers */
3685static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
3686{
3687 /* data from PHY/DSP regarding signal strength, etc.,
3688 * contents are always there, not configurable by host. */
3689 struct iwl4965_rx_non_cfg_phy *ncphy =
3690 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
3691 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
3692 >> IWL_AGC_DB_POS;
3693
3694 u32 valid_antennae =
3695 (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
3696 >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
3697 u8 max_rssi = 0;
3698 u32 i;
3699
3700 /* Find max rssi among 3 possible receivers.
3701 * These values are measured by the digital signal processor (DSP).
3702 * They should stay fairly constant even as the signal strength varies,
3703 * if the radio's automatic gain control (AGC) is working right.
3704 * AGC value (see below) will provide the "interesting" info. */
3705 for (i = 0; i < 3; i++)
3706 if (valid_antennae & (1 << i))
3707 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
3708
3709 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
3710 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
3711 max_rssi, agc);
3712
3713 /* dBm = max_rssi dB - agc dB - constant.
3714 * Higher AGC (higher radio gain) means lower signal. */
3715 return (max_rssi - agc - IWL_RSSI_OFFSET);
3716}
3717
c8b0e6e1 3718#ifdef CONFIG_IWL4965_HT
b481de9c 3719
1ea87396
AK		 3720void iwl4965_init_ht_hw_capab(struct iwl_priv *priv,
3721 struct ieee80211_ht_info *ht_info,
78330fdd 3722 enum ieee80211_band band)
326eeee8
RR		 3723{
3724 ht_info->cap = 0;
3725 memset(ht_info->supp_mcs_set, 0, 16);
3726
3727 ht_info->ht_supported = 1;
3728
78330fdd 3729 if (band == IEEE80211_BAND_5GHZ) {
326eeee8
RR		 3730 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
3731 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
3732 ht_info->supp_mcs_set[4] = 0x01;
3733 }
3734 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
3735 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
3736 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
3737 (IWL_MIMO_PS_NONE << 2));
1ea87396
AK		 3738
3739 if (priv->cfg->mod_params->amsdu_size_8K)
9ee1ba47 3740 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
326eeee8
RR		 3741
3742 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3743 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3744
3745 ht_info->supp_mcs_set[0] = 0xFF;
3746 ht_info->supp_mcs_set[1] = 0xFF;
3747}
c8b0e6e1 3748#endif /* CONFIG_IWL4965_HT */
b481de9c 3749
c79dd5b5 3750static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
b481de9c
ZY		 3751{
3752 unsigned long flags;
3753
3754 spin_lock_irqsave(&priv->sta_lock, flags);
3755 priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
3756 priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3757 priv->stations[sta_id].sta.sta.modify_mask = 0;
3758 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3759 spin_unlock_irqrestore(&priv->sta_lock, flags);
3760
bb8c093b 3761 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 3762}
3763
c79dd5b5 3764static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
b481de9c
ZY		 3765{
3766 /* FIXME: need locking over ps_status ??? */
bb8c093b 3767 u8 sta_id = iwl4965_hw_find_station(priv, addr);
b481de9c
ZY		 3768
3769 if (sta_id != IWL_INVALID_STATION) {
3770 u8 sta_awake = priv->stations[sta_id].
3771 ps_status == STA_PS_STATUS_WAKE;
3772
3773 if (sta_awake && ps_bit)
3774 priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
3775 else if (!sta_awake && !ps_bit) {
3776 iwl4965_sta_modify_ps_wake(priv, sta_id);
3777 priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
3778 }
3779 }
3780}
0a6857e7 3781#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 3782
3783/**
3784 * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
3785 *
3786 * You may hack this function to show different aspects of received frames,
3787 * including selective frame dumps.
3788 * group100 parameter selects whether to show 1 out of 100 good frames.
3789 *
3790 * TODO: This was originally written for 3945, need to audit for
3791 * proper operation with 4965.
3792 */
c79dd5b5 3793static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3794 struct iwl4965_rx_packet *pkt,
3795 struct ieee80211_hdr *header, int group100)
3796{
3797 u32 to_us;
3798 u32 print_summary = 0;
3799 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
3800 u32 hundred = 0;
3801 u32 dataframe = 0;
3802 u16 fc;
3803 u16 seq_ctl;
3804 u16 channel;
3805 u16 phy_flags;
3806 int rate_sym;
3807 u16 length;
3808 u16 status;
3809 u16 bcn_tmr;
3810 u32 tsf_low;
3811 u64 tsf;
3812 u8 rssi;
3813 u8 agc;
3814 u16 sig_avg;
3815 u16 noise_diff;
3816 struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
3817 struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
3818 struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
3819 u8 *data = IWL_RX_DATA(pkt);
3820
0a6857e7 3821 if (likely(!(iwl_debug_level & IWL_DL_RX)))
17744ff6
TW		 3822 return;
3823
3824 /* MAC header */
3825 fc = le16_to_cpu(header->frame_control);
3826 seq_ctl = le16_to_cpu(header->seq_ctrl);
3827
3828 /* metadata */
3829 channel = le16_to_cpu(rx_hdr->channel);
3830 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3831 rate_sym = rx_hdr->rate;
3832 length = le16_to_cpu(rx_hdr->len);
3833
3834 /* end-of-frame status and timestamp */
3835 status = le32_to_cpu(rx_end->status);
3836 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3837 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3838 tsf = le64_to_cpu(rx_end->timestamp);
3839
3840 /* signal statistics */
3841 rssi = rx_stats->rssi;
3842 agc = rx_stats->agc;
3843 sig_avg = le16_to_cpu(rx_stats->sig_avg);
3844 noise_diff = le16_to_cpu(rx_stats->noise_diff);
3845
3846 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3847
3848 /* if data frame is to us and all is good,
3849 * (optionally) print summary for only 1 out of every 100 */
3850 if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3851 (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3852 dataframe = 1;
3853 if (!group100)
3854 print_summary = 1; /* print each frame */
3855 else if (priv->framecnt_to_us < 100) {
3856 priv->framecnt_to_us++;
3857 print_summary = 0;
3858 } else {
3859 priv->framecnt_to_us = 0;
3860 print_summary = 1;
3861 hundred = 1;
3862 }
3863 } else {
3864 /* print summary for all other frames */
3865 print_summary = 1;
3866 }
3867
3868 if (print_summary) {
3869 char *title;
3870 int rate_idx;
3871 u32 bitrate;
3872
3873 if (hundred)
3874 title = "100Frames";
3875 else if (fc & IEEE80211_FCTL_RETRY)
3876 title = "Retry";
3877 else if (ieee80211_is_assoc_response(fc))
3878 title = "AscRsp";
3879 else if (ieee80211_is_reassoc_response(fc))
3880 title = "RasRsp";
3881 else if (ieee80211_is_probe_response(fc)) {
3882 title = "PrbRsp";
3883 print_dump = 1; /* dump frame contents */
3884 } else if (ieee80211_is_beacon(fc)) {
3885 title = "Beacon";
3886 print_dump = 1; /* dump frame contents */
3887 } else if (ieee80211_is_atim(fc))
3888 title = "ATIM";
3889 else if (ieee80211_is_auth(fc))
3890 title = "Auth";
3891 else if (ieee80211_is_deauth(fc))
3892 title = "DeAuth";
3893 else if (ieee80211_is_disassoc(fc))
3894 title = "DisAssoc";
3895 else
3896 title = "Frame";
3897
3898 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3899 if (unlikely(rate_idx == -1))
3900 bitrate = 0;
3901 else
3902 bitrate = iwl4965_rates[rate_idx].ieee / 2;
3903
3904 /* print frame summary.
3905 * MAC addresses show just the last byte (for brevity),
3906 * but you can hack it to show more, if you'd like to. */
3907 if (dataframe)
3908 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3909 "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3910 title, fc, header->addr1[5],
3911 length, rssi, channel, bitrate);
3912 else {
3913 /* src/dst addresses assume managed mode */
3914 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3915 "src=0x%02x, rssi=%u, tim=%lu usec, "
3916 "phy=0x%02x, chnl=%d\n",
3917 title, fc, header->addr1[5],
3918 header->addr3[5], rssi,
3919 tsf_low - priv->scan_start_tsf,
3920 phy_flags, channel);
3921 }
3922 }
3923 if (print_dump)
0a6857e7 3924 iwl_print_hex_dump(IWL_DL_RX, data, length);
17744ff6
TW		 3925}
3926#else
c79dd5b5 3927static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
17744ff6
TW		 3928 struct iwl4965_rx_packet *pkt,
3929 struct ieee80211_hdr *header,
3930 int group100)
3931{
3932}
3933#endif
3934
b481de9c 3935
7878a5a4 3936
857485c0 3937/* Called for REPLY_RX (legacy ABG frames), or
b481de9c 3938 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
c79dd5b5 3939static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
bb8c093b 3940 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 3941{
17744ff6
TW		 3942 struct ieee80211_hdr *header;
3943 struct ieee80211_rx_status rx_status;
bb8c093b 3944 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 3945 /* Use phy data (Rx signal strength, etc.) contained within
3946 * this rx packet for legacy frames,
3947 * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
857485c0 3948 int include_phy = (pkt->hdr.cmd == REPLY_RX);
b481de9c
ZY		 3949 struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3950 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3951 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3952 __le32 *rx_end;
3953 unsigned int len = 0;
b481de9c 3954 u16 fc;
b481de9c
ZY		 3955 u8 network_packet;
3956
17744ff6 3957 rx_status.mactime = le64_to_cpu(rx_start->timestamp);
dc92e497
TW		 3958 rx_status.freq =
3959 ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
17744ff6
TW		 3960 rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3961 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
dc92e497
TW		 3962 rx_status.rate_idx =
3963 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
17744ff6
TW		 3964 if (rx_status.band == IEEE80211_BAND_5GHZ)
3965 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3966
3967 rx_status.antenna = 0;
3968 rx_status.flag = 0;
3969
b481de9c 3970 if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
dc92e497
TW		 3971 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
3972 rx_start->cfg_phy_cnt);
b481de9c
ZY		 3973 return;
3974 }
17744ff6 3975
b481de9c
ZY		 3976 if (!include_phy) {
3977 if (priv->last_phy_res[0])
3978 rx_start = (struct iwl4965_rx_phy_res *)
3979 &priv->last_phy_res[1];
3980 else
3981 rx_start = NULL;
3982 }
3983
3984 if (!rx_start) {
3985 IWL_ERROR("MPDU frame without a PHY data\n");
3986 return;
3987 }
3988
3989 if (include_phy) {
3990 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3991 + rx_start->cfg_phy_cnt);
3992
3993 len = le16_to_cpu(rx_start->byte_count);
17744ff6 3994 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
b481de9c
ZY		 3995 sizeof(struct iwl4965_rx_phy_res) + len);
3996 } else {
3997 struct iwl4965_rx_mpdu_res_start *amsdu =
3998 (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3999
4000 header = (void *)(pkt->u.raw +
4001 sizeof(struct iwl4965_rx_mpdu_res_start));
4002 len = le16_to_cpu(amsdu->byte_count);
4003 rx_end = (__le32 *) (pkt->u.raw +
4004 sizeof(struct iwl4965_rx_mpdu_res_start) + len);
4005 }
4006
4007 if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
4008 !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
4009 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
4010 le32_to_cpu(*rx_end));
4011 return;
4012 }
4013
4014 priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
4015
b481de9c 4016 /* Find max signal strength (dBm) among 3 antenna/receiver chains */
17744ff6 4017 rx_status.ssi = iwl4965_calc_rssi(rx_start);
b481de9c
ZY		 4018
4019 /* Meaningful noise values are available only from beacon statistics,
4020 * which are gathered only when associated, and indicate noise
4021 * only for the associated network channel ...
4022 * Ignore these noise values while scanning (other channels) */
3109ece1 4023 if (iwl_is_associated(priv) &&
b481de9c 4024 !test_bit(STATUS_SCANNING, &priv->status)) {
17744ff6
TW		 4025 rx_status.noise = priv->last_rx_noise;
4026 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
4027 rx_status.noise);
b481de9c 4028 } else {
17744ff6
TW		 4029 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
4030 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
b481de9c
ZY		 4031 }
4032
4033 /* Reset beacon noise level if not associated. */
3109ece1 4034 if (!iwl_is_associated(priv))
b481de9c
ZY		 4035 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
4036
17744ff6
TW		 4037 /* Set "1" to report good data frames in groups of 100 */
4038 /* FIXME: need to optimze the call: */
4039 iwl4965_dbg_report_frame(priv, pkt, header, 1);
4040
4041 IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
4042 rx_status.ssi, rx_status.noise, rx_status.signal,
06501d29 4043 (unsigned long long)rx_status.mactime);
b481de9c 4044
bb8c093b 4045 network_packet = iwl4965_is_network_packet(priv, header);
b481de9c 4046 if (network_packet) {
17744ff6 4047 priv->last_rx_rssi = rx_status.ssi;
b481de9c
ZY		 4048 priv->last_beacon_time = priv->ucode_beacon_time;
4049 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
4050 }
4051
4052 fc = le16_to_cpu(header->frame_control);
4053 switch (fc & IEEE80211_FCTL_FTYPE) {
4054 case IEEE80211_FTYPE_MGMT:
b481de9c
ZY		 4055 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
4056 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
4057 header->addr2);
17744ff6 4058 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
b481de9c
ZY		 4059 break;
4060
4061 case IEEE80211_FTYPE_CTL:
9ab46173 4062#ifdef CONFIG_IWL4965_HT
b481de9c
ZY		 4063 switch (fc & IEEE80211_FCTL_STYPE) {
4064 case IEEE80211_STYPE_BACK_REQ:
4065 IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
4066 iwl4965_handle_data_packet(priv, 0, include_phy,
17744ff6 4067 rxb, &rx_status);
b481de9c
ZY		 4068 break;
4069 default:
4070 break;
4071 }
4072#endif
b481de9c
ZY		 4073 break;
4074
0795af57
JP		 4075 case IEEE80211_FTYPE_DATA: {
4076 DECLARE_MAC_BUF(mac1);
4077 DECLARE_MAC_BUF(mac2);
4078 DECLARE_MAC_BUF(mac3);
4079
b481de9c
ZY		 4080 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
4081 iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
4082 header->addr2);
4083
4084 if (unlikely(!network_packet))
4085 IWL_DEBUG_DROP("Dropping (non network): "
0795af57
JP		 4086 "%s, %s, %s\n",
4087 print_mac(mac1, header->addr1),
4088 print_mac(mac2, header->addr2),
4089 print_mac(mac3, header->addr3));
bb8c093b 4090 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
0795af57
JP		 4091 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
4092 print_mac(mac1, header->addr1),
4093 print_mac(mac2, header->addr2),
4094 print_mac(mac3, header->addr3));
b481de9c
ZY		 4095 else
4096 iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
17744ff6 4097 &rx_status);
b481de9c 4098 break;
0795af57 4099 }
b481de9c
ZY		 4100 default:
4101 break;
4102
4103 }
4104}
4105
4106/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
4107 * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
c79dd5b5 4108static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
bb8c093b 4109 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 4110{
bb8c093b 4111 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c
ZY		 4112 priv->last_phy_res[0] = 1;
4113 memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
4114 sizeof(struct iwl4965_rx_phy_res));
4115}
c79dd5b5 4116static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
bb8c093b 4117 struct iwl4965_rx_mem_buffer *rxb)
b481de9c
ZY		 4118
4119{
c8b0e6e1 4120#ifdef CONFIG_IWL4965_SENSITIVITY
bb8c093b
CH		 4121 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
4122 struct iwl4965_missed_beacon_notif *missed_beacon;
b481de9c
ZY		 4123
4124 missed_beacon = &pkt->u.missed_beacon;
4125 if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
4126 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
4127 le32_to_cpu(missed_beacon->consequtive_missed_beacons),
4128 le32_to_cpu(missed_beacon->total_missed_becons),
4129 le32_to_cpu(missed_beacon->num_recvd_beacons),
4130 le32_to_cpu(missed_beacon->num_expected_beacons));
4131 priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
4132 if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)))
4133 queue_work(priv->workqueue, &priv->sensitivity_work);
4134 }
c8b0e6e1 4135#endif /*CONFIG_IWL4965_SENSITIVITY*/
b481de9c 4136}
c8b0e6e1 4137#ifdef CONFIG_IWL4965_HT
b481de9c 4138
8b6eaea8
CB		 4139/**
4140 * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
4141 */
c79dd5b5 4142static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
b481de9c
ZY		 4143 int sta_id, int tid)
4144{
4145 unsigned long flags;
4146
8b6eaea8 4147 /* Remove "disable" flag, to enable Tx for this TID */
b481de9c
ZY		 4148 spin_lock_irqsave(&priv->sta_lock, flags);
4149 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
4150 priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
4151 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4152 spin_unlock_irqrestore(&priv->sta_lock, flags);
4153
bb8c093b 4154 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 4155}
4156
8b6eaea8
CB		 4157/**
4158 * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
4159 *
4160 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
4161 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
4162 */
c79dd5b5 4163static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b
CH		 4164 struct iwl4965_ht_agg *agg,
4165 struct iwl4965_compressed_ba_resp*
b481de9c
ZY		 4166 ba_resp)
4167
4168{
4169 int i, sh, ack;
fe01b477
RR		 4170 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
4171 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
4172 u64 bitmap;
4173 int successes = 0;
4174 struct ieee80211_tx_status *tx_status;
b481de9c
ZY		 4175
4176 if (unlikely(!agg->wait_for_ba)) {
4177 IWL_ERROR("Received BA when not expected\n");
4178 return -EINVAL;
4179 }
8b6eaea8
CB		 4180
4181 /* Mark that the expected block-ack response arrived */
b481de9c 4182 agg->wait_for_ba = 0;
fe01b477 4183 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
8b6eaea8
CB		 4184
4185 /* Calculate shift to align block-ack bits with our Tx window bits */
fe01b477 4186 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
01ebd063 4187 if (sh < 0) /* tbw something is wrong with indices */
b481de9c
ZY		 4188 sh += 0x100;
4189
8b6eaea8 4190 /* don't use 64-bit values for now */
fe01b477 4191 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
b481de9c
ZY		 4192
4193 if (agg->frame_count > (64 - sh)) {
4194 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
4195 return -1;
4196 }
4197
4198 /* check for success or failure according to the
8b6eaea8 4199 * transmitted bitmap and block-ack bitmap */
fe01b477 4200 bitmap &= agg->bitmap;
b481de9c 4201
8b6eaea8
CB		 4202 /* For each frame attempted in aggregation,
4203 * update driver's record of tx frame's status. */
b481de9c 4204 for (i = 0; i < agg->frame_count ; i++) {
fe01b477
RR		 4205 ack = bitmap & (1 << i);
4206 successes += !!ack;
b481de9c 4207 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
fe01b477
RR		 4208 ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
4209 agg->start_idx + i);
4210 }
4211
4212 tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
4213 tx_status->flags = IEEE80211_TX_STATUS_ACK;
99556438
RR		 4214 tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
4215 tx_status->ampdu_ack_map = successes;
4216 tx_status->ampdu_ack_len = agg->frame_count;
4c424e4c
RR		 4217 iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
4218 &tx_status->control);
fe01b477 4219
f868f4e1 4220 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
fe01b477
RR		 4221
4222 return 0;
4223}
4224
4225/**
4226 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
4227 */
c79dd5b5 4228static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 4229 u16 txq_id)
4230{
4231 /* Simply stop the queue, but don't change any configuration;
4232 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3395f6e9 4233 iwl_write_prph(priv,
12a81f60 4234 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
fe01b477
RR		 4235 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
4236 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
4237}
b481de9c 4238
fe01b477
RR		 4239/**
4240 * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
b095d03a 4241 * priv->lock must be held by the caller
fe01b477 4242 */
c79dd5b5 4243static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
fe01b477
RR		 4244 u16 ssn_idx, u8 tx_fifo)
4245{
b095d03a
RR		 4246 int ret = 0;
4247
fe01b477
RR		 4248 if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
4249 IWL_WARNING("queue number too small: %d, must be > %d\n",
4250 txq_id, IWL_BACK_QUEUE_FIRST_ID);
4251 return -EINVAL;
b481de9c
ZY		 4252 }
4253
3395f6e9 4254 ret = iwl_grab_nic_access(priv);
b095d03a
RR		 4255 if (ret)
4256 return ret;
4257
fe01b477
RR		 4258 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
4259
12a81f60 4260 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
fe01b477
RR		 4261
4262 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4263 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
4264 /* supposes that ssn_idx is valid (!= 0xFFF) */
4265 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4266
12a81f60 4267 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
fe01b477
RR		 4268 iwl4965_txq_ctx_deactivate(priv, txq_id);
4269 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
4270
3395f6e9 4271 iwl_release_nic_access(priv);
b095d03a 4272
fe01b477
RR		 4273 return 0;
4274}
b481de9c 4275
c79dd5b5 4276int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
fe01b477
RR		 4277 u8 tid, int txq_id)
4278{
4279 struct iwl4965_queue *q = &priv->txq[txq_id].q;
4280 u8 *addr = priv->stations[sta_id].sta.sta.addr;
4281 struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
4282
4283 switch (priv->stations[sta_id].tid[tid].agg.state) {
4284 case IWL_EMPTYING_HW_QUEUE_DELBA:
4285 /* We are reclaiming the last packet of the */
4286 /* aggregated HW queue */
4287 if (txq_id == tid_data->agg.txq_id &&
4288 q->read_ptr == q->write_ptr) {
4289 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
4290 int tx_fifo = default_tid_to_tx_fifo[tid];
4291 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
4292 iwl4965_tx_queue_agg_disable(priv, txq_id,
4293 ssn, tx_fifo);
4294 tid_data->agg.state = IWL_AGG_OFF;
4295 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
4296 }
4297 break;
4298 case IWL_EMPTYING_HW_QUEUE_ADDBA:
4299 /* We are reclaiming the last packet of the queue */
4300 if (tid_data->tfds_in_queue == 0) {
4301 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
4302 tid_data->agg.state = IWL_AGG_ON;
4303 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
4304 }
4305 break;
4306 }
b481de9c
ZY		 4307 return 0;
4308}
4309
8b6eaea8
CB		 4310/**
4311 * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
4312 * @index -- current index
4313 * @n_bd -- total number of entries in queue (s/b power of 2)
4314 */
bb8c093b 4315static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
b481de9c
ZY		 4316{
4317 return (index == 0) ? n_bd - 1 : index - 1;
4318}
4319
8b6eaea8
CB		 4320/**
4321 * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
4322 *
4323 * Handles block-acknowledge notification from device, which reports success
4324 * of frames sent via aggregation.
4325 */
c79dd5b5 4326static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
bb8c093b 4327 struct iwl4965_rx_mem_buffer *rxb)
b481de9c 4328{
bb8c093b
CH		 4329 struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
4330 struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
b481de9c 4331 int index;
bb8c093b
CH		 4332 struct iwl4965_tx_queue *txq = NULL;
4333 struct iwl4965_ht_agg *agg;
fe01b477 4334 DECLARE_MAC_BUF(mac);
8b6eaea8
CB		 4335
4336 /* "flow" corresponds to Tx queue */
fe01b477 4337 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
8b6eaea8
CB		 4338
4339 /* "ssn" is start of block-ack Tx window, corresponds to index
4340 * (in Tx queue's circular buffer) of first TFD/frame in window */
b481de9c
ZY		 4341 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
4342
fe01b477 4343 if (scd_flow >= ARRAY_SIZE(priv->txq)) {
b481de9c
ZY		 4344 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
4345 return;
4346 }
4347
fe01b477 4348 txq = &priv->txq[scd_flow];
b481de9c 4349 agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
8b6eaea8
CB		 4350
4351 /* Find index just before block-ack window */
bb8c093b 4352 index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
b481de9c 4353
01ebd063 4354 /* TODO: Need to get this copy more safely - now good for debug */
fe01b477 4355
0795af57
JP		 4356 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
4357 "sta_id = %d\n",
b481de9c 4358 agg->wait_for_ba,
0795af57 4359 print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
b481de9c 4360 ba_resp->sta_id);
fe01b477 4361 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
b481de9c
ZY		 4362 "%d, scd_ssn = %d\n",
4363 ba_resp->tid,
fe01b477 4364 ba_resp->seq_ctl,
0310ae72 4365 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
b481de9c
ZY		 4366 ba_resp->scd_flow,
4367 ba_resp->scd_ssn);
fe01b477 4368 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
b481de9c 4369 agg->start_idx,
f868f4e1 4370 (unsigned long long)agg->bitmap);
8b6eaea8
CB		 4371
4372 /* Update driver's record of ACK vs. not for each frame in window */
b481de9c 4373 iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
8b6eaea8
CB		 4374
4375 /* Release all TFDs before the SSN, i.e. all TFDs in front of
4376 * block-ack window (we assume that they've been successfully
4377 * transmitted ... if not, it's too late anyway). */
fe01b477
RR		 4378 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
4379 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
4380 priv->stations[ba_resp->sta_id].
4381 tid[ba_resp->tid].tfds_in_queue -= freed;
4382 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
4383 priv->mac80211_registered &&
4384 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
4385 ieee80211_wake_queue(priv->hw, scd_flow);
4386 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
4387 ba_resp->tid, scd_flow);
4388 }
b481de9c
ZY		 4389}
4390
8b6eaea8
CB		 4391/**
4392 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
4393 */
c79dd5b5 4394static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 4395 u16 txq_id)
4396{
4397 u32 tbl_dw_addr;
4398 u32 tbl_dw;
4399 u16 scd_q2ratid;
4400
4401 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
4402
4403 tbl_dw_addr = priv->scd_base_addr +
4404 SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
4405
3395f6e9 4406 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 4407
4408 if (txq_id & 0x1)
4409 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
4410 else
4411 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
4412
3395f6e9 4413 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 4414
4415 return 0;
4416}
4417
fe01b477 4418
b481de9c 4419/**
8b6eaea8
CB		 4420 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
4421 *
4422 * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
4423 * i.e. it must be one of the higher queues used for aggregation
b481de9c 4424 */
c79dd5b5 4425static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
b481de9c
ZY		 4426 int tx_fifo, int sta_id, int tid,
4427 u16 ssn_idx)
4428{
4429 unsigned long flags;
4430 int rc;
4431 u16 ra_tid;
4432
4433 if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
4434 IWL_WARNING("queue number too small: %d, must be > %d\n",
4435 txq_id, IWL_BACK_QUEUE_FIRST_ID);
4436
4437 ra_tid = BUILD_RAxTID(sta_id, tid);
4438
8b6eaea8 4439 /* Modify device's station table to Tx this TID */
bb8c093b 4440 iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
b481de9c
ZY		 4441
4442 spin_lock_irqsave(&priv->lock, flags);
3395f6e9 4443 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 4444 if (rc) {
4445 spin_unlock_irqrestore(&priv->lock, flags);
4446 return rc;
4447 }
4448
8b6eaea8 4449 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 4450 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
4451
8b6eaea8 4452 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 4453 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
4454
8b6eaea8 4455 /* Set this queue as a chain-building queue */
12a81f60 4456 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 4457
8b6eaea8
CB		 4458 /* Place first TFD at index corresponding to start sequence number.
4459 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 4460 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4461 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 4462 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4463
8b6eaea8 4464 /* Set up Tx window size and frame limit for this queue */
3395f6e9 4465 iwl_write_targ_mem(priv,
b481de9c
ZY		 4466 priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
4467 (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
4468 SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
4469
3395f6e9 4470 iwl_write_targ_mem(priv, priv->scd_base_addr +
b481de9c
ZY		 4471 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
4472 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
4473 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
4474
12a81f60 4475 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 4476
8b6eaea8 4477 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 4478 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
4479
3395f6e9 4480 iwl_release_nic_access(priv);
b481de9c
ZY		 4481 spin_unlock_irqrestore(&priv->lock, flags);
4482
4483 return 0;
4484}
4485
c8b0e6e1 4486#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4487
4488/**
4489 * iwl4965_add_station - Initialize a station's hardware rate table
4490 *
8b6eaea8 4491 * The uCode's station table contains a table of fallback rates
b481de9c
ZY		 4492 * for automatic fallback during transmission.
4493 *
8b6eaea8
CB		 4494 * NOTE: This sets up a default set of values. These will be replaced later
4495 * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
4496 * rc80211_simple.
b481de9c 4497 *
8b6eaea8
CB		 4498 * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
4499 * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
4500 * which requires station table entry to exist).
b481de9c 4501 */
c79dd5b5 4502void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
b481de9c
ZY		 4503{
4504 int i, r;
bb8c093b 4505 struct iwl4965_link_quality_cmd link_cmd = {
b481de9c
ZY		 4506 .reserved1 = 0,
4507 };
4508 u16 rate_flags;
4509
8b6eaea8
CB		 4510 /* Set up the rate scaling to start at selected rate, fall back
4511 * all the way down to 1M in IEEE order, and then spin on 1M */
b481de9c
ZY		 4512 if (is_ap)
4513 r = IWL_RATE_54M_INDEX;
8318d78a 4514 else if (priv->band == IEEE80211_BAND_5GHZ)
b481de9c
ZY		 4515 r = IWL_RATE_6M_INDEX;
4516 else
4517 r = IWL_RATE_1M_INDEX;
4518
4519 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
4520 rate_flags = 0;
4521 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
4522 rate_flags |= RATE_MCS_CCK_MSK;
4523
8b6eaea8 4524 /* Use Tx antenna B only */
b481de9c
ZY		 4525 rate_flags |= RATE_MCS_ANT_B_MSK;
4526 rate_flags &= ~RATE_MCS_ANT_A_MSK;
8b6eaea8 4527
b481de9c 4528 link_cmd.rs_table[i].rate_n_flags =
bb8c093b
CH		 4529 iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
4530 r = iwl4965_get_prev_ieee_rate(r);
b481de9c
ZY		 4531 }
4532
4533 link_cmd.general_params.single_stream_ant_msk = 2;
4534 link_cmd.general_params.dual_stream_ant_msk = 3;
4535 link_cmd.agg_params.agg_dis_start_th = 3;
4536 link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
4537
4538 /* Update the rate scaling for control frame Tx to AP */
a4062b8f 4539 link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_setting.bcast_sta_id;
b481de9c 4540
e5472978
TW		 4541 iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
4542 sizeof(link_cmd), &link_cmd, NULL);
b481de9c
ZY		 4543}
4544
c8b0e6e1 4545#ifdef CONFIG_IWL4965_HT
b481de9c 4546
c79dd5b5 4547static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
8318d78a 4548 enum ieee80211_band band,
78330fdd 4549 u16 channel, u8 extension_chan_offset)
b481de9c 4550{
bf85ea4f 4551 const struct iwl_channel_info *ch_info;
b481de9c 4552
8622e705 4553 ch_info = iwl_get_channel_info(priv, band, channel);
b481de9c
ZY		 4554 if (!is_channel_valid(ch_info))
4555 return 0;
4556
134eb5d3 4557 if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
b481de9c
ZY		 4558 return 0;
4559
4560 if ((ch_info->fat_extension_channel == extension_chan_offset) ||
4561 (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
4562 return 1;
4563
4564 return 0;
4565}
4566
c79dd5b5 4567static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
fd105e79 4568 struct ieee80211_ht_info *sta_ht_inf)
b481de9c 4569{
fd105e79 4570 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
b481de9c 4571
fd105e79
RR		 4572 if ((!iwl_ht_conf->is_ht) ||
4573 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
134eb5d3 4574 (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
b481de9c
ZY		 4575 return 0;
4576
fd105e79
RR		 4577 if (sta_ht_inf) {
4578 if ((!sta_ht_inf->ht_supported) ||
194c7ca6 4579 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
fd105e79
RR		 4580 return 0;
4581 }
b481de9c 4582
78330fdd 4583 return (iwl4965_is_channel_extension(priv, priv->band,
fd105e79
RR		 4584 iwl_ht_conf->control_channel,
4585 iwl_ht_conf->extension_chan_offset));
b481de9c
ZY		 4586}
4587
c79dd5b5 4588void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
b481de9c 4589{
bb8c093b 4590 struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
b481de9c
ZY		 4591 u32 val;
4592
4593 if (!ht_info->is_ht)
4594 return;
4595
8b6eaea8 4596 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
fd105e79 4597 if (iwl4965_is_fat_tx_allowed(priv, NULL))
b481de9c
ZY		 4598 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4599 else
4600 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
4601 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
4602
4603 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
4604 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
4605 le16_to_cpu(rxon->channel),
4606 ht_info->control_channel);
4607 rxon->channel = cpu_to_le16(ht_info->control_channel);
4608 return;
4609 }
4610
8b6eaea8 4611 /* Note: control channel is opposite of extension channel */
b481de9c
ZY		 4612 switch (ht_info->extension_chan_offset) {
4613 case IWL_EXT_CHANNEL_OFFSET_ABOVE:
4614 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
4615 break;
4616 case IWL_EXT_CHANNEL_OFFSET_BELOW:
4617 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
4618 break;
134eb5d3 4619 case IWL_EXT_CHANNEL_OFFSET_NONE:
b481de9c
ZY		 4620 default:
4621 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
4622 break;
4623 }
4624
fd105e79 4625 val = ht_info->ht_protection;
b481de9c
ZY		 4626
4627 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
4628
b481de9c
ZY		 4629 iwl4965_set_rxon_chain(priv);
4630
4631 IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
4632 "rxon flags 0x%X operation mode :0x%X "
4633 "extension channel offset 0x%x "
4634 "control chan %d\n",
fd105e79
RR		 4635 ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1],
4636 le32_to_cpu(rxon->flags), ht_info->ht_protection,
b481de9c
ZY		 4637 ht_info->extension_chan_offset,
4638 ht_info->control_channel);
4639 return;
4640}
4641
c79dd5b5 4642void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
67d62035 4643 struct ieee80211_ht_info *sta_ht_inf)
b481de9c
ZY		 4644{
4645 __le32 sta_flags;
e53cfe0e 4646 u8 mimo_ps_mode;
b481de9c 4647
67d62035 4648 if (!sta_ht_inf || !sta_ht_inf->ht_supported)
b481de9c
ZY		 4649 goto done;
4650
e53cfe0e
TW		 4651 mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
4652
b481de9c
ZY		 4653 sta_flags = priv->stations[index].sta.station_flags;
4654
e53cfe0e
TW		 4655 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
4656
4657 switch (mimo_ps_mode) {
4658 case WLAN_HT_CAP_MIMO_PS_STATIC:
4659 sta_flags |= STA_FLG_MIMO_DIS_MSK;
4660 break;
4661 case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
b481de9c 4662 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
e53cfe0e
TW		 4663 break;
4664 case WLAN_HT_CAP_MIMO_PS_DISABLED:
4665 break;
4666 default:
4667 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
4668 break;
4669 }
b481de9c
ZY		 4670
4671 sta_flags |= cpu_to_le32(
67d62035 4672 (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
b481de9c
ZY		 4673
4674 sta_flags |= cpu_to_le32(
67d62035 4675 (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
b481de9c 4676
67d62035 4677 if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
b481de9c 4678 sta_flags |= STA_FLG_FAT_EN_MSK;
67d62035 4679 else
e53cfe0e 4680 sta_flags &= ~STA_FLG_FAT_EN_MSK;
67d62035 4681
b481de9c
ZY		 4682 priv->stations[index].sta.station_flags = sta_flags;
4683 done:
4684 return;
4685}
4686
c79dd5b5 4687static void iwl4965_sta_modify_add_ba_tid(struct iwl_priv *priv,
b481de9c
ZY		 4688 int sta_id, int tid, u16 ssn)
4689{
4690 unsigned long flags;
4691
4692 spin_lock_irqsave(&priv->sta_lock, flags);
4693 priv->stations[sta_id].sta.station_flags_msk = 0;
4694 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
4695 priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
4696 priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
4697 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4698 spin_unlock_irqrestore(&priv->sta_lock, flags);
4699
bb8c093b 4700 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 4701}
4702
c79dd5b5 4703static void iwl4965_sta_modify_del_ba_tid(struct iwl_priv *priv,
b481de9c
ZY		 4704 int sta_id, int tid)
4705{
4706 unsigned long flags;
4707
4708 spin_lock_irqsave(&priv->sta_lock, flags);
4709 priv->stations[sta_id].sta.station_flags_msk = 0;
4710 priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
4711 priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
4712 priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4713 spin_unlock_irqrestore(&priv->sta_lock, flags);
4714
bb8c093b 4715 iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
b481de9c
ZY		 4716}
4717
8b6eaea8
CB		 4718/*
4719 * Find first available (lowest unused) Tx Queue, mark it "active".
4720 * Called only when finding queue for aggregation.
4721 * Should never return anything < 7, because they should already
4722 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
4723 */
c79dd5b5 4724static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
b481de9c
ZY		 4725{
4726 int txq_id;
4727
4728 for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
4729 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
4730 return txq_id;
4731 return -1;
4732}
4733
fe01b477
RR		 4734static int iwl4965_mac_ht_tx_agg_start(struct ieee80211_hw *hw, const u8 *da,
4735 u16 tid, u16 *start_seq_num)
b481de9c 4736{
c79dd5b5 4737 struct iwl_priv *priv = hw->priv;
b481de9c
ZY		 4738 int sta_id;
4739 int tx_fifo;
4740 int txq_id;
4741 int ssn = -1;
b095d03a 4742 int ret = 0;
b481de9c 4743 unsigned long flags;
bb8c093b 4744 struct iwl4965_tid_data *tid_data;
0795af57 4745 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 4746
4747 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4748 tx_fifo = default_tid_to_tx_fifo[tid];
4749 else
4750 return -EINVAL;
4751
fe01b477
RR		 4752 IWL_WARNING("%s on da = %s tid = %d\n",
4753 __func__, print_mac(mac, da), tid);
b481de9c 4754
bb8c093b 4755 sta_id = iwl4965_hw_find_station(priv, da);
b481de9c
ZY		 4756 if (sta_id == IWL_INVALID_STATION)
4757 return -ENXIO;
4758
fe01b477
RR		 4759 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
4760 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
4761 return -ENXIO;
4762 }
4763
bb8c093b 4764 txq_id = iwl4965_txq_ctx_activate_free(priv);
b481de9c
ZY		 4765 if (txq_id == -1)
4766 return -ENXIO;
4767
4768 spin_lock_irqsave(&priv->sta_lock, flags);
4769 tid_data = &priv->stations[sta_id].tid[tid];
4770 ssn = SEQ_TO_SN(tid_data->seq_number);
4771 tid_data->agg.txq_id = txq_id;
4772 spin_unlock_irqrestore(&priv->sta_lock, flags);
4773
4774 *start_seq_num = ssn;
b095d03a
RR		 4775 ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
4776 sta_id, tid, ssn);
4777 if (ret)
4778 return ret;
b481de9c 4779
b095d03a 4780 ret = 0;
fe01b477
RR		 4781 if (tid_data->tfds_in_queue == 0) {
4782 printk(KERN_ERR "HW queue is empty\n");
4783 tid_data->agg.state = IWL_AGG_ON;
4784 ieee80211_start_tx_ba_cb_irqsafe(hw, da, tid);
4785 } else {
4786 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
4787 tid_data->tfds_in_queue);
4788 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
4789 }
b095d03a 4790 return ret;
fe01b477 4791}
b481de9c 4792
fe01b477
RR		 4793static int iwl4965_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, const u8 *da,
4794 u16 tid)
b481de9c
ZY		 4795{
4796
c79dd5b5 4797 struct iwl_priv *priv = hw->priv;
b481de9c 4798 int tx_fifo_id, txq_id, sta_id, ssn = -1;
bb8c093b 4799 struct iwl4965_tid_data *tid_data;
b095d03a 4800 int ret, write_ptr, read_ptr;
fe01b477 4801 unsigned long flags;
0795af57
JP		 4802 DECLARE_MAC_BUF(mac);
4803
b481de9c 4804 if (!da) {
fe01b477 4805 IWL_ERROR("da = NULL\n");
b481de9c
ZY		 4806 return -EINVAL;
4807 }
4808
4809 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4810 tx_fifo_id = default_tid_to_tx_fifo[tid];
4811 else
4812 return -EINVAL;
4813
bb8c093b 4814 sta_id = iwl4965_hw_find_station(priv, da);
b481de9c
ZY		 4815
4816 if (sta_id == IWL_INVALID_STATION)
4817 return -ENXIO;
4818
fe01b477
RR		 4819 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4820 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4821
b481de9c
ZY		 4822 tid_data = &priv->stations[sta_id].tid[tid];
4823 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4824 txq_id = tid_data->agg.txq_id;
fe01b477
RR		 4825 write_ptr = priv->txq[txq_id].q.write_ptr;
4826 read_ptr = priv->txq[txq_id].q.read_ptr;
4827
4828 /* The queue is not empty */
4829 if (write_ptr != read_ptr) {
4830 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4831 priv->stations[sta_id].tid[tid].agg.state =
4832 IWL_EMPTYING_HW_QUEUE_DELBA;
4833 return 0;
4834 }
4835
4836 IWL_DEBUG_HT("HW queue empty\n");;
4837 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
b481de9c 4838
fe01b477 4839 spin_lock_irqsave(&priv->lock, flags);
b095d03a 4840 ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
fe01b477
RR		 4841 spin_unlock_irqrestore(&priv->lock, flags);
4842
b095d03a
RR		 4843 if (ret)
4844 return ret;
b481de9c 4845
fe01b477 4846 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, da, tid);
b481de9c 4847
fe01b477
RR		 4848 IWL_DEBUG_INFO("iwl4965_mac_ht_tx_agg_stop on da=%s tid=%d\n",
4849 print_mac(mac, da), tid);
8114fcf1 4850
8114fcf1
RR		 4851 return 0;
4852}
4853
4854int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4855 enum ieee80211_ampdu_mlme_action action,
4856 const u8 *addr, u16 tid, u16 *ssn)
4857{
c79dd5b5 4858 struct iwl_priv *priv = hw->priv;
8114fcf1
RR		 4859 int sta_id;
4860 DECLARE_MAC_BUF(mac);
4861
4862 IWL_DEBUG_HT("A-MPDU action on da=%s tid=%d ",
4863 print_mac(mac, addr), tid);
4864 sta_id = iwl4965_hw_find_station(priv, addr);
4865 switch (action) {
4866 case IEEE80211_AMPDU_RX_START:
4867 IWL_DEBUG_HT("start Rx\n");
4868 iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, *ssn);
4869 break;
4870 case IEEE80211_AMPDU_RX_STOP:
4871 IWL_DEBUG_HT("stop Rx\n");
4872 iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid);
4873 break;
4874 case IEEE80211_AMPDU_TX_START:
4875 IWL_DEBUG_HT("start Tx\n");
4876 return iwl4965_mac_ht_tx_agg_start(hw, addr, tid, ssn);
4877 case IEEE80211_AMPDU_TX_STOP:
4878 IWL_DEBUG_HT("stop Tx\n");
4879 return iwl4965_mac_ht_tx_agg_stop(hw, addr, tid);
4880 default:
4881 IWL_DEBUG_HT("unknown\n");
4882 return -EINVAL;
4883 break;
4884 }
4885 return 0;
4886}
4887
c8b0e6e1 4888#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4889
4890/* Set up 4965-specific Rx frame reply handlers */
c79dd5b5 4891void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 4892{
4893 /* Legacy Rx frames */
857485c0 4894 priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
b481de9c
ZY		 4895
4896 /* High-throughput (HT) Rx frames */
4897 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4898 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4899
4900 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4901 iwl4965_rx_missed_beacon_notif;
4902
c8b0e6e1 4903#ifdef CONFIG_IWL4965_HT
b481de9c 4904 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
c8b0e6e1 4905#endif /* CONFIG_IWL4965_HT */
b481de9c
ZY		 4906}
4907
c79dd5b5 4908void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4909{
4910 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
4911 INIT_WORK(&priv->statistics_work, iwl4965_bg_statistics_work);
c8b0e6e1 4912#ifdef CONFIG_IWL4965_SENSITIVITY
b481de9c
ZY		 4913 INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4914#endif
b481de9c
ZY		 4915 init_timer(&priv->statistics_periodic);
4916 priv->statistics_periodic.data = (unsigned long)priv;
4917 priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4918}
4919
c79dd5b5 4920void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 4921{
4922 del_timer_sync(&priv->statistics_periodic);
4923
4924 cancel_delayed_work(&priv->init_alive_start);
4925}
4926
857485c0
TW		 4927static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
4928 .enqueue_hcmd = iwl4965_enqueue_hcmd,
4929};
4930
6bc913bd 4931static struct iwl_lib_ops iwl4965_lib = {
bf85ea4f 4932 .init_drv = iwl4965_init_drv,
e2a722eb 4933 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
57aab75a
TW		 4934 .hw_nic_init = iwl4965_hw_nic_init,
4935 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
4936 .alive_notify = iwl4965_alive_notify,
4937 .load_ucode = iwl4965_load_bsm,
6bc913bd
AK		 4938 .eeprom_ops = {
4939 .verify_signature = iwlcore_eeprom_verify_signature,
4940 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4941 .release_semaphore = iwlcore_eeprom_release_semaphore,
4942 },
ad97edd2 4943 .radio_kill_sw = iwl4965_radio_kill_sw,
6bc913bd
AK		 4944};
4945
4946static struct iwl_ops iwl4965_ops = {
4947 .lib = &iwl4965_lib,
857485c0 4948 .utils = &iwl4965_hcmd_utils,
6bc913bd
AK		 4949};
4950
82b9a121
TW		 4951static struct iwl_cfg iwl4965_agn_cfg = {
4952 .name = "4965AGN",
4bf775cd 4953 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
82b9a121 4954 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
6bc913bd 4955 .ops = &iwl4965_ops,
1ea87396 4956 .mod_params = &iwl4965_mod_params,
82b9a121
TW		 4957};
4958
bb8c093b 4959struct pci_device_id iwl4965_hw_card_ids[] = {
82b9a121
TW		 4960 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
4961 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
b481de9c
ZY		 4962 {0}
4963};
4964
bb8c093b 4965MODULE_DEVICE_TABLE(pci, iwl4965_hw_card_ids);
1ea87396
AK		 4966
4967module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
4968MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4969module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
4970MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
4971module_param_named(hwcrypto, iwl4965_mod_params.hw_crypto, int, 0444);
4972MODULE_PARM_DESC(hwcrypto,
4973 "using hardware crypto engine (default 0 [software])\n");
4974module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
4975MODULE_PARM_DESC(debug, "debug output mask");
4976module_param_named(
4977 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
4978MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4979
4980module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
4981MODULE_PARM_DESC(queues_num, "number of hw queues.");
4982
4983/* QoS */
4984module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
4985MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
4986module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
4987MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4988
Linux kernel - Deliverables
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