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b481de9c ZY |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | *****************************************************************************/ | |
26 | ||
27 | #include <linux/kernel.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/version.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/pci.h> | |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/skbuff.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/wireless.h> | |
37 | #include <net/mac80211.h> | |
b481de9c | 38 | #include <linux/etherdevice.h> |
12342c47 | 39 | #include <asm/unaligned.h> |
b481de9c | 40 | |
b481de9c ZY |
41 | #include "iwl-4965.h" |
42 | #include "iwl-helpers.h" | |
43 | ||
bb8c093b | 44 | static void iwl4965_hw_card_show_info(struct iwl4965_priv *priv); |
416e1438 | 45 | |
b481de9c ZY |
46 | #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \ |
47 | [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \ | |
48 | IWL_RATE_SISO_##s##M_PLCP, \ | |
49 | IWL_RATE_MIMO_##s##M_PLCP, \ | |
50 | IWL_RATE_##r##M_IEEE, \ | |
51 | IWL_RATE_##ip##M_INDEX, \ | |
52 | IWL_RATE_##in##M_INDEX, \ | |
53 | IWL_RATE_##rp##M_INDEX, \ | |
54 | IWL_RATE_##rn##M_INDEX, \ | |
55 | IWL_RATE_##pp##M_INDEX, \ | |
56 | IWL_RATE_##np##M_INDEX } | |
57 | ||
58 | /* | |
59 | * Parameter order: | |
60 | * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate | |
61 | * | |
62 | * If there isn't a valid next or previous rate then INV is used which | |
63 | * maps to IWL_RATE_INVALID | |
64 | * | |
65 | */ | |
bb8c093b | 66 | const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = { |
b481de9c ZY |
67 | IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */ |
68 | IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */ | |
69 | IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */ | |
70 | IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */ | |
71 | IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */ | |
72 | IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */ | |
73 | IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */ | |
74 | IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */ | |
75 | IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */ | |
76 | IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */ | |
77 | IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */ | |
78 | IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */ | |
79 | IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */ | |
80 | }; | |
81 | ||
fe01b477 RR |
82 | #ifdef CONFIG_IWL4965_HT |
83 | ||
84 | static const u16 default_tid_to_tx_fifo[] = { | |
85 | IWL_TX_FIFO_AC1, | |
86 | IWL_TX_FIFO_AC0, | |
87 | IWL_TX_FIFO_AC0, | |
88 | IWL_TX_FIFO_AC1, | |
89 | IWL_TX_FIFO_AC2, | |
90 | IWL_TX_FIFO_AC2, | |
91 | IWL_TX_FIFO_AC3, | |
92 | IWL_TX_FIFO_AC3, | |
93 | IWL_TX_FIFO_NONE, | |
94 | IWL_TX_FIFO_NONE, | |
95 | IWL_TX_FIFO_NONE, | |
96 | IWL_TX_FIFO_NONE, | |
97 | IWL_TX_FIFO_NONE, | |
98 | IWL_TX_FIFO_NONE, | |
99 | IWL_TX_FIFO_NONE, | |
100 | IWL_TX_FIFO_NONE, | |
101 | IWL_TX_FIFO_AC3 | |
102 | }; | |
103 | ||
104 | #endif /*CONFIG_IWL4965_HT */ | |
105 | ||
b481de9c ZY |
106 | static int is_fat_channel(__le32 rxon_flags) |
107 | { | |
108 | return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) || | |
109 | (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK); | |
110 | } | |
111 | ||
bb8c093b | 112 | static u8 is_single_stream(struct iwl4965_priv *priv) |
b481de9c | 113 | { |
c8b0e6e1 | 114 | #ifdef CONFIG_IWL4965_HT |
fd105e79 RR |
115 | if (!priv->current_ht_config.is_ht || |
116 | (priv->current_ht_config.supp_mcs_set[1] == 0) || | |
b481de9c ZY |
117 | (priv->ps_mode == IWL_MIMO_PS_STATIC)) |
118 | return 1; | |
119 | #else | |
120 | return 1; | |
c8b0e6e1 | 121 | #endif /*CONFIG_IWL4965_HT */ |
b481de9c ZY |
122 | return 0; |
123 | } | |
124 | ||
125 | /* | |
126 | * Determine how many receiver/antenna chains to use. | |
127 | * More provides better reception via diversity. Fewer saves power. | |
128 | * MIMO (dual stream) requires at least 2, but works better with 3. | |
129 | * This does not determine *which* chains to use, just how many. | |
130 | */ | |
bb8c093b | 131 | static int iwl4965_get_rx_chain_counter(struct iwl4965_priv *priv, |
b481de9c ZY |
132 | u8 *idle_state, u8 *rx_state) |
133 | { | |
134 | u8 is_single = is_single_stream(priv); | |
135 | u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1; | |
136 | ||
137 | /* # of Rx chains to use when expecting MIMO. */ | |
138 | if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC))) | |
139 | *rx_state = 2; | |
140 | else | |
141 | *rx_state = 3; | |
142 | ||
143 | /* # Rx chains when idling and maybe trying to save power */ | |
144 | switch (priv->ps_mode) { | |
145 | case IWL_MIMO_PS_STATIC: | |
146 | case IWL_MIMO_PS_DYNAMIC: | |
147 | *idle_state = (is_cam) ? 2 : 1; | |
148 | break; | |
149 | case IWL_MIMO_PS_NONE: | |
150 | *idle_state = (is_cam) ? *rx_state : 1; | |
151 | break; | |
152 | default: | |
153 | *idle_state = 1; | |
154 | break; | |
155 | } | |
156 | ||
157 | return 0; | |
158 | } | |
159 | ||
bb8c093b | 160 | int iwl4965_hw_rxq_stop(struct iwl4965_priv *priv) |
b481de9c ZY |
161 | { |
162 | int rc; | |
163 | unsigned long flags; | |
164 | ||
165 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 166 | rc = iwl4965_grab_nic_access(priv); |
b481de9c ZY |
167 | if (rc) { |
168 | spin_unlock_irqrestore(&priv->lock, flags); | |
169 | return rc; | |
170 | } | |
171 | ||
8b6eaea8 | 172 | /* stop Rx DMA */ |
bb8c093b CH |
173 | iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
174 | rc = iwl4965_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG, | |
b481de9c ZY |
175 | (1 << 24), 1000); |
176 | if (rc < 0) | |
177 | IWL_ERROR("Can't stop Rx DMA.\n"); | |
178 | ||
bb8c093b | 179 | iwl4965_release_nic_access(priv); |
b481de9c ZY |
180 | spin_unlock_irqrestore(&priv->lock, flags); |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
bb8c093b | 185 | u8 iwl4965_hw_find_station(struct iwl4965_priv *priv, const u8 *addr) |
b481de9c ZY |
186 | { |
187 | int i; | |
188 | int start = 0; | |
189 | int ret = IWL_INVALID_STATION; | |
190 | unsigned long flags; | |
0795af57 | 191 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
192 | |
193 | if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) || | |
194 | (priv->iw_mode == IEEE80211_IF_TYPE_AP)) | |
195 | start = IWL_STA_ID; | |
196 | ||
197 | if (is_broadcast_ether_addr(addr)) | |
198 | return IWL4965_BROADCAST_ID; | |
199 | ||
200 | spin_lock_irqsave(&priv->sta_lock, flags); | |
201 | for (i = start; i < priv->hw_setting.max_stations; i++) | |
202 | if ((priv->stations[i].used) && | |
203 | (!compare_ether_addr | |
204 | (priv->stations[i].sta.sta.addr, addr))) { | |
205 | ret = i; | |
206 | goto out; | |
207 | } | |
208 | ||
a50e2e3f | 209 | IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n", |
0795af57 | 210 | print_mac(mac, addr), priv->num_stations); |
b481de9c ZY |
211 | |
212 | out: | |
213 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
214 | return ret; | |
215 | } | |
216 | ||
bb8c093b | 217 | static int iwl4965_nic_set_pwr_src(struct iwl4965_priv *priv, int pwr_max) |
b481de9c | 218 | { |
d8609652 | 219 | int ret; |
b481de9c ZY |
220 | unsigned long flags; |
221 | ||
222 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 223 | ret = iwl4965_grab_nic_access(priv); |
d8609652 | 224 | if (ret) { |
b481de9c | 225 | spin_unlock_irqrestore(&priv->lock, flags); |
d8609652 | 226 | return ret; |
b481de9c ZY |
227 | } |
228 | ||
229 | if (!pwr_max) { | |
230 | u32 val; | |
231 | ||
d8609652 | 232 | ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE, |
b481de9c ZY |
233 | &val); |
234 | ||
235 | if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) | |
bb8c093b | 236 | iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
b481de9c ZY |
237 | APMG_PS_CTRL_VAL_PWR_SRC_VAUX, |
238 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
239 | } else | |
bb8c093b | 240 | iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
b481de9c ZY |
241 | APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, |
242 | ~APMG_PS_CTRL_MSK_PWR_SRC); | |
243 | ||
bb8c093b | 244 | iwl4965_release_nic_access(priv); |
b481de9c ZY |
245 | spin_unlock_irqrestore(&priv->lock, flags); |
246 | ||
d8609652 | 247 | return ret; |
b481de9c ZY |
248 | } |
249 | ||
bb8c093b | 250 | static int iwl4965_rx_init(struct iwl4965_priv *priv, struct iwl4965_rx_queue *rxq) |
b481de9c ZY |
251 | { |
252 | int rc; | |
253 | unsigned long flags; | |
9ee1ba47 | 254 | unsigned int rb_size; |
b481de9c ZY |
255 | |
256 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 257 | rc = iwl4965_grab_nic_access(priv); |
b481de9c ZY |
258 | if (rc) { |
259 | spin_unlock_irqrestore(&priv->lock, flags); | |
260 | return rc; | |
261 | } | |
262 | ||
9ee1ba47 RR |
263 | if (iwl4965_param_amsdu_size_8K) |
264 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; | |
265 | else | |
266 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; | |
267 | ||
8b6eaea8 | 268 | /* Stop Rx DMA */ |
bb8c093b | 269 | iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
b481de9c | 270 | |
8b6eaea8 | 271 | /* Reset driver's Rx queue write index */ |
bb8c093b | 272 | iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); |
8b6eaea8 CB |
273 | |
274 | /* Tell device where to find RBD circular buffer in DRAM */ | |
bb8c093b | 275 | iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG, |
b481de9c ZY |
276 | rxq->dma_addr >> 8); |
277 | ||
8b6eaea8 | 278 | /* Tell device where in DRAM to update its Rx status */ |
bb8c093b | 279 | iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG, |
b481de9c | 280 | (priv->hw_setting.shared_phys + |
bb8c093b | 281 | offsetof(struct iwl4965_shared, val0)) >> 4); |
b481de9c | 282 | |
8b6eaea8 | 283 | /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */ |
bb8c093b | 284 | iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, |
b481de9c ZY |
285 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | |
286 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | | |
9ee1ba47 | 287 | rb_size | |
b481de9c ZY |
288 | /*0x10 << 4 | */ |
289 | (RX_QUEUE_SIZE_LOG << | |
290 | FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT)); | |
291 | ||
292 | /* | |
bb8c093b | 293 | * iwl4965_write32(priv,CSR_INT_COAL_REG,0); |
b481de9c ZY |
294 | */ |
295 | ||
bb8c093b | 296 | iwl4965_release_nic_access(priv); |
b481de9c ZY |
297 | spin_unlock_irqrestore(&priv->lock, flags); |
298 | ||
299 | return 0; | |
300 | } | |
301 | ||
8b6eaea8 | 302 | /* Tell 4965 where to find the "keep warm" buffer */ |
bb8c093b | 303 | static int iwl4965_kw_init(struct iwl4965_priv *priv) |
b481de9c ZY |
304 | { |
305 | unsigned long flags; | |
306 | int rc; | |
307 | ||
308 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 309 | rc = iwl4965_grab_nic_access(priv); |
b481de9c ZY |
310 | if (rc) |
311 | goto out; | |
312 | ||
bb8c093b | 313 | iwl4965_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG, |
b481de9c | 314 | priv->kw.dma_addr >> 4); |
bb8c093b | 315 | iwl4965_release_nic_access(priv); |
b481de9c ZY |
316 | out: |
317 | spin_unlock_irqrestore(&priv->lock, flags); | |
318 | return rc; | |
319 | } | |
320 | ||
bb8c093b | 321 | static int iwl4965_kw_alloc(struct iwl4965_priv *priv) |
b481de9c ZY |
322 | { |
323 | struct pci_dev *dev = priv->pci_dev; | |
bb8c093b | 324 | struct iwl4965_kw *kw = &priv->kw; |
b481de9c ZY |
325 | |
326 | kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */ | |
327 | kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr); | |
328 | if (!kw->v_addr) | |
329 | return -ENOMEM; | |
330 | ||
331 | return 0; | |
332 | } | |
333 | ||
334 | #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \ | |
335 | ? # x " " : "") | |
336 | ||
8b6eaea8 CB |
337 | /** |
338 | * iwl4965_set_fat_chan_info - Copy fat channel info into driver's priv. | |
339 | * | |
340 | * Does not set up a command, or touch hardware. | |
341 | */ | |
8318d78a JB |
342 | int iwl4965_set_fat_chan_info(struct iwl4965_priv *priv, |
343 | enum ieee80211_band band, u16 channel, | |
bb8c093b | 344 | const struct iwl4965_eeprom_channel *eeprom_ch, |
b481de9c ZY |
345 | u8 fat_extension_channel) |
346 | { | |
bb8c093b | 347 | struct iwl4965_channel_info *ch_info; |
b481de9c | 348 | |
bb8c093b | 349 | ch_info = (struct iwl4965_channel_info *) |
8318d78a | 350 | iwl4965_get_channel_info(priv, band, channel); |
b481de9c ZY |
351 | |
352 | if (!is_channel_valid(ch_info)) | |
353 | return -1; | |
354 | ||
355 | IWL_DEBUG_INFO("FAT Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x" | |
356 | " %ddBm): Ad-Hoc %ssupported\n", | |
357 | ch_info->channel, | |
358 | is_channel_a_band(ch_info) ? | |
359 | "5.2" : "2.4", | |
360 | CHECK_AND_PRINT(IBSS), | |
361 | CHECK_AND_PRINT(ACTIVE), | |
362 | CHECK_AND_PRINT(RADAR), | |
363 | CHECK_AND_PRINT(WIDE), | |
364 | CHECK_AND_PRINT(NARROW), | |
365 | CHECK_AND_PRINT(DFS), | |
366 | eeprom_ch->flags, | |
367 | eeprom_ch->max_power_avg, | |
368 | ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) | |
369 | && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? | |
370 | "" : "not "); | |
371 | ||
372 | ch_info->fat_eeprom = *eeprom_ch; | |
373 | ch_info->fat_max_power_avg = eeprom_ch->max_power_avg; | |
374 | ch_info->fat_curr_txpow = eeprom_ch->max_power_avg; | |
375 | ch_info->fat_min_power = 0; | |
376 | ch_info->fat_scan_power = eeprom_ch->max_power_avg; | |
377 | ch_info->fat_flags = eeprom_ch->flags; | |
378 | ch_info->fat_extension_channel = fat_extension_channel; | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
8b6eaea8 CB |
383 | /** |
384 | * iwl4965_kw_free - Free the "keep warm" buffer | |
385 | */ | |
bb8c093b | 386 | static void iwl4965_kw_free(struct iwl4965_priv *priv) |
b481de9c ZY |
387 | { |
388 | struct pci_dev *dev = priv->pci_dev; | |
bb8c093b | 389 | struct iwl4965_kw *kw = &priv->kw; |
b481de9c ZY |
390 | |
391 | if (kw->v_addr) { | |
392 | pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr); | |
393 | memset(kw, 0, sizeof(*kw)); | |
394 | } | |
395 | } | |
396 | ||
397 | /** | |
398 | * iwl4965_txq_ctx_reset - Reset TX queue context | |
399 | * Destroys all DMA structures and initialise them again | |
400 | * | |
401 | * @param priv | |
402 | * @return error code | |
403 | */ | |
bb8c093b | 404 | static int iwl4965_txq_ctx_reset(struct iwl4965_priv *priv) |
b481de9c ZY |
405 | { |
406 | int rc = 0; | |
407 | int txq_id, slots_num; | |
408 | unsigned long flags; | |
409 | ||
410 | iwl4965_kw_free(priv); | |
411 | ||
8b6eaea8 | 412 | /* Free all tx/cmd queues and keep-warm buffer */ |
bb8c093b | 413 | iwl4965_hw_txq_ctx_free(priv); |
b481de9c | 414 | |
8b6eaea8 | 415 | /* Alloc keep-warm buffer */ |
b481de9c ZY |
416 | rc = iwl4965_kw_alloc(priv); |
417 | if (rc) { | |
418 | IWL_ERROR("Keep Warm allocation failed"); | |
419 | goto error_kw; | |
420 | } | |
421 | ||
422 | spin_lock_irqsave(&priv->lock, flags); | |
423 | ||
bb8c093b | 424 | rc = iwl4965_grab_nic_access(priv); |
b481de9c ZY |
425 | if (unlikely(rc)) { |
426 | IWL_ERROR("TX reset failed"); | |
427 | spin_unlock_irqrestore(&priv->lock, flags); | |
428 | goto error_reset; | |
429 | } | |
430 | ||
8b6eaea8 | 431 | /* Turn off all Tx DMA channels */ |
bb8c093b CH |
432 | iwl4965_write_prph(priv, KDR_SCD_TXFACT, 0); |
433 | iwl4965_release_nic_access(priv); | |
b481de9c ZY |
434 | spin_unlock_irqrestore(&priv->lock, flags); |
435 | ||
8b6eaea8 | 436 | /* Tell 4965 where to find the keep-warm buffer */ |
b481de9c ZY |
437 | rc = iwl4965_kw_init(priv); |
438 | if (rc) { | |
439 | IWL_ERROR("kw_init failed\n"); | |
440 | goto error_reset; | |
441 | } | |
442 | ||
8b6eaea8 CB |
443 | /* Alloc and init all (default 16) Tx queues, |
444 | * including the command queue (#4) */ | |
b481de9c ZY |
445 | for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) { |
446 | slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? | |
447 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
bb8c093b | 448 | rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num, |
b481de9c ZY |
449 | txq_id); |
450 | if (rc) { | |
451 | IWL_ERROR("Tx %d queue init failed\n", txq_id); | |
452 | goto error; | |
453 | } | |
454 | } | |
455 | ||
456 | return rc; | |
457 | ||
458 | error: | |
bb8c093b | 459 | iwl4965_hw_txq_ctx_free(priv); |
b481de9c ZY |
460 | error_reset: |
461 | iwl4965_kw_free(priv); | |
462 | error_kw: | |
463 | return rc; | |
464 | } | |
465 | ||
bb8c093b | 466 | int iwl4965_hw_nic_init(struct iwl4965_priv *priv) |
b481de9c ZY |
467 | { |
468 | int rc; | |
469 | unsigned long flags; | |
bb8c093b | 470 | struct iwl4965_rx_queue *rxq = &priv->rxq; |
b481de9c ZY |
471 | u8 rev_id; |
472 | u32 val; | |
473 | u8 val_link; | |
474 | ||
bb8c093b | 475 | iwl4965_power_init_handle(priv); |
b481de9c ZY |
476 | |
477 | /* nic_init */ | |
478 | spin_lock_irqsave(&priv->lock, flags); | |
479 | ||
bb8c093b | 480 | iwl4965_set_bit(priv, CSR_GIO_CHICKEN_BITS, |
b481de9c ZY |
481 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); |
482 | ||
bb8c093b CH |
483 | iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
484 | rc = iwl4965_poll_bit(priv, CSR_GP_CNTRL, | |
b481de9c ZY |
485 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
486 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
487 | if (rc < 0) { | |
488 | spin_unlock_irqrestore(&priv->lock, flags); | |
489 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
490 | return rc; | |
491 | } | |
492 | ||
bb8c093b | 493 | rc = iwl4965_grab_nic_access(priv); |
b481de9c ZY |
494 | if (rc) { |
495 | spin_unlock_irqrestore(&priv->lock, flags); | |
496 | return rc; | |
497 | } | |
498 | ||
bb8c093b | 499 | iwl4965_read_prph(priv, APMG_CLK_CTRL_REG); |
b481de9c | 500 | |
bb8c093b | 501 | iwl4965_write_prph(priv, APMG_CLK_CTRL_REG, |
b481de9c ZY |
502 | APMG_CLK_VAL_DMA_CLK_RQT | |
503 | APMG_CLK_VAL_BSM_CLK_RQT); | |
bb8c093b | 504 | iwl4965_read_prph(priv, APMG_CLK_CTRL_REG); |
b481de9c ZY |
505 | |
506 | udelay(20); | |
507 | ||
bb8c093b | 508 | iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG, |
b481de9c ZY |
509 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
510 | ||
bb8c093b CH |
511 | iwl4965_release_nic_access(priv); |
512 | iwl4965_write32(priv, CSR_INT_COALESCING, 512 / 32); | |
b481de9c ZY |
513 | spin_unlock_irqrestore(&priv->lock, flags); |
514 | ||
515 | /* Determine HW type */ | |
516 | rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id); | |
517 | if (rc) | |
518 | return rc; | |
519 | ||
520 | IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id); | |
521 | ||
522 | iwl4965_nic_set_pwr_src(priv, 1); | |
523 | spin_lock_irqsave(&priv->lock, flags); | |
524 | ||
525 | if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) { | |
526 | pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val); | |
527 | /* Enable No Snoop field */ | |
528 | pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8, | |
529 | val & ~(1 << 11)); | |
530 | } | |
531 | ||
532 | spin_unlock_irqrestore(&priv->lock, flags); | |
533 | ||
b481de9c ZY |
534 | if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) { |
535 | IWL_ERROR("Older EEPROM detected! Aborting.\n"); | |
536 | return -EINVAL; | |
537 | } | |
538 | ||
539 | pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link); | |
540 | ||
541 | /* disable L1 entry -- workaround for pre-B1 */ | |
542 | pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02); | |
543 | ||
544 | spin_lock_irqsave(&priv->lock, flags); | |
545 | ||
546 | /* set CSR_HW_CONFIG_REG for uCode use */ | |
547 | ||
bb8c093b | 548 | iwl4965_set_bit(priv, CSR_SW_VER, CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R | |
b481de9c ZY |
549 | CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | |
550 | CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); | |
551 | ||
bb8c093b | 552 | rc = iwl4965_grab_nic_access(priv); |
b481de9c ZY |
553 | if (rc < 0) { |
554 | spin_unlock_irqrestore(&priv->lock, flags); | |
555 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
556 | return rc; | |
557 | } | |
558 | ||
bb8c093b CH |
559 | iwl4965_read_prph(priv, APMG_PS_CTRL_REG); |
560 | iwl4965_set_bits_prph(priv, APMG_PS_CTRL_REG, | |
b481de9c ZY |
561 | APMG_PS_CTRL_VAL_RESET_REQ); |
562 | udelay(5); | |
bb8c093b | 563 | iwl4965_clear_bits_prph(priv, APMG_PS_CTRL_REG, |
b481de9c ZY |
564 | APMG_PS_CTRL_VAL_RESET_REQ); |
565 | ||
bb8c093b | 566 | iwl4965_release_nic_access(priv); |
b481de9c ZY |
567 | spin_unlock_irqrestore(&priv->lock, flags); |
568 | ||
bb8c093b | 569 | iwl4965_hw_card_show_info(priv); |
b481de9c ZY |
570 | |
571 | /* end nic_init */ | |
572 | ||
573 | /* Allocate the RX queue, or reset if it is already allocated */ | |
574 | if (!rxq->bd) { | |
bb8c093b | 575 | rc = iwl4965_rx_queue_alloc(priv); |
b481de9c ZY |
576 | if (rc) { |
577 | IWL_ERROR("Unable to initialize Rx queue\n"); | |
578 | return -ENOMEM; | |
579 | } | |
580 | } else | |
bb8c093b | 581 | iwl4965_rx_queue_reset(priv, rxq); |
b481de9c | 582 | |
bb8c093b | 583 | iwl4965_rx_replenish(priv); |
b481de9c ZY |
584 | |
585 | iwl4965_rx_init(priv, rxq); | |
586 | ||
587 | spin_lock_irqsave(&priv->lock, flags); | |
588 | ||
589 | rxq->need_update = 1; | |
bb8c093b | 590 | iwl4965_rx_queue_update_write_ptr(priv, rxq); |
b481de9c ZY |
591 | |
592 | spin_unlock_irqrestore(&priv->lock, flags); | |
8b6eaea8 CB |
593 | |
594 | /* Allocate and init all Tx and Command queues */ | |
b481de9c ZY |
595 | rc = iwl4965_txq_ctx_reset(priv); |
596 | if (rc) | |
597 | return rc; | |
598 | ||
599 | if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE) | |
600 | IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n"); | |
601 | ||
602 | if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE) | |
603 | IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n"); | |
604 | ||
605 | set_bit(STATUS_INIT, &priv->status); | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
bb8c093b | 610 | int iwl4965_hw_nic_stop_master(struct iwl4965_priv *priv) |
b481de9c ZY |
611 | { |
612 | int rc = 0; | |
613 | u32 reg_val; | |
614 | unsigned long flags; | |
615 | ||
616 | spin_lock_irqsave(&priv->lock, flags); | |
617 | ||
618 | /* set stop master bit */ | |
bb8c093b | 619 | iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); |
b481de9c | 620 | |
bb8c093b | 621 | reg_val = iwl4965_read32(priv, CSR_GP_CNTRL); |
b481de9c ZY |
622 | |
623 | if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE == | |
624 | (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE)) | |
625 | IWL_DEBUG_INFO("Card in power save, master is already " | |
626 | "stopped\n"); | |
627 | else { | |
bb8c093b | 628 | rc = iwl4965_poll_bit(priv, CSR_RESET, |
b481de9c ZY |
629 | CSR_RESET_REG_FLAG_MASTER_DISABLED, |
630 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
631 | if (rc < 0) { | |
632 | spin_unlock_irqrestore(&priv->lock, flags); | |
633 | return rc; | |
634 | } | |
635 | } | |
636 | ||
637 | spin_unlock_irqrestore(&priv->lock, flags); | |
638 | IWL_DEBUG_INFO("stop master\n"); | |
639 | ||
640 | return rc; | |
641 | } | |
642 | ||
8b6eaea8 CB |
643 | /** |
644 | * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory | |
645 | */ | |
bb8c093b | 646 | void iwl4965_hw_txq_ctx_stop(struct iwl4965_priv *priv) |
b481de9c ZY |
647 | { |
648 | ||
649 | int txq_id; | |
650 | unsigned long flags; | |
651 | ||
8b6eaea8 | 652 | /* Stop each Tx DMA channel, and wait for it to be idle */ |
b481de9c ZY |
653 | for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) { |
654 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 655 | if (iwl4965_grab_nic_access(priv)) { |
b481de9c ZY |
656 | spin_unlock_irqrestore(&priv->lock, flags); |
657 | continue; | |
658 | } | |
659 | ||
bb8c093b | 660 | iwl4965_write_direct32(priv, |
b481de9c ZY |
661 | IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), |
662 | 0x0); | |
bb8c093b | 663 | iwl4965_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG, |
b481de9c ZY |
664 | IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE |
665 | (txq_id), 200); | |
bb8c093b | 666 | iwl4965_release_nic_access(priv); |
b481de9c ZY |
667 | spin_unlock_irqrestore(&priv->lock, flags); |
668 | } | |
669 | ||
8b6eaea8 | 670 | /* Deallocate memory for all Tx queues */ |
bb8c093b | 671 | iwl4965_hw_txq_ctx_free(priv); |
b481de9c ZY |
672 | } |
673 | ||
bb8c093b | 674 | int iwl4965_hw_nic_reset(struct iwl4965_priv *priv) |
b481de9c ZY |
675 | { |
676 | int rc = 0; | |
677 | unsigned long flags; | |
678 | ||
bb8c093b | 679 | iwl4965_hw_nic_stop_master(priv); |
b481de9c ZY |
680 | |
681 | spin_lock_irqsave(&priv->lock, flags); | |
682 | ||
bb8c093b | 683 | iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); |
b481de9c ZY |
684 | |
685 | udelay(10); | |
686 | ||
bb8c093b CH |
687 | iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); |
688 | rc = iwl4965_poll_bit(priv, CSR_RESET, | |
b481de9c ZY |
689 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, |
690 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25); | |
691 | ||
692 | udelay(10); | |
693 | ||
bb8c093b | 694 | rc = iwl4965_grab_nic_access(priv); |
b481de9c | 695 | if (!rc) { |
bb8c093b | 696 | iwl4965_write_prph(priv, APMG_CLK_EN_REG, |
b481de9c ZY |
697 | APMG_CLK_VAL_DMA_CLK_RQT | |
698 | APMG_CLK_VAL_BSM_CLK_RQT); | |
699 | ||
700 | udelay(10); | |
701 | ||
bb8c093b | 702 | iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG, |
b481de9c ZY |
703 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
704 | ||
bb8c093b | 705 | iwl4965_release_nic_access(priv); |
b481de9c ZY |
706 | } |
707 | ||
708 | clear_bit(STATUS_HCMD_ACTIVE, &priv->status); | |
709 | wake_up_interruptible(&priv->wait_command_queue); | |
710 | ||
711 | spin_unlock_irqrestore(&priv->lock, flags); | |
712 | ||
713 | return rc; | |
714 | ||
715 | } | |
716 | ||
717 | #define REG_RECALIB_PERIOD (60) | |
718 | ||
719 | /** | |
720 | * iwl4965_bg_statistics_periodic - Timer callback to queue statistics | |
721 | * | |
722 | * This callback is provided in order to queue the statistics_work | |
723 | * in work_queue context (v. softirq) | |
724 | * | |
725 | * This timer function is continually reset to execute within | |
726 | * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION | |
727 | * was received. We need to ensure we receive the statistics in order | |
728 | * to update the temperature used for calibrating the TXPOWER. However, | |
729 | * we can't send the statistics command from softirq context (which | |
730 | * is the context which timers run at) so we have to queue off the | |
731 | * statistics_work to actually send the command to the hardware. | |
732 | */ | |
733 | static void iwl4965_bg_statistics_periodic(unsigned long data) | |
734 | { | |
bb8c093b | 735 | struct iwl4965_priv *priv = (struct iwl4965_priv *)data; |
b481de9c ZY |
736 | |
737 | queue_work(priv->workqueue, &priv->statistics_work); | |
738 | } | |
739 | ||
740 | /** | |
741 | * iwl4965_bg_statistics_work - Send the statistics request to the hardware. | |
742 | * | |
bb8c093b | 743 | * This is queued by iwl4965_bg_statistics_periodic. |
b481de9c ZY |
744 | */ |
745 | static void iwl4965_bg_statistics_work(struct work_struct *work) | |
746 | { | |
bb8c093b | 747 | struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv, |
b481de9c ZY |
748 | statistics_work); |
749 | ||
750 | if (test_bit(STATUS_EXIT_PENDING, &priv->status)) | |
751 | return; | |
752 | ||
753 | mutex_lock(&priv->mutex); | |
bb8c093b | 754 | iwl4965_send_statistics_request(priv); |
b481de9c ZY |
755 | mutex_unlock(&priv->mutex); |
756 | } | |
757 | ||
758 | #define CT_LIMIT_CONST 259 | |
759 | #define TM_CT_KILL_THRESHOLD 110 | |
760 | ||
bb8c093b | 761 | void iwl4965_rf_kill_ct_config(struct iwl4965_priv *priv) |
b481de9c | 762 | { |
bb8c093b | 763 | struct iwl4965_ct_kill_config cmd; |
b481de9c ZY |
764 | u32 R1, R2, R3; |
765 | u32 temp_th; | |
766 | u32 crit_temperature; | |
767 | unsigned long flags; | |
768 | int rc = 0; | |
769 | ||
770 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 771 | iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR, |
b481de9c ZY |
772 | CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); |
773 | spin_unlock_irqrestore(&priv->lock, flags); | |
774 | ||
775 | if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) { | |
776 | R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]); | |
777 | R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]); | |
778 | R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]); | |
779 | } else { | |
780 | R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]); | |
781 | R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]); | |
782 | R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]); | |
783 | } | |
784 | ||
785 | temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD); | |
786 | ||
787 | crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2; | |
788 | cmd.critical_temperature_R = cpu_to_le32(crit_temperature); | |
bb8c093b | 789 | rc = iwl4965_send_cmd_pdu(priv, |
b481de9c ZY |
790 | REPLY_CT_KILL_CONFIG_CMD, sizeof(cmd), &cmd); |
791 | if (rc) | |
792 | IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n"); | |
793 | else | |
794 | IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n"); | |
795 | } | |
796 | ||
c8b0e6e1 | 797 | #ifdef CONFIG_IWL4965_SENSITIVITY |
b481de9c ZY |
798 | |
799 | /* "false alarms" are signals that our DSP tries to lock onto, | |
800 | * but then determines that they are either noise, or transmissions | |
801 | * from a distant wireless network (also "noise", really) that get | |
802 | * "stepped on" by stronger transmissions within our own network. | |
803 | * This algorithm attempts to set a sensitivity level that is high | |
804 | * enough to receive all of our own network traffic, but not so | |
805 | * high that our DSP gets too busy trying to lock onto non-network | |
806 | * activity/noise. */ | |
bb8c093b | 807 | static int iwl4965_sens_energy_cck(struct iwl4965_priv *priv, |
b481de9c ZY |
808 | u32 norm_fa, |
809 | u32 rx_enable_time, | |
810 | struct statistics_general_data *rx_info) | |
811 | { | |
812 | u32 max_nrg_cck = 0; | |
813 | int i = 0; | |
814 | u8 max_silence_rssi = 0; | |
815 | u32 silence_ref = 0; | |
816 | u8 silence_rssi_a = 0; | |
817 | u8 silence_rssi_b = 0; | |
818 | u8 silence_rssi_c = 0; | |
819 | u32 val; | |
820 | ||
821 | /* "false_alarms" values below are cross-multiplications to assess the | |
822 | * numbers of false alarms within the measured period of actual Rx | |
823 | * (Rx is off when we're txing), vs the min/max expected false alarms | |
824 | * (some should be expected if rx is sensitive enough) in a | |
825 | * hypothetical listening period of 200 time units (TU), 204.8 msec: | |
826 | * | |
827 | * MIN_FA/fixed-time < false_alarms/actual-rx-time < MAX_FA/beacon-time | |
828 | * | |
829 | * */ | |
830 | u32 false_alarms = norm_fa * 200 * 1024; | |
831 | u32 max_false_alarms = MAX_FA_CCK * rx_enable_time; | |
832 | u32 min_false_alarms = MIN_FA_CCK * rx_enable_time; | |
bb8c093b | 833 | struct iwl4965_sensitivity_data *data = NULL; |
b481de9c ZY |
834 | |
835 | data = &(priv->sensitivity_data); | |
836 | ||
837 | data->nrg_auto_corr_silence_diff = 0; | |
838 | ||
839 | /* Find max silence rssi among all 3 receivers. | |
840 | * This is background noise, which may include transmissions from other | |
841 | * networks, measured during silence before our network's beacon */ | |
842 | silence_rssi_a = (u8)((rx_info->beacon_silence_rssi_a & | |
8a1b0245 | 843 | ALL_BAND_FILTER) >> 8); |
b481de9c | 844 | silence_rssi_b = (u8)((rx_info->beacon_silence_rssi_b & |
8a1b0245 | 845 | ALL_BAND_FILTER) >> 8); |
b481de9c | 846 | silence_rssi_c = (u8)((rx_info->beacon_silence_rssi_c & |
8a1b0245 | 847 | ALL_BAND_FILTER) >> 8); |
b481de9c ZY |
848 | |
849 | val = max(silence_rssi_b, silence_rssi_c); | |
850 | max_silence_rssi = max(silence_rssi_a, (u8) val); | |
851 | ||
852 | /* Store silence rssi in 20-beacon history table */ | |
853 | data->nrg_silence_rssi[data->nrg_silence_idx] = max_silence_rssi; | |
854 | data->nrg_silence_idx++; | |
855 | if (data->nrg_silence_idx >= NRG_NUM_PREV_STAT_L) | |
856 | data->nrg_silence_idx = 0; | |
857 | ||
858 | /* Find max silence rssi across 20 beacon history */ | |
859 | for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) { | |
860 | val = data->nrg_silence_rssi[i]; | |
861 | silence_ref = max(silence_ref, val); | |
862 | } | |
863 | IWL_DEBUG_CALIB("silence a %u, b %u, c %u, 20-bcn max %u\n", | |
864 | silence_rssi_a, silence_rssi_b, silence_rssi_c, | |
865 | silence_ref); | |
866 | ||
867 | /* Find max rx energy (min value!) among all 3 receivers, | |
868 | * measured during beacon frame. | |
869 | * Save it in 10-beacon history table. */ | |
870 | i = data->nrg_energy_idx; | |
871 | val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c); | |
872 | data->nrg_value[i] = min(rx_info->beacon_energy_a, val); | |
873 | ||
874 | data->nrg_energy_idx++; | |
875 | if (data->nrg_energy_idx >= 10) | |
876 | data->nrg_energy_idx = 0; | |
877 | ||
878 | /* Find min rx energy (max value) across 10 beacon history. | |
879 | * This is the minimum signal level that we want to receive well. | |
880 | * Add backoff (margin so we don't miss slightly lower energy frames). | |
881 | * This establishes an upper bound (min value) for energy threshold. */ | |
882 | max_nrg_cck = data->nrg_value[0]; | |
883 | for (i = 1; i < 10; i++) | |
884 | max_nrg_cck = (u32) max(max_nrg_cck, (data->nrg_value[i])); | |
885 | max_nrg_cck += 6; | |
886 | ||
887 | IWL_DEBUG_CALIB("rx energy a %u, b %u, c %u, 10-bcn max/min %u\n", | |
888 | rx_info->beacon_energy_a, rx_info->beacon_energy_b, | |
889 | rx_info->beacon_energy_c, max_nrg_cck - 6); | |
890 | ||
891 | /* Count number of consecutive beacons with fewer-than-desired | |
892 | * false alarms. */ | |
893 | if (false_alarms < min_false_alarms) | |
894 | data->num_in_cck_no_fa++; | |
895 | else | |
896 | data->num_in_cck_no_fa = 0; | |
897 | IWL_DEBUG_CALIB("consecutive bcns with few false alarms = %u\n", | |
898 | data->num_in_cck_no_fa); | |
899 | ||
900 | /* If we got too many false alarms this time, reduce sensitivity */ | |
901 | if (false_alarms > max_false_alarms) { | |
902 | IWL_DEBUG_CALIB("norm FA %u > max FA %u\n", | |
903 | false_alarms, max_false_alarms); | |
904 | IWL_DEBUG_CALIB("... reducing sensitivity\n"); | |
905 | data->nrg_curr_state = IWL_FA_TOO_MANY; | |
906 | ||
907 | if (data->auto_corr_cck > AUTO_CORR_MAX_TH_CCK) { | |
908 | /* Store for "fewer than desired" on later beacon */ | |
909 | data->nrg_silence_ref = silence_ref; | |
910 | ||
911 | /* increase energy threshold (reduce nrg value) | |
912 | * to decrease sensitivity */ | |
913 | if (data->nrg_th_cck > (NRG_MAX_CCK + NRG_STEP_CCK)) | |
914 | data->nrg_th_cck = data->nrg_th_cck | |
915 | - NRG_STEP_CCK; | |
916 | } | |
917 | ||
918 | /* increase auto_corr values to decrease sensitivity */ | |
919 | if (data->auto_corr_cck < AUTO_CORR_MAX_TH_CCK) | |
920 | data->auto_corr_cck = AUTO_CORR_MAX_TH_CCK + 1; | |
921 | else { | |
922 | val = data->auto_corr_cck + AUTO_CORR_STEP_CCK; | |
923 | data->auto_corr_cck = min((u32)AUTO_CORR_MAX_CCK, val); | |
924 | } | |
925 | val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK; | |
926 | data->auto_corr_cck_mrc = min((u32)AUTO_CORR_MAX_CCK_MRC, val); | |
927 | ||
928 | /* Else if we got fewer than desired, increase sensitivity */ | |
929 | } else if (false_alarms < min_false_alarms) { | |
930 | data->nrg_curr_state = IWL_FA_TOO_FEW; | |
931 | ||
932 | /* Compare silence level with silence level for most recent | |
933 | * healthy number or too many false alarms */ | |
934 | data->nrg_auto_corr_silence_diff = (s32)data->nrg_silence_ref - | |
935 | (s32)silence_ref; | |
936 | ||
937 | IWL_DEBUG_CALIB("norm FA %u < min FA %u, silence diff %d\n", | |
938 | false_alarms, min_false_alarms, | |
939 | data->nrg_auto_corr_silence_diff); | |
940 | ||
941 | /* Increase value to increase sensitivity, but only if: | |
942 | * 1a) previous beacon did *not* have *too many* false alarms | |
943 | * 1b) AND there's a significant difference in Rx levels | |
944 | * from a previous beacon with too many, or healthy # FAs | |
945 | * OR 2) We've seen a lot of beacons (100) with too few | |
946 | * false alarms */ | |
947 | if ((data->nrg_prev_state != IWL_FA_TOO_MANY) && | |
948 | ((data->nrg_auto_corr_silence_diff > NRG_DIFF) || | |
949 | (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) { | |
950 | ||
951 | IWL_DEBUG_CALIB("... increasing sensitivity\n"); | |
952 | /* Increase nrg value to increase sensitivity */ | |
953 | val = data->nrg_th_cck + NRG_STEP_CCK; | |
954 | data->nrg_th_cck = min((u32)NRG_MIN_CCK, val); | |
955 | ||
956 | /* Decrease auto_corr values to increase sensitivity */ | |
957 | val = data->auto_corr_cck - AUTO_CORR_STEP_CCK; | |
958 | data->auto_corr_cck = max((u32)AUTO_CORR_MIN_CCK, val); | |
959 | ||
960 | val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK; | |
961 | data->auto_corr_cck_mrc = | |
962 | max((u32)AUTO_CORR_MIN_CCK_MRC, val); | |
963 | ||
964 | } else | |
965 | IWL_DEBUG_CALIB("... but not changing sensitivity\n"); | |
966 | ||
967 | /* Else we got a healthy number of false alarms, keep status quo */ | |
968 | } else { | |
969 | IWL_DEBUG_CALIB(" FA in safe zone\n"); | |
970 | data->nrg_curr_state = IWL_FA_GOOD_RANGE; | |
971 | ||
972 | /* Store for use in "fewer than desired" with later beacon */ | |
973 | data->nrg_silence_ref = silence_ref; | |
974 | ||
975 | /* If previous beacon had too many false alarms, | |
976 | * give it some extra margin by reducing sensitivity again | |
977 | * (but don't go below measured energy of desired Rx) */ | |
978 | if (IWL_FA_TOO_MANY == data->nrg_prev_state) { | |
979 | IWL_DEBUG_CALIB("... increasing margin\n"); | |
980 | data->nrg_th_cck -= NRG_MARGIN; | |
981 | } | |
982 | } | |
983 | ||
984 | /* Make sure the energy threshold does not go above the measured | |
985 | * energy of the desired Rx signals (reduced by backoff margin), | |
986 | * or else we might start missing Rx frames. | |
987 | * Lower value is higher energy, so we use max()! | |
988 | */ | |
989 | data->nrg_th_cck = max(max_nrg_cck, data->nrg_th_cck); | |
990 | IWL_DEBUG_CALIB("new nrg_th_cck %u\n", data->nrg_th_cck); | |
991 | ||
992 | data->nrg_prev_state = data->nrg_curr_state; | |
993 | ||
994 | return 0; | |
995 | } | |
996 | ||
997 | ||
bb8c093b | 998 | static int iwl4965_sens_auto_corr_ofdm(struct iwl4965_priv *priv, |
b481de9c ZY |
999 | u32 norm_fa, |
1000 | u32 rx_enable_time) | |
1001 | { | |
1002 | u32 val; | |
1003 | u32 false_alarms = norm_fa * 200 * 1024; | |
1004 | u32 max_false_alarms = MAX_FA_OFDM * rx_enable_time; | |
1005 | u32 min_false_alarms = MIN_FA_OFDM * rx_enable_time; | |
bb8c093b | 1006 | struct iwl4965_sensitivity_data *data = NULL; |
b481de9c ZY |
1007 | |
1008 | data = &(priv->sensitivity_data); | |
1009 | ||
1010 | /* If we got too many false alarms this time, reduce sensitivity */ | |
1011 | if (false_alarms > max_false_alarms) { | |
1012 | ||
1013 | IWL_DEBUG_CALIB("norm FA %u > max FA %u)\n", | |
1014 | false_alarms, max_false_alarms); | |
1015 | ||
1016 | val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM; | |
1017 | data->auto_corr_ofdm = | |
1018 | min((u32)AUTO_CORR_MAX_OFDM, val); | |
1019 | ||
1020 | val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM; | |
1021 | data->auto_corr_ofdm_mrc = | |
1022 | min((u32)AUTO_CORR_MAX_OFDM_MRC, val); | |
1023 | ||
1024 | val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM; | |
1025 | data->auto_corr_ofdm_x1 = | |
1026 | min((u32)AUTO_CORR_MAX_OFDM_X1, val); | |
1027 | ||
1028 | val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM; | |
1029 | data->auto_corr_ofdm_mrc_x1 = | |
1030 | min((u32)AUTO_CORR_MAX_OFDM_MRC_X1, val); | |
1031 | } | |
1032 | ||
1033 | /* Else if we got fewer than desired, increase sensitivity */ | |
1034 | else if (false_alarms < min_false_alarms) { | |
1035 | ||
1036 | IWL_DEBUG_CALIB("norm FA %u < min FA %u\n", | |
1037 | false_alarms, min_false_alarms); | |
1038 | ||
1039 | val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM; | |
1040 | data->auto_corr_ofdm = | |
1041 | max((u32)AUTO_CORR_MIN_OFDM, val); | |
1042 | ||
1043 | val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM; | |
1044 | data->auto_corr_ofdm_mrc = | |
1045 | max((u32)AUTO_CORR_MIN_OFDM_MRC, val); | |
1046 | ||
1047 | val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM; | |
1048 | data->auto_corr_ofdm_x1 = | |
1049 | max((u32)AUTO_CORR_MIN_OFDM_X1, val); | |
1050 | ||
1051 | val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM; | |
1052 | data->auto_corr_ofdm_mrc_x1 = | |
1053 | max((u32)AUTO_CORR_MIN_OFDM_MRC_X1, val); | |
1054 | } | |
1055 | ||
1056 | else | |
1057 | IWL_DEBUG_CALIB("min FA %u < norm FA %u < max FA %u OK\n", | |
1058 | min_false_alarms, false_alarms, max_false_alarms); | |
1059 | ||
1060 | return 0; | |
1061 | } | |
1062 | ||
bb8c093b CH |
1063 | static int iwl4965_sensitivity_callback(struct iwl4965_priv *priv, |
1064 | struct iwl4965_cmd *cmd, struct sk_buff *skb) | |
b481de9c ZY |
1065 | { |
1066 | /* We didn't cache the SKB; let the caller free it */ | |
1067 | return 1; | |
1068 | } | |
1069 | ||
1070 | /* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */ | |
bb8c093b | 1071 | static int iwl4965_sensitivity_write(struct iwl4965_priv *priv, u8 flags) |
b481de9c ZY |
1072 | { |
1073 | int rc = 0; | |
bb8c093b CH |
1074 | struct iwl4965_sensitivity_cmd cmd ; |
1075 | struct iwl4965_sensitivity_data *data = NULL; | |
1076 | struct iwl4965_host_cmd cmd_out = { | |
b481de9c | 1077 | .id = SENSITIVITY_CMD, |
bb8c093b | 1078 | .len = sizeof(struct iwl4965_sensitivity_cmd), |
b481de9c ZY |
1079 | .meta.flags = flags, |
1080 | .data = &cmd, | |
1081 | }; | |
1082 | ||
1083 | data = &(priv->sensitivity_data); | |
1084 | ||
1085 | memset(&cmd, 0, sizeof(cmd)); | |
1086 | ||
1087 | cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX] = | |
1088 | cpu_to_le16((u16)data->auto_corr_ofdm); | |
1089 | cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX] = | |
1090 | cpu_to_le16((u16)data->auto_corr_ofdm_mrc); | |
1091 | cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX] = | |
1092 | cpu_to_le16((u16)data->auto_corr_ofdm_x1); | |
1093 | cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX] = | |
1094 | cpu_to_le16((u16)data->auto_corr_ofdm_mrc_x1); | |
1095 | ||
1096 | cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX] = | |
1097 | cpu_to_le16((u16)data->auto_corr_cck); | |
1098 | cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX] = | |
1099 | cpu_to_le16((u16)data->auto_corr_cck_mrc); | |
1100 | ||
1101 | cmd.table[HD_MIN_ENERGY_CCK_DET_INDEX] = | |
1102 | cpu_to_le16((u16)data->nrg_th_cck); | |
1103 | cmd.table[HD_MIN_ENERGY_OFDM_DET_INDEX] = | |
1104 | cpu_to_le16((u16)data->nrg_th_ofdm); | |
1105 | ||
1106 | cmd.table[HD_BARKER_CORR_TH_ADD_MIN_INDEX] = | |
1107 | __constant_cpu_to_le16(190); | |
1108 | cmd.table[HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX] = | |
1109 | __constant_cpu_to_le16(390); | |
1110 | cmd.table[HD_OFDM_ENERGY_TH_IN_INDEX] = | |
1111 | __constant_cpu_to_le16(62); | |
1112 | ||
1113 | IWL_DEBUG_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n", | |
1114 | data->auto_corr_ofdm, data->auto_corr_ofdm_mrc, | |
1115 | data->auto_corr_ofdm_x1, data->auto_corr_ofdm_mrc_x1, | |
1116 | data->nrg_th_ofdm); | |
1117 | ||
1118 | IWL_DEBUG_CALIB("cck: ac %u mrc %u thresh %u\n", | |
1119 | data->auto_corr_cck, data->auto_corr_cck_mrc, | |
1120 | data->nrg_th_cck); | |
1121 | ||
f7d09d7c | 1122 | /* Update uCode's "work" table, and copy it to DSP */ |
b481de9c ZY |
1123 | cmd.control = SENSITIVITY_CMD_CONTROL_WORK_TABLE; |
1124 | ||
1125 | if (flags & CMD_ASYNC) | |
bb8c093b | 1126 | cmd_out.meta.u.callback = iwl4965_sensitivity_callback; |
b481de9c ZY |
1127 | |
1128 | /* Don't send command to uCode if nothing has changed */ | |
1129 | if (!memcmp(&cmd.table[0], &(priv->sensitivity_tbl[0]), | |
1130 | sizeof(u16)*HD_TABLE_SIZE)) { | |
1131 | IWL_DEBUG_CALIB("No change in SENSITIVITY_CMD\n"); | |
1132 | return 0; | |
1133 | } | |
1134 | ||
1135 | /* Copy table for comparison next time */ | |
1136 | memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]), | |
1137 | sizeof(u16)*HD_TABLE_SIZE); | |
1138 | ||
bb8c093b | 1139 | rc = iwl4965_send_cmd(priv, &cmd_out); |
b481de9c ZY |
1140 | if (!rc) { |
1141 | IWL_DEBUG_CALIB("SENSITIVITY_CMD succeeded\n"); | |
1142 | return rc; | |
1143 | } | |
1144 | ||
1145 | return 0; | |
1146 | } | |
1147 | ||
bb8c093b | 1148 | void iwl4965_init_sensitivity(struct iwl4965_priv *priv, u8 flags, u8 force) |
b481de9c ZY |
1149 | { |
1150 | int rc = 0; | |
1151 | int i; | |
bb8c093b | 1152 | struct iwl4965_sensitivity_data *data = NULL; |
b481de9c ZY |
1153 | |
1154 | IWL_DEBUG_CALIB("Start iwl4965_init_sensitivity\n"); | |
1155 | ||
1156 | if (force) | |
1157 | memset(&(priv->sensitivity_tbl[0]), 0, | |
1158 | sizeof(u16)*HD_TABLE_SIZE); | |
1159 | ||
1160 | /* Clear driver's sensitivity algo data */ | |
1161 | data = &(priv->sensitivity_data); | |
bb8c093b | 1162 | memset(data, 0, sizeof(struct iwl4965_sensitivity_data)); |
b481de9c ZY |
1163 | |
1164 | data->num_in_cck_no_fa = 0; | |
1165 | data->nrg_curr_state = IWL_FA_TOO_MANY; | |
1166 | data->nrg_prev_state = IWL_FA_TOO_MANY; | |
1167 | data->nrg_silence_ref = 0; | |
1168 | data->nrg_silence_idx = 0; | |
1169 | data->nrg_energy_idx = 0; | |
1170 | ||
1171 | for (i = 0; i < 10; i++) | |
1172 | data->nrg_value[i] = 0; | |
1173 | ||
1174 | for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) | |
1175 | data->nrg_silence_rssi[i] = 0; | |
1176 | ||
1177 | data->auto_corr_ofdm = 90; | |
1178 | data->auto_corr_ofdm_mrc = 170; | |
1179 | data->auto_corr_ofdm_x1 = 105; | |
1180 | data->auto_corr_ofdm_mrc_x1 = 220; | |
1181 | data->auto_corr_cck = AUTO_CORR_CCK_MIN_VAL_DEF; | |
1182 | data->auto_corr_cck_mrc = 200; | |
1183 | data->nrg_th_cck = 100; | |
1184 | data->nrg_th_ofdm = 100; | |
1185 | ||
1186 | data->last_bad_plcp_cnt_ofdm = 0; | |
1187 | data->last_fa_cnt_ofdm = 0; | |
1188 | data->last_bad_plcp_cnt_cck = 0; | |
1189 | data->last_fa_cnt_cck = 0; | |
1190 | ||
1191 | /* Clear prior Sensitivity command data to force send to uCode */ | |
1192 | if (force) | |
1193 | memset(&(priv->sensitivity_tbl[0]), 0, | |
1194 | sizeof(u16)*HD_TABLE_SIZE); | |
1195 | ||
1196 | rc |= iwl4965_sensitivity_write(priv, flags); | |
1197 | IWL_DEBUG_CALIB("<<return 0x%X\n", rc); | |
1198 | ||
1199 | return; | |
1200 | } | |
1201 | ||
1202 | ||
1203 | /* Reset differential Rx gains in NIC to prepare for chain noise calibration. | |
1204 | * Called after every association, but this runs only once! | |
1205 | * ... once chain noise is calibrated the first time, it's good forever. */ | |
bb8c093b | 1206 | void iwl4965_chain_noise_reset(struct iwl4965_priv *priv) |
b481de9c | 1207 | { |
bb8c093b | 1208 | struct iwl4965_chain_noise_data *data = NULL; |
b481de9c ZY |
1209 | int rc = 0; |
1210 | ||
1211 | data = &(priv->chain_noise_data); | |
bb8c093b CH |
1212 | if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl4965_is_associated(priv)) { |
1213 | struct iwl4965_calibration_cmd cmd; | |
b481de9c ZY |
1214 | |
1215 | memset(&cmd, 0, sizeof(cmd)); | |
1216 | cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD; | |
1217 | cmd.diff_gain_a = 0; | |
1218 | cmd.diff_gain_b = 0; | |
1219 | cmd.diff_gain_c = 0; | |
bb8c093b | 1220 | rc = iwl4965_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, |
b481de9c ZY |
1221 | sizeof(cmd), &cmd); |
1222 | msleep(4); | |
1223 | data->state = IWL_CHAIN_NOISE_ACCUMULATE; | |
1224 | IWL_DEBUG_CALIB("Run chain_noise_calibrate\n"); | |
1225 | } | |
1226 | return; | |
1227 | } | |
1228 | ||
1229 | /* | |
1230 | * Accumulate 20 beacons of signal and noise statistics for each of | |
1231 | * 3 receivers/antennas/rx-chains, then figure out: | |
1232 | * 1) Which antennas are connected. | |
1233 | * 2) Differential rx gain settings to balance the 3 receivers. | |
1234 | */ | |
bb8c093b CH |
1235 | static void iwl4965_noise_calibration(struct iwl4965_priv *priv, |
1236 | struct iwl4965_notif_statistics *stat_resp) | |
b481de9c | 1237 | { |
bb8c093b | 1238 | struct iwl4965_chain_noise_data *data = NULL; |
b481de9c ZY |
1239 | int rc = 0; |
1240 | ||
1241 | u32 chain_noise_a; | |
1242 | u32 chain_noise_b; | |
1243 | u32 chain_noise_c; | |
1244 | u32 chain_sig_a; | |
1245 | u32 chain_sig_b; | |
1246 | u32 chain_sig_c; | |
1247 | u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE}; | |
1248 | u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE}; | |
1249 | u32 max_average_sig; | |
1250 | u16 max_average_sig_antenna_i; | |
1251 | u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE; | |
1252 | u16 min_average_noise_antenna_i = INITIALIZATION_VALUE; | |
1253 | u16 i = 0; | |
1254 | u16 chan_num = INITIALIZATION_VALUE; | |
1255 | u32 band = INITIALIZATION_VALUE; | |
1256 | u32 active_chains = 0; | |
1257 | unsigned long flags; | |
1258 | struct statistics_rx_non_phy *rx_info = &(stat_resp->rx.general); | |
1259 | ||
1260 | data = &(priv->chain_noise_data); | |
1261 | ||
1262 | /* Accumulate just the first 20 beacons after the first association, | |
1263 | * then we're done forever. */ | |
1264 | if (data->state != IWL_CHAIN_NOISE_ACCUMULATE) { | |
1265 | if (data->state == IWL_CHAIN_NOISE_ALIVE) | |
1266 | IWL_DEBUG_CALIB("Wait for noise calib reset\n"); | |
1267 | return; | |
1268 | } | |
1269 | ||
1270 | spin_lock_irqsave(&priv->lock, flags); | |
1271 | if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) { | |
1272 | IWL_DEBUG_CALIB(" << Interference data unavailable\n"); | |
1273 | spin_unlock_irqrestore(&priv->lock, flags); | |
1274 | return; | |
1275 | } | |
1276 | ||
1277 | band = (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) ? 0 : 1; | |
1278 | chan_num = le16_to_cpu(priv->staging_rxon.channel); | |
1279 | ||
1280 | /* Make sure we accumulate data for just the associated channel | |
1281 | * (even if scanning). */ | |
1282 | if ((chan_num != (le32_to_cpu(stat_resp->flag) >> 16)) || | |
1283 | ((STATISTICS_REPLY_FLG_BAND_24G_MSK == | |
1284 | (stat_resp->flag & STATISTICS_REPLY_FLG_BAND_24G_MSK)) && band)) { | |
1285 | IWL_DEBUG_CALIB("Stats not from chan=%d, band=%d\n", | |
1286 | chan_num, band); | |
1287 | spin_unlock_irqrestore(&priv->lock, flags); | |
1288 | return; | |
1289 | } | |
1290 | ||
1291 | /* Accumulate beacon statistics values across 20 beacons */ | |
1292 | chain_noise_a = le32_to_cpu(rx_info->beacon_silence_rssi_a) & | |
1293 | IN_BAND_FILTER; | |
1294 | chain_noise_b = le32_to_cpu(rx_info->beacon_silence_rssi_b) & | |
1295 | IN_BAND_FILTER; | |
1296 | chain_noise_c = le32_to_cpu(rx_info->beacon_silence_rssi_c) & | |
1297 | IN_BAND_FILTER; | |
1298 | ||
1299 | chain_sig_a = le32_to_cpu(rx_info->beacon_rssi_a) & IN_BAND_FILTER; | |
1300 | chain_sig_b = le32_to_cpu(rx_info->beacon_rssi_b) & IN_BAND_FILTER; | |
1301 | chain_sig_c = le32_to_cpu(rx_info->beacon_rssi_c) & IN_BAND_FILTER; | |
1302 | ||
1303 | spin_unlock_irqrestore(&priv->lock, flags); | |
1304 | ||
1305 | data->beacon_count++; | |
1306 | ||
1307 | data->chain_noise_a = (chain_noise_a + data->chain_noise_a); | |
1308 | data->chain_noise_b = (chain_noise_b + data->chain_noise_b); | |
1309 | data->chain_noise_c = (chain_noise_c + data->chain_noise_c); | |
1310 | ||
1311 | data->chain_signal_a = (chain_sig_a + data->chain_signal_a); | |
1312 | data->chain_signal_b = (chain_sig_b + data->chain_signal_b); | |
1313 | data->chain_signal_c = (chain_sig_c + data->chain_signal_c); | |
1314 | ||
1315 | IWL_DEBUG_CALIB("chan=%d, band=%d, beacon=%d\n", chan_num, band, | |
1316 | data->beacon_count); | |
1317 | IWL_DEBUG_CALIB("chain_sig: a %d b %d c %d\n", | |
1318 | chain_sig_a, chain_sig_b, chain_sig_c); | |
1319 | IWL_DEBUG_CALIB("chain_noise: a %d b %d c %d\n", | |
1320 | chain_noise_a, chain_noise_b, chain_noise_c); | |
1321 | ||
1322 | /* If this is the 20th beacon, determine: | |
1323 | * 1) Disconnected antennas (using signal strengths) | |
1324 | * 2) Differential gain (using silence noise) to balance receivers */ | |
1325 | if (data->beacon_count == CAL_NUM_OF_BEACONS) { | |
1326 | ||
1327 | /* Analyze signal for disconnected antenna */ | |
1328 | average_sig[0] = (data->chain_signal_a) / CAL_NUM_OF_BEACONS; | |
1329 | average_sig[1] = (data->chain_signal_b) / CAL_NUM_OF_BEACONS; | |
1330 | average_sig[2] = (data->chain_signal_c) / CAL_NUM_OF_BEACONS; | |
1331 | ||
1332 | if (average_sig[0] >= average_sig[1]) { | |
1333 | max_average_sig = average_sig[0]; | |
1334 | max_average_sig_antenna_i = 0; | |
1335 | active_chains = (1 << max_average_sig_antenna_i); | |
1336 | } else { | |
1337 | max_average_sig = average_sig[1]; | |
1338 | max_average_sig_antenna_i = 1; | |
1339 | active_chains = (1 << max_average_sig_antenna_i); | |
1340 | } | |
1341 | ||
1342 | if (average_sig[2] >= max_average_sig) { | |
1343 | max_average_sig = average_sig[2]; | |
1344 | max_average_sig_antenna_i = 2; | |
1345 | active_chains = (1 << max_average_sig_antenna_i); | |
1346 | } | |
1347 | ||
1348 | IWL_DEBUG_CALIB("average_sig: a %d b %d c %d\n", | |
1349 | average_sig[0], average_sig[1], average_sig[2]); | |
1350 | IWL_DEBUG_CALIB("max_average_sig = %d, antenna %d\n", | |
1351 | max_average_sig, max_average_sig_antenna_i); | |
1352 | ||
1353 | /* Compare signal strengths for all 3 receivers. */ | |
1354 | for (i = 0; i < NUM_RX_CHAINS; i++) { | |
1355 | if (i != max_average_sig_antenna_i) { | |
1356 | s32 rssi_delta = (max_average_sig - | |
1357 | average_sig[i]); | |
1358 | ||
1359 | /* If signal is very weak, compared with | |
1360 | * strongest, mark it as disconnected. */ | |
1361 | if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS) | |
1362 | data->disconn_array[i] = 1; | |
1363 | else | |
1364 | active_chains |= (1 << i); | |
1365 | IWL_DEBUG_CALIB("i = %d rssiDelta = %d " | |
1366 | "disconn_array[i] = %d\n", | |
1367 | i, rssi_delta, data->disconn_array[i]); | |
1368 | } | |
1369 | } | |
1370 | ||
1371 | /*If both chains A & B are disconnected - | |
1372 | * connect B and leave A as is */ | |
1373 | if (data->disconn_array[CHAIN_A] && | |
1374 | data->disconn_array[CHAIN_B]) { | |
1375 | data->disconn_array[CHAIN_B] = 0; | |
1376 | active_chains |= (1 << CHAIN_B); | |
1377 | IWL_DEBUG_CALIB("both A & B chains are disconnected! " | |
1378 | "W/A - declare B as connected\n"); | |
1379 | } | |
1380 | ||
1381 | IWL_DEBUG_CALIB("active_chains (bitwise) = 0x%x\n", | |
1382 | active_chains); | |
1383 | ||
1384 | /* Save for use within RXON, TX, SCAN commands, etc. */ | |
1385 | priv->valid_antenna = active_chains; | |
1386 | ||
1387 | /* Analyze noise for rx balance */ | |
1388 | average_noise[0] = ((data->chain_noise_a)/CAL_NUM_OF_BEACONS); | |
1389 | average_noise[1] = ((data->chain_noise_b)/CAL_NUM_OF_BEACONS); | |
1390 | average_noise[2] = ((data->chain_noise_c)/CAL_NUM_OF_BEACONS); | |
1391 | ||
1392 | for (i = 0; i < NUM_RX_CHAINS; i++) { | |
1393 | if (!(data->disconn_array[i]) && | |
1394 | (average_noise[i] <= min_average_noise)) { | |
1395 | /* This means that chain i is active and has | |
1396 | * lower noise values so far: */ | |
1397 | min_average_noise = average_noise[i]; | |
1398 | min_average_noise_antenna_i = i; | |
1399 | } | |
1400 | } | |
1401 | ||
1402 | data->delta_gain_code[min_average_noise_antenna_i] = 0; | |
1403 | ||
1404 | IWL_DEBUG_CALIB("average_noise: a %d b %d c %d\n", | |
1405 | average_noise[0], average_noise[1], | |
1406 | average_noise[2]); | |
1407 | ||
1408 | IWL_DEBUG_CALIB("min_average_noise = %d, antenna %d\n", | |
1409 | min_average_noise, min_average_noise_antenna_i); | |
1410 | ||
1411 | for (i = 0; i < NUM_RX_CHAINS; i++) { | |
1412 | s32 delta_g = 0; | |
1413 | ||
1414 | if (!(data->disconn_array[i]) && | |
1415 | (data->delta_gain_code[i] == | |
1416 | CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) { | |
1417 | delta_g = average_noise[i] - min_average_noise; | |
1418 | data->delta_gain_code[i] = (u8)((delta_g * | |
1419 | 10) / 15); | |
1420 | if (CHAIN_NOISE_MAX_DELTA_GAIN_CODE < | |
1421 | data->delta_gain_code[i]) | |
1422 | data->delta_gain_code[i] = | |
1423 | CHAIN_NOISE_MAX_DELTA_GAIN_CODE; | |
1424 | ||
1425 | data->delta_gain_code[i] = | |
1426 | (data->delta_gain_code[i] | (1 << 2)); | |
1427 | } else | |
1428 | data->delta_gain_code[i] = 0; | |
1429 | } | |
1430 | IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n", | |
1431 | data->delta_gain_code[0], | |
1432 | data->delta_gain_code[1], | |
1433 | data->delta_gain_code[2]); | |
1434 | ||
1435 | /* Differential gain gets sent to uCode only once */ | |
1436 | if (!data->radio_write) { | |
bb8c093b | 1437 | struct iwl4965_calibration_cmd cmd; |
b481de9c ZY |
1438 | data->radio_write = 1; |
1439 | ||
1440 | memset(&cmd, 0, sizeof(cmd)); | |
1441 | cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD; | |
1442 | cmd.diff_gain_a = data->delta_gain_code[0]; | |
1443 | cmd.diff_gain_b = data->delta_gain_code[1]; | |
1444 | cmd.diff_gain_c = data->delta_gain_code[2]; | |
bb8c093b | 1445 | rc = iwl4965_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, |
b481de9c ZY |
1446 | sizeof(cmd), &cmd); |
1447 | if (rc) | |
1448 | IWL_DEBUG_CALIB("fail sending cmd " | |
1449 | "REPLY_PHY_CALIBRATION_CMD \n"); | |
1450 | ||
1451 | /* TODO we might want recalculate | |
1452 | * rx_chain in rxon cmd */ | |
1453 | ||
1454 | /* Mark so we run this algo only once! */ | |
1455 | data->state = IWL_CHAIN_NOISE_CALIBRATED; | |
1456 | } | |
1457 | data->chain_noise_a = 0; | |
1458 | data->chain_noise_b = 0; | |
1459 | data->chain_noise_c = 0; | |
1460 | data->chain_signal_a = 0; | |
1461 | data->chain_signal_b = 0; | |
1462 | data->chain_signal_c = 0; | |
1463 | data->beacon_count = 0; | |
1464 | } | |
1465 | return; | |
1466 | } | |
1467 | ||
bb8c093b CH |
1468 | static void iwl4965_sensitivity_calibration(struct iwl4965_priv *priv, |
1469 | struct iwl4965_notif_statistics *resp) | |
b481de9c ZY |
1470 | { |
1471 | int rc = 0; | |
1472 | u32 rx_enable_time; | |
1473 | u32 fa_cck; | |
1474 | u32 fa_ofdm; | |
1475 | u32 bad_plcp_cck; | |
1476 | u32 bad_plcp_ofdm; | |
1477 | u32 norm_fa_ofdm; | |
1478 | u32 norm_fa_cck; | |
bb8c093b | 1479 | struct iwl4965_sensitivity_data *data = NULL; |
b481de9c ZY |
1480 | struct statistics_rx_non_phy *rx_info = &(resp->rx.general); |
1481 | struct statistics_rx *statistics = &(resp->rx); | |
1482 | unsigned long flags; | |
1483 | struct statistics_general_data statis; | |
1484 | ||
1485 | data = &(priv->sensitivity_data); | |
1486 | ||
bb8c093b | 1487 | if (!iwl4965_is_associated(priv)) { |
b481de9c ZY |
1488 | IWL_DEBUG_CALIB("<< - not associated\n"); |
1489 | return; | |
1490 | } | |
1491 | ||
1492 | spin_lock_irqsave(&priv->lock, flags); | |
1493 | if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) { | |
1494 | IWL_DEBUG_CALIB("<< invalid data.\n"); | |
1495 | spin_unlock_irqrestore(&priv->lock, flags); | |
1496 | return; | |
1497 | } | |
1498 | ||
1499 | /* Extract Statistics: */ | |
1500 | rx_enable_time = le32_to_cpu(rx_info->channel_load); | |
1501 | fa_cck = le32_to_cpu(statistics->cck.false_alarm_cnt); | |
1502 | fa_ofdm = le32_to_cpu(statistics->ofdm.false_alarm_cnt); | |
1503 | bad_plcp_cck = le32_to_cpu(statistics->cck.plcp_err); | |
1504 | bad_plcp_ofdm = le32_to_cpu(statistics->ofdm.plcp_err); | |
1505 | ||
1506 | statis.beacon_silence_rssi_a = | |
1507 | le32_to_cpu(statistics->general.beacon_silence_rssi_a); | |
1508 | statis.beacon_silence_rssi_b = | |
1509 | le32_to_cpu(statistics->general.beacon_silence_rssi_b); | |
1510 | statis.beacon_silence_rssi_c = | |
1511 | le32_to_cpu(statistics->general.beacon_silence_rssi_c); | |
1512 | statis.beacon_energy_a = | |
1513 | le32_to_cpu(statistics->general.beacon_energy_a); | |
1514 | statis.beacon_energy_b = | |
1515 | le32_to_cpu(statistics->general.beacon_energy_b); | |
1516 | statis.beacon_energy_c = | |
1517 | le32_to_cpu(statistics->general.beacon_energy_c); | |
1518 | ||
1519 | spin_unlock_irqrestore(&priv->lock, flags); | |
1520 | ||
1521 | IWL_DEBUG_CALIB("rx_enable_time = %u usecs\n", rx_enable_time); | |
1522 | ||
1523 | if (!rx_enable_time) { | |
1524 | IWL_DEBUG_CALIB("<< RX Enable Time == 0! \n"); | |
1525 | return; | |
1526 | } | |
1527 | ||
1528 | /* These statistics increase monotonically, and do not reset | |
1529 | * at each beacon. Calculate difference from last value, or just | |
1530 | * use the new statistics value if it has reset or wrapped around. */ | |
1531 | if (data->last_bad_plcp_cnt_cck > bad_plcp_cck) | |
1532 | data->last_bad_plcp_cnt_cck = bad_plcp_cck; | |
1533 | else { | |
1534 | bad_plcp_cck -= data->last_bad_plcp_cnt_cck; | |
1535 | data->last_bad_plcp_cnt_cck += bad_plcp_cck; | |
1536 | } | |
1537 | ||
1538 | if (data->last_bad_plcp_cnt_ofdm > bad_plcp_ofdm) | |
1539 | data->last_bad_plcp_cnt_ofdm = bad_plcp_ofdm; | |
1540 | else { | |
1541 | bad_plcp_ofdm -= data->last_bad_plcp_cnt_ofdm; | |
1542 | data->last_bad_plcp_cnt_ofdm += bad_plcp_ofdm; | |
1543 | } | |
1544 | ||
1545 | if (data->last_fa_cnt_ofdm > fa_ofdm) | |
1546 | data->last_fa_cnt_ofdm = fa_ofdm; | |
1547 | else { | |
1548 | fa_ofdm -= data->last_fa_cnt_ofdm; | |
1549 | data->last_fa_cnt_ofdm += fa_ofdm; | |
1550 | } | |
1551 | ||
1552 | if (data->last_fa_cnt_cck > fa_cck) | |
1553 | data->last_fa_cnt_cck = fa_cck; | |
1554 | else { | |
1555 | fa_cck -= data->last_fa_cnt_cck; | |
1556 | data->last_fa_cnt_cck += fa_cck; | |
1557 | } | |
1558 | ||
1559 | /* Total aborted signal locks */ | |
1560 | norm_fa_ofdm = fa_ofdm + bad_plcp_ofdm; | |
1561 | norm_fa_cck = fa_cck + bad_plcp_cck; | |
1562 | ||
1563 | IWL_DEBUG_CALIB("cck: fa %u badp %u ofdm: fa %u badp %u\n", fa_cck, | |
1564 | bad_plcp_cck, fa_ofdm, bad_plcp_ofdm); | |
1565 | ||
1566 | iwl4965_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time); | |
1567 | iwl4965_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis); | |
1568 | rc |= iwl4965_sensitivity_write(priv, CMD_ASYNC); | |
1569 | ||
1570 | return; | |
1571 | } | |
1572 | ||
1573 | static void iwl4965_bg_sensitivity_work(struct work_struct *work) | |
1574 | { | |
bb8c093b | 1575 | struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv, |
b481de9c ZY |
1576 | sensitivity_work); |
1577 | ||
1578 | mutex_lock(&priv->mutex); | |
1579 | ||
1580 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
1581 | test_bit(STATUS_SCANNING, &priv->status)) { | |
1582 | mutex_unlock(&priv->mutex); | |
1583 | return; | |
1584 | } | |
1585 | ||
1586 | if (priv->start_calib) { | |
1587 | iwl4965_noise_calibration(priv, &priv->statistics); | |
1588 | ||
1589 | if (priv->sensitivity_data.state == | |
1590 | IWL_SENS_CALIB_NEED_REINIT) { | |
1591 | iwl4965_init_sensitivity(priv, CMD_ASYNC, 0); | |
1592 | priv->sensitivity_data.state = IWL_SENS_CALIB_ALLOWED; | |
1593 | } else | |
1594 | iwl4965_sensitivity_calibration(priv, | |
1595 | &priv->statistics); | |
1596 | } | |
1597 | ||
1598 | mutex_unlock(&priv->mutex); | |
1599 | return; | |
1600 | } | |
c8b0e6e1 | 1601 | #endif /*CONFIG_IWL4965_SENSITIVITY*/ |
b481de9c ZY |
1602 | |
1603 | static void iwl4965_bg_txpower_work(struct work_struct *work) | |
1604 | { | |
bb8c093b | 1605 | struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv, |
b481de9c ZY |
1606 | txpower_work); |
1607 | ||
1608 | /* If a scan happened to start before we got here | |
1609 | * then just return; the statistics notification will | |
1610 | * kick off another scheduled work to compensate for | |
1611 | * any temperature delta we missed here. */ | |
1612 | if (test_bit(STATUS_EXIT_PENDING, &priv->status) || | |
1613 | test_bit(STATUS_SCANNING, &priv->status)) | |
1614 | return; | |
1615 | ||
1616 | mutex_lock(&priv->mutex); | |
1617 | ||
1618 | /* Regardless of if we are assocaited, we must reconfigure the | |
1619 | * TX power since frames can be sent on non-radar channels while | |
1620 | * not associated */ | |
bb8c093b | 1621 | iwl4965_hw_reg_send_txpower(priv); |
b481de9c ZY |
1622 | |
1623 | /* Update last_temperature to keep is_calib_needed from running | |
1624 | * when it isn't needed... */ | |
1625 | priv->last_temperature = priv->temperature; | |
1626 | ||
1627 | mutex_unlock(&priv->mutex); | |
1628 | } | |
1629 | ||
1630 | /* | |
1631 | * Acquire priv->lock before calling this function ! | |
1632 | */ | |
bb8c093b | 1633 | static void iwl4965_set_wr_ptrs(struct iwl4965_priv *priv, int txq_id, u32 index) |
b481de9c | 1634 | { |
bb8c093b | 1635 | iwl4965_write_direct32(priv, HBUS_TARG_WRPTR, |
b481de9c | 1636 | (index & 0xff) | (txq_id << 8)); |
bb8c093b | 1637 | iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index); |
b481de9c ZY |
1638 | } |
1639 | ||
8b6eaea8 CB |
1640 | /** |
1641 | * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue | |
1642 | * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed | |
1643 | * @scd_retry: (1) Indicates queue will be used in aggregation mode | |
1644 | * | |
1645 | * NOTE: Acquire priv->lock before calling this function ! | |
b481de9c | 1646 | */ |
bb8c093b CH |
1647 | static void iwl4965_tx_queue_set_status(struct iwl4965_priv *priv, |
1648 | struct iwl4965_tx_queue *txq, | |
b481de9c ZY |
1649 | int tx_fifo_id, int scd_retry) |
1650 | { | |
1651 | int txq_id = txq->q.id; | |
8b6eaea8 CB |
1652 | |
1653 | /* Find out whether to activate Tx queue */ | |
b481de9c ZY |
1654 | int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0; |
1655 | ||
8b6eaea8 | 1656 | /* Set up and activate */ |
bb8c093b | 1657 | iwl4965_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id), |
b481de9c ZY |
1658 | (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | |
1659 | (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | | |
1660 | (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) | | |
1661 | (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) | | |
1662 | SCD_QUEUE_STTS_REG_MSK); | |
1663 | ||
1664 | txq->sched_retry = scd_retry; | |
1665 | ||
1666 | IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n", | |
8b6eaea8 | 1667 | active ? "Activate" : "Deactivate", |
b481de9c ZY |
1668 | scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); |
1669 | } | |
1670 | ||
1671 | static const u16 default_queue_to_tx_fifo[] = { | |
1672 | IWL_TX_FIFO_AC3, | |
1673 | IWL_TX_FIFO_AC2, | |
1674 | IWL_TX_FIFO_AC1, | |
1675 | IWL_TX_FIFO_AC0, | |
1676 | IWL_CMD_FIFO_NUM, | |
1677 | IWL_TX_FIFO_HCCA_1, | |
1678 | IWL_TX_FIFO_HCCA_2 | |
1679 | }; | |
1680 | ||
bb8c093b | 1681 | static inline void iwl4965_txq_ctx_activate(struct iwl4965_priv *priv, int txq_id) |
b481de9c ZY |
1682 | { |
1683 | set_bit(txq_id, &priv->txq_ctx_active_msk); | |
1684 | } | |
1685 | ||
bb8c093b | 1686 | static inline void iwl4965_txq_ctx_deactivate(struct iwl4965_priv *priv, int txq_id) |
b481de9c ZY |
1687 | { |
1688 | clear_bit(txq_id, &priv->txq_ctx_active_msk); | |
1689 | } | |
1690 | ||
bb8c093b | 1691 | int iwl4965_alive_notify(struct iwl4965_priv *priv) |
b481de9c ZY |
1692 | { |
1693 | u32 a; | |
1694 | int i = 0; | |
1695 | unsigned long flags; | |
1696 | int rc; | |
1697 | ||
1698 | spin_lock_irqsave(&priv->lock, flags); | |
1699 | ||
c8b0e6e1 | 1700 | #ifdef CONFIG_IWL4965_SENSITIVITY |
b481de9c | 1701 | memset(&(priv->sensitivity_data), 0, |
bb8c093b | 1702 | sizeof(struct iwl4965_sensitivity_data)); |
b481de9c | 1703 | memset(&(priv->chain_noise_data), 0, |
bb8c093b | 1704 | sizeof(struct iwl4965_chain_noise_data)); |
b481de9c ZY |
1705 | for (i = 0; i < NUM_RX_CHAINS; i++) |
1706 | priv->chain_noise_data.delta_gain_code[i] = | |
1707 | CHAIN_NOISE_DELTA_GAIN_INIT_VAL; | |
c8b0e6e1 | 1708 | #endif /* CONFIG_IWL4965_SENSITIVITY*/ |
bb8c093b | 1709 | rc = iwl4965_grab_nic_access(priv); |
b481de9c ZY |
1710 | if (rc) { |
1711 | spin_unlock_irqrestore(&priv->lock, flags); | |
1712 | return rc; | |
1713 | } | |
1714 | ||
8b6eaea8 | 1715 | /* Clear 4965's internal Tx Scheduler data base */ |
bb8c093b | 1716 | priv->scd_base_addr = iwl4965_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR); |
b481de9c ZY |
1717 | a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET; |
1718 | for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4) | |
bb8c093b | 1719 | iwl4965_write_targ_mem(priv, a, 0); |
b481de9c | 1720 | for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4) |
bb8c093b | 1721 | iwl4965_write_targ_mem(priv, a, 0); |
b481de9c | 1722 | for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4) |
bb8c093b | 1723 | iwl4965_write_targ_mem(priv, a, 0); |
b481de9c | 1724 | |
8b6eaea8 | 1725 | /* Tel 4965 where to find Tx byte count tables */ |
bb8c093b | 1726 | iwl4965_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR, |
b481de9c | 1727 | (priv->hw_setting.shared_phys + |
bb8c093b | 1728 | offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10); |
8b6eaea8 CB |
1729 | |
1730 | /* Disable chain mode for all queues */ | |
bb8c093b | 1731 | iwl4965_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0); |
b481de9c | 1732 | |
8b6eaea8 | 1733 | /* Initialize each Tx queue (including the command queue) */ |
b481de9c | 1734 | for (i = 0; i < priv->hw_setting.max_txq_num; i++) { |
8b6eaea8 CB |
1735 | |
1736 | /* TFD circular buffer read/write indexes */ | |
bb8c093b CH |
1737 | iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0); |
1738 | iwl4965_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); | |
8b6eaea8 CB |
1739 | |
1740 | /* Max Tx Window size for Scheduler-ACK mode */ | |
bb8c093b | 1741 | iwl4965_write_targ_mem(priv, priv->scd_base_addr + |
b481de9c ZY |
1742 | SCD_CONTEXT_QUEUE_OFFSET(i), |
1743 | (SCD_WIN_SIZE << | |
1744 | SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & | |
1745 | SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); | |
8b6eaea8 CB |
1746 | |
1747 | /* Frame limit */ | |
bb8c093b | 1748 | iwl4965_write_targ_mem(priv, priv->scd_base_addr + |
b481de9c ZY |
1749 | SCD_CONTEXT_QUEUE_OFFSET(i) + |
1750 | sizeof(u32), | |
1751 | (SCD_FRAME_LIMIT << | |
1752 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
1753 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); | |
1754 | ||
1755 | } | |
bb8c093b | 1756 | iwl4965_write_prph(priv, KDR_SCD_INTERRUPT_MASK, |
b481de9c ZY |
1757 | (1 << priv->hw_setting.max_txq_num) - 1); |
1758 | ||
8b6eaea8 | 1759 | /* Activate all Tx DMA/FIFO channels */ |
bb8c093b | 1760 | iwl4965_write_prph(priv, KDR_SCD_TXFACT, |
b481de9c ZY |
1761 | SCD_TXFACT_REG_TXFIFO_MASK(0, 7)); |
1762 | ||
1763 | iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); | |
8b6eaea8 CB |
1764 | |
1765 | /* Map each Tx/cmd queue to its corresponding fifo */ | |
b481de9c ZY |
1766 | for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) { |
1767 | int ac = default_queue_to_tx_fifo[i]; | |
1768 | iwl4965_txq_ctx_activate(priv, i); | |
1769 | iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0); | |
1770 | } | |
1771 | ||
bb8c093b | 1772 | iwl4965_release_nic_access(priv); |
b481de9c ZY |
1773 | spin_unlock_irqrestore(&priv->lock, flags); |
1774 | ||
1775 | return 0; | |
1776 | } | |
1777 | ||
8b6eaea8 CB |
1778 | /** |
1779 | * iwl4965_hw_set_hw_setting | |
1780 | * | |
1781 | * Called when initializing driver | |
1782 | */ | |
bb8c093b | 1783 | int iwl4965_hw_set_hw_setting(struct iwl4965_priv *priv) |
b481de9c | 1784 | { |
8b6eaea8 | 1785 | /* Allocate area for Tx byte count tables and Rx queue status */ |
b481de9c ZY |
1786 | priv->hw_setting.shared_virt = |
1787 | pci_alloc_consistent(priv->pci_dev, | |
bb8c093b | 1788 | sizeof(struct iwl4965_shared), |
b481de9c ZY |
1789 | &priv->hw_setting.shared_phys); |
1790 | ||
1791 | if (!priv->hw_setting.shared_virt) | |
1792 | return -1; | |
1793 | ||
bb8c093b | 1794 | memset(priv->hw_setting.shared_virt, 0, sizeof(struct iwl4965_shared)); |
b481de9c | 1795 | |
bb8c093b | 1796 | priv->hw_setting.max_txq_num = iwl4965_param_queues_num; |
b481de9c | 1797 | priv->hw_setting.ac_queue_count = AC_NUM; |
bb8c093b | 1798 | priv->hw_setting.tx_cmd_len = sizeof(struct iwl4965_tx_cmd); |
b481de9c ZY |
1799 | priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE; |
1800 | priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG; | |
9ee1ba47 RR |
1801 | if (iwl4965_param_amsdu_size_8K) |
1802 | priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_8K; | |
1803 | else | |
1804 | priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_4K; | |
1805 | priv->hw_setting.max_pkt_size = priv->hw_setting.rx_buf_size - 256; | |
b481de9c ZY |
1806 | priv->hw_setting.max_stations = IWL4965_STATION_COUNT; |
1807 | priv->hw_setting.bcast_sta_id = IWL4965_BROADCAST_ID; | |
1808 | return 0; | |
1809 | } | |
1810 | ||
1811 | /** | |
bb8c093b | 1812 | * iwl4965_hw_txq_ctx_free - Free TXQ Context |
b481de9c ZY |
1813 | * |
1814 | * Destroy all TX DMA queues and structures | |
1815 | */ | |
bb8c093b | 1816 | void iwl4965_hw_txq_ctx_free(struct iwl4965_priv *priv) |
b481de9c ZY |
1817 | { |
1818 | int txq_id; | |
1819 | ||
1820 | /* Tx queues */ | |
1821 | for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) | |
bb8c093b | 1822 | iwl4965_tx_queue_free(priv, &priv->txq[txq_id]); |
b481de9c | 1823 | |
8b6eaea8 | 1824 | /* Keep-warm buffer */ |
b481de9c ZY |
1825 | iwl4965_kw_free(priv); |
1826 | } | |
1827 | ||
1828 | /** | |
8b6eaea8 | 1829 | * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] |
b481de9c | 1830 | * |
8b6eaea8 CB |
1831 | * Does NOT advance any TFD circular buffer read/write indexes |
1832 | * Does NOT free the TFD itself (which is within circular buffer) | |
b481de9c | 1833 | */ |
bb8c093b | 1834 | int iwl4965_hw_txq_free_tfd(struct iwl4965_priv *priv, struct iwl4965_tx_queue *txq) |
b481de9c | 1835 | { |
bb8c093b CH |
1836 | struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0]; |
1837 | struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr]; | |
b481de9c ZY |
1838 | struct pci_dev *dev = priv->pci_dev; |
1839 | int i; | |
1840 | int counter = 0; | |
1841 | int index, is_odd; | |
1842 | ||
8b6eaea8 | 1843 | /* Host command buffers stay mapped in memory, nothing to clean */ |
b481de9c | 1844 | if (txq->q.id == IWL_CMD_QUEUE_NUM) |
b481de9c ZY |
1845 | return 0; |
1846 | ||
8b6eaea8 | 1847 | /* Sanity check on number of chunks */ |
b481de9c ZY |
1848 | counter = IWL_GET_BITS(*bd, num_tbs); |
1849 | if (counter > MAX_NUM_OF_TBS) { | |
1850 | IWL_ERROR("Too many chunks: %i\n", counter); | |
1851 | /* @todo issue fatal error, it is quite serious situation */ | |
1852 | return 0; | |
1853 | } | |
1854 | ||
8b6eaea8 CB |
1855 | /* Unmap chunks, if any. |
1856 | * TFD info for odd chunks is different format than for even chunks. */ | |
b481de9c ZY |
1857 | for (i = 0; i < counter; i++) { |
1858 | index = i / 2; | |
1859 | is_odd = i & 0x1; | |
1860 | ||
1861 | if (is_odd) | |
1862 | pci_unmap_single( | |
1863 | dev, | |
1864 | IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) | | |
1865 | (IWL_GET_BITS(bd->pa[index], | |
1866 | tb2_addr_hi20) << 16), | |
1867 | IWL_GET_BITS(bd->pa[index], tb2_len), | |
1868 | PCI_DMA_TODEVICE); | |
1869 | ||
1870 | else if (i > 0) | |
1871 | pci_unmap_single(dev, | |
1872 | le32_to_cpu(bd->pa[index].tb1_addr), | |
1873 | IWL_GET_BITS(bd->pa[index], tb1_len), | |
1874 | PCI_DMA_TODEVICE); | |
1875 | ||
8b6eaea8 | 1876 | /* Free SKB, if any, for this chunk */ |
fc4b6853 TW |
1877 | if (txq->txb[txq->q.read_ptr].skb[i]) { |
1878 | struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i]; | |
b481de9c ZY |
1879 | |
1880 | dev_kfree_skb(skb); | |
fc4b6853 | 1881 | txq->txb[txq->q.read_ptr].skb[i] = NULL; |
b481de9c ZY |
1882 | } |
1883 | } | |
1884 | return 0; | |
1885 | } | |
1886 | ||
bb8c093b | 1887 | int iwl4965_hw_reg_set_txpower(struct iwl4965_priv *priv, s8 power) |
b481de9c | 1888 | { |
bb8c093b | 1889 | IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n"); |
b481de9c ZY |
1890 | return -EINVAL; |
1891 | } | |
1892 | ||
1893 | static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res) | |
1894 | { | |
1895 | s32 sign = 1; | |
1896 | ||
1897 | if (num < 0) { | |
1898 | sign = -sign; | |
1899 | num = -num; | |
1900 | } | |
1901 | if (denom < 0) { | |
1902 | sign = -sign; | |
1903 | denom = -denom; | |
1904 | } | |
1905 | *res = 1; | |
1906 | *res = ((num * 2 + denom) / (denom * 2)) * sign; | |
1907 | ||
1908 | return 1; | |
1909 | } | |
1910 | ||
8b6eaea8 CB |
1911 | /** |
1912 | * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower | |
1913 | * | |
1914 | * Determines power supply voltage compensation for txpower calculations. | |
1915 | * Returns number of 1/2-dB steps to subtract from gain table index, | |
1916 | * to compensate for difference between power supply voltage during | |
1917 | * factory measurements, vs. current power supply voltage. | |
1918 | * | |
1919 | * Voltage indication is higher for lower voltage. | |
1920 | * Lower voltage requires more gain (lower gain table index). | |
1921 | */ | |
b481de9c ZY |
1922 | static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage, |
1923 | s32 current_voltage) | |
1924 | { | |
1925 | s32 comp = 0; | |
1926 | ||
1927 | if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) || | |
1928 | (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage)) | |
1929 | return 0; | |
1930 | ||
1931 | iwl4965_math_div_round(current_voltage - eeprom_voltage, | |
1932 | TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp); | |
1933 | ||
1934 | if (current_voltage > eeprom_voltage) | |
1935 | comp *= 2; | |
1936 | if ((comp < -2) || (comp > 2)) | |
1937 | comp = 0; | |
1938 | ||
1939 | return comp; | |
1940 | } | |
1941 | ||
bb8c093b | 1942 | static const struct iwl4965_channel_info * |
8318d78a JB |
1943 | iwl4965_get_channel_txpower_info(struct iwl4965_priv *priv, |
1944 | enum ieee80211_band band, u16 channel) | |
b481de9c | 1945 | { |
bb8c093b | 1946 | const struct iwl4965_channel_info *ch_info; |
b481de9c | 1947 | |
8318d78a | 1948 | ch_info = iwl4965_get_channel_info(priv, band, channel); |
b481de9c ZY |
1949 | |
1950 | if (!is_channel_valid(ch_info)) | |
1951 | return NULL; | |
1952 | ||
1953 | return ch_info; | |
1954 | } | |
1955 | ||
1956 | static s32 iwl4965_get_tx_atten_grp(u16 channel) | |
1957 | { | |
1958 | if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH && | |
1959 | channel <= CALIB_IWL_TX_ATTEN_GR5_LCH) | |
1960 | return CALIB_CH_GROUP_5; | |
1961 | ||
1962 | if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH && | |
1963 | channel <= CALIB_IWL_TX_ATTEN_GR1_LCH) | |
1964 | return CALIB_CH_GROUP_1; | |
1965 | ||
1966 | if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH && | |
1967 | channel <= CALIB_IWL_TX_ATTEN_GR2_LCH) | |
1968 | return CALIB_CH_GROUP_2; | |
1969 | ||
1970 | if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH && | |
1971 | channel <= CALIB_IWL_TX_ATTEN_GR3_LCH) | |
1972 | return CALIB_CH_GROUP_3; | |
1973 | ||
1974 | if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH && | |
1975 | channel <= CALIB_IWL_TX_ATTEN_GR4_LCH) | |
1976 | return CALIB_CH_GROUP_4; | |
1977 | ||
1978 | IWL_ERROR("Can't find txatten group for channel %d.\n", channel); | |
1979 | return -1; | |
1980 | } | |
1981 | ||
bb8c093b | 1982 | static u32 iwl4965_get_sub_band(const struct iwl4965_priv *priv, u32 channel) |
b481de9c ZY |
1983 | { |
1984 | s32 b = -1; | |
1985 | ||
1986 | for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) { | |
1987 | if (priv->eeprom.calib_info.band_info[b].ch_from == 0) | |
1988 | continue; | |
1989 | ||
1990 | if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from) | |
1991 | && (channel <= priv->eeprom.calib_info.band_info[b].ch_to)) | |
1992 | break; | |
1993 | } | |
1994 | ||
1995 | return b; | |
1996 | } | |
1997 | ||
1998 | static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2) | |
1999 | { | |
2000 | s32 val; | |
2001 | ||
2002 | if (x2 == x1) | |
2003 | return y1; | |
2004 | else { | |
2005 | iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val); | |
2006 | return val + y2; | |
2007 | } | |
2008 | } | |
2009 | ||
8b6eaea8 CB |
2010 | /** |
2011 | * iwl4965_interpolate_chan - Interpolate factory measurements for one channel | |
2012 | * | |
2013 | * Interpolates factory measurements from the two sample channels within a | |
2014 | * sub-band, to apply to channel of interest. Interpolation is proportional to | |
2015 | * differences in channel frequencies, which is proportional to differences | |
2016 | * in channel number. | |
2017 | */ | |
bb8c093b CH |
2018 | static int iwl4965_interpolate_chan(struct iwl4965_priv *priv, u32 channel, |
2019 | struct iwl4965_eeprom_calib_ch_info *chan_info) | |
b481de9c ZY |
2020 | { |
2021 | s32 s = -1; | |
2022 | u32 c; | |
2023 | u32 m; | |
bb8c093b CH |
2024 | const struct iwl4965_eeprom_calib_measure *m1; |
2025 | const struct iwl4965_eeprom_calib_measure *m2; | |
2026 | struct iwl4965_eeprom_calib_measure *omeas; | |
b481de9c ZY |
2027 | u32 ch_i1; |
2028 | u32 ch_i2; | |
2029 | ||
2030 | s = iwl4965_get_sub_band(priv, channel); | |
2031 | if (s >= EEPROM_TX_POWER_BANDS) { | |
2032 | IWL_ERROR("Tx Power can not find channel %d ", channel); | |
2033 | return -1; | |
2034 | } | |
2035 | ||
2036 | ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num; | |
2037 | ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num; | |
2038 | chan_info->ch_num = (u8) channel; | |
2039 | ||
2040 | IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n", | |
2041 | channel, s, ch_i1, ch_i2); | |
2042 | ||
2043 | for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) { | |
2044 | for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) { | |
2045 | m1 = &(priv->eeprom.calib_info.band_info[s].ch1. | |
2046 | measurements[c][m]); | |
2047 | m2 = &(priv->eeprom.calib_info.band_info[s].ch2. | |
2048 | measurements[c][m]); | |
2049 | omeas = &(chan_info->measurements[c][m]); | |
2050 | ||
2051 | omeas->actual_pow = | |
2052 | (u8) iwl4965_interpolate_value(channel, ch_i1, | |
2053 | m1->actual_pow, | |
2054 | ch_i2, | |
2055 | m2->actual_pow); | |
2056 | omeas->gain_idx = | |
2057 | (u8) iwl4965_interpolate_value(channel, ch_i1, | |
2058 | m1->gain_idx, ch_i2, | |
2059 | m2->gain_idx); | |
2060 | omeas->temperature = | |
2061 | (u8) iwl4965_interpolate_value(channel, ch_i1, | |
2062 | m1->temperature, | |
2063 | ch_i2, | |
2064 | m2->temperature); | |
2065 | omeas->pa_det = | |
2066 | (s8) iwl4965_interpolate_value(channel, ch_i1, | |
2067 | m1->pa_det, ch_i2, | |
2068 | m2->pa_det); | |
2069 | ||
2070 | IWL_DEBUG_TXPOWER | |
2071 | ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m, | |
2072 | m1->actual_pow, m2->actual_pow, omeas->actual_pow); | |
2073 | IWL_DEBUG_TXPOWER | |
2074 | ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m, | |
2075 | m1->gain_idx, m2->gain_idx, omeas->gain_idx); | |
2076 | IWL_DEBUG_TXPOWER | |
2077 | ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m, | |
2078 | m1->pa_det, m2->pa_det, omeas->pa_det); | |
2079 | IWL_DEBUG_TXPOWER | |
2080 | ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m, | |
2081 | m1->temperature, m2->temperature, | |
2082 | omeas->temperature); | |
2083 | } | |
2084 | } | |
2085 | ||
2086 | return 0; | |
2087 | } | |
2088 | ||
2089 | /* bit-rate-dependent table to prevent Tx distortion, in half-dB units, | |
2090 | * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */ | |
2091 | static s32 back_off_table[] = { | |
2092 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */ | |
2093 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */ | |
2094 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */ | |
2095 | 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */ | |
2096 | 10 /* CCK */ | |
2097 | }; | |
2098 | ||
2099 | /* Thermal compensation values for txpower for various frequency ranges ... | |
2100 | * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */ | |
bb8c093b | 2101 | static struct iwl4965_txpower_comp_entry { |
b481de9c ZY |
2102 | s32 degrees_per_05db_a; |
2103 | s32 degrees_per_05db_a_denom; | |
2104 | } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = { | |
2105 | {9, 2}, /* group 0 5.2, ch 34-43 */ | |
2106 | {4, 1}, /* group 1 5.2, ch 44-70 */ | |
2107 | {4, 1}, /* group 2 5.2, ch 71-124 */ | |
2108 | {4, 1}, /* group 3 5.2, ch 125-200 */ | |
2109 | {3, 1} /* group 4 2.4, ch all */ | |
2110 | }; | |
2111 | ||
2112 | static s32 get_min_power_index(s32 rate_power_index, u32 band) | |
2113 | { | |
2114 | if (!band) { | |
2115 | if ((rate_power_index & 7) <= 4) | |
2116 | return MIN_TX_GAIN_INDEX_52GHZ_EXT; | |
2117 | } | |
2118 | return MIN_TX_GAIN_INDEX; | |
2119 | } | |
2120 | ||
2121 | struct gain_entry { | |
2122 | u8 dsp; | |
2123 | u8 radio; | |
2124 | }; | |
2125 | ||
2126 | static const struct gain_entry gain_table[2][108] = { | |
2127 | /* 5.2GHz power gain index table */ | |
2128 | { | |
2129 | {123, 0x3F}, /* highest txpower */ | |
2130 | {117, 0x3F}, | |
2131 | {110, 0x3F}, | |
2132 | {104, 0x3F}, | |
2133 | {98, 0x3F}, | |
2134 | {110, 0x3E}, | |
2135 | {104, 0x3E}, | |
2136 | {98, 0x3E}, | |
2137 | {110, 0x3D}, | |
2138 | {104, 0x3D}, | |
2139 | {98, 0x3D}, | |
2140 | {110, 0x3C}, | |
2141 | {104, 0x3C}, | |
2142 | {98, 0x3C}, | |
2143 | {110, 0x3B}, | |
2144 | {104, 0x3B}, | |
2145 | {98, 0x3B}, | |
2146 | {110, 0x3A}, | |
2147 | {104, 0x3A}, | |
2148 | {98, 0x3A}, | |
2149 | {110, 0x39}, | |
2150 | {104, 0x39}, | |
2151 | {98, 0x39}, | |
2152 | {110, 0x38}, | |
2153 | {104, 0x38}, | |
2154 | {98, 0x38}, | |
2155 | {110, 0x37}, | |
2156 | {104, 0x37}, | |
2157 | {98, 0x37}, | |
2158 | {110, 0x36}, | |
2159 | {104, 0x36}, | |
2160 | {98, 0x36}, | |
2161 | {110, 0x35}, | |
2162 | {104, 0x35}, | |
2163 | {98, 0x35}, | |
2164 | {110, 0x34}, | |
2165 | {104, 0x34}, | |
2166 | {98, 0x34}, | |
2167 | {110, 0x33}, | |
2168 | {104, 0x33}, | |
2169 | {98, 0x33}, | |
2170 | {110, 0x32}, | |
2171 | {104, 0x32}, | |
2172 | {98, 0x32}, | |
2173 | {110, 0x31}, | |
2174 | {104, 0x31}, | |
2175 | {98, 0x31}, | |
2176 | {110, 0x30}, | |
2177 | {104, 0x30}, | |
2178 | {98, 0x30}, | |
2179 | {110, 0x25}, | |
2180 | {104, 0x25}, | |
2181 | {98, 0x25}, | |
2182 | {110, 0x24}, | |
2183 | {104, 0x24}, | |
2184 | {98, 0x24}, | |
2185 | {110, 0x23}, | |
2186 | {104, 0x23}, | |
2187 | {98, 0x23}, | |
2188 | {110, 0x22}, | |
2189 | {104, 0x18}, | |
2190 | {98, 0x18}, | |
2191 | {110, 0x17}, | |
2192 | {104, 0x17}, | |
2193 | {98, 0x17}, | |
2194 | {110, 0x16}, | |
2195 | {104, 0x16}, | |
2196 | {98, 0x16}, | |
2197 | {110, 0x15}, | |
2198 | {104, 0x15}, | |
2199 | {98, 0x15}, | |
2200 | {110, 0x14}, | |
2201 | {104, 0x14}, | |
2202 | {98, 0x14}, | |
2203 | {110, 0x13}, | |
2204 | {104, 0x13}, | |
2205 | {98, 0x13}, | |
2206 | {110, 0x12}, | |
2207 | {104, 0x08}, | |
2208 | {98, 0x08}, | |
2209 | {110, 0x07}, | |
2210 | {104, 0x07}, | |
2211 | {98, 0x07}, | |
2212 | {110, 0x06}, | |
2213 | {104, 0x06}, | |
2214 | {98, 0x06}, | |
2215 | {110, 0x05}, | |
2216 | {104, 0x05}, | |
2217 | {98, 0x05}, | |
2218 | {110, 0x04}, | |
2219 | {104, 0x04}, | |
2220 | {98, 0x04}, | |
2221 | {110, 0x03}, | |
2222 | {104, 0x03}, | |
2223 | {98, 0x03}, | |
2224 | {110, 0x02}, | |
2225 | {104, 0x02}, | |
2226 | {98, 0x02}, | |
2227 | {110, 0x01}, | |
2228 | {104, 0x01}, | |
2229 | {98, 0x01}, | |
2230 | {110, 0x00}, | |
2231 | {104, 0x00}, | |
2232 | {98, 0x00}, | |
2233 | {93, 0x00}, | |
2234 | {88, 0x00}, | |
2235 | {83, 0x00}, | |
2236 | {78, 0x00}, | |
2237 | }, | |
2238 | /* 2.4GHz power gain index table */ | |
2239 | { | |
2240 | {110, 0x3f}, /* highest txpower */ | |
2241 | {104, 0x3f}, | |
2242 | {98, 0x3f}, | |
2243 | {110, 0x3e}, | |
2244 | {104, 0x3e}, | |
2245 | {98, 0x3e}, | |
2246 | {110, 0x3d}, | |
2247 | {104, 0x3d}, | |
2248 | {98, 0x3d}, | |
2249 | {110, 0x3c}, | |
2250 | {104, 0x3c}, | |
2251 | {98, 0x3c}, | |
2252 | {110, 0x3b}, | |
2253 | {104, 0x3b}, | |
2254 | {98, 0x3b}, | |
2255 | {110, 0x3a}, | |
2256 | {104, 0x3a}, | |
2257 | {98, 0x3a}, | |
2258 | {110, 0x39}, | |
2259 | {104, 0x39}, | |
2260 | {98, 0x39}, | |
2261 | {110, 0x38}, | |
2262 | {104, 0x38}, | |
2263 | {98, 0x38}, | |
2264 | {110, 0x37}, | |
2265 | {104, 0x37}, | |
2266 | {98, 0x37}, | |
2267 | {110, 0x36}, | |
2268 | {104, 0x36}, | |
2269 | {98, 0x36}, | |
2270 | {110, 0x35}, | |
2271 | {104, 0x35}, | |
2272 | {98, 0x35}, | |
2273 | {110, 0x34}, | |
2274 | {104, 0x34}, | |
2275 | {98, 0x34}, | |
2276 | {110, 0x33}, | |
2277 | {104, 0x33}, | |
2278 | {98, 0x33}, | |
2279 | {110, 0x32}, | |
2280 | {104, 0x32}, | |
2281 | {98, 0x32}, | |
2282 | {110, 0x31}, | |
2283 | {104, 0x31}, | |
2284 | {98, 0x31}, | |
2285 | {110, 0x30}, | |
2286 | {104, 0x30}, | |
2287 | {98, 0x30}, | |
2288 | {110, 0x6}, | |
2289 | {104, 0x6}, | |
2290 | {98, 0x6}, | |
2291 | {110, 0x5}, | |
2292 | {104, 0x5}, | |
2293 | {98, 0x5}, | |
2294 | {110, 0x4}, | |
2295 | {104, 0x4}, | |
2296 | {98, 0x4}, | |
2297 | {110, 0x3}, | |
2298 | {104, 0x3}, | |
2299 | {98, 0x3}, | |
2300 | {110, 0x2}, | |
2301 | {104, 0x2}, | |
2302 | {98, 0x2}, | |
2303 | {110, 0x1}, | |
2304 | {104, 0x1}, | |
2305 | {98, 0x1}, | |
2306 | {110, 0x0}, | |
2307 | {104, 0x0}, | |
2308 | {98, 0x0}, | |
2309 | {97, 0}, | |
2310 | {96, 0}, | |
2311 | {95, 0}, | |
2312 | {94, 0}, | |
2313 | {93, 0}, | |
2314 | {92, 0}, | |
2315 | {91, 0}, | |
2316 | {90, 0}, | |
2317 | {89, 0}, | |
2318 | {88, 0}, | |
2319 | {87, 0}, | |
2320 | {86, 0}, | |
2321 | {85, 0}, | |
2322 | {84, 0}, | |
2323 | {83, 0}, | |
2324 | {82, 0}, | |
2325 | {81, 0}, | |
2326 | {80, 0}, | |
2327 | {79, 0}, | |
2328 | {78, 0}, | |
2329 | {77, 0}, | |
2330 | {76, 0}, | |
2331 | {75, 0}, | |
2332 | {74, 0}, | |
2333 | {73, 0}, | |
2334 | {72, 0}, | |
2335 | {71, 0}, | |
2336 | {70, 0}, | |
2337 | {69, 0}, | |
2338 | {68, 0}, | |
2339 | {67, 0}, | |
2340 | {66, 0}, | |
2341 | {65, 0}, | |
2342 | {64, 0}, | |
2343 | {63, 0}, | |
2344 | {62, 0}, | |
2345 | {61, 0}, | |
2346 | {60, 0}, | |
2347 | {59, 0}, | |
2348 | } | |
2349 | }; | |
2350 | ||
bb8c093b | 2351 | static int iwl4965_fill_txpower_tbl(struct iwl4965_priv *priv, u8 band, u16 channel, |
b481de9c | 2352 | u8 is_fat, u8 ctrl_chan_high, |
bb8c093b | 2353 | struct iwl4965_tx_power_db *tx_power_tbl) |
b481de9c ZY |
2354 | { |
2355 | u8 saturation_power; | |
2356 | s32 target_power; | |
2357 | s32 user_target_power; | |
2358 | s32 power_limit; | |
2359 | s32 current_temp; | |
2360 | s32 reg_limit; | |
2361 | s32 current_regulatory; | |
2362 | s32 txatten_grp = CALIB_CH_GROUP_MAX; | |
2363 | int i; | |
2364 | int c; | |
bb8c093b CH |
2365 | const struct iwl4965_channel_info *ch_info = NULL; |
2366 | struct iwl4965_eeprom_calib_ch_info ch_eeprom_info; | |
2367 | const struct iwl4965_eeprom_calib_measure *measurement; | |
b481de9c ZY |
2368 | s16 voltage; |
2369 | s32 init_voltage; | |
2370 | s32 voltage_compensation; | |
2371 | s32 degrees_per_05db_num; | |
2372 | s32 degrees_per_05db_denom; | |
2373 | s32 factory_temp; | |
2374 | s32 temperature_comp[2]; | |
2375 | s32 factory_gain_index[2]; | |
2376 | s32 factory_actual_pwr[2]; | |
2377 | s32 power_index; | |
2378 | ||
2379 | /* Sanity check requested level (dBm) */ | |
2380 | if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) { | |
2381 | IWL_WARNING("Requested user TXPOWER %d below limit.\n", | |
2382 | priv->user_txpower_limit); | |
2383 | return -EINVAL; | |
2384 | } | |
2385 | if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) { | |
2386 | IWL_WARNING("Requested user TXPOWER %d above limit.\n", | |
2387 | priv->user_txpower_limit); | |
2388 | return -EINVAL; | |
2389 | } | |
2390 | ||
2391 | /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units | |
2392 | * are used for indexing into txpower table) */ | |
2393 | user_target_power = 2 * priv->user_txpower_limit; | |
2394 | ||
2395 | /* Get current (RXON) channel, band, width */ | |
2396 | ch_info = | |
8318d78a | 2397 | iwl4965_get_channel_txpower_info(priv, priv->band, channel); |
b481de9c ZY |
2398 | |
2399 | IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band, | |
2400 | is_fat); | |
2401 | ||
2402 | if (!ch_info) | |
2403 | return -EINVAL; | |
2404 | ||
2405 | /* get txatten group, used to select 1) thermal txpower adjustment | |
2406 | * and 2) mimo txpower balance between Tx chains. */ | |
2407 | txatten_grp = iwl4965_get_tx_atten_grp(channel); | |
2408 | if (txatten_grp < 0) | |
2409 | return -EINVAL; | |
2410 | ||
2411 | IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n", | |
2412 | channel, txatten_grp); | |
2413 | ||
2414 | if (is_fat) { | |
2415 | if (ctrl_chan_high) | |
2416 | channel -= 2; | |
2417 | else | |
2418 | channel += 2; | |
2419 | } | |
2420 | ||
2421 | /* hardware txpower limits ... | |
2422 | * saturation (clipping distortion) txpowers are in half-dBm */ | |
2423 | if (band) | |
2424 | saturation_power = priv->eeprom.calib_info.saturation_power24; | |
2425 | else | |
2426 | saturation_power = priv->eeprom.calib_info.saturation_power52; | |
2427 | ||
2428 | if (saturation_power < IWL_TX_POWER_SATURATION_MIN || | |
2429 | saturation_power > IWL_TX_POWER_SATURATION_MAX) { | |
2430 | if (band) | |
2431 | saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24; | |
2432 | else | |
2433 | saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52; | |
2434 | } | |
2435 | ||
2436 | /* regulatory txpower limits ... reg_limit values are in half-dBm, | |
2437 | * max_power_avg values are in dBm, convert * 2 */ | |
2438 | if (is_fat) | |
2439 | reg_limit = ch_info->fat_max_power_avg * 2; | |
2440 | else | |
2441 | reg_limit = ch_info->max_power_avg * 2; | |
2442 | ||
2443 | if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) || | |
2444 | (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) { | |
2445 | if (band) | |
2446 | reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24; | |
2447 | else | |
2448 | reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52; | |
2449 | } | |
2450 | ||
2451 | /* Interpolate txpower calibration values for this channel, | |
2452 | * based on factory calibration tests on spaced channels. */ | |
2453 | iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info); | |
2454 | ||
2455 | /* calculate tx gain adjustment based on power supply voltage */ | |
2456 | voltage = priv->eeprom.calib_info.voltage; | |
2457 | init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage); | |
2458 | voltage_compensation = | |
2459 | iwl4965_get_voltage_compensation(voltage, init_voltage); | |
2460 | ||
2461 | IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n", | |
2462 | init_voltage, | |
2463 | voltage, voltage_compensation); | |
2464 | ||
2465 | /* get current temperature (Celsius) */ | |
2466 | current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN); | |
2467 | current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX); | |
2468 | current_temp = KELVIN_TO_CELSIUS(current_temp); | |
2469 | ||
2470 | /* select thermal txpower adjustment params, based on channel group | |
2471 | * (same frequency group used for mimo txatten adjustment) */ | |
2472 | degrees_per_05db_num = | |
2473 | tx_power_cmp_tble[txatten_grp].degrees_per_05db_a; | |
2474 | degrees_per_05db_denom = | |
2475 | tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom; | |
2476 | ||
2477 | /* get per-chain txpower values from factory measurements */ | |
2478 | for (c = 0; c < 2; c++) { | |
2479 | measurement = &ch_eeprom_info.measurements[c][1]; | |
2480 | ||
2481 | /* txgain adjustment (in half-dB steps) based on difference | |
2482 | * between factory and current temperature */ | |
2483 | factory_temp = measurement->temperature; | |
2484 | iwl4965_math_div_round((current_temp - factory_temp) * | |
2485 | degrees_per_05db_denom, | |
2486 | degrees_per_05db_num, | |
2487 | &temperature_comp[c]); | |
2488 | ||
2489 | factory_gain_index[c] = measurement->gain_idx; | |
2490 | factory_actual_pwr[c] = measurement->actual_pow; | |
2491 | ||
2492 | IWL_DEBUG_TXPOWER("chain = %d\n", c); | |
2493 | IWL_DEBUG_TXPOWER("fctry tmp %d, " | |
2494 | "curr tmp %d, comp %d steps\n", | |
2495 | factory_temp, current_temp, | |
2496 | temperature_comp[c]); | |
2497 | ||
2498 | IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n", | |
2499 | factory_gain_index[c], | |
2500 | factory_actual_pwr[c]); | |
2501 | } | |
2502 | ||
2503 | /* for each of 33 bit-rates (including 1 for CCK) */ | |
2504 | for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) { | |
2505 | u8 is_mimo_rate; | |
bb8c093b | 2506 | union iwl4965_tx_power_dual_stream tx_power; |
b481de9c ZY |
2507 | |
2508 | /* for mimo, reduce each chain's txpower by half | |
2509 | * (3dB, 6 steps), so total output power is regulatory | |
2510 | * compliant. */ | |
2511 | if (i & 0x8) { | |
2512 | current_regulatory = reg_limit - | |
2513 | IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION; | |
2514 | is_mimo_rate = 1; | |
2515 | } else { | |
2516 | current_regulatory = reg_limit; | |
2517 | is_mimo_rate = 0; | |
2518 | } | |
2519 | ||
2520 | /* find txpower limit, either hardware or regulatory */ | |
2521 | power_limit = saturation_power - back_off_table[i]; | |
2522 | if (power_limit > current_regulatory) | |
2523 | power_limit = current_regulatory; | |
2524 | ||
2525 | /* reduce user's txpower request if necessary | |
2526 | * for this rate on this channel */ | |
2527 | target_power = user_target_power; | |
2528 | if (target_power > power_limit) | |
2529 | target_power = power_limit; | |
2530 | ||
2531 | IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n", | |
2532 | i, saturation_power - back_off_table[i], | |
2533 | current_regulatory, user_target_power, | |
2534 | target_power); | |
2535 | ||
2536 | /* for each of 2 Tx chains (radio transmitters) */ | |
2537 | for (c = 0; c < 2; c++) { | |
2538 | s32 atten_value; | |
2539 | ||
2540 | if (is_mimo_rate) | |
2541 | atten_value = | |
2542 | (s32)le32_to_cpu(priv->card_alive_init. | |
2543 | tx_atten[txatten_grp][c]); | |
2544 | else | |
2545 | atten_value = 0; | |
2546 | ||
2547 | /* calculate index; higher index means lower txpower */ | |
2548 | power_index = (u8) (factory_gain_index[c] - | |
2549 | (target_power - | |
2550 | factory_actual_pwr[c]) - | |
2551 | temperature_comp[c] - | |
2552 | voltage_compensation + | |
2553 | atten_value); | |
2554 | ||
2555 | /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n", | |
2556 | power_index); */ | |
2557 | ||
2558 | if (power_index < get_min_power_index(i, band)) | |
2559 | power_index = get_min_power_index(i, band); | |
2560 | ||
2561 | /* adjust 5 GHz index to support negative indexes */ | |
2562 | if (!band) | |
2563 | power_index += 9; | |
2564 | ||
2565 | /* CCK, rate 32, reduce txpower for CCK */ | |
2566 | if (i == POWER_TABLE_CCK_ENTRY) | |
2567 | power_index += | |
2568 | IWL_TX_POWER_CCK_COMPENSATION_C_STEP; | |
2569 | ||
2570 | /* stay within the table! */ | |
2571 | if (power_index > 107) { | |
2572 | IWL_WARNING("txpower index %d > 107\n", | |
2573 | power_index); | |
2574 | power_index = 107; | |
2575 | } | |
2576 | if (power_index < 0) { | |
2577 | IWL_WARNING("txpower index %d < 0\n", | |
2578 | power_index); | |
2579 | power_index = 0; | |
2580 | } | |
2581 | ||
2582 | /* fill txpower command for this rate/chain */ | |
2583 | tx_power.s.radio_tx_gain[c] = | |
2584 | gain_table[band][power_index].radio; | |
2585 | tx_power.s.dsp_predis_atten[c] = | |
2586 | gain_table[band][power_index].dsp; | |
2587 | ||
2588 | IWL_DEBUG_TXPOWER("chain %d mimo %d index %d " | |
2589 | "gain 0x%02x dsp %d\n", | |
2590 | c, atten_value, power_index, | |
2591 | tx_power.s.radio_tx_gain[c], | |
2592 | tx_power.s.dsp_predis_atten[c]); | |
2593 | }/* for each chain */ | |
2594 | ||
2595 | tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw); | |
2596 | ||
2597 | }/* for each rate */ | |
2598 | ||
2599 | return 0; | |
2600 | } | |
2601 | ||
2602 | /** | |
bb8c093b | 2603 | * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit |
b481de9c ZY |
2604 | * |
2605 | * Uses the active RXON for channel, band, and characteristics (fat, high) | |
2606 | * The power limit is taken from priv->user_txpower_limit. | |
2607 | */ | |
bb8c093b | 2608 | int iwl4965_hw_reg_send_txpower(struct iwl4965_priv *priv) |
b481de9c | 2609 | { |
bb8c093b | 2610 | struct iwl4965_txpowertable_cmd cmd = { 0 }; |
b481de9c ZY |
2611 | int rc = 0; |
2612 | u8 band = 0; | |
2613 | u8 is_fat = 0; | |
2614 | u8 ctrl_chan_high = 0; | |
2615 | ||
2616 | if (test_bit(STATUS_SCANNING, &priv->status)) { | |
2617 | /* If this gets hit a lot, switch it to a BUG() and catch | |
2618 | * the stack trace to find out who is calling this during | |
2619 | * a scan. */ | |
2620 | IWL_WARNING("TX Power requested while scanning!\n"); | |
2621 | return -EAGAIN; | |
2622 | } | |
2623 | ||
8318d78a | 2624 | band = priv->band == IEEE80211_BAND_2GHZ; |
b481de9c ZY |
2625 | |
2626 | is_fat = is_fat_channel(priv->active_rxon.flags); | |
2627 | ||
2628 | if (is_fat && | |
2629 | (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK)) | |
2630 | ctrl_chan_high = 1; | |
2631 | ||
2632 | cmd.band = band; | |
2633 | cmd.channel = priv->active_rxon.channel; | |
2634 | ||
2635 | rc = iwl4965_fill_txpower_tbl(priv, band, | |
2636 | le16_to_cpu(priv->active_rxon.channel), | |
2637 | is_fat, ctrl_chan_high, &cmd.tx_power); | |
2638 | if (rc) | |
2639 | return rc; | |
2640 | ||
bb8c093b | 2641 | rc = iwl4965_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd); |
b481de9c ZY |
2642 | return rc; |
2643 | } | |
2644 | ||
bb8c093b | 2645 | int iwl4965_hw_channel_switch(struct iwl4965_priv *priv, u16 channel) |
b481de9c ZY |
2646 | { |
2647 | int rc; | |
2648 | u8 band = 0; | |
2649 | u8 is_fat = 0; | |
2650 | u8 ctrl_chan_high = 0; | |
bb8c093b CH |
2651 | struct iwl4965_channel_switch_cmd cmd = { 0 }; |
2652 | const struct iwl4965_channel_info *ch_info; | |
b481de9c | 2653 | |
8318d78a | 2654 | band = priv->band == IEEE80211_BAND_2GHZ; |
b481de9c | 2655 | |
8318d78a | 2656 | ch_info = iwl4965_get_channel_info(priv, priv->band, channel); |
b481de9c ZY |
2657 | |
2658 | is_fat = is_fat_channel(priv->staging_rxon.flags); | |
2659 | ||
2660 | if (is_fat && | |
2661 | (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK)) | |
2662 | ctrl_chan_high = 1; | |
2663 | ||
2664 | cmd.band = band; | |
2665 | cmd.expect_beacon = 0; | |
2666 | cmd.channel = cpu_to_le16(channel); | |
2667 | cmd.rxon_flags = priv->active_rxon.flags; | |
2668 | cmd.rxon_filter_flags = priv->active_rxon.filter_flags; | |
2669 | cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time); | |
2670 | if (ch_info) | |
2671 | cmd.expect_beacon = is_channel_radar(ch_info); | |
2672 | else | |
2673 | cmd.expect_beacon = 1; | |
2674 | ||
2675 | rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat, | |
2676 | ctrl_chan_high, &cmd.tx_power); | |
2677 | if (rc) { | |
2678 | IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc); | |
2679 | return rc; | |
2680 | } | |
2681 | ||
bb8c093b | 2682 | rc = iwl4965_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd); |
b481de9c ZY |
2683 | return rc; |
2684 | } | |
2685 | ||
2686 | #define RTS_HCCA_RETRY_LIMIT 3 | |
2687 | #define RTS_DFAULT_RETRY_LIMIT 60 | |
2688 | ||
bb8c093b CH |
2689 | void iwl4965_hw_build_tx_cmd_rate(struct iwl4965_priv *priv, |
2690 | struct iwl4965_cmd *cmd, | |
b481de9c ZY |
2691 | struct ieee80211_tx_control *ctrl, |
2692 | struct ieee80211_hdr *hdr, int sta_id, | |
2693 | int is_hcca) | |
2694 | { | |
87e4f7df | 2695 | struct iwl4965_tx_cmd *tx = &cmd->cmd.tx; |
b481de9c ZY |
2696 | u8 rts_retry_limit = 0; |
2697 | u8 data_retry_limit = 0; | |
b481de9c | 2698 | u16 fc = le16_to_cpu(hdr->frame_control); |
87e4f7df TW |
2699 | u8 rate_plcp; |
2700 | u16 rate_flags = 0; | |
8318d78a | 2701 | int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1); |
b481de9c | 2702 | |
87e4f7df | 2703 | rate_plcp = iwl4965_rates[rate_idx].plcp; |
b481de9c ZY |
2704 | |
2705 | rts_retry_limit = (is_hcca) ? | |
2706 | RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT; | |
2707 | ||
87e4f7df TW |
2708 | if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE)) |
2709 | rate_flags |= RATE_MCS_CCK_MSK; | |
2710 | ||
2711 | ||
b481de9c ZY |
2712 | if (ieee80211_is_probe_response(fc)) { |
2713 | data_retry_limit = 3; | |
2714 | if (data_retry_limit < rts_retry_limit) | |
2715 | rts_retry_limit = data_retry_limit; | |
2716 | } else | |
2717 | data_retry_limit = IWL_DEFAULT_TX_RETRY; | |
2718 | ||
2719 | if (priv->data_retry_limit != -1) | |
2720 | data_retry_limit = priv->data_retry_limit; | |
2721 | ||
87e4f7df TW |
2722 | |
2723 | if (ieee80211_is_data(fc)) { | |
2724 | tx->initial_rate_index = 0; | |
2725 | tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; | |
2726 | } else { | |
b481de9c ZY |
2727 | switch (fc & IEEE80211_FCTL_STYPE) { |
2728 | case IEEE80211_STYPE_AUTH: | |
2729 | case IEEE80211_STYPE_DEAUTH: | |
2730 | case IEEE80211_STYPE_ASSOC_REQ: | |
2731 | case IEEE80211_STYPE_REASSOC_REQ: | |
87e4f7df TW |
2732 | if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) { |
2733 | tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK; | |
2734 | tx->tx_flags |= TX_CMD_FLG_CTS_MSK; | |
b481de9c ZY |
2735 | } |
2736 | break; | |
2737 | default: | |
2738 | break; | |
2739 | } | |
87e4f7df TW |
2740 | |
2741 | /* Alternate between antenna A and B for successive frames */ | |
2742 | if (priv->use_ant_b_for_management_frame) { | |
2743 | priv->use_ant_b_for_management_frame = 0; | |
2744 | rate_flags |= RATE_MCS_ANT_B_MSK; | |
2745 | } else { | |
2746 | priv->use_ant_b_for_management_frame = 1; | |
2747 | rate_flags |= RATE_MCS_ANT_A_MSK; | |
2748 | } | |
b481de9c ZY |
2749 | } |
2750 | ||
87e4f7df TW |
2751 | tx->rts_retry_limit = rts_retry_limit; |
2752 | tx->data_retry_limit = data_retry_limit; | |
2753 | tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags); | |
b481de9c ZY |
2754 | } |
2755 | ||
bb8c093b | 2756 | int iwl4965_hw_get_rx_read(struct iwl4965_priv *priv) |
b481de9c | 2757 | { |
bb8c093b | 2758 | struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt; |
b481de9c ZY |
2759 | |
2760 | return IWL_GET_BITS(*shared_data, rb_closed_stts_rb_num); | |
2761 | } | |
2762 | ||
bb8c093b | 2763 | int iwl4965_hw_get_temperature(struct iwl4965_priv *priv) |
b481de9c ZY |
2764 | { |
2765 | return priv->temperature; | |
2766 | } | |
2767 | ||
bb8c093b CH |
2768 | unsigned int iwl4965_hw_get_beacon_cmd(struct iwl4965_priv *priv, |
2769 | struct iwl4965_frame *frame, u8 rate) | |
b481de9c | 2770 | { |
bb8c093b | 2771 | struct iwl4965_tx_beacon_cmd *tx_beacon_cmd; |
b481de9c ZY |
2772 | unsigned int frame_size; |
2773 | ||
2774 | tx_beacon_cmd = &frame->u.beacon; | |
2775 | memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); | |
2776 | ||
2777 | tx_beacon_cmd->tx.sta_id = IWL4965_BROADCAST_ID; | |
2778 | tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; | |
2779 | ||
bb8c093b | 2780 | frame_size = iwl4965_fill_beacon_frame(priv, |
b481de9c | 2781 | tx_beacon_cmd->frame, |
bb8c093b | 2782 | iwl4965_broadcast_addr, |
b481de9c ZY |
2783 | sizeof(frame->u) - sizeof(*tx_beacon_cmd)); |
2784 | ||
2785 | BUG_ON(frame_size > MAX_MPDU_SIZE); | |
2786 | tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); | |
2787 | ||
2788 | if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP)) | |
2789 | tx_beacon_cmd->tx.rate_n_flags = | |
bb8c093b | 2790 | iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK); |
b481de9c ZY |
2791 | else |
2792 | tx_beacon_cmd->tx.rate_n_flags = | |
bb8c093b | 2793 | iwl4965_hw_set_rate_n_flags(rate, 0); |
b481de9c ZY |
2794 | |
2795 | tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK | | |
2796 | TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK); | |
2797 | return (sizeof(*tx_beacon_cmd) + frame_size); | |
2798 | } | |
2799 | ||
8b6eaea8 CB |
2800 | /* |
2801 | * Tell 4965 where to find circular buffer of Tx Frame Descriptors for | |
2802 | * given Tx queue, and enable the DMA channel used for that queue. | |
2803 | * | |
2804 | * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA | |
2805 | * channels supported in hardware. | |
2806 | */ | |
bb8c093b | 2807 | int iwl4965_hw_tx_queue_init(struct iwl4965_priv *priv, struct iwl4965_tx_queue *txq) |
b481de9c ZY |
2808 | { |
2809 | int rc; | |
2810 | unsigned long flags; | |
2811 | int txq_id = txq->q.id; | |
2812 | ||
2813 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 2814 | rc = iwl4965_grab_nic_access(priv); |
b481de9c ZY |
2815 | if (rc) { |
2816 | spin_unlock_irqrestore(&priv->lock, flags); | |
2817 | return rc; | |
2818 | } | |
2819 | ||
8b6eaea8 | 2820 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
bb8c093b | 2821 | iwl4965_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id), |
b481de9c | 2822 | txq->q.dma_addr >> 8); |
8b6eaea8 CB |
2823 | |
2824 | /* Enable DMA channel, using same id as for TFD queue */ | |
bb8c093b | 2825 | iwl4965_write_direct32( |
b481de9c ZY |
2826 | priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), |
2827 | IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
2828 | IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL); | |
bb8c093b | 2829 | iwl4965_release_nic_access(priv); |
b481de9c ZY |
2830 | spin_unlock_irqrestore(&priv->lock, flags); |
2831 | ||
2832 | return 0; | |
2833 | } | |
2834 | ||
bb8c093b | 2835 | int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl4965_priv *priv, void *ptr, |
b481de9c ZY |
2836 | dma_addr_t addr, u16 len) |
2837 | { | |
2838 | int index, is_odd; | |
bb8c093b | 2839 | struct iwl4965_tfd_frame *tfd = ptr; |
b481de9c ZY |
2840 | u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs); |
2841 | ||
8b6eaea8 | 2842 | /* Each TFD can point to a maximum 20 Tx buffers */ |
b481de9c ZY |
2843 | if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) { |
2844 | IWL_ERROR("Error can not send more than %d chunks\n", | |
2845 | MAX_NUM_OF_TBS); | |
2846 | return -EINVAL; | |
2847 | } | |
2848 | ||
2849 | index = num_tbs / 2; | |
2850 | is_odd = num_tbs & 0x1; | |
2851 | ||
2852 | if (!is_odd) { | |
2853 | tfd->pa[index].tb1_addr = cpu_to_le32(addr); | |
2854 | IWL_SET_BITS(tfd->pa[index], tb1_addr_hi, | |
6a218f6f | 2855 | iwl_get_dma_hi_address(addr)); |
b481de9c ZY |
2856 | IWL_SET_BITS(tfd->pa[index], tb1_len, len); |
2857 | } else { | |
2858 | IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16, | |
2859 | (u32) (addr & 0xffff)); | |
2860 | IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16); | |
2861 | IWL_SET_BITS(tfd->pa[index], tb2_len, len); | |
2862 | } | |
2863 | ||
2864 | IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1); | |
2865 | ||
2866 | return 0; | |
2867 | } | |
2868 | ||
bb8c093b | 2869 | static void iwl4965_hw_card_show_info(struct iwl4965_priv *priv) |
b481de9c ZY |
2870 | { |
2871 | u16 hw_version = priv->eeprom.board_revision_4965; | |
2872 | ||
2873 | IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n", | |
2874 | ((hw_version >> 8) & 0x0F), | |
2875 | ((hw_version >> 8) >> 4), (hw_version & 0x00FF)); | |
2876 | ||
2877 | IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n", | |
2878 | priv->eeprom.board_pba_number_4965); | |
2879 | } | |
2880 | ||
2881 | #define IWL_TX_CRC_SIZE 4 | |
2882 | #define IWL_TX_DELIMITER_SIZE 4 | |
2883 | ||
8b6eaea8 CB |
2884 | /** |
2885 | * iwl4965_tx_queue_update_wr_ptr - Set up entry in Tx byte-count array | |
2886 | */ | |
bb8c093b CH |
2887 | int iwl4965_tx_queue_update_wr_ptr(struct iwl4965_priv *priv, |
2888 | struct iwl4965_tx_queue *txq, u16 byte_cnt) | |
b481de9c ZY |
2889 | { |
2890 | int len; | |
2891 | int txq_id = txq->q.id; | |
bb8c093b | 2892 | struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt; |
b481de9c ZY |
2893 | |
2894 | if (txq->need_update == 0) | |
2895 | return 0; | |
2896 | ||
2897 | len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
2898 | ||
8b6eaea8 | 2899 | /* Set up byte count within first 256 entries */ |
b481de9c | 2900 | IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. |
fc4b6853 | 2901 | tfd_offset[txq->q.write_ptr], byte_cnt, len); |
b481de9c | 2902 | |
8b6eaea8 | 2903 | /* If within first 64 entries, duplicate at end */ |
fc4b6853 | 2904 | if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE) |
b481de9c | 2905 | IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. |
fc4b6853 | 2906 | tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr], |
b481de9c ZY |
2907 | byte_cnt, len); |
2908 | ||
2909 | return 0; | |
2910 | } | |
2911 | ||
8b6eaea8 CB |
2912 | /** |
2913 | * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image | |
2914 | * | |
2915 | * Selects how many and which Rx receivers/antennas/chains to use. | |
2916 | * This should not be used for scan command ... it puts data in wrong place. | |
2917 | */ | |
bb8c093b | 2918 | void iwl4965_set_rxon_chain(struct iwl4965_priv *priv) |
b481de9c ZY |
2919 | { |
2920 | u8 is_single = is_single_stream(priv); | |
2921 | u8 idle_state, rx_state; | |
2922 | ||
2923 | priv->staging_rxon.rx_chain = 0; | |
2924 | rx_state = idle_state = 3; | |
2925 | ||
2926 | /* Tell uCode which antennas are actually connected. | |
2927 | * Before first association, we assume all antennas are connected. | |
2928 | * Just after first association, iwl4965_noise_calibration() | |
2929 | * checks which antennas actually *are* connected. */ | |
2930 | priv->staging_rxon.rx_chain |= | |
2931 | cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS); | |
2932 | ||
2933 | /* How many receivers should we use? */ | |
2934 | iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state); | |
2935 | priv->staging_rxon.rx_chain |= | |
2936 | cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS); | |
2937 | priv->staging_rxon.rx_chain |= | |
2938 | cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS); | |
2939 | ||
2940 | if (!is_single && (rx_state >= 2) && | |
2941 | !test_bit(STATUS_POWER_PMI, &priv->status)) | |
2942 | priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK; | |
2943 | else | |
2944 | priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK; | |
2945 | ||
2946 | IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain); | |
2947 | } | |
2948 | ||
b481de9c ZY |
2949 | /** |
2950 | * sign_extend - Sign extend a value using specified bit as sign-bit | |
2951 | * | |
2952 | * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1 | |
2953 | * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7. | |
2954 | * | |
2955 | * @param oper value to sign extend | |
2956 | * @param index 0 based bit index (0<=index<32) to sign bit | |
2957 | */ | |
2958 | static s32 sign_extend(u32 oper, int index) | |
2959 | { | |
2960 | u8 shift = 31 - index; | |
2961 | ||
2962 | return (s32)(oper << shift) >> shift; | |
2963 | } | |
2964 | ||
2965 | /** | |
2966 | * iwl4965_get_temperature - return the calibrated temperature (in Kelvin) | |
2967 | * @statistics: Provides the temperature reading from the uCode | |
2968 | * | |
2969 | * A return of <0 indicates bogus data in the statistics | |
2970 | */ | |
bb8c093b | 2971 | int iwl4965_get_temperature(const struct iwl4965_priv *priv) |
b481de9c ZY |
2972 | { |
2973 | s32 temperature; | |
2974 | s32 vt; | |
2975 | s32 R1, R2, R3; | |
2976 | u32 R4; | |
2977 | ||
2978 | if (test_bit(STATUS_TEMPERATURE, &priv->status) && | |
2979 | (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) { | |
2980 | IWL_DEBUG_TEMP("Running FAT temperature calibration\n"); | |
2981 | R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]); | |
2982 | R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]); | |
2983 | R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]); | |
2984 | R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]); | |
2985 | } else { | |
2986 | IWL_DEBUG_TEMP("Running temperature calibration\n"); | |
2987 | R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]); | |
2988 | R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]); | |
2989 | R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]); | |
2990 | R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]); | |
2991 | } | |
2992 | ||
2993 | /* | |
8b6eaea8 | 2994 | * Temperature is only 23 bits, so sign extend out to 32. |
b481de9c ZY |
2995 | * |
2996 | * NOTE If we haven't received a statistics notification yet | |
2997 | * with an updated temperature, use R4 provided to us in the | |
8b6eaea8 CB |
2998 | * "initialize" ALIVE response. |
2999 | */ | |
b481de9c ZY |
3000 | if (!test_bit(STATUS_TEMPERATURE, &priv->status)) |
3001 | vt = sign_extend(R4, 23); | |
3002 | else | |
3003 | vt = sign_extend( | |
3004 | le32_to_cpu(priv->statistics.general.temperature), 23); | |
3005 | ||
3006 | IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n", | |
3007 | R1, R2, R3, vt); | |
3008 | ||
3009 | if (R3 == R1) { | |
3010 | IWL_ERROR("Calibration conflict R1 == R3\n"); | |
3011 | return -1; | |
3012 | } | |
3013 | ||
3014 | /* Calculate temperature in degrees Kelvin, adjust by 97%. | |
3015 | * Add offset to center the adjustment around 0 degrees Centigrade. */ | |
3016 | temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2); | |
3017 | temperature /= (R3 - R1); | |
3018 | temperature = (temperature * 97) / 100 + | |
3019 | TEMPERATURE_CALIB_KELVIN_OFFSET; | |
3020 | ||
3021 | IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature, | |
3022 | KELVIN_TO_CELSIUS(temperature)); | |
3023 | ||
3024 | return temperature; | |
3025 | } | |
3026 | ||
3027 | /* Adjust Txpower only if temperature variance is greater than threshold. */ | |
3028 | #define IWL_TEMPERATURE_THRESHOLD 3 | |
3029 | ||
3030 | /** | |
3031 | * iwl4965_is_temp_calib_needed - determines if new calibration is needed | |
3032 | * | |
3033 | * If the temperature changed has changed sufficiently, then a recalibration | |
3034 | * is needed. | |
3035 | * | |
3036 | * Assumes caller will replace priv->last_temperature once calibration | |
3037 | * executed. | |
3038 | */ | |
bb8c093b | 3039 | static int iwl4965_is_temp_calib_needed(struct iwl4965_priv *priv) |
b481de9c ZY |
3040 | { |
3041 | int temp_diff; | |
3042 | ||
3043 | if (!test_bit(STATUS_STATISTICS, &priv->status)) { | |
3044 | IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n"); | |
3045 | return 0; | |
3046 | } | |
3047 | ||
3048 | temp_diff = priv->temperature - priv->last_temperature; | |
3049 | ||
3050 | /* get absolute value */ | |
3051 | if (temp_diff < 0) { | |
3052 | IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff); | |
3053 | temp_diff = -temp_diff; | |
3054 | } else if (temp_diff == 0) | |
3055 | IWL_DEBUG_POWER("Same temp, \n"); | |
3056 | else | |
3057 | IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff); | |
3058 | ||
3059 | if (temp_diff < IWL_TEMPERATURE_THRESHOLD) { | |
3060 | IWL_DEBUG_POWER("Thermal txpower calib not needed\n"); | |
3061 | return 0; | |
3062 | } | |
3063 | ||
3064 | IWL_DEBUG_POWER("Thermal txpower calib needed\n"); | |
3065 | ||
3066 | return 1; | |
3067 | } | |
3068 | ||
3069 | /* Calculate noise level, based on measurements during network silence just | |
3070 | * before arriving beacon. This measurement can be done only if we know | |
3071 | * exactly when to expect beacons, therefore only when we're associated. */ | |
bb8c093b | 3072 | static void iwl4965_rx_calc_noise(struct iwl4965_priv *priv) |
b481de9c ZY |
3073 | { |
3074 | struct statistics_rx_non_phy *rx_info | |
3075 | = &(priv->statistics.rx.general); | |
3076 | int num_active_rx = 0; | |
3077 | int total_silence = 0; | |
3078 | int bcn_silence_a = | |
3079 | le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER; | |
3080 | int bcn_silence_b = | |
3081 | le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER; | |
3082 | int bcn_silence_c = | |
3083 | le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER; | |
3084 | ||
3085 | if (bcn_silence_a) { | |
3086 | total_silence += bcn_silence_a; | |
3087 | num_active_rx++; | |
3088 | } | |
3089 | if (bcn_silence_b) { | |
3090 | total_silence += bcn_silence_b; | |
3091 | num_active_rx++; | |
3092 | } | |
3093 | if (bcn_silence_c) { | |
3094 | total_silence += bcn_silence_c; | |
3095 | num_active_rx++; | |
3096 | } | |
3097 | ||
3098 | /* Average among active antennas */ | |
3099 | if (num_active_rx) | |
3100 | priv->last_rx_noise = (total_silence / num_active_rx) - 107; | |
3101 | else | |
3102 | priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
3103 | ||
3104 | IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", | |
3105 | bcn_silence_a, bcn_silence_b, bcn_silence_c, | |
3106 | priv->last_rx_noise); | |
3107 | } | |
3108 | ||
bb8c093b | 3109 | void iwl4965_hw_rx_statistics(struct iwl4965_priv *priv, struct iwl4965_rx_mem_buffer *rxb) |
b481de9c | 3110 | { |
bb8c093b | 3111 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3112 | int change; |
3113 | s32 temp; | |
3114 | ||
3115 | IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n", | |
3116 | (int)sizeof(priv->statistics), pkt->len); | |
3117 | ||
3118 | change = ((priv->statistics.general.temperature != | |
3119 | pkt->u.stats.general.temperature) || | |
3120 | ((priv->statistics.flag & | |
3121 | STATISTICS_REPLY_FLG_FAT_MODE_MSK) != | |
3122 | (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK))); | |
3123 | ||
3124 | memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics)); | |
3125 | ||
3126 | set_bit(STATUS_STATISTICS, &priv->status); | |
3127 | ||
3128 | /* Reschedule the statistics timer to occur in | |
3129 | * REG_RECALIB_PERIOD seconds to ensure we get a | |
3130 | * thermal update even if the uCode doesn't give | |
3131 | * us one */ | |
3132 | mod_timer(&priv->statistics_periodic, jiffies + | |
3133 | msecs_to_jiffies(REG_RECALIB_PERIOD * 1000)); | |
3134 | ||
3135 | if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) && | |
3136 | (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) { | |
3137 | iwl4965_rx_calc_noise(priv); | |
c8b0e6e1 | 3138 | #ifdef CONFIG_IWL4965_SENSITIVITY |
b481de9c ZY |
3139 | queue_work(priv->workqueue, &priv->sensitivity_work); |
3140 | #endif | |
3141 | } | |
3142 | ||
3143 | /* If the hardware hasn't reported a change in | |
3144 | * temperature then don't bother computing a | |
3145 | * calibrated temperature value */ | |
3146 | if (!change) | |
3147 | return; | |
3148 | ||
3149 | temp = iwl4965_get_temperature(priv); | |
3150 | if (temp < 0) | |
3151 | return; | |
3152 | ||
3153 | if (priv->temperature != temp) { | |
3154 | if (priv->temperature) | |
3155 | IWL_DEBUG_TEMP("Temperature changed " | |
3156 | "from %dC to %dC\n", | |
3157 | KELVIN_TO_CELSIUS(priv->temperature), | |
3158 | KELVIN_TO_CELSIUS(temp)); | |
3159 | else | |
3160 | IWL_DEBUG_TEMP("Temperature " | |
3161 | "initialized to %dC\n", | |
3162 | KELVIN_TO_CELSIUS(temp)); | |
3163 | } | |
3164 | ||
3165 | priv->temperature = temp; | |
3166 | set_bit(STATUS_TEMPERATURE, &priv->status); | |
3167 | ||
3168 | if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) && | |
3169 | iwl4965_is_temp_calib_needed(priv)) | |
3170 | queue_work(priv->workqueue, &priv->txpower_work); | |
3171 | } | |
3172 | ||
12342c47 ZY |
3173 | static void iwl4965_add_radiotap(struct iwl4965_priv *priv, |
3174 | struct sk_buff *skb, | |
3175 | struct iwl4965_rx_phy_res *rx_start, | |
3176 | struct ieee80211_rx_status *stats, | |
3177 | u32 ampdu_status) | |
3178 | { | |
3179 | s8 signal = stats->ssi; | |
3180 | s8 noise = 0; | |
8318d78a | 3181 | int rate = stats->rate_idx; |
12342c47 ZY |
3182 | u64 tsf = stats->mactime; |
3183 | __le16 phy_flags_hw = rx_start->phy_flags; | |
3184 | struct iwl4965_rt_rx_hdr { | |
3185 | struct ieee80211_radiotap_header rt_hdr; | |
3186 | __le64 rt_tsf; /* TSF */ | |
3187 | u8 rt_flags; /* radiotap packet flags */ | |
3188 | u8 rt_rate; /* rate in 500kb/s */ | |
3189 | __le16 rt_channelMHz; /* channel in MHz */ | |
3190 | __le16 rt_chbitmask; /* channel bitfield */ | |
3191 | s8 rt_dbmsignal; /* signal in dBm, kluged to signed */ | |
3192 | s8 rt_dbmnoise; | |
3193 | u8 rt_antenna; /* antenna number */ | |
3194 | } __attribute__ ((packed)) *iwl4965_rt; | |
3195 | ||
3196 | /* TODO: We won't have enough headroom for HT frames. Fix it later. */ | |
3197 | if (skb_headroom(skb) < sizeof(*iwl4965_rt)) { | |
3198 | if (net_ratelimit()) | |
3199 | printk(KERN_ERR "not enough headroom [%d] for " | |
01c20986 | 3200 | "radiotap head [%zd]\n", |
12342c47 ZY |
3201 | skb_headroom(skb), sizeof(*iwl4965_rt)); |
3202 | return; | |
3203 | } | |
3204 | ||
3205 | /* put radiotap header in front of 802.11 header and data */ | |
3206 | iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt)); | |
3207 | ||
3208 | /* initialise radiotap header */ | |
3209 | iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION; | |
3210 | iwl4965_rt->rt_hdr.it_pad = 0; | |
3211 | ||
3212 | /* total header + data */ | |
3213 | put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)), | |
3214 | &iwl4965_rt->rt_hdr.it_len); | |
3215 | ||
3216 | /* Indicate all the fields we add to the radiotap header */ | |
3217 | put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) | | |
3218 | (1 << IEEE80211_RADIOTAP_FLAGS) | | |
3219 | (1 << IEEE80211_RADIOTAP_RATE) | | |
3220 | (1 << IEEE80211_RADIOTAP_CHANNEL) | | |
3221 | (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | | |
3222 | (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | | |
3223 | (1 << IEEE80211_RADIOTAP_ANTENNA)), | |
3224 | &iwl4965_rt->rt_hdr.it_present); | |
3225 | ||
3226 | /* Zero the flags, we'll add to them as we go */ | |
3227 | iwl4965_rt->rt_flags = 0; | |
3228 | ||
3229 | put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf); | |
3230 | ||
3231 | iwl4965_rt->rt_dbmsignal = signal; | |
3232 | iwl4965_rt->rt_dbmnoise = noise; | |
3233 | ||
3234 | /* Convert the channel frequency and set the flags */ | |
3235 | put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz); | |
3236 | if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK)) | |
3237 | put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM | | |
3238 | IEEE80211_CHAN_5GHZ), | |
3239 | &iwl4965_rt->rt_chbitmask); | |
3240 | else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK) | |
3241 | put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK | | |
3242 | IEEE80211_CHAN_2GHZ), | |
3243 | &iwl4965_rt->rt_chbitmask); | |
3244 | else /* 802.11g */ | |
3245 | put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM | | |
3246 | IEEE80211_CHAN_2GHZ), | |
3247 | &iwl4965_rt->rt_chbitmask); | |
3248 | ||
12342c47 ZY |
3249 | if (rate == -1) |
3250 | iwl4965_rt->rt_rate = 0; | |
3251 | else | |
3252 | iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee; | |
3253 | ||
3254 | /* | |
3255 | * "antenna number" | |
3256 | * | |
3257 | * It seems that the antenna field in the phy flags value | |
3258 | * is actually a bitfield. This is undefined by radiotap, | |
3259 | * it wants an actual antenna number but I always get "7" | |
3260 | * for most legacy frames I receive indicating that the | |
3261 | * same frame was received on all three RX chains. | |
3262 | * | |
3263 | * I think this field should be removed in favour of a | |
3264 | * new 802.11n radiotap field "RX chains" that is defined | |
3265 | * as a bitmask. | |
3266 | */ | |
3267 | iwl4965_rt->rt_antenna = | |
3268 | le16_to_cpu(phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4; | |
3269 | ||
3270 | /* set the preamble flag if appropriate */ | |
3271 | if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK) | |
3272 | iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; | |
3273 | ||
3274 | stats->flag |= RX_FLAG_RADIOTAP; | |
3275 | } | |
3276 | ||
bb8c093b | 3277 | static void iwl4965_handle_data_packet(struct iwl4965_priv *priv, int is_data, |
b481de9c | 3278 | int include_phy, |
bb8c093b | 3279 | struct iwl4965_rx_mem_buffer *rxb, |
b481de9c ZY |
3280 | struct ieee80211_rx_status *stats) |
3281 | { | |
bb8c093b | 3282 | struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data; |
b481de9c ZY |
3283 | struct iwl4965_rx_phy_res *rx_start = (include_phy) ? |
3284 | (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL; | |
3285 | struct ieee80211_hdr *hdr; | |
3286 | u16 len; | |
3287 | __le32 *rx_end; | |
3288 | unsigned int skblen; | |
3289 | u32 ampdu_status; | |
3290 | ||
3291 | if (!include_phy && priv->last_phy_res[0]) | |
3292 | rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1]; | |
3293 | ||
3294 | if (!rx_start) { | |
3295 | IWL_ERROR("MPDU frame without a PHY data\n"); | |
3296 | return; | |
3297 | } | |
3298 | if (include_phy) { | |
3299 | hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] + | |
3300 | rx_start->cfg_phy_cnt); | |
3301 | ||
3302 | len = le16_to_cpu(rx_start->byte_count); | |
3303 | ||
3304 | rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] + | |
3305 | sizeof(struct iwl4965_rx_phy_res) + | |
3306 | rx_start->cfg_phy_cnt + len); | |
3307 | ||
3308 | } else { | |
3309 | struct iwl4965_rx_mpdu_res_start *amsdu = | |
3310 | (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw; | |
3311 | ||
3312 | hdr = (struct ieee80211_hdr *)(pkt->u.raw + | |
3313 | sizeof(struct iwl4965_rx_mpdu_res_start)); | |
3314 | len = le16_to_cpu(amsdu->byte_count); | |
3315 | rx_start->byte_count = amsdu->byte_count; | |
3316 | rx_end = (__le32 *) (((u8 *) hdr) + len); | |
3317 | } | |
9ee1ba47 | 3318 | if (len > priv->hw_setting.max_pkt_size || len < 16) { |
12342c47 | 3319 | IWL_WARNING("byte count out of range [16,4K] : %d\n", len); |
b481de9c ZY |
3320 | return; |
3321 | } | |
3322 | ||
3323 | ampdu_status = le32_to_cpu(*rx_end); | |
3324 | skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32); | |
3325 | ||
3326 | /* start from MAC */ | |
3327 | skb_reserve(rxb->skb, (void *)hdr - (void *)pkt); | |
3328 | skb_put(rxb->skb, len); /* end where data ends */ | |
3329 | ||
3330 | /* We only process data packets if the interface is open */ | |
3331 | if (unlikely(!priv->is_open)) { | |
3332 | IWL_DEBUG_DROP_LIMIT | |
3333 | ("Dropping packet while interface is not open.\n"); | |
3334 | return; | |
3335 | } | |
3336 | ||
b481de9c ZY |
3337 | stats->flag = 0; |
3338 | hdr = (struct ieee80211_hdr *)rxb->skb->data; | |
3339 | ||
bb8c093b CH |
3340 | if (iwl4965_param_hwcrypto) |
3341 | iwl4965_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats); | |
b481de9c | 3342 | |
12342c47 ZY |
3343 | if (priv->add_radiotap) |
3344 | iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status); | |
3345 | ||
b481de9c ZY |
3346 | ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats); |
3347 | priv->alloc_rxb_skb--; | |
3348 | rxb->skb = NULL; | |
3349 | #ifdef LED | |
3350 | priv->led_packets += len; | |
bb8c093b | 3351 | iwl4965_setup_activity_timer(priv); |
b481de9c ZY |
3352 | #endif |
3353 | } | |
3354 | ||
3355 | /* Calc max signal level (dBm) among 3 possible receivers */ | |
3356 | static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp) | |
3357 | { | |
3358 | /* data from PHY/DSP regarding signal strength, etc., | |
3359 | * contents are always there, not configurable by host. */ | |
3360 | struct iwl4965_rx_non_cfg_phy *ncphy = | |
3361 | (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy; | |
3362 | u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK) | |
3363 | >> IWL_AGC_DB_POS; | |
3364 | ||
3365 | u32 valid_antennae = | |
3366 | (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK) | |
3367 | >> RX_PHY_FLAGS_ANTENNAE_OFFSET; | |
3368 | u8 max_rssi = 0; | |
3369 | u32 i; | |
3370 | ||
3371 | /* Find max rssi among 3 possible receivers. | |
3372 | * These values are measured by the digital signal processor (DSP). | |
3373 | * They should stay fairly constant even as the signal strength varies, | |
3374 | * if the radio's automatic gain control (AGC) is working right. | |
3375 | * AGC value (see below) will provide the "interesting" info. */ | |
3376 | for (i = 0; i < 3; i++) | |
3377 | if (valid_antennae & (1 << i)) | |
3378 | max_rssi = max(ncphy->rssi_info[i << 1], max_rssi); | |
3379 | ||
3380 | IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", | |
3381 | ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4], | |
3382 | max_rssi, agc); | |
3383 | ||
3384 | /* dBm = max_rssi dB - agc dB - constant. | |
3385 | * Higher AGC (higher radio gain) means lower signal. */ | |
3386 | return (max_rssi - agc - IWL_RSSI_OFFSET); | |
3387 | } | |
3388 | ||
c8b0e6e1 | 3389 | #ifdef CONFIG_IWL4965_HT |
b481de9c ZY |
3390 | |
3391 | /* Parsed Information Elements */ | |
3392 | struct ieee802_11_elems { | |
3393 | u8 *ds_params; | |
3394 | u8 ds_params_len; | |
3395 | u8 *tim; | |
3396 | u8 tim_len; | |
3397 | u8 *ibss_params; | |
3398 | u8 ibss_params_len; | |
3399 | u8 *erp_info; | |
3400 | u8 erp_info_len; | |
3401 | u8 *ht_cap_param; | |
3402 | u8 ht_cap_param_len; | |
3403 | u8 *ht_extra_param; | |
3404 | u8 ht_extra_param_len; | |
3405 | }; | |
3406 | ||
3407 | static int parse_elems(u8 *start, size_t len, struct ieee802_11_elems *elems) | |
3408 | { | |
3409 | size_t left = len; | |
3410 | u8 *pos = start; | |
3411 | int unknown = 0; | |
3412 | ||
3413 | memset(elems, 0, sizeof(*elems)); | |
3414 | ||
3415 | while (left >= 2) { | |
3416 | u8 id, elen; | |
3417 | ||
3418 | id = *pos++; | |
3419 | elen = *pos++; | |
3420 | left -= 2; | |
3421 | ||
3422 | if (elen > left) | |
3423 | return -1; | |
3424 | ||
3425 | switch (id) { | |
3426 | case WLAN_EID_DS_PARAMS: | |
3427 | elems->ds_params = pos; | |
3428 | elems->ds_params_len = elen; | |
3429 | break; | |
3430 | case WLAN_EID_TIM: | |
3431 | elems->tim = pos; | |
3432 | elems->tim_len = elen; | |
3433 | break; | |
3434 | case WLAN_EID_IBSS_PARAMS: | |
3435 | elems->ibss_params = pos; | |
3436 | elems->ibss_params_len = elen; | |
3437 | break; | |
3438 | case WLAN_EID_ERP_INFO: | |
3439 | elems->erp_info = pos; | |
3440 | elems->erp_info_len = elen; | |
3441 | break; | |
3442 | case WLAN_EID_HT_CAPABILITY: | |
3443 | elems->ht_cap_param = pos; | |
3444 | elems->ht_cap_param_len = elen; | |
3445 | break; | |
3446 | case WLAN_EID_HT_EXTRA_INFO: | |
3447 | elems->ht_extra_param = pos; | |
3448 | elems->ht_extra_param_len = elen; | |
3449 | break; | |
3450 | default: | |
3451 | unknown++; | |
3452 | break; | |
3453 | } | |
3454 | ||
3455 | left -= elen; | |
3456 | pos += elen; | |
3457 | } | |
3458 | ||
3459 | return 0; | |
3460 | } | |
326eeee8 RR |
3461 | |
3462 | void iwl4965_init_ht_hw_capab(struct ieee80211_ht_info *ht_info, int mode) | |
3463 | { | |
3464 | ht_info->cap = 0; | |
3465 | memset(ht_info->supp_mcs_set, 0, 16); | |
3466 | ||
3467 | ht_info->ht_supported = 1; | |
3468 | ||
3469 | if (mode == MODE_IEEE80211A) { | |
3470 | ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH; | |
3471 | ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40; | |
3472 | ht_info->supp_mcs_set[4] = 0x01; | |
3473 | } | |
3474 | ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD; | |
3475 | ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20; | |
3476 | ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS & | |
3477 | (IWL_MIMO_PS_NONE << 2)); | |
9ee1ba47 RR |
3478 | if (iwl4965_param_amsdu_size_8K) { |
3479 | printk(KERN_DEBUG "iwl4965 in A-MSDU 8K support mode\n"); | |
3480 | ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU; | |
3481 | } | |
326eeee8 RR |
3482 | |
3483 | ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF; | |
3484 | ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF; | |
3485 | ||
3486 | ht_info->supp_mcs_set[0] = 0xFF; | |
3487 | ht_info->supp_mcs_set[1] = 0xFF; | |
3488 | } | |
c8b0e6e1 | 3489 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c | 3490 | |
bb8c093b | 3491 | static void iwl4965_sta_modify_ps_wake(struct iwl4965_priv *priv, int sta_id) |
b481de9c ZY |
3492 | { |
3493 | unsigned long flags; | |
3494 | ||
3495 | spin_lock_irqsave(&priv->sta_lock, flags); | |
3496 | priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK; | |
3497 | priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK; | |
3498 | priv->stations[sta_id].sta.sta.modify_mask = 0; | |
3499 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
3500 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
3501 | ||
bb8c093b | 3502 | iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC); |
b481de9c ZY |
3503 | } |
3504 | ||
bb8c093b | 3505 | static void iwl4965_update_ps_mode(struct iwl4965_priv *priv, u16 ps_bit, u8 *addr) |
b481de9c ZY |
3506 | { |
3507 | /* FIXME: need locking over ps_status ??? */ | |
bb8c093b | 3508 | u8 sta_id = iwl4965_hw_find_station(priv, addr); |
b481de9c ZY |
3509 | |
3510 | if (sta_id != IWL_INVALID_STATION) { | |
3511 | u8 sta_awake = priv->stations[sta_id]. | |
3512 | ps_status == STA_PS_STATUS_WAKE; | |
3513 | ||
3514 | if (sta_awake && ps_bit) | |
3515 | priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP; | |
3516 | else if (!sta_awake && !ps_bit) { | |
3517 | iwl4965_sta_modify_ps_wake(priv, sta_id); | |
3518 | priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE; | |
3519 | } | |
3520 | } | |
3521 | } | |
3522 | ||
7878a5a4 MA |
3523 | #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) |
3524 | ||
b481de9c ZY |
3525 | /* Called for REPLY_4965_RX (legacy ABG frames), or |
3526 | * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */ | |
bb8c093b CH |
3527 | static void iwl4965_rx_reply_rx(struct iwl4965_priv *priv, |
3528 | struct iwl4965_rx_mem_buffer *rxb) | |
b481de9c | 3529 | { |
bb8c093b | 3530 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3531 | /* Use phy data (Rx signal strength, etc.) contained within |
3532 | * this rx packet for legacy frames, | |
3533 | * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */ | |
3534 | int include_phy = (pkt->hdr.cmd == REPLY_4965_RX); | |
3535 | struct iwl4965_rx_phy_res *rx_start = (include_phy) ? | |
3536 | (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : | |
3537 | (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1]; | |
3538 | __le32 *rx_end; | |
3539 | unsigned int len = 0; | |
3540 | struct ieee80211_hdr *header; | |
3541 | u16 fc; | |
3542 | struct ieee80211_rx_status stats = { | |
3543 | .mactime = le64_to_cpu(rx_start->timestamp), | |
8318d78a JB |
3544 | .freq = ieee80211chan2mhz(le16_to_cpu(rx_start->channel)), |
3545 | .band = | |
b481de9c | 3546 | (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? |
8318d78a | 3547 | IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ, |
b481de9c | 3548 | .antenna = 0, |
8318d78a JB |
3549 | .rate_idx = iwl4965_hw_get_rate( |
3550 | le32_to_cpu(rx_start->rate_n_flags)), | |
b481de9c | 3551 | .flag = 0, |
b481de9c ZY |
3552 | }; |
3553 | u8 network_packet; | |
3554 | ||
3555 | if ((unlikely(rx_start->cfg_phy_cnt > 20))) { | |
3556 | IWL_DEBUG_DROP | |
3557 | ("dsp size out of range [0,20]: " | |
3558 | "%d/n", rx_start->cfg_phy_cnt); | |
3559 | return; | |
3560 | } | |
3561 | if (!include_phy) { | |
3562 | if (priv->last_phy_res[0]) | |
3563 | rx_start = (struct iwl4965_rx_phy_res *) | |
3564 | &priv->last_phy_res[1]; | |
3565 | else | |
3566 | rx_start = NULL; | |
3567 | } | |
3568 | ||
3569 | if (!rx_start) { | |
3570 | IWL_ERROR("MPDU frame without a PHY data\n"); | |
3571 | return; | |
3572 | } | |
3573 | ||
3574 | if (include_phy) { | |
3575 | header = (struct ieee80211_hdr *)((u8 *) & rx_start[1] | |
3576 | + rx_start->cfg_phy_cnt); | |
3577 | ||
3578 | len = le16_to_cpu(rx_start->byte_count); | |
3579 | rx_end = (__le32 *) (pkt->u.raw + rx_start->cfg_phy_cnt + | |
3580 | sizeof(struct iwl4965_rx_phy_res) + len); | |
3581 | } else { | |
3582 | struct iwl4965_rx_mpdu_res_start *amsdu = | |
3583 | (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw; | |
3584 | ||
3585 | header = (void *)(pkt->u.raw + | |
3586 | sizeof(struct iwl4965_rx_mpdu_res_start)); | |
3587 | len = le16_to_cpu(amsdu->byte_count); | |
3588 | rx_end = (__le32 *) (pkt->u.raw + | |
3589 | sizeof(struct iwl4965_rx_mpdu_res_start) + len); | |
3590 | } | |
3591 | ||
3592 | if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) || | |
3593 | !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) { | |
3594 | IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", | |
3595 | le32_to_cpu(*rx_end)); | |
3596 | return; | |
3597 | } | |
3598 | ||
3599 | priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp); | |
3600 | ||
b481de9c ZY |
3601 | /* Find max signal strength (dBm) among 3 antenna/receiver chains */ |
3602 | stats.ssi = iwl4965_calc_rssi(rx_start); | |
3603 | ||
3604 | /* Meaningful noise values are available only from beacon statistics, | |
3605 | * which are gathered only when associated, and indicate noise | |
3606 | * only for the associated network channel ... | |
3607 | * Ignore these noise values while scanning (other channels) */ | |
bb8c093b | 3608 | if (iwl4965_is_associated(priv) && |
b481de9c ZY |
3609 | !test_bit(STATUS_SCANNING, &priv->status)) { |
3610 | stats.noise = priv->last_rx_noise; | |
bb8c093b | 3611 | stats.signal = iwl4965_calc_sig_qual(stats.ssi, stats.noise); |
b481de9c ZY |
3612 | } else { |
3613 | stats.noise = IWL_NOISE_MEAS_NOT_AVAILABLE; | |
bb8c093b | 3614 | stats.signal = iwl4965_calc_sig_qual(stats.ssi, 0); |
b481de9c ZY |
3615 | } |
3616 | ||
3617 | /* Reset beacon noise level if not associated. */ | |
bb8c093b | 3618 | if (!iwl4965_is_associated(priv)) |
b481de9c ZY |
3619 | priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE; |
3620 | ||
c8b0e6e1 | 3621 | #ifdef CONFIG_IWL4965_DEBUG |
bb8c093b CH |
3622 | /* TODO: Parts of iwl4965_report_frame are broken for 4965 */ |
3623 | if (iwl4965_debug_level & (IWL_DL_RX)) | |
b481de9c | 3624 | /* Set "1" to report good data frames in groups of 100 */ |
bb8c093b | 3625 | iwl4965_report_frame(priv, pkt, header, 1); |
b481de9c | 3626 | |
bb8c093b | 3627 | if (iwl4965_debug_level & (IWL_DL_RX | IWL_DL_STATS)) |
b481de9c ZY |
3628 | IWL_DEBUG_RX("Rssi %d, noise %d, qual %d, TSF %lu\n", |
3629 | stats.ssi, stats.noise, stats.signal, | |
3630 | (long unsigned int)le64_to_cpu(rx_start->timestamp)); | |
3631 | #endif | |
3632 | ||
bb8c093b | 3633 | network_packet = iwl4965_is_network_packet(priv, header); |
b481de9c ZY |
3634 | if (network_packet) { |
3635 | priv->last_rx_rssi = stats.ssi; | |
3636 | priv->last_beacon_time = priv->ucode_beacon_time; | |
3637 | priv->last_tsf = le64_to_cpu(rx_start->timestamp); | |
3638 | } | |
3639 | ||
3640 | fc = le16_to_cpu(header->frame_control); | |
3641 | switch (fc & IEEE80211_FCTL_FTYPE) { | |
3642 | case IEEE80211_FTYPE_MGMT: | |
3643 | ||
3644 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) | |
3645 | iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM, | |
3646 | header->addr2); | |
3647 | switch (fc & IEEE80211_FCTL_STYPE) { | |
3648 | case IEEE80211_STYPE_PROBE_RESP: | |
3649 | case IEEE80211_STYPE_BEACON: | |
3650 | if ((priv->iw_mode == IEEE80211_IF_TYPE_STA && | |
3651 | !compare_ether_addr(header->addr2, priv->bssid)) || | |
3652 | (priv->iw_mode == IEEE80211_IF_TYPE_IBSS && | |
3653 | !compare_ether_addr(header->addr3, priv->bssid))) { | |
3654 | struct ieee80211_mgmt *mgmt = | |
3655 | (struct ieee80211_mgmt *)header; | |
3656 | u64 timestamp = | |
3657 | le64_to_cpu(mgmt->u.beacon.timestamp); | |
3658 | ||
3659 | priv->timestamp0 = timestamp & 0xFFFFFFFF; | |
3660 | priv->timestamp1 = | |
3661 | (timestamp >> 32) & 0xFFFFFFFF; | |
3662 | priv->beacon_int = le16_to_cpu( | |
3663 | mgmt->u.beacon.beacon_int); | |
3664 | if (priv->call_post_assoc_from_beacon && | |
3665 | (priv->iw_mode == IEEE80211_IF_TYPE_STA)) { | |
3666 | priv->call_post_assoc_from_beacon = 0; | |
3667 | queue_work(priv->workqueue, | |
3668 | &priv->post_associate.work); | |
3669 | } | |
3670 | } | |
3671 | break; | |
3672 | ||
3673 | case IEEE80211_STYPE_ACTION: | |
3674 | break; | |
3675 | ||
3676 | /* | |
471b3efd JB |
3677 | * TODO: Use the new callback function from |
3678 | * mac80211 instead of sniffing these packets. | |
b481de9c ZY |
3679 | */ |
3680 | case IEEE80211_STYPE_ASSOC_RESP: | |
3681 | case IEEE80211_STYPE_REASSOC_RESP: | |
052c4b9f | 3682 | if (network_packet) { |
c8b0e6e1 | 3683 | #ifdef CONFIG_IWL4965_HT |
b481de9c ZY |
3684 | u8 *pos = NULL; |
3685 | struct ieee802_11_elems elems; | |
c8b0e6e1 | 3686 | #endif /*CONFIG_IWL4965_HT */ |
b481de9c ZY |
3687 | struct ieee80211_mgmt *mgnt = |
3688 | (struct ieee80211_mgmt *)header; | |
3689 | ||
7878a5a4 MA |
3690 | /* We have just associated, give some |
3691 | * time for the 4-way handshake if | |
3692 | * any. Don't start scan too early. */ | |
3693 | priv->next_scan_jiffies = jiffies + | |
3694 | IWL_DELAY_NEXT_SCAN_AFTER_ASSOC; | |
3695 | ||
b481de9c ZY |
3696 | priv->assoc_id = (~((1 << 15) | (1 << 14)) |
3697 | & le16_to_cpu(mgnt->u.assoc_resp.aid)); | |
3698 | priv->assoc_capability = | |
3699 | le16_to_cpu( | |
3700 | mgnt->u.assoc_resp.capab_info); | |
c8b0e6e1 | 3701 | #ifdef CONFIG_IWL4965_HT |
b481de9c ZY |
3702 | pos = mgnt->u.assoc_resp.variable; |
3703 | if (!parse_elems(pos, | |
3704 | len - (pos - (u8 *) mgnt), | |
3705 | &elems)) { | |
3706 | if (elems.ht_extra_param && | |
3707 | elems.ht_cap_param) | |
3708 | break; | |
3709 | } | |
c8b0e6e1 | 3710 | #endif /*CONFIG_IWL4965_HT */ |
b481de9c ZY |
3711 | /* assoc_id is 0 no association */ |
3712 | if (!priv->assoc_id) | |
3713 | break; | |
3714 | if (priv->beacon_int) | |
3715 | queue_work(priv->workqueue, | |
3716 | &priv->post_associate.work); | |
3717 | else | |
3718 | priv->call_post_assoc_from_beacon = 1; | |
3719 | } | |
3720 | ||
3721 | break; | |
3722 | ||
3723 | case IEEE80211_STYPE_PROBE_REQ: | |
3724 | if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) && | |
bb8c093b | 3725 | !iwl4965_is_associated(priv)) { |
0795af57 JP |
3726 | DECLARE_MAC_BUF(mac1); |
3727 | DECLARE_MAC_BUF(mac2); | |
3728 | DECLARE_MAC_BUF(mac3); | |
3729 | ||
b481de9c | 3730 | IWL_DEBUG_DROP("Dropping (non network): " |
0795af57 JP |
3731 | "%s, %s, %s\n", |
3732 | print_mac(mac1, header->addr1), | |
3733 | print_mac(mac2, header->addr2), | |
3734 | print_mac(mac3, header->addr3)); | |
b481de9c ZY |
3735 | return; |
3736 | } | |
3737 | } | |
3738 | iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &stats); | |
3739 | break; | |
3740 | ||
3741 | case IEEE80211_FTYPE_CTL: | |
9ab46173 | 3742 | #ifdef CONFIG_IWL4965_HT |
b481de9c ZY |
3743 | switch (fc & IEEE80211_FCTL_STYPE) { |
3744 | case IEEE80211_STYPE_BACK_REQ: | |
3745 | IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n"); | |
3746 | iwl4965_handle_data_packet(priv, 0, include_phy, | |
3747 | rxb, &stats); | |
3748 | break; | |
3749 | default: | |
3750 | break; | |
3751 | } | |
3752 | #endif | |
b481de9c ZY |
3753 | break; |
3754 | ||
0795af57 JP |
3755 | case IEEE80211_FTYPE_DATA: { |
3756 | DECLARE_MAC_BUF(mac1); | |
3757 | DECLARE_MAC_BUF(mac2); | |
3758 | DECLARE_MAC_BUF(mac3); | |
3759 | ||
b481de9c ZY |
3760 | if (priv->iw_mode == IEEE80211_IF_TYPE_AP) |
3761 | iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM, | |
3762 | header->addr2); | |
3763 | ||
3764 | if (unlikely(!network_packet)) | |
3765 | IWL_DEBUG_DROP("Dropping (non network): " | |
0795af57 JP |
3766 | "%s, %s, %s\n", |
3767 | print_mac(mac1, header->addr1), | |
3768 | print_mac(mac2, header->addr2), | |
3769 | print_mac(mac3, header->addr3)); | |
bb8c093b | 3770 | else if (unlikely(iwl4965_is_duplicate_packet(priv, header))) |
0795af57 JP |
3771 | IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n", |
3772 | print_mac(mac1, header->addr1), | |
3773 | print_mac(mac2, header->addr2), | |
3774 | print_mac(mac3, header->addr3)); | |
b481de9c ZY |
3775 | else |
3776 | iwl4965_handle_data_packet(priv, 1, include_phy, rxb, | |
3777 | &stats); | |
3778 | break; | |
0795af57 | 3779 | } |
b481de9c ZY |
3780 | default: |
3781 | break; | |
3782 | ||
3783 | } | |
3784 | } | |
3785 | ||
3786 | /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD). | |
3787 | * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */ | |
bb8c093b CH |
3788 | static void iwl4965_rx_reply_rx_phy(struct iwl4965_priv *priv, |
3789 | struct iwl4965_rx_mem_buffer *rxb) | |
b481de9c | 3790 | { |
bb8c093b | 3791 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
b481de9c ZY |
3792 | priv->last_phy_res[0] = 1; |
3793 | memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]), | |
3794 | sizeof(struct iwl4965_rx_phy_res)); | |
3795 | } | |
3796 | ||
bb8c093b CH |
3797 | static void iwl4965_rx_missed_beacon_notif(struct iwl4965_priv *priv, |
3798 | struct iwl4965_rx_mem_buffer *rxb) | |
b481de9c ZY |
3799 | |
3800 | { | |
c8b0e6e1 | 3801 | #ifdef CONFIG_IWL4965_SENSITIVITY |
bb8c093b CH |
3802 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
3803 | struct iwl4965_missed_beacon_notif *missed_beacon; | |
b481de9c ZY |
3804 | |
3805 | missed_beacon = &pkt->u.missed_beacon; | |
3806 | if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) { | |
3807 | IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n", | |
3808 | le32_to_cpu(missed_beacon->consequtive_missed_beacons), | |
3809 | le32_to_cpu(missed_beacon->total_missed_becons), | |
3810 | le32_to_cpu(missed_beacon->num_recvd_beacons), | |
3811 | le32_to_cpu(missed_beacon->num_expected_beacons)); | |
3812 | priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT; | |
3813 | if (unlikely(!test_bit(STATUS_SCANNING, &priv->status))) | |
3814 | queue_work(priv->workqueue, &priv->sensitivity_work); | |
3815 | } | |
c8b0e6e1 | 3816 | #endif /*CONFIG_IWL4965_SENSITIVITY*/ |
b481de9c ZY |
3817 | } |
3818 | ||
c8b0e6e1 | 3819 | #ifdef CONFIG_IWL4965_HT |
b481de9c | 3820 | |
8b6eaea8 CB |
3821 | /** |
3822 | * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table | |
3823 | */ | |
bb8c093b | 3824 | static void iwl4965_sta_modify_enable_tid_tx(struct iwl4965_priv *priv, |
b481de9c ZY |
3825 | int sta_id, int tid) |
3826 | { | |
3827 | unsigned long flags; | |
3828 | ||
8b6eaea8 | 3829 | /* Remove "disable" flag, to enable Tx for this TID */ |
b481de9c ZY |
3830 | spin_lock_irqsave(&priv->sta_lock, flags); |
3831 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX; | |
3832 | priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid)); | |
3833 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
3834 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
3835 | ||
bb8c093b | 3836 | iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC); |
b481de9c ZY |
3837 | } |
3838 | ||
8b6eaea8 CB |
3839 | /** |
3840 | * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack | |
3841 | * | |
3842 | * Go through block-ack's bitmap of ACK'd frames, update driver's record of | |
3843 | * ACK vs. not. This gets sent to mac80211, then to rate scaling algo. | |
3844 | */ | |
bb8c093b CH |
3845 | static int iwl4965_tx_status_reply_compressed_ba(struct iwl4965_priv *priv, |
3846 | struct iwl4965_ht_agg *agg, | |
3847 | struct iwl4965_compressed_ba_resp* | |
b481de9c ZY |
3848 | ba_resp) |
3849 | ||
3850 | { | |
3851 | int i, sh, ack; | |
fe01b477 RR |
3852 | u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl); |
3853 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); | |
3854 | u64 bitmap; | |
3855 | int successes = 0; | |
3856 | struct ieee80211_tx_status *tx_status; | |
b481de9c ZY |
3857 | |
3858 | if (unlikely(!agg->wait_for_ba)) { | |
3859 | IWL_ERROR("Received BA when not expected\n"); | |
3860 | return -EINVAL; | |
3861 | } | |
8b6eaea8 CB |
3862 | |
3863 | /* Mark that the expected block-ack response arrived */ | |
b481de9c | 3864 | agg->wait_for_ba = 0; |
fe01b477 | 3865 | IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl); |
8b6eaea8 CB |
3866 | |
3867 | /* Calculate shift to align block-ack bits with our Tx window bits */ | |
fe01b477 | 3868 | sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4); |
01ebd063 | 3869 | if (sh < 0) /* tbw something is wrong with indices */ |
b481de9c ZY |
3870 | sh += 0x100; |
3871 | ||
8b6eaea8 | 3872 | /* don't use 64-bit values for now */ |
fe01b477 | 3873 | bitmap = le64_to_cpu(ba_resp->bitmap) >> sh; |
b481de9c ZY |
3874 | |
3875 | if (agg->frame_count > (64 - sh)) { | |
3876 | IWL_DEBUG_TX_REPLY("more frames than bitmap size"); | |
3877 | return -1; | |
3878 | } | |
3879 | ||
3880 | /* check for success or failure according to the | |
8b6eaea8 | 3881 | * transmitted bitmap and block-ack bitmap */ |
fe01b477 | 3882 | bitmap &= agg->bitmap; |
b481de9c | 3883 | |
8b6eaea8 CB |
3884 | /* For each frame attempted in aggregation, |
3885 | * update driver's record of tx frame's status. */ | |
b481de9c | 3886 | for (i = 0; i < agg->frame_count ; i++) { |
fe01b477 RR |
3887 | ack = bitmap & (1 << i); |
3888 | successes += !!ack; | |
b481de9c | 3889 | IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", |
fe01b477 RR |
3890 | ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff, |
3891 | agg->start_idx + i); | |
3892 | } | |
3893 | ||
3894 | tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status; | |
3895 | tx_status->flags = IEEE80211_TX_STATUS_ACK; | |
99556438 RR |
3896 | tx_status->flags |= IEEE80211_TX_STATUS_AMPDU; |
3897 | tx_status->ampdu_ack_map = successes; | |
3898 | tx_status->ampdu_ack_len = agg->frame_count; | |
fe01b477 RR |
3899 | tx_status->control.tx_rate = agg->rate_n_flags; |
3900 | ||
3901 | IWL_DEBUG_TX_REPLY("Bitmap %llx\n", bitmap); | |
3902 | ||
3903 | return 0; | |
3904 | } | |
3905 | ||
3906 | /** | |
3907 | * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration | |
3908 | */ | |
3909 | static void iwl4965_tx_queue_stop_scheduler(struct iwl4965_priv *priv, | |
3910 | u16 txq_id) | |
3911 | { | |
3912 | /* Simply stop the queue, but don't change any configuration; | |
3913 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
3914 | iwl4965_write_prph(priv, | |
3915 | KDR_SCD_QUEUE_STATUS_BITS(txq_id), | |
3916 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
3917 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
3918 | } | |
b481de9c | 3919 | |
fe01b477 RR |
3920 | /** |
3921 | * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID | |
3922 | */ | |
3923 | static int iwl4965_tx_queue_agg_disable(struct iwl4965_priv *priv, u16 txq_id, | |
3924 | u16 ssn_idx, u8 tx_fifo) | |
3925 | { | |
3926 | if (IWL_BACK_QUEUE_FIRST_ID > txq_id) { | |
3927 | IWL_WARNING("queue number too small: %d, must be > %d\n", | |
3928 | txq_id, IWL_BACK_QUEUE_FIRST_ID); | |
3929 | return -EINVAL; | |
b481de9c ZY |
3930 | } |
3931 | ||
fe01b477 RR |
3932 | iwl4965_tx_queue_stop_scheduler(priv, txq_id); |
3933 | ||
3934 | iwl4965_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id)); | |
3935 | ||
3936 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
3937 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
3938 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
3939 | iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx); | |
3940 | ||
3941 | iwl4965_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id)); | |
3942 | iwl4965_txq_ctx_deactivate(priv, txq_id); | |
3943 | iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); | |
3944 | ||
3945 | return 0; | |
3946 | } | |
b481de9c | 3947 | |
fe01b477 RR |
3948 | int iwl4965_check_empty_hw_queue(struct iwl4965_priv *priv, int sta_id, |
3949 | u8 tid, int txq_id) | |
3950 | { | |
3951 | struct iwl4965_queue *q = &priv->txq[txq_id].q; | |
3952 | u8 *addr = priv->stations[sta_id].sta.sta.addr; | |
3953 | struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid]; | |
3954 | ||
3955 | switch (priv->stations[sta_id].tid[tid].agg.state) { | |
3956 | case IWL_EMPTYING_HW_QUEUE_DELBA: | |
3957 | /* We are reclaiming the last packet of the */ | |
3958 | /* aggregated HW queue */ | |
3959 | if (txq_id == tid_data->agg.txq_id && | |
3960 | q->read_ptr == q->write_ptr) { | |
3961 | u16 ssn = SEQ_TO_SN(tid_data->seq_number); | |
3962 | int tx_fifo = default_tid_to_tx_fifo[tid]; | |
3963 | IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n"); | |
3964 | iwl4965_tx_queue_agg_disable(priv, txq_id, | |
3965 | ssn, tx_fifo); | |
3966 | tid_data->agg.state = IWL_AGG_OFF; | |
3967 | ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid); | |
3968 | } | |
3969 | break; | |
3970 | case IWL_EMPTYING_HW_QUEUE_ADDBA: | |
3971 | /* We are reclaiming the last packet of the queue */ | |
3972 | if (tid_data->tfds_in_queue == 0) { | |
3973 | IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n"); | |
3974 | tid_data->agg.state = IWL_AGG_ON; | |
3975 | ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid); | |
3976 | } | |
3977 | break; | |
3978 | } | |
b481de9c ZY |
3979 | return 0; |
3980 | } | |
3981 | ||
8b6eaea8 CB |
3982 | /** |
3983 | * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed | |
3984 | * @index -- current index | |
3985 | * @n_bd -- total number of entries in queue (s/b power of 2) | |
3986 | */ | |
bb8c093b | 3987 | static inline int iwl4965_queue_dec_wrap(int index, int n_bd) |
b481de9c ZY |
3988 | { |
3989 | return (index == 0) ? n_bd - 1 : index - 1; | |
3990 | } | |
3991 | ||
8b6eaea8 CB |
3992 | /** |
3993 | * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA | |
3994 | * | |
3995 | * Handles block-acknowledge notification from device, which reports success | |
3996 | * of frames sent via aggregation. | |
3997 | */ | |
bb8c093b CH |
3998 | static void iwl4965_rx_reply_compressed_ba(struct iwl4965_priv *priv, |
3999 | struct iwl4965_rx_mem_buffer *rxb) | |
b481de9c | 4000 | { |
bb8c093b CH |
4001 | struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data; |
4002 | struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba; | |
b481de9c | 4003 | int index; |
bb8c093b CH |
4004 | struct iwl4965_tx_queue *txq = NULL; |
4005 | struct iwl4965_ht_agg *agg; | |
fe01b477 | 4006 | DECLARE_MAC_BUF(mac); |
8b6eaea8 CB |
4007 | |
4008 | /* "flow" corresponds to Tx queue */ | |
fe01b477 | 4009 | u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); |
8b6eaea8 CB |
4010 | |
4011 | /* "ssn" is start of block-ack Tx window, corresponds to index | |
4012 | * (in Tx queue's circular buffer) of first TFD/frame in window */ | |
b481de9c ZY |
4013 | u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn); |
4014 | ||
fe01b477 | 4015 | if (scd_flow >= ARRAY_SIZE(priv->txq)) { |
b481de9c ZY |
4016 | IWL_ERROR("BUG_ON scd_flow is bigger than number of queues"); |
4017 | return; | |
4018 | } | |
4019 | ||
fe01b477 | 4020 | txq = &priv->txq[scd_flow]; |
b481de9c | 4021 | agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg; |
8b6eaea8 CB |
4022 | |
4023 | /* Find index just before block-ack window */ | |
bb8c093b | 4024 | index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd); |
b481de9c | 4025 | |
01ebd063 | 4026 | /* TODO: Need to get this copy more safely - now good for debug */ |
fe01b477 | 4027 | |
0795af57 JP |
4028 | IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, " |
4029 | "sta_id = %d\n", | |
b481de9c | 4030 | agg->wait_for_ba, |
0795af57 | 4031 | print_mac(mac, (u8*) &ba_resp->sta_addr_lo32), |
b481de9c | 4032 | ba_resp->sta_id); |
fe01b477 | 4033 | IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = " |
b481de9c ZY |
4034 | "%d, scd_ssn = %d\n", |
4035 | ba_resp->tid, | |
fe01b477 RR |
4036 | ba_resp->seq_ctl, |
4037 | ba_resp->bitmap, | |
b481de9c ZY |
4038 | ba_resp->scd_flow, |
4039 | ba_resp->scd_ssn); | |
fe01b477 | 4040 | IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n", |
b481de9c | 4041 | agg->start_idx, |
fe01b477 | 4042 | agg->bitmap); |
8b6eaea8 CB |
4043 | |
4044 | /* Update driver's record of ACK vs. not for each frame in window */ | |
b481de9c | 4045 | iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp); |
8b6eaea8 CB |
4046 | |
4047 | /* Release all TFDs before the SSN, i.e. all TFDs in front of | |
4048 | * block-ack window (we assume that they've been successfully | |
4049 | * transmitted ... if not, it's too late anyway). */ | |
fe01b477 RR |
4050 | if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) { |
4051 | int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index); | |
4052 | priv->stations[ba_resp->sta_id]. | |
4053 | tid[ba_resp->tid].tfds_in_queue -= freed; | |
4054 | if (iwl4965_queue_space(&txq->q) > txq->q.low_mark && | |
4055 | priv->mac80211_registered && | |
4056 | agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) | |
4057 | ieee80211_wake_queue(priv->hw, scd_flow); | |
4058 | iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id, | |
4059 | ba_resp->tid, scd_flow); | |
4060 | } | |
b481de9c ZY |
4061 | } |
4062 | ||
8b6eaea8 CB |
4063 | /** |
4064 | * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue | |
4065 | */ | |
bb8c093b | 4066 | static int iwl4965_tx_queue_set_q2ratid(struct iwl4965_priv *priv, u16 ra_tid, |
b481de9c ZY |
4067 | u16 txq_id) |
4068 | { | |
4069 | u32 tbl_dw_addr; | |
4070 | u32 tbl_dw; | |
4071 | u16 scd_q2ratid; | |
4072 | ||
4073 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
4074 | ||
4075 | tbl_dw_addr = priv->scd_base_addr + | |
4076 | SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); | |
4077 | ||
bb8c093b | 4078 | tbl_dw = iwl4965_read_targ_mem(priv, tbl_dw_addr); |
b481de9c ZY |
4079 | |
4080 | if (txq_id & 0x1) | |
4081 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
4082 | else | |
4083 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
4084 | ||
bb8c093b | 4085 | iwl4965_write_targ_mem(priv, tbl_dw_addr, tbl_dw); |
b481de9c ZY |
4086 | |
4087 | return 0; | |
4088 | } | |
4089 | ||
fe01b477 | 4090 | |
b481de9c | 4091 | /** |
8b6eaea8 CB |
4092 | * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue |
4093 | * | |
4094 | * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID, | |
4095 | * i.e. it must be one of the higher queues used for aggregation | |
b481de9c | 4096 | */ |
bb8c093b | 4097 | static int iwl4965_tx_queue_agg_enable(struct iwl4965_priv *priv, int txq_id, |
b481de9c ZY |
4098 | int tx_fifo, int sta_id, int tid, |
4099 | u16 ssn_idx) | |
4100 | { | |
4101 | unsigned long flags; | |
4102 | int rc; | |
4103 | u16 ra_tid; | |
4104 | ||
4105 | if (IWL_BACK_QUEUE_FIRST_ID > txq_id) | |
4106 | IWL_WARNING("queue number too small: %d, must be > %d\n", | |
4107 | txq_id, IWL_BACK_QUEUE_FIRST_ID); | |
4108 | ||
4109 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
4110 | ||
8b6eaea8 | 4111 | /* Modify device's station table to Tx this TID */ |
bb8c093b | 4112 | iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid); |
b481de9c ZY |
4113 | |
4114 | spin_lock_irqsave(&priv->lock, flags); | |
bb8c093b | 4115 | rc = iwl4965_grab_nic_access(priv); |
b481de9c ZY |
4116 | if (rc) { |
4117 | spin_unlock_irqrestore(&priv->lock, flags); | |
4118 | return rc; | |
4119 | } | |
4120 | ||
8b6eaea8 | 4121 | /* Stop this Tx queue before configuring it */ |
b481de9c ZY |
4122 | iwl4965_tx_queue_stop_scheduler(priv, txq_id); |
4123 | ||
8b6eaea8 | 4124 | /* Map receiver-address / traffic-ID to this queue */ |
b481de9c ZY |
4125 | iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id); |
4126 | ||
8b6eaea8 | 4127 | /* Set this queue as a chain-building queue */ |
8a1b0245 | 4128 | iwl4965_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id)); |
b481de9c | 4129 | |
8b6eaea8 CB |
4130 | /* Place first TFD at index corresponding to start sequence number. |
4131 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
fc4b6853 TW |
4132 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); |
4133 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
b481de9c ZY |
4134 | iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx); |
4135 | ||
8b6eaea8 | 4136 | /* Set up Tx window size and frame limit for this queue */ |
bb8c093b | 4137 | iwl4965_write_targ_mem(priv, |
b481de9c ZY |
4138 | priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id), |
4139 | (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & | |
4140 | SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); | |
4141 | ||
bb8c093b | 4142 | iwl4965_write_targ_mem(priv, priv->scd_base_addr + |
b481de9c ZY |
4143 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
4144 | (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) | |
4145 | & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); | |
4146 | ||
bb8c093b | 4147 | iwl4965_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id)); |
b481de9c | 4148 | |
8b6eaea8 | 4149 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ |
b481de9c ZY |
4150 | iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); |
4151 | ||
bb8c093b | 4152 | iwl4965_release_nic_access(priv); |
b481de9c ZY |
4153 | spin_unlock_irqrestore(&priv->lock, flags); |
4154 | ||
4155 | return 0; | |
4156 | } | |
4157 | ||
c8b0e6e1 | 4158 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c ZY |
4159 | |
4160 | /** | |
4161 | * iwl4965_add_station - Initialize a station's hardware rate table | |
4162 | * | |
8b6eaea8 | 4163 | * The uCode's station table contains a table of fallback rates |
b481de9c ZY |
4164 | * for automatic fallback during transmission. |
4165 | * | |
8b6eaea8 CB |
4166 | * NOTE: This sets up a default set of values. These will be replaced later |
4167 | * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of | |
4168 | * rc80211_simple. | |
b481de9c | 4169 | * |
8b6eaea8 CB |
4170 | * NOTE: Run REPLY_ADD_STA command to set up station table entry, before |
4171 | * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD, | |
4172 | * which requires station table entry to exist). | |
b481de9c | 4173 | */ |
bb8c093b | 4174 | void iwl4965_add_station(struct iwl4965_priv *priv, const u8 *addr, int is_ap) |
b481de9c ZY |
4175 | { |
4176 | int i, r; | |
bb8c093b | 4177 | struct iwl4965_link_quality_cmd link_cmd = { |
b481de9c ZY |
4178 | .reserved1 = 0, |
4179 | }; | |
4180 | u16 rate_flags; | |
4181 | ||
8b6eaea8 CB |
4182 | /* Set up the rate scaling to start at selected rate, fall back |
4183 | * all the way down to 1M in IEEE order, and then spin on 1M */ | |
b481de9c ZY |
4184 | if (is_ap) |
4185 | r = IWL_RATE_54M_INDEX; | |
8318d78a | 4186 | else if (priv->band == IEEE80211_BAND_5GHZ) |
b481de9c ZY |
4187 | r = IWL_RATE_6M_INDEX; |
4188 | else | |
4189 | r = IWL_RATE_1M_INDEX; | |
4190 | ||
4191 | for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) { | |
4192 | rate_flags = 0; | |
4193 | if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE) | |
4194 | rate_flags |= RATE_MCS_CCK_MSK; | |
4195 | ||
8b6eaea8 | 4196 | /* Use Tx antenna B only */ |
b481de9c ZY |
4197 | rate_flags |= RATE_MCS_ANT_B_MSK; |
4198 | rate_flags &= ~RATE_MCS_ANT_A_MSK; | |
8b6eaea8 | 4199 | |
b481de9c | 4200 | link_cmd.rs_table[i].rate_n_flags = |
bb8c093b CH |
4201 | iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags); |
4202 | r = iwl4965_get_prev_ieee_rate(r); | |
b481de9c ZY |
4203 | } |
4204 | ||
4205 | link_cmd.general_params.single_stream_ant_msk = 2; | |
4206 | link_cmd.general_params.dual_stream_ant_msk = 3; | |
4207 | link_cmd.agg_params.agg_dis_start_th = 3; | |
4208 | link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000); | |
4209 | ||
4210 | /* Update the rate scaling for control frame Tx to AP */ | |
4211 | link_cmd.sta_id = is_ap ? IWL_AP_ID : IWL4965_BROADCAST_ID; | |
4212 | ||
bb8c093b | 4213 | iwl4965_send_cmd_pdu(priv, REPLY_TX_LINK_QUALITY_CMD, sizeof(link_cmd), |
b481de9c ZY |
4214 | &link_cmd); |
4215 | } | |
4216 | ||
c8b0e6e1 | 4217 | #ifdef CONFIG_IWL4965_HT |
b481de9c | 4218 | |
8318d78a JB |
4219 | static u8 iwl4965_is_channel_extension(struct iwl4965_priv *priv, |
4220 | enum ieee80211_band band, | |
b481de9c ZY |
4221 | u16 channel, u8 extension_chan_offset) |
4222 | { | |
bb8c093b | 4223 | const struct iwl4965_channel_info *ch_info; |
b481de9c | 4224 | |
8318d78a | 4225 | ch_info = iwl4965_get_channel_info(priv, band, channel); |
b481de9c ZY |
4226 | if (!is_channel_valid(ch_info)) |
4227 | return 0; | |
4228 | ||
4229 | if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_AUTO) | |
4230 | return 0; | |
4231 | ||
4232 | if ((ch_info->fat_extension_channel == extension_chan_offset) || | |
4233 | (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX)) | |
4234 | return 1; | |
4235 | ||
4236 | return 0; | |
4237 | } | |
4238 | ||
bb8c093b | 4239 | static u8 iwl4965_is_fat_tx_allowed(struct iwl4965_priv *priv, |
fd105e79 | 4240 | struct ieee80211_ht_info *sta_ht_inf) |
b481de9c | 4241 | { |
fd105e79 | 4242 | struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config; |
b481de9c | 4243 | |
fd105e79 RR |
4244 | if ((!iwl_ht_conf->is_ht) || |
4245 | (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) || | |
4246 | (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_AUTO)) | |
b481de9c ZY |
4247 | return 0; |
4248 | ||
fd105e79 RR |
4249 | if (sta_ht_inf) { |
4250 | if ((!sta_ht_inf->ht_supported) || | |
194c7ca6 | 4251 | (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH))) |
fd105e79 RR |
4252 | return 0; |
4253 | } | |
b481de9c | 4254 | |
bb8c093b | 4255 | return (iwl4965_is_channel_extension(priv, priv->phymode, |
fd105e79 RR |
4256 | iwl_ht_conf->control_channel, |
4257 | iwl_ht_conf->extension_chan_offset)); | |
b481de9c ZY |
4258 | } |
4259 | ||
fd105e79 | 4260 | void iwl4965_set_rxon_ht(struct iwl4965_priv *priv, struct iwl_ht_info *ht_info) |
b481de9c | 4261 | { |
bb8c093b | 4262 | struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon; |
b481de9c ZY |
4263 | u32 val; |
4264 | ||
4265 | if (!ht_info->is_ht) | |
4266 | return; | |
4267 | ||
8b6eaea8 | 4268 | /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */ |
fd105e79 | 4269 | if (iwl4965_is_fat_tx_allowed(priv, NULL)) |
b481de9c ZY |
4270 | rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK; |
4271 | else | |
4272 | rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK | | |
4273 | RXON_FLG_CHANNEL_MODE_PURE_40_MSK); | |
4274 | ||
4275 | if (le16_to_cpu(rxon->channel) != ht_info->control_channel) { | |
4276 | IWL_DEBUG_ASSOC("control diff than current %d %d\n", | |
4277 | le16_to_cpu(rxon->channel), | |
4278 | ht_info->control_channel); | |
4279 | rxon->channel = cpu_to_le16(ht_info->control_channel); | |
4280 | return; | |
4281 | } | |
4282 | ||
8b6eaea8 | 4283 | /* Note: control channel is opposite of extension channel */ |
b481de9c ZY |
4284 | switch (ht_info->extension_chan_offset) { |
4285 | case IWL_EXT_CHANNEL_OFFSET_ABOVE: | |
4286 | rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK); | |
4287 | break; | |
4288 | case IWL_EXT_CHANNEL_OFFSET_BELOW: | |
4289 | rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK; | |
4290 | break; | |
4291 | case IWL_EXT_CHANNEL_OFFSET_AUTO: | |
4292 | rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK; | |
4293 | break; | |
4294 | default: | |
4295 | rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK; | |
4296 | break; | |
4297 | } | |
4298 | ||
fd105e79 | 4299 | val = ht_info->ht_protection; |
b481de9c ZY |
4300 | |
4301 | rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS); | |
4302 | ||
b481de9c ZY |
4303 | iwl4965_set_rxon_chain(priv); |
4304 | ||
4305 | IWL_DEBUG_ASSOC("supported HT rate 0x%X %X " | |
4306 | "rxon flags 0x%X operation mode :0x%X " | |
4307 | "extension channel offset 0x%x " | |
4308 | "control chan %d\n", | |
fd105e79 RR |
4309 | ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1], |
4310 | le32_to_cpu(rxon->flags), ht_info->ht_protection, | |
b481de9c ZY |
4311 | ht_info->extension_chan_offset, |
4312 | ht_info->control_channel); | |
4313 | return; | |
4314 | } | |
4315 | ||
67d62035 RR |
4316 | void iwl4965_set_ht_add_station(struct iwl4965_priv *priv, u8 index, |
4317 | struct ieee80211_ht_info *sta_ht_inf) | |
b481de9c ZY |
4318 | { |
4319 | __le32 sta_flags; | |
e53cfe0e | 4320 | u8 mimo_ps_mode; |
b481de9c | 4321 | |
67d62035 | 4322 | if (!sta_ht_inf || !sta_ht_inf->ht_supported) |
b481de9c ZY |
4323 | goto done; |
4324 | ||
e53cfe0e TW |
4325 | mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2; |
4326 | ||
b481de9c ZY |
4327 | sta_flags = priv->stations[index].sta.station_flags; |
4328 | ||
e53cfe0e TW |
4329 | sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK); |
4330 | ||
4331 | switch (mimo_ps_mode) { | |
4332 | case WLAN_HT_CAP_MIMO_PS_STATIC: | |
4333 | sta_flags |= STA_FLG_MIMO_DIS_MSK; | |
4334 | break; | |
4335 | case WLAN_HT_CAP_MIMO_PS_DYNAMIC: | |
b481de9c | 4336 | sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK; |
e53cfe0e TW |
4337 | break; |
4338 | case WLAN_HT_CAP_MIMO_PS_DISABLED: | |
4339 | break; | |
4340 | default: | |
4341 | IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode); | |
4342 | break; | |
4343 | } | |
b481de9c ZY |
4344 | |
4345 | sta_flags |= cpu_to_le32( | |
67d62035 | 4346 | (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS); |
b481de9c ZY |
4347 | |
4348 | sta_flags |= cpu_to_le32( | |
67d62035 | 4349 | (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS); |
b481de9c | 4350 | |
67d62035 | 4351 | if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf)) |
b481de9c | 4352 | sta_flags |= STA_FLG_FAT_EN_MSK; |
67d62035 | 4353 | else |
e53cfe0e | 4354 | sta_flags &= ~STA_FLG_FAT_EN_MSK; |
67d62035 | 4355 | |
b481de9c ZY |
4356 | priv->stations[index].sta.station_flags = sta_flags; |
4357 | done: | |
4358 | return; | |
4359 | } | |
4360 | ||
bb8c093b | 4361 | static void iwl4965_sta_modify_add_ba_tid(struct iwl4965_priv *priv, |
b481de9c ZY |
4362 | int sta_id, int tid, u16 ssn) |
4363 | { | |
4364 | unsigned long flags; | |
4365 | ||
4366 | spin_lock_irqsave(&priv->sta_lock, flags); | |
4367 | priv->stations[sta_id].sta.station_flags_msk = 0; | |
4368 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK; | |
4369 | priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid; | |
4370 | priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn); | |
4371 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
4372 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
4373 | ||
bb8c093b | 4374 | iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC); |
b481de9c ZY |
4375 | } |
4376 | ||
bb8c093b | 4377 | static void iwl4965_sta_modify_del_ba_tid(struct iwl4965_priv *priv, |
b481de9c ZY |
4378 | int sta_id, int tid) |
4379 | { | |
4380 | unsigned long flags; | |
4381 | ||
4382 | spin_lock_irqsave(&priv->sta_lock, flags); | |
4383 | priv->stations[sta_id].sta.station_flags_msk = 0; | |
4384 | priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK; | |
4385 | priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid; | |
4386 | priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; | |
4387 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
4388 | ||
bb8c093b | 4389 | iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC); |
b481de9c ZY |
4390 | } |
4391 | ||
8b6eaea8 CB |
4392 | /* |
4393 | * Find first available (lowest unused) Tx Queue, mark it "active". | |
4394 | * Called only when finding queue for aggregation. | |
4395 | * Should never return anything < 7, because they should already | |
4396 | * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6). | |
4397 | */ | |
bb8c093b | 4398 | static int iwl4965_txq_ctx_activate_free(struct iwl4965_priv *priv) |
b481de9c ZY |
4399 | { |
4400 | int txq_id; | |
4401 | ||
4402 | for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) | |
4403 | if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk)) | |
4404 | return txq_id; | |
4405 | return -1; | |
4406 | } | |
4407 | ||
fe01b477 RR |
4408 | static int iwl4965_mac_ht_tx_agg_start(struct ieee80211_hw *hw, const u8 *da, |
4409 | u16 tid, u16 *start_seq_num) | |
b481de9c | 4410 | { |
bb8c093b | 4411 | struct iwl4965_priv *priv = hw->priv; |
b481de9c ZY |
4412 | int sta_id; |
4413 | int tx_fifo; | |
4414 | int txq_id; | |
4415 | int ssn = -1; | |
fe01b477 | 4416 | int rc = 0; |
b481de9c | 4417 | unsigned long flags; |
bb8c093b | 4418 | struct iwl4965_tid_data *tid_data; |
0795af57 | 4419 | DECLARE_MAC_BUF(mac); |
b481de9c ZY |
4420 | |
4421 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) | |
4422 | tx_fifo = default_tid_to_tx_fifo[tid]; | |
4423 | else | |
4424 | return -EINVAL; | |
4425 | ||
fe01b477 RR |
4426 | IWL_WARNING("%s on da = %s tid = %d\n", |
4427 | __func__, print_mac(mac, da), tid); | |
b481de9c | 4428 | |
bb8c093b | 4429 | sta_id = iwl4965_hw_find_station(priv, da); |
b481de9c ZY |
4430 | if (sta_id == IWL_INVALID_STATION) |
4431 | return -ENXIO; | |
4432 | ||
fe01b477 RR |
4433 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) { |
4434 | IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n"); | |
4435 | return -ENXIO; | |
4436 | } | |
4437 | ||
bb8c093b | 4438 | txq_id = iwl4965_txq_ctx_activate_free(priv); |
b481de9c ZY |
4439 | if (txq_id == -1) |
4440 | return -ENXIO; | |
4441 | ||
4442 | spin_lock_irqsave(&priv->sta_lock, flags); | |
4443 | tid_data = &priv->stations[sta_id].tid[tid]; | |
4444 | ssn = SEQ_TO_SN(tid_data->seq_number); | |
4445 | tid_data->agg.txq_id = txq_id; | |
4446 | spin_unlock_irqrestore(&priv->sta_lock, flags); | |
4447 | ||
4448 | *start_seq_num = ssn; | |
fe01b477 | 4449 | rc = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo, |
b481de9c | 4450 | sta_id, tid, ssn); |
fe01b477 RR |
4451 | if (rc) |
4452 | return rc; | |
b481de9c | 4453 | |
fe01b477 RR |
4454 | rc = 0; |
4455 | if (tid_data->tfds_in_queue == 0) { | |
4456 | printk(KERN_ERR "HW queue is empty\n"); | |
4457 | tid_data->agg.state = IWL_AGG_ON; | |
4458 | ieee80211_start_tx_ba_cb_irqsafe(hw, da, tid); | |
4459 | } else { | |
4460 | IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n", | |
4461 | tid_data->tfds_in_queue); | |
4462 | tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA; | |
4463 | } | |
4464 | return rc; | |
4465 | } | |
b481de9c | 4466 | |
fe01b477 RR |
4467 | static int iwl4965_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, const u8 *da, |
4468 | u16 tid) | |
b481de9c ZY |
4469 | { |
4470 | ||
bb8c093b | 4471 | struct iwl4965_priv *priv = hw->priv; |
b481de9c | 4472 | int tx_fifo_id, txq_id, sta_id, ssn = -1; |
bb8c093b | 4473 | struct iwl4965_tid_data *tid_data; |
fe01b477 RR |
4474 | int rc, write_ptr, read_ptr; |
4475 | unsigned long flags; | |
0795af57 JP |
4476 | DECLARE_MAC_BUF(mac); |
4477 | ||
b481de9c | 4478 | if (!da) { |
fe01b477 | 4479 | IWL_ERROR("da = NULL\n"); |
b481de9c ZY |
4480 | return -EINVAL; |
4481 | } | |
4482 | ||
4483 | if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo))) | |
4484 | tx_fifo_id = default_tid_to_tx_fifo[tid]; | |
4485 | else | |
4486 | return -EINVAL; | |
4487 | ||
bb8c093b | 4488 | sta_id = iwl4965_hw_find_station(priv, da); |
b481de9c ZY |
4489 | |
4490 | if (sta_id == IWL_INVALID_STATION) | |
4491 | return -ENXIO; | |
4492 | ||
fe01b477 RR |
4493 | if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON) |
4494 | IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n"); | |
4495 | ||
b481de9c ZY |
4496 | tid_data = &priv->stations[sta_id].tid[tid]; |
4497 | ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4; | |
4498 | txq_id = tid_data->agg.txq_id; | |
fe01b477 RR |
4499 | write_ptr = priv->txq[txq_id].q.write_ptr; |
4500 | read_ptr = priv->txq[txq_id].q.read_ptr; | |
4501 | ||
4502 | /* The queue is not empty */ | |
4503 | if (write_ptr != read_ptr) { | |
4504 | IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n"); | |
4505 | priv->stations[sta_id].tid[tid].agg.state = | |
4506 | IWL_EMPTYING_HW_QUEUE_DELBA; | |
4507 | return 0; | |
4508 | } | |
4509 | ||
4510 | IWL_DEBUG_HT("HW queue empty\n");; | |
4511 | priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF; | |
b481de9c | 4512 | |
fe01b477 RR |
4513 | spin_lock_irqsave(&priv->lock, flags); |
4514 | rc = iwl4965_grab_nic_access(priv); | |
4515 | if (rc) { | |
4516 | spin_unlock_irqrestore(&priv->lock, flags); | |
4517 | return rc; | |
4518 | } | |
b481de9c | 4519 | rc = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id); |
fe01b477 RR |
4520 | iwl4965_release_nic_access(priv); |
4521 | spin_unlock_irqrestore(&priv->lock, flags); | |
4522 | ||
b481de9c ZY |
4523 | if (rc) |
4524 | return rc; | |
4525 | ||
fe01b477 | 4526 | ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, da, tid); |
b481de9c | 4527 | |
fe01b477 RR |
4528 | IWL_DEBUG_INFO("iwl4965_mac_ht_tx_agg_stop on da=%s tid=%d\n", |
4529 | print_mac(mac, da), tid); | |
8114fcf1 | 4530 | |
8114fcf1 RR |
4531 | return 0; |
4532 | } | |
4533 | ||
4534 | int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw, | |
4535 | enum ieee80211_ampdu_mlme_action action, | |
4536 | const u8 *addr, u16 tid, u16 *ssn) | |
4537 | { | |
4538 | struct iwl4965_priv *priv = hw->priv; | |
4539 | int sta_id; | |
4540 | DECLARE_MAC_BUF(mac); | |
4541 | ||
4542 | IWL_DEBUG_HT("A-MPDU action on da=%s tid=%d ", | |
4543 | print_mac(mac, addr), tid); | |
4544 | sta_id = iwl4965_hw_find_station(priv, addr); | |
4545 | switch (action) { | |
4546 | case IEEE80211_AMPDU_RX_START: | |
4547 | IWL_DEBUG_HT("start Rx\n"); | |
4548 | iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, *ssn); | |
4549 | break; | |
4550 | case IEEE80211_AMPDU_RX_STOP: | |
4551 | IWL_DEBUG_HT("stop Rx\n"); | |
4552 | iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid); | |
4553 | break; | |
4554 | case IEEE80211_AMPDU_TX_START: | |
4555 | IWL_DEBUG_HT("start Tx\n"); | |
4556 | return iwl4965_mac_ht_tx_agg_start(hw, addr, tid, ssn); | |
4557 | case IEEE80211_AMPDU_TX_STOP: | |
4558 | IWL_DEBUG_HT("stop Tx\n"); | |
4559 | return iwl4965_mac_ht_tx_agg_stop(hw, addr, tid); | |
4560 | default: | |
4561 | IWL_DEBUG_HT("unknown\n"); | |
4562 | return -EINVAL; | |
4563 | break; | |
4564 | } | |
4565 | return 0; | |
4566 | } | |
4567 | ||
c8b0e6e1 | 4568 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c ZY |
4569 | |
4570 | /* Set up 4965-specific Rx frame reply handlers */ | |
bb8c093b | 4571 | void iwl4965_hw_rx_handler_setup(struct iwl4965_priv *priv) |
b481de9c ZY |
4572 | { |
4573 | /* Legacy Rx frames */ | |
4574 | priv->rx_handlers[REPLY_4965_RX] = iwl4965_rx_reply_rx; | |
4575 | ||
4576 | /* High-throughput (HT) Rx frames */ | |
4577 | priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy; | |
4578 | priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx; | |
4579 | ||
4580 | priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] = | |
4581 | iwl4965_rx_missed_beacon_notif; | |
4582 | ||
c8b0e6e1 | 4583 | #ifdef CONFIG_IWL4965_HT |
b481de9c | 4584 | priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba; |
c8b0e6e1 | 4585 | #endif /* CONFIG_IWL4965_HT */ |
b481de9c ZY |
4586 | } |
4587 | ||
bb8c093b | 4588 | void iwl4965_hw_setup_deferred_work(struct iwl4965_priv *priv) |
b481de9c ZY |
4589 | { |
4590 | INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work); | |
4591 | INIT_WORK(&priv->statistics_work, iwl4965_bg_statistics_work); | |
c8b0e6e1 | 4592 | #ifdef CONFIG_IWL4965_SENSITIVITY |
b481de9c ZY |
4593 | INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work); |
4594 | #endif | |
b481de9c ZY |
4595 | init_timer(&priv->statistics_periodic); |
4596 | priv->statistics_periodic.data = (unsigned long)priv; | |
4597 | priv->statistics_periodic.function = iwl4965_bg_statistics_periodic; | |
4598 | } | |
4599 | ||
bb8c093b | 4600 | void iwl4965_hw_cancel_deferred_work(struct iwl4965_priv *priv) |
b481de9c ZY |
4601 | { |
4602 | del_timer_sync(&priv->statistics_periodic); | |
4603 | ||
4604 | cancel_delayed_work(&priv->init_alive_start); | |
4605 | } | |
4606 | ||
bb8c093b | 4607 | struct pci_device_id iwl4965_hw_card_ids[] = { |
3567c11d ZY |
4608 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4229)}, |
4609 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4230)}, | |
b481de9c ZY |
4610 | {0} |
4611 | }; | |
4612 | ||
796083cb BC |
4613 | /* |
4614 | * The device's EEPROM semaphore prevents conflicts between driver and uCode | |
4615 | * when accessing the EEPROM; each access is a series of pulses to/from the | |
4616 | * EEPROM chip, not a single event, so even reads could conflict if they | |
4617 | * weren't arbitrated by the semaphore. | |
4618 | */ | |
bb8c093b | 4619 | int iwl4965_eeprom_acquire_semaphore(struct iwl4965_priv *priv) |
b481de9c ZY |
4620 | { |
4621 | u16 count; | |
4622 | int rc; | |
4623 | ||
4624 | for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) { | |
796083cb | 4625 | /* Request semaphore */ |
bb8c093b | 4626 | iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
b481de9c | 4627 | CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM); |
796083cb BC |
4628 | |
4629 | /* See if we got it */ | |
bb8c093b | 4630 | rc = iwl4965_poll_bit(priv, CSR_HW_IF_CONFIG_REG, |
b481de9c ZY |
4631 | CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, |
4632 | CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM, | |
4633 | EEPROM_SEM_TIMEOUT); | |
4634 | if (rc >= 0) { | |
91e17473 | 4635 | IWL_DEBUG_IO("Acquired semaphore after %d tries.\n", |
b481de9c ZY |
4636 | count+1); |
4637 | return rc; | |
4638 | } | |
4639 | } | |
4640 | ||
4641 | return rc; | |
4642 | } | |
4643 | ||
bb8c093b | 4644 | MODULE_DEVICE_TABLE(pci, iwl4965_hw_card_ids); |