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iwlwifi: workaround interrupt handling no some platforms
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <net/mac80211.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47 38#include <asm/unaligned.h>
b481de9c 39
6bc913bd 40#include "iwl-eeprom.h"
3e0d4cb1 41#include "iwl-dev.h"
fee1247a 42#include "iwl-core.h"
3395f6e9 43#include "iwl-io.h"
b481de9c 44#include "iwl-helpers.h"
f0832f13 45#include "iwl-calib.h"
5083e563 46#include "iwl-sta.h"
b481de9c 47
630fe9b6 48static int iwl4965_send_tx_power(struct iwl_priv *priv);
91dbc5bd 49static int iwl4965_hw_get_temperature(const struct iwl_priv *priv);
630fe9b6 50
d16dc48a
TW		 51/* Change firmware file name, using "-" and incrementing number,
52 * *only* when uCode interface or architecture changes so that it
53 * is not compatible with earlier drivers.
54 * This number will also appear in << 8 position of 1st dword of uCode file */
55#define IWL4965_UCODE_API "-2"
56
57
1ea87396
AK		 58/* module parameters */
59static struct iwl_mod_params iwl4965_mod_params = {
038669e4 60 .num_of_queues = IWL49_NUM_QUEUES,
9f17b318 61 .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
1ea87396
AK		 62 .enable_qos = 1,
63 .amsdu_size_8K = 1,
3a1081e8 64 .restart_fw = 1,
1ea87396
AK		 65 /* the rest are 0 by default */
66};
67
57aab75a
TW		 68/* check contents of special bootstrap uCode SRAM */
69static int iwl4965_verify_bsm(struct iwl_priv *priv)
70{
71 __le32 *image = priv->ucode_boot.v_addr;
72 u32 len = priv->ucode_boot.len;
73 u32 reg;
74 u32 val;
75
76 IWL_DEBUG_INFO("Begin verify bsm\n");
77
78 /* verify BSM SRAM contents */
79 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
80 for (reg = BSM_SRAM_LOWER_BOUND;
81 reg < BSM_SRAM_LOWER_BOUND + len;
82 reg += sizeof(u32), image++) {
83 val = iwl_read_prph(priv, reg);
84 if (val != le32_to_cpu(*image)) {
85 IWL_ERROR("BSM uCode verification failed at "
86 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
87 BSM_SRAM_LOWER_BOUND,
88 reg - BSM_SRAM_LOWER_BOUND, len,
89 val, le32_to_cpu(*image));
90 return -EIO;
91 }
92 }
93
94 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
95
96 return 0;
97}
98
99/**
100 * iwl4965_load_bsm - Load bootstrap instructions
101 *
102 * BSM operation:
103 *
104 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
105 * in special SRAM that does not power down during RFKILL. When powering back
106 * up after power-saving sleeps (or during initial uCode load), the BSM loads
107 * the bootstrap program into the on-board processor, and starts it.
108 *
109 * The bootstrap program loads (via DMA) instructions and data for a new
110 * program from host DRAM locations indicated by the host driver in the
111 * BSM_DRAM_* registers. Once the new program is loaded, it starts
112 * automatically.
113 *
114 * When initializing the NIC, the host driver points the BSM to the
115 * "initialize" uCode image. This uCode sets up some internal data, then
116 * notifies host via "initialize alive" that it is complete.
117 *
118 * The host then replaces the BSM_DRAM_* pointer values to point to the
119 * normal runtime uCode instructions and a backup uCode data cache buffer
120 * (filled initially with starting data values for the on-board processor),
121 * then triggers the "initialize" uCode to load and launch the runtime uCode,
122 * which begins normal operation.
123 *
124 * When doing a power-save shutdown, runtime uCode saves data SRAM into
125 * the backup data cache in DRAM before SRAM is powered down.
126 *
127 * When powering back up, the BSM loads the bootstrap program. This reloads
128 * the runtime uCode instructions and the backup data cache into SRAM,
129 * and re-launches the runtime uCode from where it left off.
130 */
131static int iwl4965_load_bsm(struct iwl_priv *priv)
132{
133 __le32 *image = priv->ucode_boot.v_addr;
134 u32 len = priv->ucode_boot.len;
135 dma_addr_t pinst;
136 dma_addr_t pdata;
137 u32 inst_len;
138 u32 data_len;
139 int i;
140 u32 done;
141 u32 reg_offset;
142 int ret;
143
144 IWL_DEBUG_INFO("Begin load bsm\n");
145
fe9b6b72
RR		 146 priv->ucode_type = UCODE_RT;
147
57aab75a
TW		 148 /* make sure bootstrap program is no larger than BSM's SRAM size */
149 if (len > IWL_MAX_BSM_SIZE)
150 return -EINVAL;
151
152 /* Tell bootstrap uCode where to find the "Initialize" uCode
153 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
2d87889f 154 * NOTE: iwl_init_alive_start() will replace these values,
57aab75a 155 * after the "initialize" uCode has run, to point to
2d87889f
TW		 156 * runtime/protocol instructions and backup data cache.
157 */
57aab75a
TW		 158 pinst = priv->ucode_init.p_addr >> 4;
159 pdata = priv->ucode_init_data.p_addr >> 4;
160 inst_len = priv->ucode_init.len;
161 data_len = priv->ucode_init_data.len;
162
163 ret = iwl_grab_nic_access(priv);
164 if (ret)
165 return ret;
166
167 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
168 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
169 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
170 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
171
172 /* Fill BSM memory with bootstrap instructions */
173 for (reg_offset = BSM_SRAM_LOWER_BOUND;
174 reg_offset < BSM_SRAM_LOWER_BOUND + len;
175 reg_offset += sizeof(u32), image++)
176 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
177
178 ret = iwl4965_verify_bsm(priv);
179 if (ret) {
180 iwl_release_nic_access(priv);
181 return ret;
182 }
183
184 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
185 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
186 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
187 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
188
189 /* Load bootstrap code into instruction SRAM now,
190 * to prepare to load "initialize" uCode */
191 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
192
193 /* Wait for load of bootstrap uCode to finish */
194 for (i = 0; i < 100; i++) {
195 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
196 if (!(done & BSM_WR_CTRL_REG_BIT_START))
197 break;
198 udelay(10);
199 }
200 if (i < 100)
201 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
202 else {
203 IWL_ERROR("BSM write did not complete!\n");
204 return -EIO;
205 }
206
207 /* Enable future boot loads whenever power management unit triggers it
208 * (e.g. when powering back up after power-save shutdown) */
209 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
210
211 iwl_release_nic_access(priv);
212
213 return 0;
214}
215
f3ccc08c
EG		 216/**
217 * iwl4965_set_ucode_ptrs - Set uCode address location
218 *
219 * Tell initialization uCode where to find runtime uCode.
220 *
221 * BSM registers initially contain pointers to initialization uCode.
222 * We need to replace them to load runtime uCode inst and data,
223 * and to save runtime data when powering down.
224 */
225static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
226{
227 dma_addr_t pinst;
228 dma_addr_t pdata;
229 unsigned long flags;
230 int ret = 0;
231
232 /* bits 35:4 for 4965 */
233 pinst = priv->ucode_code.p_addr >> 4;
234 pdata = priv->ucode_data_backup.p_addr >> 4;
235
236 spin_lock_irqsave(&priv->lock, flags);
237 ret = iwl_grab_nic_access(priv);
238 if (ret) {
239 spin_unlock_irqrestore(&priv->lock, flags);
240 return ret;
241 }
242
243 /* Tell bootstrap uCode where to find image to load */
244 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
245 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
246 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
247 priv->ucode_data.len);
248
249 /* Inst bytecount must be last to set up, bit 31 signals uCode
250 * that all new ptr/size info is in place */
251 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
252 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
253 iwl_release_nic_access(priv);
254
255 spin_unlock_irqrestore(&priv->lock, flags);
256
257 IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
258
259 return ret;
260}
261
262/**
263 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
264 *
265 * Called after REPLY_ALIVE notification received from "initialize" uCode.
266 *
267 * The 4965 "initialize" ALIVE reply contains calibration data for:
268 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
269 * (3945 does not contain this data).
270 *
271 * Tell "initialize" uCode to go ahead and load the runtime uCode.
272*/
273static void iwl4965_init_alive_start(struct iwl_priv *priv)
274{
275 /* Check alive response for "valid" sign from uCode */
276 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
277 /* We had an error bringing up the hardware, so take it
278 * all the way back down so we can try again */
279 IWL_DEBUG_INFO("Initialize Alive failed.\n");
280 goto restart;
281 }
282
283 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
284 * This is a paranoid check, because we would not have gotten the
285 * "initialize" alive if code weren't properly loaded. */
286 if (iwl_verify_ucode(priv)) {
287 /* Runtime instruction load was bad;
288 * take it all the way back down so we can try again */
289 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
290 goto restart;
291 }
292
293 /* Calculate temperature */
91dbc5bd 294 priv->temperature = iwl4965_hw_get_temperature(priv);
f3ccc08c
EG		 295
296 /* Send pointers to protocol/runtime uCode image ... init code will
297 * load and launch runtime uCode, which will send us another "Alive"
298 * notification. */
299 IWL_DEBUG_INFO("Initialization Alive received.\n");
300 if (iwl4965_set_ucode_ptrs(priv)) {
301 /* Runtime instruction load won't happen;
302 * take it all the way back down so we can try again */
303 IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
304 goto restart;
305 }
306 return;
307
308restart:
309 queue_work(priv->workqueue, &priv->restart);
310}
311
b481de9c
ZY		 312static int is_fat_channel(__le32 rxon_flags)
313{
314 return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
315 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
316}
317
8614f360
TW		 318/*
319 * EEPROM handlers
320 */
321
322static int iwl4965_eeprom_check_version(struct iwl_priv *priv)
323{
324 u16 eeprom_ver;
325 u16 calib_ver;
326
327 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
328
329 calib_ver = iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
330
331 if (eeprom_ver < EEPROM_4965_EEPROM_VERSION ||
332 calib_ver < EEPROM_4965_TX_POWER_VERSION)
333 goto err;
334
335 return 0;
336err:
337 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
338 eeprom_ver, EEPROM_4965_EEPROM_VERSION,
339 calib_ver, EEPROM_4965_TX_POWER_VERSION);
340 return -EINVAL;
341
342}
b481de9c 343
da1bc453
TW		 344/*
345 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
346 * must be called under priv->lock and mac access
347 */
348static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
b481de9c 349{
da1bc453 350 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
b481de9c
ZY		 351}
352
91238714 353static int iwl4965_apm_init(struct iwl_priv *priv)
b481de9c 354{
91238714 355 int ret = 0;
b481de9c 356
3395f6e9 357 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
91238714 358 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
b481de9c 359
8f061891
TW		 360 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
361 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
362 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
363
91238714
TW		 364 /* set "initialization complete" bit to move adapter
365 * D0U* --> D0A* state */
3395f6e9 366 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
b481de9c 367
91238714
TW		 368 /* wait for clock stabilization */
369 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
370 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
371 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
372 if (ret < 0) {
373 IWL_DEBUG_INFO("Failed to init the card\n");
374 goto out;
b481de9c
ZY		 375 }
376
91238714
TW		 377 ret = iwl_grab_nic_access(priv);
378 if (ret)
379 goto out;
b481de9c 380
91238714 381 /* enable DMA */
8f061891
TW		 382 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
383 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c
ZY		 384
385 udelay(20);
386
8f061891 387 /* disable L1-Active */
3395f6e9 388 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
91238714 389 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 390
3395f6e9 391 iwl_release_nic_access(priv);
91238714 392out:
91238714
TW		 393 return ret;
394}
395
694cc56d
TW		 396
397static void iwl4965_nic_config(struct iwl_priv *priv)
91238714
TW		 398{
399 unsigned long flags;
91238714 400 u32 val;
694cc56d
TW		 401 u16 radio_cfg;
402 u8 val_link;
6f4083aa 403
b481de9c
ZY		 404 spin_lock_irqsave(&priv->lock, flags);
405
b661c819 406 if ((priv->rev_id & 0x80) == 0x80 && (priv->rev_id & 0x7f) < 8) {
b481de9c
ZY		 407 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
408 /* Enable No Snoop field */
409 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
410 val & ~(1 << 11));
411 }
412
b481de9c
ZY		 413 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
414
8f061891
TW		 415 /* L1 is enabled by BIOS */
416 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
417 /* diable L0S disabled L1A enabled */
418 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
419 else
420 /* L0S enabled L1A disabled */
421 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
b481de9c 422
694cc56d 423 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
b481de9c 424
694cc56d
TW		 425 /* write radio config values to register */
426 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
427 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
428 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
429 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
430 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
b481de9c 431
694cc56d 432 /* set CSR_HW_CONFIG_REG for uCode use */
3395f6e9 433 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
a395b920
TW		 434 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
435 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
b481de9c 436
694cc56d
TW		 437 priv->calib_info = (struct iwl_eeprom_calib_info *)
438 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
439
440 spin_unlock_irqrestore(&priv->lock, flags);
441}
442
46315e01
TW		 443static int iwl4965_apm_stop_master(struct iwl_priv *priv)
444{
445 int ret = 0;
446 unsigned long flags;
447
448 spin_lock_irqsave(&priv->lock, flags);
449
450 /* set stop master bit */
451 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
452
453 ret = iwl_poll_bit(priv, CSR_RESET,
454 CSR_RESET_REG_FLAG_MASTER_DISABLED,
455 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
456 if (ret < 0)
457 goto out;
458
459out:
460 spin_unlock_irqrestore(&priv->lock, flags);
461 IWL_DEBUG_INFO("stop master\n");
462
463 return ret;
464}
465
f118a91d
TW		 466static void iwl4965_apm_stop(struct iwl_priv *priv)
467{
468 unsigned long flags;
469
46315e01 470 iwl4965_apm_stop_master(priv);
f118a91d
TW		 471
472 spin_lock_irqsave(&priv->lock, flags);
473
474 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
475
476 udelay(10);
477
478 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
479 spin_unlock_irqrestore(&priv->lock, flags);
480}
481
7f066108 482static int iwl4965_apm_reset(struct iwl_priv *priv)
b481de9c 483{
7f066108 484 int ret = 0;
b481de9c
ZY		 485 unsigned long flags;
486
46315e01 487 iwl4965_apm_stop_master(priv);
b481de9c
ZY		 488
489 spin_lock_irqsave(&priv->lock, flags);
490
3395f6e9 491 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c
ZY		 492
493 udelay(10);
494
7f066108
TW		 495 /* FIXME: put here L1A -L0S w/a */
496
3395f6e9 497 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
f118a91d 498
7f066108 499 ret = iwl_poll_bit(priv, CSR_RESET,
b481de9c
ZY		 500 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
501 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
502
7f066108
TW		 503 if (ret)
504 goto out;
505
b481de9c
ZY		 506 udelay(10);
507
7f066108
TW		 508 ret = iwl_grab_nic_access(priv);
509 if (ret)
510 goto out;
511 /* Enable DMA and BSM Clock */
512 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
513 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c 514
7f066108 515 udelay(10);
b481de9c 516
7f066108
TW		 517 /* disable L1A */
518 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
519 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
b481de9c 520
7f066108 521 iwl_release_nic_access(priv);
b481de9c
ZY		 522
523 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
524 wake_up_interruptible(&priv->wait_command_queue);
525
7f066108 526out:
b481de9c
ZY		 527 spin_unlock_irqrestore(&priv->lock, flags);
528
7f066108 529 return ret;
b481de9c
ZY		 530}
531
b481de9c
ZY		 532/* Reset differential Rx gains in NIC to prepare for chain noise calibration.
533 * Called after every association, but this runs only once!
534 * ... once chain noise is calibrated the first time, it's good forever. */
f0832f13 535static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
b481de9c 536{
f0832f13 537 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
b481de9c 538
3109ece1 539 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
bb8c093b 540 struct iwl4965_calibration_cmd cmd;
b481de9c
ZY		 541
542 memset(&cmd, 0, sizeof(cmd));
543 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
544 cmd.diff_gain_a = 0;
545 cmd.diff_gain_b = 0;
546 cmd.diff_gain_c = 0;
f0832f13
EG		 547 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
548 sizeof(cmd), &cmd))
549 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
b481de9c
ZY		 550 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
551 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
552 }
b481de9c
ZY		 553}
554
f0832f13
EG		 555static void iwl4965_gain_computation(struct iwl_priv *priv,
556 u32 *average_noise,
557 u16 min_average_noise_antenna_i,
558 u32 min_average_noise)
b481de9c 559{
f0832f13
EG		 560 int i, ret;
561 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
b481de9c 562
f0832f13 563 data->delta_gain_code[min_average_noise_antenna_i] = 0;
b481de9c 564
f0832f13
EG		 565 for (i = 0; i < NUM_RX_CHAINS; i++) {
566 s32 delta_g = 0;
b481de9c 567
f0832f13
EG		 568 if (!(data->disconn_array[i]) &&
569 (data->delta_gain_code[i] ==
b481de9c 570 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
f0832f13
EG		 571 delta_g = average_noise[i] - min_average_noise;
572 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
573 data->delta_gain_code[i] =
574 min(data->delta_gain_code[i],
575 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
576
577 data->delta_gain_code[i] =
578 (data->delta_gain_code[i] | (1 << 2));
579 } else {
580 data->delta_gain_code[i] = 0;
b481de9c 581 }
b481de9c 582 }
f0832f13
EG		 583 IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
584 data->delta_gain_code[0],
585 data->delta_gain_code[1],
586 data->delta_gain_code[2]);
b481de9c 587
f0832f13
EG		 588 /* Differential gain gets sent to uCode only once */
589 if (!data->radio_write) {
590 struct iwl4965_calibration_cmd cmd;
591 data->radio_write = 1;
b481de9c 592
f0832f13
EG		 593 memset(&cmd, 0, sizeof(cmd));
594 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
595 cmd.diff_gain_a = data->delta_gain_code[0];
596 cmd.diff_gain_b = data->delta_gain_code[1];
597 cmd.diff_gain_c = data->delta_gain_code[2];
598 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
599 sizeof(cmd), &cmd);
600 if (ret)
601 IWL_DEBUG_CALIB("fail sending cmd "
602 "REPLY_PHY_CALIBRATION_CMD \n");
603
604 /* TODO we might want recalculate
605 * rx_chain in rxon cmd */
606
607 /* Mark so we run this algo only once! */
608 data->state = IWL_CHAIN_NOISE_CALIBRATED;
b481de9c 609 }
f0832f13
EG		 610 data->chain_noise_a = 0;
611 data->chain_noise_b = 0;
612 data->chain_noise_c = 0;
613 data->chain_signal_a = 0;
614 data->chain_signal_b = 0;
615 data->chain_signal_c = 0;
616 data->beacon_count = 0;
b481de9c
ZY		 617}
618
a326a5d0
EG		 619static void iwl4965_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
620 __le32 *tx_flags)
621{
622 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
623 *tx_flags |= TX_CMD_FLG_RTS_MSK;
624 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
625 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
626 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
627 *tx_flags |= TX_CMD_FLG_CTS_MSK;
628 }
629}
630
b481de9c
ZY		 631static void iwl4965_bg_txpower_work(struct work_struct *work)
632{
c79dd5b5 633 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 634 txpower_work);
635
636 /* If a scan happened to start before we got here
637 * then just return; the statistics notification will
638 * kick off another scheduled work to compensate for
639 * any temperature delta we missed here. */
640 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
641 test_bit(STATUS_SCANNING, &priv->status))
642 return;
643
644 mutex_lock(&priv->mutex);
645
646 /* Regardless of if we are assocaited, we must reconfigure the
647 * TX power since frames can be sent on non-radar channels while
648 * not associated */
630fe9b6 649 iwl4965_send_tx_power(priv);
b481de9c
ZY		 650
651 /* Update last_temperature to keep is_calib_needed from running
652 * when it isn't needed... */
653 priv->last_temperature = priv->temperature;
654
655 mutex_unlock(&priv->mutex);
656}
657
658/*
659 * Acquire priv->lock before calling this function !
660 */
c79dd5b5 661static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
b481de9c 662{
3395f6e9 663 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
b481de9c 664 (index & 0xff) | (txq_id << 8));
12a81f60 665 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
b481de9c
ZY		 666}
667
8b6eaea8
CB		 668/**
669 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
670 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
671 * @scd_retry: (1) Indicates queue will be used in aggregation mode
672 *
673 * NOTE: Acquire priv->lock before calling this function !
b481de9c 674 */
c79dd5b5 675static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
16466903 676 struct iwl_tx_queue *txq,
b481de9c
ZY		 677 int tx_fifo_id, int scd_retry)
678{
679 int txq_id = txq->q.id;
8b6eaea8
CB		 680
681 /* Find out whether to activate Tx queue */
b481de9c
ZY		 682 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
683
8b6eaea8 684 /* Set up and activate */
12a81f60 685 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 686 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
687 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
688 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
689 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
690 IWL49_SCD_QUEUE_STTS_REG_MSK);
b481de9c
ZY		 691
692 txq->sched_retry = scd_retry;
693
694 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
8b6eaea8 695 active ? "Activate" : "Deactivate",
b481de9c
ZY		 696 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
697}
698
699static const u16 default_queue_to_tx_fifo[] = {
700 IWL_TX_FIFO_AC3,
701 IWL_TX_FIFO_AC2,
702 IWL_TX_FIFO_AC1,
703 IWL_TX_FIFO_AC0,
038669e4 704 IWL49_CMD_FIFO_NUM,
b481de9c
ZY		 705 IWL_TX_FIFO_HCCA_1,
706 IWL_TX_FIFO_HCCA_2
707};
708
be1f3ab6 709static int iwl4965_alive_notify(struct iwl_priv *priv)
b481de9c
ZY		 710{
711 u32 a;
712 int i = 0;
713 unsigned long flags;
857485c0 714 int ret;
b481de9c
ZY		 715
716 spin_lock_irqsave(&priv->lock, flags);
717
3395f6e9 718 ret = iwl_grab_nic_access(priv);
857485c0 719 if (ret) {
b481de9c 720 spin_unlock_irqrestore(&priv->lock, flags);
857485c0 721 return ret;
b481de9c
ZY		 722 }
723
8b6eaea8 724 /* Clear 4965's internal Tx Scheduler data base */
12a81f60 725 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
038669e4
EG		 726 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
727 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
3395f6e9 728 iwl_write_targ_mem(priv, a, 0);
038669e4 729 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
3395f6e9 730 iwl_write_targ_mem(priv, a, 0);
5425e490 731 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
3395f6e9 732 iwl_write_targ_mem(priv, a, 0);
b481de9c 733
8b6eaea8 734 /* Tel 4965 where to find Tx byte count tables */
12a81f60 735 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
059ff826 736 (priv->shared_phys +
bb8c093b 737 offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
8b6eaea8
CB		 738
739 /* Disable chain mode for all queues */
12a81f60 740 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
b481de9c 741
8b6eaea8 742 /* Initialize each Tx queue (including the command queue) */
5425e490 743 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
8b6eaea8
CB		 744
745 /* TFD circular buffer read/write indexes */
12a81f60 746 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
3395f6e9 747 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
8b6eaea8
CB		 748
749 /* Max Tx Window size for Scheduler-ACK mode */
3395f6e9 750 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 751 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
752 (SCD_WIN_SIZE <<
753 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
754 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
8b6eaea8
CB		 755
756 /* Frame limit */
3395f6e9 757 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 758 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
759 sizeof(u32),
760 (SCD_FRAME_LIMIT <<
761 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
762 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c
ZY		 763
764 }
12a81f60 765 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
5425e490 766 (1 << priv->hw_params.max_txq_num) - 1);
b481de9c 767
8b6eaea8 768 /* Activate all Tx DMA/FIFO channels */
da1bc453 769 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
b481de9c
ZY		 770
771 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
8b6eaea8
CB		 772
773 /* Map each Tx/cmd queue to its corresponding fifo */
b481de9c
ZY		 774 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
775 int ac = default_queue_to_tx_fifo[i];
36470749 776 iwl_txq_ctx_activate(priv, i);
b481de9c
ZY		 777 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
778 }
779
3395f6e9 780 iwl_release_nic_access(priv);
b481de9c
ZY		 781 spin_unlock_irqrestore(&priv->lock, flags);
782
857485c0 783 return ret;
b481de9c
ZY		 784}
785
f0832f13
EG		 786static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
787 .min_nrg_cck = 97,
788 .max_nrg_cck = 0,
789
790 .auto_corr_min_ofdm = 85,
791 .auto_corr_min_ofdm_mrc = 170,
792 .auto_corr_min_ofdm_x1 = 105,
793 .auto_corr_min_ofdm_mrc_x1 = 220,
794
795 .auto_corr_max_ofdm = 120,
796 .auto_corr_max_ofdm_mrc = 210,
797 .auto_corr_max_ofdm_x1 = 140,
798 .auto_corr_max_ofdm_mrc_x1 = 270,
799
800 .auto_corr_min_cck = 125,
801 .auto_corr_max_cck = 200,
802 .auto_corr_min_cck_mrc = 200,
803 .auto_corr_max_cck_mrc = 400,
804
805 .nrg_th_cck = 100,
806 .nrg_th_ofdm = 100,
807};
f0832f13 808
8b6eaea8 809/**
5425e490 810 * iwl4965_hw_set_hw_params
8b6eaea8
CB		 811 *
812 * Called when initializing driver
813 */
be1f3ab6 814static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 815{
316c30d9 816
038669e4 817 if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
1ea87396 818 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
316c30d9 819 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
038669e4 820 IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
059ff826 821 return -EINVAL;
316c30d9 822 }
b481de9c 823
5425e490 824 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
7f3e4bb6 825 priv->hw_params.first_ampdu_q = IWL49_FIRST_AMPDU_QUEUE;
5425e490
TW		 826 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
827 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
099b40b7
RR		 828 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
829 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
830 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
831 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
832
ec35cf2a
TW		 833 priv->hw_params.tx_chains_num = 2;
834 priv->hw_params.rx_chains_num = 2;
fde0db31
GC		 835 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
836 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
099b40b7
RR		 837 priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
838
f0832f13 839 priv->hw_params.sens = &iwl4965_sensitivity;
3e82a822 840
059ff826 841 return 0;
b481de9c
ZY		 842}
843
b481de9c
ZY		 844static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
845{
846 s32 sign = 1;
847
848 if (num < 0) {
849 sign = -sign;
850 num = -num;
851 }
852 if (denom < 0) {
853 sign = -sign;
854 denom = -denom;
855 }
856 *res = 1;
857 *res = ((num * 2 + denom) / (denom * 2)) * sign;
858
859 return 1;
860}
861
8b6eaea8
CB		 862/**
863 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
864 *
865 * Determines power supply voltage compensation for txpower calculations.
866 * Returns number of 1/2-dB steps to subtract from gain table index,
867 * to compensate for difference between power supply voltage during
868 * factory measurements, vs. current power supply voltage.
869 *
870 * Voltage indication is higher for lower voltage.
871 * Lower voltage requires more gain (lower gain table index).
872 */
b481de9c
ZY		 873static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
874 s32 current_voltage)
875{
876 s32 comp = 0;
877
878 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
879 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
880 return 0;
881
882 iwl4965_math_div_round(current_voltage - eeprom_voltage,
883 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
884
885 if (current_voltage > eeprom_voltage)
886 comp *= 2;
887 if ((comp < -2) || (comp > 2))
888 comp = 0;
889
890 return comp;
891}
892
b481de9c
ZY		 893static s32 iwl4965_get_tx_atten_grp(u16 channel)
894{
895 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
896 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
897 return CALIB_CH_GROUP_5;
898
899 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
900 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
901 return CALIB_CH_GROUP_1;
902
903 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
904 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
905 return CALIB_CH_GROUP_2;
906
907 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
908 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
909 return CALIB_CH_GROUP_3;
910
911 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
912 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
913 return CALIB_CH_GROUP_4;
914
915 IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
916 return -1;
917}
918
c79dd5b5 919static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
b481de9c
ZY		 920{
921 s32 b = -1;
922
923 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
073d3f5f 924 if (priv->calib_info->band_info[b].ch_from == 0)
b481de9c
ZY		 925 continue;
926
073d3f5f
TW		 927 if ((channel >= priv->calib_info->band_info[b].ch_from)
928 && (channel <= priv->calib_info->band_info[b].ch_to))
b481de9c
ZY		 929 break;
930 }
931
932 return b;
933}
934
935static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
936{
937 s32 val;
938
939 if (x2 == x1)
940 return y1;
941 else {
942 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
943 return val + y2;
944 }
945}
946
8b6eaea8
CB		 947/**
948 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
949 *
950 * Interpolates factory measurements from the two sample channels within a
951 * sub-band, to apply to channel of interest. Interpolation is proportional to
952 * differences in channel frequencies, which is proportional to differences
953 * in channel number.
954 */
c79dd5b5 955static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
073d3f5f 956 struct iwl_eeprom_calib_ch_info *chan_info)
b481de9c
ZY		 957{
958 s32 s = -1;
959 u32 c;
960 u32 m;
073d3f5f
TW		 961 const struct iwl_eeprom_calib_measure *m1;
962 const struct iwl_eeprom_calib_measure *m2;
963 struct iwl_eeprom_calib_measure *omeas;
b481de9c
ZY		 964 u32 ch_i1;
965 u32 ch_i2;
966
967 s = iwl4965_get_sub_band(priv, channel);
968 if (s >= EEPROM_TX_POWER_BANDS) {
6f147926 969 IWL_ERROR("Tx Power can not find channel %d\n", channel);
b481de9c
ZY		 970 return -1;
971 }
972
073d3f5f
TW		 973 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
974 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
b481de9c
ZY		 975 chan_info->ch_num = (u8) channel;
976
977 IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
978 channel, s, ch_i1, ch_i2);
979
980 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
981 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
073d3f5f 982 m1 = &(priv->calib_info->band_info[s].ch1.
b481de9c 983 measurements[c][m]);
073d3f5f 984 m2 = &(priv->calib_info->band_info[s].ch2.
b481de9c
ZY		 985 measurements[c][m]);
986 omeas = &(chan_info->measurements[c][m]);
987
988 omeas->actual_pow =
989 (u8) iwl4965_interpolate_value(channel, ch_i1,
990 m1->actual_pow,
991 ch_i2,
992 m2->actual_pow);
993 omeas->gain_idx =
994 (u8) iwl4965_interpolate_value(channel, ch_i1,
995 m1->gain_idx, ch_i2,
996 m2->gain_idx);
997 omeas->temperature =
998 (u8) iwl4965_interpolate_value(channel, ch_i1,
999 m1->temperature,
1000 ch_i2,
1001 m2->temperature);
1002 omeas->pa_det =
1003 (s8) iwl4965_interpolate_value(channel, ch_i1,
1004 m1->pa_det, ch_i2,
1005 m2->pa_det);
1006
1007 IWL_DEBUG_TXPOWER
1008 ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1009 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1010 IWL_DEBUG_TXPOWER
1011 ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1012 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1013 IWL_DEBUG_TXPOWER
1014 ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1015 m1->pa_det, m2->pa_det, omeas->pa_det);
1016 IWL_DEBUG_TXPOWER
1017 ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
1018 m1->temperature, m2->temperature,
1019 omeas->temperature);
1020 }
1021 }
1022
1023 return 0;
1024}
1025
1026/* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1027 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1028static s32 back_off_table[] = {
1029 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1030 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1031 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1032 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1033 10 /* CCK */
1034};
1035
1036/* Thermal compensation values for txpower for various frequency ranges ...
1037 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
bb8c093b 1038static struct iwl4965_txpower_comp_entry {
b481de9c
ZY		 1039 s32 degrees_per_05db_a;
1040 s32 degrees_per_05db_a_denom;
1041} tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1042 {9, 2}, /* group 0 5.2, ch 34-43 */
1043 {4, 1}, /* group 1 5.2, ch 44-70 */
1044 {4, 1}, /* group 2 5.2, ch 71-124 */
1045 {4, 1}, /* group 3 5.2, ch 125-200 */
1046 {3, 1} /* group 4 2.4, ch all */
1047};
1048
1049static s32 get_min_power_index(s32 rate_power_index, u32 band)
1050{
1051 if (!band) {
1052 if ((rate_power_index & 7) <= 4)
1053 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1054 }
1055 return MIN_TX_GAIN_INDEX;
1056}
1057
1058struct gain_entry {
1059 u8 dsp;
1060 u8 radio;
1061};
1062
1063static const struct gain_entry gain_table[2][108] = {
1064 /* 5.2GHz power gain index table */
1065 {
1066 {123, 0x3F}, /* highest txpower */
1067 {117, 0x3F},
1068 {110, 0x3F},
1069 {104, 0x3F},
1070 {98, 0x3F},
1071 {110, 0x3E},
1072 {104, 0x3E},
1073 {98, 0x3E},
1074 {110, 0x3D},
1075 {104, 0x3D},
1076 {98, 0x3D},
1077 {110, 0x3C},
1078 {104, 0x3C},
1079 {98, 0x3C},
1080 {110, 0x3B},
1081 {104, 0x3B},
1082 {98, 0x3B},
1083 {110, 0x3A},
1084 {104, 0x3A},
1085 {98, 0x3A},
1086 {110, 0x39},
1087 {104, 0x39},
1088 {98, 0x39},
1089 {110, 0x38},
1090 {104, 0x38},
1091 {98, 0x38},
1092 {110, 0x37},
1093 {104, 0x37},
1094 {98, 0x37},
1095 {110, 0x36},
1096 {104, 0x36},
1097 {98, 0x36},
1098 {110, 0x35},
1099 {104, 0x35},
1100 {98, 0x35},
1101 {110, 0x34},
1102 {104, 0x34},
1103 {98, 0x34},
1104 {110, 0x33},
1105 {104, 0x33},
1106 {98, 0x33},
1107 {110, 0x32},
1108 {104, 0x32},
1109 {98, 0x32},
1110 {110, 0x31},
1111 {104, 0x31},
1112 {98, 0x31},
1113 {110, 0x30},
1114 {104, 0x30},
1115 {98, 0x30},
1116 {110, 0x25},
1117 {104, 0x25},
1118 {98, 0x25},
1119 {110, 0x24},
1120 {104, 0x24},
1121 {98, 0x24},
1122 {110, 0x23},
1123 {104, 0x23},
1124 {98, 0x23},
1125 {110, 0x22},
1126 {104, 0x18},
1127 {98, 0x18},
1128 {110, 0x17},
1129 {104, 0x17},
1130 {98, 0x17},
1131 {110, 0x16},
1132 {104, 0x16},
1133 {98, 0x16},
1134 {110, 0x15},
1135 {104, 0x15},
1136 {98, 0x15},
1137 {110, 0x14},
1138 {104, 0x14},
1139 {98, 0x14},
1140 {110, 0x13},
1141 {104, 0x13},
1142 {98, 0x13},
1143 {110, 0x12},
1144 {104, 0x08},
1145 {98, 0x08},
1146 {110, 0x07},
1147 {104, 0x07},
1148 {98, 0x07},
1149 {110, 0x06},
1150 {104, 0x06},
1151 {98, 0x06},
1152 {110, 0x05},
1153 {104, 0x05},
1154 {98, 0x05},
1155 {110, 0x04},
1156 {104, 0x04},
1157 {98, 0x04},
1158 {110, 0x03},
1159 {104, 0x03},
1160 {98, 0x03},
1161 {110, 0x02},
1162 {104, 0x02},
1163 {98, 0x02},
1164 {110, 0x01},
1165 {104, 0x01},
1166 {98, 0x01},
1167 {110, 0x00},
1168 {104, 0x00},
1169 {98, 0x00},
1170 {93, 0x00},
1171 {88, 0x00},
1172 {83, 0x00},
1173 {78, 0x00},
1174 },
1175 /* 2.4GHz power gain index table */
1176 {
1177 {110, 0x3f}, /* highest txpower */
1178 {104, 0x3f},
1179 {98, 0x3f},
1180 {110, 0x3e},
1181 {104, 0x3e},
1182 {98, 0x3e},
1183 {110, 0x3d},
1184 {104, 0x3d},
1185 {98, 0x3d},
1186 {110, 0x3c},
1187 {104, 0x3c},
1188 {98, 0x3c},
1189 {110, 0x3b},
1190 {104, 0x3b},
1191 {98, 0x3b},
1192 {110, 0x3a},
1193 {104, 0x3a},
1194 {98, 0x3a},
1195 {110, 0x39},
1196 {104, 0x39},
1197 {98, 0x39},
1198 {110, 0x38},
1199 {104, 0x38},
1200 {98, 0x38},
1201 {110, 0x37},
1202 {104, 0x37},
1203 {98, 0x37},
1204 {110, 0x36},
1205 {104, 0x36},
1206 {98, 0x36},
1207 {110, 0x35},
1208 {104, 0x35},
1209 {98, 0x35},
1210 {110, 0x34},
1211 {104, 0x34},
1212 {98, 0x34},
1213 {110, 0x33},
1214 {104, 0x33},
1215 {98, 0x33},
1216 {110, 0x32},
1217 {104, 0x32},
1218 {98, 0x32},
1219 {110, 0x31},
1220 {104, 0x31},
1221 {98, 0x31},
1222 {110, 0x30},
1223 {104, 0x30},
1224 {98, 0x30},
1225 {110, 0x6},
1226 {104, 0x6},
1227 {98, 0x6},
1228 {110, 0x5},
1229 {104, 0x5},
1230 {98, 0x5},
1231 {110, 0x4},
1232 {104, 0x4},
1233 {98, 0x4},
1234 {110, 0x3},
1235 {104, 0x3},
1236 {98, 0x3},
1237 {110, 0x2},
1238 {104, 0x2},
1239 {98, 0x2},
1240 {110, 0x1},
1241 {104, 0x1},
1242 {98, 0x1},
1243 {110, 0x0},
1244 {104, 0x0},
1245 {98, 0x0},
1246 {97, 0},
1247 {96, 0},
1248 {95, 0},
1249 {94, 0},
1250 {93, 0},
1251 {92, 0},
1252 {91, 0},
1253 {90, 0},
1254 {89, 0},
1255 {88, 0},
1256 {87, 0},
1257 {86, 0},
1258 {85, 0},
1259 {84, 0},
1260 {83, 0},
1261 {82, 0},
1262 {81, 0},
1263 {80, 0},
1264 {79, 0},
1265 {78, 0},
1266 {77, 0},
1267 {76, 0},
1268 {75, 0},
1269 {74, 0},
1270 {73, 0},
1271 {72, 0},
1272 {71, 0},
1273 {70, 0},
1274 {69, 0},
1275 {68, 0},
1276 {67, 0},
1277 {66, 0},
1278 {65, 0},
1279 {64, 0},
1280 {63, 0},
1281 {62, 0},
1282 {61, 0},
1283 {60, 0},
1284 {59, 0},
1285 }
1286};
1287
c79dd5b5 1288static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
b481de9c 1289 u8 is_fat, u8 ctrl_chan_high,
bb8c093b 1290 struct iwl4965_tx_power_db *tx_power_tbl)
b481de9c
ZY		 1291{
1292 u8 saturation_power;
1293 s32 target_power;
1294 s32 user_target_power;
1295 s32 power_limit;
1296 s32 current_temp;
1297 s32 reg_limit;
1298 s32 current_regulatory;
1299 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1300 int i;
1301 int c;
bf85ea4f 1302 const struct iwl_channel_info *ch_info = NULL;
073d3f5f
TW		 1303 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1304 const struct iwl_eeprom_calib_measure *measurement;
b481de9c
ZY		 1305 s16 voltage;
1306 s32 init_voltage;
1307 s32 voltage_compensation;
1308 s32 degrees_per_05db_num;
1309 s32 degrees_per_05db_denom;
1310 s32 factory_temp;
1311 s32 temperature_comp[2];
1312 s32 factory_gain_index[2];
1313 s32 factory_actual_pwr[2];
1314 s32 power_index;
1315
b481de9c
ZY		 1316 /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1317 * are used for indexing into txpower table) */
630fe9b6 1318 user_target_power = 2 * priv->tx_power_user_lmt;
b481de9c
ZY		 1319
1320 /* Get current (RXON) channel, band, width */
b481de9c
ZY		 1321 IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1322 is_fat);
1323
630fe9b6
TW		 1324 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1325
1326 if (!is_channel_valid(ch_info))
b481de9c
ZY		 1327 return -EINVAL;
1328
1329 /* get txatten group, used to select 1) thermal txpower adjustment
1330 * and 2) mimo txpower balance between Tx chains. */
1331 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1332 if (txatten_grp < 0)
1333 return -EINVAL;
1334
1335 IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1336 channel, txatten_grp);
1337
1338 if (is_fat) {
1339 if (ctrl_chan_high)
1340 channel -= 2;
1341 else
1342 channel += 2;
1343 }
1344
1345 /* hardware txpower limits ...
1346 * saturation (clipping distortion) txpowers are in half-dBm */
1347 if (band)
073d3f5f 1348 saturation_power = priv->calib_info->saturation_power24;
b481de9c 1349 else
073d3f5f 1350 saturation_power = priv->calib_info->saturation_power52;
b481de9c
ZY		 1351
1352 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1353 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1354 if (band)
1355 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1356 else
1357 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1358 }
1359
1360 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1361 * max_power_avg values are in dBm, convert * 2 */
1362 if (is_fat)
1363 reg_limit = ch_info->fat_max_power_avg * 2;
1364 else
1365 reg_limit = ch_info->max_power_avg * 2;
1366
1367 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1368 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1369 if (band)
1370 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1371 else
1372 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1373 }
1374
1375 /* Interpolate txpower calibration values for this channel,
1376 * based on factory calibration tests on spaced channels. */
1377 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1378
1379 /* calculate tx gain adjustment based on power supply voltage */
073d3f5f 1380 voltage = priv->calib_info->voltage;
b481de9c
ZY		 1381 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1382 voltage_compensation =
1383 iwl4965_get_voltage_compensation(voltage, init_voltage);
1384
1385 IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
1386 init_voltage,
1387 voltage, voltage_compensation);
1388
1389 /* get current temperature (Celsius) */
1390 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1391 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1392 current_temp = KELVIN_TO_CELSIUS(current_temp);
1393
1394 /* select thermal txpower adjustment params, based on channel group
1395 * (same frequency group used for mimo txatten adjustment) */
1396 degrees_per_05db_num =
1397 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1398 degrees_per_05db_denom =
1399 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1400
1401 /* get per-chain txpower values from factory measurements */
1402 for (c = 0; c < 2; c++) {
1403 measurement = &ch_eeprom_info.measurements[c][1];
1404
1405 /* txgain adjustment (in half-dB steps) based on difference
1406 * between factory and current temperature */
1407 factory_temp = measurement->temperature;
1408 iwl4965_math_div_round((current_temp - factory_temp) *
1409 degrees_per_05db_denom,
1410 degrees_per_05db_num,
1411 &temperature_comp[c]);
1412
1413 factory_gain_index[c] = measurement->gain_idx;
1414 factory_actual_pwr[c] = measurement->actual_pow;
1415
1416 IWL_DEBUG_TXPOWER("chain = %d\n", c);
1417 IWL_DEBUG_TXPOWER("fctry tmp %d, "
1418 "curr tmp %d, comp %d steps\n",
1419 factory_temp, current_temp,
1420 temperature_comp[c]);
1421
1422 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
1423 factory_gain_index[c],
1424 factory_actual_pwr[c]);
1425 }
1426
1427 /* for each of 33 bit-rates (including 1 for CCK) */
1428 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1429 u8 is_mimo_rate;
bb8c093b 1430 union iwl4965_tx_power_dual_stream tx_power;
b481de9c
ZY		 1431
1432 /* for mimo, reduce each chain's txpower by half
1433 * (3dB, 6 steps), so total output power is regulatory
1434 * compliant. */
1435 if (i & 0x8) {
1436 current_regulatory = reg_limit -
1437 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1438 is_mimo_rate = 1;
1439 } else {
1440 current_regulatory = reg_limit;
1441 is_mimo_rate = 0;
1442 }
1443
1444 /* find txpower limit, either hardware or regulatory */
1445 power_limit = saturation_power - back_off_table[i];
1446 if (power_limit > current_regulatory)
1447 power_limit = current_regulatory;
1448
1449 /* reduce user's txpower request if necessary
1450 * for this rate on this channel */
1451 target_power = user_target_power;
1452 if (target_power > power_limit)
1453 target_power = power_limit;
1454
1455 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
1456 i, saturation_power - back_off_table[i],
1457 current_regulatory, user_target_power,
1458 target_power);
1459
1460 /* for each of 2 Tx chains (radio transmitters) */
1461 for (c = 0; c < 2; c++) {
1462 s32 atten_value;
1463
1464 if (is_mimo_rate)
1465 atten_value =
1466 (s32)le32_to_cpu(priv->card_alive_init.
1467 tx_atten[txatten_grp][c]);
1468 else
1469 atten_value = 0;
1470
1471 /* calculate index; higher index means lower txpower */
1472 power_index = (u8) (factory_gain_index[c] -
1473 (target_power -
1474 factory_actual_pwr[c]) -
1475 temperature_comp[c] -
1476 voltage_compensation +
1477 atten_value);
1478
1479/* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
1480 power_index); */
1481
1482 if (power_index < get_min_power_index(i, band))
1483 power_index = get_min_power_index(i, band);
1484
1485 /* adjust 5 GHz index to support negative indexes */
1486 if (!band)
1487 power_index += 9;
1488
1489 /* CCK, rate 32, reduce txpower for CCK */
1490 if (i == POWER_TABLE_CCK_ENTRY)
1491 power_index +=
1492 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1493
1494 /* stay within the table! */
1495 if (power_index > 107) {
1496 IWL_WARNING("txpower index %d > 107\n",
1497 power_index);
1498 power_index = 107;
1499 }
1500 if (power_index < 0) {
1501 IWL_WARNING("txpower index %d < 0\n",
1502 power_index);
1503 power_index = 0;
1504 }
1505
1506 /* fill txpower command for this rate/chain */
1507 tx_power.s.radio_tx_gain[c] =
1508 gain_table[band][power_index].radio;
1509 tx_power.s.dsp_predis_atten[c] =
1510 gain_table[band][power_index].dsp;
1511
1512 IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
1513 "gain 0x%02x dsp %d\n",
1514 c, atten_value, power_index,
1515 tx_power.s.radio_tx_gain[c],
1516 tx_power.s.dsp_predis_atten[c]);
3ac7f146 1517 } /* for each chain */
b481de9c
ZY		 1518
1519 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1520
3ac7f146 1521 } /* for each rate */
b481de9c
ZY		 1522
1523 return 0;
1524}
1525
1526/**
630fe9b6 1527 * iwl4965_send_tx_power - Configure the TXPOWER level user limit
b481de9c
ZY		 1528 *
1529 * Uses the active RXON for channel, band, and characteristics (fat, high)
630fe9b6 1530 * The power limit is taken from priv->tx_power_user_lmt.
b481de9c 1531 */
630fe9b6 1532static int iwl4965_send_tx_power(struct iwl_priv *priv)
b481de9c 1533{
bb8c093b 1534 struct iwl4965_txpowertable_cmd cmd = { 0 };
857485c0 1535 int ret;
b481de9c
ZY		 1536 u8 band = 0;
1537 u8 is_fat = 0;
1538 u8 ctrl_chan_high = 0;
1539
1540 if (test_bit(STATUS_SCANNING, &priv->status)) {
1541 /* If this gets hit a lot, switch it to a BUG() and catch
1542 * the stack trace to find out who is calling this during
1543 * a scan. */
1544 IWL_WARNING("TX Power requested while scanning!\n");
1545 return -EAGAIN;
1546 }
1547
8318d78a 1548 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c
ZY		 1549
1550 is_fat = is_fat_channel(priv->active_rxon.flags);
1551
1552 if (is_fat &&
1553 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1554 ctrl_chan_high = 1;
1555
1556 cmd.band = band;
1557 cmd.channel = priv->active_rxon.channel;
1558
857485c0 1559 ret = iwl4965_fill_txpower_tbl(priv, band,
b481de9c
ZY		 1560 le16_to_cpu(priv->active_rxon.channel),
1561 is_fat, ctrl_chan_high, &cmd.tx_power);
857485c0
TW		 1562 if (ret)
1563 goto out;
b481de9c 1564
857485c0
TW		 1565 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1566
1567out:
1568 return ret;
b481de9c
ZY		 1569}
1570
7e8c519e
TW		 1571static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
1572{
1573 int ret = 0;
1574 struct iwl4965_rxon_assoc_cmd rxon_assoc;
c1adf9fb
GG		 1575 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1576 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
7e8c519e
TW		 1577
1578 if ((rxon1->flags == rxon2->flags) &&
1579 (rxon1->filter_flags == rxon2->filter_flags) &&
1580 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1581 (rxon1->ofdm_ht_single_stream_basic_rates ==
1582 rxon2->ofdm_ht_single_stream_basic_rates) &&
1583 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1584 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1585 (rxon1->rx_chain == rxon2->rx_chain) &&
1586 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1587 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1588 return 0;
1589 }
1590
1591 rxon_assoc.flags = priv->staging_rxon.flags;
1592 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1593 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1594 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1595 rxon_assoc.reserved = 0;
1596 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1597 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1598 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1599 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1600 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1601
1602 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1603 sizeof(rxon_assoc), &rxon_assoc, NULL);
1604 if (ret)
1605 return ret;
1606
1607 return ret;
1608}
1609
1610
c79dd5b5 1611int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1612{
1613 int rc;
1614 u8 band = 0;
1615 u8 is_fat = 0;
1616 u8 ctrl_chan_high = 0;
bb8c093b 1617 struct iwl4965_channel_switch_cmd cmd = { 0 };
bf85ea4f 1618 const struct iwl_channel_info *ch_info;
b481de9c 1619
8318d78a 1620 band = priv->band == IEEE80211_BAND_2GHZ;
b481de9c 1621
8622e705 1622 ch_info = iwl_get_channel_info(priv, priv->band, channel);
b481de9c
ZY		 1623
1624 is_fat = is_fat_channel(priv->staging_rxon.flags);
1625
1626 if (is_fat &&
1627 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1628 ctrl_chan_high = 1;
1629
1630 cmd.band = band;
1631 cmd.expect_beacon = 0;
1632 cmd.channel = cpu_to_le16(channel);
1633 cmd.rxon_flags = priv->active_rxon.flags;
1634 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
1635 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1636 if (ch_info)
1637 cmd.expect_beacon = is_channel_radar(ch_info);
1638 else
1639 cmd.expect_beacon = 1;
1640
1641 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
1642 ctrl_chan_high, &cmd.tx_power);
1643 if (rc) {
1644 IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
1645 return rc;
1646 }
1647
857485c0 1648 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
b481de9c
ZY		 1649 return rc;
1650}
1651
d67f5489 1652static int iwl4965_shared_mem_rx_idx(struct iwl_priv *priv)
b481de9c 1653{
059ff826
TW		 1654 struct iwl4965_shared *s = priv->shared_virt;
1655 return le32_to_cpu(s->rb_closed) & 0xFFF;
b481de9c
ZY		 1656}
1657
399f4900
RR		 1658static int iwl4965_alloc_shared_mem(struct iwl_priv *priv)
1659{
1660 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
1661 sizeof(struct iwl4965_shared),
1662 &priv->shared_phys);
1663 if (!priv->shared_virt)
1664 return -ENOMEM;
1665
1666 memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
1667
d67f5489
RR		 1668 priv->rb_closed_offset = offsetof(struct iwl4965_shared, rb_closed);
1669
399f4900
RR		 1670 return 0;
1671}
1672
1673static void iwl4965_free_shared_mem(struct iwl_priv *priv)
1674{
1675 if (priv->shared_virt)
1676 pci_free_consistent(priv->pci_dev,
1677 sizeof(struct iwl4965_shared),
1678 priv->shared_virt,
1679 priv->shared_phys);
1680}
1681
8b6eaea8 1682/**
e2a722eb 1683 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
8b6eaea8 1684 */
e2a722eb 1685static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 1686 struct iwl_tx_queue *txq,
e2a722eb 1687 u16 byte_cnt)
b481de9c
ZY		 1688{
1689 int len;
1690 int txq_id = txq->q.id;
059ff826 1691 struct iwl4965_shared *shared_data = priv->shared_virt;
b481de9c 1692
b481de9c
ZY		 1693 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1694
8b6eaea8 1695 /* Set up byte count within first 256 entries */
b481de9c 1696 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
fc4b6853 1697 tfd_offset[txq->q.write_ptr], byte_cnt, len);
b481de9c 1698
8b6eaea8 1699 /* If within first 64 entries, duplicate at end */
038669e4 1700 if (txq->q.write_ptr < IWL49_MAX_WIN_SIZE)
b481de9c 1701 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
038669e4 1702 tfd_offset[IWL49_QUEUE_SIZE + txq->q.write_ptr],
b481de9c 1703 byte_cnt, len);
b481de9c
ZY		 1704}
1705
b481de9c
ZY		 1706/**
1707 * sign_extend - Sign extend a value using specified bit as sign-bit
1708 *
1709 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1710 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1711 *
1712 * @param oper value to sign extend
1713 * @param index 0 based bit index (0<=index<32) to sign bit
1714 */
1715static s32 sign_extend(u32 oper, int index)
1716{
1717 u8 shift = 31 - index;
1718
1719 return (s32)(oper << shift) >> shift;
1720}
1721
1722/**
91dbc5bd 1723 * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
b481de9c
ZY		 1724 * @statistics: Provides the temperature reading from the uCode
1725 *
1726 * A return of <0 indicates bogus data in the statistics
1727 */
91dbc5bd 1728static int iwl4965_hw_get_temperature(const struct iwl_priv *priv)
b481de9c
ZY		 1729{
1730 s32 temperature;
1731 s32 vt;
1732 s32 R1, R2, R3;
1733 u32 R4;
1734
1735 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1736 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
1737 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
1738 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1739 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1740 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1741 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1742 } else {
1743 IWL_DEBUG_TEMP("Running temperature calibration\n");
1744 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1745 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1746 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1747 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
1748 }
1749
1750 /*
8b6eaea8 1751 * Temperature is only 23 bits, so sign extend out to 32.
b481de9c
ZY		 1752 *
1753 * NOTE If we haven't received a statistics notification yet
1754 * with an updated temperature, use R4 provided to us in the
8b6eaea8
CB		 1755 * "initialize" ALIVE response.
1756 */
b481de9c
ZY		 1757 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
1758 vt = sign_extend(R4, 23);
1759 else
1760 vt = sign_extend(
1761 le32_to_cpu(priv->statistics.general.temperature), 23);
1762
91dbc5bd 1763 IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
b481de9c
ZY		 1764
1765 if (R3 == R1) {
1766 IWL_ERROR("Calibration conflict R1 == R3\n");
1767 return -1;
1768 }
1769
1770 /* Calculate temperature in degrees Kelvin, adjust by 97%.
1771 * Add offset to center the adjustment around 0 degrees Centigrade. */
1772 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
1773 temperature /= (R3 - R1);
91dbc5bd 1774 temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
b481de9c 1775
91dbc5bd
EG		 1776 IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n",
1777 temperature, KELVIN_TO_CELSIUS(temperature));
b481de9c
ZY		 1778
1779 return temperature;
1780}
1781
1782/* Adjust Txpower only if temperature variance is greater than threshold. */
1783#define IWL_TEMPERATURE_THRESHOLD 3
1784
1785/**
1786 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
1787 *
1788 * If the temperature changed has changed sufficiently, then a recalibration
1789 * is needed.
1790 *
1791 * Assumes caller will replace priv->last_temperature once calibration
1792 * executed.
1793 */
c79dd5b5 1794static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1795{
1796 int temp_diff;
1797
1798 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
1799 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
1800 return 0;
1801 }
1802
1803 temp_diff = priv->temperature - priv->last_temperature;
1804
1805 /* get absolute value */
1806 if (temp_diff < 0) {
1807 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
1808 temp_diff = -temp_diff;
1809 } else if (temp_diff == 0)
1810 IWL_DEBUG_POWER("Same temp, \n");
1811 else
1812 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
1813
1814 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
1815 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
1816 return 0;
1817 }
1818
1819 IWL_DEBUG_POWER("Thermal txpower calib needed\n");
1820
1821 return 1;
1822}
1823
5225640b 1824static void iwl4965_temperature_calib(struct iwl_priv *priv)
b481de9c 1825{
b481de9c 1826 s32 temp;
b481de9c 1827
91dbc5bd 1828 temp = iwl4965_hw_get_temperature(priv);
b481de9c
ZY		 1829 if (temp < 0)
1830 return;
1831
1832 if (priv->temperature != temp) {
1833 if (priv->temperature)
1834 IWL_DEBUG_TEMP("Temperature changed "
1835 "from %dC to %dC\n",
1836 KELVIN_TO_CELSIUS(priv->temperature),
1837 KELVIN_TO_CELSIUS(temp));
1838 else
1839 IWL_DEBUG_TEMP("Temperature "
1840 "initialized to %dC\n",
1841 KELVIN_TO_CELSIUS(temp));
1842 }
1843
1844 priv->temperature = temp;
1845 set_bit(STATUS_TEMPERATURE, &priv->status);
1846
203566f3
EG		 1847 if (!priv->disable_tx_power_cal &&
1848 unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
1849 iwl4965_is_temp_calib_needed(priv))
b481de9c
ZY		 1850 queue_work(priv->workqueue, &priv->txpower_work);
1851}
1852
fe01b477
RR		 1853/**
1854 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
1855 */
c79dd5b5 1856static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
fe01b477
RR		 1857 u16 txq_id)
1858{
1859 /* Simply stop the queue, but don't change any configuration;
1860 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3395f6e9 1861 iwl_write_prph(priv,
12a81f60 1862 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
038669e4
EG		 1863 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1864 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
fe01b477 1865}
b481de9c 1866
fe01b477 1867/**
7f3e4bb6 1868 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
b095d03a 1869 * priv->lock must be held by the caller
fe01b477 1870 */
30e553e3
TW		 1871static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1872 u16 ssn_idx, u8 tx_fifo)
fe01b477 1873{
b095d03a
RR		 1874 int ret = 0;
1875
9f17b318
TW		 1876 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1877 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
1878 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1879 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1880 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
fe01b477 1881 return -EINVAL;
b481de9c
ZY		 1882 }
1883
3395f6e9 1884 ret = iwl_grab_nic_access(priv);
b095d03a
RR		 1885 if (ret)
1886 return ret;
1887
fe01b477
RR		 1888 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1889
12a81f60 1890 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
fe01b477
RR		 1891
1892 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1893 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1894 /* supposes that ssn_idx is valid (!= 0xFFF) */
1895 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1896
12a81f60 1897 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
36470749 1898 iwl_txq_ctx_deactivate(priv, txq_id);
fe01b477
RR		 1899 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1900
3395f6e9 1901 iwl_release_nic_access(priv);
b095d03a 1902
fe01b477
RR		 1903 return 0;
1904}
b481de9c 1905
8b6eaea8
CB		 1906/**
1907 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
1908 */
c79dd5b5 1909static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
b481de9c
ZY		 1910 u16 txq_id)
1911{
1912 u32 tbl_dw_addr;
1913 u32 tbl_dw;
1914 u16 scd_q2ratid;
1915
30e553e3 1916 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
b481de9c
ZY		 1917
1918 tbl_dw_addr = priv->scd_base_addr +
038669e4 1919 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
b481de9c 1920
3395f6e9 1921 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
b481de9c
ZY		 1922
1923 if (txq_id & 0x1)
1924 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1925 else
1926 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1927
3395f6e9 1928 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
b481de9c
ZY		 1929
1930 return 0;
1931}
1932
fe01b477 1933
b481de9c 1934/**
8b6eaea8
CB		 1935 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
1936 *
7f3e4bb6 1937 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
8b6eaea8 1938 * i.e. it must be one of the higher queues used for aggregation
b481de9c 1939 */
30e553e3
TW		 1940static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1941 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
b481de9c
ZY		 1942{
1943 unsigned long flags;
30e553e3 1944 int ret;
b481de9c
ZY		 1945 u16 ra_tid;
1946
9f17b318
TW		 1947 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1948 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
1949 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1950 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1951 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
1952 return -EINVAL;
1953 }
b481de9c
ZY		 1954
1955 ra_tid = BUILD_RAxTID(sta_id, tid);
1956
8b6eaea8 1957 /* Modify device's station table to Tx this TID */
5083e563 1958 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
b481de9c
ZY		 1959
1960 spin_lock_irqsave(&priv->lock, flags);
30e553e3
TW		 1961 ret = iwl_grab_nic_access(priv);
1962 if (ret) {
b481de9c 1963 spin_unlock_irqrestore(&priv->lock, flags);
30e553e3 1964 return ret;
b481de9c
ZY		 1965 }
1966
8b6eaea8 1967 /* Stop this Tx queue before configuring it */
b481de9c
ZY		 1968 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1969
8b6eaea8 1970 /* Map receiver-address / traffic-ID to this queue */
b481de9c
ZY		 1971 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1972
8b6eaea8 1973 /* Set this queue as a chain-building queue */
12a81f60 1974 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
b481de9c 1975
8b6eaea8
CB		 1976 /* Place first TFD at index corresponding to start sequence number.
1977 * Assumes that ssn_idx is valid (!= 0xFFF) */
fc4b6853
TW		 1978 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1979 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
b481de9c
ZY		 1980 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1981
8b6eaea8 1982 /* Set up Tx window size and frame limit for this queue */
3395f6e9 1983 iwl_write_targ_mem(priv,
038669e4
EG		 1984 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
1985 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1986 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
b481de9c 1987
3395f6e9 1988 iwl_write_targ_mem(priv, priv->scd_base_addr +
038669e4
EG		 1989 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1990 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
1991 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
b481de9c 1992
12a81f60 1993 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
b481de9c 1994
8b6eaea8 1995 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
b481de9c
ZY		 1996 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1997
3395f6e9 1998 iwl_release_nic_access(priv);
b481de9c
ZY		 1999 spin_unlock_irqrestore(&priv->lock, flags);
2000
2001 return 0;
2002}
2003
133636de 2004
c1adf9fb
GG		 2005static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
2006{
2007 switch (cmd_id) {
2008 case REPLY_RXON:
2009 return (u16) sizeof(struct iwl4965_rxon_cmd);
2010 default:
2011 return len;
2012 }
2013}
2014
133636de
TW		 2015static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2016{
2017 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
2018 addsta->mode = cmd->mode;
2019 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2020 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2021 addsta->station_flags = cmd->station_flags;
2022 addsta->station_flags_msk = cmd->station_flags_msk;
2023 addsta->tid_disable_tx = cmd->tid_disable_tx;
2024 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2025 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2026 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2027 addsta->reserved1 = __constant_cpu_to_le16(0);
2028 addsta->reserved2 = __constant_cpu_to_le32(0);
2029
2030 return (u16)sizeof(struct iwl4965_addsta_cmd);
2031}
f20217d9 2032
f20217d9
TW		 2033static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
2034{
25a6572c 2035 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
f20217d9
TW		 2036}
2037
2038/**
2039 * iwl4965_tx_status_reply_tx - Handle Tx rspnse for frames in aggregation queue
2040 */
2041static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
2042 struct iwl_ht_agg *agg,
25a6572c
TW		 2043 struct iwl4965_tx_resp *tx_resp,
2044 int txq_id, u16 start_idx)
f20217d9
TW		 2045{
2046 u16 status;
25a6572c 2047 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
f20217d9
TW		 2048 struct ieee80211_tx_info *info = NULL;
2049 struct ieee80211_hdr *hdr = NULL;
e7d326ac 2050 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 2051 int i, sh, idx;
f20217d9 2052 u16 seq;
f20217d9
TW		 2053 if (agg->wait_for_ba)
2054 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
2055
2056 agg->frame_count = tx_resp->frame_count;
2057 agg->start_idx = start_idx;
e7d326ac 2058 agg->rate_n_flags = rate_n_flags;
f20217d9
TW		 2059 agg->bitmap = 0;
2060
2061 /* # frames attempted by Tx command */
2062 if (agg->frame_count == 1) {
2063 /* Only one frame was attempted; no block-ack will arrive */
2064 status = le16_to_cpu(frame_status[0].status);
25a6572c 2065 idx = start_idx;
f20217d9
TW		 2066
2067 /* FIXME: code repetition */
2068 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
2069 agg->frame_count, agg->start_idx, idx);
2070
2071 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
2072 info->status.retry_count = tx_resp->failure_frame;
2073 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
2074 info->flags |= iwl_is_tx_success(status)?
2075 IEEE80211_TX_STAT_ACK : 0;
e7d326ac 2076 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
f20217d9
TW		 2077 /* FIXME: code repetition end */
2078
2079 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
2080 status & 0xff, tx_resp->failure_frame);
e7d326ac 2081 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
f20217d9
TW		 2082
2083 agg->wait_for_ba = 0;
2084 } else {
2085 /* Two or more frames were attempted; expect block-ack */
2086 u64 bitmap = 0;
2087 int start = agg->start_idx;
2088
2089 /* Construct bit-map of pending frames within Tx window */
2090 for (i = 0; i < agg->frame_count; i++) {
2091 u16 sc;
2092 status = le16_to_cpu(frame_status[i].status);
2093 seq = le16_to_cpu(frame_status[i].sequence);
2094 idx = SEQ_TO_INDEX(seq);
2095 txq_id = SEQ_TO_QUEUE(seq);
2096
2097 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
2098 AGG_TX_STATE_ABORT_MSK))
2099 continue;
2100
2101 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
2102 agg->frame_count, txq_id, idx);
2103
2104 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
2105
2106 sc = le16_to_cpu(hdr->seq_ctrl);
2107 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
2108 IWL_ERROR("BUG_ON idx doesn't match seq control"
2109 " idx=%d, seq_idx=%d, seq=%d\n",
2110 idx, SEQ_TO_SN(sc),
2111 hdr->seq_ctrl);
2112 return -1;
2113 }
2114
2115 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
2116 i, idx, SEQ_TO_SN(sc));
2117
2118 sh = idx - start;
2119 if (sh > 64) {
2120 sh = (start - idx) + 0xff;
2121 bitmap = bitmap << sh;
2122 sh = 0;
2123 start = idx;
2124 } else if (sh < -64)
2125 sh = 0xff - (start - idx);
2126 else if (sh < 0) {
2127 sh = start - idx;
2128 start = idx;
2129 bitmap = bitmap << sh;
2130 sh = 0;
2131 }
4aa41f12
EG		 2132 bitmap |= 1ULL << sh;
2133 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
2134 start, (unsigned long long)bitmap);
f20217d9
TW		 2135 }
2136
2137 agg->bitmap = bitmap;
2138 agg->start_idx = start;
f20217d9
TW		 2139 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
2140 agg->frame_count, agg->start_idx,
2141 (unsigned long long)agg->bitmap);
2142
2143 if (bitmap)
2144 agg->wait_for_ba = 1;
2145 }
2146 return 0;
2147}
f20217d9
TW		 2148
2149/**
2150 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
2151 */
2152static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
2153 struct iwl_rx_mem_buffer *rxb)
2154{
2155 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2156 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2157 int txq_id = SEQ_TO_QUEUE(sequence);
2158 int index = SEQ_TO_INDEX(sequence);
2159 struct iwl_tx_queue *txq = &priv->txq[txq_id];
2160 struct ieee80211_tx_info *info;
2161 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
25a6572c 2162 u32 status = le32_to_cpu(tx_resp->u.status);
f20217d9 2163 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
fd7c8a40 2164 __le16 fc;
f20217d9
TW		 2165 struct ieee80211_hdr *hdr;
2166 u8 *qc = NULL;
f20217d9
TW		 2167
2168 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
2169 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
2170 "is out of range [0-%d] %d %d\n", txq_id,
2171 index, txq->q.n_bd, txq->q.write_ptr,
2172 txq->q.read_ptr);
2173 return;
2174 }
2175
2176 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
2177 memset(&info->status, 0, sizeof(info->status));
2178
f20217d9 2179 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
fd7c8a40
HH		 2180 fc = hdr->frame_control;
2181 if (ieee80211_is_data_qos(fc)) {
2182 qc = ieee80211_get_qos_ctl(hdr);
f20217d9
TW		 2183 tid = qc[0] & 0xf;
2184 }
2185
2186 sta_id = iwl_get_ra_sta_id(priv, hdr);
2187 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
2188 IWL_ERROR("Station not known\n");
2189 return;
2190 }
2191
2192 if (txq->sched_retry) {
2193 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
2194 struct iwl_ht_agg *agg = NULL;
2195
2196 if (!qc)
2197 return;
2198
2199 agg = &priv->stations[sta_id].tid[tid].agg;
2200
25a6572c 2201 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
f20217d9 2202
3235427e
RR		 2203 /* check if BAR is needed */
2204 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
2205 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
f20217d9
TW		 2206
2207 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2208 int freed, ampdu_q;
2209 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2210 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
2211 "%d index %d\n", scd_ssn , index);
17b88929 2212 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
f20217d9
TW		 2213 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2214
2215 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
2216 txq_id >= 0 && priv->mac80211_registered &&
2217 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
2218 /* calculate mac80211 ampdu sw queue to wake */
7f3e4bb6 2219 ampdu_q = txq_id - IWL49_FIRST_AMPDU_QUEUE +
f20217d9
TW		 2220 priv->hw->queues;
2221 if (agg->state == IWL_AGG_OFF)
2222 ieee80211_wake_queue(priv->hw, txq_id);
2223 else
2224 ieee80211_wake_queue(priv->hw, ampdu_q);
2225 }
30e553e3 2226 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
f20217d9
TW		 2227 }
2228 } else {
4f85f5b3
RR		 2229 info->status.retry_count = tx_resp->failure_frame;
2230 info->flags |=
2231 iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
e7d326ac 2232 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 2233 le32_to_cpu(tx_resp->rate_n_flags),
2234 info);
2235
2236 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
2237 "0x%x retries %d\n", txq_id,
2238 iwl_get_tx_fail_reason(status),
2239 status, le32_to_cpu(tx_resp->rate_n_flags),
2240 tx_resp->failure_frame);
2241
2242 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
e7d326ac 2243
4f85f5b3
RR		 2244 if (index != -1) {
2245 int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
2246 if (tid != MAX_TID_COUNT)
f20217d9 2247 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
4f85f5b3 2248 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
f20217d9
TW		 2249 (txq_id >= 0) && priv->mac80211_registered)
2250 ieee80211_wake_queue(priv->hw, txq_id);
4f85f5b3 2251 if (tid != MAX_TID_COUNT)
30e553e3 2252 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
4f85f5b3 2253 }
f20217d9 2254 }
f20217d9
TW		 2255
2256 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
2257 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
2258}
2259
caab8f1a
TW		 2260static int iwl4965_calc_rssi(struct iwl_priv *priv,
2261 struct iwl_rx_phy_res *rx_resp)
2262{
2263 /* data from PHY/DSP regarding signal strength, etc.,
2264 * contents are always there, not configurable by host. */
2265 struct iwl4965_rx_non_cfg_phy *ncphy =
2266 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
2267 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK)
2268 >> IWL49_AGC_DB_POS;
2269
2270 u32 valid_antennae =
2271 (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK)
2272 >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
2273 u8 max_rssi = 0;
2274 u32 i;
2275
2276 /* Find max rssi among 3 possible receivers.
2277 * These values are measured by the digital signal processor (DSP).
2278 * They should stay fairly constant even as the signal strength varies,
2279 * if the radio's automatic gain control (AGC) is working right.
2280 * AGC value (see below) will provide the "interesting" info. */
2281 for (i = 0; i < 3; i++)
2282 if (valid_antennae & (1 << i))
2283 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2284
2285 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2286 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2287 max_rssi, agc);
2288
2289 /* dBm = max_rssi dB - agc dB - constant.
2290 * Higher AGC (higher radio gain) means lower signal. */
2291 return max_rssi - agc - IWL_RSSI_OFFSET;
2292}
2293
f20217d9 2294
b481de9c 2295/* Set up 4965-specific Rx frame reply handlers */
d4789efe 2296static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
b481de9c
ZY		 2297{
2298 /* Legacy Rx frames */
1781a07f 2299 priv->rx_handlers[REPLY_RX] = iwl_rx_reply_rx;
37a44211 2300 /* Tx response */
f20217d9 2301 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
b481de9c
ZY		 2302}
2303
4e39317d 2304static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2305{
2306 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
b481de9c
ZY		 2307}
2308
4e39317d 2309static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2310{
4e39317d 2311 cancel_work_sync(&priv->txpower_work);
b481de9c
ZY		 2312}
2313
3c424c28
TW		 2314
2315static struct iwl_hcmd_ops iwl4965_hcmd = {
7e8c519e 2316 .rxon_assoc = iwl4965_send_rxon_assoc,
3c424c28
TW		 2317};
2318
857485c0 2319static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
c1adf9fb 2320 .get_hcmd_size = iwl4965_get_hcmd_size,
133636de 2321 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
f0832f13
EG		 2322 .chain_noise_reset = iwl4965_chain_noise_reset,
2323 .gain_computation = iwl4965_gain_computation,
a326a5d0 2324 .rts_tx_cmd_flag = iwl4965_rts_tx_cmd_flag,
caab8f1a 2325 .calc_rssi = iwl4965_calc_rssi,
857485c0
TW		 2326};
2327
6bc913bd 2328static struct iwl_lib_ops iwl4965_lib = {
5425e490 2329 .set_hw_params = iwl4965_hw_set_hw_params,
399f4900
RR		 2330 .alloc_shared_mem = iwl4965_alloc_shared_mem,
2331 .free_shared_mem = iwl4965_free_shared_mem,
d67f5489 2332 .shared_mem_rx_idx = iwl4965_shared_mem_rx_idx,
e2a722eb 2333 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
da1bc453 2334 .txq_set_sched = iwl4965_txq_set_sched,
30e553e3
TW		 2335 .txq_agg_enable = iwl4965_txq_agg_enable,
2336 .txq_agg_disable = iwl4965_txq_agg_disable,
d4789efe 2337 .rx_handler_setup = iwl4965_rx_handler_setup,
4e39317d
EG		 2338 .setup_deferred_work = iwl4965_setup_deferred_work,
2339 .cancel_deferred_work = iwl4965_cancel_deferred_work,
57aab75a
TW		 2340 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
2341 .alive_notify = iwl4965_alive_notify,
f3ccc08c 2342 .init_alive_start = iwl4965_init_alive_start,
57aab75a 2343 .load_ucode = iwl4965_load_bsm,
6f4083aa 2344 .apm_ops = {
91238714 2345 .init = iwl4965_apm_init,
7f066108 2346 .reset = iwl4965_apm_reset,
f118a91d 2347 .stop = iwl4965_apm_stop,
694cc56d 2348 .config = iwl4965_nic_config,
6f4083aa
TW		 2349 .set_pwr_src = iwl4965_set_pwr_src,
2350 },
6bc913bd 2351 .eeprom_ops = {
073d3f5f
TW		 2352 .regulatory_bands = {
2353 EEPROM_REGULATORY_BAND_1_CHANNELS,
2354 EEPROM_REGULATORY_BAND_2_CHANNELS,
2355 EEPROM_REGULATORY_BAND_3_CHANNELS,
2356 EEPROM_REGULATORY_BAND_4_CHANNELS,
2357 EEPROM_REGULATORY_BAND_5_CHANNELS,
2358 EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
2359 EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
2360 },
6bc913bd
AK		 2361 .verify_signature = iwlcore_eeprom_verify_signature,
2362 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
2363 .release_semaphore = iwlcore_eeprom_release_semaphore,
8614f360 2364 .check_version = iwl4965_eeprom_check_version,
073d3f5f 2365 .query_addr = iwlcore_eeprom_query_addr,
6bc913bd 2366 },
630fe9b6 2367 .send_tx_power = iwl4965_send_tx_power,
5da4b55f 2368 .update_chain_flags = iwl4965_update_chain_flags,
8f91aecb 2369 .temperature = iwl4965_temperature_calib,
6bc913bd
AK		 2370};
2371
2372static struct iwl_ops iwl4965_ops = {
2373 .lib = &iwl4965_lib,
3c424c28 2374 .hcmd = &iwl4965_hcmd,
857485c0 2375 .utils = &iwl4965_hcmd_utils,
6bc913bd
AK		 2376};
2377
fed9017e 2378struct iwl_cfg iwl4965_agn_cfg = {
82b9a121 2379 .name = "4965AGN",
4bf775cd 2380 .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
82b9a121 2381 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
073d3f5f 2382 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
6bc913bd 2383 .ops = &iwl4965_ops,
1ea87396 2384 .mod_params = &iwl4965_mod_params,
82b9a121
TW		 2385};
2386
d16dc48a
TW		 2387/* Module firmware */
2388MODULE_FIRMWARE("iwlwifi-4965" IWL4965_UCODE_API ".ucode");
2389
1ea87396
AK		 2390module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
2391MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
2392module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
2393MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
fcc76c6b 2394module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
61a2d07d 2395MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
1ea87396
AK		 2396module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
2397MODULE_PARM_DESC(debug, "debug output mask");
2398module_param_named(
2399 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
2400MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
2401
2402module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
2403MODULE_PARM_DESC(queues_num, "number of hw queues.");
1ea87396
AK		 2404/* QoS */
2405module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
2406MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
49779293
RR		 2407/* 11n */
2408module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, 0444);
2409MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
1ea87396
AK		 2410module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
2411MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
49779293 2412
3a1081e8
EK		 2413module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
2414MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");
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