projects / deliverable / linux.git / blame
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| b481de9c ZY |
1 | /****************************************************************************** |
| 2 | * | |
| 3 | * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved. | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or modify it | |
| 6 | * under the terms of version 2 of the GNU General Public License as | |
| 7 | * published by the Free Software Foundation. | |
| 8 | * | |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 12 | * more details. | |
| 13 | * | |
| 14 | * You should have received a copy of the GNU General Public License along with | |
| 15 | * this program; if not, write to the Free Software Foundation, Inc., | |
| 16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
| 17 | * | |
| 18 | * The full GNU General Public License is included in this distribution in the | |
| 19 | * file called LICENSE. | |
| 20 | * | |
| 21 | * Contact Information: | |
| 22 | * James P. Ketrenos <ipw2100-admin@linux.intel.com> | |
| 23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
| 24 | * | |
| 25 | *****************************************************************************/ | |
| 26 | #ifndef __iwl_4965_h__ | |
| 27 | #define __iwl_4965_h__ | |
| 28 | ||
| 29 | struct iwl_priv; | |
| 30 | struct sta_ht_info; | |
| 31 | ||
| 32 | /* | |
| 33 | * Forward declare iwl-4965.c functions for iwl-base.c | |
| 34 | */ | |
| 91e17473 | 35 | extern int iwl_eeprom_acquire_semaphore(struct iwl_priv *priv); |
| b481de9c ZY |
36 | extern void iwl_eeprom_release_semaphore(struct iwl_priv *priv); |
| 37 | ||
| 38 | extern int iwl4965_tx_queue_update_wr_ptr(struct iwl_priv *priv, | |
| 39 | struct iwl_tx_queue *txq, | |
| 40 | u16 byte_cnt); | |
| 41 | extern void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, | |
| 42 | int is_ap); | |
| 43 | extern void iwl4965_set_rxon_ht(struct iwl_priv *priv, | |
| 44 | struct sta_ht_info *ht_info); | |
| 45 | ||
| 46 | extern void iwl4965_set_rxon_chain(struct iwl_priv *priv); | |
| 47 | extern int iwl4965_tx_cmd(struct iwl_priv *priv, struct iwl_cmd *out_cmd, | |
| 48 | u8 sta_id, dma_addr_t txcmd_phys, | |
| 49 | struct ieee80211_hdr *hdr, u8 hdr_len, | |
| 50 | struct ieee80211_tx_control *ctrl, void *sta_in); | |
| 51 | extern int iwl4965_init_hw_rates(struct iwl_priv *priv, | |
| 52 | struct ieee80211_rate *rates); | |
| 53 | extern int iwl4965_alive_notify(struct iwl_priv *priv); | |
| 54 | extern void iwl4965_update_rate_scaling(struct iwl_priv *priv, u8 mode); | |
| 55 | extern void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index); | |
| 56 | ||
| 57 | extern void iwl4965_chain_noise_reset(struct iwl_priv *priv); | |
| 58 | extern void iwl4965_init_sensitivity(struct iwl_priv *priv, u8 flags, | |
| 59 | u8 force); | |
| 60 | extern int iwl4965_set_fat_chan_info(struct iwl_priv *priv, int phymode, | |
| 61 | u16 channel, | |
| 62 | const struct iwl_eeprom_channel *eeprom_ch, | |
| 63 | u8 fat_extension_channel); | |
| 64 | extern void iwl4965_rf_kill_ct_config(struct iwl_priv *priv); | |
| 65 | ||
| 66 | #ifdef CONFIG_IWLWIFI_HT | |
| 67 | #ifdef CONFIG_IWLWIFI_HT_AGG | |
| 68 | extern int iwl_mac_ht_tx_agg_start(struct ieee80211_hw *hw, u8 *da, | |
| 69 | u16 tid, u16 *start_seq_num); | |
| 70 | extern int iwl_mac_ht_rx_agg_start(struct ieee80211_hw *hw, u8 *da, | |
| 71 | u16 tid, u16 start_seq_num); | |
| 72 | extern int iwl_mac_ht_rx_agg_stop(struct ieee80211_hw *hw, u8 *da, | |
| 73 | u16 tid, int generator); | |
| 74 | extern int iwl_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, u8 *da, | |
| 75 | u16 tid, int generator); | |
| 76 | extern void iwl4965_turn_off_agg(struct iwl_priv *priv, u8 tid); | |
| 77 | #endif /* CONFIG_IWLWIFI_HT_AGG */ | |
| 78 | #endif /*CONFIG_IWLWIFI_HT */ | |
| 79 | /* Structures, enum, and defines specific to the 4965 */ | |
| 80 | ||
| 81 | #define IWL4965_KW_SIZE 0x1000 /*4k */ | |
| 82 | ||
| 83 | struct iwl_kw { | |
| 84 | dma_addr_t dma_addr; | |
| 85 | void *v_addr; | |
| 86 | size_t size; | |
| 87 | }; | |
| 88 | ||
| 89 | #define TID_QUEUE_CELL_SPACING 50 /*mS */ | |
| 90 | #define TID_QUEUE_MAX_SIZE 20 | |
| 91 | #define TID_ROUND_VALUE 5 /* mS */ | |
| 92 | #define TID_MAX_LOAD_COUNT 8 | |
| 93 | ||
| 94 | #define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING) | |
| 95 | #define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y)) | |
| 96 | ||
| 97 | #define TID_ALL_ENABLED 0x7f | |
| 98 | #define TID_ALL_SPECIFIED 0xff | |
| 99 | #define TID_AGG_TPT_THREHOLD 0x0 | |
| 100 | ||
| 101 | #define IWL_CHANNEL_WIDTH_20MHZ 0 | |
| 102 | #define IWL_CHANNEL_WIDTH_40MHZ 1 | |
| 103 | ||
| 104 | #define IWL_MIMO_PS_STATIC 0 | |
| 105 | #define IWL_MIMO_PS_NONE 3 | |
| 106 | #define IWL_MIMO_PS_DYNAMIC 1 | |
| 107 | #define IWL_MIMO_PS_INVALID 2 | |
| 108 | ||
| 109 | #define IWL_OPERATION_MODE_AUTO 0 | |
| 110 | #define IWL_OPERATION_MODE_HT_ONLY 1 | |
| 111 | #define IWL_OPERATION_MODE_MIXED 2 | |
| 112 | #define IWL_OPERATION_MODE_20MHZ 3 | |
| 113 | ||
| 114 | #define IWL_EXT_CHANNEL_OFFSET_AUTO 0 | |
| 115 | #define IWL_EXT_CHANNEL_OFFSET_ABOVE 1 | |
| 116 | #define IWL_EXT_CHANNEL_OFFSET_ 2 | |
| 117 | #define IWL_EXT_CHANNEL_OFFSET_BELOW 3 | |
| 118 | #define IWL_EXT_CHANNEL_OFFSET_MAX 4 | |
| 119 | ||
| 120 | #define NRG_NUM_PREV_STAT_L 20 | |
| 121 | #define NUM_RX_CHAINS (3) | |
| 122 | ||
| 123 | #define TX_POWER_IWL_ILLEGAL_VDET -100000 | |
| 124 | #define TX_POWER_IWL_ILLEGAL_VOLTAGE -10000 | |
| 125 | #define TX_POWER_IWL_CLOSED_LOOP_MIN_POWER 18 | |
| 126 | #define TX_POWER_IWL_CLOSED_LOOP_MAX_POWER 34 | |
| 127 | #define TX_POWER_IWL_VDET_SLOPE_BELOW_NOMINAL 17 | |
| 128 | #define TX_POWER_IWL_VDET_SLOPE_ABOVE_NOMINAL 20 | |
| 129 | #define TX_POWER_IWL_NOMINAL_POWER 26 | |
| 130 | #define TX_POWER_IWL_CLOSED_LOOP_ITERATION_LIMIT 1 | |
| 131 | #define TX_POWER_IWL_VOLTAGE_CODES_PER_03V 7 | |
| 132 | #define TX_POWER_IWL_DEGREES_PER_VDET_CODE 11 | |
| 133 | #define IWL_TX_POWER_MAX_NUM_PA_MEASUREMENTS 1 | |
| 134 | #define IWL_TX_POWER_CCK_COMPENSATION_B_STEP (9) | |
| 135 | #define IWL_TX_POWER_CCK_COMPENSATION_C_STEP (5) | |
| 136 | ||
| 137 | struct iwl_traffic_load { | |
| 138 | unsigned long time_stamp; | |
| 139 | u32 packet_count[TID_QUEUE_MAX_SIZE]; | |
| 140 | u8 queue_count; | |
| 141 | u8 head; | |
| 142 | u32 total; | |
| 143 | }; | |
| 144 | ||
| 145 | #ifdef CONFIG_IWLWIFI_HT_AGG | |
| 146 | struct iwl_agg_control { | |
| 147 | unsigned long next_retry; | |
| 148 | u32 wait_for_agg_status; | |
| 149 | u32 tid_retry; | |
| 150 | u32 requested_ba; | |
| 151 | u32 granted_ba; | |
| 152 | u8 auto_agg; | |
| 153 | u32 tid_traffic_load_threshold; | |
| 154 | u32 ba_timeout; | |
| 155 | struct iwl_traffic_load traffic_load[TID_MAX_LOAD_COUNT]; | |
| 156 | }; | |
| 157 | #endif /*CONFIG_IWLWIFI_HT_AGG */ | |
| 158 | ||
| 159 | struct iwl_lq_mngr { | |
| 160 | #ifdef CONFIG_IWLWIFI_HT_AGG | |
| 161 | struct iwl_agg_control agg_ctrl; | |
| 162 | #endif | |
| 163 | spinlock_t lock; | |
| 164 | s32 max_window_size; | |
| 165 | s32 *expected_tpt; | |
| 166 | u8 *next_higher_rate; | |
| 167 | u8 *next_lower_rate; | |
| 168 | unsigned long stamp; | |
| 169 | unsigned long stamp_last; | |
| 170 | u32 flush_time; | |
| 171 | u32 tx_packets; | |
| 172 | u8 lq_ready; | |
| 173 | }; | |
| 174 | ||
| 175 | ||
| 176 | /* Sensitivity and chain noise calibration */ | |
| 177 | #define INTERFERENCE_DATA_AVAILABLE __constant_cpu_to_le32(1) | |
| 178 | #define INITIALIZATION_VALUE 0xFFFF | |
| 179 | #define CAL_NUM_OF_BEACONS 20 | |
| 180 | #define MAXIMUM_ALLOWED_PATHLOSS 15 | |
| 181 | ||
| 182 | /* Param table within SENSITIVITY_CMD */ | |
| 183 | #define HD_MIN_ENERGY_CCK_DET_INDEX (0) | |
| 184 | #define HD_MIN_ENERGY_OFDM_DET_INDEX (1) | |
| 185 | #define HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX (2) | |
| 186 | #define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX (3) | |
| 187 | #define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX (4) | |
| 188 | #define HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX (5) | |
| 189 | #define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX (6) | |
| 190 | #define HD_BARKER_CORR_TH_ADD_MIN_INDEX (7) | |
| 191 | #define HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX (8) | |
| 192 | #define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX (9) | |
| 193 | #define HD_OFDM_ENERGY_TH_IN_INDEX (10) | |
| 194 | ||
| 195 | #define SENSITIVITY_CMD_CONTROL_DEFAULT_TABLE __constant_cpu_to_le16(0) | |
| 196 | #define SENSITIVITY_CMD_CONTROL_WORK_TABLE __constant_cpu_to_le16(1) | |
| 197 | ||
| 198 | #define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3 | |
| 199 | ||
| 200 | #define MAX_FA_OFDM 50 | |
| 201 | #define MIN_FA_OFDM 5 | |
| 202 | #define MAX_FA_CCK 50 | |
| 203 | #define MIN_FA_CCK 5 | |
| 204 | ||
| 205 | #define NRG_MIN_CCK 97 | |
| 206 | #define NRG_MAX_CCK 0 | |
| 207 | ||
| 208 | #define AUTO_CORR_MIN_OFDM 85 | |
| 209 | #define AUTO_CORR_MIN_OFDM_MRC 170 | |
| 210 | #define AUTO_CORR_MIN_OFDM_X1 105 | |
| 211 | #define AUTO_CORR_MIN_OFDM_MRC_X1 220 | |
| 212 | #define AUTO_CORR_MAX_OFDM 120 | |
| 213 | #define AUTO_CORR_MAX_OFDM_MRC 210 | |
| 214 | #define AUTO_CORR_MAX_OFDM_X1 140 | |
| 215 | #define AUTO_CORR_MAX_OFDM_MRC_X1 270 | |
| 216 | #define AUTO_CORR_STEP_OFDM 1 | |
| 217 | ||
| 218 | #define AUTO_CORR_MIN_CCK (125) | |
| 219 | #define AUTO_CORR_MAX_CCK (200) | |
| 220 | #define AUTO_CORR_MIN_CCK_MRC 200 | |
| 221 | #define AUTO_CORR_MAX_CCK_MRC 400 | |
| 222 | #define AUTO_CORR_STEP_CCK 3 | |
| 223 | #define AUTO_CORR_MAX_TH_CCK 160 | |
| 224 | ||
| 225 | #define NRG_ALG 0 | |
| 226 | #define AUTO_CORR_ALG 1 | |
| 227 | #define NRG_DIFF 2 | |
| 228 | #define NRG_STEP_CCK 2 | |
| 229 | #define NRG_MARGIN 8 | |
| 230 | #define MAX_NUMBER_CCK_NO_FA 100 | |
| 231 | ||
| 232 | #define AUTO_CORR_CCK_MIN_VAL_DEF (125) | |
| 233 | ||
| 234 | #define CHAIN_A 0 | |
| 235 | #define CHAIN_B 1 | |
| 236 | #define CHAIN_C 2 | |
| 237 | #define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4 | |
| 238 | #define ALL_BAND_FILTER 0xFF00 | |
| 239 | #define IN_BAND_FILTER 0xFF | |
| 240 | #define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF | |
| 241 | ||
| 242 | enum iwl_false_alarm_state { | |
| 243 | IWL_FA_TOO_MANY = 0, | |
| 244 | IWL_FA_TOO_FEW = 1, | |
| 245 | IWL_FA_GOOD_RANGE = 2, | |
| 246 | }; | |
| 247 | ||
| 248 | enum iwl_chain_noise_state { | |
| 249 | IWL_CHAIN_NOISE_ALIVE = 0, /* must be 0 */ | |
| 250 | IWL_CHAIN_NOISE_ACCUMULATE = 1, | |
| 251 | IWL_CHAIN_NOISE_CALIBRATED = 2, | |
| 252 | }; | |
| 253 | ||
| 254 | enum iwl_sensitivity_state { | |
| 255 | IWL_SENS_CALIB_ALLOWED = 0, | |
| 256 | IWL_SENS_CALIB_NEED_REINIT = 1, | |
| 257 | }; | |
| 258 | ||
| 259 | enum iwl_calib_enabled_state { | |
| 260 | IWL_CALIB_DISABLED = 0, /* must be 0 */ | |
| 261 | IWL_CALIB_ENABLED = 1, | |
| 262 | }; | |
| 263 | ||
| 264 | struct statistics_general_data { | |
| 265 | u32 beacon_silence_rssi_a; | |
| 266 | u32 beacon_silence_rssi_b; | |
| 267 | u32 beacon_silence_rssi_c; | |
| 268 | u32 beacon_energy_a; | |
| 269 | u32 beacon_energy_b; | |
| 270 | u32 beacon_energy_c; | |
| 271 | }; | |
| 272 | ||
| 273 | /* Sensitivity calib data */ | |
| 274 | struct iwl_sensitivity_data { | |
| 275 | u32 auto_corr_ofdm; | |
| 276 | u32 auto_corr_ofdm_mrc; | |
| 277 | u32 auto_corr_ofdm_x1; | |
| 278 | u32 auto_corr_ofdm_mrc_x1; | |
| 279 | u32 auto_corr_cck; | |
| 280 | u32 auto_corr_cck_mrc; | |
| 281 | ||
| 282 | u32 last_bad_plcp_cnt_ofdm; | |
| 283 | u32 last_fa_cnt_ofdm; | |
| 284 | u32 last_bad_plcp_cnt_cck; | |
| 285 | u32 last_fa_cnt_cck; | |
| 286 | ||
| 287 | u32 nrg_curr_state; | |
| 288 | u32 nrg_prev_state; | |
| 289 | u32 nrg_value[10]; | |
| 290 | u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L]; | |
| 291 | u32 nrg_silence_ref; | |
| 292 | u32 nrg_energy_idx; | |
| 293 | u32 nrg_silence_idx; | |
| 294 | u32 nrg_th_cck; | |
| 295 | s32 nrg_auto_corr_silence_diff; | |
| 296 | u32 num_in_cck_no_fa; | |
| 297 | u32 nrg_th_ofdm; | |
| 298 | ||
| 299 | u8 state; | |
| 300 | }; | |
| 301 | ||
| 302 | /* Chain noise (differential Rx gain) calib data */ | |
| 303 | struct iwl_chain_noise_data { | |
| 304 | u8 state; | |
| 305 | u16 beacon_count; | |
| 306 | u32 chain_noise_a; | |
| 307 | u32 chain_noise_b; | |
| 308 | u32 chain_noise_c; | |
| 309 | u32 chain_signal_a; | |
| 310 | u32 chain_signal_b; | |
| 311 | u32 chain_signal_c; | |
| 312 | u8 disconn_array[NUM_RX_CHAINS]; | |
| 313 | u8 delta_gain_code[NUM_RX_CHAINS]; | |
| 314 | u8 radio_write; | |
| 315 | }; | |
| 316 | ||
| 317 | /* IWL4965 */ | |
| 318 | #define RATE_MCS_CODE_MSK 0x7 | |
| 319 | #define RATE_MCS_MIMO_POS 3 | |
| 320 | #define RATE_MCS_MIMO_MSK 0x8 | |
| 321 | #define RATE_MCS_HT_DUP_POS 5 | |
| 322 | #define RATE_MCS_HT_DUP_MSK 0x20 | |
| 323 | #define RATE_MCS_FLAGS_POS 8 | |
| 324 | #define RATE_MCS_HT_POS 8 | |
| 325 | #define RATE_MCS_HT_MSK 0x100 | |
| 326 | #define RATE_MCS_CCK_POS 9 | |
| 327 | #define RATE_MCS_CCK_MSK 0x200 | |
| 328 | #define RATE_MCS_GF_POS 10 | |
| 329 | #define RATE_MCS_GF_MSK 0x400 | |
| 330 | ||
| 331 | #define RATE_MCS_FAT_POS 11 | |
| 332 | #define RATE_MCS_FAT_MSK 0x800 | |
| 333 | #define RATE_MCS_DUP_POS 12 | |
| 334 | #define RATE_MCS_DUP_MSK 0x1000 | |
| 335 | #define RATE_MCS_SGI_POS 13 | |
| 336 | #define RATE_MCS_SGI_MSK 0x2000 | |
| 337 | ||
| 338 | #define EEPROM_SEM_TIMEOUT 10 | |
| 339 | #define EEPROM_SEM_RETRY_LIMIT 1000 | |
| 340 | ||
| 341 | #endif /* __iwl_4965_h__ */ |