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5a6a256e TW |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. |
5a6a256e TW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
23 | * | |
24 | *****************************************************************************/ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
5a6a256e TW |
28 | #include <linux/init.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/skbuff.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/wireless.h> | |
35 | #include <net/mac80211.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <asm/unaligned.h> | |
38 | ||
39 | #include "iwl-eeprom.h" | |
3e0d4cb1 | 40 | #include "iwl-dev.h" |
5a6a256e TW |
41 | #include "iwl-core.h" |
42 | #include "iwl-io.h" | |
e26e47d9 | 43 | #include "iwl-sta.h" |
5a6a256e | 44 | #include "iwl-helpers.h" |
e932a609 | 45 | #include "iwl-agn-led.h" |
5a6a256e | 46 | #include "iwl-5000-hw.h" |
c0bac76a | 47 | #include "iwl-6000-hw.h" |
5a6a256e | 48 | |
a0987a8d | 49 | /* Highest firmware API version supported */ |
c9d2fbf3 | 50 | #define IWL5000_UCODE_API_MAX 2 |
39e6d225 | 51 | #define IWL5150_UCODE_API_MAX 2 |
5a6a256e | 52 | |
a0987a8d RC |
53 | /* Lowest firmware API version supported */ |
54 | #define IWL5000_UCODE_API_MIN 1 | |
55 | #define IWL5150_UCODE_API_MIN 1 | |
56 | ||
57 | #define IWL5000_FW_PRE "iwlwifi-5000-" | |
58 | #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode" | |
59 | #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api) | |
60 | ||
61 | #define IWL5150_FW_PRE "iwlwifi-5150-" | |
62 | #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode" | |
63 | #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api) | |
4e062f99 | 64 | |
99da1b48 RR |
65 | static const u16 iwl5000_default_queue_to_tx_fifo[] = { |
66 | IWL_TX_FIFO_AC3, | |
67 | IWL_TX_FIFO_AC2, | |
68 | IWL_TX_FIFO_AC1, | |
69 | IWL_TX_FIFO_AC0, | |
70 | IWL50_CMD_FIFO_NUM, | |
71 | IWL_TX_FIFO_HCCA_1, | |
72 | IWL_TX_FIFO_HCCA_2 | |
73 | }; | |
74 | ||
9371d4ed | 75 | /* NIC configuration for 5000 series */ |
672639de | 76 | void iwl5000_nic_config(struct iwl_priv *priv) |
e86fe9f6 TW |
77 | { |
78 | unsigned long flags; | |
79 | u16 radio_cfg; | |
e86fe9f6 TW |
80 | |
81 | spin_lock_irqsave(&priv->lock, flags); | |
82 | ||
e86fe9f6 TW |
83 | radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); |
84 | ||
85 | /* write radio config values to register */ | |
9371d4ed | 86 | if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX) |
e86fe9f6 TW |
87 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
88 | EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | | |
89 | EEPROM_RF_CFG_STEP_MSK(radio_cfg) | | |
90 | EEPROM_RF_CFG_DASH_MSK(radio_cfg)); | |
91 | ||
92 | /* set CSR_HW_CONFIG_REG for uCode use */ | |
93 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
94 | CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | | |
95 | CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); | |
96 | ||
4c43e0d0 TW |
97 | /* W/A : NIC is stuck in a reset state after Early PCIe power off |
98 | * (PCIe power is lost before PERST# is asserted), | |
99 | * causing ME FW to lose ownership and not being able to obtain it back. | |
100 | */ | |
2d3db679 | 101 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
4c43e0d0 TW |
102 | APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, |
103 | ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); | |
104 | ||
02c06e4a | 105 | |
e86fe9f6 TW |
106 | spin_unlock_irqrestore(&priv->lock, flags); |
107 | } | |
108 | ||
109 | ||
25ae3986 TW |
110 | /* |
111 | * EEPROM | |
112 | */ | |
113 | static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) | |
114 | { | |
115 | u16 offset = 0; | |
116 | ||
117 | if ((address & INDIRECT_ADDRESS) == 0) | |
118 | return address; | |
119 | ||
120 | switch (address & INDIRECT_TYPE_MSK) { | |
121 | case INDIRECT_HOST: | |
122 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); | |
123 | break; | |
124 | case INDIRECT_GENERAL: | |
125 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); | |
126 | break; | |
127 | case INDIRECT_REGULATORY: | |
128 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); | |
129 | break; | |
130 | case INDIRECT_CALIBRATION: | |
131 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); | |
132 | break; | |
133 | case INDIRECT_PROCESS_ADJST: | |
134 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); | |
135 | break; | |
136 | case INDIRECT_OTHERS: | |
137 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); | |
138 | break; | |
139 | default: | |
15b1687c | 140 | IWL_ERR(priv, "illegal indirect type: 0x%X\n", |
25ae3986 TW |
141 | address & INDIRECT_TYPE_MSK); |
142 | break; | |
143 | } | |
144 | ||
145 | /* translate the offset from words to byte */ | |
146 | return (address & ADDRESS_MSK) + (offset << 1); | |
147 | } | |
148 | ||
672639de | 149 | u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv) |
f1f69415 | 150 | { |
f1f69415 TW |
151 | struct iwl_eeprom_calib_hdr { |
152 | u8 version; | |
153 | u8 pa_type; | |
154 | u16 voltage; | |
155 | } *hdr; | |
156 | ||
f1f69415 TW |
157 | hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, |
158 | EEPROM_5000_CALIB_ALL); | |
0ef2ca67 | 159 | return hdr->version; |
f1f69415 TW |
160 | |
161 | } | |
162 | ||
33fd5033 EG |
163 | static void iwl5000_gain_computation(struct iwl_priv *priv, |
164 | u32 average_noise[NUM_RX_CHAINS], | |
165 | u16 min_average_noise_antenna_i, | |
d8c07e7a WYG |
166 | u32 min_average_noise, |
167 | u8 default_chain) | |
33fd5033 EG |
168 | { |
169 | int i; | |
170 | s32 delta_g; | |
171 | struct iwl_chain_noise_data *data = &priv->chain_noise_data; | |
172 | ||
d8c07e7a WYG |
173 | /* |
174 | * Find Gain Code for the chains based on "default chain" | |
175 | */ | |
176 | for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) { | |
33fd5033 EG |
177 | if ((data->disconn_array[i])) { |
178 | data->delta_gain_code[i] = 0; | |
179 | continue; | |
180 | } | |
065e63b0 | 181 | delta_g = (1000 * ((s32)average_noise[default_chain] - |
33fd5033 EG |
182 | (s32)average_noise[i])) / 1500; |
183 | /* bound gain by 2 bits value max, 3rd bit is sign */ | |
184 | data->delta_gain_code[i] = | |
886e71de | 185 | min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE); |
33fd5033 EG |
186 | |
187 | if (delta_g < 0) | |
188 | /* set negative sign */ | |
189 | data->delta_gain_code[i] |= (1 << 2); | |
190 | } | |
191 | ||
e1623446 | 192 | IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n", |
33fd5033 EG |
193 | data->delta_gain_code[1], data->delta_gain_code[2]); |
194 | ||
195 | if (!data->radio_write) { | |
f69f42a6 | 196 | struct iwl_calib_chain_noise_gain_cmd cmd; |
0d950d84 | 197 | |
33fd5033 EG |
198 | memset(&cmd, 0, sizeof(cmd)); |
199 | ||
0d950d84 TW |
200 | cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; |
201 | cmd.hdr.first_group = 0; | |
202 | cmd.hdr.groups_num = 1; | |
203 | cmd.hdr.data_valid = 1; | |
33fd5033 EG |
204 | cmd.delta_gain_1 = data->delta_gain_code[1]; |
205 | cmd.delta_gain_2 = data->delta_gain_code[2]; | |
206 | iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, | |
207 | sizeof(cmd), &cmd, NULL); | |
208 | ||
209 | data->radio_write = 1; | |
210 | data->state = IWL_CHAIN_NOISE_CALIBRATED; | |
211 | } | |
212 | ||
213 | data->chain_noise_a = 0; | |
214 | data->chain_noise_b = 0; | |
215 | data->chain_noise_c = 0; | |
216 | data->chain_signal_a = 0; | |
217 | data->chain_signal_b = 0; | |
218 | data->chain_signal_c = 0; | |
219 | data->beacon_count = 0; | |
220 | } | |
221 | ||
222 | static void iwl5000_chain_noise_reset(struct iwl_priv *priv) | |
223 | { | |
224 | struct iwl_chain_noise_data *data = &priv->chain_noise_data; | |
0d950d84 | 225 | int ret; |
33fd5033 EG |
226 | |
227 | if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { | |
f69f42a6 | 228 | struct iwl_calib_chain_noise_reset_cmd cmd; |
33fd5033 | 229 | memset(&cmd, 0, sizeof(cmd)); |
0d950d84 TW |
230 | |
231 | cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; | |
232 | cmd.hdr.first_group = 0; | |
233 | cmd.hdr.groups_num = 1; | |
234 | cmd.hdr.data_valid = 1; | |
235 | ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, | |
236 | sizeof(cmd), &cmd); | |
237 | if (ret) | |
15b1687c WT |
238 | IWL_ERR(priv, |
239 | "Could not send REPLY_PHY_CALIBRATION_CMD\n"); | |
33fd5033 | 240 | data->state = IWL_CHAIN_NOISE_ACCUMULATE; |
e1623446 | 241 | IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n"); |
33fd5033 EG |
242 | } |
243 | } | |
244 | ||
e8c00dcb | 245 | void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, |
a326a5d0 EG |
246 | __le32 *tx_flags) |
247 | { | |
e6a9854b JB |
248 | if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || |
249 | (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) | |
a326a5d0 EG |
250 | *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK; |
251 | else | |
252 | *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK; | |
253 | } | |
254 | ||
33fd5033 EG |
255 | static struct iwl_sensitivity_ranges iwl5000_sensitivity = { |
256 | .min_nrg_cck = 95, | |
fe6efb4b | 257 | .max_nrg_cck = 0, /* not used, set to 0 */ |
33fd5033 EG |
258 | .auto_corr_min_ofdm = 90, |
259 | .auto_corr_min_ofdm_mrc = 170, | |
260 | .auto_corr_min_ofdm_x1 = 120, | |
261 | .auto_corr_min_ofdm_mrc_x1 = 240, | |
262 | ||
263 | .auto_corr_max_ofdm = 120, | |
264 | .auto_corr_max_ofdm_mrc = 210, | |
265 | .auto_corr_max_ofdm_x1 = 155, | |
266 | .auto_corr_max_ofdm_mrc_x1 = 290, | |
267 | ||
268 | .auto_corr_min_cck = 125, | |
269 | .auto_corr_max_cck = 200, | |
270 | .auto_corr_min_cck_mrc = 170, | |
271 | .auto_corr_max_cck_mrc = 400, | |
272 | .nrg_th_cck = 95, | |
273 | .nrg_th_ofdm = 95, | |
55036d66 WYG |
274 | |
275 | .barker_corr_th_min = 190, | |
276 | .barker_corr_th_min_mrc = 390, | |
277 | .nrg_th_cca = 62, | |
33fd5033 EG |
278 | }; |
279 | ||
9d67187d WYG |
280 | static struct iwl_sensitivity_ranges iwl5150_sensitivity = { |
281 | .min_nrg_cck = 95, | |
282 | .max_nrg_cck = 0, /* not used, set to 0 */ | |
283 | .auto_corr_min_ofdm = 90, | |
284 | .auto_corr_min_ofdm_mrc = 170, | |
285 | .auto_corr_min_ofdm_x1 = 105, | |
286 | .auto_corr_min_ofdm_mrc_x1 = 220, | |
287 | ||
288 | .auto_corr_max_ofdm = 120, | |
289 | .auto_corr_max_ofdm_mrc = 210, | |
290 | /* max = min for performance bug in 5150 DSP */ | |
291 | .auto_corr_max_ofdm_x1 = 105, | |
292 | .auto_corr_max_ofdm_mrc_x1 = 220, | |
293 | ||
294 | .auto_corr_min_cck = 125, | |
295 | .auto_corr_max_cck = 200, | |
296 | .auto_corr_min_cck_mrc = 170, | |
297 | .auto_corr_max_cck_mrc = 400, | |
298 | .nrg_th_cck = 95, | |
299 | .nrg_th_ofdm = 95, | |
55036d66 WYG |
300 | |
301 | .barker_corr_th_min = 190, | |
302 | .barker_corr_th_min_mrc = 390, | |
303 | .nrg_th_cca = 62, | |
9d67187d WYG |
304 | }; |
305 | ||
672639de | 306 | const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, |
25ae3986 TW |
307 | size_t offset) |
308 | { | |
309 | u32 address = eeprom_indirect_address(priv, offset); | |
310 | BUG_ON(address >= priv->cfg->eeprom_size); | |
311 | return &priv->eeprom[address]; | |
312 | } | |
313 | ||
62161aef | 314 | static void iwl5150_set_ct_threshold(struct iwl_priv *priv) |
339afc89 | 315 | { |
62161aef | 316 | const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF; |
672639de | 317 | s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) - |
62161aef WYG |
318 | iwl_temp_calib_to_offset(priv); |
319 | ||
320 | priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef; | |
321 | } | |
322 | ||
323 | static void iwl5000_set_ct_threshold(struct iwl_priv *priv) | |
324 | { | |
325 | /* want Celsius */ | |
672639de | 326 | priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY; |
339afc89 TW |
327 | } |
328 | ||
7c616cba TW |
329 | /* |
330 | * Calibration | |
331 | */ | |
be5d56ed | 332 | static int iwl5000_set_Xtal_calib(struct iwl_priv *priv) |
7c616cba | 333 | { |
0d950d84 | 334 | struct iwl_calib_xtal_freq_cmd cmd; |
7c616cba TW |
335 | u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); |
336 | ||
0d950d84 TW |
337 | cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD; |
338 | cmd.hdr.first_group = 0; | |
339 | cmd.hdr.groups_num = 1; | |
340 | cmd.hdr.data_valid = 1; | |
341 | cmd.cap_pin1 = (u8)xtal_calib[0]; | |
342 | cmd.cap_pin2 = (u8)xtal_calib[1]; | |
f69f42a6 | 343 | return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL], |
0d950d84 | 344 | (u8 *)&cmd, sizeof(cmd)); |
7c616cba TW |
345 | } |
346 | ||
7c616cba TW |
347 | static int iwl5000_send_calib_cfg(struct iwl_priv *priv) |
348 | { | |
f69f42a6 | 349 | struct iwl_calib_cfg_cmd calib_cfg_cmd; |
7c616cba TW |
350 | struct iwl_host_cmd cmd = { |
351 | .id = CALIBRATION_CFG_CMD, | |
f69f42a6 | 352 | .len = sizeof(struct iwl_calib_cfg_cmd), |
7c616cba TW |
353 | .data = &calib_cfg_cmd, |
354 | }; | |
355 | ||
356 | memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); | |
357 | calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; | |
358 | calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; | |
359 | calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; | |
360 | calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; | |
361 | ||
362 | return iwl_send_cmd(priv, &cmd); | |
363 | } | |
364 | ||
365 | static void iwl5000_rx_calib_result(struct iwl_priv *priv, | |
366 | struct iwl_rx_mem_buffer *rxb) | |
367 | { | |
2f301227 | 368 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
f69f42a6 | 369 | struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw; |
396887a2 | 370 | int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; |
6e21f2c1 | 371 | int index; |
7c616cba TW |
372 | |
373 | /* reduce the size of the length field itself */ | |
374 | len -= 4; | |
375 | ||
6e21f2c1 TW |
376 | /* Define the order in which the results will be sent to the runtime |
377 | * uCode. iwl_send_calib_results sends them in a row according to their | |
378 | * index. We sort them here */ | |
7c616cba | 379 | switch (hdr->op_code) { |
819500c5 TW |
380 | case IWL_PHY_CALIBRATE_DC_CMD: |
381 | index = IWL_CALIB_DC; | |
382 | break; | |
f69f42a6 TW |
383 | case IWL_PHY_CALIBRATE_LO_CMD: |
384 | index = IWL_CALIB_LO; | |
7c616cba | 385 | break; |
f69f42a6 TW |
386 | case IWL_PHY_CALIBRATE_TX_IQ_CMD: |
387 | index = IWL_CALIB_TX_IQ; | |
7c616cba | 388 | break; |
f69f42a6 TW |
389 | case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD: |
390 | index = IWL_CALIB_TX_IQ_PERD; | |
7c616cba | 391 | break; |
201706ac TW |
392 | case IWL_PHY_CALIBRATE_BASE_BAND_CMD: |
393 | index = IWL_CALIB_BASE_BAND; | |
394 | break; | |
7c616cba | 395 | default: |
15b1687c | 396 | IWL_ERR(priv, "Unknown calibration notification %d\n", |
7c616cba TW |
397 | hdr->op_code); |
398 | return; | |
399 | } | |
6e21f2c1 | 400 | iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len); |
7c616cba TW |
401 | } |
402 | ||
403 | static void iwl5000_rx_calib_complete(struct iwl_priv *priv, | |
404 | struct iwl_rx_mem_buffer *rxb) | |
405 | { | |
e1623446 | 406 | IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n"); |
7c616cba TW |
407 | queue_work(priv->workqueue, &priv->restart); |
408 | } | |
409 | ||
dbb983b7 RR |
410 | /* |
411 | * ucode | |
412 | */ | |
413 | static int iwl5000_load_section(struct iwl_priv *priv, | |
414 | struct fw_desc *image, | |
415 | u32 dst_addr) | |
416 | { | |
dbb983b7 RR |
417 | dma_addr_t phy_addr = image->p_addr; |
418 | u32 byte_cnt = image->len; | |
419 | ||
dbb983b7 RR |
420 | iwl_write_direct32(priv, |
421 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
422 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
423 | ||
424 | iwl_write_direct32(priv, | |
425 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); | |
426 | ||
427 | iwl_write_direct32(priv, | |
428 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), | |
429 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
430 | ||
dbb983b7 | 431 | iwl_write_direct32(priv, |
f0b9f5cb | 432 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
499b1883 | 433 | (iwl_get_dma_hi_addr(phy_addr) |
f0b9f5cb TW |
434 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); |
435 | ||
dbb983b7 RR |
436 | iwl_write_direct32(priv, |
437 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), | |
438 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
439 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
440 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
441 | ||
442 | iwl_write_direct32(priv, | |
443 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
444 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
9c80c502 | 445 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | |
dbb983b7 RR |
446 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); |
447 | ||
dbb983b7 RR |
448 | return 0; |
449 | } | |
450 | ||
451 | static int iwl5000_load_given_ucode(struct iwl_priv *priv, | |
452 | struct fw_desc *inst_image, | |
453 | struct fw_desc *data_image) | |
454 | { | |
455 | int ret = 0; | |
456 | ||
250bdd21 SO |
457 | ret = iwl5000_load_section(priv, inst_image, |
458 | IWL50_RTC_INST_LOWER_BOUND); | |
dbb983b7 RR |
459 | if (ret) |
460 | return ret; | |
461 | ||
e1623446 | 462 | IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n"); |
dbb983b7 | 463 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
9c80c502 | 464 | priv->ucode_write_complete, 5 * HZ); |
dbb983b7 | 465 | if (ret == -ERESTARTSYS) { |
15b1687c | 466 | IWL_ERR(priv, "Could not load the INST uCode section due " |
dbb983b7 RR |
467 | "to interrupt\n"); |
468 | return ret; | |
469 | } | |
470 | if (!ret) { | |
15b1687c | 471 | IWL_ERR(priv, "Could not load the INST uCode section\n"); |
dbb983b7 RR |
472 | return -ETIMEDOUT; |
473 | } | |
474 | ||
475 | priv->ucode_write_complete = 0; | |
476 | ||
477 | ret = iwl5000_load_section( | |
250bdd21 | 478 | priv, data_image, IWL50_RTC_DATA_LOWER_BOUND); |
dbb983b7 RR |
479 | if (ret) |
480 | return ret; | |
481 | ||
e1623446 | 482 | IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n"); |
dbb983b7 RR |
483 | |
484 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
485 | priv->ucode_write_complete, 5 * HZ); | |
486 | if (ret == -ERESTARTSYS) { | |
15b1687c | 487 | IWL_ERR(priv, "Could not load the INST uCode section due " |
dbb983b7 RR |
488 | "to interrupt\n"); |
489 | return ret; | |
490 | } else if (!ret) { | |
15b1687c | 491 | IWL_ERR(priv, "Could not load the DATA uCode section\n"); |
dbb983b7 RR |
492 | return -ETIMEDOUT; |
493 | } else | |
494 | ret = 0; | |
495 | ||
496 | priv->ucode_write_complete = 0; | |
497 | ||
498 | return ret; | |
499 | } | |
500 | ||
672639de | 501 | int iwl5000_load_ucode(struct iwl_priv *priv) |
dbb983b7 RR |
502 | { |
503 | int ret = 0; | |
504 | ||
505 | /* check whether init ucode should be loaded, or rather runtime ucode */ | |
506 | if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { | |
e1623446 | 507 | IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n"); |
dbb983b7 RR |
508 | ret = iwl5000_load_given_ucode(priv, |
509 | &priv->ucode_init, &priv->ucode_init_data); | |
510 | if (!ret) { | |
e1623446 | 511 | IWL_DEBUG_INFO(priv, "Init ucode load complete.\n"); |
dbb983b7 RR |
512 | priv->ucode_type = UCODE_INIT; |
513 | } | |
514 | } else { | |
e1623446 | 515 | IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. " |
dbb983b7 RR |
516 | "Loading runtime ucode...\n"); |
517 | ret = iwl5000_load_given_ucode(priv, | |
518 | &priv->ucode_code, &priv->ucode_data); | |
519 | if (!ret) { | |
e1623446 | 520 | IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n"); |
dbb983b7 RR |
521 | priv->ucode_type = UCODE_RT; |
522 | } | |
523 | } | |
524 | ||
525 | return ret; | |
526 | } | |
527 | ||
672639de | 528 | void iwl5000_init_alive_start(struct iwl_priv *priv) |
99da1b48 RR |
529 | { |
530 | int ret = 0; | |
531 | ||
532 | /* Check alive response for "valid" sign from uCode */ | |
533 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
534 | /* We had an error bringing up the hardware, so take it | |
535 | * all the way back down so we can try again */ | |
e1623446 | 536 | IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n"); |
99da1b48 RR |
537 | goto restart; |
538 | } | |
539 | ||
540 | /* initialize uCode was loaded... verify inst image. | |
541 | * This is a paranoid check, because we would not have gotten the | |
542 | * "initialize" alive if code weren't properly loaded. */ | |
543 | if (iwl_verify_ucode(priv)) { | |
544 | /* Runtime instruction load was bad; | |
545 | * take it all the way back down so we can try again */ | |
e1623446 | 546 | IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n"); |
99da1b48 RR |
547 | goto restart; |
548 | } | |
549 | ||
c587de0b | 550 | iwl_clear_stations_table(priv); |
99da1b48 RR |
551 | ret = priv->cfg->ops->lib->alive_notify(priv); |
552 | if (ret) { | |
39aadf8c WT |
553 | IWL_WARN(priv, |
554 | "Could not complete ALIVE transition: %d\n", ret); | |
99da1b48 RR |
555 | goto restart; |
556 | } | |
557 | ||
7c616cba | 558 | iwl5000_send_calib_cfg(priv); |
99da1b48 RR |
559 | return; |
560 | ||
561 | restart: | |
562 | /* real restart (first load init_ucode) */ | |
563 | queue_work(priv->workqueue, &priv->restart); | |
564 | } | |
565 | ||
566 | static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, | |
567 | int txq_id, u32 index) | |
568 | { | |
569 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, | |
570 | (index & 0xff) | (txq_id << 8)); | |
571 | iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); | |
572 | } | |
573 | ||
574 | static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, | |
575 | struct iwl_tx_queue *txq, | |
576 | int tx_fifo_id, int scd_retry) | |
577 | { | |
578 | int txq_id = txq->q.id; | |
3fd07a1e | 579 | int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; |
99da1b48 RR |
580 | |
581 | iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), | |
582 | (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
583 | (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | | |
584 | (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | | |
585 | IWL50_SCD_QUEUE_STTS_REG_MSK); | |
586 | ||
587 | txq->sched_retry = scd_retry; | |
588 | ||
e1623446 | 589 | IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n", |
99da1b48 RR |
590 | active ? "Activate" : "Deactivate", |
591 | scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); | |
592 | } | |
593 | ||
672639de | 594 | int iwl5000_alive_notify(struct iwl_priv *priv) |
99da1b48 RR |
595 | { |
596 | u32 a; | |
99da1b48 | 597 | unsigned long flags; |
31a73fe4 | 598 | int i, chan; |
40fc95d5 | 599 | u32 reg_val; |
99da1b48 RR |
600 | |
601 | spin_lock_irqsave(&priv->lock, flags); | |
602 | ||
99da1b48 RR |
603 | priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); |
604 | a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; | |
605 | for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; | |
606 | a += 4) | |
607 | iwl_write_targ_mem(priv, a, 0); | |
608 | for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; | |
609 | a += 4) | |
610 | iwl_write_targ_mem(priv, a, 0); | |
39d5e0ce HW |
611 | for (; a < priv->scd_base_addr + |
612 | IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4) | |
99da1b48 RR |
613 | iwl_write_targ_mem(priv, a, 0); |
614 | ||
615 | iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, | |
4ddbb7d0 | 616 | priv->scd_bc_tbls.dma >> 10); |
31a73fe4 WT |
617 | |
618 | /* Enable DMA channel */ | |
619 | for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++) | |
620 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
621 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
622 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
623 | ||
40fc95d5 WT |
624 | /* Update FH chicken bits */ |
625 | reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG); | |
626 | iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG, | |
627 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
628 | ||
99da1b48 | 629 | iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, |
4ddbb7d0 | 630 | IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num)); |
99da1b48 RR |
631 | iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); |
632 | ||
633 | /* initiate the queues */ | |
634 | for (i = 0; i < priv->hw_params.max_txq_num; i++) { | |
635 | iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); | |
636 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); | |
637 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
638 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); | |
639 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
640 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + | |
641 | sizeof(u32), | |
642 | ((SCD_WIN_SIZE << | |
643 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
644 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
645 | ((SCD_FRAME_LIMIT << | |
646 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
647 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
648 | } | |
649 | ||
650 | iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, | |
da1bc453 | 651 | IWL_MASK(0, priv->hw_params.max_txq_num)); |
99da1b48 | 652 | |
da1bc453 TW |
653 | /* Activate all Tx DMA/FIFO channels */ |
654 | priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); | |
99da1b48 RR |
655 | |
656 | iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); | |
9c80c502 | 657 | |
99da1b48 RR |
658 | /* map qos queues to fifos one-to-one */ |
659 | for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { | |
660 | int ac = iwl5000_default_queue_to_tx_fifo[i]; | |
661 | iwl_txq_ctx_activate(priv, i); | |
662 | iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); | |
663 | } | |
a221e6f7 JB |
664 | |
665 | /* | |
666 | * TODO - need to initialize these queues and map them to FIFOs | |
667 | * in the loop above, not only mark them as active. We do this | |
668 | * because we want the first aggregation queue to be queue #10, | |
669 | * but do not use 8 or 9 otherwise yet. | |
670 | */ | |
99da1b48 RR |
671 | iwl_txq_ctx_activate(priv, 7); |
672 | iwl_txq_ctx_activate(priv, 8); | |
673 | iwl_txq_ctx_activate(priv, 9); | |
674 | ||
99da1b48 RR |
675 | spin_unlock_irqrestore(&priv->lock, flags); |
676 | ||
7c616cba | 677 | |
1933ac4d | 678 | iwl_send_wimax_coex(priv); |
9636e583 | 679 | |
be5d56ed TW |
680 | iwl5000_set_Xtal_calib(priv); |
681 | iwl_send_calib_results(priv); | |
7c616cba | 682 | |
99da1b48 RR |
683 | return 0; |
684 | } | |
685 | ||
672639de | 686 | int iwl5000_hw_set_hw_params(struct iwl_priv *priv) |
fdd3e8a4 | 687 | { |
88804e2b WYG |
688 | if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES && |
689 | priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES) | |
690 | priv->cfg->num_of_queues = | |
691 | priv->cfg->mod_params->num_of_queues; | |
25ae3986 | 692 | |
88804e2b | 693 | priv->hw_params.max_txq_num = priv->cfg->num_of_queues; |
f3f911d1 | 694 | priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM; |
4ddbb7d0 | 695 | priv->hw_params.scd_bc_tbls_size = |
88804e2b WYG |
696 | priv->cfg->num_of_queues * |
697 | sizeof(struct iwl5000_scd_bc_tbl); | |
a8e74e27 | 698 | priv->hw_params.tfd_size = sizeof(struct iwl_tfd); |
fdd3e8a4 TW |
699 | priv->hw_params.max_stations = IWL5000_STATION_COUNT; |
700 | priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; | |
c0bac76a | 701 | |
f3a2a424 WYG |
702 | priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; |
703 | priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; | |
c0bac76a | 704 | |
da154e30 | 705 | priv->hw_params.max_bsm_size = 0; |
7aafef1c | 706 | priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) | |
fdd3e8a4 | 707 | BIT(IEEE80211_BAND_5GHZ); |
141c43a3 WT |
708 | priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR; |
709 | ||
c0bac76a JS |
710 | priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant); |
711 | priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant); | |
712 | priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant; | |
713 | priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant; | |
c031bf80 | 714 | |
62161aef WYG |
715 | if (priv->cfg->ops->lib->temp_ops.set_ct_kill) |
716 | priv->cfg->ops->lib->temp_ops.set_ct_kill(priv); | |
c031bf80 | 717 | |
9d67187d | 718 | /* Set initial sensitivity parameters */ |
be5d56ed TW |
719 | /* Set initial calibration set */ |
720 | switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { | |
c0bac76a | 721 | case CSR_HW_REV_TYPE_5150: |
9d67187d | 722 | priv->hw_params.sens = &iwl5150_sensitivity; |
be5d56ed | 723 | priv->hw_params.calib_init_cfg = |
c0bac76a | 724 | BIT(IWL_CALIB_DC) | |
f69f42a6 | 725 | BIT(IWL_CALIB_LO) | |
201706ac | 726 | BIT(IWL_CALIB_TX_IQ) | |
201706ac | 727 | BIT(IWL_CALIB_BASE_BAND); |
c0bac76a | 728 | |
be5d56ed | 729 | break; |
c0bac76a | 730 | default: |
9d67187d | 731 | priv->hw_params.sens = &iwl5000_sensitivity; |
819500c5 | 732 | priv->hw_params.calib_init_cfg = |
c0bac76a | 733 | BIT(IWL_CALIB_XTAL) | |
7470d7f5 WT |
734 | BIT(IWL_CALIB_LO) | |
735 | BIT(IWL_CALIB_TX_IQ) | | |
c0bac76a | 736 | BIT(IWL_CALIB_TX_IQ_PERD) | |
7470d7f5 | 737 | BIT(IWL_CALIB_BASE_BAND); |
be5d56ed TW |
738 | break; |
739 | } | |
740 | ||
fdd3e8a4 TW |
741 | return 0; |
742 | } | |
d4100dd9 | 743 | |
7839fc03 EG |
744 | /** |
745 | * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
746 | */ | |
672639de | 747 | void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, |
16466903 | 748 | struct iwl_tx_queue *txq, |
7839fc03 EG |
749 | u16 byte_cnt) |
750 | { | |
4ddbb7d0 | 751 | struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; |
127901ab | 752 | int write_ptr = txq->q.write_ptr; |
7839fc03 EG |
753 | int txq_id = txq->q.id; |
754 | u8 sec_ctl = 0; | |
127901ab TW |
755 | u8 sta_id = 0; |
756 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
757 | __le16 bc_ent; | |
7839fc03 | 758 | |
127901ab | 759 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
7839fc03 EG |
760 | |
761 | if (txq_id != IWL_CMD_QUEUE_NUM) { | |
127901ab | 762 | sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; |
da99c4b6 | 763 | sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; |
7839fc03 EG |
764 | |
765 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
766 | case TX_CMD_SEC_CCM: | |
767 | len += CCMP_MIC_LEN; | |
768 | break; | |
769 | case TX_CMD_SEC_TKIP: | |
770 | len += TKIP_ICV_LEN; | |
771 | break; | |
772 | case TX_CMD_SEC_WEP: | |
773 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
774 | break; | |
775 | } | |
776 | } | |
777 | ||
127901ab | 778 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); |
7839fc03 | 779 | |
4ddbb7d0 | 780 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; |
7839fc03 | 781 | |
127901ab | 782 | if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) |
4ddbb7d0 | 783 | scd_bc_tbl[txq_id]. |
127901ab | 784 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; |
7839fc03 EG |
785 | } |
786 | ||
672639de | 787 | void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, |
972cf447 TW |
788 | struct iwl_tx_queue *txq) |
789 | { | |
4ddbb7d0 | 790 | struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; |
127901ab TW |
791 | int txq_id = txq->q.id; |
792 | int read_ptr = txq->q.read_ptr; | |
793 | u8 sta_id = 0; | |
794 | __le16 bc_ent; | |
795 | ||
796 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
972cf447 TW |
797 | |
798 | if (txq_id != IWL_CMD_QUEUE_NUM) | |
127901ab | 799 | sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id; |
972cf447 | 800 | |
127901ab | 801 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); |
4ddbb7d0 | 802 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; |
972cf447 | 803 | |
127901ab | 804 | if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) |
4ddbb7d0 | 805 | scd_bc_tbl[txq_id]. |
127901ab | 806 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; |
972cf447 TW |
807 | } |
808 | ||
e26e47d9 TW |
809 | static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, |
810 | u16 txq_id) | |
811 | { | |
812 | u32 tbl_dw_addr; | |
813 | u32 tbl_dw; | |
814 | u16 scd_q2ratid; | |
815 | ||
816 | scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
817 | ||
818 | tbl_dw_addr = priv->scd_base_addr + | |
819 | IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); | |
820 | ||
821 | tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); | |
822 | ||
823 | if (txq_id & 0x1) | |
824 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
825 | else | |
826 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
827 | ||
828 | iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); | |
829 | ||
830 | return 0; | |
831 | } | |
832 | static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) | |
833 | { | |
834 | /* Simply stop the queue, but don't change any configuration; | |
835 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
836 | iwl_write_prph(priv, | |
837 | IWL50_SCD_QUEUE_STATUS_BITS(txq_id), | |
838 | (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
839 | (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
840 | } | |
841 | ||
672639de | 842 | int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, |
e26e47d9 TW |
843 | int tx_fifo, int sta_id, int tid, u16 ssn_idx) |
844 | { | |
845 | unsigned long flags; | |
e26e47d9 TW |
846 | u16 ra_tid; |
847 | ||
9f17b318 | 848 | if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || |
88804e2b WYG |
849 | (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues |
850 | <= txq_id)) { | |
39aadf8c WT |
851 | IWL_WARN(priv, |
852 | "queue number out of range: %d, must be %d to %d\n", | |
9f17b318 | 853 | txq_id, IWL50_FIRST_AMPDU_QUEUE, |
88804e2b WYG |
854 | IWL50_FIRST_AMPDU_QUEUE + |
855 | priv->cfg->num_of_ampdu_queues - 1); | |
9f17b318 TW |
856 | return -EINVAL; |
857 | } | |
e26e47d9 TW |
858 | |
859 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
860 | ||
861 | /* Modify device's station table to Tx this TID */ | |
9f58671e | 862 | iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); |
e26e47d9 TW |
863 | |
864 | spin_lock_irqsave(&priv->lock, flags); | |
e26e47d9 TW |
865 | |
866 | /* Stop this Tx queue before configuring it */ | |
867 | iwl5000_tx_queue_stop_scheduler(priv, txq_id); | |
868 | ||
869 | /* Map receiver-address / traffic-ID to this queue */ | |
870 | iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id); | |
871 | ||
872 | /* Set this queue as a chain-building queue */ | |
873 | iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id)); | |
874 | ||
875 | /* enable aggregations for the queue */ | |
876 | iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id)); | |
877 | ||
878 | /* Place first TFD at index corresponding to start sequence number. | |
879 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
880 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
881 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
882 | iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); | |
883 | ||
884 | /* Set up Tx window size and frame limit for this queue */ | |
885 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
886 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + | |
887 | sizeof(u32), | |
888 | ((SCD_WIN_SIZE << | |
889 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
890 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
891 | ((SCD_FRAME_LIMIT << | |
892 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
893 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
894 | ||
895 | iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); | |
896 | ||
897 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
898 | iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); | |
899 | ||
e26e47d9 TW |
900 | spin_unlock_irqrestore(&priv->lock, flags); |
901 | ||
902 | return 0; | |
903 | } | |
904 | ||
672639de | 905 | int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, |
e26e47d9 TW |
906 | u16 ssn_idx, u8 tx_fifo) |
907 | { | |
9f17b318 | 908 | if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || |
88804e2b WYG |
909 | (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues |
910 | <= txq_id)) { | |
a2f1cbeb | 911 | IWL_ERR(priv, |
39aadf8c | 912 | "queue number out of range: %d, must be %d to %d\n", |
9f17b318 | 913 | txq_id, IWL50_FIRST_AMPDU_QUEUE, |
88804e2b WYG |
914 | IWL50_FIRST_AMPDU_QUEUE + |
915 | priv->cfg->num_of_ampdu_queues - 1); | |
e26e47d9 TW |
916 | return -EINVAL; |
917 | } | |
918 | ||
e26e47d9 TW |
919 | iwl5000_tx_queue_stop_scheduler(priv, txq_id); |
920 | ||
921 | iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); | |
922 | ||
923 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
924 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
925 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
926 | iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); | |
927 | ||
928 | iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); | |
929 | iwl_txq_ctx_deactivate(priv, txq_id); | |
930 | iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); | |
931 | ||
e26e47d9 TW |
932 | return 0; |
933 | } | |
934 | ||
e8c00dcb | 935 | u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) |
2469bf2e TW |
936 | { |
937 | u16 size = (u16)sizeof(struct iwl_addsta_cmd); | |
c587de0b TW |
938 | struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data; |
939 | memcpy(addsta, cmd, size); | |
940 | /* resrved in 5000 */ | |
941 | addsta->rate_n_flags = cpu_to_le16(0); | |
2469bf2e TW |
942 | return size; |
943 | } | |
944 | ||
945 | ||
da1bc453 | 946 | /* |
a96a27f9 | 947 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask |
da1bc453 TW |
948 | * must be called under priv->lock and mac access |
949 | */ | |
672639de | 950 | void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) |
5a676bbe | 951 | { |
da1bc453 | 952 | iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); |
5a676bbe RR |
953 | } |
954 | ||
e532fa0e RR |
955 | |
956 | static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) | |
957 | { | |
3ac7f146 | 958 | return le32_to_cpup((__le32 *)&tx_resp->status + |
25a6572c | 959 | tx_resp->frame_count) & MAX_SN; |
e532fa0e RR |
960 | } |
961 | ||
962 | static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, | |
963 | struct iwl_ht_agg *agg, | |
964 | struct iwl5000_tx_resp *tx_resp, | |
25a6572c | 965 | int txq_id, u16 start_idx) |
e532fa0e RR |
966 | { |
967 | u16 status; | |
968 | struct agg_tx_status *frame_status = &tx_resp->status; | |
969 | struct ieee80211_tx_info *info = NULL; | |
970 | struct ieee80211_hdr *hdr = NULL; | |
e7d326ac | 971 | u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); |
25a6572c | 972 | int i, sh, idx; |
e532fa0e RR |
973 | u16 seq; |
974 | ||
975 | if (agg->wait_for_ba) | |
e1623446 | 976 | IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n"); |
e532fa0e RR |
977 | |
978 | agg->frame_count = tx_resp->frame_count; | |
979 | agg->start_idx = start_idx; | |
e7d326ac | 980 | agg->rate_n_flags = rate_n_flags; |
e532fa0e RR |
981 | agg->bitmap = 0; |
982 | ||
983 | /* # frames attempted by Tx command */ | |
984 | if (agg->frame_count == 1) { | |
985 | /* Only one frame was attempted; no block-ack will arrive */ | |
986 | status = le16_to_cpu(frame_status[0].status); | |
25a6572c | 987 | idx = start_idx; |
e532fa0e RR |
988 | |
989 | /* FIXME: code repetition */ | |
e1623446 | 990 | IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n", |
e532fa0e RR |
991 | agg->frame_count, agg->start_idx, idx); |
992 | ||
993 | info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); | |
e6a9854b | 994 | info->status.rates[0].count = tx_resp->failure_frame + 1; |
e532fa0e | 995 | info->flags &= ~IEEE80211_TX_CTL_AMPDU; |
c3056065 | 996 | info->flags |= iwl_is_tx_success(status) ? |
3fd07a1e | 997 | IEEE80211_TX_STAT_ACK : 0; |
e7d326ac TW |
998 | iwl_hwrate_to_tx_control(priv, rate_n_flags, info); |
999 | ||
e532fa0e RR |
1000 | /* FIXME: code repetition end */ |
1001 | ||
e1623446 | 1002 | IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n", |
e532fa0e | 1003 | status & 0xff, tx_resp->failure_frame); |
e1623446 | 1004 | IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags); |
e532fa0e RR |
1005 | |
1006 | agg->wait_for_ba = 0; | |
1007 | } else { | |
1008 | /* Two or more frames were attempted; expect block-ack */ | |
1009 | u64 bitmap = 0; | |
1010 | int start = agg->start_idx; | |
1011 | ||
1012 | /* Construct bit-map of pending frames within Tx window */ | |
1013 | for (i = 0; i < agg->frame_count; i++) { | |
1014 | u16 sc; | |
1015 | status = le16_to_cpu(frame_status[i].status); | |
1016 | seq = le16_to_cpu(frame_status[i].sequence); | |
1017 | idx = SEQ_TO_INDEX(seq); | |
1018 | txq_id = SEQ_TO_QUEUE(seq); | |
1019 | ||
1020 | if (status & (AGG_TX_STATE_FEW_BYTES_MSK | | |
1021 | AGG_TX_STATE_ABORT_MSK)) | |
1022 | continue; | |
1023 | ||
e1623446 | 1024 | IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n", |
e532fa0e RR |
1025 | agg->frame_count, txq_id, idx); |
1026 | ||
1027 | hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); | |
6c6a22e2 SG |
1028 | if (!hdr) { |
1029 | IWL_ERR(priv, | |
1030 | "BUG_ON idx doesn't point to valid skb" | |
1031 | " idx=%d, txq_id=%d\n", idx, txq_id); | |
1032 | return -1; | |
1033 | } | |
e532fa0e RR |
1034 | |
1035 | sc = le16_to_cpu(hdr->seq_ctrl); | |
1036 | if (idx != (SEQ_TO_SN(sc) & 0xff)) { | |
15b1687c WT |
1037 | IWL_ERR(priv, |
1038 | "BUG_ON idx doesn't match seq control" | |
1039 | " idx=%d, seq_idx=%d, seq=%d\n", | |
e532fa0e RR |
1040 | idx, SEQ_TO_SN(sc), |
1041 | hdr->seq_ctrl); | |
1042 | return -1; | |
1043 | } | |
1044 | ||
e1623446 | 1045 | IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n", |
e532fa0e RR |
1046 | i, idx, SEQ_TO_SN(sc)); |
1047 | ||
1048 | sh = idx - start; | |
1049 | if (sh > 64) { | |
1050 | sh = (start - idx) + 0xff; | |
1051 | bitmap = bitmap << sh; | |
1052 | sh = 0; | |
1053 | start = idx; | |
1054 | } else if (sh < -64) | |
1055 | sh = 0xff - (start - idx); | |
1056 | else if (sh < 0) { | |
1057 | sh = start - idx; | |
1058 | start = idx; | |
1059 | bitmap = bitmap << sh; | |
1060 | sh = 0; | |
1061 | } | |
4aa41f12 | 1062 | bitmap |= 1ULL << sh; |
e1623446 | 1063 | IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n", |
4aa41f12 | 1064 | start, (unsigned long long)bitmap); |
e532fa0e RR |
1065 | } |
1066 | ||
1067 | agg->bitmap = bitmap; | |
1068 | agg->start_idx = start; | |
e1623446 | 1069 | IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n", |
e532fa0e RR |
1070 | agg->frame_count, agg->start_idx, |
1071 | (unsigned long long)agg->bitmap); | |
1072 | ||
1073 | if (bitmap) | |
1074 | agg->wait_for_ba = 1; | |
1075 | } | |
1076 | return 0; | |
1077 | } | |
1078 | ||
1079 | static void iwl5000_rx_reply_tx(struct iwl_priv *priv, | |
1080 | struct iwl_rx_mem_buffer *rxb) | |
1081 | { | |
2f301227 | 1082 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
e532fa0e RR |
1083 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
1084 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1085 | int index = SEQ_TO_INDEX(sequence); | |
1086 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1087 | struct ieee80211_tx_info *info; | |
1088 | struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; | |
1089 | u32 status = le16_to_cpu(tx_resp->status.status); | |
3fd07a1e TW |
1090 | int tid; |
1091 | int sta_id; | |
1092 | int freed; | |
e532fa0e RR |
1093 | |
1094 | if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { | |
15b1687c | 1095 | IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d " |
e532fa0e RR |
1096 | "is out of range [0-%d] %d %d\n", txq_id, |
1097 | index, txq->q.n_bd, txq->q.write_ptr, | |
1098 | txq->q.read_ptr); | |
1099 | return; | |
1100 | } | |
1101 | ||
1102 | info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); | |
1103 | memset(&info->status, 0, sizeof(info->status)); | |
1104 | ||
3fd07a1e TW |
1105 | tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS; |
1106 | sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS; | |
e532fa0e RR |
1107 | |
1108 | if (txq->sched_retry) { | |
1109 | const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp); | |
1110 | struct iwl_ht_agg *agg = NULL; | |
1111 | ||
e532fa0e RR |
1112 | agg = &priv->stations[sta_id].tid[tid].agg; |
1113 | ||
25a6572c | 1114 | iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); |
e532fa0e | 1115 | |
3235427e RR |
1116 | /* check if BAR is needed */ |
1117 | if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) | |
1118 | info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; | |
e532fa0e RR |
1119 | |
1120 | if (txq->q.read_ptr != (scd_ssn & 0xff)) { | |
e532fa0e | 1121 | index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); |
e1623446 | 1122 | IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim " |
3fd07a1e TW |
1123 | "scd_ssn=%d idx=%d txq=%d swq=%d\n", |
1124 | scd_ssn , index, txq_id, txq->swq_id); | |
1125 | ||
17b88929 | 1126 | freed = iwl_tx_queue_reclaim(priv, txq_id, index); |
e532fa0e RR |
1127 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
1128 | ||
3fd07a1e TW |
1129 | if (priv->mac80211_registered && |
1130 | (iwl_queue_space(&txq->q) > txq->q.low_mark) && | |
1131 | (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) { | |
e532fa0e | 1132 | if (agg->state == IWL_AGG_OFF) |
e4e72fb4 | 1133 | iwl_wake_queue(priv, txq_id); |
e532fa0e | 1134 | else |
e4e72fb4 | 1135 | iwl_wake_queue(priv, txq->swq_id); |
e532fa0e | 1136 | } |
e532fa0e RR |
1137 | } |
1138 | } else { | |
3fd07a1e TW |
1139 | BUG_ON(txq_id != txq->swq_id); |
1140 | ||
e6a9854b | 1141 | info->status.rates[0].count = tx_resp->failure_frame + 1; |
3fd07a1e TW |
1142 | info->flags |= iwl_is_tx_success(status) ? |
1143 | IEEE80211_TX_STAT_ACK : 0; | |
e7d326ac | 1144 | iwl_hwrate_to_tx_control(priv, |
4f85f5b3 RR |
1145 | le32_to_cpu(tx_resp->rate_n_flags), |
1146 | info); | |
1147 | ||
e1623446 | 1148 | IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags " |
3fd07a1e TW |
1149 | "0x%x retries %d\n", |
1150 | txq_id, | |
1151 | iwl_get_tx_fail_reason(status), status, | |
1152 | le32_to_cpu(tx_resp->rate_n_flags), | |
1153 | tx_resp->failure_frame); | |
4f85f5b3 | 1154 | |
3fd07a1e TW |
1155 | freed = iwl_tx_queue_reclaim(priv, txq_id, index); |
1156 | if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) | |
e532fa0e | 1157 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
3fd07a1e TW |
1158 | |
1159 | if (priv->mac80211_registered && | |
1160 | (iwl_queue_space(&txq->q) > txq->q.low_mark)) | |
e4e72fb4 | 1161 | iwl_wake_queue(priv, txq_id); |
e532fa0e | 1162 | } |
e532fa0e | 1163 | |
3fd07a1e TW |
1164 | if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) |
1165 | iwl_txq_check_empty(priv, sta_id, tid, txq_id); | |
1166 | ||
e532fa0e | 1167 | if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) |
15b1687c | 1168 | IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n"); |
e532fa0e RR |
1169 | } |
1170 | ||
a96a27f9 | 1171 | /* Currently 5000 is the superset of everything */ |
e8c00dcb | 1172 | u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) |
c1adf9fb GG |
1173 | { |
1174 | return len; | |
1175 | } | |
1176 | ||
672639de | 1177 | void iwl5000_setup_deferred_work(struct iwl_priv *priv) |
203566f3 EG |
1178 | { |
1179 | /* in 5000 the tx power calibration is done in uCode */ | |
1180 | priv->disable_tx_power_cal = 1; | |
1181 | } | |
1182 | ||
672639de | 1183 | void iwl5000_rx_handler_setup(struct iwl_priv *priv) |
b600e4e1 | 1184 | { |
7c616cba TW |
1185 | /* init calibration handlers */ |
1186 | priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = | |
1187 | iwl5000_rx_calib_result; | |
1188 | priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = | |
1189 | iwl5000_rx_calib_complete; | |
e532fa0e | 1190 | priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx; |
b600e4e1 RR |
1191 | } |
1192 | ||
7c616cba | 1193 | |
672639de | 1194 | int iwl5000_hw_valid_rtc_data_addr(u32 addr) |
87283cc1 | 1195 | { |
250bdd21 | 1196 | return (addr >= IWL50_RTC_DATA_LOWER_BOUND) && |
87283cc1 RR |
1197 | (addr < IWL50_RTC_DATA_UPPER_BOUND); |
1198 | } | |
1199 | ||
fe7a90c2 RR |
1200 | static int iwl5000_send_rxon_assoc(struct iwl_priv *priv) |
1201 | { | |
1202 | int ret = 0; | |
1203 | struct iwl5000_rxon_assoc_cmd rxon_assoc; | |
1204 | const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; | |
1205 | const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; | |
1206 | ||
1207 | if ((rxon1->flags == rxon2->flags) && | |
1208 | (rxon1->filter_flags == rxon2->filter_flags) && | |
1209 | (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && | |
1210 | (rxon1->ofdm_ht_single_stream_basic_rates == | |
1211 | rxon2->ofdm_ht_single_stream_basic_rates) && | |
1212 | (rxon1->ofdm_ht_dual_stream_basic_rates == | |
1213 | rxon2->ofdm_ht_dual_stream_basic_rates) && | |
1214 | (rxon1->ofdm_ht_triple_stream_basic_rates == | |
1215 | rxon2->ofdm_ht_triple_stream_basic_rates) && | |
1216 | (rxon1->acquisition_data == rxon2->acquisition_data) && | |
1217 | (rxon1->rx_chain == rxon2->rx_chain) && | |
1218 | (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { | |
e1623446 | 1219 | IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n"); |
fe7a90c2 RR |
1220 | return 0; |
1221 | } | |
1222 | ||
1223 | rxon_assoc.flags = priv->staging_rxon.flags; | |
1224 | rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; | |
1225 | rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; | |
1226 | rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; | |
1227 | rxon_assoc.reserved1 = 0; | |
1228 | rxon_assoc.reserved2 = 0; | |
1229 | rxon_assoc.reserved3 = 0; | |
1230 | rxon_assoc.ofdm_ht_single_stream_basic_rates = | |
1231 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates; | |
1232 | rxon_assoc.ofdm_ht_dual_stream_basic_rates = | |
1233 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; | |
1234 | rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; | |
1235 | rxon_assoc.ofdm_ht_triple_stream_basic_rates = | |
1236 | priv->staging_rxon.ofdm_ht_triple_stream_basic_rates; | |
1237 | rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data; | |
1238 | ||
1239 | ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, | |
1240 | sizeof(rxon_assoc), &rxon_assoc, NULL); | |
1241 | if (ret) | |
1242 | return ret; | |
1243 | ||
1244 | return ret; | |
1245 | } | |
672639de | 1246 | int iwl5000_send_tx_power(struct iwl_priv *priv) |
630fe9b6 TW |
1247 | { |
1248 | struct iwl5000_tx_power_dbm_cmd tx_power_cmd; | |
76a2407a | 1249 | u8 tx_ant_cfg_cmd; |
630fe9b6 TW |
1250 | |
1251 | /* half dBm need to multiply */ | |
1252 | tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt); | |
853554ac | 1253 | tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED; |
630fe9b6 | 1254 | tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO; |
76a2407a JS |
1255 | |
1256 | if (IWL_UCODE_API(priv->ucode_ver) == 1) | |
1257 | tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1; | |
1258 | else | |
1259 | tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD; | |
1260 | ||
1261 | return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd, | |
630fe9b6 TW |
1262 | sizeof(tx_power_cmd), &tx_power_cmd, |
1263 | NULL); | |
1264 | } | |
1265 | ||
672639de | 1266 | void iwl5000_temperature(struct iwl_priv *priv) |
8f91aecb EG |
1267 | { |
1268 | /* store temperature from statistics (in Celsius) */ | |
5225640b | 1269 | priv->temperature = le32_to_cpu(priv->statistics.general.temperature); |
39b73fb1 | 1270 | iwl_tt_handler(priv); |
8f91aecb | 1271 | } |
fe7a90c2 | 1272 | |
62161aef WYG |
1273 | static void iwl5150_temperature(struct iwl_priv *priv) |
1274 | { | |
1275 | u32 vt = 0; | |
1276 | s32 offset = iwl_temp_calib_to_offset(priv); | |
1277 | ||
1278 | vt = le32_to_cpu(priv->statistics.general.temperature); | |
1279 | vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset; | |
1280 | /* now vt hold the temperature in Kelvin */ | |
1281 | priv->temperature = KELVIN_TO_CELSIUS(vt); | |
15993e08 | 1282 | iwl_tt_handler(priv); |
62161aef WYG |
1283 | } |
1284 | ||
caab8f1a | 1285 | /* Calc max signal level (dBm) among 3 possible receivers */ |
e8c00dcb | 1286 | int iwl5000_calc_rssi(struct iwl_priv *priv, |
caab8f1a TW |
1287 | struct iwl_rx_phy_res *rx_resp) |
1288 | { | |
1289 | /* data from PHY/DSP regarding signal strength, etc., | |
1290 | * contents are always there, not configurable by host | |
1291 | */ | |
1292 | struct iwl5000_non_cfg_phy *ncphy = | |
1293 | (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf; | |
1294 | u32 val, rssi_a, rssi_b, rssi_c, max_rssi; | |
1295 | u8 agc; | |
1296 | ||
1297 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]); | |
1298 | agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS; | |
1299 | ||
1300 | /* Find max rssi among 3 possible receivers. | |
1301 | * These values are measured by the digital signal processor (DSP). | |
1302 | * They should stay fairly constant even as the signal strength varies, | |
1303 | * if the radio's automatic gain control (AGC) is working right. | |
1304 | * AGC value (see below) will provide the "interesting" info. | |
1305 | */ | |
1306 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]); | |
1307 | rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS; | |
1308 | rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS; | |
1309 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]); | |
1310 | rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS; | |
1311 | ||
1312 | max_rssi = max_t(u32, rssi_a, rssi_b); | |
1313 | max_rssi = max_t(u32, max_rssi, rssi_c); | |
1314 | ||
e1623446 | 1315 | IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n", |
caab8f1a TW |
1316 | rssi_a, rssi_b, rssi_c, max_rssi, agc); |
1317 | ||
1318 | /* dBm = max_rssi dB - agc dB - constant. | |
1319 | * Higher AGC (higher radio gain) means lower signal. */ | |
250bdd21 | 1320 | return max_rssi - agc - IWL49_RSSI_OFFSET; |
caab8f1a TW |
1321 | } |
1322 | ||
2f748dec WYG |
1323 | static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant) |
1324 | { | |
1325 | struct iwl_tx_ant_config_cmd tx_ant_cmd = { | |
1326 | .valid = cpu_to_le32(valid_tx_ant), | |
1327 | }; | |
1328 | ||
1329 | if (IWL_UCODE_API(priv->ucode_ver) > 1) { | |
1330 | IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant); | |
1331 | return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD, | |
1332 | sizeof(struct iwl_tx_ant_config_cmd), | |
1333 | &tx_ant_cmd); | |
1334 | } else { | |
1335 | IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n"); | |
1336 | return -EOPNOTSUPP; | |
1337 | } | |
1338 | } | |
1339 | ||
1340 | ||
cc0f555d JS |
1341 | #define IWL5000_UCODE_GET(item) \ |
1342 | static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\ | |
1343 | u32 api_ver) \ | |
1344 | { \ | |
1345 | if (api_ver <= 2) \ | |
1346 | return le32_to_cpu(ucode->u.v1.item); \ | |
1347 | return le32_to_cpu(ucode->u.v2.item); \ | |
1348 | } | |
1349 | ||
1350 | static u32 iwl5000_ucode_get_header_size(u32 api_ver) | |
1351 | { | |
1352 | if (api_ver <= 2) | |
1353 | return UCODE_HEADER_SIZE(1); | |
1354 | return UCODE_HEADER_SIZE(2); | |
1355 | } | |
1356 | ||
1357 | static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode, | |
1358 | u32 api_ver) | |
1359 | { | |
1360 | if (api_ver <= 2) | |
1361 | return 0; | |
1362 | return le32_to_cpu(ucode->u.v2.build); | |
1363 | } | |
1364 | ||
1365 | static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode, | |
1366 | u32 api_ver) | |
1367 | { | |
1368 | if (api_ver <= 2) | |
1369 | return (u8 *) ucode->u.v1.data; | |
1370 | return (u8 *) ucode->u.v2.data; | |
1371 | } | |
1372 | ||
1373 | IWL5000_UCODE_GET(inst_size); | |
1374 | IWL5000_UCODE_GET(data_size); | |
1375 | IWL5000_UCODE_GET(init_size); | |
1376 | IWL5000_UCODE_GET(init_data_size); | |
1377 | IWL5000_UCODE_GET(boot_size); | |
1378 | ||
4a56e965 WYG |
1379 | static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel) |
1380 | { | |
1381 | struct iwl5000_channel_switch_cmd cmd; | |
1382 | const struct iwl_channel_info *ch_info; | |
1383 | struct iwl_host_cmd hcmd = { | |
1384 | .id = REPLY_CHANNEL_SWITCH, | |
1385 | .len = sizeof(cmd), | |
1386 | .flags = CMD_SIZE_HUGE, | |
1387 | .data = &cmd, | |
1388 | }; | |
1389 | ||
1390 | IWL_DEBUG_11H(priv, "channel switch from %d to %d\n", | |
1391 | priv->active_rxon.channel, channel); | |
1392 | cmd.band = priv->band == IEEE80211_BAND_2GHZ; | |
1393 | cmd.channel = cpu_to_le16(channel); | |
1394 | cmd.rxon_flags = priv->active_rxon.flags; | |
1395 | cmd.rxon_filter_flags = priv->active_rxon.filter_flags; | |
1396 | cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time); | |
1397 | ch_info = iwl_get_channel_info(priv, priv->band, channel); | |
1398 | if (ch_info) | |
1399 | cmd.expect_beacon = is_channel_radar(ch_info); | |
1400 | else { | |
1401 | IWL_ERR(priv, "invalid channel switch from %u to %u\n", | |
1402 | priv->active_rxon.channel, channel); | |
1403 | return -EFAULT; | |
1404 | } | |
1405 | ||
1406 | return iwl_send_cmd_sync(priv, &hcmd); | |
1407 | } | |
1408 | ||
e8c00dcb | 1409 | struct iwl_hcmd_ops iwl5000_hcmd = { |
fe7a90c2 | 1410 | .rxon_assoc = iwl5000_send_rxon_assoc, |
e0158e61 | 1411 | .commit_rxon = iwl_commit_rxon, |
45823531 | 1412 | .set_rxon_chain = iwl_set_rxon_chain, |
2f748dec | 1413 | .set_tx_ant = iwl5000_send_tx_ant_config, |
da8dec29 TW |
1414 | }; |
1415 | ||
e8c00dcb | 1416 | struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { |
c1adf9fb | 1417 | .get_hcmd_size = iwl5000_get_hcmd_size, |
2469bf2e | 1418 | .build_addsta_hcmd = iwl5000_build_addsta_hcmd, |
33fd5033 EG |
1419 | .gain_computation = iwl5000_gain_computation, |
1420 | .chain_noise_reset = iwl5000_chain_noise_reset, | |
a326a5d0 | 1421 | .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, |
caab8f1a | 1422 | .calc_rssi = iwl5000_calc_rssi, |
da8dec29 TW |
1423 | }; |
1424 | ||
cc0f555d JS |
1425 | struct iwl_ucode_ops iwl5000_ucode = { |
1426 | .get_header_size = iwl5000_ucode_get_header_size, | |
1427 | .get_build = iwl5000_ucode_get_build, | |
1428 | .get_inst_size = iwl5000_ucode_get_inst_size, | |
1429 | .get_data_size = iwl5000_ucode_get_data_size, | |
1430 | .get_init_size = iwl5000_ucode_get_init_size, | |
1431 | .get_init_data_size = iwl5000_ucode_get_init_data_size, | |
1432 | .get_boot_size = iwl5000_ucode_get_boot_size, | |
1433 | .get_data = iwl5000_ucode_get_data, | |
1434 | }; | |
1435 | ||
e8c00dcb | 1436 | struct iwl_lib_ops iwl5000_lib = { |
fdd3e8a4 | 1437 | .set_hw_params = iwl5000_hw_set_hw_params, |
7839fc03 | 1438 | .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, |
972cf447 | 1439 | .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, |
da1bc453 | 1440 | .txq_set_sched = iwl5000_txq_set_sched, |
e26e47d9 TW |
1441 | .txq_agg_enable = iwl5000_txq_agg_enable, |
1442 | .txq_agg_disable = iwl5000_txq_agg_disable, | |
7aaa1d79 SO |
1443 | .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd, |
1444 | .txq_free_tfd = iwl_hw_txq_free_tfd, | |
a8e74e27 | 1445 | .txq_init = iwl_hw_tx_queue_init, |
b600e4e1 | 1446 | .rx_handler_setup = iwl5000_rx_handler_setup, |
203566f3 | 1447 | .setup_deferred_work = iwl5000_setup_deferred_work, |
87283cc1 | 1448 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, |
b7a79404 RC |
1449 | .dump_nic_event_log = iwl_dump_nic_event_log, |
1450 | .dump_nic_error_log = iwl_dump_nic_error_log, | |
dbb983b7 | 1451 | .load_ucode = iwl5000_load_ucode, |
99da1b48 RR |
1452 | .init_alive_start = iwl5000_init_alive_start, |
1453 | .alive_notify = iwl5000_alive_notify, | |
630fe9b6 | 1454 | .send_tx_power = iwl5000_send_tx_power, |
5b9f8cd3 | 1455 | .update_chain_flags = iwl_update_chain_flags, |
4a56e965 | 1456 | .set_channel_switch = iwl5000_hw_channel_switch, |
30d59260 | 1457 | .apm_ops = { |
fadb3582 | 1458 | .init = iwl_apm_init, |
d68b603c | 1459 | .stop = iwl_apm_stop, |
5a835353 | 1460 | .config = iwl5000_nic_config, |
5b9f8cd3 | 1461 | .set_pwr_src = iwl_set_pwr_src, |
30d59260 | 1462 | }, |
da8dec29 | 1463 | .eeprom_ops = { |
25ae3986 TW |
1464 | .regulatory_bands = { |
1465 | EEPROM_5000_REG_BAND_1_CHANNELS, | |
1466 | EEPROM_5000_REG_BAND_2_CHANNELS, | |
1467 | EEPROM_5000_REG_BAND_3_CHANNELS, | |
1468 | EEPROM_5000_REG_BAND_4_CHANNELS, | |
1469 | EEPROM_5000_REG_BAND_5_CHANNELS, | |
7aafef1c WYG |
1470 | EEPROM_5000_REG_BAND_24_HT40_CHANNELS, |
1471 | EEPROM_5000_REG_BAND_52_HT40_CHANNELS | |
25ae3986 | 1472 | }, |
da8dec29 TW |
1473 | .verify_signature = iwlcore_eeprom_verify_signature, |
1474 | .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, | |
1475 | .release_semaphore = iwlcore_eeprom_release_semaphore, | |
0ef2ca67 | 1476 | .calib_version = iwl5000_eeprom_calib_version, |
25ae3986 | 1477 | .query_addr = iwl5000_eeprom_query_addr, |
da8dec29 | 1478 | }, |
5bbe233b | 1479 | .post_associate = iwl_post_associate, |
ef850d7c | 1480 | .isr = iwl_isr_ict, |
60690a6a | 1481 | .config_ap = iwl_config_ap, |
62161aef WYG |
1482 | .temp_ops = { |
1483 | .temperature = iwl5000_temperature, | |
1484 | .set_ct_kill = iwl5000_set_ct_threshold, | |
1485 | }, | |
1486 | }; | |
1487 | ||
1488 | static struct iwl_lib_ops iwl5150_lib = { | |
1489 | .set_hw_params = iwl5000_hw_set_hw_params, | |
1490 | .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, | |
1491 | .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, | |
1492 | .txq_set_sched = iwl5000_txq_set_sched, | |
1493 | .txq_agg_enable = iwl5000_txq_agg_enable, | |
1494 | .txq_agg_disable = iwl5000_txq_agg_disable, | |
1495 | .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd, | |
1496 | .txq_free_tfd = iwl_hw_txq_free_tfd, | |
1497 | .txq_init = iwl_hw_tx_queue_init, | |
1498 | .rx_handler_setup = iwl5000_rx_handler_setup, | |
1499 | .setup_deferred_work = iwl5000_setup_deferred_work, | |
1500 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, | |
b7a79404 RC |
1501 | .dump_nic_event_log = iwl_dump_nic_event_log, |
1502 | .dump_nic_error_log = iwl_dump_nic_error_log, | |
62161aef WYG |
1503 | .load_ucode = iwl5000_load_ucode, |
1504 | .init_alive_start = iwl5000_init_alive_start, | |
1505 | .alive_notify = iwl5000_alive_notify, | |
1506 | .send_tx_power = iwl5000_send_tx_power, | |
1507 | .update_chain_flags = iwl_update_chain_flags, | |
4a56e965 | 1508 | .set_channel_switch = iwl5000_hw_channel_switch, |
62161aef | 1509 | .apm_ops = { |
fadb3582 | 1510 | .init = iwl_apm_init, |
d68b603c | 1511 | .stop = iwl_apm_stop, |
62161aef WYG |
1512 | .config = iwl5000_nic_config, |
1513 | .set_pwr_src = iwl_set_pwr_src, | |
1514 | }, | |
1515 | .eeprom_ops = { | |
1516 | .regulatory_bands = { | |
1517 | EEPROM_5000_REG_BAND_1_CHANNELS, | |
1518 | EEPROM_5000_REG_BAND_2_CHANNELS, | |
1519 | EEPROM_5000_REG_BAND_3_CHANNELS, | |
1520 | EEPROM_5000_REG_BAND_4_CHANNELS, | |
1521 | EEPROM_5000_REG_BAND_5_CHANNELS, | |
7aafef1c WYG |
1522 | EEPROM_5000_REG_BAND_24_HT40_CHANNELS, |
1523 | EEPROM_5000_REG_BAND_52_HT40_CHANNELS | |
62161aef WYG |
1524 | }, |
1525 | .verify_signature = iwlcore_eeprom_verify_signature, | |
1526 | .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, | |
1527 | .release_semaphore = iwlcore_eeprom_release_semaphore, | |
1528 | .calib_version = iwl5000_eeprom_calib_version, | |
1529 | .query_addr = iwl5000_eeprom_query_addr, | |
1530 | }, | |
1531 | .post_associate = iwl_post_associate, | |
ef850d7c | 1532 | .isr = iwl_isr_ict, |
62161aef WYG |
1533 | .config_ap = iwl_config_ap, |
1534 | .temp_ops = { | |
1535 | .temperature = iwl5150_temperature, | |
1536 | .set_ct_kill = iwl5150_set_ct_threshold, | |
1537 | }, | |
da8dec29 TW |
1538 | }; |
1539 | ||
e932a609 | 1540 | static struct iwl_ops iwl5000_ops = { |
cc0f555d | 1541 | .ucode = &iwl5000_ucode, |
da8dec29 TW |
1542 | .lib = &iwl5000_lib, |
1543 | .hcmd = &iwl5000_hcmd, | |
1544 | .utils = &iwl5000_hcmd_utils, | |
e932a609 | 1545 | .led = &iwlagn_led_ops, |
da8dec29 TW |
1546 | }; |
1547 | ||
62161aef | 1548 | static struct iwl_ops iwl5150_ops = { |
cc0f555d | 1549 | .ucode = &iwl5000_ucode, |
62161aef WYG |
1550 | .lib = &iwl5150_lib, |
1551 | .hcmd = &iwl5000_hcmd, | |
1552 | .utils = &iwl5000_hcmd_utils, | |
e932a609 | 1553 | .led = &iwlagn_led_ops, |
62161aef WYG |
1554 | }; |
1555 | ||
cec2d3f3 | 1556 | struct iwl_mod_params iwl50_mod_params = { |
5a6a256e | 1557 | .amsdu_size_8K = 1, |
3a1081e8 | 1558 | .restart_fw = 1, |
5a6a256e TW |
1559 | /* the rest are 0 by default */ |
1560 | }; | |
1561 | ||
1562 | ||
1563 | struct iwl_cfg iwl5300_agn_cfg = { | |
1564 | .name = "5300AGN", | |
a0987a8d RC |
1565 | .fw_name_pre = IWL5000_FW_PRE, |
1566 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1567 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
5a6a256e | 1568 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
da8dec29 | 1569 | .ops = &iwl5000_ops, |
25ae3986 | 1570 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
1571 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1572 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
88804e2b WYG |
1573 | .num_of_queues = IWL50_NUM_QUEUES, |
1574 | .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, | |
5a6a256e | 1575 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1576 | .valid_tx_ant = ANT_ABC, |
1577 | .valid_rx_ant = ANT_ABC, | |
fadb3582 BC |
1578 | .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, |
1579 | .set_l0s = true, | |
1580 | .use_bsm = false, | |
b261793d | 1581 | .ht_greenfield_support = true, |
f2d0d0e2 | 1582 | .led_compensation = 51, |
d8c07e7a | 1583 | .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, |
5a6a256e TW |
1584 | }; |
1585 | ||
47408639 EK |
1586 | struct iwl_cfg iwl5100_bg_cfg = { |
1587 | .name = "5100BG", | |
a0987a8d RC |
1588 | .fw_name_pre = IWL5000_FW_PRE, |
1589 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1590 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
47408639 EK |
1591 | .sku = IWL_SKU_G, |
1592 | .ops = &iwl5000_ops, | |
1593 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, | |
0ef2ca67 TW |
1594 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1595 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
88804e2b WYG |
1596 | .num_of_queues = IWL50_NUM_QUEUES, |
1597 | .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, | |
47408639 | 1598 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1599 | .valid_tx_ant = ANT_B, |
1600 | .valid_rx_ant = ANT_AB, | |
fadb3582 BC |
1601 | .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, |
1602 | .set_l0s = true, | |
1603 | .use_bsm = false, | |
b261793d | 1604 | .ht_greenfield_support = true, |
f2d0d0e2 | 1605 | .led_compensation = 51, |
d8c07e7a | 1606 | .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, |
47408639 EK |
1607 | }; |
1608 | ||
1609 | struct iwl_cfg iwl5100_abg_cfg = { | |
1610 | .name = "5100ABG", | |
a0987a8d RC |
1611 | .fw_name_pre = IWL5000_FW_PRE, |
1612 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1613 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
47408639 EK |
1614 | .sku = IWL_SKU_A|IWL_SKU_G, |
1615 | .ops = &iwl5000_ops, | |
1616 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, | |
0ef2ca67 TW |
1617 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1618 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
88804e2b WYG |
1619 | .num_of_queues = IWL50_NUM_QUEUES, |
1620 | .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, | |
47408639 | 1621 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1622 | .valid_tx_ant = ANT_B, |
1623 | .valid_rx_ant = ANT_AB, | |
fadb3582 BC |
1624 | .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, |
1625 | .set_l0s = true, | |
1626 | .use_bsm = false, | |
b261793d | 1627 | .ht_greenfield_support = true, |
f2d0d0e2 | 1628 | .led_compensation = 51, |
d8c07e7a | 1629 | .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, |
47408639 EK |
1630 | }; |
1631 | ||
5a6a256e TW |
1632 | struct iwl_cfg iwl5100_agn_cfg = { |
1633 | .name = "5100AGN", | |
a0987a8d RC |
1634 | .fw_name_pre = IWL5000_FW_PRE, |
1635 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1636 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
5a6a256e | 1637 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
da8dec29 | 1638 | .ops = &iwl5000_ops, |
25ae3986 | 1639 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
1640 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1641 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
88804e2b WYG |
1642 | .num_of_queues = IWL50_NUM_QUEUES, |
1643 | .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, | |
5a6a256e | 1644 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1645 | .valid_tx_ant = ANT_B, |
1646 | .valid_rx_ant = ANT_AB, | |
fadb3582 BC |
1647 | .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, |
1648 | .set_l0s = true, | |
1649 | .use_bsm = false, | |
b261793d | 1650 | .ht_greenfield_support = true, |
f2d0d0e2 | 1651 | .led_compensation = 51, |
d8c07e7a | 1652 | .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, |
5a6a256e TW |
1653 | }; |
1654 | ||
1655 | struct iwl_cfg iwl5350_agn_cfg = { | |
1656 | .name = "5350AGN", | |
a0987a8d RC |
1657 | .fw_name_pre = IWL5000_FW_PRE, |
1658 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1659 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
5a6a256e | 1660 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
da8dec29 | 1661 | .ops = &iwl5000_ops, |
25ae3986 | 1662 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
1663 | .eeprom_ver = EEPROM_5050_EEPROM_VERSION, |
1664 | .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, | |
88804e2b WYG |
1665 | .num_of_queues = IWL50_NUM_QUEUES, |
1666 | .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, | |
5a6a256e | 1667 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1668 | .valid_tx_ant = ANT_ABC, |
1669 | .valid_rx_ant = ANT_ABC, | |
fadb3582 BC |
1670 | .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, |
1671 | .set_l0s = true, | |
1672 | .use_bsm = false, | |
b261793d | 1673 | .ht_greenfield_support = true, |
f2d0d0e2 | 1674 | .led_compensation = 51, |
d8c07e7a | 1675 | .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, |
5a6a256e TW |
1676 | }; |
1677 | ||
7100e924 TW |
1678 | struct iwl_cfg iwl5150_agn_cfg = { |
1679 | .name = "5150AGN", | |
a0987a8d RC |
1680 | .fw_name_pre = IWL5150_FW_PRE, |
1681 | .ucode_api_max = IWL5150_UCODE_API_MAX, | |
1682 | .ucode_api_min = IWL5150_UCODE_API_MIN, | |
7100e924 | 1683 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
62161aef | 1684 | .ops = &iwl5150_ops, |
7100e924 | 1685 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
fd63edba TW |
1686 | .eeprom_ver = EEPROM_5050_EEPROM_VERSION, |
1687 | .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, | |
88804e2b WYG |
1688 | .num_of_queues = IWL50_NUM_QUEUES, |
1689 | .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, | |
7100e924 | 1690 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1691 | .valid_tx_ant = ANT_A, |
1692 | .valid_rx_ant = ANT_AB, | |
fadb3582 BC |
1693 | .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL, |
1694 | .set_l0s = true, | |
1695 | .use_bsm = false, | |
b261793d | 1696 | .ht_greenfield_support = true, |
f2d0d0e2 | 1697 | .led_compensation = 51, |
d8c07e7a | 1698 | .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, |
7100e924 TW |
1699 | }; |
1700 | ||
a0987a8d RC |
1701 | MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX)); |
1702 | MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX)); | |
c9f79ed2 | 1703 | |
4e30cb69 | 1704 | module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO); |
5a6a256e TW |
1705 | MODULE_PARM_DESC(swcrypto50, |
1706 | "using software crypto engine (default 0 [hardware])\n"); | |
4e30cb69 | 1707 | module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO); |
5a6a256e | 1708 | MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); |
4e30cb69 | 1709 | module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO); |
49779293 | 1710 | MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality"); |
4e30cb69 WYG |
1711 | module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, |
1712 | int, S_IRUGO); | |
5a6a256e | 1713 | MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); |
4e30cb69 | 1714 | module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO); |
3a1081e8 | 1715 | MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); |