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iwlwifi: enable packet injection for iwl3945
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
CommitLineData
5a6a256e
TW		 1/******************************************************************************
2 *
3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/version.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <net/mac80211.h>
37#include <linux/etherdevice.h>
38#include <asm/unaligned.h>
39
40#include "iwl-eeprom.h"
3e0d4cb1 41#include "iwl-dev.h"
5a6a256e
TW		 42#include "iwl-core.h"
43#include "iwl-io.h"
e26e47d9 44#include "iwl-sta.h"
5a6a256e
TW		 45#include "iwl-helpers.h"
46#include "iwl-5000-hw.h"
47
48#define IWL5000_UCODE_API "-1"
49
99da1b48
RR		 50static const u16 iwl5000_default_queue_to_tx_fifo[] = {
51 IWL_TX_FIFO_AC3,
52 IWL_TX_FIFO_AC2,
53 IWL_TX_FIFO_AC1,
54 IWL_TX_FIFO_AC0,
55 IWL50_CMD_FIFO_NUM,
56 IWL_TX_FIFO_HCCA_1,
57 IWL_TX_FIFO_HCCA_2
58};
59
46315e01
TW		 60/* FIXME: same implementation as 4965 */
61static int iwl5000_apm_stop_master(struct iwl_priv *priv)
62{
63 int ret = 0;
64 unsigned long flags;
65
66 spin_lock_irqsave(&priv->lock, flags);
67
68 /* set stop master bit */
69 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
70
71 ret = iwl_poll_bit(priv, CSR_RESET,
72 CSR_RESET_REG_FLAG_MASTER_DISABLED,
73 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
74 if (ret < 0)
75 goto out;
76
77out:
78 spin_unlock_irqrestore(&priv->lock, flags);
79 IWL_DEBUG_INFO("stop master\n");
80
81 return ret;
82}
83
84
30d59260
TW		 85static int iwl5000_apm_init(struct iwl_priv *priv)
86{
87 int ret = 0;
88
89 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
90 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
91
8f061891
TW		 92 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
93 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
94 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
95
30d59260
TW		 96 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
97
98 /* set "initialization complete" bit to move adapter
99 * D0U* --> D0A* state */
100 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
101
102 /* wait for clock stabilization */
103 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
104 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
105 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
106 if (ret < 0) {
107 IWL_DEBUG_INFO("Failed to init the card\n");
108 return ret;
109 }
110
111 ret = iwl_grab_nic_access(priv);
112 if (ret)
113 return ret;
114
115 /* enable DMA */
8f061891 116 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
30d59260
TW		 117
118 udelay(20);
119
8f061891 120 /* disable L1-Active */
30d59260 121 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
8f061891 122 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
30d59260
TW		 123
124 iwl_release_nic_access(priv);
125
126 return ret;
127}
128
f118a91d
TW		 129/* FIXME: this is indentical to 4965 */
130static void iwl5000_apm_stop(struct iwl_priv *priv)
131{
132 unsigned long flags;
133
46315e01 134 iwl5000_apm_stop_master(priv);
f118a91d
TW		 135
136 spin_lock_irqsave(&priv->lock, flags);
137
138 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
139
140 udelay(10);
141
142 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
143
144 spin_unlock_irqrestore(&priv->lock, flags);
145}
146
147
7f066108
TW		 148static int iwl5000_apm_reset(struct iwl_priv *priv)
149{
150 int ret = 0;
151 unsigned long flags;
152
46315e01 153 iwl5000_apm_stop_master(priv);
7f066108
TW		 154
155 spin_lock_irqsave(&priv->lock, flags);
156
157 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
158
159 udelay(10);
160
161
162 /* FIXME: put here L1A -L0S w/a */
163
164 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
165
166 /* set "initialization complete" bit to move adapter
167 * D0U* --> D0A* state */
168 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
169
170 /* wait for clock stabilization */
171 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
172 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
173 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
174 if (ret < 0) {
175 IWL_DEBUG_INFO("Failed to init the card\n");
176 goto out;
177 }
178
179 ret = iwl_grab_nic_access(priv);
180 if (ret)
181 goto out;
182
183 /* enable DMA */
184 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
185
186 udelay(20);
187
188 /* disable L1-Active */
189 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
190 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
191
192 iwl_release_nic_access(priv);
193
194out:
195 spin_unlock_irqrestore(&priv->lock, flags);
196
197 return ret;
198}
199
200
5a835353 201static void iwl5000_nic_config(struct iwl_priv *priv)
e86fe9f6
TW		 202{
203 unsigned long flags;
204 u16 radio_cfg;
205 u8 val_link;
206
207 spin_lock_irqsave(&priv->lock, flags);
208
209 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
210
8f061891
TW		 211 /* L1 is enabled by BIOS */
212 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
213 /* diable L0S disabled L1A enabled */
214 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
215 else
216 /* L0S enabled L1A disabled */
217 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
e86fe9f6
TW		 218
219 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
220
221 /* write radio config values to register */
222 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
223 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
224 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
225 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
226 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
227
228 /* set CSR_HW_CONFIG_REG for uCode use */
229 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
230 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
231 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
232
233 spin_unlock_irqrestore(&priv->lock, flags);
234}
235
236
237
25ae3986
TW		 238/*
239 * EEPROM
240 */
241static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
242{
243 u16 offset = 0;
244
245 if ((address & INDIRECT_ADDRESS) == 0)
246 return address;
247
248 switch (address & INDIRECT_TYPE_MSK) {
249 case INDIRECT_HOST:
250 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
251 break;
252 case INDIRECT_GENERAL:
253 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
254 break;
255 case INDIRECT_REGULATORY:
256 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
257 break;
258 case INDIRECT_CALIBRATION:
259 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
260 break;
261 case INDIRECT_PROCESS_ADJST:
262 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
263 break;
264 case INDIRECT_OTHERS:
265 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
266 break;
267 default:
268 IWL_ERROR("illegal indirect type: 0x%X\n",
269 address & INDIRECT_TYPE_MSK);
270 break;
271 }
272
273 /* translate the offset from words to byte */
274 return (address & ADDRESS_MSK) + (offset << 1);
275}
276
f1f69415
TW		 277static int iwl5000_eeprom_check_version(struct iwl_priv *priv)
278{
279 u16 eeprom_ver;
280 struct iwl_eeprom_calib_hdr {
281 u8 version;
282 u8 pa_type;
283 u16 voltage;
284 } *hdr;
285
286 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
287
288 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
289 EEPROM_5000_CALIB_ALL);
290
291 if (eeprom_ver < EEPROM_5000_EEPROM_VERSION ||
292 hdr->version < EEPROM_5000_TX_POWER_VERSION)
293 goto err;
294
295 return 0;
296err:
297 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
298 eeprom_ver, EEPROM_5000_EEPROM_VERSION,
299 hdr->version, EEPROM_5000_TX_POWER_VERSION);
300 return -EINVAL;
301
302}
303
33fd5033
EG		 304static void iwl5000_gain_computation(struct iwl_priv *priv,
305 u32 average_noise[NUM_RX_CHAINS],
306 u16 min_average_noise_antenna_i,
307 u32 min_average_noise)
308{
309 int i;
310 s32 delta_g;
311 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
312
313 /* Find Gain Code for the antennas B and C */
314 for (i = 1; i < NUM_RX_CHAINS; i++) {
315 if ((data->disconn_array[i])) {
316 data->delta_gain_code[i] = 0;
317 continue;
318 }
319 delta_g = (1000 * ((s32)average_noise[0] -
320 (s32)average_noise[i])) / 1500;
321 /* bound gain by 2 bits value max, 3rd bit is sign */
322 data->delta_gain_code[i] =
323 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
324
325 if (delta_g < 0)
326 /* set negative sign */
327 data->delta_gain_code[i] |= (1 << 2);
328 }
329
330 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
331 data->delta_gain_code[1], data->delta_gain_code[2]);
332
333 if (!data->radio_write) {
334 struct iwl5000_calibration_chain_noise_gain_cmd cmd;
335 memset(&cmd, 0, sizeof(cmd));
336
337 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
338 cmd.delta_gain_1 = data->delta_gain_code[1];
339 cmd.delta_gain_2 = data->delta_gain_code[2];
340 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
341 sizeof(cmd), &cmd, NULL);
342
343 data->radio_write = 1;
344 data->state = IWL_CHAIN_NOISE_CALIBRATED;
345 }
346
347 data->chain_noise_a = 0;
348 data->chain_noise_b = 0;
349 data->chain_noise_c = 0;
350 data->chain_signal_a = 0;
351 data->chain_signal_b = 0;
352 data->chain_signal_c = 0;
353 data->beacon_count = 0;
354}
355
356static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
357{
358 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
359
360 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
361 struct iwl5000_calibration_chain_noise_reset_cmd cmd;
362
363 memset(&cmd, 0, sizeof(cmd));
364 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
365 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
366 sizeof(cmd), &cmd))
367 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
368 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
369 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
370 }
371}
372
373static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
374 .min_nrg_cck = 95,
375 .max_nrg_cck = 0,
376 .auto_corr_min_ofdm = 90,
377 .auto_corr_min_ofdm_mrc = 170,
378 .auto_corr_min_ofdm_x1 = 120,
379 .auto_corr_min_ofdm_mrc_x1 = 240,
380
381 .auto_corr_max_ofdm = 120,
382 .auto_corr_max_ofdm_mrc = 210,
383 .auto_corr_max_ofdm_x1 = 155,
384 .auto_corr_max_ofdm_mrc_x1 = 290,
385
386 .auto_corr_min_cck = 125,
387 .auto_corr_max_cck = 200,
388 .auto_corr_min_cck_mrc = 170,
389 .auto_corr_max_cck_mrc = 400,
390 .nrg_th_cck = 95,
391 .nrg_th_ofdm = 95,
392};
393
25ae3986
TW		 394static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
395 size_t offset)
396{
397 u32 address = eeprom_indirect_address(priv, offset);
398 BUG_ON(address >= priv->cfg->eeprom_size);
399 return &priv->eeprom[address];
400}
401
7c616cba
TW		 402/*
403 * Calibration
404 */
405static int iwl5000_send_Xtal_calib(struct iwl_priv *priv)
406{
407 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
408
409 struct iwl5000_calibration cal_cmd = {
410 .op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD,
411 .data = {
412 (u8)xtal_calib[0],
413 (u8)xtal_calib[1],
414 }
415 };
416
417 return iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
418 sizeof(cal_cmd), &cal_cmd);
419}
420
421static int iwl5000_send_calib_results(struct iwl_priv *priv)
422{
423 int ret = 0;
424
d2f18bfd
EG		 425 struct iwl_host_cmd hcmd = {
426 .id = REPLY_PHY_CALIBRATION_CMD,
427 .meta.flags = CMD_SIZE_HUGE,
428 };
7c616cba 429
d2f18bfd
EG		 430 if (priv->calib_results.lo_res) {
431 hcmd.len = priv->calib_results.lo_res_len;
432 hcmd.data = priv->calib_results.lo_res;
433 ret = iwl_send_cmd_sync(priv, &hcmd);
7c616cba 434
d2f18bfd
EG		 435 if (ret)
436 goto err;
437 }
7c616cba 438
d2f18bfd
EG		 439 if (priv->calib_results.tx_iq_res) {
440 hcmd.len = priv->calib_results.tx_iq_res_len;
441 hcmd.data = priv->calib_results.tx_iq_res;
442 ret = iwl_send_cmd_sync(priv, &hcmd);
7c616cba 443
d2f18bfd
EG		 444 if (ret)
445 goto err;
446 }
447
448 if (priv->calib_results.tx_iq_perd_res) {
449 hcmd.len = priv->calib_results.tx_iq_perd_res_len;
450 hcmd.data = priv->calib_results.tx_iq_perd_res;
451 ret = iwl_send_cmd_sync(priv, &hcmd);
452
453 if (ret)
454 goto err;
455 }
7c616cba
TW		 456
457 return 0;
458err:
459 IWL_ERROR("Error %d\n", ret);
460 return ret;
461}
462
463static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
464{
465 struct iwl5000_calib_cfg_cmd calib_cfg_cmd;
466 struct iwl_host_cmd cmd = {
467 .id = CALIBRATION_CFG_CMD,
468 .len = sizeof(struct iwl5000_calib_cfg_cmd),
469 .data = &calib_cfg_cmd,
470 };
471
472 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
473 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
474 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
475 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
476 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
477
478 return iwl_send_cmd(priv, &cmd);
479}
480
481static void iwl5000_rx_calib_result(struct iwl_priv *priv,
482 struct iwl_rx_mem_buffer *rxb)
483{
484 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
485 struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw;
486 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
487
488 iwl_free_calib_results(priv);
489
490 /* reduce the size of the length field itself */
491 len -= 4;
492
493 switch (hdr->op_code) {
494 case IWL5000_PHY_CALIBRATE_LO_CMD:
495 priv->calib_results.lo_res = kzalloc(len, GFP_ATOMIC);
496 priv->calib_results.lo_res_len = len;
497 memcpy(priv->calib_results.lo_res, pkt->u.raw, len);
498 break;
499 case IWL5000_PHY_CALIBRATE_TX_IQ_CMD:
500 priv->calib_results.tx_iq_res = kzalloc(len, GFP_ATOMIC);
501 priv->calib_results.tx_iq_res_len = len;
502 memcpy(priv->calib_results.tx_iq_res, pkt->u.raw, len);
503 break;
504 case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD:
505 priv->calib_results.tx_iq_perd_res = kzalloc(len, GFP_ATOMIC);
506 priv->calib_results.tx_iq_perd_res_len = len;
507 memcpy(priv->calib_results.tx_iq_perd_res, pkt->u.raw, len);
508 break;
509 default:
510 IWL_ERROR("Unknown calibration notification %d\n",
511 hdr->op_code);
512 return;
513 }
514}
515
516static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
517 struct iwl_rx_mem_buffer *rxb)
518{
519 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
520 queue_work(priv->workqueue, &priv->restart);
521}
522
dbb983b7
RR		 523/*
524 * ucode
525 */
526static int iwl5000_load_section(struct iwl_priv *priv,
527 struct fw_desc *image,
528 u32 dst_addr)
529{
530 int ret = 0;
531 unsigned long flags;
532
533 dma_addr_t phy_addr = image->p_addr;
534 u32 byte_cnt = image->len;
535
536 spin_lock_irqsave(&priv->lock, flags);
537 ret = iwl_grab_nic_access(priv);
538 if (ret) {
539 spin_unlock_irqrestore(&priv->lock, flags);
540 return ret;
541 }
542
543 iwl_write_direct32(priv,
544 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
545 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
546
547 iwl_write_direct32(priv,
548 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
549
550 iwl_write_direct32(priv,
551 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
552 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
553
554 /* FIME: write the MSB of the phy_addr in CTRL1
555 * iwl_write_direct32(priv,
556 IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL),
557 ((phy_addr & MSB_MSK)
558 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count);
559 */
560 iwl_write_direct32(priv,
561 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt);
562 iwl_write_direct32(priv,
563 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
564 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
565 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
566 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
567
568 iwl_write_direct32(priv,
569 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
570 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
571 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
572 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
573
574 iwl_release_nic_access(priv);
575 spin_unlock_irqrestore(&priv->lock, flags);
576 return 0;
577}
578
579static int iwl5000_load_given_ucode(struct iwl_priv *priv,
580 struct fw_desc *inst_image,
581 struct fw_desc *data_image)
582{
583 int ret = 0;
584
585 ret = iwl5000_load_section(
586 priv, inst_image, RTC_INST_LOWER_BOUND);
587 if (ret)
588 return ret;
589
590 IWL_DEBUG_INFO("INST uCode section being loaded...\n");
591 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
592 priv->ucode_write_complete, 5 * HZ);
593 if (ret == -ERESTARTSYS) {
594 IWL_ERROR("Could not load the INST uCode section due "
595 "to interrupt\n");
596 return ret;
597 }
598 if (!ret) {
599 IWL_ERROR("Could not load the INST uCode section\n");
600 return -ETIMEDOUT;
601 }
602
603 priv->ucode_write_complete = 0;
604
605 ret = iwl5000_load_section(
606 priv, data_image, RTC_DATA_LOWER_BOUND);
607 if (ret)
608 return ret;
609
610 IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
611
612 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
613 priv->ucode_write_complete, 5 * HZ);
614 if (ret == -ERESTARTSYS) {
615 IWL_ERROR("Could not load the INST uCode section due "
616 "to interrupt\n");
617 return ret;
618 } else if (!ret) {
619 IWL_ERROR("Could not load the DATA uCode section\n");
620 return -ETIMEDOUT;
621 } else
622 ret = 0;
623
624 priv->ucode_write_complete = 0;
625
626 return ret;
627}
628
629static int iwl5000_load_ucode(struct iwl_priv *priv)
630{
631 int ret = 0;
632
633 /* check whether init ucode should be loaded, or rather runtime ucode */
634 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
635 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
636 ret = iwl5000_load_given_ucode(priv,
637 &priv->ucode_init, &priv->ucode_init_data);
638 if (!ret) {
639 IWL_DEBUG_INFO("Init ucode load complete.\n");
640 priv->ucode_type = UCODE_INIT;
641 }
642 } else {
643 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
644 "Loading runtime ucode...\n");
645 ret = iwl5000_load_given_ucode(priv,
646 &priv->ucode_code, &priv->ucode_data);
647 if (!ret) {
648 IWL_DEBUG_INFO("Runtime ucode load complete.\n");
649 priv->ucode_type = UCODE_RT;
650 }
651 }
652
653 return ret;
654}
655
99da1b48
RR		 656static void iwl5000_init_alive_start(struct iwl_priv *priv)
657{
658 int ret = 0;
659
660 /* Check alive response for "valid" sign from uCode */
661 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
662 /* We had an error bringing up the hardware, so take it
663 * all the way back down so we can try again */
664 IWL_DEBUG_INFO("Initialize Alive failed.\n");
665 goto restart;
666 }
667
668 /* initialize uCode was loaded... verify inst image.
669 * This is a paranoid check, because we would not have gotten the
670 * "initialize" alive if code weren't properly loaded. */
671 if (iwl_verify_ucode(priv)) {
672 /* Runtime instruction load was bad;
673 * take it all the way back down so we can try again */
674 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
675 goto restart;
676 }
677
37deb2a0 678 iwl_clear_stations_table(priv);
99da1b48
RR		 679 ret = priv->cfg->ops->lib->alive_notify(priv);
680 if (ret) {
681 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
682 goto restart;
683 }
684
7c616cba 685 iwl5000_send_calib_cfg(priv);
99da1b48
RR		 686 return;
687
688restart:
689 /* real restart (first load init_ucode) */
690 queue_work(priv->workqueue, &priv->restart);
691}
692
693static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
694 int txq_id, u32 index)
695{
696 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
697 (index & 0xff) | (txq_id << 8));
698 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
699}
700
701static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
702 struct iwl_tx_queue *txq,
703 int tx_fifo_id, int scd_retry)
704{
705 int txq_id = txq->q.id;
706 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
707
708 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
709 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
710 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
711 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
712 IWL50_SCD_QUEUE_STTS_REG_MSK);
713
714 txq->sched_retry = scd_retry;
715
716 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
717 active ? "Activate" : "Deactivate",
718 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
719}
720
9636e583
RR		 721static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
722{
723 struct iwl_wimax_coex_cmd coex_cmd;
724
725 memset(&coex_cmd, 0, sizeof(coex_cmd));
726
727 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
728 sizeof(coex_cmd), &coex_cmd);
729}
730
99da1b48
RR		 731static int iwl5000_alive_notify(struct iwl_priv *priv)
732{
733 u32 a;
734 int i = 0;
735 unsigned long flags;
736 int ret;
737
738 spin_lock_irqsave(&priv->lock, flags);
739
740 ret = iwl_grab_nic_access(priv);
741 if (ret) {
742 spin_unlock_irqrestore(&priv->lock, flags);
743 return ret;
744 }
745
746 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
747 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
748 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
749 a += 4)
750 iwl_write_targ_mem(priv, a, 0);
751 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
752 a += 4)
753 iwl_write_targ_mem(priv, a, 0);
754 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
755 iwl_write_targ_mem(priv, a, 0);
756
757 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
758 (priv->shared_phys +
759 offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
760 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
761 IWL50_SCD_QUEUECHAIN_SEL_ALL(
762 priv->hw_params.max_txq_num));
763 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
764
765 /* initiate the queues */
766 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
767 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
768 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
769 iwl_write_targ_mem(priv, priv->scd_base_addr +
770 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
771 iwl_write_targ_mem(priv, priv->scd_base_addr +
772 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
773 sizeof(u32),
774 ((SCD_WIN_SIZE <<
775 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
776 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
777 ((SCD_FRAME_LIMIT <<
778 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
779 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
780 }
781
782 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
da1bc453 783 IWL_MASK(0, priv->hw_params.max_txq_num));
99da1b48 784
da1bc453
TW		 785 /* Activate all Tx DMA/FIFO channels */
786 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
99da1b48
RR		 787
788 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
789 /* map qos queues to fifos one-to-one */
790 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
791 int ac = iwl5000_default_queue_to_tx_fifo[i];
792 iwl_txq_ctx_activate(priv, i);
793 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
794 }
795 /* TODO - need to initialize those FIFOs inside the loop above,
796 * not only mark them as active */
797 iwl_txq_ctx_activate(priv, 4);
798 iwl_txq_ctx_activate(priv, 7);
799 iwl_txq_ctx_activate(priv, 8);
800 iwl_txq_ctx_activate(priv, 9);
801
802 iwl_release_nic_access(priv);
803 spin_unlock_irqrestore(&priv->lock, flags);
804
7c616cba 805
9636e583
RR		 806 iwl5000_send_wimax_coex(priv);
807
7c616cba
TW		 808 iwl5000_send_Xtal_calib(priv);
809
0a078ffa 810 if (priv->ucode_type == UCODE_RT)
7c616cba
TW		 811 iwl5000_send_calib_results(priv);
812
99da1b48
RR		 813 return 0;
814}
815
fdd3e8a4
TW		 816static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
817{
818 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
819 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
820 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
821 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
822 return -EINVAL;
823 }
25ae3986 824
fdd3e8a4 825 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
7f3e4bb6 826 priv->hw_params.first_ampdu_q = IWL50_FIRST_AMPDU_QUEUE;
fdd3e8a4
TW		 827 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
828 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
829 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
830 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
da154e30 831 priv->hw_params.max_bsm_size = 0;
fdd3e8a4
TW		 832 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
833 BIT(IEEE80211_BAND_5GHZ);
33fd5033 834 priv->hw_params.sens = &iwl5000_sensitivity;
fdd3e8a4
TW		 835
836 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
837 case CSR_HW_REV_TYPE_5100:
838 case CSR_HW_REV_TYPE_5150:
839 priv->hw_params.tx_chains_num = 1;
840 priv->hw_params.rx_chains_num = 2;
841 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */
1179f18d
TW		 842 priv->hw_params.valid_tx_ant = ANT_A;
843 priv->hw_params.valid_rx_ant = ANT_AB;
fdd3e8a4
TW		 844 break;
845 case CSR_HW_REV_TYPE_5300:
846 case CSR_HW_REV_TYPE_5350:
847 priv->hw_params.tx_chains_num = 3;
848 priv->hw_params.rx_chains_num = 3;
1179f18d
TW		 849 priv->hw_params.valid_tx_ant = ANT_ABC;
850 priv->hw_params.valid_rx_ant = ANT_ABC;
fdd3e8a4
TW		 851 break;
852 }
c031bf80
EG		 853
854 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
855 case CSR_HW_REV_TYPE_5100:
856 case CSR_HW_REV_TYPE_5300:
857 /* 5X00 wants in Celsius */
858 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
859 break;
860 case CSR_HW_REV_TYPE_5150:
861 case CSR_HW_REV_TYPE_5350:
862 /* 5X50 wants in Kelvin */
863 priv->hw_params.ct_kill_threshold =
864 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
865 break;
866 }
867
fdd3e8a4
TW		 868 return 0;
869}
d4100dd9
RR		 870
871static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
872{
873 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
874 sizeof(struct iwl5000_shared),
875 &priv->shared_phys);
876 if (!priv->shared_virt)
877 return -ENOMEM;
878
879 memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
880
d67f5489
RR		 881 priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
882
d4100dd9
RR		 883 return 0;
884}
885
886static void iwl5000_free_shared_mem(struct iwl_priv *priv)
887{
888 if (priv->shared_virt)
889 pci_free_consistent(priv->pci_dev,
890 sizeof(struct iwl5000_shared),
891 priv->shared_virt,
892 priv->shared_phys);
893}
894
d67f5489
RR		 895static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
896{
897 struct iwl5000_shared *s = priv->shared_virt;
898 return le32_to_cpu(s->rb_closed) & 0xFFF;
899}
900
7839fc03
EG		 901/**
902 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
903 */
904static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 905 struct iwl_tx_queue *txq,
7839fc03
EG		 906 u16 byte_cnt)
907{
908 struct iwl5000_shared *shared_data = priv->shared_virt;
909 int txq_id = txq->q.id;
910 u8 sec_ctl = 0;
911 u8 sta = 0;
912 int len;
913
914 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
915
916 if (txq_id != IWL_CMD_QUEUE_NUM) {
917 sta = txq->cmd[txq->q.write_ptr].cmd.tx.sta_id;
918 sec_ctl = txq->cmd[txq->q.write_ptr].cmd.tx.sec_ctl;
919
920 switch (sec_ctl & TX_CMD_SEC_MSK) {
921 case TX_CMD_SEC_CCM:
922 len += CCMP_MIC_LEN;
923 break;
924 case TX_CMD_SEC_TKIP:
925 len += TKIP_ICV_LEN;
926 break;
927 case TX_CMD_SEC_WEP:
928 len += WEP_IV_LEN + WEP_ICV_LEN;
929 break;
930 }
931 }
932
933 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
934 tfd_offset[txq->q.write_ptr], byte_cnt, len);
935
936 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
937 tfd_offset[txq->q.write_ptr], sta_id, sta);
938
939 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
940 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
941 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
942 byte_cnt, len);
943 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
944 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
945 sta_id, sta);
946 }
947}
948
972cf447
TW		 949static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
950 struct iwl_tx_queue *txq)
951{
952 int txq_id = txq->q.id;
953 struct iwl5000_shared *shared_data = priv->shared_virt;
954 u8 sta = 0;
955
956 if (txq_id != IWL_CMD_QUEUE_NUM)
957 sta = txq->cmd[txq->q.read_ptr].cmd.tx.sta_id;
958
959 shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr].
960 val = cpu_to_le16(1 | (sta << 12));
961
962 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
963 shared_data->queues_byte_cnt_tbls[txq_id].
964 tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr].
965 val = cpu_to_le16(1 | (sta << 12));
966 }
967}
968
e26e47d9
TW		 969static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
970 u16 txq_id)
971{
972 u32 tbl_dw_addr;
973 u32 tbl_dw;
974 u16 scd_q2ratid;
975
976 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
977
978 tbl_dw_addr = priv->scd_base_addr +
979 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
980
981 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
982
983 if (txq_id & 0x1)
984 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
985 else
986 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
987
988 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
989
990 return 0;
991}
992static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
993{
994 /* Simply stop the queue, but don't change any configuration;
995 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
996 iwl_write_prph(priv,
997 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
998 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
999 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1000}
1001
1002static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1003 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1004{
1005 unsigned long flags;
1006 int ret;
1007 u16 ra_tid;
1008
1009 if (IWL50_FIRST_AMPDU_QUEUE > txq_id)
1010 IWL_WARNING("queue number too small: %d, must be > %d\n",
1011 txq_id, IWL50_FIRST_AMPDU_QUEUE);
1012
1013 ra_tid = BUILD_RAxTID(sta_id, tid);
1014
1015 /* Modify device's station table to Tx this TID */
1016 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
1017
1018 spin_lock_irqsave(&priv->lock, flags);
1019 ret = iwl_grab_nic_access(priv);
1020 if (ret) {
1021 spin_unlock_irqrestore(&priv->lock, flags);
1022 return ret;
1023 }
1024
1025 /* Stop this Tx queue before configuring it */
1026 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1027
1028 /* Map receiver-address / traffic-ID to this queue */
1029 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1030
1031 /* Set this queue as a chain-building queue */
1032 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1033
1034 /* enable aggregations for the queue */
1035 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1036
1037 /* Place first TFD at index corresponding to start sequence number.
1038 * Assumes that ssn_idx is valid (!= 0xFFF) */
1039 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1040 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1041 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1042
1043 /* Set up Tx window size and frame limit for this queue */
1044 iwl_write_targ_mem(priv, priv->scd_base_addr +
1045 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1046 sizeof(u32),
1047 ((SCD_WIN_SIZE <<
1048 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1049 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1050 ((SCD_FRAME_LIMIT <<
1051 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1052 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1053
1054 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1055
1056 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1057 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1058
1059 iwl_release_nic_access(priv);
1060 spin_unlock_irqrestore(&priv->lock, flags);
1061
1062 return 0;
1063}
1064
1065static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1066 u16 ssn_idx, u8 tx_fifo)
1067{
1068 int ret;
1069
1070 if (IWL50_FIRST_AMPDU_QUEUE > txq_id) {
1071 IWL_WARNING("queue number too small: %d, must be > %d\n",
1072 txq_id, IWL50_FIRST_AMPDU_QUEUE);
1073 return -EINVAL;
1074 }
1075
1076 ret = iwl_grab_nic_access(priv);
1077 if (ret)
1078 return ret;
1079
1080 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1081
1082 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1083
1084 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1085 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1086 /* supposes that ssn_idx is valid (!= 0xFFF) */
1087 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1088
1089 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1090 iwl_txq_ctx_deactivate(priv, txq_id);
1091 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1092
1093 iwl_release_nic_access(priv);
1094
1095 return 0;
1096}
1097
2469bf2e
TW		 1098static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1099{
1100 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1101 memcpy(data, cmd, size);
1102 return size;
1103}
1104
1105
da1bc453
TW		 1106/*
1107 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
1108 * must be called under priv->lock and mac access
1109 */
1110static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
5a676bbe 1111{
da1bc453 1112 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
5a676bbe
RR		 1113}
1114
e532fa0e
RR		 1115
1116static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1117{
25a6572c
TW		 1118 return le32_to_cpup((__le32*)&tx_resp->status +
1119 tx_resp->frame_count) & MAX_SN;
e532fa0e
RR		 1120}
1121
1122static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1123 struct iwl_ht_agg *agg,
1124 struct iwl5000_tx_resp *tx_resp,
25a6572c 1125 int txq_id, u16 start_idx)
e532fa0e
RR		 1126{
1127 u16 status;
1128 struct agg_tx_status *frame_status = &tx_resp->status;
1129 struct ieee80211_tx_info *info = NULL;
1130 struct ieee80211_hdr *hdr = NULL;
e7d326ac 1131 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 1132 int i, sh, idx;
e532fa0e
RR		 1133 u16 seq;
1134
1135 if (agg->wait_for_ba)
1136 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1137
1138 agg->frame_count = tx_resp->frame_count;
1139 agg->start_idx = start_idx;
e7d326ac 1140 agg->rate_n_flags = rate_n_flags;
e532fa0e
RR		 1141 agg->bitmap = 0;
1142
1143 /* # frames attempted by Tx command */
1144 if (agg->frame_count == 1) {
1145 /* Only one frame was attempted; no block-ack will arrive */
1146 status = le16_to_cpu(frame_status[0].status);
25a6572c 1147 idx = start_idx;
e532fa0e
RR		 1148
1149 /* FIXME: code repetition */
1150 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1151 agg->frame_count, agg->start_idx, idx);
1152
1153 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1154 info->status.retry_count = tx_resp->failure_frame;
1155 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1156 info->flags |= iwl_is_tx_success(status)?
1157 IEEE80211_TX_STAT_ACK : 0;
e7d326ac
TW		 1158 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1159
e532fa0e
RR		 1160 /* FIXME: code repetition end */
1161
1162 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1163 status & 0xff, tx_resp->failure_frame);
e7d326ac 1164 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
e532fa0e
RR		 1165
1166 agg->wait_for_ba = 0;
1167 } else {
1168 /* Two or more frames were attempted; expect block-ack */
1169 u64 bitmap = 0;
1170 int start = agg->start_idx;
1171
1172 /* Construct bit-map of pending frames within Tx window */
1173 for (i = 0; i < agg->frame_count; i++) {
1174 u16 sc;
1175 status = le16_to_cpu(frame_status[i].status);
1176 seq = le16_to_cpu(frame_status[i].sequence);
1177 idx = SEQ_TO_INDEX(seq);
1178 txq_id = SEQ_TO_QUEUE(seq);
1179
1180 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1181 AGG_TX_STATE_ABORT_MSK))
1182 continue;
1183
1184 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1185 agg->frame_count, txq_id, idx);
1186
1187 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1188
1189 sc = le16_to_cpu(hdr->seq_ctrl);
1190 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1191 IWL_ERROR("BUG_ON idx doesn't match seq control"
1192 " idx=%d, seq_idx=%d, seq=%d\n",
1193 idx, SEQ_TO_SN(sc),
1194 hdr->seq_ctrl);
1195 return -1;
1196 }
1197
1198 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1199 i, idx, SEQ_TO_SN(sc));
1200
1201 sh = idx - start;
1202 if (sh > 64) {
1203 sh = (start - idx) + 0xff;
1204 bitmap = bitmap << sh;
1205 sh = 0;
1206 start = idx;
1207 } else if (sh < -64)
1208 sh = 0xff - (start - idx);
1209 else if (sh < 0) {
1210 sh = start - idx;
1211 start = idx;
1212 bitmap = bitmap << sh;
1213 sh = 0;
1214 }
1215 bitmap |= (1 << sh);
1216 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
1217 start, (u32)(bitmap & 0xFFFFFFFF));
1218 }
1219
1220 agg->bitmap = bitmap;
1221 agg->start_idx = start;
e532fa0e
RR		 1222 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1223 agg->frame_count, agg->start_idx,
1224 (unsigned long long)agg->bitmap);
1225
1226 if (bitmap)
1227 agg->wait_for_ba = 1;
1228 }
1229 return 0;
1230}
1231
1232static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1233 struct iwl_rx_mem_buffer *rxb)
1234{
1235 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1236 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1237 int txq_id = SEQ_TO_QUEUE(sequence);
1238 int index = SEQ_TO_INDEX(sequence);
1239 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1240 struct ieee80211_tx_info *info;
1241 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1242 u32 status = le16_to_cpu(tx_resp->status.status);
e532fa0e 1243 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
e532fa0e
RR		 1244 struct ieee80211_hdr *hdr;
1245 u8 *qc = NULL;
e532fa0e
RR		 1246
1247 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1248 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1249 "is out of range [0-%d] %d %d\n", txq_id,
1250 index, txq->q.n_bd, txq->q.write_ptr,
1251 txq->q.read_ptr);
1252 return;
1253 }
1254
1255 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1256 memset(&info->status, 0, sizeof(info->status));
1257
e532fa0e 1258 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
fd7c8a40
HH		 1259 if (ieee80211_is_data_qos(hdr->frame_control)) {
1260 qc = ieee80211_get_qos_ctl(hdr);
e532fa0e
RR		 1261 tid = qc[0] & 0xf;
1262 }
1263
1264 sta_id = iwl_get_ra_sta_id(priv, hdr);
1265 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
1266 IWL_ERROR("Station not known\n");
1267 return;
1268 }
1269
1270 if (txq->sched_retry) {
1271 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1272 struct iwl_ht_agg *agg = NULL;
1273
1274 if (!qc)
1275 return;
1276
1277 agg = &priv->stations[sta_id].tid[tid].agg;
1278
25a6572c 1279 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
e532fa0e
RR		 1280
1281 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) {
1282 /* TODO: send BAR */
1283 }
1284
1285 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1286 int freed, ampdu_q;
1287 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1288 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
1289 "%d index %d\n", scd_ssn , index);
17b88929 1290 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
e532fa0e
RR		 1291 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1292
1293 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1294 txq_id >= 0 && priv->mac80211_registered &&
1295 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
1296 /* calculate mac80211 ampdu sw queue to wake */
7f3e4bb6 1297 ampdu_q = txq_id - IWL50_FIRST_AMPDU_QUEUE +
e532fa0e
RR		 1298 priv->hw->queues;
1299 if (agg->state == IWL_AGG_OFF)
1300 ieee80211_wake_queue(priv->hw, txq_id);
1301 else
1302 ieee80211_wake_queue(priv->hw, ampdu_q);
1303 }
30e553e3 1304 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
e532fa0e
RR		 1305 }
1306 } else {
4f85f5b3
RR		 1307 info->status.retry_count = tx_resp->failure_frame;
1308 info->flags =
1309 iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
e7d326ac 1310 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 1311 le32_to_cpu(tx_resp->rate_n_flags),
1312 info);
1313
1314 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
1315 "0x%x retries %d\n", txq_id,
1316 iwl_get_tx_fail_reason(status),
1317 status, le32_to_cpu(tx_resp->rate_n_flags),
1318 tx_resp->failure_frame);
1319
1320 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
1321 if (index != -1) {
1322 int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1323 if (tid != MAX_TID_COUNT)
e532fa0e 1324 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
4f85f5b3 1325 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
e532fa0e
RR		 1326 (txq_id >= 0) && priv->mac80211_registered)
1327 ieee80211_wake_queue(priv->hw, txq_id);
4f85f5b3 1328 if (tid != MAX_TID_COUNT)
30e553e3 1329 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
4f85f5b3 1330 }
e532fa0e 1331 }
e532fa0e
RR		 1332
1333 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1334 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
1335}
1336
c1adf9fb
GG		 1337/* Currently 5000 is the supperset of everything */
1338static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1339{
1340 return len;
1341}
1342
203566f3
EG		 1343static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1344{
1345 /* in 5000 the tx power calibration is done in uCode */
1346 priv->disable_tx_power_cal = 1;
1347}
1348
b600e4e1
RR		 1349static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1350{
7c616cba
TW		 1351 /* init calibration handlers */
1352 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1353 iwl5000_rx_calib_result;
1354 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1355 iwl5000_rx_calib_complete;
e532fa0e 1356 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
b600e4e1
RR		 1357}
1358
7c616cba 1359
87283cc1
RR		 1360static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1361{
1362 return (addr >= RTC_DATA_LOWER_BOUND) &&
1363 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1364}
1365
fe7a90c2
RR		 1366static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1367{
1368 int ret = 0;
1369 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1370 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1371 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1372
1373 if ((rxon1->flags == rxon2->flags) &&
1374 (rxon1->filter_flags == rxon2->filter_flags) &&
1375 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1376 (rxon1->ofdm_ht_single_stream_basic_rates ==
1377 rxon2->ofdm_ht_single_stream_basic_rates) &&
1378 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1379 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1380 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1381 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1382 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1383 (rxon1->rx_chain == rxon2->rx_chain) &&
1384 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1385 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1386 return 0;
1387 }
1388
1389 rxon_assoc.flags = priv->staging_rxon.flags;
1390 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1391 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1392 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1393 rxon_assoc.reserved1 = 0;
1394 rxon_assoc.reserved2 = 0;
1395 rxon_assoc.reserved3 = 0;
1396 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1397 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1398 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1399 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1400 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1401 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1402 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1403 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1404
1405 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1406 sizeof(rxon_assoc), &rxon_assoc, NULL);
1407 if (ret)
1408 return ret;
1409
1410 return ret;
1411}
630fe9b6
TW		 1412static int iwl5000_send_tx_power(struct iwl_priv *priv)
1413{
1414 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1415
1416 /* half dBm need to multiply */
1417 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
853554ac 1418 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
630fe9b6
TW		 1419 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1420 return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1421 sizeof(tx_power_cmd), &tx_power_cmd,
1422 NULL);
1423}
1424
8f91aecb
EG		 1425static void iwl5000_temperature(struct iwl_priv *priv,
1426 struct iwl_notif_statistics *stats)
1427{
1428 /* store temperature from statistics (in Celsius) */
1429 priv->temperature = le32_to_cpu(stats->general.temperature);
1430}
fe7a90c2 1431
da8dec29 1432static struct iwl_hcmd_ops iwl5000_hcmd = {
fe7a90c2 1433 .rxon_assoc = iwl5000_send_rxon_assoc,
da8dec29
TW		 1434};
1435
1436static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
c1adf9fb 1437 .get_hcmd_size = iwl5000_get_hcmd_size,
2469bf2e 1438 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
33fd5033
EG		 1439 .gain_computation = iwl5000_gain_computation,
1440 .chain_noise_reset = iwl5000_chain_noise_reset,
da8dec29
TW		 1441};
1442
1443static struct iwl_lib_ops iwl5000_lib = {
fdd3e8a4 1444 .set_hw_params = iwl5000_hw_set_hw_params,
d4100dd9
RR		 1445 .alloc_shared_mem = iwl5000_alloc_shared_mem,
1446 .free_shared_mem = iwl5000_free_shared_mem,
d67f5489 1447 .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
7839fc03 1448 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
972cf447 1449 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
da1bc453 1450 .txq_set_sched = iwl5000_txq_set_sched,
e26e47d9
TW		 1451 .txq_agg_enable = iwl5000_txq_agg_enable,
1452 .txq_agg_disable = iwl5000_txq_agg_disable,
b600e4e1 1453 .rx_handler_setup = iwl5000_rx_handler_setup,
203566f3 1454 .setup_deferred_work = iwl5000_setup_deferred_work,
87283cc1 1455 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
dbb983b7 1456 .load_ucode = iwl5000_load_ucode,
99da1b48
RR		 1457 .init_alive_start = iwl5000_init_alive_start,
1458 .alive_notify = iwl5000_alive_notify,
630fe9b6 1459 .send_tx_power = iwl5000_send_tx_power,
8f91aecb 1460 .temperature = iwl5000_temperature,
30d59260
TW		 1461 .apm_ops = {
1462 .init = iwl5000_apm_init,
7f066108 1463 .reset = iwl5000_apm_reset,
f118a91d 1464 .stop = iwl5000_apm_stop,
5a835353 1465 .config = iwl5000_nic_config,
88acbd3b 1466 .set_pwr_src = iwl4965_set_pwr_src,
30d59260 1467 },
da8dec29 1468 .eeprom_ops = {
25ae3986
TW		 1469 .regulatory_bands = {
1470 EEPROM_5000_REG_BAND_1_CHANNELS,
1471 EEPROM_5000_REG_BAND_2_CHANNELS,
1472 EEPROM_5000_REG_BAND_3_CHANNELS,
1473 EEPROM_5000_REG_BAND_4_CHANNELS,
1474 EEPROM_5000_REG_BAND_5_CHANNELS,
1475 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1476 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1477 },
da8dec29
TW		 1478 .verify_signature = iwlcore_eeprom_verify_signature,
1479 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1480 .release_semaphore = iwlcore_eeprom_release_semaphore,
f1f69415 1481 .check_version = iwl5000_eeprom_check_version,
25ae3986 1482 .query_addr = iwl5000_eeprom_query_addr,
da8dec29
TW		 1483 },
1484};
1485
1486static struct iwl_ops iwl5000_ops = {
1487 .lib = &iwl5000_lib,
1488 .hcmd = &iwl5000_hcmd,
1489 .utils = &iwl5000_hcmd_utils,
1490};
1491
5a6a256e
TW		 1492static struct iwl_mod_params iwl50_mod_params = {
1493 .num_of_queues = IWL50_NUM_QUEUES,
1494 .enable_qos = 1,
1495 .amsdu_size_8K = 1,
3a1081e8 1496 .restart_fw = 1,
5a6a256e
TW		 1497 /* the rest are 0 by default */
1498};
1499
1500
1501struct iwl_cfg iwl5300_agn_cfg = {
1502 .name = "5300AGN",
1503 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1504 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1505 .ops = &iwl5000_ops,
25ae3986 1506 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
5a6a256e
TW		 1507 .mod_params = &iwl50_mod_params,
1508};
1509
1510struct iwl_cfg iwl5100_agn_cfg = {
1511 .name = "5100AGN",
1512 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1513 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1514 .ops = &iwl5000_ops,
25ae3986 1515 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
5a6a256e
TW		 1516 .mod_params = &iwl50_mod_params,
1517};
1518
1519struct iwl_cfg iwl5350_agn_cfg = {
1520 .name = "5350AGN",
1521 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1522 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1523 .ops = &iwl5000_ops,
25ae3986 1524 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
5a6a256e
TW		 1525 .mod_params = &iwl50_mod_params,
1526};
1527
1528module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1529MODULE_PARM_DESC(disable50,
1530 "manually disable the 50XX radio (default 0 [radio on])");
1531module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1532MODULE_PARM_DESC(swcrypto50,
1533 "using software crypto engine (default 0 [hardware])\n");
1534module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1535MODULE_PARM_DESC(debug50, "50XX debug output mask");
1536module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1537MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1538module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1539MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
49779293
RR		 1540module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1541MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
5a6a256e
TW		 1542module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1543MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
3a1081e8
EK		 1544module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1545MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
Linux kernel - Deliverables
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