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iwlwifi: fixes RTS / CTS support
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
CommitLineData
5a6a256e
TW		 1/******************************************************************************
2 *
3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/version.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <net/mac80211.h>
37#include <linux/etherdevice.h>
38#include <asm/unaligned.h>
39
40#include "iwl-eeprom.h"
3e0d4cb1 41#include "iwl-dev.h"
5a6a256e
TW		 42#include "iwl-core.h"
43#include "iwl-io.h"
e26e47d9 44#include "iwl-sta.h"
5a6a256e
TW		 45#include "iwl-helpers.h"
46#include "iwl-5000-hw.h"
47
48#define IWL5000_UCODE_API "-1"
49
99da1b48
RR		 50static const u16 iwl5000_default_queue_to_tx_fifo[] = {
51 IWL_TX_FIFO_AC3,
52 IWL_TX_FIFO_AC2,
53 IWL_TX_FIFO_AC1,
54 IWL_TX_FIFO_AC0,
55 IWL50_CMD_FIFO_NUM,
56 IWL_TX_FIFO_HCCA_1,
57 IWL_TX_FIFO_HCCA_2
58};
59
46315e01
TW		 60/* FIXME: same implementation as 4965 */
61static int iwl5000_apm_stop_master(struct iwl_priv *priv)
62{
63 int ret = 0;
64 unsigned long flags;
65
66 spin_lock_irqsave(&priv->lock, flags);
67
68 /* set stop master bit */
69 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
70
71 ret = iwl_poll_bit(priv, CSR_RESET,
72 CSR_RESET_REG_FLAG_MASTER_DISABLED,
73 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
74 if (ret < 0)
75 goto out;
76
77out:
78 spin_unlock_irqrestore(&priv->lock, flags);
79 IWL_DEBUG_INFO("stop master\n");
80
81 return ret;
82}
83
84
30d59260
TW		 85static int iwl5000_apm_init(struct iwl_priv *priv)
86{
87 int ret = 0;
88
89 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
90 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
91
8f061891
TW		 92 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
93 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
94 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
95
30d59260
TW		 96 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
97
98 /* set "initialization complete" bit to move adapter
99 * D0U* --> D0A* state */
100 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
101
102 /* wait for clock stabilization */
103 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
104 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
105 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
106 if (ret < 0) {
107 IWL_DEBUG_INFO("Failed to init the card\n");
108 return ret;
109 }
110
111 ret = iwl_grab_nic_access(priv);
112 if (ret)
113 return ret;
114
115 /* enable DMA */
8f061891 116 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
30d59260
TW		 117
118 udelay(20);
119
8f061891 120 /* disable L1-Active */
30d59260 121 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
8f061891 122 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
30d59260
TW		 123
124 iwl_release_nic_access(priv);
125
126 return ret;
127}
128
f118a91d
TW		 129/* FIXME: this is indentical to 4965 */
130static void iwl5000_apm_stop(struct iwl_priv *priv)
131{
132 unsigned long flags;
133
46315e01 134 iwl5000_apm_stop_master(priv);
f118a91d
TW		 135
136 spin_lock_irqsave(&priv->lock, flags);
137
138 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
139
140 udelay(10);
141
142 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
143
144 spin_unlock_irqrestore(&priv->lock, flags);
145}
146
147
7f066108
TW		 148static int iwl5000_apm_reset(struct iwl_priv *priv)
149{
150 int ret = 0;
151 unsigned long flags;
152
46315e01 153 iwl5000_apm_stop_master(priv);
7f066108
TW		 154
155 spin_lock_irqsave(&priv->lock, flags);
156
157 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
158
159 udelay(10);
160
161
162 /* FIXME: put here L1A -L0S w/a */
163
164 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
165
166 /* set "initialization complete" bit to move adapter
167 * D0U* --> D0A* state */
168 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
169
170 /* wait for clock stabilization */
171 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
172 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
173 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
174 if (ret < 0) {
175 IWL_DEBUG_INFO("Failed to init the card\n");
176 goto out;
177 }
178
179 ret = iwl_grab_nic_access(priv);
180 if (ret)
181 goto out;
182
183 /* enable DMA */
184 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
185
186 udelay(20);
187
188 /* disable L1-Active */
189 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
190 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
191
192 iwl_release_nic_access(priv);
193
194out:
195 spin_unlock_irqrestore(&priv->lock, flags);
196
197 return ret;
198}
199
200
5a835353 201static void iwl5000_nic_config(struct iwl_priv *priv)
e86fe9f6
TW		 202{
203 unsigned long flags;
204 u16 radio_cfg;
205 u8 val_link;
206
207 spin_lock_irqsave(&priv->lock, flags);
208
209 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
210
8f061891
TW		 211 /* L1 is enabled by BIOS */
212 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
213 /* diable L0S disabled L1A enabled */
214 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
215 else
216 /* L0S enabled L1A disabled */
217 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
e86fe9f6
TW		 218
219 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
220
221 /* write radio config values to register */
222 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
223 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
224 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
225 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
226 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
227
228 /* set CSR_HW_CONFIG_REG for uCode use */
229 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
230 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
231 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
232
233 spin_unlock_irqrestore(&priv->lock, flags);
234}
235
236
237
25ae3986
TW		 238/*
239 * EEPROM
240 */
241static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
242{
243 u16 offset = 0;
244
245 if ((address & INDIRECT_ADDRESS) == 0)
246 return address;
247
248 switch (address & INDIRECT_TYPE_MSK) {
249 case INDIRECT_HOST:
250 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
251 break;
252 case INDIRECT_GENERAL:
253 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
254 break;
255 case INDIRECT_REGULATORY:
256 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
257 break;
258 case INDIRECT_CALIBRATION:
259 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
260 break;
261 case INDIRECT_PROCESS_ADJST:
262 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
263 break;
264 case INDIRECT_OTHERS:
265 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
266 break;
267 default:
268 IWL_ERROR("illegal indirect type: 0x%X\n",
269 address & INDIRECT_TYPE_MSK);
270 break;
271 }
272
273 /* translate the offset from words to byte */
274 return (address & ADDRESS_MSK) + (offset << 1);
275}
276
f1f69415
TW		 277static int iwl5000_eeprom_check_version(struct iwl_priv *priv)
278{
279 u16 eeprom_ver;
280 struct iwl_eeprom_calib_hdr {
281 u8 version;
282 u8 pa_type;
283 u16 voltage;
284 } *hdr;
285
286 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
287
288 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
289 EEPROM_5000_CALIB_ALL);
290
291 if (eeprom_ver < EEPROM_5000_EEPROM_VERSION ||
292 hdr->version < EEPROM_5000_TX_POWER_VERSION)
293 goto err;
294
295 return 0;
296err:
297 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
298 eeprom_ver, EEPROM_5000_EEPROM_VERSION,
299 hdr->version, EEPROM_5000_TX_POWER_VERSION);
300 return -EINVAL;
301
302}
303
33fd5033
EG		 304static void iwl5000_gain_computation(struct iwl_priv *priv,
305 u32 average_noise[NUM_RX_CHAINS],
306 u16 min_average_noise_antenna_i,
307 u32 min_average_noise)
308{
309 int i;
310 s32 delta_g;
311 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
312
313 /* Find Gain Code for the antennas B and C */
314 for (i = 1; i < NUM_RX_CHAINS; i++) {
315 if ((data->disconn_array[i])) {
316 data->delta_gain_code[i] = 0;
317 continue;
318 }
319 delta_g = (1000 * ((s32)average_noise[0] -
320 (s32)average_noise[i])) / 1500;
321 /* bound gain by 2 bits value max, 3rd bit is sign */
322 data->delta_gain_code[i] =
323 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
324
325 if (delta_g < 0)
326 /* set negative sign */
327 data->delta_gain_code[i] |= (1 << 2);
328 }
329
330 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
331 data->delta_gain_code[1], data->delta_gain_code[2]);
332
333 if (!data->radio_write) {
334 struct iwl5000_calibration_chain_noise_gain_cmd cmd;
335 memset(&cmd, 0, sizeof(cmd));
336
337 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
338 cmd.delta_gain_1 = data->delta_gain_code[1];
339 cmd.delta_gain_2 = data->delta_gain_code[2];
340 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
341 sizeof(cmd), &cmd, NULL);
342
343 data->radio_write = 1;
344 data->state = IWL_CHAIN_NOISE_CALIBRATED;
345 }
346
347 data->chain_noise_a = 0;
348 data->chain_noise_b = 0;
349 data->chain_noise_c = 0;
350 data->chain_signal_a = 0;
351 data->chain_signal_b = 0;
352 data->chain_signal_c = 0;
353 data->beacon_count = 0;
354}
355
356static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
357{
358 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
359
360 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
361 struct iwl5000_calibration_chain_noise_reset_cmd cmd;
362
363 memset(&cmd, 0, sizeof(cmd));
364 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
365 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
366 sizeof(cmd), &cmd))
367 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
368 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
369 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
370 }
371}
372
a326a5d0
EG		 373static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
374 __le32 *tx_flags)
375{
376 if ((info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) ||
377 (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT))
378 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
379 else
380 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
381}
382
33fd5033
EG		 383static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
384 .min_nrg_cck = 95,
385 .max_nrg_cck = 0,
386 .auto_corr_min_ofdm = 90,
387 .auto_corr_min_ofdm_mrc = 170,
388 .auto_corr_min_ofdm_x1 = 120,
389 .auto_corr_min_ofdm_mrc_x1 = 240,
390
391 .auto_corr_max_ofdm = 120,
392 .auto_corr_max_ofdm_mrc = 210,
393 .auto_corr_max_ofdm_x1 = 155,
394 .auto_corr_max_ofdm_mrc_x1 = 290,
395
396 .auto_corr_min_cck = 125,
397 .auto_corr_max_cck = 200,
398 .auto_corr_min_cck_mrc = 170,
399 .auto_corr_max_cck_mrc = 400,
400 .nrg_th_cck = 95,
401 .nrg_th_ofdm = 95,
402};
403
25ae3986
TW		 404static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
405 size_t offset)
406{
407 u32 address = eeprom_indirect_address(priv, offset);
408 BUG_ON(address >= priv->cfg->eeprom_size);
409 return &priv->eeprom[address];
410}
411
7c616cba
TW		 412/*
413 * Calibration
414 */
415static int iwl5000_send_Xtal_calib(struct iwl_priv *priv)
416{
417 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
418
419 struct iwl5000_calibration cal_cmd = {
420 .op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD,
421 .data = {
422 (u8)xtal_calib[0],
423 (u8)xtal_calib[1],
424 }
425 };
426
427 return iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
428 sizeof(cal_cmd), &cal_cmd);
429}
430
431static int iwl5000_send_calib_results(struct iwl_priv *priv)
432{
433 int ret = 0;
434
d2f18bfd
EG		 435 struct iwl_host_cmd hcmd = {
436 .id = REPLY_PHY_CALIBRATION_CMD,
437 .meta.flags = CMD_SIZE_HUGE,
438 };
7c616cba 439
d2f18bfd
EG		 440 if (priv->calib_results.lo_res) {
441 hcmd.len = priv->calib_results.lo_res_len;
442 hcmd.data = priv->calib_results.lo_res;
443 ret = iwl_send_cmd_sync(priv, &hcmd);
7c616cba 444
d2f18bfd
EG		 445 if (ret)
446 goto err;
447 }
7c616cba 448
d2f18bfd
EG		 449 if (priv->calib_results.tx_iq_res) {
450 hcmd.len = priv->calib_results.tx_iq_res_len;
451 hcmd.data = priv->calib_results.tx_iq_res;
452 ret = iwl_send_cmd_sync(priv, &hcmd);
7c616cba 453
d2f18bfd
EG		 454 if (ret)
455 goto err;
456 }
457
458 if (priv->calib_results.tx_iq_perd_res) {
459 hcmd.len = priv->calib_results.tx_iq_perd_res_len;
460 hcmd.data = priv->calib_results.tx_iq_perd_res;
461 ret = iwl_send_cmd_sync(priv, &hcmd);
462
463 if (ret)
464 goto err;
465 }
7c616cba
TW		 466
467 return 0;
468err:
469 IWL_ERROR("Error %d\n", ret);
470 return ret;
471}
472
473static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
474{
475 struct iwl5000_calib_cfg_cmd calib_cfg_cmd;
476 struct iwl_host_cmd cmd = {
477 .id = CALIBRATION_CFG_CMD,
478 .len = sizeof(struct iwl5000_calib_cfg_cmd),
479 .data = &calib_cfg_cmd,
480 };
481
482 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
483 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
484 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
485 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
486 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
487
488 return iwl_send_cmd(priv, &cmd);
489}
490
491static void iwl5000_rx_calib_result(struct iwl_priv *priv,
492 struct iwl_rx_mem_buffer *rxb)
493{
494 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
495 struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw;
496 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
497
498 iwl_free_calib_results(priv);
499
500 /* reduce the size of the length field itself */
501 len -= 4;
502
503 switch (hdr->op_code) {
504 case IWL5000_PHY_CALIBRATE_LO_CMD:
505 priv->calib_results.lo_res = kzalloc(len, GFP_ATOMIC);
506 priv->calib_results.lo_res_len = len;
507 memcpy(priv->calib_results.lo_res, pkt->u.raw, len);
508 break;
509 case IWL5000_PHY_CALIBRATE_TX_IQ_CMD:
510 priv->calib_results.tx_iq_res = kzalloc(len, GFP_ATOMIC);
511 priv->calib_results.tx_iq_res_len = len;
512 memcpy(priv->calib_results.tx_iq_res, pkt->u.raw, len);
513 break;
514 case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD:
515 priv->calib_results.tx_iq_perd_res = kzalloc(len, GFP_ATOMIC);
516 priv->calib_results.tx_iq_perd_res_len = len;
517 memcpy(priv->calib_results.tx_iq_perd_res, pkt->u.raw, len);
518 break;
519 default:
520 IWL_ERROR("Unknown calibration notification %d\n",
521 hdr->op_code);
522 return;
523 }
524}
525
526static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
527 struct iwl_rx_mem_buffer *rxb)
528{
529 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
530 queue_work(priv->workqueue, &priv->restart);
531}
532
dbb983b7
RR		 533/*
534 * ucode
535 */
536static int iwl5000_load_section(struct iwl_priv *priv,
537 struct fw_desc *image,
538 u32 dst_addr)
539{
540 int ret = 0;
541 unsigned long flags;
542
543 dma_addr_t phy_addr = image->p_addr;
544 u32 byte_cnt = image->len;
545
546 spin_lock_irqsave(&priv->lock, flags);
547 ret = iwl_grab_nic_access(priv);
548 if (ret) {
549 spin_unlock_irqrestore(&priv->lock, flags);
550 return ret;
551 }
552
553 iwl_write_direct32(priv,
554 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
555 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
556
557 iwl_write_direct32(priv,
558 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
559
560 iwl_write_direct32(priv,
561 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
562 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
563
564 /* FIME: write the MSB of the phy_addr in CTRL1
565 * iwl_write_direct32(priv,
566 IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL),
567 ((phy_addr & MSB_MSK)
568 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count);
569 */
570 iwl_write_direct32(priv,
571 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt);
572 iwl_write_direct32(priv,
573 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
574 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
575 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
576 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
577
578 iwl_write_direct32(priv,
579 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
580 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
581 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
582 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
583
584 iwl_release_nic_access(priv);
585 spin_unlock_irqrestore(&priv->lock, flags);
586 return 0;
587}
588
589static int iwl5000_load_given_ucode(struct iwl_priv *priv,
590 struct fw_desc *inst_image,
591 struct fw_desc *data_image)
592{
593 int ret = 0;
594
595 ret = iwl5000_load_section(
596 priv, inst_image, RTC_INST_LOWER_BOUND);
597 if (ret)
598 return ret;
599
600 IWL_DEBUG_INFO("INST uCode section being loaded...\n");
601 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
602 priv->ucode_write_complete, 5 * HZ);
603 if (ret == -ERESTARTSYS) {
604 IWL_ERROR("Could not load the INST uCode section due "
605 "to interrupt\n");
606 return ret;
607 }
608 if (!ret) {
609 IWL_ERROR("Could not load the INST uCode section\n");
610 return -ETIMEDOUT;
611 }
612
613 priv->ucode_write_complete = 0;
614
615 ret = iwl5000_load_section(
616 priv, data_image, RTC_DATA_LOWER_BOUND);
617 if (ret)
618 return ret;
619
620 IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
621
622 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
623 priv->ucode_write_complete, 5 * HZ);
624 if (ret == -ERESTARTSYS) {
625 IWL_ERROR("Could not load the INST uCode section due "
626 "to interrupt\n");
627 return ret;
628 } else if (!ret) {
629 IWL_ERROR("Could not load the DATA uCode section\n");
630 return -ETIMEDOUT;
631 } else
632 ret = 0;
633
634 priv->ucode_write_complete = 0;
635
636 return ret;
637}
638
639static int iwl5000_load_ucode(struct iwl_priv *priv)
640{
641 int ret = 0;
642
643 /* check whether init ucode should be loaded, or rather runtime ucode */
644 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
645 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
646 ret = iwl5000_load_given_ucode(priv,
647 &priv->ucode_init, &priv->ucode_init_data);
648 if (!ret) {
649 IWL_DEBUG_INFO("Init ucode load complete.\n");
650 priv->ucode_type = UCODE_INIT;
651 }
652 } else {
653 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
654 "Loading runtime ucode...\n");
655 ret = iwl5000_load_given_ucode(priv,
656 &priv->ucode_code, &priv->ucode_data);
657 if (!ret) {
658 IWL_DEBUG_INFO("Runtime ucode load complete.\n");
659 priv->ucode_type = UCODE_RT;
660 }
661 }
662
663 return ret;
664}
665
99da1b48
RR		 666static void iwl5000_init_alive_start(struct iwl_priv *priv)
667{
668 int ret = 0;
669
670 /* Check alive response for "valid" sign from uCode */
671 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
672 /* We had an error bringing up the hardware, so take it
673 * all the way back down so we can try again */
674 IWL_DEBUG_INFO("Initialize Alive failed.\n");
675 goto restart;
676 }
677
678 /* initialize uCode was loaded... verify inst image.
679 * This is a paranoid check, because we would not have gotten the
680 * "initialize" alive if code weren't properly loaded. */
681 if (iwl_verify_ucode(priv)) {
682 /* Runtime instruction load was bad;
683 * take it all the way back down so we can try again */
684 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
685 goto restart;
686 }
687
37deb2a0 688 iwl_clear_stations_table(priv);
99da1b48
RR		 689 ret = priv->cfg->ops->lib->alive_notify(priv);
690 if (ret) {
691 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
692 goto restart;
693 }
694
7c616cba 695 iwl5000_send_calib_cfg(priv);
99da1b48
RR		 696 return;
697
698restart:
699 /* real restart (first load init_ucode) */
700 queue_work(priv->workqueue, &priv->restart);
701}
702
703static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
704 int txq_id, u32 index)
705{
706 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
707 (index & 0xff) | (txq_id << 8));
708 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
709}
710
711static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
712 struct iwl_tx_queue *txq,
713 int tx_fifo_id, int scd_retry)
714{
715 int txq_id = txq->q.id;
716 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
717
718 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
719 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
720 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
721 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
722 IWL50_SCD_QUEUE_STTS_REG_MSK);
723
724 txq->sched_retry = scd_retry;
725
726 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
727 active ? "Activate" : "Deactivate",
728 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
729}
730
9636e583
RR		 731static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
732{
733 struct iwl_wimax_coex_cmd coex_cmd;
734
735 memset(&coex_cmd, 0, sizeof(coex_cmd));
736
737 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
738 sizeof(coex_cmd), &coex_cmd);
739}
740
99da1b48
RR		 741static int iwl5000_alive_notify(struct iwl_priv *priv)
742{
743 u32 a;
744 int i = 0;
745 unsigned long flags;
746 int ret;
747
748 spin_lock_irqsave(&priv->lock, flags);
749
750 ret = iwl_grab_nic_access(priv);
751 if (ret) {
752 spin_unlock_irqrestore(&priv->lock, flags);
753 return ret;
754 }
755
756 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
757 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
758 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
759 a += 4)
760 iwl_write_targ_mem(priv, a, 0);
761 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
762 a += 4)
763 iwl_write_targ_mem(priv, a, 0);
764 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
765 iwl_write_targ_mem(priv, a, 0);
766
767 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
768 (priv->shared_phys +
769 offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
770 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
771 IWL50_SCD_QUEUECHAIN_SEL_ALL(
772 priv->hw_params.max_txq_num));
773 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
774
775 /* initiate the queues */
776 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
777 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
778 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
779 iwl_write_targ_mem(priv, priv->scd_base_addr +
780 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
781 iwl_write_targ_mem(priv, priv->scd_base_addr +
782 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
783 sizeof(u32),
784 ((SCD_WIN_SIZE <<
785 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
786 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
787 ((SCD_FRAME_LIMIT <<
788 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
789 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
790 }
791
792 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
da1bc453 793 IWL_MASK(0, priv->hw_params.max_txq_num));
99da1b48 794
da1bc453
TW		 795 /* Activate all Tx DMA/FIFO channels */
796 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
99da1b48
RR		 797
798 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
799 /* map qos queues to fifos one-to-one */
800 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
801 int ac = iwl5000_default_queue_to_tx_fifo[i];
802 iwl_txq_ctx_activate(priv, i);
803 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
804 }
805 /* TODO - need to initialize those FIFOs inside the loop above,
806 * not only mark them as active */
807 iwl_txq_ctx_activate(priv, 4);
808 iwl_txq_ctx_activate(priv, 7);
809 iwl_txq_ctx_activate(priv, 8);
810 iwl_txq_ctx_activate(priv, 9);
811
812 iwl_release_nic_access(priv);
813 spin_unlock_irqrestore(&priv->lock, flags);
814
7c616cba 815
9636e583
RR		 816 iwl5000_send_wimax_coex(priv);
817
7c616cba
TW		 818 iwl5000_send_Xtal_calib(priv);
819
0a078ffa 820 if (priv->ucode_type == UCODE_RT)
7c616cba
TW		 821 iwl5000_send_calib_results(priv);
822
99da1b48
RR		 823 return 0;
824}
825
fdd3e8a4
TW		 826static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
827{
828 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
829 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
830 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
831 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
832 return -EINVAL;
833 }
25ae3986 834
fdd3e8a4 835 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
7f3e4bb6 836 priv->hw_params.first_ampdu_q = IWL50_FIRST_AMPDU_QUEUE;
fdd3e8a4
TW		 837 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
838 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
839 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
840 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
da154e30 841 priv->hw_params.max_bsm_size = 0;
fdd3e8a4
TW		 842 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
843 BIT(IEEE80211_BAND_5GHZ);
33fd5033 844 priv->hw_params.sens = &iwl5000_sensitivity;
fdd3e8a4
TW		 845
846 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
847 case CSR_HW_REV_TYPE_5100:
848 case CSR_HW_REV_TYPE_5150:
849 priv->hw_params.tx_chains_num = 1;
850 priv->hw_params.rx_chains_num = 2;
851 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */
1179f18d
TW		 852 priv->hw_params.valid_tx_ant = ANT_A;
853 priv->hw_params.valid_rx_ant = ANT_AB;
fdd3e8a4
TW		 854 break;
855 case CSR_HW_REV_TYPE_5300:
856 case CSR_HW_REV_TYPE_5350:
857 priv->hw_params.tx_chains_num = 3;
858 priv->hw_params.rx_chains_num = 3;
1179f18d
TW		 859 priv->hw_params.valid_tx_ant = ANT_ABC;
860 priv->hw_params.valid_rx_ant = ANT_ABC;
fdd3e8a4
TW		 861 break;
862 }
c031bf80
EG		 863
864 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
865 case CSR_HW_REV_TYPE_5100:
866 case CSR_HW_REV_TYPE_5300:
867 /* 5X00 wants in Celsius */
868 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
869 break;
870 case CSR_HW_REV_TYPE_5150:
871 case CSR_HW_REV_TYPE_5350:
872 /* 5X50 wants in Kelvin */
873 priv->hw_params.ct_kill_threshold =
874 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
875 break;
876 }
877
fdd3e8a4
TW		 878 return 0;
879}
d4100dd9
RR		 880
881static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
882{
883 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
884 sizeof(struct iwl5000_shared),
885 &priv->shared_phys);
886 if (!priv->shared_virt)
887 return -ENOMEM;
888
889 memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
890
d67f5489
RR		 891 priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
892
d4100dd9
RR		 893 return 0;
894}
895
896static void iwl5000_free_shared_mem(struct iwl_priv *priv)
897{
898 if (priv->shared_virt)
899 pci_free_consistent(priv->pci_dev,
900 sizeof(struct iwl5000_shared),
901 priv->shared_virt,
902 priv->shared_phys);
903}
904
d67f5489
RR		 905static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
906{
907 struct iwl5000_shared *s = priv->shared_virt;
908 return le32_to_cpu(s->rb_closed) & 0xFFF;
909}
910
7839fc03
EG		 911/**
912 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
913 */
914static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 915 struct iwl_tx_queue *txq,
7839fc03
EG		 916 u16 byte_cnt)
917{
918 struct iwl5000_shared *shared_data = priv->shared_virt;
919 int txq_id = txq->q.id;
920 u8 sec_ctl = 0;
921 u8 sta = 0;
922 int len;
923
924 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
925
926 if (txq_id != IWL_CMD_QUEUE_NUM) {
927 sta = txq->cmd[txq->q.write_ptr].cmd.tx.sta_id;
928 sec_ctl = txq->cmd[txq->q.write_ptr].cmd.tx.sec_ctl;
929
930 switch (sec_ctl & TX_CMD_SEC_MSK) {
931 case TX_CMD_SEC_CCM:
932 len += CCMP_MIC_LEN;
933 break;
934 case TX_CMD_SEC_TKIP:
935 len += TKIP_ICV_LEN;
936 break;
937 case TX_CMD_SEC_WEP:
938 len += WEP_IV_LEN + WEP_ICV_LEN;
939 break;
940 }
941 }
942
943 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
944 tfd_offset[txq->q.write_ptr], byte_cnt, len);
945
946 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
947 tfd_offset[txq->q.write_ptr], sta_id, sta);
948
949 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
950 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
951 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
952 byte_cnt, len);
953 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
954 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
955 sta_id, sta);
956 }
957}
958
972cf447
TW		 959static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
960 struct iwl_tx_queue *txq)
961{
962 int txq_id = txq->q.id;
963 struct iwl5000_shared *shared_data = priv->shared_virt;
964 u8 sta = 0;
965
966 if (txq_id != IWL_CMD_QUEUE_NUM)
967 sta = txq->cmd[txq->q.read_ptr].cmd.tx.sta_id;
968
969 shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr].
970 val = cpu_to_le16(1 | (sta << 12));
971
972 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
973 shared_data->queues_byte_cnt_tbls[txq_id].
974 tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr].
975 val = cpu_to_le16(1 | (sta << 12));
976 }
977}
978
e26e47d9
TW		 979static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
980 u16 txq_id)
981{
982 u32 tbl_dw_addr;
983 u32 tbl_dw;
984 u16 scd_q2ratid;
985
986 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
987
988 tbl_dw_addr = priv->scd_base_addr +
989 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
990
991 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
992
993 if (txq_id & 0x1)
994 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
995 else
996 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
997
998 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
999
1000 return 0;
1001}
1002static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
1003{
1004 /* Simply stop the queue, but don't change any configuration;
1005 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1006 iwl_write_prph(priv,
1007 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
1008 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1009 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1010}
1011
1012static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1013 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1014{
1015 unsigned long flags;
1016 int ret;
1017 u16 ra_tid;
1018
1019 if (IWL50_FIRST_AMPDU_QUEUE > txq_id)
1020 IWL_WARNING("queue number too small: %d, must be > %d\n",
1021 txq_id, IWL50_FIRST_AMPDU_QUEUE);
1022
1023 ra_tid = BUILD_RAxTID(sta_id, tid);
1024
1025 /* Modify device's station table to Tx this TID */
1026 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
1027
1028 spin_lock_irqsave(&priv->lock, flags);
1029 ret = iwl_grab_nic_access(priv);
1030 if (ret) {
1031 spin_unlock_irqrestore(&priv->lock, flags);
1032 return ret;
1033 }
1034
1035 /* Stop this Tx queue before configuring it */
1036 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1037
1038 /* Map receiver-address / traffic-ID to this queue */
1039 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1040
1041 /* Set this queue as a chain-building queue */
1042 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1043
1044 /* enable aggregations for the queue */
1045 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1046
1047 /* Place first TFD at index corresponding to start sequence number.
1048 * Assumes that ssn_idx is valid (!= 0xFFF) */
1049 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1050 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1051 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1052
1053 /* Set up Tx window size and frame limit for this queue */
1054 iwl_write_targ_mem(priv, priv->scd_base_addr +
1055 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1056 sizeof(u32),
1057 ((SCD_WIN_SIZE <<
1058 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1059 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1060 ((SCD_FRAME_LIMIT <<
1061 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1062 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1063
1064 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1065
1066 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1067 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1068
1069 iwl_release_nic_access(priv);
1070 spin_unlock_irqrestore(&priv->lock, flags);
1071
1072 return 0;
1073}
1074
1075static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1076 u16 ssn_idx, u8 tx_fifo)
1077{
1078 int ret;
1079
1080 if (IWL50_FIRST_AMPDU_QUEUE > txq_id) {
1081 IWL_WARNING("queue number too small: %d, must be > %d\n",
1082 txq_id, IWL50_FIRST_AMPDU_QUEUE);
1083 return -EINVAL;
1084 }
1085
1086 ret = iwl_grab_nic_access(priv);
1087 if (ret)
1088 return ret;
1089
1090 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1091
1092 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1093
1094 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1095 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1096 /* supposes that ssn_idx is valid (!= 0xFFF) */
1097 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1098
1099 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1100 iwl_txq_ctx_deactivate(priv, txq_id);
1101 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1102
1103 iwl_release_nic_access(priv);
1104
1105 return 0;
1106}
1107
2469bf2e
TW		 1108static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1109{
1110 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1111 memcpy(data, cmd, size);
1112 return size;
1113}
1114
1115
da1bc453
TW		 1116/*
1117 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
1118 * must be called under priv->lock and mac access
1119 */
1120static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
5a676bbe 1121{
da1bc453 1122 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
5a676bbe
RR		 1123}
1124
e532fa0e
RR		 1125
1126static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1127{
25a6572c
TW		 1128 return le32_to_cpup((__le32*)&tx_resp->status +
1129 tx_resp->frame_count) & MAX_SN;
e532fa0e
RR		 1130}
1131
1132static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1133 struct iwl_ht_agg *agg,
1134 struct iwl5000_tx_resp *tx_resp,
25a6572c 1135 int txq_id, u16 start_idx)
e532fa0e
RR		 1136{
1137 u16 status;
1138 struct agg_tx_status *frame_status = &tx_resp->status;
1139 struct ieee80211_tx_info *info = NULL;
1140 struct ieee80211_hdr *hdr = NULL;
e7d326ac 1141 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 1142 int i, sh, idx;
e532fa0e
RR		 1143 u16 seq;
1144
1145 if (agg->wait_for_ba)
1146 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1147
1148 agg->frame_count = tx_resp->frame_count;
1149 agg->start_idx = start_idx;
e7d326ac 1150 agg->rate_n_flags = rate_n_flags;
e532fa0e
RR		 1151 agg->bitmap = 0;
1152
1153 /* # frames attempted by Tx command */
1154 if (agg->frame_count == 1) {
1155 /* Only one frame was attempted; no block-ack will arrive */
1156 status = le16_to_cpu(frame_status[0].status);
25a6572c 1157 idx = start_idx;
e532fa0e
RR		 1158
1159 /* FIXME: code repetition */
1160 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1161 agg->frame_count, agg->start_idx, idx);
1162
1163 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1164 info->status.retry_count = tx_resp->failure_frame;
1165 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1166 info->flags |= iwl_is_tx_success(status)?
1167 IEEE80211_TX_STAT_ACK : 0;
e7d326ac
TW		 1168 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1169
e532fa0e
RR		 1170 /* FIXME: code repetition end */
1171
1172 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1173 status & 0xff, tx_resp->failure_frame);
e7d326ac 1174 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
e532fa0e
RR		 1175
1176 agg->wait_for_ba = 0;
1177 } else {
1178 /* Two or more frames were attempted; expect block-ack */
1179 u64 bitmap = 0;
1180 int start = agg->start_idx;
1181
1182 /* Construct bit-map of pending frames within Tx window */
1183 for (i = 0; i < agg->frame_count; i++) {
1184 u16 sc;
1185 status = le16_to_cpu(frame_status[i].status);
1186 seq = le16_to_cpu(frame_status[i].sequence);
1187 idx = SEQ_TO_INDEX(seq);
1188 txq_id = SEQ_TO_QUEUE(seq);
1189
1190 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1191 AGG_TX_STATE_ABORT_MSK))
1192 continue;
1193
1194 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1195 agg->frame_count, txq_id, idx);
1196
1197 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1198
1199 sc = le16_to_cpu(hdr->seq_ctrl);
1200 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1201 IWL_ERROR("BUG_ON idx doesn't match seq control"
1202 " idx=%d, seq_idx=%d, seq=%d\n",
1203 idx, SEQ_TO_SN(sc),
1204 hdr->seq_ctrl);
1205 return -1;
1206 }
1207
1208 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1209 i, idx, SEQ_TO_SN(sc));
1210
1211 sh = idx - start;
1212 if (sh > 64) {
1213 sh = (start - idx) + 0xff;
1214 bitmap = bitmap << sh;
1215 sh = 0;
1216 start = idx;
1217 } else if (sh < -64)
1218 sh = 0xff - (start - idx);
1219 else if (sh < 0) {
1220 sh = start - idx;
1221 start = idx;
1222 bitmap = bitmap << sh;
1223 sh = 0;
1224 }
1225 bitmap |= (1 << sh);
1226 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%x\n",
1227 start, (u32)(bitmap & 0xFFFFFFFF));
1228 }
1229
1230 agg->bitmap = bitmap;
1231 agg->start_idx = start;
e532fa0e
RR		 1232 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1233 agg->frame_count, agg->start_idx,
1234 (unsigned long long)agg->bitmap);
1235
1236 if (bitmap)
1237 agg->wait_for_ba = 1;
1238 }
1239 return 0;
1240}
1241
1242static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1243 struct iwl_rx_mem_buffer *rxb)
1244{
1245 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1246 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1247 int txq_id = SEQ_TO_QUEUE(sequence);
1248 int index = SEQ_TO_INDEX(sequence);
1249 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1250 struct ieee80211_tx_info *info;
1251 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1252 u32 status = le16_to_cpu(tx_resp->status.status);
e532fa0e 1253 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
e532fa0e
RR		 1254 struct ieee80211_hdr *hdr;
1255 u8 *qc = NULL;
e532fa0e
RR		 1256
1257 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1258 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1259 "is out of range [0-%d] %d %d\n", txq_id,
1260 index, txq->q.n_bd, txq->q.write_ptr,
1261 txq->q.read_ptr);
1262 return;
1263 }
1264
1265 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1266 memset(&info->status, 0, sizeof(info->status));
1267
e532fa0e 1268 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
fd7c8a40
HH		 1269 if (ieee80211_is_data_qos(hdr->frame_control)) {
1270 qc = ieee80211_get_qos_ctl(hdr);
e532fa0e
RR		 1271 tid = qc[0] & 0xf;
1272 }
1273
1274 sta_id = iwl_get_ra_sta_id(priv, hdr);
1275 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
1276 IWL_ERROR("Station not known\n");
1277 return;
1278 }
1279
1280 if (txq->sched_retry) {
1281 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1282 struct iwl_ht_agg *agg = NULL;
1283
1284 if (!qc)
1285 return;
1286
1287 agg = &priv->stations[sta_id].tid[tid].agg;
1288
25a6572c 1289 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
e532fa0e 1290
3235427e
RR		 1291 /* check if BAR is needed */
1292 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1293 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
e532fa0e
RR		 1294
1295 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1296 int freed, ampdu_q;
1297 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1298 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
1299 "%d index %d\n", scd_ssn , index);
17b88929 1300 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
e532fa0e
RR		 1301 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1302
1303 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1304 txq_id >= 0 && priv->mac80211_registered &&
1305 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
1306 /* calculate mac80211 ampdu sw queue to wake */
7f3e4bb6 1307 ampdu_q = txq_id - IWL50_FIRST_AMPDU_QUEUE +
e532fa0e
RR		 1308 priv->hw->queues;
1309 if (agg->state == IWL_AGG_OFF)
1310 ieee80211_wake_queue(priv->hw, txq_id);
1311 else
1312 ieee80211_wake_queue(priv->hw, ampdu_q);
1313 }
30e553e3 1314 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
e532fa0e
RR		 1315 }
1316 } else {
4f85f5b3
RR		 1317 info->status.retry_count = tx_resp->failure_frame;
1318 info->flags =
1319 iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
e7d326ac 1320 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 1321 le32_to_cpu(tx_resp->rate_n_flags),
1322 info);
1323
1324 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
1325 "0x%x retries %d\n", txq_id,
1326 iwl_get_tx_fail_reason(status),
1327 status, le32_to_cpu(tx_resp->rate_n_flags),
1328 tx_resp->failure_frame);
1329
1330 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
1331 if (index != -1) {
1332 int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1333 if (tid != MAX_TID_COUNT)
e532fa0e 1334 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
4f85f5b3 1335 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
e532fa0e
RR		 1336 (txq_id >= 0) && priv->mac80211_registered)
1337 ieee80211_wake_queue(priv->hw, txq_id);
4f85f5b3 1338 if (tid != MAX_TID_COUNT)
30e553e3 1339 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
4f85f5b3 1340 }
e532fa0e 1341 }
e532fa0e
RR		 1342
1343 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1344 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
1345}
1346
c1adf9fb
GG		 1347/* Currently 5000 is the supperset of everything */
1348static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1349{
1350 return len;
1351}
1352
203566f3
EG		 1353static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1354{
1355 /* in 5000 the tx power calibration is done in uCode */
1356 priv->disable_tx_power_cal = 1;
1357}
1358
b600e4e1
RR		 1359static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1360{
7c616cba
TW		 1361 /* init calibration handlers */
1362 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1363 iwl5000_rx_calib_result;
1364 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1365 iwl5000_rx_calib_complete;
e532fa0e 1366 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
b600e4e1
RR		 1367}
1368
7c616cba 1369
87283cc1
RR		 1370static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1371{
1372 return (addr >= RTC_DATA_LOWER_BOUND) &&
1373 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1374}
1375
fe7a90c2
RR		 1376static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1377{
1378 int ret = 0;
1379 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1380 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1381 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1382
1383 if ((rxon1->flags == rxon2->flags) &&
1384 (rxon1->filter_flags == rxon2->filter_flags) &&
1385 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1386 (rxon1->ofdm_ht_single_stream_basic_rates ==
1387 rxon2->ofdm_ht_single_stream_basic_rates) &&
1388 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1389 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1390 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1391 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1392 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1393 (rxon1->rx_chain == rxon2->rx_chain) &&
1394 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1395 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1396 return 0;
1397 }
1398
1399 rxon_assoc.flags = priv->staging_rxon.flags;
1400 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1401 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1402 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1403 rxon_assoc.reserved1 = 0;
1404 rxon_assoc.reserved2 = 0;
1405 rxon_assoc.reserved3 = 0;
1406 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1407 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1408 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1409 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1410 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1411 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1412 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1413 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1414
1415 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1416 sizeof(rxon_assoc), &rxon_assoc, NULL);
1417 if (ret)
1418 return ret;
1419
1420 return ret;
1421}
630fe9b6
TW		 1422static int iwl5000_send_tx_power(struct iwl_priv *priv)
1423{
1424 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1425
1426 /* half dBm need to multiply */
1427 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
853554ac 1428 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
630fe9b6
TW		 1429 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1430 return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1431 sizeof(tx_power_cmd), &tx_power_cmd,
1432 NULL);
1433}
1434
5225640b 1435static void iwl5000_temperature(struct iwl_priv *priv)
8f91aecb
EG		 1436{
1437 /* store temperature from statistics (in Celsius) */
5225640b 1438 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
8f91aecb 1439}
fe7a90c2 1440
da8dec29 1441static struct iwl_hcmd_ops iwl5000_hcmd = {
fe7a90c2 1442 .rxon_assoc = iwl5000_send_rxon_assoc,
da8dec29
TW		 1443};
1444
1445static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
c1adf9fb 1446 .get_hcmd_size = iwl5000_get_hcmd_size,
2469bf2e 1447 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
33fd5033
EG		 1448 .gain_computation = iwl5000_gain_computation,
1449 .chain_noise_reset = iwl5000_chain_noise_reset,
a326a5d0 1450 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
da8dec29
TW		 1451};
1452
1453static struct iwl_lib_ops iwl5000_lib = {
fdd3e8a4 1454 .set_hw_params = iwl5000_hw_set_hw_params,
d4100dd9
RR		 1455 .alloc_shared_mem = iwl5000_alloc_shared_mem,
1456 .free_shared_mem = iwl5000_free_shared_mem,
d67f5489 1457 .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
7839fc03 1458 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
972cf447 1459 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
da1bc453 1460 .txq_set_sched = iwl5000_txq_set_sched,
e26e47d9
TW		 1461 .txq_agg_enable = iwl5000_txq_agg_enable,
1462 .txq_agg_disable = iwl5000_txq_agg_disable,
b600e4e1 1463 .rx_handler_setup = iwl5000_rx_handler_setup,
203566f3 1464 .setup_deferred_work = iwl5000_setup_deferred_work,
87283cc1 1465 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
dbb983b7 1466 .load_ucode = iwl5000_load_ucode,
99da1b48
RR		 1467 .init_alive_start = iwl5000_init_alive_start,
1468 .alive_notify = iwl5000_alive_notify,
630fe9b6 1469 .send_tx_power = iwl5000_send_tx_power,
8f91aecb 1470 .temperature = iwl5000_temperature,
30d59260
TW		 1471 .apm_ops = {
1472 .init = iwl5000_apm_init,
7f066108 1473 .reset = iwl5000_apm_reset,
f118a91d 1474 .stop = iwl5000_apm_stop,
5a835353 1475 .config = iwl5000_nic_config,
88acbd3b 1476 .set_pwr_src = iwl4965_set_pwr_src,
30d59260 1477 },
da8dec29 1478 .eeprom_ops = {
25ae3986
TW		 1479 .regulatory_bands = {
1480 EEPROM_5000_REG_BAND_1_CHANNELS,
1481 EEPROM_5000_REG_BAND_2_CHANNELS,
1482 EEPROM_5000_REG_BAND_3_CHANNELS,
1483 EEPROM_5000_REG_BAND_4_CHANNELS,
1484 EEPROM_5000_REG_BAND_5_CHANNELS,
1485 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1486 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1487 },
da8dec29
TW		 1488 .verify_signature = iwlcore_eeprom_verify_signature,
1489 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1490 .release_semaphore = iwlcore_eeprom_release_semaphore,
f1f69415 1491 .check_version = iwl5000_eeprom_check_version,
25ae3986 1492 .query_addr = iwl5000_eeprom_query_addr,
da8dec29
TW		 1493 },
1494};
1495
1496static struct iwl_ops iwl5000_ops = {
1497 .lib = &iwl5000_lib,
1498 .hcmd = &iwl5000_hcmd,
1499 .utils = &iwl5000_hcmd_utils,
1500};
1501
5a6a256e
TW		 1502static struct iwl_mod_params iwl50_mod_params = {
1503 .num_of_queues = IWL50_NUM_QUEUES,
1504 .enable_qos = 1,
1505 .amsdu_size_8K = 1,
3a1081e8 1506 .restart_fw = 1,
5a6a256e
TW		 1507 /* the rest are 0 by default */
1508};
1509
1510
1511struct iwl_cfg iwl5300_agn_cfg = {
1512 .name = "5300AGN",
1513 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1514 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1515 .ops = &iwl5000_ops,
25ae3986 1516 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
5a6a256e
TW		 1517 .mod_params = &iwl50_mod_params,
1518};
1519
47408639
EK		 1520struct iwl_cfg iwl5100_bg_cfg = {
1521 .name = "5100BG",
1522 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1523 .sku = IWL_SKU_G,
1524 .ops = &iwl5000_ops,
1525 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1526 .mod_params = &iwl50_mod_params,
1527};
1528
1529struct iwl_cfg iwl5100_abg_cfg = {
1530 .name = "5100ABG",
1531 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1532 .sku = IWL_SKU_A|IWL_SKU_G,
1533 .ops = &iwl5000_ops,
1534 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1535 .mod_params = &iwl50_mod_params,
1536};
1537
5a6a256e
TW		 1538struct iwl_cfg iwl5100_agn_cfg = {
1539 .name = "5100AGN",
1540 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1541 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1542 .ops = &iwl5000_ops,
25ae3986 1543 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
5a6a256e
TW		 1544 .mod_params = &iwl50_mod_params,
1545};
1546
1547struct iwl_cfg iwl5350_agn_cfg = {
1548 .name = "5350AGN",
1549 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1550 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1551 .ops = &iwl5000_ops,
25ae3986 1552 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
5a6a256e
TW		 1553 .mod_params = &iwl50_mod_params,
1554};
1555
1556module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1557MODULE_PARM_DESC(disable50,
1558 "manually disable the 50XX radio (default 0 [radio on])");
1559module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1560MODULE_PARM_DESC(swcrypto50,
1561 "using software crypto engine (default 0 [hardware])\n");
1562module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1563MODULE_PARM_DESC(debug50, "50XX debug output mask");
1564module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1565MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1566module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1567MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
49779293
RR		 1568module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1569MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
5a6a256e
TW		 1570module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1571MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
3a1081e8
EK		 1572module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1573MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
Linux kernel - Deliverables
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