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5a6a256e TW |
1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
23 | * | |
24 | *****************************************************************************/ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
5a6a256e TW |
28 | #include <linux/init.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/skbuff.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/wireless.h> | |
35 | #include <net/mac80211.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <asm/unaligned.h> | |
38 | ||
39 | #include "iwl-eeprom.h" | |
3e0d4cb1 | 40 | #include "iwl-dev.h" |
5a6a256e TW |
41 | #include "iwl-core.h" |
42 | #include "iwl-io.h" | |
e26e47d9 | 43 | #include "iwl-sta.h" |
5a6a256e TW |
44 | #include "iwl-helpers.h" |
45 | #include "iwl-5000-hw.h" | |
46 | ||
47 | #define IWL5000_UCODE_API "-1" | |
48 | ||
99da1b48 RR |
49 | static const u16 iwl5000_default_queue_to_tx_fifo[] = { |
50 | IWL_TX_FIFO_AC3, | |
51 | IWL_TX_FIFO_AC2, | |
52 | IWL_TX_FIFO_AC1, | |
53 | IWL_TX_FIFO_AC0, | |
54 | IWL50_CMD_FIFO_NUM, | |
55 | IWL_TX_FIFO_HCCA_1, | |
56 | IWL_TX_FIFO_HCCA_2 | |
57 | }; | |
58 | ||
46315e01 TW |
59 | /* FIXME: same implementation as 4965 */ |
60 | static int iwl5000_apm_stop_master(struct iwl_priv *priv) | |
61 | { | |
62 | int ret = 0; | |
63 | unsigned long flags; | |
64 | ||
65 | spin_lock_irqsave(&priv->lock, flags); | |
66 | ||
67 | /* set stop master bit */ | |
68 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); | |
69 | ||
70 | ret = iwl_poll_bit(priv, CSR_RESET, | |
71 | CSR_RESET_REG_FLAG_MASTER_DISABLED, | |
72 | CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); | |
73 | if (ret < 0) | |
74 | goto out; | |
75 | ||
76 | out: | |
77 | spin_unlock_irqrestore(&priv->lock, flags); | |
78 | IWL_DEBUG_INFO("stop master\n"); | |
79 | ||
80 | return ret; | |
81 | } | |
82 | ||
83 | ||
30d59260 TW |
84 | static int iwl5000_apm_init(struct iwl_priv *priv) |
85 | { | |
86 | int ret = 0; | |
87 | ||
88 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
89 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
90 | ||
8f061891 TW |
91 | /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */ |
92 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
93 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | |
94 | ||
4c43e0d0 TW |
95 | /* Set FH wait treshold to maximum (HW error during stress W/A) */ |
96 | iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); | |
97 | ||
98 | /* enable HAP INTA to move device L1a -> L0s */ | |
99 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
100 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); | |
101 | ||
30d59260 TW |
102 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); |
103 | ||
104 | /* set "initialization complete" bit to move adapter | |
105 | * D0U* --> D0A* state */ | |
106 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
107 | ||
108 | /* wait for clock stabilization */ | |
109 | ret = iwl_poll_bit(priv, CSR_GP_CNTRL, | |
110 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
111 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
112 | if (ret < 0) { | |
113 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
114 | return ret; | |
115 | } | |
116 | ||
117 | ret = iwl_grab_nic_access(priv); | |
118 | if (ret) | |
119 | return ret; | |
120 | ||
121 | /* enable DMA */ | |
8f061891 | 122 | iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); |
30d59260 TW |
123 | |
124 | udelay(20); | |
125 | ||
8f061891 | 126 | /* disable L1-Active */ |
30d59260 | 127 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, |
8f061891 | 128 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
30d59260 TW |
129 | |
130 | iwl_release_nic_access(priv); | |
131 | ||
132 | return ret; | |
133 | } | |
134 | ||
f118a91d TW |
135 | /* FIXME: this is indentical to 4965 */ |
136 | static void iwl5000_apm_stop(struct iwl_priv *priv) | |
137 | { | |
138 | unsigned long flags; | |
139 | ||
46315e01 | 140 | iwl5000_apm_stop_master(priv); |
f118a91d TW |
141 | |
142 | spin_lock_irqsave(&priv->lock, flags); | |
143 | ||
144 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
145 | ||
146 | udelay(10); | |
147 | ||
1d3e6c61 MA |
148 | /* clear "init complete" move adapter D0A* --> D0U state */ |
149 | iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
f118a91d TW |
150 | |
151 | spin_unlock_irqrestore(&priv->lock, flags); | |
152 | } | |
153 | ||
154 | ||
7f066108 TW |
155 | static int iwl5000_apm_reset(struct iwl_priv *priv) |
156 | { | |
157 | int ret = 0; | |
158 | unsigned long flags; | |
159 | ||
46315e01 | 160 | iwl5000_apm_stop_master(priv); |
7f066108 TW |
161 | |
162 | spin_lock_irqsave(&priv->lock, flags); | |
163 | ||
164 | iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET); | |
165 | ||
166 | udelay(10); | |
167 | ||
168 | ||
169 | /* FIXME: put here L1A -L0S w/a */ | |
170 | ||
171 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); | |
172 | ||
173 | /* set "initialization complete" bit to move adapter | |
174 | * D0U* --> D0A* state */ | |
175 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
176 | ||
177 | /* wait for clock stabilization */ | |
178 | ret = iwl_poll_bit(priv, CSR_GP_CNTRL, | |
179 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
180 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | |
181 | if (ret < 0) { | |
182 | IWL_DEBUG_INFO("Failed to init the card\n"); | |
183 | goto out; | |
184 | } | |
185 | ||
186 | ret = iwl_grab_nic_access(priv); | |
187 | if (ret) | |
188 | goto out; | |
189 | ||
190 | /* enable DMA */ | |
191 | iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); | |
192 | ||
193 | udelay(20); | |
194 | ||
195 | /* disable L1-Active */ | |
196 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, | |
197 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
198 | ||
199 | iwl_release_nic_access(priv); | |
200 | ||
201 | out: | |
202 | spin_unlock_irqrestore(&priv->lock, flags); | |
203 | ||
204 | return ret; | |
205 | } | |
206 | ||
207 | ||
5a835353 | 208 | static void iwl5000_nic_config(struct iwl_priv *priv) |
e86fe9f6 TW |
209 | { |
210 | unsigned long flags; | |
211 | u16 radio_cfg; | |
e7b63581 | 212 | u16 link; |
e86fe9f6 TW |
213 | |
214 | spin_lock_irqsave(&priv->lock, flags); | |
215 | ||
e7b63581 | 216 | pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link); |
e86fe9f6 | 217 | |
8f061891 | 218 | /* L1 is enabled by BIOS */ |
e7b63581 | 219 | if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN) |
8f061891 TW |
220 | /* diable L0S disabled L1A enabled */ |
221 | iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
222 | else | |
223 | /* L0S enabled L1A disabled */ | |
224 | iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); | |
e86fe9f6 TW |
225 | |
226 | radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); | |
227 | ||
228 | /* write radio config values to register */ | |
229 | if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX) | |
230 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
231 | EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | | |
232 | EEPROM_RF_CFG_STEP_MSK(radio_cfg) | | |
233 | EEPROM_RF_CFG_DASH_MSK(radio_cfg)); | |
234 | ||
235 | /* set CSR_HW_CONFIG_REG for uCode use */ | |
236 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
237 | CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | | |
238 | CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); | |
239 | ||
4c43e0d0 TW |
240 | /* W/A : NIC is stuck in a reset state after Early PCIe power off |
241 | * (PCIe power is lost before PERST# is asserted), | |
242 | * causing ME FW to lose ownership and not being able to obtain it back. | |
243 | */ | |
2d3db679 TW |
244 | iwl_grab_nic_access(priv); |
245 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, | |
4c43e0d0 TW |
246 | APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, |
247 | ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); | |
2d3db679 | 248 | iwl_release_nic_access(priv); |
4c43e0d0 | 249 | |
e86fe9f6 TW |
250 | spin_unlock_irqrestore(&priv->lock, flags); |
251 | } | |
252 | ||
253 | ||
254 | ||
25ae3986 TW |
255 | /* |
256 | * EEPROM | |
257 | */ | |
258 | static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) | |
259 | { | |
260 | u16 offset = 0; | |
261 | ||
262 | if ((address & INDIRECT_ADDRESS) == 0) | |
263 | return address; | |
264 | ||
265 | switch (address & INDIRECT_TYPE_MSK) { | |
266 | case INDIRECT_HOST: | |
267 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); | |
268 | break; | |
269 | case INDIRECT_GENERAL: | |
270 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); | |
271 | break; | |
272 | case INDIRECT_REGULATORY: | |
273 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); | |
274 | break; | |
275 | case INDIRECT_CALIBRATION: | |
276 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); | |
277 | break; | |
278 | case INDIRECT_PROCESS_ADJST: | |
279 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); | |
280 | break; | |
281 | case INDIRECT_OTHERS: | |
282 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); | |
283 | break; | |
284 | default: | |
285 | IWL_ERROR("illegal indirect type: 0x%X\n", | |
286 | address & INDIRECT_TYPE_MSK); | |
287 | break; | |
288 | } | |
289 | ||
290 | /* translate the offset from words to byte */ | |
291 | return (address & ADDRESS_MSK) + (offset << 1); | |
292 | } | |
293 | ||
f1f69415 TW |
294 | static int iwl5000_eeprom_check_version(struct iwl_priv *priv) |
295 | { | |
296 | u16 eeprom_ver; | |
297 | struct iwl_eeprom_calib_hdr { | |
298 | u8 version; | |
299 | u8 pa_type; | |
300 | u16 voltage; | |
301 | } *hdr; | |
302 | ||
303 | eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION); | |
304 | ||
305 | hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, | |
306 | EEPROM_5000_CALIB_ALL); | |
307 | ||
308 | if (eeprom_ver < EEPROM_5000_EEPROM_VERSION || | |
309 | hdr->version < EEPROM_5000_TX_POWER_VERSION) | |
310 | goto err; | |
311 | ||
312 | return 0; | |
313 | err: | |
314 | IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n", | |
315 | eeprom_ver, EEPROM_5000_EEPROM_VERSION, | |
316 | hdr->version, EEPROM_5000_TX_POWER_VERSION); | |
317 | return -EINVAL; | |
318 | ||
319 | } | |
320 | ||
33fd5033 EG |
321 | static void iwl5000_gain_computation(struct iwl_priv *priv, |
322 | u32 average_noise[NUM_RX_CHAINS], | |
323 | u16 min_average_noise_antenna_i, | |
324 | u32 min_average_noise) | |
325 | { | |
326 | int i; | |
327 | s32 delta_g; | |
328 | struct iwl_chain_noise_data *data = &priv->chain_noise_data; | |
329 | ||
330 | /* Find Gain Code for the antennas B and C */ | |
331 | for (i = 1; i < NUM_RX_CHAINS; i++) { | |
332 | if ((data->disconn_array[i])) { | |
333 | data->delta_gain_code[i] = 0; | |
334 | continue; | |
335 | } | |
336 | delta_g = (1000 * ((s32)average_noise[0] - | |
337 | (s32)average_noise[i])) / 1500; | |
338 | /* bound gain by 2 bits value max, 3rd bit is sign */ | |
339 | data->delta_gain_code[i] = | |
340 | min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE); | |
341 | ||
342 | if (delta_g < 0) | |
343 | /* set negative sign */ | |
344 | data->delta_gain_code[i] |= (1 << 2); | |
345 | } | |
346 | ||
347 | IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n", | |
348 | data->delta_gain_code[1], data->delta_gain_code[2]); | |
349 | ||
350 | if (!data->radio_write) { | |
351 | struct iwl5000_calibration_chain_noise_gain_cmd cmd; | |
352 | memset(&cmd, 0, sizeof(cmd)); | |
353 | ||
354 | cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; | |
355 | cmd.delta_gain_1 = data->delta_gain_code[1]; | |
356 | cmd.delta_gain_2 = data->delta_gain_code[2]; | |
357 | iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, | |
358 | sizeof(cmd), &cmd, NULL); | |
359 | ||
360 | data->radio_write = 1; | |
361 | data->state = IWL_CHAIN_NOISE_CALIBRATED; | |
362 | } | |
363 | ||
364 | data->chain_noise_a = 0; | |
365 | data->chain_noise_b = 0; | |
366 | data->chain_noise_c = 0; | |
367 | data->chain_signal_a = 0; | |
368 | data->chain_signal_b = 0; | |
369 | data->chain_signal_c = 0; | |
370 | data->beacon_count = 0; | |
371 | } | |
372 | ||
373 | static void iwl5000_chain_noise_reset(struct iwl_priv *priv) | |
374 | { | |
375 | struct iwl_chain_noise_data *data = &priv->chain_noise_data; | |
376 | ||
377 | if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { | |
378 | struct iwl5000_calibration_chain_noise_reset_cmd cmd; | |
379 | ||
380 | memset(&cmd, 0, sizeof(cmd)); | |
381 | cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; | |
382 | if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, | |
383 | sizeof(cmd), &cmd)) | |
384 | IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n"); | |
385 | data->state = IWL_CHAIN_NOISE_ACCUMULATE; | |
386 | IWL_DEBUG_CALIB("Run chain_noise_calibrate\n"); | |
387 | } | |
388 | } | |
389 | ||
a326a5d0 EG |
390 | static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, |
391 | __le32 *tx_flags) | |
392 | { | |
393 | if ((info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) || | |
394 | (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT)) | |
395 | *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK; | |
396 | else | |
397 | *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK; | |
398 | } | |
399 | ||
33fd5033 EG |
400 | static struct iwl_sensitivity_ranges iwl5000_sensitivity = { |
401 | .min_nrg_cck = 95, | |
402 | .max_nrg_cck = 0, | |
403 | .auto_corr_min_ofdm = 90, | |
404 | .auto_corr_min_ofdm_mrc = 170, | |
405 | .auto_corr_min_ofdm_x1 = 120, | |
406 | .auto_corr_min_ofdm_mrc_x1 = 240, | |
407 | ||
408 | .auto_corr_max_ofdm = 120, | |
409 | .auto_corr_max_ofdm_mrc = 210, | |
410 | .auto_corr_max_ofdm_x1 = 155, | |
411 | .auto_corr_max_ofdm_mrc_x1 = 290, | |
412 | ||
413 | .auto_corr_min_cck = 125, | |
414 | .auto_corr_max_cck = 200, | |
415 | .auto_corr_min_cck_mrc = 170, | |
416 | .auto_corr_max_cck_mrc = 400, | |
417 | .nrg_th_cck = 95, | |
418 | .nrg_th_ofdm = 95, | |
419 | }; | |
420 | ||
25ae3986 TW |
421 | static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, |
422 | size_t offset) | |
423 | { | |
424 | u32 address = eeprom_indirect_address(priv, offset); | |
425 | BUG_ON(address >= priv->cfg->eeprom_size); | |
426 | return &priv->eeprom[address]; | |
427 | } | |
428 | ||
7c616cba TW |
429 | /* |
430 | * Calibration | |
431 | */ | |
432 | static int iwl5000_send_Xtal_calib(struct iwl_priv *priv) | |
433 | { | |
434 | u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); | |
435 | ||
436 | struct iwl5000_calibration cal_cmd = { | |
437 | .op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD, | |
438 | .data = { | |
439 | (u8)xtal_calib[0], | |
440 | (u8)xtal_calib[1], | |
441 | } | |
442 | }; | |
443 | ||
444 | return iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, | |
445 | sizeof(cal_cmd), &cal_cmd); | |
446 | } | |
447 | ||
7c616cba TW |
448 | static int iwl5000_send_calib_cfg(struct iwl_priv *priv) |
449 | { | |
450 | struct iwl5000_calib_cfg_cmd calib_cfg_cmd; | |
451 | struct iwl_host_cmd cmd = { | |
452 | .id = CALIBRATION_CFG_CMD, | |
453 | .len = sizeof(struct iwl5000_calib_cfg_cmd), | |
454 | .data = &calib_cfg_cmd, | |
455 | }; | |
456 | ||
457 | memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); | |
458 | calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; | |
459 | calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; | |
460 | calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; | |
461 | calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; | |
462 | ||
463 | return iwl_send_cmd(priv, &cmd); | |
464 | } | |
465 | ||
466 | static void iwl5000_rx_calib_result(struct iwl_priv *priv, | |
467 | struct iwl_rx_mem_buffer *rxb) | |
468 | { | |
469 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; | |
470 | struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw; | |
471 | int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK; | |
6e21f2c1 | 472 | int index; |
7c616cba TW |
473 | |
474 | /* reduce the size of the length field itself */ | |
475 | len -= 4; | |
476 | ||
6e21f2c1 TW |
477 | /* Define the order in which the results will be sent to the runtime |
478 | * uCode. iwl_send_calib_results sends them in a row according to their | |
479 | * index. We sort them here */ | |
7c616cba TW |
480 | switch (hdr->op_code) { |
481 | case IWL5000_PHY_CALIBRATE_LO_CMD: | |
6e21f2c1 | 482 | index = IWL5000_CALIB_LO; |
7c616cba TW |
483 | break; |
484 | case IWL5000_PHY_CALIBRATE_TX_IQ_CMD: | |
6e21f2c1 | 485 | index = IWL5000_CALIB_TX_IQ; |
7c616cba TW |
486 | break; |
487 | case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD: | |
6e21f2c1 | 488 | index = IWL5000_CALIB_TX_IQ_PERD; |
7c616cba TW |
489 | break; |
490 | default: | |
491 | IWL_ERROR("Unknown calibration notification %d\n", | |
492 | hdr->op_code); | |
493 | return; | |
494 | } | |
6e21f2c1 | 495 | iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len); |
7c616cba TW |
496 | } |
497 | ||
498 | static void iwl5000_rx_calib_complete(struct iwl_priv *priv, | |
499 | struct iwl_rx_mem_buffer *rxb) | |
500 | { | |
501 | IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n"); | |
502 | queue_work(priv->workqueue, &priv->restart); | |
503 | } | |
504 | ||
dbb983b7 RR |
505 | /* |
506 | * ucode | |
507 | */ | |
508 | static int iwl5000_load_section(struct iwl_priv *priv, | |
509 | struct fw_desc *image, | |
510 | u32 dst_addr) | |
511 | { | |
512 | int ret = 0; | |
513 | unsigned long flags; | |
514 | ||
515 | dma_addr_t phy_addr = image->p_addr; | |
516 | u32 byte_cnt = image->len; | |
517 | ||
518 | spin_lock_irqsave(&priv->lock, flags); | |
519 | ret = iwl_grab_nic_access(priv); | |
520 | if (ret) { | |
521 | spin_unlock_irqrestore(&priv->lock, flags); | |
522 | return ret; | |
523 | } | |
524 | ||
525 | iwl_write_direct32(priv, | |
526 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
527 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
528 | ||
529 | iwl_write_direct32(priv, | |
530 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); | |
531 | ||
532 | iwl_write_direct32(priv, | |
533 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), | |
534 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
535 | ||
dbb983b7 | 536 | iwl_write_direct32(priv, |
f0b9f5cb TW |
537 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
538 | (iwl_get_dma_hi_address(phy_addr) | |
539 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); | |
540 | ||
dbb983b7 RR |
541 | iwl_write_direct32(priv, |
542 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), | |
543 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
544 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
545 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
546 | ||
547 | iwl_write_direct32(priv, | |
548 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
549 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
550 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL | | |
551 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); | |
552 | ||
553 | iwl_release_nic_access(priv); | |
554 | spin_unlock_irqrestore(&priv->lock, flags); | |
555 | return 0; | |
556 | } | |
557 | ||
558 | static int iwl5000_load_given_ucode(struct iwl_priv *priv, | |
559 | struct fw_desc *inst_image, | |
560 | struct fw_desc *data_image) | |
561 | { | |
562 | int ret = 0; | |
563 | ||
564 | ret = iwl5000_load_section( | |
565 | priv, inst_image, RTC_INST_LOWER_BOUND); | |
566 | if (ret) | |
567 | return ret; | |
568 | ||
569 | IWL_DEBUG_INFO("INST uCode section being loaded...\n"); | |
570 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
571 | priv->ucode_write_complete, 5 * HZ); | |
572 | if (ret == -ERESTARTSYS) { | |
573 | IWL_ERROR("Could not load the INST uCode section due " | |
574 | "to interrupt\n"); | |
575 | return ret; | |
576 | } | |
577 | if (!ret) { | |
578 | IWL_ERROR("Could not load the INST uCode section\n"); | |
579 | return -ETIMEDOUT; | |
580 | } | |
581 | ||
582 | priv->ucode_write_complete = 0; | |
583 | ||
584 | ret = iwl5000_load_section( | |
585 | priv, data_image, RTC_DATA_LOWER_BOUND); | |
586 | if (ret) | |
587 | return ret; | |
588 | ||
589 | IWL_DEBUG_INFO("DATA uCode section being loaded...\n"); | |
590 | ||
591 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
592 | priv->ucode_write_complete, 5 * HZ); | |
593 | if (ret == -ERESTARTSYS) { | |
594 | IWL_ERROR("Could not load the INST uCode section due " | |
595 | "to interrupt\n"); | |
596 | return ret; | |
597 | } else if (!ret) { | |
598 | IWL_ERROR("Could not load the DATA uCode section\n"); | |
599 | return -ETIMEDOUT; | |
600 | } else | |
601 | ret = 0; | |
602 | ||
603 | priv->ucode_write_complete = 0; | |
604 | ||
605 | return ret; | |
606 | } | |
607 | ||
608 | static int iwl5000_load_ucode(struct iwl_priv *priv) | |
609 | { | |
610 | int ret = 0; | |
611 | ||
612 | /* check whether init ucode should be loaded, or rather runtime ucode */ | |
613 | if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { | |
614 | IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n"); | |
615 | ret = iwl5000_load_given_ucode(priv, | |
616 | &priv->ucode_init, &priv->ucode_init_data); | |
617 | if (!ret) { | |
618 | IWL_DEBUG_INFO("Init ucode load complete.\n"); | |
619 | priv->ucode_type = UCODE_INIT; | |
620 | } | |
621 | } else { | |
622 | IWL_DEBUG_INFO("Init ucode not found, or already loaded. " | |
623 | "Loading runtime ucode...\n"); | |
624 | ret = iwl5000_load_given_ucode(priv, | |
625 | &priv->ucode_code, &priv->ucode_data); | |
626 | if (!ret) { | |
627 | IWL_DEBUG_INFO("Runtime ucode load complete.\n"); | |
628 | priv->ucode_type = UCODE_RT; | |
629 | } | |
630 | } | |
631 | ||
632 | return ret; | |
633 | } | |
634 | ||
99da1b48 RR |
635 | static void iwl5000_init_alive_start(struct iwl_priv *priv) |
636 | { | |
637 | int ret = 0; | |
638 | ||
639 | /* Check alive response for "valid" sign from uCode */ | |
640 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
641 | /* We had an error bringing up the hardware, so take it | |
642 | * all the way back down so we can try again */ | |
643 | IWL_DEBUG_INFO("Initialize Alive failed.\n"); | |
644 | goto restart; | |
645 | } | |
646 | ||
647 | /* initialize uCode was loaded... verify inst image. | |
648 | * This is a paranoid check, because we would not have gotten the | |
649 | * "initialize" alive if code weren't properly loaded. */ | |
650 | if (iwl_verify_ucode(priv)) { | |
651 | /* Runtime instruction load was bad; | |
652 | * take it all the way back down so we can try again */ | |
653 | IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n"); | |
654 | goto restart; | |
655 | } | |
656 | ||
37deb2a0 | 657 | iwl_clear_stations_table(priv); |
99da1b48 RR |
658 | ret = priv->cfg->ops->lib->alive_notify(priv); |
659 | if (ret) { | |
660 | IWL_WARNING("Could not complete ALIVE transition: %d\n", ret); | |
661 | goto restart; | |
662 | } | |
663 | ||
7c616cba | 664 | iwl5000_send_calib_cfg(priv); |
99da1b48 RR |
665 | return; |
666 | ||
667 | restart: | |
668 | /* real restart (first load init_ucode) */ | |
669 | queue_work(priv->workqueue, &priv->restart); | |
670 | } | |
671 | ||
672 | static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, | |
673 | int txq_id, u32 index) | |
674 | { | |
675 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, | |
676 | (index & 0xff) | (txq_id << 8)); | |
677 | iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); | |
678 | } | |
679 | ||
680 | static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, | |
681 | struct iwl_tx_queue *txq, | |
682 | int tx_fifo_id, int scd_retry) | |
683 | { | |
684 | int txq_id = txq->q.id; | |
685 | int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0; | |
686 | ||
687 | iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), | |
688 | (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
689 | (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | | |
690 | (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | | |
691 | IWL50_SCD_QUEUE_STTS_REG_MSK); | |
692 | ||
693 | txq->sched_retry = scd_retry; | |
694 | ||
695 | IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n", | |
696 | active ? "Activate" : "Deactivate", | |
697 | scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); | |
698 | } | |
699 | ||
9636e583 RR |
700 | static int iwl5000_send_wimax_coex(struct iwl_priv *priv) |
701 | { | |
702 | struct iwl_wimax_coex_cmd coex_cmd; | |
703 | ||
704 | memset(&coex_cmd, 0, sizeof(coex_cmd)); | |
705 | ||
706 | return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, | |
707 | sizeof(coex_cmd), &coex_cmd); | |
708 | } | |
709 | ||
99da1b48 RR |
710 | static int iwl5000_alive_notify(struct iwl_priv *priv) |
711 | { | |
712 | u32 a; | |
713 | int i = 0; | |
714 | unsigned long flags; | |
715 | int ret; | |
716 | ||
717 | spin_lock_irqsave(&priv->lock, flags); | |
718 | ||
719 | ret = iwl_grab_nic_access(priv); | |
720 | if (ret) { | |
721 | spin_unlock_irqrestore(&priv->lock, flags); | |
722 | return ret; | |
723 | } | |
724 | ||
725 | priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); | |
726 | a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; | |
727 | for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; | |
728 | a += 4) | |
729 | iwl_write_targ_mem(priv, a, 0); | |
730 | for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; | |
731 | a += 4) | |
732 | iwl_write_targ_mem(priv, a, 0); | |
733 | for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4) | |
734 | iwl_write_targ_mem(priv, a, 0); | |
735 | ||
736 | iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, | |
737 | (priv->shared_phys + | |
738 | offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10); | |
739 | iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, | |
740 | IWL50_SCD_QUEUECHAIN_SEL_ALL( | |
741 | priv->hw_params.max_txq_num)); | |
742 | iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); | |
743 | ||
744 | /* initiate the queues */ | |
745 | for (i = 0; i < priv->hw_params.max_txq_num; i++) { | |
746 | iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); | |
747 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); | |
748 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
749 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); | |
750 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
751 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + | |
752 | sizeof(u32), | |
753 | ((SCD_WIN_SIZE << | |
754 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
755 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
756 | ((SCD_FRAME_LIMIT << | |
757 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
758 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
759 | } | |
760 | ||
761 | iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, | |
da1bc453 | 762 | IWL_MASK(0, priv->hw_params.max_txq_num)); |
99da1b48 | 763 | |
da1bc453 TW |
764 | /* Activate all Tx DMA/FIFO channels */ |
765 | priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); | |
99da1b48 RR |
766 | |
767 | iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); | |
768 | /* map qos queues to fifos one-to-one */ | |
769 | for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { | |
770 | int ac = iwl5000_default_queue_to_tx_fifo[i]; | |
771 | iwl_txq_ctx_activate(priv, i); | |
772 | iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); | |
773 | } | |
774 | /* TODO - need to initialize those FIFOs inside the loop above, | |
775 | * not only mark them as active */ | |
776 | iwl_txq_ctx_activate(priv, 4); | |
777 | iwl_txq_ctx_activate(priv, 7); | |
778 | iwl_txq_ctx_activate(priv, 8); | |
779 | iwl_txq_ctx_activate(priv, 9); | |
780 | ||
781 | iwl_release_nic_access(priv); | |
782 | spin_unlock_irqrestore(&priv->lock, flags); | |
783 | ||
7c616cba | 784 | |
9636e583 RR |
785 | iwl5000_send_wimax_coex(priv); |
786 | ||
7c616cba TW |
787 | iwl5000_send_Xtal_calib(priv); |
788 | ||
0a078ffa | 789 | if (priv->ucode_type == UCODE_RT) |
6e21f2c1 | 790 | iwl_send_calib_results(priv); |
7c616cba | 791 | |
99da1b48 RR |
792 | return 0; |
793 | } | |
794 | ||
fdd3e8a4 TW |
795 | static int iwl5000_hw_set_hw_params(struct iwl_priv *priv) |
796 | { | |
797 | if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) || | |
798 | (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) { | |
799 | IWL_ERROR("invalid queues_num, should be between %d and %d\n", | |
800 | IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES); | |
801 | return -EINVAL; | |
802 | } | |
25ae3986 | 803 | |
fdd3e8a4 | 804 | priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues; |
7f3e4bb6 | 805 | priv->hw_params.first_ampdu_q = IWL50_FIRST_AMPDU_QUEUE; |
fdd3e8a4 TW |
806 | priv->hw_params.max_stations = IWL5000_STATION_COUNT; |
807 | priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; | |
808 | priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; | |
809 | priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; | |
da154e30 | 810 | priv->hw_params.max_bsm_size = 0; |
fdd3e8a4 TW |
811 | priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) | |
812 | BIT(IEEE80211_BAND_5GHZ); | |
33fd5033 | 813 | priv->hw_params.sens = &iwl5000_sensitivity; |
fdd3e8a4 TW |
814 | |
815 | switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { | |
816 | case CSR_HW_REV_TYPE_5100: | |
817 | case CSR_HW_REV_TYPE_5150: | |
818 | priv->hw_params.tx_chains_num = 1; | |
819 | priv->hw_params.rx_chains_num = 2; | |
820 | /* FIXME: move to ANT_A, ANT_B, ANT_C enum */ | |
1179f18d TW |
821 | priv->hw_params.valid_tx_ant = ANT_A; |
822 | priv->hw_params.valid_rx_ant = ANT_AB; | |
fdd3e8a4 TW |
823 | break; |
824 | case CSR_HW_REV_TYPE_5300: | |
825 | case CSR_HW_REV_TYPE_5350: | |
826 | priv->hw_params.tx_chains_num = 3; | |
827 | priv->hw_params.rx_chains_num = 3; | |
1179f18d TW |
828 | priv->hw_params.valid_tx_ant = ANT_ABC; |
829 | priv->hw_params.valid_rx_ant = ANT_ABC; | |
fdd3e8a4 TW |
830 | break; |
831 | } | |
c031bf80 EG |
832 | |
833 | switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { | |
834 | case CSR_HW_REV_TYPE_5100: | |
835 | case CSR_HW_REV_TYPE_5300: | |
d5d7c584 TW |
836 | case CSR_HW_REV_TYPE_5350: |
837 | /* 5X00 and 5350 wants in Celsius */ | |
c031bf80 EG |
838 | priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD; |
839 | break; | |
840 | case CSR_HW_REV_TYPE_5150: | |
d5d7c584 | 841 | /* 5150 wants in Kelvin */ |
c031bf80 EG |
842 | priv->hw_params.ct_kill_threshold = |
843 | CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD); | |
844 | break; | |
845 | } | |
846 | ||
fdd3e8a4 TW |
847 | return 0; |
848 | } | |
d4100dd9 RR |
849 | |
850 | static int iwl5000_alloc_shared_mem(struct iwl_priv *priv) | |
851 | { | |
852 | priv->shared_virt = pci_alloc_consistent(priv->pci_dev, | |
853 | sizeof(struct iwl5000_shared), | |
854 | &priv->shared_phys); | |
855 | if (!priv->shared_virt) | |
856 | return -ENOMEM; | |
857 | ||
858 | memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared)); | |
859 | ||
d67f5489 RR |
860 | priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed); |
861 | ||
d4100dd9 RR |
862 | return 0; |
863 | } | |
864 | ||
865 | static void iwl5000_free_shared_mem(struct iwl_priv *priv) | |
866 | { | |
867 | if (priv->shared_virt) | |
868 | pci_free_consistent(priv->pci_dev, | |
869 | sizeof(struct iwl5000_shared), | |
870 | priv->shared_virt, | |
871 | priv->shared_phys); | |
872 | } | |
873 | ||
d67f5489 RR |
874 | static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv) |
875 | { | |
876 | struct iwl5000_shared *s = priv->shared_virt; | |
877 | return le32_to_cpu(s->rb_closed) & 0xFFF; | |
878 | } | |
879 | ||
7839fc03 EG |
880 | /** |
881 | * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
882 | */ | |
883 | static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, | |
16466903 | 884 | struct iwl_tx_queue *txq, |
7839fc03 EG |
885 | u16 byte_cnt) |
886 | { | |
887 | struct iwl5000_shared *shared_data = priv->shared_virt; | |
888 | int txq_id = txq->q.id; | |
889 | u8 sec_ctl = 0; | |
890 | u8 sta = 0; | |
891 | int len; | |
892 | ||
893 | len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
894 | ||
895 | if (txq_id != IWL_CMD_QUEUE_NUM) { | |
da99c4b6 GG |
896 | sta = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; |
897 | sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; | |
7839fc03 EG |
898 | |
899 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
900 | case TX_CMD_SEC_CCM: | |
901 | len += CCMP_MIC_LEN; | |
902 | break; | |
903 | case TX_CMD_SEC_TKIP: | |
904 | len += TKIP_ICV_LEN; | |
905 | break; | |
906 | case TX_CMD_SEC_WEP: | |
907 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
908 | break; | |
909 | } | |
910 | } | |
911 | ||
912 | IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. | |
913 | tfd_offset[txq->q.write_ptr], byte_cnt, len); | |
914 | ||
915 | IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. | |
916 | tfd_offset[txq->q.write_ptr], sta_id, sta); | |
917 | ||
918 | if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) { | |
919 | IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. | |
920 | tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr], | |
921 | byte_cnt, len); | |
922 | IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id]. | |
923 | tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr], | |
924 | sta_id, sta); | |
925 | } | |
926 | } | |
927 | ||
972cf447 TW |
928 | static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, |
929 | struct iwl_tx_queue *txq) | |
930 | { | |
931 | int txq_id = txq->q.id; | |
932 | struct iwl5000_shared *shared_data = priv->shared_virt; | |
933 | u8 sta = 0; | |
934 | ||
935 | if (txq_id != IWL_CMD_QUEUE_NUM) | |
da99c4b6 | 936 | sta = txq->cmd[txq->q.read_ptr]->cmd.tx.sta_id; |
972cf447 TW |
937 | |
938 | shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr]. | |
939 | val = cpu_to_le16(1 | (sta << 12)); | |
940 | ||
941 | if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) { | |
942 | shared_data->queues_byte_cnt_tbls[txq_id]. | |
943 | tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr]. | |
944 | val = cpu_to_le16(1 | (sta << 12)); | |
945 | } | |
946 | } | |
947 | ||
e26e47d9 TW |
948 | static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, |
949 | u16 txq_id) | |
950 | { | |
951 | u32 tbl_dw_addr; | |
952 | u32 tbl_dw; | |
953 | u16 scd_q2ratid; | |
954 | ||
955 | scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
956 | ||
957 | tbl_dw_addr = priv->scd_base_addr + | |
958 | IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); | |
959 | ||
960 | tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); | |
961 | ||
962 | if (txq_id & 0x1) | |
963 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
964 | else | |
965 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
966 | ||
967 | iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); | |
968 | ||
969 | return 0; | |
970 | } | |
971 | static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) | |
972 | { | |
973 | /* Simply stop the queue, but don't change any configuration; | |
974 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
975 | iwl_write_prph(priv, | |
976 | IWL50_SCD_QUEUE_STATUS_BITS(txq_id), | |
977 | (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
978 | (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
979 | } | |
980 | ||
981 | static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, | |
982 | int tx_fifo, int sta_id, int tid, u16 ssn_idx) | |
983 | { | |
984 | unsigned long flags; | |
985 | int ret; | |
986 | u16 ra_tid; | |
987 | ||
9f17b318 TW |
988 | if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || |
989 | (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { | |
990 | IWL_WARNING("queue number out of range: %d, must be %d to %d\n", | |
991 | txq_id, IWL50_FIRST_AMPDU_QUEUE, | |
992 | IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); | |
993 | return -EINVAL; | |
994 | } | |
e26e47d9 TW |
995 | |
996 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
997 | ||
998 | /* Modify device's station table to Tx this TID */ | |
999 | iwl_sta_modify_enable_tid_tx(priv, sta_id, tid); | |
1000 | ||
1001 | spin_lock_irqsave(&priv->lock, flags); | |
1002 | ret = iwl_grab_nic_access(priv); | |
1003 | if (ret) { | |
1004 | spin_unlock_irqrestore(&priv->lock, flags); | |
1005 | return ret; | |
1006 | } | |
1007 | ||
1008 | /* Stop this Tx queue before configuring it */ | |
1009 | iwl5000_tx_queue_stop_scheduler(priv, txq_id); | |
1010 | ||
1011 | /* Map receiver-address / traffic-ID to this queue */ | |
1012 | iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id); | |
1013 | ||
1014 | /* Set this queue as a chain-building queue */ | |
1015 | iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id)); | |
1016 | ||
1017 | /* enable aggregations for the queue */ | |
1018 | iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id)); | |
1019 | ||
1020 | /* Place first TFD at index corresponding to start sequence number. | |
1021 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
1022 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
1023 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
1024 | iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); | |
1025 | ||
1026 | /* Set up Tx window size and frame limit for this queue */ | |
1027 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
1028 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + | |
1029 | sizeof(u32), | |
1030 | ((SCD_WIN_SIZE << | |
1031 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
1032 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
1033 | ((SCD_FRAME_LIMIT << | |
1034 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
1035 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
1036 | ||
1037 | iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); | |
1038 | ||
1039 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
1040 | iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); | |
1041 | ||
1042 | iwl_release_nic_access(priv); | |
1043 | spin_unlock_irqrestore(&priv->lock, flags); | |
1044 | ||
1045 | return 0; | |
1046 | } | |
1047 | ||
1048 | static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, | |
1049 | u16 ssn_idx, u8 tx_fifo) | |
1050 | { | |
1051 | int ret; | |
1052 | ||
9f17b318 TW |
1053 | if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || |
1054 | (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { | |
1055 | IWL_WARNING("queue number out of range: %d, must be %d to %d\n", | |
1056 | txq_id, IWL50_FIRST_AMPDU_QUEUE, | |
1057 | IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); | |
e26e47d9 TW |
1058 | return -EINVAL; |
1059 | } | |
1060 | ||
1061 | ret = iwl_grab_nic_access(priv); | |
1062 | if (ret) | |
1063 | return ret; | |
1064 | ||
1065 | iwl5000_tx_queue_stop_scheduler(priv, txq_id); | |
1066 | ||
1067 | iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); | |
1068 | ||
1069 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
1070 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
1071 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
1072 | iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); | |
1073 | ||
1074 | iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); | |
1075 | iwl_txq_ctx_deactivate(priv, txq_id); | |
1076 | iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); | |
1077 | ||
1078 | iwl_release_nic_access(priv); | |
1079 | ||
1080 | return 0; | |
1081 | } | |
1082 | ||
2469bf2e TW |
1083 | static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) |
1084 | { | |
1085 | u16 size = (u16)sizeof(struct iwl_addsta_cmd); | |
1086 | memcpy(data, cmd, size); | |
1087 | return size; | |
1088 | } | |
1089 | ||
1090 | ||
da1bc453 TW |
1091 | /* |
1092 | * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask | |
1093 | * must be called under priv->lock and mac access | |
1094 | */ | |
1095 | static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) | |
5a676bbe | 1096 | { |
da1bc453 | 1097 | iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); |
5a676bbe RR |
1098 | } |
1099 | ||
e532fa0e RR |
1100 | |
1101 | static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) | |
1102 | { | |
3ac7f146 | 1103 | return le32_to_cpup((__le32 *)&tx_resp->status + |
25a6572c | 1104 | tx_resp->frame_count) & MAX_SN; |
e532fa0e RR |
1105 | } |
1106 | ||
1107 | static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, | |
1108 | struct iwl_ht_agg *agg, | |
1109 | struct iwl5000_tx_resp *tx_resp, | |
25a6572c | 1110 | int txq_id, u16 start_idx) |
e532fa0e RR |
1111 | { |
1112 | u16 status; | |
1113 | struct agg_tx_status *frame_status = &tx_resp->status; | |
1114 | struct ieee80211_tx_info *info = NULL; | |
1115 | struct ieee80211_hdr *hdr = NULL; | |
e7d326ac | 1116 | u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); |
25a6572c | 1117 | int i, sh, idx; |
e532fa0e RR |
1118 | u16 seq; |
1119 | ||
1120 | if (agg->wait_for_ba) | |
1121 | IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n"); | |
1122 | ||
1123 | agg->frame_count = tx_resp->frame_count; | |
1124 | agg->start_idx = start_idx; | |
e7d326ac | 1125 | agg->rate_n_flags = rate_n_flags; |
e532fa0e RR |
1126 | agg->bitmap = 0; |
1127 | ||
1128 | /* # frames attempted by Tx command */ | |
1129 | if (agg->frame_count == 1) { | |
1130 | /* Only one frame was attempted; no block-ack will arrive */ | |
1131 | status = le16_to_cpu(frame_status[0].status); | |
25a6572c | 1132 | idx = start_idx; |
e532fa0e RR |
1133 | |
1134 | /* FIXME: code repetition */ | |
1135 | IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", | |
1136 | agg->frame_count, agg->start_idx, idx); | |
1137 | ||
1138 | info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); | |
1139 | info->status.retry_count = tx_resp->failure_frame; | |
1140 | info->flags &= ~IEEE80211_TX_CTL_AMPDU; | |
1141 | info->flags |= iwl_is_tx_success(status)? | |
1142 | IEEE80211_TX_STAT_ACK : 0; | |
e7d326ac TW |
1143 | iwl_hwrate_to_tx_control(priv, rate_n_flags, info); |
1144 | ||
e532fa0e RR |
1145 | /* FIXME: code repetition end */ |
1146 | ||
1147 | IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n", | |
1148 | status & 0xff, tx_resp->failure_frame); | |
e7d326ac | 1149 | IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags); |
e532fa0e RR |
1150 | |
1151 | agg->wait_for_ba = 0; | |
1152 | } else { | |
1153 | /* Two or more frames were attempted; expect block-ack */ | |
1154 | u64 bitmap = 0; | |
1155 | int start = agg->start_idx; | |
1156 | ||
1157 | /* Construct bit-map of pending frames within Tx window */ | |
1158 | for (i = 0; i < agg->frame_count; i++) { | |
1159 | u16 sc; | |
1160 | status = le16_to_cpu(frame_status[i].status); | |
1161 | seq = le16_to_cpu(frame_status[i].sequence); | |
1162 | idx = SEQ_TO_INDEX(seq); | |
1163 | txq_id = SEQ_TO_QUEUE(seq); | |
1164 | ||
1165 | if (status & (AGG_TX_STATE_FEW_BYTES_MSK | | |
1166 | AGG_TX_STATE_ABORT_MSK)) | |
1167 | continue; | |
1168 | ||
1169 | IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", | |
1170 | agg->frame_count, txq_id, idx); | |
1171 | ||
1172 | hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); | |
1173 | ||
1174 | sc = le16_to_cpu(hdr->seq_ctrl); | |
1175 | if (idx != (SEQ_TO_SN(sc) & 0xff)) { | |
1176 | IWL_ERROR("BUG_ON idx doesn't match seq control" | |
1177 | " idx=%d, seq_idx=%d, seq=%d\n", | |
1178 | idx, SEQ_TO_SN(sc), | |
1179 | hdr->seq_ctrl); | |
1180 | return -1; | |
1181 | } | |
1182 | ||
1183 | IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", | |
1184 | i, idx, SEQ_TO_SN(sc)); | |
1185 | ||
1186 | sh = idx - start; | |
1187 | if (sh > 64) { | |
1188 | sh = (start - idx) + 0xff; | |
1189 | bitmap = bitmap << sh; | |
1190 | sh = 0; | |
1191 | start = idx; | |
1192 | } else if (sh < -64) | |
1193 | sh = 0xff - (start - idx); | |
1194 | else if (sh < 0) { | |
1195 | sh = start - idx; | |
1196 | start = idx; | |
1197 | bitmap = bitmap << sh; | |
1198 | sh = 0; | |
1199 | } | |
4aa41f12 EG |
1200 | bitmap |= 1ULL << sh; |
1201 | IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n", | |
1202 | start, (unsigned long long)bitmap); | |
e532fa0e RR |
1203 | } |
1204 | ||
1205 | agg->bitmap = bitmap; | |
1206 | agg->start_idx = start; | |
e532fa0e RR |
1207 | IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", |
1208 | agg->frame_count, agg->start_idx, | |
1209 | (unsigned long long)agg->bitmap); | |
1210 | ||
1211 | if (bitmap) | |
1212 | agg->wait_for_ba = 1; | |
1213 | } | |
1214 | return 0; | |
1215 | } | |
1216 | ||
1217 | static void iwl5000_rx_reply_tx(struct iwl_priv *priv, | |
1218 | struct iwl_rx_mem_buffer *rxb) | |
1219 | { | |
1220 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1221 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | |
1222 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1223 | int index = SEQ_TO_INDEX(sequence); | |
1224 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1225 | struct ieee80211_tx_info *info; | |
1226 | struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; | |
1227 | u32 status = le16_to_cpu(tx_resp->status.status); | |
e532fa0e | 1228 | int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION; |
e532fa0e RR |
1229 | struct ieee80211_hdr *hdr; |
1230 | u8 *qc = NULL; | |
e532fa0e RR |
1231 | |
1232 | if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { | |
1233 | IWL_ERROR("Read index for DMA queue txq_id (%d) index %d " | |
1234 | "is out of range [0-%d] %d %d\n", txq_id, | |
1235 | index, txq->q.n_bd, txq->q.write_ptr, | |
1236 | txq->q.read_ptr); | |
1237 | return; | |
1238 | } | |
1239 | ||
1240 | info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); | |
1241 | memset(&info->status, 0, sizeof(info->status)); | |
1242 | ||
e532fa0e | 1243 | hdr = iwl_tx_queue_get_hdr(priv, txq_id, index); |
fd7c8a40 HH |
1244 | if (ieee80211_is_data_qos(hdr->frame_control)) { |
1245 | qc = ieee80211_get_qos_ctl(hdr); | |
e532fa0e RR |
1246 | tid = qc[0] & 0xf; |
1247 | } | |
1248 | ||
1249 | sta_id = iwl_get_ra_sta_id(priv, hdr); | |
1250 | if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) { | |
1251 | IWL_ERROR("Station not known\n"); | |
1252 | return; | |
1253 | } | |
1254 | ||
1255 | if (txq->sched_retry) { | |
1256 | const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp); | |
1257 | struct iwl_ht_agg *agg = NULL; | |
1258 | ||
1259 | if (!qc) | |
1260 | return; | |
1261 | ||
1262 | agg = &priv->stations[sta_id].tid[tid].agg; | |
1263 | ||
25a6572c | 1264 | iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); |
e532fa0e | 1265 | |
3235427e RR |
1266 | /* check if BAR is needed */ |
1267 | if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) | |
1268 | info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; | |
e532fa0e RR |
1269 | |
1270 | if (txq->q.read_ptr != (scd_ssn & 0xff)) { | |
1271 | int freed, ampdu_q; | |
1272 | index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); | |
1273 | IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn " | |
1274 | "%d index %d\n", scd_ssn , index); | |
17b88929 | 1275 | freed = iwl_tx_queue_reclaim(priv, txq_id, index); |
e532fa0e RR |
1276 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
1277 | ||
1278 | if (iwl_queue_space(&txq->q) > txq->q.low_mark && | |
1279 | txq_id >= 0 && priv->mac80211_registered && | |
1280 | agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) { | |
1281 | /* calculate mac80211 ampdu sw queue to wake */ | |
7f3e4bb6 | 1282 | ampdu_q = txq_id - IWL50_FIRST_AMPDU_QUEUE + |
e532fa0e RR |
1283 | priv->hw->queues; |
1284 | if (agg->state == IWL_AGG_OFF) | |
1285 | ieee80211_wake_queue(priv->hw, txq_id); | |
1286 | else | |
1287 | ieee80211_wake_queue(priv->hw, ampdu_q); | |
1288 | } | |
30e553e3 | 1289 | iwl_txq_check_empty(priv, sta_id, tid, txq_id); |
e532fa0e RR |
1290 | } |
1291 | } else { | |
4f85f5b3 RR |
1292 | info->status.retry_count = tx_resp->failure_frame; |
1293 | info->flags = | |
1294 | iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0; | |
e7d326ac | 1295 | iwl_hwrate_to_tx_control(priv, |
4f85f5b3 RR |
1296 | le32_to_cpu(tx_resp->rate_n_flags), |
1297 | info); | |
1298 | ||
1299 | IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags " | |
1300 | "0x%x retries %d\n", txq_id, | |
1301 | iwl_get_tx_fail_reason(status), | |
1302 | status, le32_to_cpu(tx_resp->rate_n_flags), | |
1303 | tx_resp->failure_frame); | |
1304 | ||
1305 | IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index); | |
1306 | if (index != -1) { | |
1307 | int freed = iwl_tx_queue_reclaim(priv, txq_id, index); | |
1308 | if (tid != MAX_TID_COUNT) | |
e532fa0e | 1309 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
4f85f5b3 | 1310 | if (iwl_queue_space(&txq->q) > txq->q.low_mark && |
e532fa0e RR |
1311 | (txq_id >= 0) && priv->mac80211_registered) |
1312 | ieee80211_wake_queue(priv->hw, txq_id); | |
4f85f5b3 | 1313 | if (tid != MAX_TID_COUNT) |
30e553e3 | 1314 | iwl_txq_check_empty(priv, sta_id, tid, txq_id); |
4f85f5b3 | 1315 | } |
e532fa0e | 1316 | } |
e532fa0e RR |
1317 | |
1318 | if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) | |
1319 | IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n"); | |
1320 | } | |
1321 | ||
c1adf9fb GG |
1322 | /* Currently 5000 is the supperset of everything */ |
1323 | static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) | |
1324 | { | |
1325 | return len; | |
1326 | } | |
1327 | ||
203566f3 EG |
1328 | static void iwl5000_setup_deferred_work(struct iwl_priv *priv) |
1329 | { | |
1330 | /* in 5000 the tx power calibration is done in uCode */ | |
1331 | priv->disable_tx_power_cal = 1; | |
1332 | } | |
1333 | ||
b600e4e1 RR |
1334 | static void iwl5000_rx_handler_setup(struct iwl_priv *priv) |
1335 | { | |
7c616cba TW |
1336 | /* init calibration handlers */ |
1337 | priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = | |
1338 | iwl5000_rx_calib_result; | |
1339 | priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = | |
1340 | iwl5000_rx_calib_complete; | |
e532fa0e | 1341 | priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx; |
b600e4e1 RR |
1342 | } |
1343 | ||
7c616cba | 1344 | |
87283cc1 RR |
1345 | static int iwl5000_hw_valid_rtc_data_addr(u32 addr) |
1346 | { | |
1347 | return (addr >= RTC_DATA_LOWER_BOUND) && | |
1348 | (addr < IWL50_RTC_DATA_UPPER_BOUND); | |
1349 | } | |
1350 | ||
fe7a90c2 RR |
1351 | static int iwl5000_send_rxon_assoc(struct iwl_priv *priv) |
1352 | { | |
1353 | int ret = 0; | |
1354 | struct iwl5000_rxon_assoc_cmd rxon_assoc; | |
1355 | const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; | |
1356 | const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; | |
1357 | ||
1358 | if ((rxon1->flags == rxon2->flags) && | |
1359 | (rxon1->filter_flags == rxon2->filter_flags) && | |
1360 | (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && | |
1361 | (rxon1->ofdm_ht_single_stream_basic_rates == | |
1362 | rxon2->ofdm_ht_single_stream_basic_rates) && | |
1363 | (rxon1->ofdm_ht_dual_stream_basic_rates == | |
1364 | rxon2->ofdm_ht_dual_stream_basic_rates) && | |
1365 | (rxon1->ofdm_ht_triple_stream_basic_rates == | |
1366 | rxon2->ofdm_ht_triple_stream_basic_rates) && | |
1367 | (rxon1->acquisition_data == rxon2->acquisition_data) && | |
1368 | (rxon1->rx_chain == rxon2->rx_chain) && | |
1369 | (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { | |
1370 | IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n"); | |
1371 | return 0; | |
1372 | } | |
1373 | ||
1374 | rxon_assoc.flags = priv->staging_rxon.flags; | |
1375 | rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; | |
1376 | rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; | |
1377 | rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; | |
1378 | rxon_assoc.reserved1 = 0; | |
1379 | rxon_assoc.reserved2 = 0; | |
1380 | rxon_assoc.reserved3 = 0; | |
1381 | rxon_assoc.ofdm_ht_single_stream_basic_rates = | |
1382 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates; | |
1383 | rxon_assoc.ofdm_ht_dual_stream_basic_rates = | |
1384 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; | |
1385 | rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; | |
1386 | rxon_assoc.ofdm_ht_triple_stream_basic_rates = | |
1387 | priv->staging_rxon.ofdm_ht_triple_stream_basic_rates; | |
1388 | rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data; | |
1389 | ||
1390 | ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, | |
1391 | sizeof(rxon_assoc), &rxon_assoc, NULL); | |
1392 | if (ret) | |
1393 | return ret; | |
1394 | ||
1395 | return ret; | |
1396 | } | |
630fe9b6 TW |
1397 | static int iwl5000_send_tx_power(struct iwl_priv *priv) |
1398 | { | |
1399 | struct iwl5000_tx_power_dbm_cmd tx_power_cmd; | |
1400 | ||
1401 | /* half dBm need to multiply */ | |
1402 | tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt); | |
853554ac | 1403 | tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED; |
630fe9b6 TW |
1404 | tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO; |
1405 | return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD, | |
1406 | sizeof(tx_power_cmd), &tx_power_cmd, | |
1407 | NULL); | |
1408 | } | |
1409 | ||
5225640b | 1410 | static void iwl5000_temperature(struct iwl_priv *priv) |
8f91aecb EG |
1411 | { |
1412 | /* store temperature from statistics (in Celsius) */ | |
5225640b | 1413 | priv->temperature = le32_to_cpu(priv->statistics.general.temperature); |
8f91aecb | 1414 | } |
fe7a90c2 | 1415 | |
caab8f1a TW |
1416 | /* Calc max signal level (dBm) among 3 possible receivers */ |
1417 | static int iwl5000_calc_rssi(struct iwl_priv *priv, | |
1418 | struct iwl_rx_phy_res *rx_resp) | |
1419 | { | |
1420 | /* data from PHY/DSP regarding signal strength, etc., | |
1421 | * contents are always there, not configurable by host | |
1422 | */ | |
1423 | struct iwl5000_non_cfg_phy *ncphy = | |
1424 | (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf; | |
1425 | u32 val, rssi_a, rssi_b, rssi_c, max_rssi; | |
1426 | u8 agc; | |
1427 | ||
1428 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]); | |
1429 | agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS; | |
1430 | ||
1431 | /* Find max rssi among 3 possible receivers. | |
1432 | * These values are measured by the digital signal processor (DSP). | |
1433 | * They should stay fairly constant even as the signal strength varies, | |
1434 | * if the radio's automatic gain control (AGC) is working right. | |
1435 | * AGC value (see below) will provide the "interesting" info. | |
1436 | */ | |
1437 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]); | |
1438 | rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS; | |
1439 | rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS; | |
1440 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]); | |
1441 | rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS; | |
1442 | ||
1443 | max_rssi = max_t(u32, rssi_a, rssi_b); | |
1444 | max_rssi = max_t(u32, max_rssi, rssi_c); | |
1445 | ||
1446 | IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", | |
1447 | rssi_a, rssi_b, rssi_c, max_rssi, agc); | |
1448 | ||
1449 | /* dBm = max_rssi dB - agc dB - constant. | |
1450 | * Higher AGC (higher radio gain) means lower signal. */ | |
1451 | return max_rssi - agc - IWL_RSSI_OFFSET; | |
1452 | } | |
1453 | ||
da8dec29 | 1454 | static struct iwl_hcmd_ops iwl5000_hcmd = { |
fe7a90c2 | 1455 | .rxon_assoc = iwl5000_send_rxon_assoc, |
da8dec29 TW |
1456 | }; |
1457 | ||
1458 | static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { | |
c1adf9fb | 1459 | .get_hcmd_size = iwl5000_get_hcmd_size, |
2469bf2e | 1460 | .build_addsta_hcmd = iwl5000_build_addsta_hcmd, |
33fd5033 EG |
1461 | .gain_computation = iwl5000_gain_computation, |
1462 | .chain_noise_reset = iwl5000_chain_noise_reset, | |
a326a5d0 | 1463 | .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, |
caab8f1a | 1464 | .calc_rssi = iwl5000_calc_rssi, |
da8dec29 TW |
1465 | }; |
1466 | ||
1467 | static struct iwl_lib_ops iwl5000_lib = { | |
fdd3e8a4 | 1468 | .set_hw_params = iwl5000_hw_set_hw_params, |
d4100dd9 RR |
1469 | .alloc_shared_mem = iwl5000_alloc_shared_mem, |
1470 | .free_shared_mem = iwl5000_free_shared_mem, | |
d67f5489 | 1471 | .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx, |
7839fc03 | 1472 | .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, |
972cf447 | 1473 | .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, |
da1bc453 | 1474 | .txq_set_sched = iwl5000_txq_set_sched, |
e26e47d9 TW |
1475 | .txq_agg_enable = iwl5000_txq_agg_enable, |
1476 | .txq_agg_disable = iwl5000_txq_agg_disable, | |
b600e4e1 | 1477 | .rx_handler_setup = iwl5000_rx_handler_setup, |
203566f3 | 1478 | .setup_deferred_work = iwl5000_setup_deferred_work, |
87283cc1 | 1479 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, |
dbb983b7 | 1480 | .load_ucode = iwl5000_load_ucode, |
99da1b48 RR |
1481 | .init_alive_start = iwl5000_init_alive_start, |
1482 | .alive_notify = iwl5000_alive_notify, | |
630fe9b6 | 1483 | .send_tx_power = iwl5000_send_tx_power, |
8f91aecb | 1484 | .temperature = iwl5000_temperature, |
ca579617 | 1485 | .update_chain_flags = iwl4965_update_chain_flags, |
30d59260 TW |
1486 | .apm_ops = { |
1487 | .init = iwl5000_apm_init, | |
7f066108 | 1488 | .reset = iwl5000_apm_reset, |
f118a91d | 1489 | .stop = iwl5000_apm_stop, |
5a835353 | 1490 | .config = iwl5000_nic_config, |
88acbd3b | 1491 | .set_pwr_src = iwl4965_set_pwr_src, |
30d59260 | 1492 | }, |
da8dec29 | 1493 | .eeprom_ops = { |
25ae3986 TW |
1494 | .regulatory_bands = { |
1495 | EEPROM_5000_REG_BAND_1_CHANNELS, | |
1496 | EEPROM_5000_REG_BAND_2_CHANNELS, | |
1497 | EEPROM_5000_REG_BAND_3_CHANNELS, | |
1498 | EEPROM_5000_REG_BAND_4_CHANNELS, | |
1499 | EEPROM_5000_REG_BAND_5_CHANNELS, | |
1500 | EEPROM_5000_REG_BAND_24_FAT_CHANNELS, | |
1501 | EEPROM_5000_REG_BAND_52_FAT_CHANNELS | |
1502 | }, | |
da8dec29 TW |
1503 | .verify_signature = iwlcore_eeprom_verify_signature, |
1504 | .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, | |
1505 | .release_semaphore = iwlcore_eeprom_release_semaphore, | |
f1f69415 | 1506 | .check_version = iwl5000_eeprom_check_version, |
25ae3986 | 1507 | .query_addr = iwl5000_eeprom_query_addr, |
da8dec29 TW |
1508 | }, |
1509 | }; | |
1510 | ||
1511 | static struct iwl_ops iwl5000_ops = { | |
1512 | .lib = &iwl5000_lib, | |
1513 | .hcmd = &iwl5000_hcmd, | |
1514 | .utils = &iwl5000_hcmd_utils, | |
1515 | }; | |
1516 | ||
5a6a256e TW |
1517 | static struct iwl_mod_params iwl50_mod_params = { |
1518 | .num_of_queues = IWL50_NUM_QUEUES, | |
9f17b318 | 1519 | .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, |
5a6a256e TW |
1520 | .enable_qos = 1, |
1521 | .amsdu_size_8K = 1, | |
3a1081e8 | 1522 | .restart_fw = 1, |
5a6a256e TW |
1523 | /* the rest are 0 by default */ |
1524 | }; | |
1525 | ||
1526 | ||
1527 | struct iwl_cfg iwl5300_agn_cfg = { | |
1528 | .name = "5300AGN", | |
1529 | .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", | |
1530 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, | |
da8dec29 | 1531 | .ops = &iwl5000_ops, |
25ae3986 | 1532 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
5a6a256e TW |
1533 | .mod_params = &iwl50_mod_params, |
1534 | }; | |
1535 | ||
47408639 EK |
1536 | struct iwl_cfg iwl5100_bg_cfg = { |
1537 | .name = "5100BG", | |
1538 | .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", | |
1539 | .sku = IWL_SKU_G, | |
1540 | .ops = &iwl5000_ops, | |
1541 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, | |
1542 | .mod_params = &iwl50_mod_params, | |
1543 | }; | |
1544 | ||
1545 | struct iwl_cfg iwl5100_abg_cfg = { | |
1546 | .name = "5100ABG", | |
1547 | .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", | |
1548 | .sku = IWL_SKU_A|IWL_SKU_G, | |
1549 | .ops = &iwl5000_ops, | |
1550 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, | |
1551 | .mod_params = &iwl50_mod_params, | |
1552 | }; | |
1553 | ||
5a6a256e TW |
1554 | struct iwl_cfg iwl5100_agn_cfg = { |
1555 | .name = "5100AGN", | |
1556 | .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", | |
1557 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, | |
da8dec29 | 1558 | .ops = &iwl5000_ops, |
25ae3986 | 1559 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
5a6a256e TW |
1560 | .mod_params = &iwl50_mod_params, |
1561 | }; | |
1562 | ||
1563 | struct iwl_cfg iwl5350_agn_cfg = { | |
1564 | .name = "5350AGN", | |
1565 | .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode", | |
1566 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, | |
da8dec29 | 1567 | .ops = &iwl5000_ops, |
25ae3986 | 1568 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
5a6a256e TW |
1569 | .mod_params = &iwl50_mod_params, |
1570 | }; | |
1571 | ||
c9f79ed2 TW |
1572 | MODULE_FIRMWARE("iwlwifi-5000" IWL5000_UCODE_API ".ucode"); |
1573 | ||
5a6a256e TW |
1574 | module_param_named(disable50, iwl50_mod_params.disable, int, 0444); |
1575 | MODULE_PARM_DESC(disable50, | |
1576 | "manually disable the 50XX radio (default 0 [radio on])"); | |
1577 | module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444); | |
1578 | MODULE_PARM_DESC(swcrypto50, | |
1579 | "using software crypto engine (default 0 [hardware])\n"); | |
1580 | module_param_named(debug50, iwl50_mod_params.debug, int, 0444); | |
1581 | MODULE_PARM_DESC(debug50, "50XX debug output mask"); | |
1582 | module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444); | |
1583 | MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); | |
1584 | module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444); | |
1585 | MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality"); | |
49779293 RR |
1586 | module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444); |
1587 | MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality"); | |
5a6a256e TW |
1588 | module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444); |
1589 | MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); | |
3a1081e8 EK |
1590 | module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444); |
1591 | MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); |