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5a6a256e TW |
1 | /****************************************************************************** |
2 | * | |
01f8162a | 3 | * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. |
5a6a256e TW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
23 | * | |
24 | *****************************************************************************/ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
5a6a256e TW |
28 | #include <linux/init.h> |
29 | #include <linux/pci.h> | |
30 | #include <linux/dma-mapping.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/skbuff.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/wireless.h> | |
35 | #include <net/mac80211.h> | |
36 | #include <linux/etherdevice.h> | |
37 | #include <asm/unaligned.h> | |
38 | ||
39 | #include "iwl-eeprom.h" | |
3e0d4cb1 | 40 | #include "iwl-dev.h" |
5a6a256e TW |
41 | #include "iwl-core.h" |
42 | #include "iwl-io.h" | |
e26e47d9 | 43 | #include "iwl-sta.h" |
5a6a256e | 44 | #include "iwl-helpers.h" |
e932a609 | 45 | #include "iwl-agn-led.h" |
5a6a256e | 46 | #include "iwl-5000-hw.h" |
c0bac76a | 47 | #include "iwl-6000-hw.h" |
5a6a256e | 48 | |
a0987a8d | 49 | /* Highest firmware API version supported */ |
c9d2fbf3 | 50 | #define IWL5000_UCODE_API_MAX 2 |
39e6d225 | 51 | #define IWL5150_UCODE_API_MAX 2 |
5a6a256e | 52 | |
a0987a8d RC |
53 | /* Lowest firmware API version supported */ |
54 | #define IWL5000_UCODE_API_MIN 1 | |
55 | #define IWL5150_UCODE_API_MIN 1 | |
56 | ||
57 | #define IWL5000_FW_PRE "iwlwifi-5000-" | |
58 | #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode" | |
59 | #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api) | |
60 | ||
61 | #define IWL5150_FW_PRE "iwlwifi-5150-" | |
62 | #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode" | |
63 | #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api) | |
4e062f99 | 64 | |
99da1b48 RR |
65 | static const u16 iwl5000_default_queue_to_tx_fifo[] = { |
66 | IWL_TX_FIFO_AC3, | |
67 | IWL_TX_FIFO_AC2, | |
68 | IWL_TX_FIFO_AC1, | |
69 | IWL_TX_FIFO_AC0, | |
70 | IWL50_CMD_FIFO_NUM, | |
71 | IWL_TX_FIFO_HCCA_1, | |
72 | IWL_TX_FIFO_HCCA_2 | |
73 | }; | |
74 | ||
672639de | 75 | int iwl5000_apm_init(struct iwl_priv *priv) |
30d59260 TW |
76 | { |
77 | int ret = 0; | |
78 | ||
79 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
80 | CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); | |
81 | ||
8f061891 TW |
82 | /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */ |
83 | iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS, | |
84 | CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); | |
85 | ||
a96a27f9 | 86 | /* Set FH wait threshold to maximum (HW error during stress W/A) */ |
4c43e0d0 TW |
87 | iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); |
88 | ||
89 | /* enable HAP INTA to move device L1a -> L0s */ | |
90 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
91 | CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); | |
92 | ||
050681b7 JS |
93 | if (priv->cfg->need_pll_cfg) |
94 | iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); | |
30d59260 TW |
95 | |
96 | /* set "initialization complete" bit to move adapter | |
97 | * D0U* --> D0A* state */ | |
98 | iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); | |
99 | ||
100 | /* wait for clock stabilization */ | |
1739d332 AK |
101 | ret = iwl_poll_bit(priv, CSR_GP_CNTRL, |
102 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, | |
73d7b5ac | 103 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); |
30d59260 | 104 | if (ret < 0) { |
e1623446 | 105 | IWL_DEBUG_INFO(priv, "Failed to init the card\n"); |
30d59260 TW |
106 | return ret; |
107 | } | |
108 | ||
30d59260 | 109 | /* enable DMA */ |
8f061891 | 110 | iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT); |
30d59260 TW |
111 | |
112 | udelay(20); | |
113 | ||
8f061891 | 114 | /* disable L1-Active */ |
30d59260 | 115 | iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG, |
8f061891 | 116 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); |
30d59260 | 117 | |
30d59260 TW |
118 | return ret; |
119 | } | |
120 | ||
9371d4ed | 121 | /* NIC configuration for 5000 series */ |
672639de | 122 | void iwl5000_nic_config(struct iwl_priv *priv) |
e86fe9f6 TW |
123 | { |
124 | unsigned long flags; | |
125 | u16 radio_cfg; | |
3fdb68de | 126 | u16 lctl; |
e86fe9f6 TW |
127 | |
128 | spin_lock_irqsave(&priv->lock, flags); | |
129 | ||
3fdb68de | 130 | lctl = iwl_pcie_link_ctl(priv); |
e86fe9f6 | 131 | |
3fdb68de TW |
132 | /* HW bug W/A */ |
133 | /* L1-ASPM is enabled by BIOS */ | |
134 | if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN) | |
135 | /* L1-APSM enabled: disable L0S */ | |
8f061891 TW |
136 | iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
137 | else | |
3fdb68de | 138 | /* L1-ASPM disabled: enable L0S */ |
8f061891 | 139 | iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); |
e86fe9f6 TW |
140 | |
141 | radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG); | |
142 | ||
143 | /* write radio config values to register */ | |
9371d4ed | 144 | if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX) |
e86fe9f6 TW |
145 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, |
146 | EEPROM_RF_CFG_TYPE_MSK(radio_cfg) | | |
147 | EEPROM_RF_CFG_STEP_MSK(radio_cfg) | | |
148 | EEPROM_RF_CFG_DASH_MSK(radio_cfg)); | |
149 | ||
150 | /* set CSR_HW_CONFIG_REG for uCode use */ | |
151 | iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, | |
152 | CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI | | |
153 | CSR_HW_IF_CONFIG_REG_BIT_MAC_SI); | |
154 | ||
4c43e0d0 TW |
155 | /* W/A : NIC is stuck in a reset state after Early PCIe power off |
156 | * (PCIe power is lost before PERST# is asserted), | |
157 | * causing ME FW to lose ownership and not being able to obtain it back. | |
158 | */ | |
2d3db679 | 159 | iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, |
4c43e0d0 TW |
160 | APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS, |
161 | ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS); | |
162 | ||
02c06e4a | 163 | |
e86fe9f6 TW |
164 | spin_unlock_irqrestore(&priv->lock, flags); |
165 | } | |
166 | ||
167 | ||
25ae3986 TW |
168 | /* |
169 | * EEPROM | |
170 | */ | |
171 | static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) | |
172 | { | |
173 | u16 offset = 0; | |
174 | ||
175 | if ((address & INDIRECT_ADDRESS) == 0) | |
176 | return address; | |
177 | ||
178 | switch (address & INDIRECT_TYPE_MSK) { | |
179 | case INDIRECT_HOST: | |
180 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST); | |
181 | break; | |
182 | case INDIRECT_GENERAL: | |
183 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL); | |
184 | break; | |
185 | case INDIRECT_REGULATORY: | |
186 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY); | |
187 | break; | |
188 | case INDIRECT_CALIBRATION: | |
189 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION); | |
190 | break; | |
191 | case INDIRECT_PROCESS_ADJST: | |
192 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST); | |
193 | break; | |
194 | case INDIRECT_OTHERS: | |
195 | offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS); | |
196 | break; | |
197 | default: | |
15b1687c | 198 | IWL_ERR(priv, "illegal indirect type: 0x%X\n", |
25ae3986 TW |
199 | address & INDIRECT_TYPE_MSK); |
200 | break; | |
201 | } | |
202 | ||
203 | /* translate the offset from words to byte */ | |
204 | return (address & ADDRESS_MSK) + (offset << 1); | |
205 | } | |
206 | ||
672639de | 207 | u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv) |
f1f69415 | 208 | { |
f1f69415 TW |
209 | struct iwl_eeprom_calib_hdr { |
210 | u8 version; | |
211 | u8 pa_type; | |
212 | u16 voltage; | |
213 | } *hdr; | |
214 | ||
f1f69415 TW |
215 | hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, |
216 | EEPROM_5000_CALIB_ALL); | |
0ef2ca67 | 217 | return hdr->version; |
f1f69415 TW |
218 | |
219 | } | |
220 | ||
33fd5033 EG |
221 | static void iwl5000_gain_computation(struct iwl_priv *priv, |
222 | u32 average_noise[NUM_RX_CHAINS], | |
223 | u16 min_average_noise_antenna_i, | |
d8c07e7a WYG |
224 | u32 min_average_noise, |
225 | u8 default_chain) | |
33fd5033 EG |
226 | { |
227 | int i; | |
228 | s32 delta_g; | |
229 | struct iwl_chain_noise_data *data = &priv->chain_noise_data; | |
230 | ||
d8c07e7a WYG |
231 | /* |
232 | * Find Gain Code for the chains based on "default chain" | |
233 | */ | |
234 | for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) { | |
33fd5033 EG |
235 | if ((data->disconn_array[i])) { |
236 | data->delta_gain_code[i] = 0; | |
237 | continue; | |
238 | } | |
239 | delta_g = (1000 * ((s32)average_noise[0] - | |
240 | (s32)average_noise[i])) / 1500; | |
241 | /* bound gain by 2 bits value max, 3rd bit is sign */ | |
242 | data->delta_gain_code[i] = | |
886e71de | 243 | min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE); |
33fd5033 EG |
244 | |
245 | if (delta_g < 0) | |
246 | /* set negative sign */ | |
247 | data->delta_gain_code[i] |= (1 << 2); | |
248 | } | |
249 | ||
e1623446 | 250 | IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n", |
33fd5033 EG |
251 | data->delta_gain_code[1], data->delta_gain_code[2]); |
252 | ||
253 | if (!data->radio_write) { | |
f69f42a6 | 254 | struct iwl_calib_chain_noise_gain_cmd cmd; |
0d950d84 | 255 | |
33fd5033 EG |
256 | memset(&cmd, 0, sizeof(cmd)); |
257 | ||
0d950d84 TW |
258 | cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD; |
259 | cmd.hdr.first_group = 0; | |
260 | cmd.hdr.groups_num = 1; | |
261 | cmd.hdr.data_valid = 1; | |
33fd5033 EG |
262 | cmd.delta_gain_1 = data->delta_gain_code[1]; |
263 | cmd.delta_gain_2 = data->delta_gain_code[2]; | |
264 | iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD, | |
265 | sizeof(cmd), &cmd, NULL); | |
266 | ||
267 | data->radio_write = 1; | |
268 | data->state = IWL_CHAIN_NOISE_CALIBRATED; | |
269 | } | |
270 | ||
271 | data->chain_noise_a = 0; | |
272 | data->chain_noise_b = 0; | |
273 | data->chain_noise_c = 0; | |
274 | data->chain_signal_a = 0; | |
275 | data->chain_signal_b = 0; | |
276 | data->chain_signal_c = 0; | |
277 | data->beacon_count = 0; | |
278 | } | |
279 | ||
280 | static void iwl5000_chain_noise_reset(struct iwl_priv *priv) | |
281 | { | |
282 | struct iwl_chain_noise_data *data = &priv->chain_noise_data; | |
0d950d84 | 283 | int ret; |
33fd5033 EG |
284 | |
285 | if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) { | |
f69f42a6 | 286 | struct iwl_calib_chain_noise_reset_cmd cmd; |
33fd5033 | 287 | memset(&cmd, 0, sizeof(cmd)); |
0d950d84 TW |
288 | |
289 | cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD; | |
290 | cmd.hdr.first_group = 0; | |
291 | cmd.hdr.groups_num = 1; | |
292 | cmd.hdr.data_valid = 1; | |
293 | ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD, | |
294 | sizeof(cmd), &cmd); | |
295 | if (ret) | |
15b1687c WT |
296 | IWL_ERR(priv, |
297 | "Could not send REPLY_PHY_CALIBRATION_CMD\n"); | |
33fd5033 | 298 | data->state = IWL_CHAIN_NOISE_ACCUMULATE; |
e1623446 | 299 | IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n"); |
33fd5033 EG |
300 | } |
301 | } | |
302 | ||
e8c00dcb | 303 | void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info, |
a326a5d0 EG |
304 | __le32 *tx_flags) |
305 | { | |
e6a9854b JB |
306 | if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || |
307 | (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) | |
a326a5d0 EG |
308 | *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK; |
309 | else | |
310 | *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK; | |
311 | } | |
312 | ||
33fd5033 EG |
313 | static struct iwl_sensitivity_ranges iwl5000_sensitivity = { |
314 | .min_nrg_cck = 95, | |
fe6efb4b | 315 | .max_nrg_cck = 0, /* not used, set to 0 */ |
33fd5033 EG |
316 | .auto_corr_min_ofdm = 90, |
317 | .auto_corr_min_ofdm_mrc = 170, | |
318 | .auto_corr_min_ofdm_x1 = 120, | |
319 | .auto_corr_min_ofdm_mrc_x1 = 240, | |
320 | ||
321 | .auto_corr_max_ofdm = 120, | |
322 | .auto_corr_max_ofdm_mrc = 210, | |
323 | .auto_corr_max_ofdm_x1 = 155, | |
324 | .auto_corr_max_ofdm_mrc_x1 = 290, | |
325 | ||
326 | .auto_corr_min_cck = 125, | |
327 | .auto_corr_max_cck = 200, | |
328 | .auto_corr_min_cck_mrc = 170, | |
329 | .auto_corr_max_cck_mrc = 400, | |
330 | .nrg_th_cck = 95, | |
331 | .nrg_th_ofdm = 95, | |
332 | }; | |
333 | ||
9d67187d WYG |
334 | static struct iwl_sensitivity_ranges iwl5150_sensitivity = { |
335 | .min_nrg_cck = 95, | |
336 | .max_nrg_cck = 0, /* not used, set to 0 */ | |
337 | .auto_corr_min_ofdm = 90, | |
338 | .auto_corr_min_ofdm_mrc = 170, | |
339 | .auto_corr_min_ofdm_x1 = 105, | |
340 | .auto_corr_min_ofdm_mrc_x1 = 220, | |
341 | ||
342 | .auto_corr_max_ofdm = 120, | |
343 | .auto_corr_max_ofdm_mrc = 210, | |
344 | /* max = min for performance bug in 5150 DSP */ | |
345 | .auto_corr_max_ofdm_x1 = 105, | |
346 | .auto_corr_max_ofdm_mrc_x1 = 220, | |
347 | ||
348 | .auto_corr_min_cck = 125, | |
349 | .auto_corr_max_cck = 200, | |
350 | .auto_corr_min_cck_mrc = 170, | |
351 | .auto_corr_max_cck_mrc = 400, | |
352 | .nrg_th_cck = 95, | |
353 | .nrg_th_ofdm = 95, | |
354 | }; | |
355 | ||
672639de | 356 | const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv, |
25ae3986 TW |
357 | size_t offset) |
358 | { | |
359 | u32 address = eeprom_indirect_address(priv, offset); | |
360 | BUG_ON(address >= priv->cfg->eeprom_size); | |
361 | return &priv->eeprom[address]; | |
362 | } | |
363 | ||
62161aef | 364 | static void iwl5150_set_ct_threshold(struct iwl_priv *priv) |
339afc89 | 365 | { |
62161aef | 366 | const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF; |
672639de | 367 | s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) - |
62161aef WYG |
368 | iwl_temp_calib_to_offset(priv); |
369 | ||
370 | priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef; | |
371 | } | |
372 | ||
373 | static void iwl5000_set_ct_threshold(struct iwl_priv *priv) | |
374 | { | |
375 | /* want Celsius */ | |
672639de | 376 | priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY; |
339afc89 TW |
377 | } |
378 | ||
7c616cba TW |
379 | /* |
380 | * Calibration | |
381 | */ | |
be5d56ed | 382 | static int iwl5000_set_Xtal_calib(struct iwl_priv *priv) |
7c616cba | 383 | { |
0d950d84 | 384 | struct iwl_calib_xtal_freq_cmd cmd; |
7c616cba TW |
385 | u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL); |
386 | ||
0d950d84 TW |
387 | cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD; |
388 | cmd.hdr.first_group = 0; | |
389 | cmd.hdr.groups_num = 1; | |
390 | cmd.hdr.data_valid = 1; | |
391 | cmd.cap_pin1 = (u8)xtal_calib[0]; | |
392 | cmd.cap_pin2 = (u8)xtal_calib[1]; | |
f69f42a6 | 393 | return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL], |
0d950d84 | 394 | (u8 *)&cmd, sizeof(cmd)); |
7c616cba TW |
395 | } |
396 | ||
7c616cba TW |
397 | static int iwl5000_send_calib_cfg(struct iwl_priv *priv) |
398 | { | |
f69f42a6 | 399 | struct iwl_calib_cfg_cmd calib_cfg_cmd; |
7c616cba TW |
400 | struct iwl_host_cmd cmd = { |
401 | .id = CALIBRATION_CFG_CMD, | |
f69f42a6 | 402 | .len = sizeof(struct iwl_calib_cfg_cmd), |
7c616cba TW |
403 | .data = &calib_cfg_cmd, |
404 | }; | |
405 | ||
406 | memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd)); | |
407 | calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL; | |
408 | calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL; | |
409 | calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL; | |
410 | calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL; | |
411 | ||
412 | return iwl_send_cmd(priv, &cmd); | |
413 | } | |
414 | ||
415 | static void iwl5000_rx_calib_result(struct iwl_priv *priv, | |
416 | struct iwl_rx_mem_buffer *rxb) | |
417 | { | |
418 | struct iwl_rx_packet *pkt = (void *)rxb->skb->data; | |
f69f42a6 | 419 | struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw; |
396887a2 | 420 | int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; |
6e21f2c1 | 421 | int index; |
7c616cba TW |
422 | |
423 | /* reduce the size of the length field itself */ | |
424 | len -= 4; | |
425 | ||
6e21f2c1 TW |
426 | /* Define the order in which the results will be sent to the runtime |
427 | * uCode. iwl_send_calib_results sends them in a row according to their | |
428 | * index. We sort them here */ | |
7c616cba | 429 | switch (hdr->op_code) { |
819500c5 TW |
430 | case IWL_PHY_CALIBRATE_DC_CMD: |
431 | index = IWL_CALIB_DC; | |
432 | break; | |
f69f42a6 TW |
433 | case IWL_PHY_CALIBRATE_LO_CMD: |
434 | index = IWL_CALIB_LO; | |
7c616cba | 435 | break; |
f69f42a6 TW |
436 | case IWL_PHY_CALIBRATE_TX_IQ_CMD: |
437 | index = IWL_CALIB_TX_IQ; | |
7c616cba | 438 | break; |
f69f42a6 TW |
439 | case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD: |
440 | index = IWL_CALIB_TX_IQ_PERD; | |
7c616cba | 441 | break; |
201706ac TW |
442 | case IWL_PHY_CALIBRATE_BASE_BAND_CMD: |
443 | index = IWL_CALIB_BASE_BAND; | |
444 | break; | |
7c616cba | 445 | default: |
15b1687c | 446 | IWL_ERR(priv, "Unknown calibration notification %d\n", |
7c616cba TW |
447 | hdr->op_code); |
448 | return; | |
449 | } | |
6e21f2c1 | 450 | iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len); |
7c616cba TW |
451 | } |
452 | ||
453 | static void iwl5000_rx_calib_complete(struct iwl_priv *priv, | |
454 | struct iwl_rx_mem_buffer *rxb) | |
455 | { | |
e1623446 | 456 | IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n"); |
7c616cba TW |
457 | queue_work(priv->workqueue, &priv->restart); |
458 | } | |
459 | ||
dbb983b7 RR |
460 | /* |
461 | * ucode | |
462 | */ | |
463 | static int iwl5000_load_section(struct iwl_priv *priv, | |
464 | struct fw_desc *image, | |
465 | u32 dst_addr) | |
466 | { | |
dbb983b7 RR |
467 | dma_addr_t phy_addr = image->p_addr; |
468 | u32 byte_cnt = image->len; | |
469 | ||
dbb983b7 RR |
470 | iwl_write_direct32(priv, |
471 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
472 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); | |
473 | ||
474 | iwl_write_direct32(priv, | |
475 | FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr); | |
476 | ||
477 | iwl_write_direct32(priv, | |
478 | FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), | |
479 | phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); | |
480 | ||
dbb983b7 | 481 | iwl_write_direct32(priv, |
f0b9f5cb | 482 | FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), |
499b1883 | 483 | (iwl_get_dma_hi_addr(phy_addr) |
f0b9f5cb TW |
484 | << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); |
485 | ||
dbb983b7 RR |
486 | iwl_write_direct32(priv, |
487 | FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), | |
488 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM | | |
489 | 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX | | |
490 | FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); | |
491 | ||
492 | iwl_write_direct32(priv, | |
493 | FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), | |
494 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
9c80c502 | 495 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | |
dbb983b7 RR |
496 | FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); |
497 | ||
dbb983b7 RR |
498 | return 0; |
499 | } | |
500 | ||
501 | static int iwl5000_load_given_ucode(struct iwl_priv *priv, | |
502 | struct fw_desc *inst_image, | |
503 | struct fw_desc *data_image) | |
504 | { | |
505 | int ret = 0; | |
506 | ||
250bdd21 SO |
507 | ret = iwl5000_load_section(priv, inst_image, |
508 | IWL50_RTC_INST_LOWER_BOUND); | |
dbb983b7 RR |
509 | if (ret) |
510 | return ret; | |
511 | ||
e1623446 | 512 | IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n"); |
dbb983b7 | 513 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, |
9c80c502 | 514 | priv->ucode_write_complete, 5 * HZ); |
dbb983b7 | 515 | if (ret == -ERESTARTSYS) { |
15b1687c | 516 | IWL_ERR(priv, "Could not load the INST uCode section due " |
dbb983b7 RR |
517 | "to interrupt\n"); |
518 | return ret; | |
519 | } | |
520 | if (!ret) { | |
15b1687c | 521 | IWL_ERR(priv, "Could not load the INST uCode section\n"); |
dbb983b7 RR |
522 | return -ETIMEDOUT; |
523 | } | |
524 | ||
525 | priv->ucode_write_complete = 0; | |
526 | ||
527 | ret = iwl5000_load_section( | |
250bdd21 | 528 | priv, data_image, IWL50_RTC_DATA_LOWER_BOUND); |
dbb983b7 RR |
529 | if (ret) |
530 | return ret; | |
531 | ||
e1623446 | 532 | IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n"); |
dbb983b7 RR |
533 | |
534 | ret = wait_event_interruptible_timeout(priv->wait_command_queue, | |
535 | priv->ucode_write_complete, 5 * HZ); | |
536 | if (ret == -ERESTARTSYS) { | |
15b1687c | 537 | IWL_ERR(priv, "Could not load the INST uCode section due " |
dbb983b7 RR |
538 | "to interrupt\n"); |
539 | return ret; | |
540 | } else if (!ret) { | |
15b1687c | 541 | IWL_ERR(priv, "Could not load the DATA uCode section\n"); |
dbb983b7 RR |
542 | return -ETIMEDOUT; |
543 | } else | |
544 | ret = 0; | |
545 | ||
546 | priv->ucode_write_complete = 0; | |
547 | ||
548 | return ret; | |
549 | } | |
550 | ||
672639de | 551 | int iwl5000_load_ucode(struct iwl_priv *priv) |
dbb983b7 RR |
552 | { |
553 | int ret = 0; | |
554 | ||
555 | /* check whether init ucode should be loaded, or rather runtime ucode */ | |
556 | if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) { | |
e1623446 | 557 | IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n"); |
dbb983b7 RR |
558 | ret = iwl5000_load_given_ucode(priv, |
559 | &priv->ucode_init, &priv->ucode_init_data); | |
560 | if (!ret) { | |
e1623446 | 561 | IWL_DEBUG_INFO(priv, "Init ucode load complete.\n"); |
dbb983b7 RR |
562 | priv->ucode_type = UCODE_INIT; |
563 | } | |
564 | } else { | |
e1623446 | 565 | IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. " |
dbb983b7 RR |
566 | "Loading runtime ucode...\n"); |
567 | ret = iwl5000_load_given_ucode(priv, | |
568 | &priv->ucode_code, &priv->ucode_data); | |
569 | if (!ret) { | |
e1623446 | 570 | IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n"); |
dbb983b7 RR |
571 | priv->ucode_type = UCODE_RT; |
572 | } | |
573 | } | |
574 | ||
575 | return ret; | |
576 | } | |
577 | ||
672639de | 578 | void iwl5000_init_alive_start(struct iwl_priv *priv) |
99da1b48 RR |
579 | { |
580 | int ret = 0; | |
581 | ||
582 | /* Check alive response for "valid" sign from uCode */ | |
583 | if (priv->card_alive_init.is_valid != UCODE_VALID_OK) { | |
584 | /* We had an error bringing up the hardware, so take it | |
585 | * all the way back down so we can try again */ | |
e1623446 | 586 | IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n"); |
99da1b48 RR |
587 | goto restart; |
588 | } | |
589 | ||
590 | /* initialize uCode was loaded... verify inst image. | |
591 | * This is a paranoid check, because we would not have gotten the | |
592 | * "initialize" alive if code weren't properly loaded. */ | |
593 | if (iwl_verify_ucode(priv)) { | |
594 | /* Runtime instruction load was bad; | |
595 | * take it all the way back down so we can try again */ | |
e1623446 | 596 | IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n"); |
99da1b48 RR |
597 | goto restart; |
598 | } | |
599 | ||
c587de0b | 600 | iwl_clear_stations_table(priv); |
99da1b48 RR |
601 | ret = priv->cfg->ops->lib->alive_notify(priv); |
602 | if (ret) { | |
39aadf8c WT |
603 | IWL_WARN(priv, |
604 | "Could not complete ALIVE transition: %d\n", ret); | |
99da1b48 RR |
605 | goto restart; |
606 | } | |
607 | ||
7c616cba | 608 | iwl5000_send_calib_cfg(priv); |
99da1b48 RR |
609 | return; |
610 | ||
611 | restart: | |
612 | /* real restart (first load init_ucode) */ | |
613 | queue_work(priv->workqueue, &priv->restart); | |
614 | } | |
615 | ||
616 | static void iwl5000_set_wr_ptrs(struct iwl_priv *priv, | |
617 | int txq_id, u32 index) | |
618 | { | |
619 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, | |
620 | (index & 0xff) | (txq_id << 8)); | |
621 | iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index); | |
622 | } | |
623 | ||
624 | static void iwl5000_tx_queue_set_status(struct iwl_priv *priv, | |
625 | struct iwl_tx_queue *txq, | |
626 | int tx_fifo_id, int scd_retry) | |
627 | { | |
628 | int txq_id = txq->q.id; | |
3fd07a1e | 629 | int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0; |
99da1b48 RR |
630 | |
631 | iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id), | |
632 | (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
633 | (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) | | |
634 | (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) | | |
635 | IWL50_SCD_QUEUE_STTS_REG_MSK); | |
636 | ||
637 | txq->sched_retry = scd_retry; | |
638 | ||
e1623446 | 639 | IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n", |
99da1b48 RR |
640 | active ? "Activate" : "Deactivate", |
641 | scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); | |
642 | } | |
643 | ||
9636e583 RR |
644 | static int iwl5000_send_wimax_coex(struct iwl_priv *priv) |
645 | { | |
646 | struct iwl_wimax_coex_cmd coex_cmd; | |
647 | ||
648 | memset(&coex_cmd, 0, sizeof(coex_cmd)); | |
649 | ||
650 | return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD, | |
651 | sizeof(coex_cmd), &coex_cmd); | |
652 | } | |
653 | ||
672639de | 654 | int iwl5000_alive_notify(struct iwl_priv *priv) |
99da1b48 RR |
655 | { |
656 | u32 a; | |
99da1b48 | 657 | unsigned long flags; |
31a73fe4 | 658 | int i, chan; |
40fc95d5 | 659 | u32 reg_val; |
99da1b48 RR |
660 | |
661 | spin_lock_irqsave(&priv->lock, flags); | |
662 | ||
99da1b48 RR |
663 | priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR); |
664 | a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET; | |
665 | for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET; | |
666 | a += 4) | |
667 | iwl_write_targ_mem(priv, a, 0); | |
668 | for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET; | |
669 | a += 4) | |
670 | iwl_write_targ_mem(priv, a, 0); | |
39d5e0ce HW |
671 | for (; a < priv->scd_base_addr + |
672 | IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4) | |
99da1b48 RR |
673 | iwl_write_targ_mem(priv, a, 0); |
674 | ||
675 | iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR, | |
4ddbb7d0 | 676 | priv->scd_bc_tbls.dma >> 10); |
31a73fe4 WT |
677 | |
678 | /* Enable DMA channel */ | |
679 | for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++) | |
680 | iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
681 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
682 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
683 | ||
40fc95d5 WT |
684 | /* Update FH chicken bits */ |
685 | reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG); | |
686 | iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG, | |
687 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
688 | ||
99da1b48 | 689 | iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, |
4ddbb7d0 | 690 | IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num)); |
99da1b48 RR |
691 | iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0); |
692 | ||
693 | /* initiate the queues */ | |
694 | for (i = 0; i < priv->hw_params.max_txq_num; i++) { | |
695 | iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0); | |
696 | iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); | |
697 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
698 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0); | |
699 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
700 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) + | |
701 | sizeof(u32), | |
702 | ((SCD_WIN_SIZE << | |
703 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
704 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
705 | ((SCD_FRAME_LIMIT << | |
706 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
707 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
708 | } | |
709 | ||
710 | iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK, | |
da1bc453 | 711 | IWL_MASK(0, priv->hw_params.max_txq_num)); |
99da1b48 | 712 | |
da1bc453 TW |
713 | /* Activate all Tx DMA/FIFO channels */ |
714 | priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7)); | |
99da1b48 RR |
715 | |
716 | iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); | |
9c80c502 | 717 | |
99da1b48 RR |
718 | /* map qos queues to fifos one-to-one */ |
719 | for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) { | |
720 | int ac = iwl5000_default_queue_to_tx_fifo[i]; | |
721 | iwl_txq_ctx_activate(priv, i); | |
722 | iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0); | |
723 | } | |
724 | /* TODO - need to initialize those FIFOs inside the loop above, | |
725 | * not only mark them as active */ | |
726 | iwl_txq_ctx_activate(priv, 4); | |
727 | iwl_txq_ctx_activate(priv, 7); | |
728 | iwl_txq_ctx_activate(priv, 8); | |
729 | iwl_txq_ctx_activate(priv, 9); | |
730 | ||
99da1b48 RR |
731 | spin_unlock_irqrestore(&priv->lock, flags); |
732 | ||
7c616cba | 733 | |
9636e583 RR |
734 | iwl5000_send_wimax_coex(priv); |
735 | ||
be5d56ed TW |
736 | iwl5000_set_Xtal_calib(priv); |
737 | iwl_send_calib_results(priv); | |
7c616cba | 738 | |
99da1b48 RR |
739 | return 0; |
740 | } | |
741 | ||
672639de | 742 | int iwl5000_hw_set_hw_params(struct iwl_priv *priv) |
fdd3e8a4 TW |
743 | { |
744 | if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) || | |
745 | (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) { | |
15b1687c WT |
746 | IWL_ERR(priv, |
747 | "invalid queues_num, should be between %d and %d\n", | |
748 | IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES); | |
fdd3e8a4 TW |
749 | return -EINVAL; |
750 | } | |
25ae3986 | 751 | |
fdd3e8a4 | 752 | priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues; |
f3f911d1 | 753 | priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM; |
4ddbb7d0 TW |
754 | priv->hw_params.scd_bc_tbls_size = |
755 | IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl); | |
a8e74e27 | 756 | priv->hw_params.tfd_size = sizeof(struct iwl_tfd); |
fdd3e8a4 TW |
757 | priv->hw_params.max_stations = IWL5000_STATION_COUNT; |
758 | priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID; | |
c0bac76a | 759 | |
f3a2a424 WYG |
760 | priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE; |
761 | priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE; | |
c0bac76a | 762 | |
da154e30 | 763 | priv->hw_params.max_bsm_size = 0; |
7aafef1c | 764 | priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) | |
fdd3e8a4 | 765 | BIT(IEEE80211_BAND_5GHZ); |
141c43a3 WT |
766 | priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR; |
767 | ||
c0bac76a JS |
768 | priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant); |
769 | priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant); | |
770 | priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant; | |
771 | priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant; | |
c031bf80 | 772 | |
62161aef WYG |
773 | if (priv->cfg->ops->lib->temp_ops.set_ct_kill) |
774 | priv->cfg->ops->lib->temp_ops.set_ct_kill(priv); | |
c031bf80 | 775 | |
9d67187d | 776 | /* Set initial sensitivity parameters */ |
be5d56ed TW |
777 | /* Set initial calibration set */ |
778 | switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) { | |
c0bac76a | 779 | case CSR_HW_REV_TYPE_5150: |
9d67187d | 780 | priv->hw_params.sens = &iwl5150_sensitivity; |
be5d56ed | 781 | priv->hw_params.calib_init_cfg = |
c0bac76a | 782 | BIT(IWL_CALIB_DC) | |
f69f42a6 | 783 | BIT(IWL_CALIB_LO) | |
201706ac | 784 | BIT(IWL_CALIB_TX_IQ) | |
201706ac | 785 | BIT(IWL_CALIB_BASE_BAND); |
c0bac76a | 786 | |
be5d56ed | 787 | break; |
c0bac76a | 788 | default: |
9d67187d | 789 | priv->hw_params.sens = &iwl5000_sensitivity; |
819500c5 | 790 | priv->hw_params.calib_init_cfg = |
c0bac76a | 791 | BIT(IWL_CALIB_XTAL) | |
7470d7f5 WT |
792 | BIT(IWL_CALIB_LO) | |
793 | BIT(IWL_CALIB_TX_IQ) | | |
c0bac76a | 794 | BIT(IWL_CALIB_TX_IQ_PERD) | |
7470d7f5 | 795 | BIT(IWL_CALIB_BASE_BAND); |
be5d56ed TW |
796 | break; |
797 | } | |
798 | ||
fdd3e8a4 TW |
799 | return 0; |
800 | } | |
d4100dd9 | 801 | |
7839fc03 EG |
802 | /** |
803 | * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
804 | */ | |
672639de | 805 | void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv, |
16466903 | 806 | struct iwl_tx_queue *txq, |
7839fc03 EG |
807 | u16 byte_cnt) |
808 | { | |
4ddbb7d0 | 809 | struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; |
127901ab | 810 | int write_ptr = txq->q.write_ptr; |
7839fc03 EG |
811 | int txq_id = txq->q.id; |
812 | u8 sec_ctl = 0; | |
127901ab TW |
813 | u8 sta_id = 0; |
814 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
815 | __le16 bc_ent; | |
7839fc03 | 816 | |
127901ab | 817 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
7839fc03 EG |
818 | |
819 | if (txq_id != IWL_CMD_QUEUE_NUM) { | |
127901ab | 820 | sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id; |
da99c4b6 | 821 | sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl; |
7839fc03 EG |
822 | |
823 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
824 | case TX_CMD_SEC_CCM: | |
825 | len += CCMP_MIC_LEN; | |
826 | break; | |
827 | case TX_CMD_SEC_TKIP: | |
828 | len += TKIP_ICV_LEN; | |
829 | break; | |
830 | case TX_CMD_SEC_WEP: | |
831 | len += WEP_IV_LEN + WEP_ICV_LEN; | |
832 | break; | |
833 | } | |
834 | } | |
835 | ||
127901ab | 836 | bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12)); |
7839fc03 | 837 | |
4ddbb7d0 | 838 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; |
7839fc03 | 839 | |
127901ab | 840 | if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) |
4ddbb7d0 | 841 | scd_bc_tbl[txq_id]. |
127901ab | 842 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; |
7839fc03 EG |
843 | } |
844 | ||
672639de | 845 | void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv, |
972cf447 TW |
846 | struct iwl_tx_queue *txq) |
847 | { | |
4ddbb7d0 | 848 | struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr; |
127901ab TW |
849 | int txq_id = txq->q.id; |
850 | int read_ptr = txq->q.read_ptr; | |
851 | u8 sta_id = 0; | |
852 | __le16 bc_ent; | |
853 | ||
854 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
972cf447 TW |
855 | |
856 | if (txq_id != IWL_CMD_QUEUE_NUM) | |
127901ab | 857 | sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id; |
972cf447 | 858 | |
127901ab | 859 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); |
4ddbb7d0 | 860 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; |
972cf447 | 861 | |
127901ab | 862 | if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP) |
4ddbb7d0 | 863 | scd_bc_tbl[txq_id]. |
127901ab | 864 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; |
972cf447 TW |
865 | } |
866 | ||
e26e47d9 TW |
867 | static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid, |
868 | u16 txq_id) | |
869 | { | |
870 | u32 tbl_dw_addr; | |
871 | u32 tbl_dw; | |
872 | u16 scd_q2ratid; | |
873 | ||
874 | scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
875 | ||
876 | tbl_dw_addr = priv->scd_base_addr + | |
877 | IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); | |
878 | ||
879 | tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr); | |
880 | ||
881 | if (txq_id & 0x1) | |
882 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
883 | else | |
884 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
885 | ||
886 | iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw); | |
887 | ||
888 | return 0; | |
889 | } | |
890 | static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) | |
891 | { | |
892 | /* Simply stop the queue, but don't change any configuration; | |
893 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
894 | iwl_write_prph(priv, | |
895 | IWL50_SCD_QUEUE_STATUS_BITS(txq_id), | |
896 | (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
897 | (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
898 | } | |
899 | ||
672639de | 900 | int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id, |
e26e47d9 TW |
901 | int tx_fifo, int sta_id, int tid, u16 ssn_idx) |
902 | { | |
903 | unsigned long flags; | |
e26e47d9 TW |
904 | u16 ra_tid; |
905 | ||
9f17b318 TW |
906 | if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || |
907 | (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { | |
39aadf8c WT |
908 | IWL_WARN(priv, |
909 | "queue number out of range: %d, must be %d to %d\n", | |
9f17b318 TW |
910 | txq_id, IWL50_FIRST_AMPDU_QUEUE, |
911 | IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); | |
912 | return -EINVAL; | |
913 | } | |
e26e47d9 TW |
914 | |
915 | ra_tid = BUILD_RAxTID(sta_id, tid); | |
916 | ||
917 | /* Modify device's station table to Tx this TID */ | |
9f58671e | 918 | iwl_sta_tx_modify_enable_tid(priv, sta_id, tid); |
e26e47d9 TW |
919 | |
920 | spin_lock_irqsave(&priv->lock, flags); | |
e26e47d9 TW |
921 | |
922 | /* Stop this Tx queue before configuring it */ | |
923 | iwl5000_tx_queue_stop_scheduler(priv, txq_id); | |
924 | ||
925 | /* Map receiver-address / traffic-ID to this queue */ | |
926 | iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id); | |
927 | ||
928 | /* Set this queue as a chain-building queue */ | |
929 | iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id)); | |
930 | ||
931 | /* enable aggregations for the queue */ | |
932 | iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id)); | |
933 | ||
934 | /* Place first TFD at index corresponding to start sequence number. | |
935 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
936 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
937 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
938 | iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); | |
939 | ||
940 | /* Set up Tx window size and frame limit for this queue */ | |
941 | iwl_write_targ_mem(priv, priv->scd_base_addr + | |
942 | IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + | |
943 | sizeof(u32), | |
944 | ((SCD_WIN_SIZE << | |
945 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
946 | IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
947 | ((SCD_FRAME_LIMIT << | |
948 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
949 | IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
950 | ||
951 | iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); | |
952 | ||
953 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ | |
954 | iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); | |
955 | ||
e26e47d9 TW |
956 | spin_unlock_irqrestore(&priv->lock, flags); |
957 | ||
958 | return 0; | |
959 | } | |
960 | ||
672639de | 961 | int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id, |
e26e47d9 TW |
962 | u16 ssn_idx, u8 tx_fifo) |
963 | { | |
9f17b318 TW |
964 | if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) || |
965 | (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) { | |
a2f1cbeb | 966 | IWL_ERR(priv, |
39aadf8c | 967 | "queue number out of range: %d, must be %d to %d\n", |
9f17b318 TW |
968 | txq_id, IWL50_FIRST_AMPDU_QUEUE, |
969 | IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1); | |
e26e47d9 TW |
970 | return -EINVAL; |
971 | } | |
972 | ||
e26e47d9 TW |
973 | iwl5000_tx_queue_stop_scheduler(priv, txq_id); |
974 | ||
975 | iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id)); | |
976 | ||
977 | priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); | |
978 | priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); | |
979 | /* supposes that ssn_idx is valid (!= 0xFFF) */ | |
980 | iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx); | |
981 | ||
982 | iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id)); | |
983 | iwl_txq_ctx_deactivate(priv, txq_id); | |
984 | iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); | |
985 | ||
e26e47d9 TW |
986 | return 0; |
987 | } | |
988 | ||
e8c00dcb | 989 | u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) |
2469bf2e TW |
990 | { |
991 | u16 size = (u16)sizeof(struct iwl_addsta_cmd); | |
c587de0b TW |
992 | struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data; |
993 | memcpy(addsta, cmd, size); | |
994 | /* resrved in 5000 */ | |
995 | addsta->rate_n_flags = cpu_to_le16(0); | |
2469bf2e TW |
996 | return size; |
997 | } | |
998 | ||
999 | ||
da1bc453 | 1000 | /* |
a96a27f9 | 1001 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask |
da1bc453 TW |
1002 | * must be called under priv->lock and mac access |
1003 | */ | |
672639de | 1004 | void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask) |
5a676bbe | 1005 | { |
da1bc453 | 1006 | iwl_write_prph(priv, IWL50_SCD_TXFACT, mask); |
5a676bbe RR |
1007 | } |
1008 | ||
e532fa0e RR |
1009 | |
1010 | static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) | |
1011 | { | |
3ac7f146 | 1012 | return le32_to_cpup((__le32 *)&tx_resp->status + |
25a6572c | 1013 | tx_resp->frame_count) & MAX_SN; |
e532fa0e RR |
1014 | } |
1015 | ||
1016 | static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv, | |
1017 | struct iwl_ht_agg *agg, | |
1018 | struct iwl5000_tx_resp *tx_resp, | |
25a6572c | 1019 | int txq_id, u16 start_idx) |
e532fa0e RR |
1020 | { |
1021 | u16 status; | |
1022 | struct agg_tx_status *frame_status = &tx_resp->status; | |
1023 | struct ieee80211_tx_info *info = NULL; | |
1024 | struct ieee80211_hdr *hdr = NULL; | |
e7d326ac | 1025 | u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); |
25a6572c | 1026 | int i, sh, idx; |
e532fa0e RR |
1027 | u16 seq; |
1028 | ||
1029 | if (agg->wait_for_ba) | |
e1623446 | 1030 | IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n"); |
e532fa0e RR |
1031 | |
1032 | agg->frame_count = tx_resp->frame_count; | |
1033 | agg->start_idx = start_idx; | |
e7d326ac | 1034 | agg->rate_n_flags = rate_n_flags; |
e532fa0e RR |
1035 | agg->bitmap = 0; |
1036 | ||
1037 | /* # frames attempted by Tx command */ | |
1038 | if (agg->frame_count == 1) { | |
1039 | /* Only one frame was attempted; no block-ack will arrive */ | |
1040 | status = le16_to_cpu(frame_status[0].status); | |
25a6572c | 1041 | idx = start_idx; |
e532fa0e RR |
1042 | |
1043 | /* FIXME: code repetition */ | |
e1623446 | 1044 | IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n", |
e532fa0e RR |
1045 | agg->frame_count, agg->start_idx, idx); |
1046 | ||
1047 | info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]); | |
e6a9854b | 1048 | info->status.rates[0].count = tx_resp->failure_frame + 1; |
e532fa0e | 1049 | info->flags &= ~IEEE80211_TX_CTL_AMPDU; |
c3056065 | 1050 | info->flags |= iwl_is_tx_success(status) ? |
3fd07a1e | 1051 | IEEE80211_TX_STAT_ACK : 0; |
e7d326ac TW |
1052 | iwl_hwrate_to_tx_control(priv, rate_n_flags, info); |
1053 | ||
e532fa0e RR |
1054 | /* FIXME: code repetition end */ |
1055 | ||
e1623446 | 1056 | IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n", |
e532fa0e | 1057 | status & 0xff, tx_resp->failure_frame); |
e1623446 | 1058 | IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags); |
e532fa0e RR |
1059 | |
1060 | agg->wait_for_ba = 0; | |
1061 | } else { | |
1062 | /* Two or more frames were attempted; expect block-ack */ | |
1063 | u64 bitmap = 0; | |
1064 | int start = agg->start_idx; | |
1065 | ||
1066 | /* Construct bit-map of pending frames within Tx window */ | |
1067 | for (i = 0; i < agg->frame_count; i++) { | |
1068 | u16 sc; | |
1069 | status = le16_to_cpu(frame_status[i].status); | |
1070 | seq = le16_to_cpu(frame_status[i].sequence); | |
1071 | idx = SEQ_TO_INDEX(seq); | |
1072 | txq_id = SEQ_TO_QUEUE(seq); | |
1073 | ||
1074 | if (status & (AGG_TX_STATE_FEW_BYTES_MSK | | |
1075 | AGG_TX_STATE_ABORT_MSK)) | |
1076 | continue; | |
1077 | ||
e1623446 | 1078 | IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n", |
e532fa0e RR |
1079 | agg->frame_count, txq_id, idx); |
1080 | ||
1081 | hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); | |
6c6a22e2 SG |
1082 | if (!hdr) { |
1083 | IWL_ERR(priv, | |
1084 | "BUG_ON idx doesn't point to valid skb" | |
1085 | " idx=%d, txq_id=%d\n", idx, txq_id); | |
1086 | return -1; | |
1087 | } | |
e532fa0e RR |
1088 | |
1089 | sc = le16_to_cpu(hdr->seq_ctrl); | |
1090 | if (idx != (SEQ_TO_SN(sc) & 0xff)) { | |
15b1687c WT |
1091 | IWL_ERR(priv, |
1092 | "BUG_ON idx doesn't match seq control" | |
1093 | " idx=%d, seq_idx=%d, seq=%d\n", | |
e532fa0e RR |
1094 | idx, SEQ_TO_SN(sc), |
1095 | hdr->seq_ctrl); | |
1096 | return -1; | |
1097 | } | |
1098 | ||
e1623446 | 1099 | IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n", |
e532fa0e RR |
1100 | i, idx, SEQ_TO_SN(sc)); |
1101 | ||
1102 | sh = idx - start; | |
1103 | if (sh > 64) { | |
1104 | sh = (start - idx) + 0xff; | |
1105 | bitmap = bitmap << sh; | |
1106 | sh = 0; | |
1107 | start = idx; | |
1108 | } else if (sh < -64) | |
1109 | sh = 0xff - (start - idx); | |
1110 | else if (sh < 0) { | |
1111 | sh = start - idx; | |
1112 | start = idx; | |
1113 | bitmap = bitmap << sh; | |
1114 | sh = 0; | |
1115 | } | |
4aa41f12 | 1116 | bitmap |= 1ULL << sh; |
e1623446 | 1117 | IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n", |
4aa41f12 | 1118 | start, (unsigned long long)bitmap); |
e532fa0e RR |
1119 | } |
1120 | ||
1121 | agg->bitmap = bitmap; | |
1122 | agg->start_idx = start; | |
e1623446 | 1123 | IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n", |
e532fa0e RR |
1124 | agg->frame_count, agg->start_idx, |
1125 | (unsigned long long)agg->bitmap); | |
1126 | ||
1127 | if (bitmap) | |
1128 | agg->wait_for_ba = 1; | |
1129 | } | |
1130 | return 0; | |
1131 | } | |
1132 | ||
1133 | static void iwl5000_rx_reply_tx(struct iwl_priv *priv, | |
1134 | struct iwl_rx_mem_buffer *rxb) | |
1135 | { | |
1136 | struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data; | |
1137 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); | |
1138 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1139 | int index = SEQ_TO_INDEX(sequence); | |
1140 | struct iwl_tx_queue *txq = &priv->txq[txq_id]; | |
1141 | struct ieee80211_tx_info *info; | |
1142 | struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; | |
1143 | u32 status = le16_to_cpu(tx_resp->status.status); | |
3fd07a1e TW |
1144 | int tid; |
1145 | int sta_id; | |
1146 | int freed; | |
e532fa0e RR |
1147 | |
1148 | if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { | |
15b1687c | 1149 | IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d " |
e532fa0e RR |
1150 | "is out of range [0-%d] %d %d\n", txq_id, |
1151 | index, txq->q.n_bd, txq->q.write_ptr, | |
1152 | txq->q.read_ptr); | |
1153 | return; | |
1154 | } | |
1155 | ||
1156 | info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]); | |
1157 | memset(&info->status, 0, sizeof(info->status)); | |
1158 | ||
3fd07a1e TW |
1159 | tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS; |
1160 | sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS; | |
e532fa0e RR |
1161 | |
1162 | if (txq->sched_retry) { | |
1163 | const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp); | |
1164 | struct iwl_ht_agg *agg = NULL; | |
1165 | ||
e532fa0e RR |
1166 | agg = &priv->stations[sta_id].tid[tid].agg; |
1167 | ||
25a6572c | 1168 | iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); |
e532fa0e | 1169 | |
3235427e RR |
1170 | /* check if BAR is needed */ |
1171 | if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) | |
1172 | info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; | |
e532fa0e RR |
1173 | |
1174 | if (txq->q.read_ptr != (scd_ssn & 0xff)) { | |
e532fa0e | 1175 | index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); |
e1623446 | 1176 | IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim " |
3fd07a1e TW |
1177 | "scd_ssn=%d idx=%d txq=%d swq=%d\n", |
1178 | scd_ssn , index, txq_id, txq->swq_id); | |
1179 | ||
17b88929 | 1180 | freed = iwl_tx_queue_reclaim(priv, txq_id, index); |
e532fa0e RR |
1181 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
1182 | ||
3fd07a1e TW |
1183 | if (priv->mac80211_registered && |
1184 | (iwl_queue_space(&txq->q) > txq->q.low_mark) && | |
1185 | (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) { | |
e532fa0e | 1186 | if (agg->state == IWL_AGG_OFF) |
e4e72fb4 | 1187 | iwl_wake_queue(priv, txq_id); |
e532fa0e | 1188 | else |
e4e72fb4 | 1189 | iwl_wake_queue(priv, txq->swq_id); |
e532fa0e | 1190 | } |
e532fa0e RR |
1191 | } |
1192 | } else { | |
3fd07a1e TW |
1193 | BUG_ON(txq_id != txq->swq_id); |
1194 | ||
e6a9854b | 1195 | info->status.rates[0].count = tx_resp->failure_frame + 1; |
3fd07a1e TW |
1196 | info->flags |= iwl_is_tx_success(status) ? |
1197 | IEEE80211_TX_STAT_ACK : 0; | |
e7d326ac | 1198 | iwl_hwrate_to_tx_control(priv, |
4f85f5b3 RR |
1199 | le32_to_cpu(tx_resp->rate_n_flags), |
1200 | info); | |
1201 | ||
e1623446 | 1202 | IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags " |
3fd07a1e TW |
1203 | "0x%x retries %d\n", |
1204 | txq_id, | |
1205 | iwl_get_tx_fail_reason(status), status, | |
1206 | le32_to_cpu(tx_resp->rate_n_flags), | |
1207 | tx_resp->failure_frame); | |
4f85f5b3 | 1208 | |
3fd07a1e TW |
1209 | freed = iwl_tx_queue_reclaim(priv, txq_id, index); |
1210 | if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) | |
e532fa0e | 1211 | priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; |
3fd07a1e TW |
1212 | |
1213 | if (priv->mac80211_registered && | |
1214 | (iwl_queue_space(&txq->q) > txq->q.low_mark)) | |
e4e72fb4 | 1215 | iwl_wake_queue(priv, txq_id); |
e532fa0e | 1216 | } |
e532fa0e | 1217 | |
3fd07a1e TW |
1218 | if (ieee80211_is_data_qos(tx_resp->frame_ctrl)) |
1219 | iwl_txq_check_empty(priv, sta_id, tid, txq_id); | |
1220 | ||
e532fa0e | 1221 | if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) |
15b1687c | 1222 | IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n"); |
e532fa0e RR |
1223 | } |
1224 | ||
a96a27f9 | 1225 | /* Currently 5000 is the superset of everything */ |
e8c00dcb | 1226 | u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len) |
c1adf9fb GG |
1227 | { |
1228 | return len; | |
1229 | } | |
1230 | ||
672639de | 1231 | void iwl5000_setup_deferred_work(struct iwl_priv *priv) |
203566f3 EG |
1232 | { |
1233 | /* in 5000 the tx power calibration is done in uCode */ | |
1234 | priv->disable_tx_power_cal = 1; | |
1235 | } | |
1236 | ||
672639de | 1237 | void iwl5000_rx_handler_setup(struct iwl_priv *priv) |
b600e4e1 | 1238 | { |
7c616cba TW |
1239 | /* init calibration handlers */ |
1240 | priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = | |
1241 | iwl5000_rx_calib_result; | |
1242 | priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = | |
1243 | iwl5000_rx_calib_complete; | |
e532fa0e | 1244 | priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx; |
b600e4e1 RR |
1245 | } |
1246 | ||
7c616cba | 1247 | |
672639de | 1248 | int iwl5000_hw_valid_rtc_data_addr(u32 addr) |
87283cc1 | 1249 | { |
250bdd21 | 1250 | return (addr >= IWL50_RTC_DATA_LOWER_BOUND) && |
87283cc1 RR |
1251 | (addr < IWL50_RTC_DATA_UPPER_BOUND); |
1252 | } | |
1253 | ||
fe7a90c2 RR |
1254 | static int iwl5000_send_rxon_assoc(struct iwl_priv *priv) |
1255 | { | |
1256 | int ret = 0; | |
1257 | struct iwl5000_rxon_assoc_cmd rxon_assoc; | |
1258 | const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; | |
1259 | const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; | |
1260 | ||
1261 | if ((rxon1->flags == rxon2->flags) && | |
1262 | (rxon1->filter_flags == rxon2->filter_flags) && | |
1263 | (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && | |
1264 | (rxon1->ofdm_ht_single_stream_basic_rates == | |
1265 | rxon2->ofdm_ht_single_stream_basic_rates) && | |
1266 | (rxon1->ofdm_ht_dual_stream_basic_rates == | |
1267 | rxon2->ofdm_ht_dual_stream_basic_rates) && | |
1268 | (rxon1->ofdm_ht_triple_stream_basic_rates == | |
1269 | rxon2->ofdm_ht_triple_stream_basic_rates) && | |
1270 | (rxon1->acquisition_data == rxon2->acquisition_data) && | |
1271 | (rxon1->rx_chain == rxon2->rx_chain) && | |
1272 | (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { | |
e1623446 | 1273 | IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n"); |
fe7a90c2 RR |
1274 | return 0; |
1275 | } | |
1276 | ||
1277 | rxon_assoc.flags = priv->staging_rxon.flags; | |
1278 | rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; | |
1279 | rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; | |
1280 | rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; | |
1281 | rxon_assoc.reserved1 = 0; | |
1282 | rxon_assoc.reserved2 = 0; | |
1283 | rxon_assoc.reserved3 = 0; | |
1284 | rxon_assoc.ofdm_ht_single_stream_basic_rates = | |
1285 | priv->staging_rxon.ofdm_ht_single_stream_basic_rates; | |
1286 | rxon_assoc.ofdm_ht_dual_stream_basic_rates = | |
1287 | priv->staging_rxon.ofdm_ht_dual_stream_basic_rates; | |
1288 | rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain; | |
1289 | rxon_assoc.ofdm_ht_triple_stream_basic_rates = | |
1290 | priv->staging_rxon.ofdm_ht_triple_stream_basic_rates; | |
1291 | rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data; | |
1292 | ||
1293 | ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC, | |
1294 | sizeof(rxon_assoc), &rxon_assoc, NULL); | |
1295 | if (ret) | |
1296 | return ret; | |
1297 | ||
1298 | return ret; | |
1299 | } | |
672639de | 1300 | int iwl5000_send_tx_power(struct iwl_priv *priv) |
630fe9b6 TW |
1301 | { |
1302 | struct iwl5000_tx_power_dbm_cmd tx_power_cmd; | |
76a2407a | 1303 | u8 tx_ant_cfg_cmd; |
630fe9b6 TW |
1304 | |
1305 | /* half dBm need to multiply */ | |
1306 | tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt); | |
853554ac | 1307 | tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED; |
630fe9b6 | 1308 | tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO; |
76a2407a JS |
1309 | |
1310 | if (IWL_UCODE_API(priv->ucode_ver) == 1) | |
1311 | tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1; | |
1312 | else | |
1313 | tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD; | |
1314 | ||
1315 | return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd, | |
630fe9b6 TW |
1316 | sizeof(tx_power_cmd), &tx_power_cmd, |
1317 | NULL); | |
1318 | } | |
1319 | ||
672639de | 1320 | void iwl5000_temperature(struct iwl_priv *priv) |
8f91aecb EG |
1321 | { |
1322 | /* store temperature from statistics (in Celsius) */ | |
5225640b | 1323 | priv->temperature = le32_to_cpu(priv->statistics.general.temperature); |
39b73fb1 | 1324 | iwl_tt_handler(priv); |
8f91aecb | 1325 | } |
fe7a90c2 | 1326 | |
62161aef WYG |
1327 | static void iwl5150_temperature(struct iwl_priv *priv) |
1328 | { | |
1329 | u32 vt = 0; | |
1330 | s32 offset = iwl_temp_calib_to_offset(priv); | |
1331 | ||
1332 | vt = le32_to_cpu(priv->statistics.general.temperature); | |
1333 | vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset; | |
1334 | /* now vt hold the temperature in Kelvin */ | |
1335 | priv->temperature = KELVIN_TO_CELSIUS(vt); | |
15993e08 | 1336 | iwl_tt_handler(priv); |
62161aef WYG |
1337 | } |
1338 | ||
caab8f1a | 1339 | /* Calc max signal level (dBm) among 3 possible receivers */ |
e8c00dcb | 1340 | int iwl5000_calc_rssi(struct iwl_priv *priv, |
caab8f1a TW |
1341 | struct iwl_rx_phy_res *rx_resp) |
1342 | { | |
1343 | /* data from PHY/DSP regarding signal strength, etc., | |
1344 | * contents are always there, not configurable by host | |
1345 | */ | |
1346 | struct iwl5000_non_cfg_phy *ncphy = | |
1347 | (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf; | |
1348 | u32 val, rssi_a, rssi_b, rssi_c, max_rssi; | |
1349 | u8 agc; | |
1350 | ||
1351 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]); | |
1352 | agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS; | |
1353 | ||
1354 | /* Find max rssi among 3 possible receivers. | |
1355 | * These values are measured by the digital signal processor (DSP). | |
1356 | * They should stay fairly constant even as the signal strength varies, | |
1357 | * if the radio's automatic gain control (AGC) is working right. | |
1358 | * AGC value (see below) will provide the "interesting" info. | |
1359 | */ | |
1360 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]); | |
1361 | rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS; | |
1362 | rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS; | |
1363 | val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]); | |
1364 | rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS; | |
1365 | ||
1366 | max_rssi = max_t(u32, rssi_a, rssi_b); | |
1367 | max_rssi = max_t(u32, max_rssi, rssi_c); | |
1368 | ||
e1623446 | 1369 | IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n", |
caab8f1a TW |
1370 | rssi_a, rssi_b, rssi_c, max_rssi, agc); |
1371 | ||
1372 | /* dBm = max_rssi dB - agc dB - constant. | |
1373 | * Higher AGC (higher radio gain) means lower signal. */ | |
250bdd21 | 1374 | return max_rssi - agc - IWL49_RSSI_OFFSET; |
caab8f1a TW |
1375 | } |
1376 | ||
2f748dec WYG |
1377 | static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant) |
1378 | { | |
1379 | struct iwl_tx_ant_config_cmd tx_ant_cmd = { | |
1380 | .valid = cpu_to_le32(valid_tx_ant), | |
1381 | }; | |
1382 | ||
1383 | if (IWL_UCODE_API(priv->ucode_ver) > 1) { | |
1384 | IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant); | |
1385 | return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD, | |
1386 | sizeof(struct iwl_tx_ant_config_cmd), | |
1387 | &tx_ant_cmd); | |
1388 | } else { | |
1389 | IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n"); | |
1390 | return -EOPNOTSUPP; | |
1391 | } | |
1392 | } | |
1393 | ||
1394 | ||
cc0f555d JS |
1395 | #define IWL5000_UCODE_GET(item) \ |
1396 | static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\ | |
1397 | u32 api_ver) \ | |
1398 | { \ | |
1399 | if (api_ver <= 2) \ | |
1400 | return le32_to_cpu(ucode->u.v1.item); \ | |
1401 | return le32_to_cpu(ucode->u.v2.item); \ | |
1402 | } | |
1403 | ||
1404 | static u32 iwl5000_ucode_get_header_size(u32 api_ver) | |
1405 | { | |
1406 | if (api_ver <= 2) | |
1407 | return UCODE_HEADER_SIZE(1); | |
1408 | return UCODE_HEADER_SIZE(2); | |
1409 | } | |
1410 | ||
1411 | static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode, | |
1412 | u32 api_ver) | |
1413 | { | |
1414 | if (api_ver <= 2) | |
1415 | return 0; | |
1416 | return le32_to_cpu(ucode->u.v2.build); | |
1417 | } | |
1418 | ||
1419 | static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode, | |
1420 | u32 api_ver) | |
1421 | { | |
1422 | if (api_ver <= 2) | |
1423 | return (u8 *) ucode->u.v1.data; | |
1424 | return (u8 *) ucode->u.v2.data; | |
1425 | } | |
1426 | ||
1427 | IWL5000_UCODE_GET(inst_size); | |
1428 | IWL5000_UCODE_GET(data_size); | |
1429 | IWL5000_UCODE_GET(init_size); | |
1430 | IWL5000_UCODE_GET(init_data_size); | |
1431 | IWL5000_UCODE_GET(boot_size); | |
1432 | ||
e8c00dcb | 1433 | struct iwl_hcmd_ops iwl5000_hcmd = { |
fe7a90c2 | 1434 | .rxon_assoc = iwl5000_send_rxon_assoc, |
e0158e61 | 1435 | .commit_rxon = iwl_commit_rxon, |
45823531 | 1436 | .set_rxon_chain = iwl_set_rxon_chain, |
2f748dec | 1437 | .set_tx_ant = iwl5000_send_tx_ant_config, |
da8dec29 TW |
1438 | }; |
1439 | ||
e8c00dcb | 1440 | struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = { |
c1adf9fb | 1441 | .get_hcmd_size = iwl5000_get_hcmd_size, |
2469bf2e | 1442 | .build_addsta_hcmd = iwl5000_build_addsta_hcmd, |
33fd5033 EG |
1443 | .gain_computation = iwl5000_gain_computation, |
1444 | .chain_noise_reset = iwl5000_chain_noise_reset, | |
a326a5d0 | 1445 | .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag, |
caab8f1a | 1446 | .calc_rssi = iwl5000_calc_rssi, |
da8dec29 TW |
1447 | }; |
1448 | ||
cc0f555d JS |
1449 | struct iwl_ucode_ops iwl5000_ucode = { |
1450 | .get_header_size = iwl5000_ucode_get_header_size, | |
1451 | .get_build = iwl5000_ucode_get_build, | |
1452 | .get_inst_size = iwl5000_ucode_get_inst_size, | |
1453 | .get_data_size = iwl5000_ucode_get_data_size, | |
1454 | .get_init_size = iwl5000_ucode_get_init_size, | |
1455 | .get_init_data_size = iwl5000_ucode_get_init_data_size, | |
1456 | .get_boot_size = iwl5000_ucode_get_boot_size, | |
1457 | .get_data = iwl5000_ucode_get_data, | |
1458 | }; | |
1459 | ||
e8c00dcb | 1460 | struct iwl_lib_ops iwl5000_lib = { |
fdd3e8a4 | 1461 | .set_hw_params = iwl5000_hw_set_hw_params, |
7839fc03 | 1462 | .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, |
972cf447 | 1463 | .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, |
da1bc453 | 1464 | .txq_set_sched = iwl5000_txq_set_sched, |
e26e47d9 TW |
1465 | .txq_agg_enable = iwl5000_txq_agg_enable, |
1466 | .txq_agg_disable = iwl5000_txq_agg_disable, | |
7aaa1d79 SO |
1467 | .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd, |
1468 | .txq_free_tfd = iwl_hw_txq_free_tfd, | |
a8e74e27 | 1469 | .txq_init = iwl_hw_tx_queue_init, |
b600e4e1 | 1470 | .rx_handler_setup = iwl5000_rx_handler_setup, |
203566f3 | 1471 | .setup_deferred_work = iwl5000_setup_deferred_work, |
87283cc1 | 1472 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, |
b7a79404 RC |
1473 | .dump_nic_event_log = iwl_dump_nic_event_log, |
1474 | .dump_nic_error_log = iwl_dump_nic_error_log, | |
dbb983b7 | 1475 | .load_ucode = iwl5000_load_ucode, |
99da1b48 RR |
1476 | .init_alive_start = iwl5000_init_alive_start, |
1477 | .alive_notify = iwl5000_alive_notify, | |
630fe9b6 | 1478 | .send_tx_power = iwl5000_send_tx_power, |
5b9f8cd3 | 1479 | .update_chain_flags = iwl_update_chain_flags, |
30d59260 TW |
1480 | .apm_ops = { |
1481 | .init = iwl5000_apm_init, | |
d68b603c | 1482 | .stop = iwl_apm_stop, |
5a835353 | 1483 | .config = iwl5000_nic_config, |
5b9f8cd3 | 1484 | .set_pwr_src = iwl_set_pwr_src, |
30d59260 | 1485 | }, |
da8dec29 | 1486 | .eeprom_ops = { |
25ae3986 TW |
1487 | .regulatory_bands = { |
1488 | EEPROM_5000_REG_BAND_1_CHANNELS, | |
1489 | EEPROM_5000_REG_BAND_2_CHANNELS, | |
1490 | EEPROM_5000_REG_BAND_3_CHANNELS, | |
1491 | EEPROM_5000_REG_BAND_4_CHANNELS, | |
1492 | EEPROM_5000_REG_BAND_5_CHANNELS, | |
7aafef1c WYG |
1493 | EEPROM_5000_REG_BAND_24_HT40_CHANNELS, |
1494 | EEPROM_5000_REG_BAND_52_HT40_CHANNELS | |
25ae3986 | 1495 | }, |
da8dec29 TW |
1496 | .verify_signature = iwlcore_eeprom_verify_signature, |
1497 | .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, | |
1498 | .release_semaphore = iwlcore_eeprom_release_semaphore, | |
0ef2ca67 | 1499 | .calib_version = iwl5000_eeprom_calib_version, |
25ae3986 | 1500 | .query_addr = iwl5000_eeprom_query_addr, |
da8dec29 | 1501 | }, |
5bbe233b | 1502 | .post_associate = iwl_post_associate, |
ef850d7c | 1503 | .isr = iwl_isr_ict, |
60690a6a | 1504 | .config_ap = iwl_config_ap, |
62161aef WYG |
1505 | .temp_ops = { |
1506 | .temperature = iwl5000_temperature, | |
1507 | .set_ct_kill = iwl5000_set_ct_threshold, | |
1508 | }, | |
1509 | }; | |
1510 | ||
1511 | static struct iwl_lib_ops iwl5150_lib = { | |
1512 | .set_hw_params = iwl5000_hw_set_hw_params, | |
1513 | .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl, | |
1514 | .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl, | |
1515 | .txq_set_sched = iwl5000_txq_set_sched, | |
1516 | .txq_agg_enable = iwl5000_txq_agg_enable, | |
1517 | .txq_agg_disable = iwl5000_txq_agg_disable, | |
1518 | .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd, | |
1519 | .txq_free_tfd = iwl_hw_txq_free_tfd, | |
1520 | .txq_init = iwl_hw_tx_queue_init, | |
1521 | .rx_handler_setup = iwl5000_rx_handler_setup, | |
1522 | .setup_deferred_work = iwl5000_setup_deferred_work, | |
1523 | .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr, | |
b7a79404 RC |
1524 | .dump_nic_event_log = iwl_dump_nic_event_log, |
1525 | .dump_nic_error_log = iwl_dump_nic_error_log, | |
62161aef WYG |
1526 | .load_ucode = iwl5000_load_ucode, |
1527 | .init_alive_start = iwl5000_init_alive_start, | |
1528 | .alive_notify = iwl5000_alive_notify, | |
1529 | .send_tx_power = iwl5000_send_tx_power, | |
1530 | .update_chain_flags = iwl_update_chain_flags, | |
1531 | .apm_ops = { | |
1532 | .init = iwl5000_apm_init, | |
d68b603c | 1533 | .stop = iwl_apm_stop, |
62161aef WYG |
1534 | .config = iwl5000_nic_config, |
1535 | .set_pwr_src = iwl_set_pwr_src, | |
1536 | }, | |
1537 | .eeprom_ops = { | |
1538 | .regulatory_bands = { | |
1539 | EEPROM_5000_REG_BAND_1_CHANNELS, | |
1540 | EEPROM_5000_REG_BAND_2_CHANNELS, | |
1541 | EEPROM_5000_REG_BAND_3_CHANNELS, | |
1542 | EEPROM_5000_REG_BAND_4_CHANNELS, | |
1543 | EEPROM_5000_REG_BAND_5_CHANNELS, | |
7aafef1c WYG |
1544 | EEPROM_5000_REG_BAND_24_HT40_CHANNELS, |
1545 | EEPROM_5000_REG_BAND_52_HT40_CHANNELS | |
62161aef WYG |
1546 | }, |
1547 | .verify_signature = iwlcore_eeprom_verify_signature, | |
1548 | .acquire_semaphore = iwlcore_eeprom_acquire_semaphore, | |
1549 | .release_semaphore = iwlcore_eeprom_release_semaphore, | |
1550 | .calib_version = iwl5000_eeprom_calib_version, | |
1551 | .query_addr = iwl5000_eeprom_query_addr, | |
1552 | }, | |
1553 | .post_associate = iwl_post_associate, | |
ef850d7c | 1554 | .isr = iwl_isr_ict, |
62161aef WYG |
1555 | .config_ap = iwl_config_ap, |
1556 | .temp_ops = { | |
1557 | .temperature = iwl5150_temperature, | |
1558 | .set_ct_kill = iwl5150_set_ct_threshold, | |
1559 | }, | |
da8dec29 TW |
1560 | }; |
1561 | ||
e932a609 | 1562 | static struct iwl_ops iwl5000_ops = { |
cc0f555d | 1563 | .ucode = &iwl5000_ucode, |
da8dec29 TW |
1564 | .lib = &iwl5000_lib, |
1565 | .hcmd = &iwl5000_hcmd, | |
1566 | .utils = &iwl5000_hcmd_utils, | |
e932a609 | 1567 | .led = &iwlagn_led_ops, |
da8dec29 TW |
1568 | }; |
1569 | ||
62161aef | 1570 | static struct iwl_ops iwl5150_ops = { |
cc0f555d | 1571 | .ucode = &iwl5000_ucode, |
62161aef WYG |
1572 | .lib = &iwl5150_lib, |
1573 | .hcmd = &iwl5000_hcmd, | |
1574 | .utils = &iwl5000_hcmd_utils, | |
e932a609 | 1575 | .led = &iwlagn_led_ops, |
62161aef WYG |
1576 | }; |
1577 | ||
cec2d3f3 | 1578 | struct iwl_mod_params iwl50_mod_params = { |
5a6a256e | 1579 | .num_of_queues = IWL50_NUM_QUEUES, |
9f17b318 | 1580 | .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES, |
5a6a256e | 1581 | .amsdu_size_8K = 1, |
3a1081e8 | 1582 | .restart_fw = 1, |
5a6a256e TW |
1583 | /* the rest are 0 by default */ |
1584 | }; | |
1585 | ||
1586 | ||
1587 | struct iwl_cfg iwl5300_agn_cfg = { | |
1588 | .name = "5300AGN", | |
a0987a8d RC |
1589 | .fw_name_pre = IWL5000_FW_PRE, |
1590 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1591 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
5a6a256e | 1592 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
da8dec29 | 1593 | .ops = &iwl5000_ops, |
25ae3986 | 1594 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
1595 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1596 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
5a6a256e | 1597 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1598 | .valid_tx_ant = ANT_ABC, |
1599 | .valid_rx_ant = ANT_ABC, | |
050681b7 | 1600 | .need_pll_cfg = true, |
b261793d | 1601 | .ht_greenfield_support = true, |
f2d0d0e2 | 1602 | .led_compensation = 51, |
d8c07e7a | 1603 | .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, |
5a6a256e TW |
1604 | }; |
1605 | ||
47408639 EK |
1606 | struct iwl_cfg iwl5100_bg_cfg = { |
1607 | .name = "5100BG", | |
a0987a8d RC |
1608 | .fw_name_pre = IWL5000_FW_PRE, |
1609 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1610 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
47408639 EK |
1611 | .sku = IWL_SKU_G, |
1612 | .ops = &iwl5000_ops, | |
1613 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, | |
0ef2ca67 TW |
1614 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1615 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
47408639 | 1616 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1617 | .valid_tx_ant = ANT_B, |
1618 | .valid_rx_ant = ANT_AB, | |
050681b7 | 1619 | .need_pll_cfg = true, |
b261793d | 1620 | .ht_greenfield_support = true, |
f2d0d0e2 | 1621 | .led_compensation = 51, |
d8c07e7a | 1622 | .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, |
47408639 EK |
1623 | }; |
1624 | ||
1625 | struct iwl_cfg iwl5100_abg_cfg = { | |
1626 | .name = "5100ABG", | |
a0987a8d RC |
1627 | .fw_name_pre = IWL5000_FW_PRE, |
1628 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1629 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
47408639 EK |
1630 | .sku = IWL_SKU_A|IWL_SKU_G, |
1631 | .ops = &iwl5000_ops, | |
1632 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, | |
0ef2ca67 TW |
1633 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1634 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
47408639 | 1635 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1636 | .valid_tx_ant = ANT_B, |
1637 | .valid_rx_ant = ANT_AB, | |
050681b7 | 1638 | .need_pll_cfg = true, |
b261793d | 1639 | .ht_greenfield_support = true, |
f2d0d0e2 | 1640 | .led_compensation = 51, |
d8c07e7a | 1641 | .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, |
47408639 EK |
1642 | }; |
1643 | ||
5a6a256e TW |
1644 | struct iwl_cfg iwl5100_agn_cfg = { |
1645 | .name = "5100AGN", | |
a0987a8d RC |
1646 | .fw_name_pre = IWL5000_FW_PRE, |
1647 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1648 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
5a6a256e | 1649 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
da8dec29 | 1650 | .ops = &iwl5000_ops, |
25ae3986 | 1651 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
1652 | .eeprom_ver = EEPROM_5000_EEPROM_VERSION, |
1653 | .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION, | |
5a6a256e | 1654 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1655 | .valid_tx_ant = ANT_B, |
1656 | .valid_rx_ant = ANT_AB, | |
050681b7 | 1657 | .need_pll_cfg = true, |
b261793d | 1658 | .ht_greenfield_support = true, |
f2d0d0e2 | 1659 | .led_compensation = 51, |
d8c07e7a | 1660 | .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, |
5a6a256e TW |
1661 | }; |
1662 | ||
1663 | struct iwl_cfg iwl5350_agn_cfg = { | |
1664 | .name = "5350AGN", | |
a0987a8d RC |
1665 | .fw_name_pre = IWL5000_FW_PRE, |
1666 | .ucode_api_max = IWL5000_UCODE_API_MAX, | |
1667 | .ucode_api_min = IWL5000_UCODE_API_MIN, | |
5a6a256e | 1668 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
da8dec29 | 1669 | .ops = &iwl5000_ops, |
25ae3986 | 1670 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
0ef2ca67 TW |
1671 | .eeprom_ver = EEPROM_5050_EEPROM_VERSION, |
1672 | .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, | |
5a6a256e | 1673 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1674 | .valid_tx_ant = ANT_ABC, |
1675 | .valid_rx_ant = ANT_ABC, | |
050681b7 | 1676 | .need_pll_cfg = true, |
b261793d | 1677 | .ht_greenfield_support = true, |
f2d0d0e2 | 1678 | .led_compensation = 51, |
d8c07e7a | 1679 | .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, |
5a6a256e TW |
1680 | }; |
1681 | ||
7100e924 TW |
1682 | struct iwl_cfg iwl5150_agn_cfg = { |
1683 | .name = "5150AGN", | |
a0987a8d RC |
1684 | .fw_name_pre = IWL5150_FW_PRE, |
1685 | .ucode_api_max = IWL5150_UCODE_API_MAX, | |
1686 | .ucode_api_min = IWL5150_UCODE_API_MIN, | |
7100e924 | 1687 | .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N, |
62161aef | 1688 | .ops = &iwl5150_ops, |
7100e924 | 1689 | .eeprom_size = IWL_5000_EEPROM_IMG_SIZE, |
fd63edba TW |
1690 | .eeprom_ver = EEPROM_5050_EEPROM_VERSION, |
1691 | .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION, | |
7100e924 | 1692 | .mod_params = &iwl50_mod_params, |
c0bac76a JS |
1693 | .valid_tx_ant = ANT_A, |
1694 | .valid_rx_ant = ANT_AB, | |
050681b7 | 1695 | .need_pll_cfg = true, |
b261793d | 1696 | .ht_greenfield_support = true, |
f2d0d0e2 | 1697 | .led_compensation = 51, |
d8c07e7a | 1698 | .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS, |
7100e924 TW |
1699 | }; |
1700 | ||
a0987a8d RC |
1701 | MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX)); |
1702 | MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX)); | |
c9f79ed2 | 1703 | |
4e30cb69 | 1704 | module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO); |
5a6a256e TW |
1705 | MODULE_PARM_DESC(swcrypto50, |
1706 | "using software crypto engine (default 0 [hardware])\n"); | |
4e30cb69 | 1707 | module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO); |
5a6a256e | 1708 | MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series"); |
4e30cb69 | 1709 | module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO); |
49779293 | 1710 | MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality"); |
4e30cb69 WYG |
1711 | module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, |
1712 | int, S_IRUGO); | |
5a6a256e | 1713 | MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series"); |
4e30cb69 | 1714 | module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO); |
3a1081e8 | 1715 | MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error"); |