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iwlwifi: use new mac80211 SMPS
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
CommitLineData
5a6a256e
TW		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
5a6a256e
TW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26#include <linux/kernel.h>
27#include <linux/module.h>
5a6a256e
TW		 28#include <linux/init.h>
29#include <linux/pci.h>
30#include <linux/dma-mapping.h>
31#include <linux/delay.h>
d43c36dc 32#include <linux/sched.h>
5a6a256e
TW		 33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <net/mac80211.h>
37#include <linux/etherdevice.h>
38#include <asm/unaligned.h>
39
40#include "iwl-eeprom.h"
3e0d4cb1 41#include "iwl-dev.h"
5a6a256e
TW		 42#include "iwl-core.h"
43#include "iwl-io.h"
e26e47d9 44#include "iwl-sta.h"
5a6a256e 45#include "iwl-helpers.h"
e932a609 46#include "iwl-agn-led.h"
5a6a256e 47#include "iwl-5000-hw.h"
c0bac76a 48#include "iwl-6000-hw.h"
5a6a256e 49
a0987a8d 50/* Highest firmware API version supported */
c9d2fbf3 51#define IWL5000_UCODE_API_MAX 2
39e6d225 52#define IWL5150_UCODE_API_MAX 2
5a6a256e 53
a0987a8d
RC		 54/* Lowest firmware API version supported */
55#define IWL5000_UCODE_API_MIN 1
56#define IWL5150_UCODE_API_MIN 1
57
58#define IWL5000_FW_PRE "iwlwifi-5000-"
59#define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
60#define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
61
62#define IWL5150_FW_PRE "iwlwifi-5150-"
63#define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
64#define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
4e062f99 65
99da1b48
RR		 66static const u16 iwl5000_default_queue_to_tx_fifo[] = {
67 IWL_TX_FIFO_AC3,
68 IWL_TX_FIFO_AC2,
69 IWL_TX_FIFO_AC1,
70 IWL_TX_FIFO_AC0,
71 IWL50_CMD_FIFO_NUM,
72 IWL_TX_FIFO_HCCA_1,
73 IWL_TX_FIFO_HCCA_2
74};
75
9371d4ed 76/* NIC configuration for 5000 series */
672639de 77void iwl5000_nic_config(struct iwl_priv *priv)
e86fe9f6
TW		 78{
79 unsigned long flags;
80 u16 radio_cfg;
e86fe9f6
TW		 81
82 spin_lock_irqsave(&priv->lock, flags);
83
e86fe9f6
TW		 84 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
85
86 /* write radio config values to register */
9371d4ed 87 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
e86fe9f6
TW		 88 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
89 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
90 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
91 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
92
93 /* set CSR_HW_CONFIG_REG for uCode use */
94 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
95 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
96 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
97
4c43e0d0
TW		 98 /* W/A : NIC is stuck in a reset state after Early PCIe power off
99 * (PCIe power is lost before PERST# is asserted),
100 * causing ME FW to lose ownership and not being able to obtain it back.
101 */
2d3db679 102 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
4c43e0d0
TW		 103 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
104 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
105
02c06e4a 106
e86fe9f6
TW		 107 spin_unlock_irqrestore(&priv->lock, flags);
108}
109
110
25ae3986
TW		 111/*
112 * EEPROM
113 */
114static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
115{
116 u16 offset = 0;
117
118 if ((address & INDIRECT_ADDRESS) == 0)
119 return address;
120
121 switch (address & INDIRECT_TYPE_MSK) {
122 case INDIRECT_HOST:
123 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
124 break;
125 case INDIRECT_GENERAL:
126 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
127 break;
128 case INDIRECT_REGULATORY:
129 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
130 break;
131 case INDIRECT_CALIBRATION:
132 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
133 break;
134 case INDIRECT_PROCESS_ADJST:
135 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
136 break;
137 case INDIRECT_OTHERS:
138 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
139 break;
140 default:
15b1687c 141 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
25ae3986
TW		 142 address & INDIRECT_TYPE_MSK);
143 break;
144 }
145
146 /* translate the offset from words to byte */
147 return (address & ADDRESS_MSK) + (offset << 1);
148}
149
672639de 150u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
f1f69415 151{
f1f69415
TW		 152 struct iwl_eeprom_calib_hdr {
153 u8 version;
154 u8 pa_type;
155 u16 voltage;
156 } *hdr;
157
f1f69415
TW		 158 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
159 EEPROM_5000_CALIB_ALL);
0ef2ca67 160 return hdr->version;
f1f69415
TW		 161
162}
163
33fd5033
EG		 164static void iwl5000_gain_computation(struct iwl_priv *priv,
165 u32 average_noise[NUM_RX_CHAINS],
166 u16 min_average_noise_antenna_i,
d8c07e7a
WYG		 167 u32 min_average_noise,
168 u8 default_chain)
33fd5033
EG		 169{
170 int i;
171 s32 delta_g;
172 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
173
d8c07e7a
WYG		 174 /*
175 * Find Gain Code for the chains based on "default chain"
176 */
177 for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
33fd5033
EG		 178 if ((data->disconn_array[i])) {
179 data->delta_gain_code[i] = 0;
180 continue;
181 }
065e63b0 182 delta_g = (1000 * ((s32)average_noise[default_chain] -
33fd5033
EG		 183 (s32)average_noise[i])) / 1500;
184 /* bound gain by 2 bits value max, 3rd bit is sign */
185 data->delta_gain_code[i] =
886e71de 186 min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
33fd5033
EG		 187
188 if (delta_g < 0)
189 /* set negative sign */
190 data->delta_gain_code[i] |= (1 << 2);
191 }
192
e1623446 193 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
33fd5033
EG		 194 data->delta_gain_code[1], data->delta_gain_code[2]);
195
196 if (!data->radio_write) {
f69f42a6 197 struct iwl_calib_chain_noise_gain_cmd cmd;
0d950d84 198
33fd5033
EG		 199 memset(&cmd, 0, sizeof(cmd));
200
0d950d84
TW		 201 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
202 cmd.hdr.first_group = 0;
203 cmd.hdr.groups_num = 1;
204 cmd.hdr.data_valid = 1;
33fd5033
EG		 205 cmd.delta_gain_1 = data->delta_gain_code[1];
206 cmd.delta_gain_2 = data->delta_gain_code[2];
207 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
208 sizeof(cmd), &cmd, NULL);
209
210 data->radio_write = 1;
211 data->state = IWL_CHAIN_NOISE_CALIBRATED;
212 }
213
214 data->chain_noise_a = 0;
215 data->chain_noise_b = 0;
216 data->chain_noise_c = 0;
217 data->chain_signal_a = 0;
218 data->chain_signal_b = 0;
219 data->chain_signal_c = 0;
220 data->beacon_count = 0;
221}
222
223static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
224{
225 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
0d950d84 226 int ret;
33fd5033
EG		 227
228 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
f69f42a6 229 struct iwl_calib_chain_noise_reset_cmd cmd;
33fd5033 230 memset(&cmd, 0, sizeof(cmd));
0d950d84
TW		 231
232 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
233 cmd.hdr.first_group = 0;
234 cmd.hdr.groups_num = 1;
235 cmd.hdr.data_valid = 1;
236 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
237 sizeof(cmd), &cmd);
238 if (ret)
15b1687c
WT		 239 IWL_ERR(priv,
240 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
33fd5033 241 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
e1623446 242 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
33fd5033
EG		 243 }
244}
245
e8c00dcb 246void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
a326a5d0
EG		 247 __le32 *tx_flags)
248{
e6a9854b
JB		 249 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
250 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
a326a5d0
EG		 251 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
252 else
253 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
254}
255
33fd5033
EG		 256static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
257 .min_nrg_cck = 95,
fe6efb4b 258 .max_nrg_cck = 0, /* not used, set to 0 */
33fd5033
EG		 259 .auto_corr_min_ofdm = 90,
260 .auto_corr_min_ofdm_mrc = 170,
261 .auto_corr_min_ofdm_x1 = 120,
262 .auto_corr_min_ofdm_mrc_x1 = 240,
263
264 .auto_corr_max_ofdm = 120,
265 .auto_corr_max_ofdm_mrc = 210,
266 .auto_corr_max_ofdm_x1 = 155,
267 .auto_corr_max_ofdm_mrc_x1 = 290,
268
269 .auto_corr_min_cck = 125,
270 .auto_corr_max_cck = 200,
271 .auto_corr_min_cck_mrc = 170,
272 .auto_corr_max_cck_mrc = 400,
273 .nrg_th_cck = 95,
274 .nrg_th_ofdm = 95,
55036d66
WYG		 275
276 .barker_corr_th_min = 190,
277 .barker_corr_th_min_mrc = 390,
278 .nrg_th_cca = 62,
33fd5033
EG		 279};
280
9d67187d
WYG		 281static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
282 .min_nrg_cck = 95,
283 .max_nrg_cck = 0, /* not used, set to 0 */
284 .auto_corr_min_ofdm = 90,
285 .auto_corr_min_ofdm_mrc = 170,
286 .auto_corr_min_ofdm_x1 = 105,
287 .auto_corr_min_ofdm_mrc_x1 = 220,
288
289 .auto_corr_max_ofdm = 120,
290 .auto_corr_max_ofdm_mrc = 210,
291 /* max = min for performance bug in 5150 DSP */
292 .auto_corr_max_ofdm_x1 = 105,
293 .auto_corr_max_ofdm_mrc_x1 = 220,
294
295 .auto_corr_min_cck = 125,
296 .auto_corr_max_cck = 200,
297 .auto_corr_min_cck_mrc = 170,
298 .auto_corr_max_cck_mrc = 400,
299 .nrg_th_cck = 95,
300 .nrg_th_ofdm = 95,
55036d66
WYG		 301
302 .barker_corr_th_min = 190,
303 .barker_corr_th_min_mrc = 390,
304 .nrg_th_cca = 62,
9d67187d
WYG		 305};
306
672639de 307const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
25ae3986
TW		 308 size_t offset)
309{
310 u32 address = eeprom_indirect_address(priv, offset);
311 BUG_ON(address >= priv->cfg->eeprom_size);
312 return &priv->eeprom[address];
313}
314
62161aef 315static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
339afc89 316{
62161aef 317 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
672639de 318 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
62161aef
WYG		 319 iwl_temp_calib_to_offset(priv);
320
321 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
322}
323
324static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
325{
326 /* want Celsius */
672639de 327 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
339afc89
TW		 328}
329
7c616cba
TW		 330/*
331 * Calibration
332 */
be5d56ed 333static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
7c616cba 334{
0d950d84 335 struct iwl_calib_xtal_freq_cmd cmd;
7c616cba
TW		 336 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
337
0d950d84
TW		 338 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
339 cmd.hdr.first_group = 0;
340 cmd.hdr.groups_num = 1;
341 cmd.hdr.data_valid = 1;
342 cmd.cap_pin1 = (u8)xtal_calib[0];
343 cmd.cap_pin2 = (u8)xtal_calib[1];
f69f42a6 344 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
0d950d84 345 (u8 *)&cmd, sizeof(cmd));
7c616cba
TW		 346}
347
7c616cba
TW		 348static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
349{
f69f42a6 350 struct iwl_calib_cfg_cmd calib_cfg_cmd;
7c616cba
TW		 351 struct iwl_host_cmd cmd = {
352 .id = CALIBRATION_CFG_CMD,
f69f42a6 353 .len = sizeof(struct iwl_calib_cfg_cmd),
7c616cba
TW		 354 .data = &calib_cfg_cmd,
355 };
356
357 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
358 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
359 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
360 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
361 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
362
363 return iwl_send_cmd(priv, &cmd);
364}
365
366static void iwl5000_rx_calib_result(struct iwl_priv *priv,
367 struct iwl_rx_mem_buffer *rxb)
368{
2f301227 369 struct iwl_rx_packet *pkt = rxb_addr(rxb);
f69f42a6 370 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
396887a2 371 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
6e21f2c1 372 int index;
7c616cba
TW		 373
374 /* reduce the size of the length field itself */
375 len -= 4;
376
6e21f2c1
TW		 377 /* Define the order in which the results will be sent to the runtime
378 * uCode. iwl_send_calib_results sends them in a row according to their
379 * index. We sort them here */
7c616cba 380 switch (hdr->op_code) {
819500c5
TW		 381 case IWL_PHY_CALIBRATE_DC_CMD:
382 index = IWL_CALIB_DC;
383 break;
f69f42a6
TW		 384 case IWL_PHY_CALIBRATE_LO_CMD:
385 index = IWL_CALIB_LO;
7c616cba 386 break;
f69f42a6
TW		 387 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
388 index = IWL_CALIB_TX_IQ;
7c616cba 389 break;
f69f42a6
TW		 390 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
391 index = IWL_CALIB_TX_IQ_PERD;
7c616cba 392 break;
201706ac
TW		 393 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
394 index = IWL_CALIB_BASE_BAND;
395 break;
7c616cba 396 default:
15b1687c 397 IWL_ERR(priv, "Unknown calibration notification %d\n",
7c616cba
TW		 398 hdr->op_code);
399 return;
400 }
6e21f2c1 401 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
7c616cba
TW		 402}
403
404static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
405 struct iwl_rx_mem_buffer *rxb)
406{
e1623446 407 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
7c616cba
TW		 408 queue_work(priv->workqueue, &priv->restart);
409}
410
dbb983b7
RR		 411/*
412 * ucode
413 */
414static int iwl5000_load_section(struct iwl_priv *priv,
415 struct fw_desc *image,
416 u32 dst_addr)
417{
dbb983b7
RR		 418 dma_addr_t phy_addr = image->p_addr;
419 u32 byte_cnt = image->len;
420
dbb983b7
RR		 421 iwl_write_direct32(priv,
422 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
423 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
424
425 iwl_write_direct32(priv,
426 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
427
428 iwl_write_direct32(priv,
429 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
430 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
431
dbb983b7 432 iwl_write_direct32(priv,
f0b9f5cb 433 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
499b1883 434 (iwl_get_dma_hi_addr(phy_addr)
f0b9f5cb
TW		 435 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
436
dbb983b7
RR		 437 iwl_write_direct32(priv,
438 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
439 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
440 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
441 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
442
443 iwl_write_direct32(priv,
444 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
445 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
9c80c502 446 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
dbb983b7
RR		 447 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
448
dbb983b7
RR		 449 return 0;
450}
451
452static int iwl5000_load_given_ucode(struct iwl_priv *priv,
453 struct fw_desc *inst_image,
454 struct fw_desc *data_image)
455{
456 int ret = 0;
457
250bdd21
SO		 458 ret = iwl5000_load_section(priv, inst_image,
459 IWL50_RTC_INST_LOWER_BOUND);
dbb983b7
RR		 460 if (ret)
461 return ret;
462
e1623446 463 IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
dbb983b7 464 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
9c80c502 465 priv->ucode_write_complete, 5 * HZ);
dbb983b7 466 if (ret == -ERESTARTSYS) {
15b1687c 467 IWL_ERR(priv, "Could not load the INST uCode section due "
dbb983b7
RR		 468 "to interrupt\n");
469 return ret;
470 }
471 if (!ret) {
15b1687c 472 IWL_ERR(priv, "Could not load the INST uCode section\n");
dbb983b7
RR		 473 return -ETIMEDOUT;
474 }
475
476 priv->ucode_write_complete = 0;
477
478 ret = iwl5000_load_section(
250bdd21 479 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
dbb983b7
RR		 480 if (ret)
481 return ret;
482
e1623446 483 IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
dbb983b7
RR		 484
485 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
486 priv->ucode_write_complete, 5 * HZ);
487 if (ret == -ERESTARTSYS) {
15b1687c 488 IWL_ERR(priv, "Could not load the INST uCode section due "
dbb983b7
RR		 489 "to interrupt\n");
490 return ret;
491 } else if (!ret) {
15b1687c 492 IWL_ERR(priv, "Could not load the DATA uCode section\n");
dbb983b7
RR		 493 return -ETIMEDOUT;
494 } else
495 ret = 0;
496
497 priv->ucode_write_complete = 0;
498
499 return ret;
500}
501
672639de 502int iwl5000_load_ucode(struct iwl_priv *priv)
dbb983b7
RR		 503{
504 int ret = 0;
505
506 /* check whether init ucode should be loaded, or rather runtime ucode */
507 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
e1623446 508 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
dbb983b7
RR		 509 ret = iwl5000_load_given_ucode(priv,
510 &priv->ucode_init, &priv->ucode_init_data);
511 if (!ret) {
e1623446 512 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
dbb983b7
RR		 513 priv->ucode_type = UCODE_INIT;
514 }
515 } else {
e1623446 516 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
dbb983b7
RR		 517 "Loading runtime ucode...\n");
518 ret = iwl5000_load_given_ucode(priv,
519 &priv->ucode_code, &priv->ucode_data);
520 if (!ret) {
e1623446 521 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
dbb983b7
RR		 522 priv->ucode_type = UCODE_RT;
523 }
524 }
525
526 return ret;
527}
528
672639de 529void iwl5000_init_alive_start(struct iwl_priv *priv)
99da1b48
RR		 530{
531 int ret = 0;
532
533 /* Check alive response for "valid" sign from uCode */
534 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
535 /* We had an error bringing up the hardware, so take it
536 * all the way back down so we can try again */
e1623446 537 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
99da1b48
RR		 538 goto restart;
539 }
540
541 /* initialize uCode was loaded... verify inst image.
542 * This is a paranoid check, because we would not have gotten the
543 * "initialize" alive if code weren't properly loaded. */
544 if (iwl_verify_ucode(priv)) {
545 /* Runtime instruction load was bad;
546 * take it all the way back down so we can try again */
e1623446 547 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
99da1b48
RR		 548 goto restart;
549 }
550
c587de0b 551 iwl_clear_stations_table(priv);
99da1b48
RR		 552 ret = priv->cfg->ops->lib->alive_notify(priv);
553 if (ret) {
39aadf8c
WT		 554 IWL_WARN(priv,
555 "Could not complete ALIVE transition: %d\n", ret);
99da1b48
RR		 556 goto restart;
557 }
558
7c616cba 559 iwl5000_send_calib_cfg(priv);
99da1b48
RR		 560 return;
561
562restart:
563 /* real restart (first load init_ucode) */
564 queue_work(priv->workqueue, &priv->restart);
565}
566
567static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
568 int txq_id, u32 index)
569{
570 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
571 (index & 0xff) | (txq_id << 8));
572 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
573}
574
575static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
576 struct iwl_tx_queue *txq,
577 int tx_fifo_id, int scd_retry)
578{
579 int txq_id = txq->q.id;
3fd07a1e 580 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
99da1b48
RR		 581
582 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
583 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
584 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
585 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
586 IWL50_SCD_QUEUE_STTS_REG_MSK);
587
588 txq->sched_retry = scd_retry;
589
e1623446 590 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
99da1b48
RR		 591 active ? "Activate" : "Deactivate",
592 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
593}
594
672639de 595int iwl5000_alive_notify(struct iwl_priv *priv)
99da1b48
RR		 596{
597 u32 a;
99da1b48 598 unsigned long flags;
31a73fe4 599 int i, chan;
40fc95d5 600 u32 reg_val;
99da1b48
RR		 601
602 spin_lock_irqsave(&priv->lock, flags);
603
99da1b48
RR		 604 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
605 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
606 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
607 a += 4)
608 iwl_write_targ_mem(priv, a, 0);
609 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
610 a += 4)
611 iwl_write_targ_mem(priv, a, 0);
39d5e0ce
HW		 612 for (; a < priv->scd_base_addr +
613 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
99da1b48
RR		 614 iwl_write_targ_mem(priv, a, 0);
615
616 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
4ddbb7d0 617 priv->scd_bc_tbls.dma >> 10);
31a73fe4
WT		 618
619 /* Enable DMA channel */
620 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
621 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
622 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
623 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
624
40fc95d5
WT		 625 /* Update FH chicken bits */
626 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
627 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
628 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
629
99da1b48 630 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
4ddbb7d0 631 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
99da1b48
RR		 632 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
633
634 /* initiate the queues */
635 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
636 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
637 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
638 iwl_write_targ_mem(priv, priv->scd_base_addr +
639 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
640 iwl_write_targ_mem(priv, priv->scd_base_addr +
641 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
642 sizeof(u32),
643 ((SCD_WIN_SIZE <<
644 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
645 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
646 ((SCD_FRAME_LIMIT <<
647 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
648 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
649 }
650
651 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
da1bc453 652 IWL_MASK(0, priv->hw_params.max_txq_num));
99da1b48 653
da1bc453
TW		 654 /* Activate all Tx DMA/FIFO channels */
655 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
99da1b48
RR		 656
657 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
9c80c502 658
99da1b48
RR		 659 /* map qos queues to fifos one-to-one */
660 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
661 int ac = iwl5000_default_queue_to_tx_fifo[i];
662 iwl_txq_ctx_activate(priv, i);
663 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
664 }
a221e6f7
JB		 665
666 /*
667 * TODO - need to initialize these queues and map them to FIFOs
668 * in the loop above, not only mark them as active. We do this
669 * because we want the first aggregation queue to be queue #10,
670 * but do not use 8 or 9 otherwise yet.
671 */
99da1b48
RR		 672 iwl_txq_ctx_activate(priv, 7);
673 iwl_txq_ctx_activate(priv, 8);
674 iwl_txq_ctx_activate(priv, 9);
675
99da1b48
RR		 676 spin_unlock_irqrestore(&priv->lock, flags);
677
7c616cba 678
1933ac4d 679 iwl_send_wimax_coex(priv);
9636e583 680
be5d56ed
TW		 681 iwl5000_set_Xtal_calib(priv);
682 iwl_send_calib_results(priv);
7c616cba 683
99da1b48
RR		 684 return 0;
685}
686
672639de 687int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
fdd3e8a4 688{
88804e2b
WYG		 689 if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
690 priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES)
691 priv->cfg->num_of_queues =
692 priv->cfg->mod_params->num_of_queues;
25ae3986 693
88804e2b 694 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
f3f911d1 695 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
4ddbb7d0 696 priv->hw_params.scd_bc_tbls_size =
88804e2b
WYG		 697 priv->cfg->num_of_queues *
698 sizeof(struct iwl5000_scd_bc_tbl);
a8e74e27 699 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
fdd3e8a4
TW		 700 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
701 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
c0bac76a 702
f3a2a424
WYG		 703 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
704 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
c0bac76a 705
da154e30 706 priv->hw_params.max_bsm_size = 0;
7aafef1c 707 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
fdd3e8a4 708 BIT(IEEE80211_BAND_5GHZ);
141c43a3
WT		 709 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
710
c0bac76a
JS		 711 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
712 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
713 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
714 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
c031bf80 715
62161aef
WYG		 716 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
717 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
c031bf80 718
9d67187d 719 /* Set initial sensitivity parameters */
be5d56ed
TW		 720 /* Set initial calibration set */
721 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
c0bac76a 722 case CSR_HW_REV_TYPE_5150:
9d67187d 723 priv->hw_params.sens = &iwl5150_sensitivity;
be5d56ed 724 priv->hw_params.calib_init_cfg =
c0bac76a 725 BIT(IWL_CALIB_DC) |
f69f42a6 726 BIT(IWL_CALIB_LO) |
201706ac 727 BIT(IWL_CALIB_TX_IQ) |
201706ac 728 BIT(IWL_CALIB_BASE_BAND);
c0bac76a 729
be5d56ed 730 break;
c0bac76a 731 default:
9d67187d 732 priv->hw_params.sens = &iwl5000_sensitivity;
819500c5 733 priv->hw_params.calib_init_cfg =
c0bac76a 734 BIT(IWL_CALIB_XTAL) |
7470d7f5
WT		 735 BIT(IWL_CALIB_LO) |
736 BIT(IWL_CALIB_TX_IQ) |
c0bac76a 737 BIT(IWL_CALIB_TX_IQ_PERD) |
7470d7f5 738 BIT(IWL_CALIB_BASE_BAND);
be5d56ed
TW		 739 break;
740 }
741
fdd3e8a4
TW		 742 return 0;
743}
d4100dd9 744
7839fc03
EG		 745/**
746 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
747 */
672639de 748void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 749 struct iwl_tx_queue *txq,
7839fc03
EG		 750 u16 byte_cnt)
751{
4ddbb7d0 752 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab 753 int write_ptr = txq->q.write_ptr;
7839fc03
EG		 754 int txq_id = txq->q.id;
755 u8 sec_ctl = 0;
127901ab
TW		 756 u8 sta_id = 0;
757 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
758 __le16 bc_ent;
7839fc03 759
127901ab 760 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
7839fc03
EG		 761
762 if (txq_id != IWL_CMD_QUEUE_NUM) {
127901ab 763 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
da99c4b6 764 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
7839fc03
EG		 765
766 switch (sec_ctl & TX_CMD_SEC_MSK) {
767 case TX_CMD_SEC_CCM:
768 len += CCMP_MIC_LEN;
769 break;
770 case TX_CMD_SEC_TKIP:
771 len += TKIP_ICV_LEN;
772 break;
773 case TX_CMD_SEC_WEP:
774 len += WEP_IV_LEN + WEP_ICV_LEN;
775 break;
776 }
777 }
778
127901ab 779 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
7839fc03 780
4ddbb7d0 781 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
7839fc03 782
127901ab 783 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 784 scd_bc_tbl[txq_id].
127901ab 785 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
7839fc03
EG		 786}
787
672639de 788void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
972cf447
TW		 789 struct iwl_tx_queue *txq)
790{
4ddbb7d0 791 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab
TW		 792 int txq_id = txq->q.id;
793 int read_ptr = txq->q.read_ptr;
794 u8 sta_id = 0;
795 __le16 bc_ent;
796
797 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
972cf447
TW		 798
799 if (txq_id != IWL_CMD_QUEUE_NUM)
127901ab 800 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
972cf447 801
127901ab 802 bc_ent = cpu_to_le16(1 | (sta_id << 12));
4ddbb7d0 803 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
972cf447 804
127901ab 805 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 806 scd_bc_tbl[txq_id].
127901ab 807 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
972cf447
TW		 808}
809
e26e47d9
TW		 810static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
811 u16 txq_id)
812{
813 u32 tbl_dw_addr;
814 u32 tbl_dw;
815 u16 scd_q2ratid;
816
817 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
818
819 tbl_dw_addr = priv->scd_base_addr +
820 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
821
822 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
823
824 if (txq_id & 0x1)
825 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
826 else
827 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
828
829 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
830
831 return 0;
832}
833static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
834{
835 /* Simply stop the queue, but don't change any configuration;
836 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
837 iwl_write_prph(priv,
838 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
839 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
840 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
841}
842
672639de 843int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
e26e47d9
TW		 844 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
845{
846 unsigned long flags;
e26e47d9
TW		 847 u16 ra_tid;
848
9f17b318 849 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
88804e2b
WYG		 850 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
851 <= txq_id)) {
39aadf8c
WT		 852 IWL_WARN(priv,
853 "queue number out of range: %d, must be %d to %d\n",
9f17b318 854 txq_id, IWL50_FIRST_AMPDU_QUEUE,
88804e2b
WYG		 855 IWL50_FIRST_AMPDU_QUEUE +
856 priv->cfg->num_of_ampdu_queues - 1);
9f17b318
TW		 857 return -EINVAL;
858 }
e26e47d9
TW		 859
860 ra_tid = BUILD_RAxTID(sta_id, tid);
861
862 /* Modify device's station table to Tx this TID */
9f58671e 863 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
e26e47d9
TW		 864
865 spin_lock_irqsave(&priv->lock, flags);
e26e47d9
TW		 866
867 /* Stop this Tx queue before configuring it */
868 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
869
870 /* Map receiver-address / traffic-ID to this queue */
871 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
872
873 /* Set this queue as a chain-building queue */
874 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
875
876 /* enable aggregations for the queue */
877 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
878
879 /* Place first TFD at index corresponding to start sequence number.
880 * Assumes that ssn_idx is valid (!= 0xFFF) */
881 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
882 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
883 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
884
885 /* Set up Tx window size and frame limit for this queue */
886 iwl_write_targ_mem(priv, priv->scd_base_addr +
887 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
888 sizeof(u32),
889 ((SCD_WIN_SIZE <<
890 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
891 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
892 ((SCD_FRAME_LIMIT <<
893 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
894 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
895
896 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
897
898 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
899 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
900
e26e47d9
TW		 901 spin_unlock_irqrestore(&priv->lock, flags);
902
903 return 0;
904}
905
672639de 906int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
e26e47d9
TW		 907 u16 ssn_idx, u8 tx_fifo)
908{
9f17b318 909 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
88804e2b
WYG		 910 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
911 <= txq_id)) {
a2f1cbeb 912 IWL_ERR(priv,
39aadf8c 913 "queue number out of range: %d, must be %d to %d\n",
9f17b318 914 txq_id, IWL50_FIRST_AMPDU_QUEUE,
88804e2b
WYG		 915 IWL50_FIRST_AMPDU_QUEUE +
916 priv->cfg->num_of_ampdu_queues - 1);
e26e47d9
TW		 917 return -EINVAL;
918 }
919
e26e47d9
TW		 920 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
921
922 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
923
924 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
925 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
926 /* supposes that ssn_idx is valid (!= 0xFFF) */
927 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
928
929 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
930 iwl_txq_ctx_deactivate(priv, txq_id);
931 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
932
e26e47d9
TW		 933 return 0;
934}
935
e8c00dcb 936u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2469bf2e
TW		 937{
938 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
c587de0b
TW		 939 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
940 memcpy(addsta, cmd, size);
941 /* resrved in 5000 */
942 addsta->rate_n_flags = cpu_to_le16(0);
2469bf2e
TW		 943 return size;
944}
945
946
da1bc453 947/*
a96a27f9 948 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
da1bc453
TW		 949 * must be called under priv->lock and mac access
950 */
672639de 951void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
5a676bbe 952{
da1bc453 953 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
5a676bbe
RR		 954}
955
e532fa0e
RR		 956
957static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
958{
3ac7f146 959 return le32_to_cpup((__le32 *)&tx_resp->status +
25a6572c 960 tx_resp->frame_count) & MAX_SN;
e532fa0e
RR		 961}
962
963static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
964 struct iwl_ht_agg *agg,
965 struct iwl5000_tx_resp *tx_resp,
25a6572c 966 int txq_id, u16 start_idx)
e532fa0e
RR		 967{
968 u16 status;
969 struct agg_tx_status *frame_status = &tx_resp->status;
970 struct ieee80211_tx_info *info = NULL;
971 struct ieee80211_hdr *hdr = NULL;
e7d326ac 972 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 973 int i, sh, idx;
e532fa0e
RR		 974 u16 seq;
975
976 if (agg->wait_for_ba)
e1623446 977 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
e532fa0e
RR		 978
979 agg->frame_count = tx_resp->frame_count;
980 agg->start_idx = start_idx;
e7d326ac 981 agg->rate_n_flags = rate_n_flags;
e532fa0e
RR		 982 agg->bitmap = 0;
983
984 /* # frames attempted by Tx command */
985 if (agg->frame_count == 1) {
986 /* Only one frame was attempted; no block-ack will arrive */
987 status = le16_to_cpu(frame_status[0].status);
25a6572c 988 idx = start_idx;
e532fa0e
RR		 989
990 /* FIXME: code repetition */
e1623446 991 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
e532fa0e
RR		 992 agg->frame_count, agg->start_idx, idx);
993
994 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
e6a9854b 995 info->status.rates[0].count = tx_resp->failure_frame + 1;
e532fa0e 996 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
c397bf15 997 info->flags |= iwl_tx_status_to_mac80211(status);
e7d326ac
TW		 998 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
999
e532fa0e
RR		 1000 /* FIXME: code repetition end */
1001
e1623446 1002 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
e532fa0e 1003 status & 0xff, tx_resp->failure_frame);
e1623446 1004 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
e532fa0e
RR		 1005
1006 agg->wait_for_ba = 0;
1007 } else {
1008 /* Two or more frames were attempted; expect block-ack */
1009 u64 bitmap = 0;
1010 int start = agg->start_idx;
1011
1012 /* Construct bit-map of pending frames within Tx window */
1013 for (i = 0; i < agg->frame_count; i++) {
1014 u16 sc;
1015 status = le16_to_cpu(frame_status[i].status);
1016 seq = le16_to_cpu(frame_status[i].sequence);
1017 idx = SEQ_TO_INDEX(seq);
1018 txq_id = SEQ_TO_QUEUE(seq);
1019
1020 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1021 AGG_TX_STATE_ABORT_MSK))
1022 continue;
1023
e1623446 1024 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
e532fa0e
RR		 1025 agg->frame_count, txq_id, idx);
1026
1027 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
6c6a22e2
SG		 1028 if (!hdr) {
1029 IWL_ERR(priv,
1030 "BUG_ON idx doesn't point to valid skb"
1031 " idx=%d, txq_id=%d\n", idx, txq_id);
1032 return -1;
1033 }
e532fa0e
RR		 1034
1035 sc = le16_to_cpu(hdr->seq_ctrl);
1036 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
15b1687c
WT		 1037 IWL_ERR(priv,
1038 "BUG_ON idx doesn't match seq control"
1039 " idx=%d, seq_idx=%d, seq=%d\n",
e532fa0e
RR		 1040 idx, SEQ_TO_SN(sc),
1041 hdr->seq_ctrl);
1042 return -1;
1043 }
1044
e1623446 1045 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
e532fa0e
RR		 1046 i, idx, SEQ_TO_SN(sc));
1047
1048 sh = idx - start;
1049 if (sh > 64) {
1050 sh = (start - idx) + 0xff;
1051 bitmap = bitmap << sh;
1052 sh = 0;
1053 start = idx;
1054 } else if (sh < -64)
1055 sh = 0xff - (start - idx);
1056 else if (sh < 0) {
1057 sh = start - idx;
1058 start = idx;
1059 bitmap = bitmap << sh;
1060 sh = 0;
1061 }
4aa41f12 1062 bitmap |= 1ULL << sh;
e1623446 1063 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
4aa41f12 1064 start, (unsigned long long)bitmap);
e532fa0e
RR		 1065 }
1066
1067 agg->bitmap = bitmap;
1068 agg->start_idx = start;
e1623446 1069 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
e532fa0e
RR		 1070 agg->frame_count, agg->start_idx,
1071 (unsigned long long)agg->bitmap);
1072
1073 if (bitmap)
1074 agg->wait_for_ba = 1;
1075 }
1076 return 0;
1077}
1078
1079static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1080 struct iwl_rx_mem_buffer *rxb)
1081{
2f301227 1082 struct iwl_rx_packet *pkt = rxb_addr(rxb);
e532fa0e
RR		 1083 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1084 int txq_id = SEQ_TO_QUEUE(sequence);
1085 int index = SEQ_TO_INDEX(sequence);
1086 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1087 struct ieee80211_tx_info *info;
1088 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1089 u32 status = le16_to_cpu(tx_resp->status.status);
3fd07a1e
TW		 1090 int tid;
1091 int sta_id;
1092 int freed;
e532fa0e
RR		 1093
1094 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 1095 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
e532fa0e
RR		 1096 "is out of range [0-%d] %d %d\n", txq_id,
1097 index, txq->q.n_bd, txq->q.write_ptr,
1098 txq->q.read_ptr);
1099 return;
1100 }
1101
1102 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1103 memset(&info->status, 0, sizeof(info->status));
1104
3fd07a1e
TW		 1105 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1106 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
e532fa0e
RR		 1107
1108 if (txq->sched_retry) {
1109 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1110 struct iwl_ht_agg *agg = NULL;
1111
e532fa0e
RR		 1112 agg = &priv->stations[sta_id].tid[tid].agg;
1113
25a6572c 1114 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
e532fa0e 1115
3235427e
RR		 1116 /* check if BAR is needed */
1117 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1118 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
e532fa0e
RR		 1119
1120 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
e532fa0e 1121 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
e1623446 1122 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
3fd07a1e
TW		 1123 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1124 scd_ssn , index, txq_id, txq->swq_id);
1125
17b88929 1126 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
e532fa0e
RR		 1127 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1128
3fd07a1e
TW		 1129 if (priv->mac80211_registered &&
1130 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1131 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
e532fa0e 1132 if (agg->state == IWL_AGG_OFF)
e4e72fb4 1133 iwl_wake_queue(priv, txq_id);
e532fa0e 1134 else
e4e72fb4 1135 iwl_wake_queue(priv, txq->swq_id);
e532fa0e 1136 }
e532fa0e
RR		 1137 }
1138 } else {
3fd07a1e
TW		 1139 BUG_ON(txq_id != txq->swq_id);
1140
e6a9854b 1141 info->status.rates[0].count = tx_resp->failure_frame + 1;
c397bf15 1142 info->flags |= iwl_tx_status_to_mac80211(status);
e7d326ac 1143 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 1144 le32_to_cpu(tx_resp->rate_n_flags),
1145 info);
1146
e1623446 1147 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
3fd07a1e
TW		 1148 "0x%x retries %d\n",
1149 txq_id,
1150 iwl_get_tx_fail_reason(status), status,
1151 le32_to_cpu(tx_resp->rate_n_flags),
1152 tx_resp->failure_frame);
4f85f5b3 1153
3fd07a1e
TW		 1154 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1155 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
e532fa0e 1156 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
3fd07a1e
TW		 1157
1158 if (priv->mac80211_registered &&
1159 (iwl_queue_space(&txq->q) > txq->q.low_mark))
e4e72fb4 1160 iwl_wake_queue(priv, txq_id);
e532fa0e 1161 }
e532fa0e 1162
3fd07a1e
TW		 1163 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1164 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1165
e532fa0e 1166 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 1167 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
e532fa0e
RR		 1168}
1169
a96a27f9 1170/* Currently 5000 is the superset of everything */
e8c00dcb 1171u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
c1adf9fb
GG		 1172{
1173 return len;
1174}
1175
672639de 1176void iwl5000_setup_deferred_work(struct iwl_priv *priv)
203566f3
EG		 1177{
1178 /* in 5000 the tx power calibration is done in uCode */
1179 priv->disable_tx_power_cal = 1;
1180}
1181
672639de 1182void iwl5000_rx_handler_setup(struct iwl_priv *priv)
b600e4e1 1183{
7c616cba
TW		 1184 /* init calibration handlers */
1185 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1186 iwl5000_rx_calib_result;
1187 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1188 iwl5000_rx_calib_complete;
e532fa0e 1189 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
b600e4e1
RR		 1190}
1191
7c616cba 1192
672639de 1193int iwl5000_hw_valid_rtc_data_addr(u32 addr)
87283cc1 1194{
250bdd21 1195 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
87283cc1
RR		 1196 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1197}
1198
fe7a90c2
RR		 1199static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1200{
1201 int ret = 0;
1202 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1203 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1204 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1205
1206 if ((rxon1->flags == rxon2->flags) &&
1207 (rxon1->filter_flags == rxon2->filter_flags) &&
1208 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1209 (rxon1->ofdm_ht_single_stream_basic_rates ==
1210 rxon2->ofdm_ht_single_stream_basic_rates) &&
1211 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1212 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1213 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1214 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1215 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1216 (rxon1->rx_chain == rxon2->rx_chain) &&
1217 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
e1623446 1218 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
fe7a90c2
RR		 1219 return 0;
1220 }
1221
1222 rxon_assoc.flags = priv->staging_rxon.flags;
1223 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1224 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1225 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1226 rxon_assoc.reserved1 = 0;
1227 rxon_assoc.reserved2 = 0;
1228 rxon_assoc.reserved3 = 0;
1229 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1230 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1231 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1232 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1233 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1234 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1235 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1236 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1237
1238 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1239 sizeof(rxon_assoc), &rxon_assoc, NULL);
1240 if (ret)
1241 return ret;
1242
1243 return ret;
1244}
672639de 1245int iwl5000_send_tx_power(struct iwl_priv *priv)
630fe9b6
TW		 1246{
1247 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
76a2407a 1248 u8 tx_ant_cfg_cmd;
630fe9b6
TW		 1249
1250 /* half dBm need to multiply */
1251 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
ae16fc3c
WYG		 1252
1253 if (priv->tx_power_lmt_in_half_dbm &&
1254 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
1255 /*
1256 * For the newer devices which using enhanced/extend tx power
1257 * table in EEPROM, the format is in half dBm. driver need to
1258 * convert to dBm format before report to mac80211.
1259 * By doing so, there is a possibility of 1/2 dBm resolution
1260 * lost. driver will perform "round-up" operation before
1261 * reporting, but it will cause 1/2 dBm tx power over the
1262 * regulatory limit. Perform the checking here, if the
1263 * "tx_power_user_lmt" is higher than EEPROM value (in
1264 * half-dBm format), lower the tx power based on EEPROM
1265 */
1266 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
1267 }
853554ac 1268 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
630fe9b6 1269 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
76a2407a
JS		 1270
1271 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1272 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1273 else
1274 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1275
1276 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
630fe9b6
TW		 1277 sizeof(tx_power_cmd), &tx_power_cmd,
1278 NULL);
1279}
1280
672639de 1281void iwl5000_temperature(struct iwl_priv *priv)
8f91aecb
EG		 1282{
1283 /* store temperature from statistics (in Celsius) */
5225640b 1284 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
39b73fb1 1285 iwl_tt_handler(priv);
8f91aecb 1286}
fe7a90c2 1287
62161aef
WYG		 1288static void iwl5150_temperature(struct iwl_priv *priv)
1289{
1290 u32 vt = 0;
1291 s32 offset = iwl_temp_calib_to_offset(priv);
1292
1293 vt = le32_to_cpu(priv->statistics.general.temperature);
1294 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1295 /* now vt hold the temperature in Kelvin */
1296 priv->temperature = KELVIN_TO_CELSIUS(vt);
15993e08 1297 iwl_tt_handler(priv);
62161aef
WYG		 1298}
1299
caab8f1a 1300/* Calc max signal level (dBm) among 3 possible receivers */
e8c00dcb 1301int iwl5000_calc_rssi(struct iwl_priv *priv,
caab8f1a
TW		 1302 struct iwl_rx_phy_res *rx_resp)
1303{
1304 /* data from PHY/DSP regarding signal strength, etc.,
1305 * contents are always there, not configurable by host
1306 */
1307 struct iwl5000_non_cfg_phy *ncphy =
1308 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1309 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1310 u8 agc;
1311
1312 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1313 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1314
1315 /* Find max rssi among 3 possible receivers.
1316 * These values are measured by the digital signal processor (DSP).
1317 * They should stay fairly constant even as the signal strength varies,
1318 * if the radio's automatic gain control (AGC) is working right.
1319 * AGC value (see below) will provide the "interesting" info.
1320 */
1321 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1322 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1323 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1324 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1325 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1326
1327 max_rssi = max_t(u32, rssi_a, rssi_b);
1328 max_rssi = max_t(u32, max_rssi, rssi_c);
1329
e1623446 1330 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
caab8f1a
TW		 1331 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1332
1333 /* dBm = max_rssi dB - agc dB - constant.
1334 * Higher AGC (higher radio gain) means lower signal. */
250bdd21 1335 return max_rssi - agc - IWL49_RSSI_OFFSET;
caab8f1a
TW		 1336}
1337
2f748dec
WYG		 1338static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1339{
1340 struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1341 .valid = cpu_to_le32(valid_tx_ant),
1342 };
1343
1344 if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1345 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1346 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1347 sizeof(struct iwl_tx_ant_config_cmd),
1348 &tx_ant_cmd);
1349 } else {
1350 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1351 return -EOPNOTSUPP;
1352 }
1353}
1354
1355
cc0f555d
JS		 1356#define IWL5000_UCODE_GET(item) \
1357static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1358 u32 api_ver) \
1359{ \
1360 if (api_ver <= 2) \
1361 return le32_to_cpu(ucode->u.v1.item); \
1362 return le32_to_cpu(ucode->u.v2.item); \
1363}
1364
1365static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1366{
1367 if (api_ver <= 2)
1368 return UCODE_HEADER_SIZE(1);
1369 return UCODE_HEADER_SIZE(2);
1370}
1371
1372static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1373 u32 api_ver)
1374{
1375 if (api_ver <= 2)
1376 return 0;
1377 return le32_to_cpu(ucode->u.v2.build);
1378}
1379
1380static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1381 u32 api_ver)
1382{
1383 if (api_ver <= 2)
1384 return (u8 *) ucode->u.v1.data;
1385 return (u8 *) ucode->u.v2.data;
1386}
1387
1388IWL5000_UCODE_GET(inst_size);
1389IWL5000_UCODE_GET(data_size);
1390IWL5000_UCODE_GET(init_size);
1391IWL5000_UCODE_GET(init_data_size);
1392IWL5000_UCODE_GET(boot_size);
1393
4a56e965
WYG		 1394static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1395{
1396 struct iwl5000_channel_switch_cmd cmd;
1397 const struct iwl_channel_info *ch_info;
1398 struct iwl_host_cmd hcmd = {
1399 .id = REPLY_CHANNEL_SWITCH,
1400 .len = sizeof(cmd),
1401 .flags = CMD_SIZE_HUGE,
1402 .data = &cmd,
1403 };
1404
1405 IWL_DEBUG_11H(priv, "channel switch from %d to %d\n",
1406 priv->active_rxon.channel, channel);
1407 cmd.band = priv->band == IEEE80211_BAND_2GHZ;
1408 cmd.channel = cpu_to_le16(channel);
0924e519
WYG		 1409 cmd.rxon_flags = priv->staging_rxon.flags;
1410 cmd.rxon_filter_flags = priv->staging_rxon.filter_flags;
4a56e965
WYG		 1411 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1412 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1413 if (ch_info)
1414 cmd.expect_beacon = is_channel_radar(ch_info);
1415 else {
1416 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
1417 priv->active_rxon.channel, channel);
1418 return -EFAULT;
1419 }
0924e519
WYG		 1420 priv->switch_rxon.channel = cpu_to_le16(channel);
1421 priv->switch_rxon.switch_in_progress = true;
4a56e965
WYG		 1422
1423 return iwl_send_cmd_sync(priv, &hcmd);
1424}
1425
e8c00dcb 1426struct iwl_hcmd_ops iwl5000_hcmd = {
fe7a90c2 1427 .rxon_assoc = iwl5000_send_rxon_assoc,
e0158e61 1428 .commit_rxon = iwl_commit_rxon,
45823531 1429 .set_rxon_chain = iwl_set_rxon_chain,
2f748dec 1430 .set_tx_ant = iwl5000_send_tx_ant_config,
da8dec29
TW		 1431};
1432
e8c00dcb 1433struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
c1adf9fb 1434 .get_hcmd_size = iwl5000_get_hcmd_size,
2469bf2e 1435 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
33fd5033
EG		 1436 .gain_computation = iwl5000_gain_computation,
1437 .chain_noise_reset = iwl5000_chain_noise_reset,
a326a5d0 1438 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
caab8f1a 1439 .calc_rssi = iwl5000_calc_rssi,
da8dec29
TW		 1440};
1441
cc0f555d
JS		 1442struct iwl_ucode_ops iwl5000_ucode = {
1443 .get_header_size = iwl5000_ucode_get_header_size,
1444 .get_build = iwl5000_ucode_get_build,
1445 .get_inst_size = iwl5000_ucode_get_inst_size,
1446 .get_data_size = iwl5000_ucode_get_data_size,
1447 .get_init_size = iwl5000_ucode_get_init_size,
1448 .get_init_data_size = iwl5000_ucode_get_init_data_size,
1449 .get_boot_size = iwl5000_ucode_get_boot_size,
1450 .get_data = iwl5000_ucode_get_data,
1451};
1452
e8c00dcb 1453struct iwl_lib_ops iwl5000_lib = {
fdd3e8a4 1454 .set_hw_params = iwl5000_hw_set_hw_params,
7839fc03 1455 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
972cf447 1456 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
da1bc453 1457 .txq_set_sched = iwl5000_txq_set_sched,
e26e47d9
TW		 1458 .txq_agg_enable = iwl5000_txq_agg_enable,
1459 .txq_agg_disable = iwl5000_txq_agg_disable,
7aaa1d79
SO		 1460 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1461 .txq_free_tfd = iwl_hw_txq_free_tfd,
a8e74e27 1462 .txq_init = iwl_hw_tx_queue_init,
b600e4e1 1463 .rx_handler_setup = iwl5000_rx_handler_setup,
203566f3 1464 .setup_deferred_work = iwl5000_setup_deferred_work,
87283cc1 1465 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
b7a79404
RC		 1466 .dump_nic_event_log = iwl_dump_nic_event_log,
1467 .dump_nic_error_log = iwl_dump_nic_error_log,
696bdee3 1468 .dump_csr = iwl_dump_csr,
dbb983b7 1469 .load_ucode = iwl5000_load_ucode,
99da1b48
RR		 1470 .init_alive_start = iwl5000_init_alive_start,
1471 .alive_notify = iwl5000_alive_notify,
630fe9b6 1472 .send_tx_power = iwl5000_send_tx_power,
5b9f8cd3 1473 .update_chain_flags = iwl_update_chain_flags,
4a56e965 1474 .set_channel_switch = iwl5000_hw_channel_switch,
30d59260 1475 .apm_ops = {
fadb3582 1476 .init = iwl_apm_init,
d68b603c 1477 .stop = iwl_apm_stop,
5a835353 1478 .config = iwl5000_nic_config,
5b9f8cd3 1479 .set_pwr_src = iwl_set_pwr_src,
30d59260 1480 },
da8dec29 1481 .eeprom_ops = {
25ae3986
TW		 1482 .regulatory_bands = {
1483 EEPROM_5000_REG_BAND_1_CHANNELS,
1484 EEPROM_5000_REG_BAND_2_CHANNELS,
1485 EEPROM_5000_REG_BAND_3_CHANNELS,
1486 EEPROM_5000_REG_BAND_4_CHANNELS,
1487 EEPROM_5000_REG_BAND_5_CHANNELS,
7aafef1c
WYG		 1488 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1489 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
25ae3986 1490 },
da8dec29
TW		 1491 .verify_signature = iwlcore_eeprom_verify_signature,
1492 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1493 .release_semaphore = iwlcore_eeprom_release_semaphore,
0ef2ca67 1494 .calib_version = iwl5000_eeprom_calib_version,
25ae3986 1495 .query_addr = iwl5000_eeprom_query_addr,
da8dec29 1496 },
5bbe233b 1497 .post_associate = iwl_post_associate,
ef850d7c 1498 .isr = iwl_isr_ict,
60690a6a 1499 .config_ap = iwl_config_ap,
62161aef
WYG		 1500 .temp_ops = {
1501 .temperature = iwl5000_temperature,
1502 .set_ct_kill = iwl5000_set_ct_threshold,
1503 },
1504};
1505
1506static struct iwl_lib_ops iwl5150_lib = {
1507 .set_hw_params = iwl5000_hw_set_hw_params,
1508 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1509 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1510 .txq_set_sched = iwl5000_txq_set_sched,
1511 .txq_agg_enable = iwl5000_txq_agg_enable,
1512 .txq_agg_disable = iwl5000_txq_agg_disable,
1513 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1514 .txq_free_tfd = iwl_hw_txq_free_tfd,
1515 .txq_init = iwl_hw_tx_queue_init,
1516 .rx_handler_setup = iwl5000_rx_handler_setup,
1517 .setup_deferred_work = iwl5000_setup_deferred_work,
1518 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
b7a79404
RC		 1519 .dump_nic_event_log = iwl_dump_nic_event_log,
1520 .dump_nic_error_log = iwl_dump_nic_error_log,
696bdee3 1521 .dump_csr = iwl_dump_csr,
62161aef
WYG		 1522 .load_ucode = iwl5000_load_ucode,
1523 .init_alive_start = iwl5000_init_alive_start,
1524 .alive_notify = iwl5000_alive_notify,
1525 .send_tx_power = iwl5000_send_tx_power,
1526 .update_chain_flags = iwl_update_chain_flags,
4a56e965 1527 .set_channel_switch = iwl5000_hw_channel_switch,
62161aef 1528 .apm_ops = {
fadb3582 1529 .init = iwl_apm_init,
d68b603c 1530 .stop = iwl_apm_stop,
62161aef
WYG		 1531 .config = iwl5000_nic_config,
1532 .set_pwr_src = iwl_set_pwr_src,
1533 },
1534 .eeprom_ops = {
1535 .regulatory_bands = {
1536 EEPROM_5000_REG_BAND_1_CHANNELS,
1537 EEPROM_5000_REG_BAND_2_CHANNELS,
1538 EEPROM_5000_REG_BAND_3_CHANNELS,
1539 EEPROM_5000_REG_BAND_4_CHANNELS,
1540 EEPROM_5000_REG_BAND_5_CHANNELS,
7aafef1c
WYG		 1541 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1542 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
62161aef
WYG		 1543 },
1544 .verify_signature = iwlcore_eeprom_verify_signature,
1545 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1546 .release_semaphore = iwlcore_eeprom_release_semaphore,
1547 .calib_version = iwl5000_eeprom_calib_version,
1548 .query_addr = iwl5000_eeprom_query_addr,
1549 },
1550 .post_associate = iwl_post_associate,
ef850d7c 1551 .isr = iwl_isr_ict,
62161aef
WYG		 1552 .config_ap = iwl_config_ap,
1553 .temp_ops = {
1554 .temperature = iwl5150_temperature,
1555 .set_ct_kill = iwl5150_set_ct_threshold,
1556 },
da8dec29
TW		 1557};
1558
e932a609 1559static struct iwl_ops iwl5000_ops = {
cc0f555d 1560 .ucode = &iwl5000_ucode,
da8dec29
TW		 1561 .lib = &iwl5000_lib,
1562 .hcmd = &iwl5000_hcmd,
1563 .utils = &iwl5000_hcmd_utils,
e932a609 1564 .led = &iwlagn_led_ops,
da8dec29
TW		 1565};
1566
62161aef 1567static struct iwl_ops iwl5150_ops = {
cc0f555d 1568 .ucode = &iwl5000_ucode,
62161aef
WYG		 1569 .lib = &iwl5150_lib,
1570 .hcmd = &iwl5000_hcmd,
1571 .utils = &iwl5000_hcmd_utils,
e932a609 1572 .led = &iwlagn_led_ops,
62161aef
WYG		 1573};
1574
cec2d3f3 1575struct iwl_mod_params iwl50_mod_params = {
5a6a256e 1576 .amsdu_size_8K = 1,
3a1081e8 1577 .restart_fw = 1,
5a6a256e
TW		 1578 /* the rest are 0 by default */
1579};
1580
1581
1582struct iwl_cfg iwl5300_agn_cfg = {
1583 .name = "5300AGN",
a0987a8d
RC		 1584 .fw_name_pre = IWL5000_FW_PRE,
1585 .ucode_api_max = IWL5000_UCODE_API_MAX,
1586 .ucode_api_min = IWL5000_UCODE_API_MIN,
5a6a256e 1587 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1588 .ops = &iwl5000_ops,
25ae3986 1589 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1590 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1591 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
88804e2b
WYG		 1592 .num_of_queues = IWL50_NUM_QUEUES,
1593 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e 1594 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1595 .valid_tx_ant = ANT_ABC,
1596 .valid_rx_ant = ANT_ABC,
fadb3582
BC		 1597 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1598 .set_l0s = true,
1599 .use_bsm = false,
b261793d 1600 .ht_greenfield_support = true,
f2d0d0e2 1601 .led_compensation = 51,
d8c07e7a 1602 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
5a6a256e
TW		 1603};
1604
ac592574
WYG		 1605struct iwl_cfg iwl5100_bgn_cfg = {
1606 .name = "5100BGN",
a0987a8d
RC		 1607 .fw_name_pre = IWL5000_FW_PRE,
1608 .ucode_api_max = IWL5000_UCODE_API_MAX,
1609 .ucode_api_min = IWL5000_UCODE_API_MIN,
ac592574 1610 .sku = IWL_SKU_G|IWL_SKU_N,
47408639
EK		 1611 .ops = &iwl5000_ops,
1612 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1613 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1614 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
88804e2b
WYG		 1615 .num_of_queues = IWL50_NUM_QUEUES,
1616 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
47408639 1617 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1618 .valid_tx_ant = ANT_B,
1619 .valid_rx_ant = ANT_AB,
fadb3582
BC		 1620 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1621 .set_l0s = true,
1622 .use_bsm = false,
b261793d 1623 .ht_greenfield_support = true,
f2d0d0e2 1624 .led_compensation = 51,
d8c07e7a 1625 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
47408639
EK		 1626};
1627
1628struct iwl_cfg iwl5100_abg_cfg = {
1629 .name = "5100ABG",
a0987a8d
RC		 1630 .fw_name_pre = IWL5000_FW_PRE,
1631 .ucode_api_max = IWL5000_UCODE_API_MAX,
1632 .ucode_api_min = IWL5000_UCODE_API_MIN,
47408639
EK		 1633 .sku = IWL_SKU_A|IWL_SKU_G,
1634 .ops = &iwl5000_ops,
1635 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1636 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1637 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
88804e2b
WYG		 1638 .num_of_queues = IWL50_NUM_QUEUES,
1639 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
47408639 1640 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1641 .valid_tx_ant = ANT_B,
1642 .valid_rx_ant = ANT_AB,
fadb3582
BC		 1643 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1644 .set_l0s = true,
1645 .use_bsm = false,
f2d0d0e2 1646 .led_compensation = 51,
d8c07e7a 1647 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
47408639
EK		 1648};
1649
5a6a256e
TW		 1650struct iwl_cfg iwl5100_agn_cfg = {
1651 .name = "5100AGN",
a0987a8d
RC		 1652 .fw_name_pre = IWL5000_FW_PRE,
1653 .ucode_api_max = IWL5000_UCODE_API_MAX,
1654 .ucode_api_min = IWL5000_UCODE_API_MIN,
5a6a256e 1655 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1656 .ops = &iwl5000_ops,
25ae3986 1657 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1658 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1659 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
88804e2b
WYG		 1660 .num_of_queues = IWL50_NUM_QUEUES,
1661 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e 1662 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1663 .valid_tx_ant = ANT_B,
1664 .valid_rx_ant = ANT_AB,
fadb3582
BC		 1665 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1666 .set_l0s = true,
1667 .use_bsm = false,
b261793d 1668 .ht_greenfield_support = true,
f2d0d0e2 1669 .led_compensation = 51,
d8c07e7a 1670 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
5a6a256e
TW		 1671};
1672
1673struct iwl_cfg iwl5350_agn_cfg = {
1674 .name = "5350AGN",
a0987a8d
RC		 1675 .fw_name_pre = IWL5000_FW_PRE,
1676 .ucode_api_max = IWL5000_UCODE_API_MAX,
1677 .ucode_api_min = IWL5000_UCODE_API_MIN,
5a6a256e 1678 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1679 .ops = &iwl5000_ops,
25ae3986 1680 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1681 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1682 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
88804e2b
WYG		 1683 .num_of_queues = IWL50_NUM_QUEUES,
1684 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e 1685 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1686 .valid_tx_ant = ANT_ABC,
1687 .valid_rx_ant = ANT_ABC,
fadb3582
BC		 1688 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1689 .set_l0s = true,
1690 .use_bsm = false,
b261793d 1691 .ht_greenfield_support = true,
f2d0d0e2 1692 .led_compensation = 51,
d8c07e7a 1693 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
5a6a256e
TW		 1694};
1695
7100e924
TW		 1696struct iwl_cfg iwl5150_agn_cfg = {
1697 .name = "5150AGN",
a0987a8d
RC		 1698 .fw_name_pre = IWL5150_FW_PRE,
1699 .ucode_api_max = IWL5150_UCODE_API_MAX,
1700 .ucode_api_min = IWL5150_UCODE_API_MIN,
7100e924 1701 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
62161aef 1702 .ops = &iwl5150_ops,
7100e924 1703 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
fd63edba
TW		 1704 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1705 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
88804e2b
WYG		 1706 .num_of_queues = IWL50_NUM_QUEUES,
1707 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
7100e924 1708 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1709 .valid_tx_ant = ANT_A,
1710 .valid_rx_ant = ANT_AB,
fadb3582
BC		 1711 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1712 .set_l0s = true,
1713 .use_bsm = false,
b261793d 1714 .ht_greenfield_support = true,
f2d0d0e2 1715 .led_compensation = 51,
d8c07e7a 1716 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
7100e924
TW		 1717};
1718
ac592574
WYG		 1719struct iwl_cfg iwl5150_abg_cfg = {
1720 .name = "5150ABG",
1721 .fw_name_pre = IWL5150_FW_PRE,
1722 .ucode_api_max = IWL5150_UCODE_API_MAX,
1723 .ucode_api_min = IWL5150_UCODE_API_MIN,
1724 .sku = IWL_SKU_A|IWL_SKU_G,
1725 .ops = &iwl5150_ops,
1726 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1727 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1728 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1729 .num_of_queues = IWL50_NUM_QUEUES,
1730 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1731 .mod_params = &iwl50_mod_params,
1732 .valid_tx_ant = ANT_A,
1733 .valid_rx_ant = ANT_AB,
1734 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1735 .set_l0s = true,
1736 .use_bsm = false,
1737 .led_compensation = 51,
1738 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
7100e924
TW		 1739};
1740
a0987a8d
RC		 1741MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1742MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
c9f79ed2 1743
4e30cb69 1744module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
5a6a256e
TW		 1745MODULE_PARM_DESC(swcrypto50,
1746 "using software crypto engine (default 0 [hardware])\n");
4e30cb69 1747module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
5a6a256e 1748MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
4e30cb69 1749module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
49779293 1750MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
4e30cb69
WYG		 1751module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1752 int, S_IRUGO);
5a6a256e 1753MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
4e30cb69 1754module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
3a1081e8 1755MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
Linux kernel - Deliverables
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