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iwlwifi: move plcp check to separated function
[deliverable/linux.git] / drivers / net / wireless / iwlwifi / iwl-5000.c
CommitLineData
5a6a256e
TW		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
5a6a256e
TW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 *
24 *****************************************************************************/
25
26#include <linux/kernel.h>
27#include <linux/module.h>
5a6a256e
TW		 28#include <linux/init.h>
29#include <linux/pci.h>
30#include <linux/dma-mapping.h>
31#include <linux/delay.h>
d43c36dc 32#include <linux/sched.h>
5a6a256e
TW		 33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <net/mac80211.h>
37#include <linux/etherdevice.h>
38#include <asm/unaligned.h>
39
40#include "iwl-eeprom.h"
3e0d4cb1 41#include "iwl-dev.h"
5a6a256e
TW		 42#include "iwl-core.h"
43#include "iwl-io.h"
e26e47d9 44#include "iwl-sta.h"
5a6a256e 45#include "iwl-helpers.h"
a1175124 46#include "iwl-agn.h"
e932a609 47#include "iwl-agn-led.h"
5a6a256e 48#include "iwl-5000-hw.h"
c0bac76a 49#include "iwl-6000-hw.h"
5a6a256e 50
a0987a8d 51/* Highest firmware API version supported */
c9d2fbf3 52#define IWL5000_UCODE_API_MAX 2
39e6d225 53#define IWL5150_UCODE_API_MAX 2
5a6a256e 54
a0987a8d
RC		 55/* Lowest firmware API version supported */
56#define IWL5000_UCODE_API_MIN 1
57#define IWL5150_UCODE_API_MIN 1
58
59#define IWL5000_FW_PRE "iwlwifi-5000-"
60#define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
61#define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
62
63#define IWL5150_FW_PRE "iwlwifi-5150-"
64#define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
65#define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
4e062f99 66
edc1a3a0
JB		 67static const s8 iwl5000_default_queue_to_tx_fifo[] = {
68 IWL_TX_FIFO_VO,
69 IWL_TX_FIFO_VI,
70 IWL_TX_FIFO_BE,
71 IWL_TX_FIFO_BK,
99da1b48 72 IWL50_CMD_FIFO_NUM,
edc1a3a0
JB		 73 IWL_TX_FIFO_UNUSED,
74 IWL_TX_FIFO_UNUSED,
75 IWL_TX_FIFO_UNUSED,
76 IWL_TX_FIFO_UNUSED,
77 IWL_TX_FIFO_UNUSED,
99da1b48
RR		 78};
79
9371d4ed 80/* NIC configuration for 5000 series */
672639de 81void iwl5000_nic_config(struct iwl_priv *priv)
e86fe9f6
TW		 82{
83 unsigned long flags;
84 u16 radio_cfg;
e86fe9f6
TW		 85
86 spin_lock_irqsave(&priv->lock, flags);
87
e86fe9f6
TW		 88 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
89
90 /* write radio config values to register */
9371d4ed 91 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
e86fe9f6
TW		 92 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
93 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
94 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
95 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
96
97 /* set CSR_HW_CONFIG_REG for uCode use */
98 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
99 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
100 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
101
4c43e0d0
TW		 102 /* W/A : NIC is stuck in a reset state after Early PCIe power off
103 * (PCIe power is lost before PERST# is asserted),
104 * causing ME FW to lose ownership and not being able to obtain it back.
105 */
2d3db679 106 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
4c43e0d0
TW		 107 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
108 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
109
02c06e4a 110
e86fe9f6
TW		 111 spin_unlock_irqrestore(&priv->lock, flags);
112}
113
114
25ae3986
TW		 115/*
116 * EEPROM
117 */
118static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
119{
120 u16 offset = 0;
121
122 if ((address & INDIRECT_ADDRESS) == 0)
123 return address;
124
125 switch (address & INDIRECT_TYPE_MSK) {
126 case INDIRECT_HOST:
127 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
128 break;
129 case INDIRECT_GENERAL:
130 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
131 break;
132 case INDIRECT_REGULATORY:
133 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
134 break;
135 case INDIRECT_CALIBRATION:
136 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
137 break;
138 case INDIRECT_PROCESS_ADJST:
139 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
140 break;
141 case INDIRECT_OTHERS:
142 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
143 break;
144 default:
15b1687c 145 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
25ae3986
TW		 146 address & INDIRECT_TYPE_MSK);
147 break;
148 }
149
150 /* translate the offset from words to byte */
151 return (address & ADDRESS_MSK) + (offset << 1);
152}
153
672639de 154u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
f1f69415 155{
f1f69415
TW		 156 struct iwl_eeprom_calib_hdr {
157 u8 version;
158 u8 pa_type;
159 u16 voltage;
160 } *hdr;
161
f1f69415
TW		 162 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
163 EEPROM_5000_CALIB_ALL);
0ef2ca67 164 return hdr->version;
f1f69415
TW		 165
166}
167
33fd5033
EG		 168static void iwl5000_gain_computation(struct iwl_priv *priv,
169 u32 average_noise[NUM_RX_CHAINS],
170 u16 min_average_noise_antenna_i,
d8c07e7a
WYG		 171 u32 min_average_noise,
172 u8 default_chain)
33fd5033
EG		 173{
174 int i;
175 s32 delta_g;
176 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
177
d8c07e7a
WYG		 178 /*
179 * Find Gain Code for the chains based on "default chain"
180 */
181 for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
33fd5033
EG		 182 if ((data->disconn_array[i])) {
183 data->delta_gain_code[i] = 0;
184 continue;
185 }
d4fe5ac9
BC		 186
187 delta_g = (priv->cfg->chain_noise_scale *
188 ((s32)average_noise[default_chain] -
33fd5033 189 (s32)average_noise[i])) / 1500;
d4fe5ac9 190
33fd5033
EG		 191 /* bound gain by 2 bits value max, 3rd bit is sign */
192 data->delta_gain_code[i] =
886e71de 193 min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
33fd5033
EG		 194
195 if (delta_g < 0)
d4fe5ac9
BC		 196 /*
197 * set negative sign ...
198 * note to Intel developers: This is uCode API format,
199 * not the format of any internal device registers.
200 * Do not change this format for e.g. 6050 or similar
201 * devices. Change format only if more resolution
202 * (i.e. more than 2 bits magnitude) is needed.
203 */
33fd5033
EG		 204 data->delta_gain_code[i] |= (1 << 2);
205 }
206
e1623446 207 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
33fd5033
EG		 208 data->delta_gain_code[1], data->delta_gain_code[2]);
209
210 if (!data->radio_write) {
f69f42a6 211 struct iwl_calib_chain_noise_gain_cmd cmd;
0d950d84 212
33fd5033
EG		 213 memset(&cmd, 0, sizeof(cmd));
214
0d950d84
TW		 215 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
216 cmd.hdr.first_group = 0;
217 cmd.hdr.groups_num = 1;
218 cmd.hdr.data_valid = 1;
33fd5033
EG		 219 cmd.delta_gain_1 = data->delta_gain_code[1];
220 cmd.delta_gain_2 = data->delta_gain_code[2];
221 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
222 sizeof(cmd), &cmd, NULL);
223
224 data->radio_write = 1;
225 data->state = IWL_CHAIN_NOISE_CALIBRATED;
226 }
227
228 data->chain_noise_a = 0;
229 data->chain_noise_b = 0;
230 data->chain_noise_c = 0;
231 data->chain_signal_a = 0;
232 data->chain_signal_b = 0;
233 data->chain_signal_c = 0;
234 data->beacon_count = 0;
235}
236
237static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
238{
239 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
0d950d84 240 int ret;
33fd5033
EG		 241
242 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
f69f42a6 243 struct iwl_calib_chain_noise_reset_cmd cmd;
33fd5033 244 memset(&cmd, 0, sizeof(cmd));
0d950d84
TW		 245
246 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
247 cmd.hdr.first_group = 0;
248 cmd.hdr.groups_num = 1;
249 cmd.hdr.data_valid = 1;
250 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
251 sizeof(cmd), &cmd);
252 if (ret)
15b1687c
WT		 253 IWL_ERR(priv,
254 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
33fd5033 255 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
e1623446 256 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
33fd5033
EG		 257 }
258}
259
e8c00dcb 260void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
a326a5d0
EG		 261 __le32 *tx_flags)
262{
e6a9854b
JB		 263 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
264 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
a326a5d0
EG		 265 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
266 else
267 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
268}
269
33fd5033
EG		 270static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
271 .min_nrg_cck = 95,
fe6efb4b 272 .max_nrg_cck = 0, /* not used, set to 0 */
33fd5033
EG		 273 .auto_corr_min_ofdm = 90,
274 .auto_corr_min_ofdm_mrc = 170,
275 .auto_corr_min_ofdm_x1 = 120,
276 .auto_corr_min_ofdm_mrc_x1 = 240,
277
278 .auto_corr_max_ofdm = 120,
279 .auto_corr_max_ofdm_mrc = 210,
9bead763
WYG		 280 .auto_corr_max_ofdm_x1 = 120,
281 .auto_corr_max_ofdm_mrc_x1 = 240,
33fd5033
EG		 282
283 .auto_corr_min_cck = 125,
284 .auto_corr_max_cck = 200,
285 .auto_corr_min_cck_mrc = 170,
286 .auto_corr_max_cck_mrc = 400,
287 .nrg_th_cck = 95,
288 .nrg_th_ofdm = 95,
55036d66
WYG		 289
290 .barker_corr_th_min = 190,
291 .barker_corr_th_min_mrc = 390,
292 .nrg_th_cca = 62,
33fd5033
EG		 293};
294
9d67187d
WYG		 295static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
296 .min_nrg_cck = 95,
297 .max_nrg_cck = 0, /* not used, set to 0 */
298 .auto_corr_min_ofdm = 90,
299 .auto_corr_min_ofdm_mrc = 170,
300 .auto_corr_min_ofdm_x1 = 105,
301 .auto_corr_min_ofdm_mrc_x1 = 220,
302
303 .auto_corr_max_ofdm = 120,
304 .auto_corr_max_ofdm_mrc = 210,
305 /* max = min for performance bug in 5150 DSP */
306 .auto_corr_max_ofdm_x1 = 105,
307 .auto_corr_max_ofdm_mrc_x1 = 220,
308
309 .auto_corr_min_cck = 125,
310 .auto_corr_max_cck = 200,
311 .auto_corr_min_cck_mrc = 170,
312 .auto_corr_max_cck_mrc = 400,
313 .nrg_th_cck = 95,
314 .nrg_th_ofdm = 95,
55036d66
WYG		 315
316 .barker_corr_th_min = 190,
317 .barker_corr_th_min_mrc = 390,
318 .nrg_th_cca = 62,
9d67187d
WYG		 319};
320
672639de 321const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
25ae3986
TW		 322 size_t offset)
323{
324 u32 address = eeprom_indirect_address(priv, offset);
325 BUG_ON(address >= priv->cfg->eeprom_size);
326 return &priv->eeprom[address];
327}
328
62161aef 329static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
339afc89 330{
62161aef 331 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
672639de 332 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
62161aef
WYG		 333 iwl_temp_calib_to_offset(priv);
334
335 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
336}
337
338static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
339{
340 /* want Celsius */
672639de 341 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
339afc89
TW		 342}
343
7c616cba
TW		 344/*
345 * Calibration
346 */
be5d56ed 347static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
7c616cba 348{
0d950d84 349 struct iwl_calib_xtal_freq_cmd cmd;
b7bb1756
JB		 350 __le16 *xtal_calib =
351 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
7c616cba 352
0d950d84
TW		 353 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
354 cmd.hdr.first_group = 0;
355 cmd.hdr.groups_num = 1;
356 cmd.hdr.data_valid = 1;
b7bb1756
JB		 357 cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
358 cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
f69f42a6 359 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
0d950d84 360 (u8 *)&cmd, sizeof(cmd));
7c616cba
TW		 361}
362
7c616cba
TW		 363static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
364{
f69f42a6 365 struct iwl_calib_cfg_cmd calib_cfg_cmd;
7c616cba
TW		 366 struct iwl_host_cmd cmd = {
367 .id = CALIBRATION_CFG_CMD,
f69f42a6 368 .len = sizeof(struct iwl_calib_cfg_cmd),
7c616cba
TW		 369 .data = &calib_cfg_cmd,
370 };
371
372 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
373 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
374 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
375 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
376 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
377
378 return iwl_send_cmd(priv, &cmd);
379}
380
381static void iwl5000_rx_calib_result(struct iwl_priv *priv,
382 struct iwl_rx_mem_buffer *rxb)
383{
2f301227 384 struct iwl_rx_packet *pkt = rxb_addr(rxb);
f69f42a6 385 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
396887a2 386 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
6e21f2c1 387 int index;
7c616cba
TW		 388
389 /* reduce the size of the length field itself */
390 len -= 4;
391
6e21f2c1
TW		 392 /* Define the order in which the results will be sent to the runtime
393 * uCode. iwl_send_calib_results sends them in a row according to their
394 * index. We sort them here */
7c616cba 395 switch (hdr->op_code) {
819500c5
TW		 396 case IWL_PHY_CALIBRATE_DC_CMD:
397 index = IWL_CALIB_DC;
398 break;
f69f42a6
TW		 399 case IWL_PHY_CALIBRATE_LO_CMD:
400 index = IWL_CALIB_LO;
7c616cba 401 break;
f69f42a6
TW		 402 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
403 index = IWL_CALIB_TX_IQ;
7c616cba 404 break;
f69f42a6
TW		 405 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
406 index = IWL_CALIB_TX_IQ_PERD;
7c616cba 407 break;
201706ac
TW		 408 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
409 index = IWL_CALIB_BASE_BAND;
410 break;
7c616cba 411 default:
15b1687c 412 IWL_ERR(priv, "Unknown calibration notification %d\n",
7c616cba
TW		 413 hdr->op_code);
414 return;
415 }
6e21f2c1 416 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
7c616cba
TW		 417}
418
419static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
420 struct iwl_rx_mem_buffer *rxb)
421{
e1623446 422 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
7c616cba
TW		 423 queue_work(priv->workqueue, &priv->restart);
424}
425
dbb983b7
RR		 426/*
427 * ucode
428 */
9f1f3cea
JB		 429static int iwl5000_load_section(struct iwl_priv *priv, const char *name,
430 struct fw_desc *image, u32 dst_addr)
dbb983b7 431{
dbb983b7
RR		 432 dma_addr_t phy_addr = image->p_addr;
433 u32 byte_cnt = image->len;
9f1f3cea
JB		 434 int ret;
435
436 priv->ucode_write_complete = 0;
dbb983b7 437
dbb983b7
RR		 438 iwl_write_direct32(priv,
439 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
440 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
441
442 iwl_write_direct32(priv,
443 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
444
445 iwl_write_direct32(priv,
446 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
447 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
448
dbb983b7 449 iwl_write_direct32(priv,
f0b9f5cb 450 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
499b1883 451 (iwl_get_dma_hi_addr(phy_addr)
f0b9f5cb
TW		 452 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
453
dbb983b7
RR		 454 iwl_write_direct32(priv,
455 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
456 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
457 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
458 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
459
460 iwl_write_direct32(priv,
461 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
462 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
9c80c502 463 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
dbb983b7
RR		 464 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
465
9f1f3cea 466 IWL_DEBUG_INFO(priv, "%s uCode section being loaded...\n", name);
dbb983b7 467 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
9c80c502 468 priv->ucode_write_complete, 5 * HZ);
dbb983b7 469 if (ret == -ERESTARTSYS) {
9f1f3cea
JB		 470 IWL_ERR(priv, "Could not load the %s uCode section due "
471 "to interrupt\n", name);
dbb983b7
RR		 472 return ret;
473 }
474 if (!ret) {
9f1f3cea
JB		 475 IWL_ERR(priv, "Could not load the %s uCode section\n",
476 name);
dbb983b7
RR		 477 return -ETIMEDOUT;
478 }
479
9f1f3cea
JB		 480 return 0;
481}
dbb983b7 482
9f1f3cea
JB		 483static int iwl5000_load_given_ucode(struct iwl_priv *priv,
484 struct fw_desc *inst_image,
485 struct fw_desc *data_image)
486{
487 int ret = 0;
dbb983b7 488
9f1f3cea
JB		 489 ret = iwl5000_load_section(priv, "INST", inst_image,
490 IWL50_RTC_INST_LOWER_BOUND);
491 if (ret)
dbb983b7 492 return ret;
dbb983b7 493
9f1f3cea
JB		 494 return iwl5000_load_section(priv, "DATA", data_image,
495 IWL50_RTC_DATA_LOWER_BOUND);
dbb983b7
RR		 496}
497
672639de 498int iwl5000_load_ucode(struct iwl_priv *priv)
dbb983b7
RR		 499{
500 int ret = 0;
501
502 /* check whether init ucode should be loaded, or rather runtime ucode */
503 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
e1623446 504 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
dbb983b7
RR		 505 ret = iwl5000_load_given_ucode(priv,
506 &priv->ucode_init, &priv->ucode_init_data);
507 if (!ret) {
e1623446 508 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
dbb983b7
RR		 509 priv->ucode_type = UCODE_INIT;
510 }
511 } else {
e1623446 512 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
dbb983b7
RR		 513 "Loading runtime ucode...\n");
514 ret = iwl5000_load_given_ucode(priv,
515 &priv->ucode_code, &priv->ucode_data);
516 if (!ret) {
e1623446 517 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
dbb983b7
RR		 518 priv->ucode_type = UCODE_RT;
519 }
520 }
521
522 return ret;
523}
524
672639de 525void iwl5000_init_alive_start(struct iwl_priv *priv)
99da1b48
RR		 526{
527 int ret = 0;
528
529 /* Check alive response for "valid" sign from uCode */
530 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
531 /* We had an error bringing up the hardware, so take it
532 * all the way back down so we can try again */
e1623446 533 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
99da1b48
RR		 534 goto restart;
535 }
536
537 /* initialize uCode was loaded... verify inst image.
538 * This is a paranoid check, because we would not have gotten the
539 * "initialize" alive if code weren't properly loaded. */
540 if (iwl_verify_ucode(priv)) {
541 /* Runtime instruction load was bad;
542 * take it all the way back down so we can try again */
e1623446 543 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
99da1b48
RR		 544 goto restart;
545 }
546
99da1b48
RR		 547 ret = priv->cfg->ops->lib->alive_notify(priv);
548 if (ret) {
39aadf8c
WT		 549 IWL_WARN(priv,
550 "Could not complete ALIVE transition: %d\n", ret);
99da1b48
RR		 551 goto restart;
552 }
553
7c616cba 554 iwl5000_send_calib_cfg(priv);
99da1b48
RR		 555 return;
556
557restart:
558 /* real restart (first load init_ucode) */
559 queue_work(priv->workqueue, &priv->restart);
560}
561
562static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
563 int txq_id, u32 index)
564{
565 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
566 (index & 0xff) | (txq_id << 8));
567 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
568}
569
570static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
571 struct iwl_tx_queue *txq,
572 int tx_fifo_id, int scd_retry)
573{
574 int txq_id = txq->q.id;
3fd07a1e 575 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
99da1b48
RR		 576
577 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
578 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
579 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
580 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
581 IWL50_SCD_QUEUE_STTS_REG_MSK);
582
583 txq->sched_retry = scd_retry;
584
949cd92c 585 IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
99da1b48 586 active ? "Activate" : "Deactivate",
949cd92c 587 scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
99da1b48
RR		 588}
589
672639de 590int iwl5000_alive_notify(struct iwl_priv *priv)
99da1b48
RR		 591{
592 u32 a;
99da1b48 593 unsigned long flags;
31a73fe4 594 int i, chan;
40fc95d5 595 u32 reg_val;
99da1b48
RR		 596
597 spin_lock_irqsave(&priv->lock, flags);
598
99da1b48
RR		 599 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
600 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
601 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
602 a += 4)
603 iwl_write_targ_mem(priv, a, 0);
604 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
605 a += 4)
606 iwl_write_targ_mem(priv, a, 0);
39d5e0ce
HW		 607 for (; a < priv->scd_base_addr +
608 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
99da1b48
RR		 609 iwl_write_targ_mem(priv, a, 0);
610
611 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
4ddbb7d0 612 priv->scd_bc_tbls.dma >> 10);
31a73fe4
WT		 613
614 /* Enable DMA channel */
615 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
616 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
617 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
618 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
619
40fc95d5
WT		 620 /* Update FH chicken bits */
621 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
622 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
623 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
624
99da1b48 625 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
4ddbb7d0 626 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
99da1b48
RR		 627 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
628
629 /* initiate the queues */
630 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
631 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
632 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
633 iwl_write_targ_mem(priv, priv->scd_base_addr +
634 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
635 iwl_write_targ_mem(priv, priv->scd_base_addr +
636 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
637 sizeof(u32),
638 ((SCD_WIN_SIZE <<
639 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
640 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
641 ((SCD_FRAME_LIMIT <<
642 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
643 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
644 }
645
646 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
da1bc453 647 IWL_MASK(0, priv->hw_params.max_txq_num));
99da1b48 648
da1bc453
TW		 649 /* Activate all Tx DMA/FIFO channels */
650 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
99da1b48
RR		 651
652 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
9c80c502 653
a9e10fb9
WYG		 654 /* make sure all queue are not stopped */
655 memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
656 for (i = 0; i < 4; i++)
657 atomic_set(&priv->queue_stop_count[i], 0);
658
dff010ac
WYG		 659 /* reset to 0 to enable all the queue first */
660 priv->txq_ctx_active_msk = 0;
99da1b48 661 /* map qos queues to fifos one-to-one */
edc1a3a0
JB		 662 BUILD_BUG_ON(ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo) != 10);
663
99da1b48
RR		 664 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
665 int ac = iwl5000_default_queue_to_tx_fifo[i];
edc1a3a0 666
99da1b48 667 iwl_txq_ctx_activate(priv, i);
edc1a3a0
JB		 668
669 if (ac == IWL_TX_FIFO_UNUSED)
670 continue;
671
99da1b48
RR		 672 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
673 }
a221e6f7 674
99da1b48
RR		 675 spin_unlock_irqrestore(&priv->lock, flags);
676
1933ac4d 677 iwl_send_wimax_coex(priv);
9636e583 678
be5d56ed
TW		 679 iwl5000_set_Xtal_calib(priv);
680 iwl_send_calib_results(priv);
7c616cba 681
99da1b48
RR		 682 return 0;
683}
684
672639de 685int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
fdd3e8a4 686{
88804e2b
WYG		 687 if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
688 priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES)
689 priv->cfg->num_of_queues =
690 priv->cfg->mod_params->num_of_queues;
25ae3986 691
88804e2b 692 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
f3f911d1 693 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
4ddbb7d0 694 priv->hw_params.scd_bc_tbls_size =
88804e2b
WYG		 695 priv->cfg->num_of_queues *
696 sizeof(struct iwl5000_scd_bc_tbl);
a8e74e27 697 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
fdd3e8a4
TW		 698 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
699 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
c0bac76a 700
f3a2a424
WYG		 701 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
702 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
c0bac76a 703
da154e30 704 priv->hw_params.max_bsm_size = 0;
7aafef1c 705 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
fdd3e8a4 706 BIT(IEEE80211_BAND_5GHZ);
141c43a3
WT		 707 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
708
c0bac76a
JS		 709 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
710 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
711 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
712 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
c031bf80 713
62161aef
WYG		 714 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
715 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
c031bf80 716
9d67187d 717 /* Set initial sensitivity parameters */
be5d56ed
TW		 718 /* Set initial calibration set */
719 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
c0bac76a 720 case CSR_HW_REV_TYPE_5150:
9d67187d 721 priv->hw_params.sens = &iwl5150_sensitivity;
be5d56ed 722 priv->hw_params.calib_init_cfg =
c0bac76a 723 BIT(IWL_CALIB_DC) |
f69f42a6 724 BIT(IWL_CALIB_LO) |
201706ac 725 BIT(IWL_CALIB_TX_IQ) |
201706ac 726 BIT(IWL_CALIB_BASE_BAND);
c0bac76a 727
be5d56ed 728 break;
c0bac76a 729 default:
9d67187d 730 priv->hw_params.sens = &iwl5000_sensitivity;
819500c5 731 priv->hw_params.calib_init_cfg =
c0bac76a 732 BIT(IWL_CALIB_XTAL) |
7470d7f5
WT		 733 BIT(IWL_CALIB_LO) |
734 BIT(IWL_CALIB_TX_IQ) |
c0bac76a 735 BIT(IWL_CALIB_TX_IQ_PERD) |
7470d7f5 736 BIT(IWL_CALIB_BASE_BAND);
be5d56ed
TW		 737 break;
738 }
739
fdd3e8a4
TW		 740 return 0;
741}
d4100dd9 742
7839fc03
EG		 743/**
744 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
745 */
672639de 746void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
16466903 747 struct iwl_tx_queue *txq,
7839fc03
EG		 748 u16 byte_cnt)
749{
4ddbb7d0 750 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab 751 int write_ptr = txq->q.write_ptr;
7839fc03
EG		 752 int txq_id = txq->q.id;
753 u8 sec_ctl = 0;
127901ab
TW		 754 u8 sta_id = 0;
755 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
756 __le16 bc_ent;
7839fc03 757
127901ab 758 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
7839fc03
EG		 759
760 if (txq_id != IWL_CMD_QUEUE_NUM) {
127901ab 761 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
da99c4b6 762 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
7839fc03
EG		 763
764 switch (sec_ctl & TX_CMD_SEC_MSK) {
765 case TX_CMD_SEC_CCM:
766 len += CCMP_MIC_LEN;
767 break;
768 case TX_CMD_SEC_TKIP:
769 len += TKIP_ICV_LEN;
770 break;
771 case TX_CMD_SEC_WEP:
772 len += WEP_IV_LEN + WEP_ICV_LEN;
773 break;
774 }
775 }
776
127901ab 777 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
7839fc03 778
4ddbb7d0 779 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
7839fc03 780
8ce1ef4a 781 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 782 scd_bc_tbl[txq_id].
127901ab 783 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
7839fc03
EG		 784}
785
672639de 786void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
972cf447
TW		 787 struct iwl_tx_queue *txq)
788{
4ddbb7d0 789 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
127901ab
TW		 790 int txq_id = txq->q.id;
791 int read_ptr = txq->q.read_ptr;
792 u8 sta_id = 0;
793 __le16 bc_ent;
794
795 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
972cf447
TW		 796
797 if (txq_id != IWL_CMD_QUEUE_NUM)
127901ab 798 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
972cf447 799
8ce1ef4a 800 bc_ent = cpu_to_le16(1 | (sta_id << 12));
4ddbb7d0 801 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
972cf447 802
8ce1ef4a 803 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
4ddbb7d0 804 scd_bc_tbl[txq_id].
8ce1ef4a 805 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
972cf447
TW		 806}
807
e26e47d9
TW		 808static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
809 u16 txq_id)
810{
811 u32 tbl_dw_addr;
812 u32 tbl_dw;
813 u16 scd_q2ratid;
814
815 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
816
817 tbl_dw_addr = priv->scd_base_addr +
818 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
819
820 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
821
822 if (txq_id & 0x1)
823 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
824 else
825 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
826
827 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
828
829 return 0;
830}
831static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
832{
833 /* Simply stop the queue, but don't change any configuration;
834 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
835 iwl_write_prph(priv,
836 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
837 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
838 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
839}
840
672639de 841int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
e26e47d9
TW		 842 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
843{
844 unsigned long flags;
e26e47d9
TW		 845 u16 ra_tid;
846
9f17b318 847 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
88804e2b
WYG		 848 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
849 <= txq_id)) {
39aadf8c
WT		 850 IWL_WARN(priv,
851 "queue number out of range: %d, must be %d to %d\n",
9f17b318 852 txq_id, IWL50_FIRST_AMPDU_QUEUE,
88804e2b
WYG		 853 IWL50_FIRST_AMPDU_QUEUE +
854 priv->cfg->num_of_ampdu_queues - 1);
9f17b318
TW		 855 return -EINVAL;
856 }
e26e47d9
TW		 857
858 ra_tid = BUILD_RAxTID(sta_id, tid);
859
860 /* Modify device's station table to Tx this TID */
9f58671e 861 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
e26e47d9
TW		 862
863 spin_lock_irqsave(&priv->lock, flags);
e26e47d9
TW		 864
865 /* Stop this Tx queue before configuring it */
866 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
867
868 /* Map receiver-address / traffic-ID to this queue */
869 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
870
871 /* Set this queue as a chain-building queue */
872 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
873
874 /* enable aggregations for the queue */
875 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
876
877 /* Place first TFD at index corresponding to start sequence number.
878 * Assumes that ssn_idx is valid (!= 0xFFF) */
879 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
880 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
881 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
882
883 /* Set up Tx window size and frame limit for this queue */
884 iwl_write_targ_mem(priv, priv->scd_base_addr +
885 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
886 sizeof(u32),
887 ((SCD_WIN_SIZE <<
888 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
889 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
890 ((SCD_FRAME_LIMIT <<
891 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
892 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
893
894 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
895
896 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
897 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
898
e26e47d9
TW		 899 spin_unlock_irqrestore(&priv->lock, flags);
900
901 return 0;
902}
903
672639de 904int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
e26e47d9
TW		 905 u16 ssn_idx, u8 tx_fifo)
906{
9f17b318 907 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
88804e2b
WYG		 908 (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
909 <= txq_id)) {
a2f1cbeb 910 IWL_ERR(priv,
39aadf8c 911 "queue number out of range: %d, must be %d to %d\n",
9f17b318 912 txq_id, IWL50_FIRST_AMPDU_QUEUE,
88804e2b
WYG		 913 IWL50_FIRST_AMPDU_QUEUE +
914 priv->cfg->num_of_ampdu_queues - 1);
e26e47d9
TW		 915 return -EINVAL;
916 }
917
e26e47d9
TW		 918 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
919
920 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
921
922 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
923 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
924 /* supposes that ssn_idx is valid (!= 0xFFF) */
925 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
926
927 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
928 iwl_txq_ctx_deactivate(priv, txq_id);
929 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
930
e26e47d9
TW		 931 return 0;
932}
933
e8c00dcb 934u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2469bf2e
TW		 935{
936 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
c587de0b
TW		 937 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
938 memcpy(addsta, cmd, size);
939 /* resrved in 5000 */
940 addsta->rate_n_flags = cpu_to_le16(0);
2469bf2e
TW		 941 return size;
942}
943
944
da1bc453 945/*
a96a27f9 946 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
da1bc453
TW		 947 * must be called under priv->lock and mac access
948 */
672639de 949void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
5a676bbe 950{
da1bc453 951 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
5a676bbe
RR		 952}
953
e532fa0e
RR		 954
955static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
956{
3ac7f146 957 return le32_to_cpup((__le32 *)&tx_resp->status +
25a6572c 958 tx_resp->frame_count) & MAX_SN;
e532fa0e
RR		 959}
960
961static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
962 struct iwl_ht_agg *agg,
963 struct iwl5000_tx_resp *tx_resp,
25a6572c 964 int txq_id, u16 start_idx)
e532fa0e
RR		 965{
966 u16 status;
967 struct agg_tx_status *frame_status = &tx_resp->status;
968 struct ieee80211_tx_info *info = NULL;
969 struct ieee80211_hdr *hdr = NULL;
e7d326ac 970 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
25a6572c 971 int i, sh, idx;
e532fa0e
RR		 972 u16 seq;
973
974 if (agg->wait_for_ba)
e1623446 975 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
e532fa0e
RR		 976
977 agg->frame_count = tx_resp->frame_count;
978 agg->start_idx = start_idx;
e7d326ac 979 agg->rate_n_flags = rate_n_flags;
e532fa0e
RR		 980 agg->bitmap = 0;
981
982 /* # frames attempted by Tx command */
983 if (agg->frame_count == 1) {
984 /* Only one frame was attempted; no block-ack will arrive */
985 status = le16_to_cpu(frame_status[0].status);
25a6572c 986 idx = start_idx;
e532fa0e
RR		 987
988 /* FIXME: code repetition */
e1623446 989 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
e532fa0e
RR		 990 agg->frame_count, agg->start_idx, idx);
991
992 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
e6a9854b 993 info->status.rates[0].count = tx_resp->failure_frame + 1;
e532fa0e 994 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
c397bf15 995 info->flags |= iwl_tx_status_to_mac80211(status);
e7d326ac
TW		 996 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
997
e532fa0e
RR		 998 /* FIXME: code repetition end */
999
e1623446 1000 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
e532fa0e 1001 status & 0xff, tx_resp->failure_frame);
e1623446 1002 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
e532fa0e
RR		 1003
1004 agg->wait_for_ba = 0;
1005 } else {
1006 /* Two or more frames were attempted; expect block-ack */
1007 u64 bitmap = 0;
1008 int start = agg->start_idx;
1009
1010 /* Construct bit-map of pending frames within Tx window */
1011 for (i = 0; i < agg->frame_count; i++) {
1012 u16 sc;
1013 status = le16_to_cpu(frame_status[i].status);
1014 seq = le16_to_cpu(frame_status[i].sequence);
1015 idx = SEQ_TO_INDEX(seq);
1016 txq_id = SEQ_TO_QUEUE(seq);
1017
1018 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1019 AGG_TX_STATE_ABORT_MSK))
1020 continue;
1021
e1623446 1022 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
e532fa0e
RR		 1023 agg->frame_count, txq_id, idx);
1024
1025 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
6c6a22e2
SG		 1026 if (!hdr) {
1027 IWL_ERR(priv,
1028 "BUG_ON idx doesn't point to valid skb"
1029 " idx=%d, txq_id=%d\n", idx, txq_id);
1030 return -1;
1031 }
e532fa0e
RR		 1032
1033 sc = le16_to_cpu(hdr->seq_ctrl);
1034 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
15b1687c
WT		 1035 IWL_ERR(priv,
1036 "BUG_ON idx doesn't match seq control"
1037 " idx=%d, seq_idx=%d, seq=%d\n",
e532fa0e
RR		 1038 idx, SEQ_TO_SN(sc),
1039 hdr->seq_ctrl);
1040 return -1;
1041 }
1042
e1623446 1043 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
e532fa0e
RR		 1044 i, idx, SEQ_TO_SN(sc));
1045
1046 sh = idx - start;
1047 if (sh > 64) {
1048 sh = (start - idx) + 0xff;
1049 bitmap = bitmap << sh;
1050 sh = 0;
1051 start = idx;
1052 } else if (sh < -64)
1053 sh = 0xff - (start - idx);
1054 else if (sh < 0) {
1055 sh = start - idx;
1056 start = idx;
1057 bitmap = bitmap << sh;
1058 sh = 0;
1059 }
4aa41f12 1060 bitmap |= 1ULL << sh;
e1623446 1061 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
4aa41f12 1062 start, (unsigned long long)bitmap);
e532fa0e
RR		 1063 }
1064
1065 agg->bitmap = bitmap;
1066 agg->start_idx = start;
e1623446 1067 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
e532fa0e
RR		 1068 agg->frame_count, agg->start_idx,
1069 (unsigned long long)agg->bitmap);
1070
1071 if (bitmap)
1072 agg->wait_for_ba = 1;
1073 }
1074 return 0;
1075}
1076
1077static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1078 struct iwl_rx_mem_buffer *rxb)
1079{
2f301227 1080 struct iwl_rx_packet *pkt = rxb_addr(rxb);
e532fa0e
RR		 1081 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1082 int txq_id = SEQ_TO_QUEUE(sequence);
1083 int index = SEQ_TO_INDEX(sequence);
1084 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1085 struct ieee80211_tx_info *info;
1086 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1087 u32 status = le16_to_cpu(tx_resp->status.status);
3fd07a1e
TW		 1088 int tid;
1089 int sta_id;
1090 int freed;
e532fa0e
RR		 1091
1092 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 1093 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
e532fa0e
RR		 1094 "is out of range [0-%d] %d %d\n", txq_id,
1095 index, txq->q.n_bd, txq->q.write_ptr,
1096 txq->q.read_ptr);
1097 return;
1098 }
1099
1100 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1101 memset(&info->status, 0, sizeof(info->status));
1102
3fd07a1e
TW		 1103 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1104 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
e532fa0e
RR		 1105
1106 if (txq->sched_retry) {
1107 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1108 struct iwl_ht_agg *agg = NULL;
1109
e532fa0e
RR		 1110 agg = &priv->stations[sta_id].tid[tid].agg;
1111
25a6572c 1112 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
e532fa0e 1113
3235427e
RR		 1114 /* check if BAR is needed */
1115 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1116 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
e532fa0e
RR		 1117
1118 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
e532fa0e 1119 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
e1623446 1120 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
3fd07a1e
TW		 1121 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1122 scd_ssn , index, txq_id, txq->swq_id);
1123
17b88929 1124 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
a239a8b4 1125 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
e532fa0e 1126
3fd07a1e
TW		 1127 if (priv->mac80211_registered &&
1128 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1129 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
e532fa0e 1130 if (agg->state == IWL_AGG_OFF)
e4e72fb4 1131 iwl_wake_queue(priv, txq_id);
e532fa0e 1132 else
e4e72fb4 1133 iwl_wake_queue(priv, txq->swq_id);
e532fa0e 1134 }
e532fa0e
RR		 1135 }
1136 } else {
3fd07a1e
TW		 1137 BUG_ON(txq_id != txq->swq_id);
1138
e6a9854b 1139 info->status.rates[0].count = tx_resp->failure_frame + 1;
c397bf15 1140 info->flags |= iwl_tx_status_to_mac80211(status);
e7d326ac 1141 iwl_hwrate_to_tx_control(priv,
4f85f5b3
RR		 1142 le32_to_cpu(tx_resp->rate_n_flags),
1143 info);
1144
e1623446 1145 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
3fd07a1e
TW		 1146 "0x%x retries %d\n",
1147 txq_id,
1148 iwl_get_tx_fail_reason(status), status,
1149 le32_to_cpu(tx_resp->rate_n_flags),
1150 tx_resp->failure_frame);
4f85f5b3 1151
3fd07a1e 1152 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
a120e912 1153 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
3fd07a1e
TW		 1154
1155 if (priv->mac80211_registered &&
1156 (iwl_queue_space(&txq->q) > txq->q.low_mark))
e4e72fb4 1157 iwl_wake_queue(priv, txq_id);
e532fa0e 1158 }
e532fa0e 1159
a120e912 1160 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
3fd07a1e 1161
e532fa0e 1162 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 1163 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
e532fa0e
RR		 1164}
1165
a96a27f9 1166/* Currently 5000 is the superset of everything */
e8c00dcb 1167u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
c1adf9fb
GG		 1168{
1169 return len;
1170}
1171
672639de 1172void iwl5000_setup_deferred_work(struct iwl_priv *priv)
203566f3
EG		 1173{
1174 /* in 5000 the tx power calibration is done in uCode */
1175 priv->disable_tx_power_cal = 1;
1176}
1177
672639de 1178void iwl5000_rx_handler_setup(struct iwl_priv *priv)
b600e4e1 1179{
7c616cba
TW		 1180 /* init calibration handlers */
1181 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1182 iwl5000_rx_calib_result;
1183 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1184 iwl5000_rx_calib_complete;
e532fa0e 1185 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
b600e4e1
RR		 1186}
1187
7c616cba 1188
672639de 1189int iwl5000_hw_valid_rtc_data_addr(u32 addr)
87283cc1 1190{
250bdd21 1191 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
87283cc1
RR		 1192 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1193}
1194
fe7a90c2
RR		 1195static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1196{
1197 int ret = 0;
1198 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1199 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1200 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1201
1202 if ((rxon1->flags == rxon2->flags) &&
1203 (rxon1->filter_flags == rxon2->filter_flags) &&
1204 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1205 (rxon1->ofdm_ht_single_stream_basic_rates ==
1206 rxon2->ofdm_ht_single_stream_basic_rates) &&
1207 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1208 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1209 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1210 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1211 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1212 (rxon1->rx_chain == rxon2->rx_chain) &&
1213 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
e1623446 1214 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
fe7a90c2
RR		 1215 return 0;
1216 }
1217
1218 rxon_assoc.flags = priv->staging_rxon.flags;
1219 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1220 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1221 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1222 rxon_assoc.reserved1 = 0;
1223 rxon_assoc.reserved2 = 0;
1224 rxon_assoc.reserved3 = 0;
1225 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1226 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1227 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1228 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1229 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1230 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1231 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1232 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1233
1234 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1235 sizeof(rxon_assoc), &rxon_assoc, NULL);
1236 if (ret)
1237 return ret;
1238
1239 return ret;
1240}
672639de 1241int iwl5000_send_tx_power(struct iwl_priv *priv)
630fe9b6
TW		 1242{
1243 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
76a2407a 1244 u8 tx_ant_cfg_cmd;
630fe9b6
TW		 1245
1246 /* half dBm need to multiply */
1247 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
ae16fc3c
WYG		 1248
1249 if (priv->tx_power_lmt_in_half_dbm &&
1250 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
1251 /*
1252 * For the newer devices which using enhanced/extend tx power
1253 * table in EEPROM, the format is in half dBm. driver need to
1254 * convert to dBm format before report to mac80211.
1255 * By doing so, there is a possibility of 1/2 dBm resolution
1256 * lost. driver will perform "round-up" operation before
1257 * reporting, but it will cause 1/2 dBm tx power over the
1258 * regulatory limit. Perform the checking here, if the
1259 * "tx_power_user_lmt" is higher than EEPROM value (in
1260 * half-dBm format), lower the tx power based on EEPROM
1261 */
1262 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
1263 }
853554ac 1264 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
630fe9b6 1265 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
76a2407a
JS		 1266
1267 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1268 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1269 else
1270 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1271
1272 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
630fe9b6
TW		 1273 sizeof(tx_power_cmd), &tx_power_cmd,
1274 NULL);
1275}
1276
672639de 1277void iwl5000_temperature(struct iwl_priv *priv)
8f91aecb
EG		 1278{
1279 /* store temperature from statistics (in Celsius) */
5225640b 1280 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
39b73fb1 1281 iwl_tt_handler(priv);
8f91aecb 1282}
fe7a90c2 1283
62161aef
WYG		 1284static void iwl5150_temperature(struct iwl_priv *priv)
1285{
1286 u32 vt = 0;
1287 s32 offset = iwl_temp_calib_to_offset(priv);
1288
1289 vt = le32_to_cpu(priv->statistics.general.temperature);
1290 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1291 /* now vt hold the temperature in Kelvin */
1292 priv->temperature = KELVIN_TO_CELSIUS(vt);
15993e08 1293 iwl_tt_handler(priv);
62161aef
WYG		 1294}
1295
caab8f1a 1296/* Calc max signal level (dBm) among 3 possible receivers */
e8c00dcb 1297int iwl5000_calc_rssi(struct iwl_priv *priv,
caab8f1a
TW		 1298 struct iwl_rx_phy_res *rx_resp)
1299{
1300 /* data from PHY/DSP regarding signal strength, etc.,
1301 * contents are always there, not configurable by host
1302 */
1303 struct iwl5000_non_cfg_phy *ncphy =
1304 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1305 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1306 u8 agc;
1307
1308 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1309 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1310
1311 /* Find max rssi among 3 possible receivers.
1312 * These values are measured by the digital signal processor (DSP).
1313 * They should stay fairly constant even as the signal strength varies,
1314 * if the radio's automatic gain control (AGC) is working right.
1315 * AGC value (see below) will provide the "interesting" info.
1316 */
1317 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1318 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1319 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1320 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1321 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1322
1323 max_rssi = max_t(u32, rssi_a, rssi_b);
1324 max_rssi = max_t(u32, max_rssi, rssi_c);
1325
e1623446 1326 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
caab8f1a
TW		 1327 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1328
1329 /* dBm = max_rssi dB - agc dB - constant.
1330 * Higher AGC (higher radio gain) means lower signal. */
250bdd21 1331 return max_rssi - agc - IWL49_RSSI_OFFSET;
caab8f1a
TW		 1332}
1333
2f748dec
WYG		 1334static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1335{
1336 struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1337 .valid = cpu_to_le32(valid_tx_ant),
1338 };
1339
1340 if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1341 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1342 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1343 sizeof(struct iwl_tx_ant_config_cmd),
1344 &tx_ant_cmd);
1345 } else {
1346 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1347 return -EOPNOTSUPP;
1348 }
1349}
1350
1351
cc0f555d
JS		 1352#define IWL5000_UCODE_GET(item) \
1353static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1354 u32 api_ver) \
1355{ \
1356 if (api_ver <= 2) \
1357 return le32_to_cpu(ucode->u.v1.item); \
1358 return le32_to_cpu(ucode->u.v2.item); \
1359}
1360
1361static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1362{
1363 if (api_ver <= 2)
1364 return UCODE_HEADER_SIZE(1);
1365 return UCODE_HEADER_SIZE(2);
1366}
1367
1368static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1369 u32 api_ver)
1370{
1371 if (api_ver <= 2)
1372 return 0;
1373 return le32_to_cpu(ucode->u.v2.build);
1374}
1375
1376static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1377 u32 api_ver)
1378{
1379 if (api_ver <= 2)
1380 return (u8 *) ucode->u.v1.data;
1381 return (u8 *) ucode->u.v2.data;
1382}
1383
1384IWL5000_UCODE_GET(inst_size);
1385IWL5000_UCODE_GET(data_size);
1386IWL5000_UCODE_GET(init_size);
1387IWL5000_UCODE_GET(init_data_size);
1388IWL5000_UCODE_GET(boot_size);
1389
4a56e965
WYG		 1390static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1391{
1392 struct iwl5000_channel_switch_cmd cmd;
1393 const struct iwl_channel_info *ch_info;
1394 struct iwl_host_cmd hcmd = {
1395 .id = REPLY_CHANNEL_SWITCH,
1396 .len = sizeof(cmd),
1397 .flags = CMD_SIZE_HUGE,
1398 .data = &cmd,
1399 };
1400
1401 IWL_DEBUG_11H(priv, "channel switch from %d to %d\n",
1402 priv->active_rxon.channel, channel);
1403 cmd.band = priv->band == IEEE80211_BAND_2GHZ;
1404 cmd.channel = cpu_to_le16(channel);
0924e519
WYG		 1405 cmd.rxon_flags = priv->staging_rxon.flags;
1406 cmd.rxon_filter_flags = priv->staging_rxon.filter_flags;
4a56e965
WYG		 1407 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1408 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1409 if (ch_info)
1410 cmd.expect_beacon = is_channel_radar(ch_info);
1411 else {
1412 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
1413 priv->active_rxon.channel, channel);
1414 return -EFAULT;
1415 }
0924e519
WYG		 1416 priv->switch_rxon.channel = cpu_to_le16(channel);
1417 priv->switch_rxon.switch_in_progress = true;
4a56e965
WYG		 1418
1419 return iwl_send_cmd_sync(priv, &hcmd);
1420}
1421
e8c00dcb 1422struct iwl_hcmd_ops iwl5000_hcmd = {
fe7a90c2 1423 .rxon_assoc = iwl5000_send_rxon_assoc,
e0158e61 1424 .commit_rxon = iwl_commit_rxon,
45823531 1425 .set_rxon_chain = iwl_set_rxon_chain,
2f748dec 1426 .set_tx_ant = iwl5000_send_tx_ant_config,
da8dec29
TW		 1427};
1428
e8c00dcb 1429struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
c1adf9fb 1430 .get_hcmd_size = iwl5000_get_hcmd_size,
2469bf2e 1431 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
33fd5033
EG		 1432 .gain_computation = iwl5000_gain_computation,
1433 .chain_noise_reset = iwl5000_chain_noise_reset,
a326a5d0 1434 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
caab8f1a 1435 .calc_rssi = iwl5000_calc_rssi,
da8dec29
TW		 1436};
1437
cc0f555d
JS		 1438struct iwl_ucode_ops iwl5000_ucode = {
1439 .get_header_size = iwl5000_ucode_get_header_size,
1440 .get_build = iwl5000_ucode_get_build,
1441 .get_inst_size = iwl5000_ucode_get_inst_size,
1442 .get_data_size = iwl5000_ucode_get_data_size,
1443 .get_init_size = iwl5000_ucode_get_init_size,
1444 .get_init_data_size = iwl5000_ucode_get_init_data_size,
1445 .get_boot_size = iwl5000_ucode_get_boot_size,
1446 .get_data = iwl5000_ucode_get_data,
1447};
1448
e8c00dcb 1449struct iwl_lib_ops iwl5000_lib = {
fdd3e8a4 1450 .set_hw_params = iwl5000_hw_set_hw_params,
7839fc03 1451 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
972cf447 1452 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
da1bc453 1453 .txq_set_sched = iwl5000_txq_set_sched,
e26e47d9
TW		 1454 .txq_agg_enable = iwl5000_txq_agg_enable,
1455 .txq_agg_disable = iwl5000_txq_agg_disable,
7aaa1d79
SO		 1456 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1457 .txq_free_tfd = iwl_hw_txq_free_tfd,
a8e74e27 1458 .txq_init = iwl_hw_tx_queue_init,
b600e4e1 1459 .rx_handler_setup = iwl5000_rx_handler_setup,
203566f3 1460 .setup_deferred_work = iwl5000_setup_deferred_work,
87283cc1 1461 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
b7a79404
RC		 1462 .dump_nic_event_log = iwl_dump_nic_event_log,
1463 .dump_nic_error_log = iwl_dump_nic_error_log,
696bdee3 1464 .dump_csr = iwl_dump_csr,
1b3eb823 1465 .dump_fh = iwl_dump_fh,
dbb983b7 1466 .load_ucode = iwl5000_load_ucode,
99da1b48
RR		 1467 .init_alive_start = iwl5000_init_alive_start,
1468 .alive_notify = iwl5000_alive_notify,
630fe9b6 1469 .send_tx_power = iwl5000_send_tx_power,
5b9f8cd3 1470 .update_chain_flags = iwl_update_chain_flags,
4a56e965 1471 .set_channel_switch = iwl5000_hw_channel_switch,
30d59260 1472 .apm_ops = {
fadb3582 1473 .init = iwl_apm_init,
d68b603c 1474 .stop = iwl_apm_stop,
5a835353 1475 .config = iwl5000_nic_config,
5b9f8cd3 1476 .set_pwr_src = iwl_set_pwr_src,
30d59260 1477 },
da8dec29 1478 .eeprom_ops = {
25ae3986
TW		 1479 .regulatory_bands = {
1480 EEPROM_5000_REG_BAND_1_CHANNELS,
1481 EEPROM_5000_REG_BAND_2_CHANNELS,
1482 EEPROM_5000_REG_BAND_3_CHANNELS,
1483 EEPROM_5000_REG_BAND_4_CHANNELS,
1484 EEPROM_5000_REG_BAND_5_CHANNELS,
7aafef1c
WYG		 1485 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1486 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
25ae3986 1487 },
da8dec29
TW		 1488 .verify_signature = iwlcore_eeprom_verify_signature,
1489 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1490 .release_semaphore = iwlcore_eeprom_release_semaphore,
0ef2ca67 1491 .calib_version = iwl5000_eeprom_calib_version,
25ae3986 1492 .query_addr = iwl5000_eeprom_query_addr,
da8dec29 1493 },
5bbe233b 1494 .post_associate = iwl_post_associate,
ef850d7c 1495 .isr = iwl_isr_ict,
60690a6a 1496 .config_ap = iwl_config_ap,
62161aef
WYG		 1497 .temp_ops = {
1498 .temperature = iwl5000_temperature,
1499 .set_ct_kill = iwl5000_set_ct_threshold,
1500 },
3459ab5a 1501 .add_bcast_station = iwl_add_bcast_station,
b74e31a9 1502 .recover_from_tx_stall = iwl_bg_monitor_recover,
beac5498 1503 .recover_from_statistics = iwl_recover_from_statistics,
62161aef
WYG		 1504};
1505
1506static struct iwl_lib_ops iwl5150_lib = {
1507 .set_hw_params = iwl5000_hw_set_hw_params,
1508 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1509 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1510 .txq_set_sched = iwl5000_txq_set_sched,
1511 .txq_agg_enable = iwl5000_txq_agg_enable,
1512 .txq_agg_disable = iwl5000_txq_agg_disable,
1513 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1514 .txq_free_tfd = iwl_hw_txq_free_tfd,
1515 .txq_init = iwl_hw_tx_queue_init,
1516 .rx_handler_setup = iwl5000_rx_handler_setup,
1517 .setup_deferred_work = iwl5000_setup_deferred_work,
1518 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
b7a79404
RC		 1519 .dump_nic_event_log = iwl_dump_nic_event_log,
1520 .dump_nic_error_log = iwl_dump_nic_error_log,
696bdee3 1521 .dump_csr = iwl_dump_csr,
62161aef
WYG		 1522 .load_ucode = iwl5000_load_ucode,
1523 .init_alive_start = iwl5000_init_alive_start,
1524 .alive_notify = iwl5000_alive_notify,
1525 .send_tx_power = iwl5000_send_tx_power,
1526 .update_chain_flags = iwl_update_chain_flags,
4a56e965 1527 .set_channel_switch = iwl5000_hw_channel_switch,
62161aef 1528 .apm_ops = {
fadb3582 1529 .init = iwl_apm_init,
d68b603c 1530 .stop = iwl_apm_stop,
62161aef
WYG		 1531 .config = iwl5000_nic_config,
1532 .set_pwr_src = iwl_set_pwr_src,
1533 },
1534 .eeprom_ops = {
1535 .regulatory_bands = {
1536 EEPROM_5000_REG_BAND_1_CHANNELS,
1537 EEPROM_5000_REG_BAND_2_CHANNELS,
1538 EEPROM_5000_REG_BAND_3_CHANNELS,
1539 EEPROM_5000_REG_BAND_4_CHANNELS,
1540 EEPROM_5000_REG_BAND_5_CHANNELS,
7aafef1c
WYG		 1541 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1542 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
62161aef
WYG		 1543 },
1544 .verify_signature = iwlcore_eeprom_verify_signature,
1545 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1546 .release_semaphore = iwlcore_eeprom_release_semaphore,
1547 .calib_version = iwl5000_eeprom_calib_version,
1548 .query_addr = iwl5000_eeprom_query_addr,
1549 },
1550 .post_associate = iwl_post_associate,
ef850d7c 1551 .isr = iwl_isr_ict,
62161aef
WYG		 1552 .config_ap = iwl_config_ap,
1553 .temp_ops = {
1554 .temperature = iwl5150_temperature,
1555 .set_ct_kill = iwl5150_set_ct_threshold,
1556 },
3459ab5a 1557 .add_bcast_station = iwl_add_bcast_station,
b74e31a9 1558 .recover_from_tx_stall = iwl_bg_monitor_recover,
beac5498 1559 .recover_from_statistics = iwl_recover_from_statistics,
da8dec29
TW		 1560};
1561
45d5d805 1562static const struct iwl_ops iwl5000_ops = {
cc0f555d 1563 .ucode = &iwl5000_ucode,
da8dec29
TW		 1564 .lib = &iwl5000_lib,
1565 .hcmd = &iwl5000_hcmd,
1566 .utils = &iwl5000_hcmd_utils,
e932a609 1567 .led = &iwlagn_led_ops,
da8dec29
TW		 1568};
1569
45d5d805 1570static const struct iwl_ops iwl5150_ops = {
cc0f555d 1571 .ucode = &iwl5000_ucode,
62161aef
WYG		 1572 .lib = &iwl5150_lib,
1573 .hcmd = &iwl5000_hcmd,
1574 .utils = &iwl5000_hcmd_utils,
e932a609 1575 .led = &iwlagn_led_ops,
62161aef
WYG		 1576};
1577
cec2d3f3 1578struct iwl_mod_params iwl50_mod_params = {
5a6a256e 1579 .amsdu_size_8K = 1,
3a1081e8 1580 .restart_fw = 1,
5a6a256e
TW		 1581 /* the rest are 0 by default */
1582};
1583
1584
1585struct iwl_cfg iwl5300_agn_cfg = {
c11362c0 1586 .name = "Intel(R) Ultimate N WiFi Link 5300 AGN",
a0987a8d
RC		 1587 .fw_name_pre = IWL5000_FW_PRE,
1588 .ucode_api_max = IWL5000_UCODE_API_MAX,
1589 .ucode_api_min = IWL5000_UCODE_API_MIN,
5a6a256e 1590 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1591 .ops = &iwl5000_ops,
25ae3986 1592 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1593 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1594 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
88804e2b
WYG		 1595 .num_of_queues = IWL50_NUM_QUEUES,
1596 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e 1597 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1598 .valid_tx_ant = ANT_ABC,
1599 .valid_rx_ant = ANT_ABC,
fadb3582
BC		 1600 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1601 .set_l0s = true,
1602 .use_bsm = false,
b261793d 1603 .ht_greenfield_support = true,
f2d0d0e2 1604 .led_compensation = 51,
1152dcc2 1605 .use_rts_for_ht = true, /* use rts/cts protection */
d8c07e7a 1606 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
3e4fb5fa 1607 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
d4fe5ac9 1608 .chain_noise_scale = 1000,
b74e31a9 1609 .monitor_recover_period = IWL_MONITORING_PERIOD,
5a6a256e
TW		 1610};
1611
ac592574 1612struct iwl_cfg iwl5100_bgn_cfg = {
c11362c0 1613 .name = "Intel(R) WiFi Link 5100 BGN",
a0987a8d
RC		 1614 .fw_name_pre = IWL5000_FW_PRE,
1615 .ucode_api_max = IWL5000_UCODE_API_MAX,
1616 .ucode_api_min = IWL5000_UCODE_API_MIN,
ac592574 1617 .sku = IWL_SKU_G|IWL_SKU_N,
47408639
EK		 1618 .ops = &iwl5000_ops,
1619 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1620 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1621 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
88804e2b
WYG		 1622 .num_of_queues = IWL50_NUM_QUEUES,
1623 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
47408639 1624 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1625 .valid_tx_ant = ANT_B,
1626 .valid_rx_ant = ANT_AB,
fadb3582
BC		 1627 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1628 .set_l0s = true,
1629 .use_bsm = false,
b261793d 1630 .ht_greenfield_support = true,
f2d0d0e2 1631 .led_compensation = 51,
1152dcc2 1632 .use_rts_for_ht = true, /* use rts/cts protection */
d8c07e7a 1633 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
3e4fb5fa 1634 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
d4fe5ac9 1635 .chain_noise_scale = 1000,
b74e31a9 1636 .monitor_recover_period = IWL_MONITORING_PERIOD,
47408639
EK		 1637};
1638
1639struct iwl_cfg iwl5100_abg_cfg = {
c11362c0 1640 .name = "Intel(R) WiFi Link 5100 ABG",
a0987a8d
RC		 1641 .fw_name_pre = IWL5000_FW_PRE,
1642 .ucode_api_max = IWL5000_UCODE_API_MAX,
1643 .ucode_api_min = IWL5000_UCODE_API_MIN,
47408639
EK		 1644 .sku = IWL_SKU_A|IWL_SKU_G,
1645 .ops = &iwl5000_ops,
1646 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1647 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1648 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
88804e2b
WYG		 1649 .num_of_queues = IWL50_NUM_QUEUES,
1650 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
47408639 1651 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1652 .valid_tx_ant = ANT_B,
1653 .valid_rx_ant = ANT_AB,
fadb3582
BC		 1654 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1655 .set_l0s = true,
1656 .use_bsm = false,
f2d0d0e2 1657 .led_compensation = 51,
d8c07e7a 1658 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
3e4fb5fa 1659 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
d4fe5ac9 1660 .chain_noise_scale = 1000,
b74e31a9 1661 .monitor_recover_period = IWL_MONITORING_PERIOD,
47408639
EK		 1662};
1663
5a6a256e 1664struct iwl_cfg iwl5100_agn_cfg = {
c11362c0 1665 .name = "Intel(R) WiFi Link 5100 AGN",
a0987a8d
RC		 1666 .fw_name_pre = IWL5000_FW_PRE,
1667 .ucode_api_max = IWL5000_UCODE_API_MAX,
1668 .ucode_api_min = IWL5000_UCODE_API_MIN,
5a6a256e 1669 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1670 .ops = &iwl5000_ops,
25ae3986 1671 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1672 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1673 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
88804e2b
WYG		 1674 .num_of_queues = IWL50_NUM_QUEUES,
1675 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e 1676 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1677 .valid_tx_ant = ANT_B,
1678 .valid_rx_ant = ANT_AB,
fadb3582
BC		 1679 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1680 .set_l0s = true,
1681 .use_bsm = false,
b261793d 1682 .ht_greenfield_support = true,
f2d0d0e2 1683 .led_compensation = 51,
1152dcc2 1684 .use_rts_for_ht = true, /* use rts/cts protection */
d8c07e7a 1685 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
3e4fb5fa 1686 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
d4fe5ac9 1687 .chain_noise_scale = 1000,
b74e31a9 1688 .monitor_recover_period = IWL_MONITORING_PERIOD,
5a6a256e
TW		 1689};
1690
1691struct iwl_cfg iwl5350_agn_cfg = {
c11362c0 1692 .name = "Intel(R) WiMAX/WiFi Link 5350 AGN",
a0987a8d
RC		 1693 .fw_name_pre = IWL5000_FW_PRE,
1694 .ucode_api_max = IWL5000_UCODE_API_MAX,
1695 .ucode_api_min = IWL5000_UCODE_API_MIN,
5a6a256e 1696 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
da8dec29 1697 .ops = &iwl5000_ops,
25ae3986 1698 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
0ef2ca67
TW		 1699 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1700 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
88804e2b
WYG		 1701 .num_of_queues = IWL50_NUM_QUEUES,
1702 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
5a6a256e 1703 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1704 .valid_tx_ant = ANT_ABC,
1705 .valid_rx_ant = ANT_ABC,
fadb3582
BC		 1706 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1707 .set_l0s = true,
1708 .use_bsm = false,
b261793d 1709 .ht_greenfield_support = true,
f2d0d0e2 1710 .led_compensation = 51,
1152dcc2 1711 .use_rts_for_ht = true, /* use rts/cts protection */
d8c07e7a 1712 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
3e4fb5fa 1713 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
d4fe5ac9 1714 .chain_noise_scale = 1000,
b74e31a9 1715 .monitor_recover_period = IWL_MONITORING_PERIOD,
5a6a256e
TW		 1716};
1717
7100e924 1718struct iwl_cfg iwl5150_agn_cfg = {
c11362c0 1719 .name = "Intel(R) WiMAX/WiFi Link 5150 AGN",
a0987a8d
RC		 1720 .fw_name_pre = IWL5150_FW_PRE,
1721 .ucode_api_max = IWL5150_UCODE_API_MAX,
1722 .ucode_api_min = IWL5150_UCODE_API_MIN,
7100e924 1723 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
62161aef 1724 .ops = &iwl5150_ops,
7100e924 1725 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
fd63edba
TW		 1726 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1727 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
88804e2b
WYG		 1728 .num_of_queues = IWL50_NUM_QUEUES,
1729 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
7100e924 1730 .mod_params = &iwl50_mod_params,
c0bac76a
JS		 1731 .valid_tx_ant = ANT_A,
1732 .valid_rx_ant = ANT_AB,
fadb3582
BC		 1733 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1734 .set_l0s = true,
1735 .use_bsm = false,
b261793d 1736 .ht_greenfield_support = true,
f2d0d0e2 1737 .led_compensation = 51,
1152dcc2 1738 .use_rts_for_ht = true, /* use rts/cts protection */
d8c07e7a 1739 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
3e4fb5fa 1740 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
d4fe5ac9 1741 .chain_noise_scale = 1000,
b74e31a9 1742 .monitor_recover_period = IWL_MONITORING_PERIOD,
7100e924
TW		 1743};
1744
ac592574 1745struct iwl_cfg iwl5150_abg_cfg = {
c11362c0 1746 .name = "Intel(R) WiMAX/WiFi Link 5150 ABG",
ac592574
WYG		 1747 .fw_name_pre = IWL5150_FW_PRE,
1748 .ucode_api_max = IWL5150_UCODE_API_MAX,
1749 .ucode_api_min = IWL5150_UCODE_API_MIN,
1750 .sku = IWL_SKU_A|IWL_SKU_G,
1751 .ops = &iwl5150_ops,
1752 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1753 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1754 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1755 .num_of_queues = IWL50_NUM_QUEUES,
1756 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1757 .mod_params = &iwl50_mod_params,
1758 .valid_tx_ant = ANT_A,
1759 .valid_rx_ant = ANT_AB,
1760 .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1761 .set_l0s = true,
1762 .use_bsm = false,
1763 .led_compensation = 51,
1764 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
3e4fb5fa 1765 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
d4fe5ac9 1766 .chain_noise_scale = 1000,
b74e31a9 1767 .monitor_recover_period = IWL_MONITORING_PERIOD,
7100e924
TW		 1768};
1769
a0987a8d
RC		 1770MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1771MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
c9f79ed2 1772
4e30cb69 1773module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
5a6a256e
TW		 1774MODULE_PARM_DESC(swcrypto50,
1775 "using software crypto engine (default 0 [hardware])\n");
4e30cb69 1776module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
5a6a256e 1777MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
4e30cb69 1778module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
49779293 1779MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
4e30cb69
WYG		 1780module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1781 int, S_IRUGO);
5a6a256e 1782MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
4e30cb69 1783module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
3a1081e8 1784MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");
Linux kernel - Deliverables
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